Back-contact solar cell, battery module and photovoltaic system

Abstract

The present disclosure is applicable to the technical field of solar cells. Provided are a back-contact solar cell, a battery module and a photovoltaic system. The back-contact solar cell comprises: a silicon substrate, which has a back face and a front face that are arranged opposite each other; a P-type doped polysilicon layer located in a first region on the back face of the silicon substrate; an N-type doped polysilicon layer located in a second region on the back face of the silicon substrate, wherein the first region is different from the second region; a P-type doped internal diffusion layer formed inside the silicon substrate and arranged close to the P-type doped polysilicon layer; and an N-type doped internal diffusion layer formed inside the silicon substrate and arranged close to the N-type doped polysilicon layer, wherein the depth of the P-type doped internal diffusion layer is greater than the depth of the N-type doped internal diffusion layer. In the back-contact solar cell provided in the present disclosure, setting the depth of the P-type doped internal diffusion layer to be greater than the depth of the N-type doped internal diffusion layer and increasing the depth of the P-type doped internal diffusion layer can improve the emitter busbar efficiency of the back-contact solar cell, thereby improving the cell efficiency.

Description

Back contact solar cell, cell assembly and photovoltaic system

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202410822620.7, filed on June 24, 2024, and entitled "A back contact solar cell, cell assembly and photovoltaic system", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of solar cells, in particular to a back contact solar cell, cell assembly and photovoltaic system. BACKGROUND

[0004] Solar power generation is a sustainable clean energy source, which can convert sunlight into electrical energy by using the photovoltaic effect of semiconductor p-n junction, and the conversion efficiency is an important indicator of solar cell performance. IBC (Interdigitated back contact) solar cell, also known as interdigital back contact cell, has both positive and negative electrodes designed on the back surface of the cell, so that the front surface is completely free from the obstruction of metal grid lines, eliminating the optical loss caused by the obstruction of metal grid lines, and the electrode width can be designed wider than the existing one, reducing the series resistance loss, thereby greatly improving the conversion efficiency of the cell. In addition, due to the design of no electrode on the front surface of the cell, the product appearance is more beautiful, which is suitable for various application scenarios.

[0005] In the prior art, the back surface of the back contact solar cell forms staggered P and N regions. Generally, when the P-type doped polysilicon layer of the P region and the N-type doped polysilicon layer of the N region are prepared, the P-type doped polysilicon layer will form a P-type doped inner expansion layer inside the silicon wafer, and the N-type doped polysilicon layer will form an N-type doped inner expansion layer inside the silicon wafer. In order to facilitate processing, the depth of the P-type doped inner expansion layer and the N-type doped inner expansion layer is usually approximately equal, which will make the emitter current collection efficiency low, thereby affecting the cell efficiency. SUMMARY

[0006] The present disclosure provides a back contact solar cell, which aims to solve the problem that the P-type doped inner expansion layer and the N-type doped inner expansion layer have equal depth in the prior art back contact solar cell, the emitter current collection efficiency is low, and thereby the cell efficiency is affected.

[0007] The present disclosure is implemented in this way, providing a back contact solar cell, comprising:

[0008] a silicon substrate having a back surface and a front surface arranged oppositely;

[0009] A P-doped polysilicon layer is located in a first region on the back side of the silicon substrate;

[0010] An N-doped polysilicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region;

[0011] A P-doped inner extension layer is formed inside the silicon substrate and is arranged close to the P-doped polysilicon layer;

[0012] An N-doped inner extension layer is formed inside the silicon substrate and is arranged close to the N-doped polysilicon layer;

[0013] The depth of the P-doped inner extension layer is greater than the depth of the N-doped inner extension layer.

[0014] In some embodiments, the ratio of the depth of the P-doped inner extension layer to the depth of the N-doped inner extension layer is 1-4, and is not equal to 1.

[0015] In some embodiments, the ratio of the depth of the P-doped inner extension layer to the depth of the N-doped inner extension layer is 1-2, and is not equal to 1.

[0016] In some embodiments, the depth of the P-doped inner extension layer is 30-800 nm; and the depth of the N-doped inner extension layer is 10-600 nm.

[0017] In some embodiments, the width of the P-doped inner extension layer is greater than the width of the N-doped inner extension layer.

[0018] In some embodiments, the ratio of the width of the P-doped inner extension layer to the width of the N-doped inner extension layer is 1-2, and is not equal to 1.

[0019] In some embodiments, the volume of the P-doped inner extension layer is greater than the volume of the N-doped inner extension layer.

[0020] In some embodiments, the ratio of the volume of the P-doped inner extension layer to the volume of the N-doped inner extension layer is 1-2, and is not equal to 1.

[0021] In some embodiments, the thickness of the N-doped polysilicon layer is greater than the thickness of the P-doped polysilicon layer.

[0022] In some embodiments, the ratio of the thickness of the N-doped polysilicon layer to the thickness of the P-doped polysilicon layer is 1-2, and is not equal to 1.

[0023] In some embodiments, the ratio of the thickness of the N-doped polysilicon layer to the thickness of the P-doped polysilicon layer is 1-1.5, and is not equal to 1.

[0024] In some embodiments, further comprising:

[0025] a first passivation layer disposed between the P-type doped inner extension layer and the P-type doped polysilicon layer, the first passivation layer containing P-type dopants;

[0026] a second passivation layer disposed between the N-type doped inner extension layer and the N-type doped polysilicon layer, the second passivation layer containing N-type dopants;

[0027] wherein a doping concentration of the P-type dopants of the first passivation layer is less than a doping concentration of the N-type dopants of the second passivation layer.

[0028] In some embodiments, a doping concentration of the P-type dopants of the P-type doped inner extension layer is less than a doping concentration of the N-type dopants of the N-type doped inner extension layer.

[0029] The present disclosure also provides a battery assembly comprising the back contact solar cell described above.

[0030] The present disclosure also provides a photovoltaic system comprising the battery assembly described above.

[0031] The present disclosure provides a back contact solar cell by setting a depth of a P-type doped inner extension layer to be greater than a depth of an N-type doped inner extension layer, without affecting a depth requirement of the N-type doped inner extension layer, by increasing the depth of the P-type doped inner extension layer, which can improve an emitter current collection efficiency of the back contact solar cell, thereby improving a cell efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0032] FIG. 1 is a schematic diagram of a back contact solar cell according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, further detailed description will be made to the present disclosure in combination with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure, and are not used to limit the present disclosure.

[0034] The present disclosure provides a back contact solar cell by setting a depth of a P-type doped inner extension layer to be greater than a depth of an N-type doped inner extension layer, without affecting a depth requirement of the N-type doped inner extension layer, by increasing the depth of the P-type doped inner extension layer, which can improve an emitter current collection efficiency of the back contact solar cell, thereby improving a cell efficiency.

[0035] Referring to FIG. 1, the present disclosure provides a back contact solar cell, comprising:

[0036] a silicon substrate 1 having a back surface and a front surface arranged opposite to each other;

[0037] a P-doped polysilicon layer 2 located in a first region of the back surface of the silicon substrate 1;

[0038] an N-doped polysilicon layer 4 located in a second region of the back surface of the silicon substrate 1, and different from the first region;

[0039] a P-doped inner extension layer 3 formed inside the silicon substrate 1 and arranged close to the P-doped polysilicon layer 2;

[0040] an N-doped inner extension layer 5 formed inside the silicon substrate 1 and arranged close to the N-doped polysilicon layer 4;

[0041] wherein the depth d3 of the P-doped inner extension layer 3 is greater than the depth d4 of the N-doped inner extension layer 5.

[0042] As shown in FIG. 1, the back surface of the silicon substrate 1 is the lower side, and the front surface is the upper side. The dashed line L1 and the dashed line L2 are only used to distinguish the first region and the second region, and are not actually present in the back contact solar cell. Referring to FIG. 1, the region on the left side of the dashed line L1 is the first region, and the region on the right side of the dashed line L2 is the second region. The first region and the second region are different regions. The P-doped polysilicon layer 2 is located in the first region of the back surface of the silicon substrate 1, and the N-doped polysilicon layer 4 is located in the second region of the back surface of the silicon substrate 1. The P-doped polysilicon layer 2 is located in the region on the left side of the dashed line L1 of the back surface of the silicon substrate 1, and the N-doped polysilicon layer 4 is located in the region on the right side of the dashed line L2 of the first side of the silicon substrate 1.

[0043] In the embodiments of the present disclosure, the silicon substrate 1 can be an N-type silicon substrate or a P-type silicon substrate.

[0044] In the embodiments of the present disclosure, the depth d3 of the P-doped inner extension layer 3 is the distance from the back surface of the silicon substrate 1 to the bottom surface of the P-doped inner extension layer 3, and the depth d4 of the N-doped inner extension layer 5 is the distance from the back surface of the silicon substrate 1 to the bottom surface of the N-doped inner extension layer 5. By setting the depth d3 of the P-doped inner extension layer 3 to be greater than the depth d4 of the N-doped inner extension layer 5, the depth of the N-doped inner extension layer 5 is not changed, and by increasing the depth of the P-doped inner extension layer 3, the emitter current collection efficiency of the back contact solar cell can be improved, thereby improving the cell efficiency.

[0045] In actual application, the depth d3 of the P-type doped inner extension layer 3 can be greater than the depth d4 of the N-type doped inner extension layer 5 by adjusting the heat treatment temperature and time during preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4, so as to effectively improve the cell efficiency. For example, the depth d3 of the P-type doped inner extension layer 3 can be greater than the depth d4 of the N-type doped inner extension layer 5 by controlling the heat treatment temperature of the P-type doped polysilicon layer 2 to be greater than the heat treatment temperature of the N-type doped polysilicon layer 4 or by controlling the heat treatment time of the P-type doped polysilicon layer 2 to be greater than the heat treatment time of the N-type doped polysilicon layer 4; or the depth d3 of the P-type doped inner extension layer 3 can be greater than the depth d4 of the N-type doped inner extension layer 5 by controlling the heat treatment temperature of the P-type doped polysilicon layer 2 to be greater than the heat treatment temperature of the N-type doped polysilicon layer 4 and by controlling the heat treatment time of the P-type doped polysilicon layer 2 to be greater than the heat treatment time of the N-type doped polysilicon layer 4.

[0046] As an embodiment of the present disclosure, the ratio of the depth d3 of the P-type doped inner extension layer 3 to the depth d4 of the N-type doped inner extension layer 5 is 1-4 and not equal to 1.

[0047] In the embodiment, the ratio of the depth d3 of the P-type doped inner extension layer 3 to the depth d4 of the N-type doped inner extension layer 5 is greater than 1 and less than or equal to 4, which can improve the emitter current collection efficiency of the back contact solar cell, improve the cell efficiency, and facilitate the control of the depth difference between the P-type doped inner extension layer 3 and the N-type doped inner extension layer 5 and the processing of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4.

[0048] For example, the ratio of the depth d3 of the P-type doped inner extension layer 3 to the depth d4 of the N-type doped inner extension layer 5 can be:

[0049] 1.01, or 1.08, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.0; or 2.2, or 2.3, or 2.5, or 2.6, or 2.9, or 3.0, or 3.5, or 3.7, or 3.8, or 3.9, or 4.0.

[0050] As an embodiment of the present disclosure, the ratio of the depth d3 of the P-type doped inner extension layer 3 to the depth d4 of the N-type doped inner extension layer 5 is 1-2.

[0051] In the embodiment, the ratio of the depth d3 of the P-type doped inner diffusion layer 3 to the depth d4 of the N-type doped inner diffusion layer 5 is greater than 1 and less than or equal to 2, which can ensure that the depth d3 of the P-type doped inner diffusion layer 3 and the depth d4 of the N-type doped inner diffusion layer 5 are in a more appropriate range, which can improve the emitter current collection efficiency of the back contact solar cell, improve the cell efficiency, and facilitate the processing of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4.

[0052] As an embodiment of the present disclosure, the depth d3 of the P-type doped inner diffusion layer 3 is 30-800 nm; and the depth d4 of the N-type doped inner diffusion layer 5 is 10-600 nm.

[0053] For example, the depth d3 of the P-type doped inner diffusion layer 3 can be 30 nm, or 50 nm, or 80 nm, or 100 nm, or 150 nm, or 180 nm, or 220 nm, or 250 nm, or 280 nm, or 300 nm, or 350 nm, or 400 nm, or 450 nm, or 500 nm, or 560 nm, or 600 nm, or 650 nm, or 680 nm, or 700 nm, or 720 nm, or 780 nm, or 800 nm.

[0054] For example, the depth d4 of the N-type doped inner diffusion layer 5 can be 10 nm, or 50 nm, or 100 nm, or 150 nm, or 200 nm, or 250 nm, or 300 nm, or 240 nm, or 350 nm, or 400 nm, or 450 nm, or 500 nm, or 550 nm, or 600 nm.

[0055] As an embodiment of the present disclosure, the width of the P-type doped inner diffusion layer 3 is greater than the width of the N-type doped inner diffusion layer 5.

[0056] In the embodiment, the width of the P-type doped inner diffusion layer 3 is greater than the width of the N-type doped inner diffusion layer 5, which can make the area of the P-type doped inner diffusion layer 3 greater than the area of the N-type doped inner diffusion layer 5, increase the area of the P-type doped inner diffusion layer 3, and further improve the emitter current collection efficiency of the back contact solar cell, thereby improving the cell efficiency. Specifically, the width of the P-type doped polysilicon layer 2 can be increased, thereby increasing the width of the P-type doped inner diffusion layer 3 formed by the diffusion of the P-type doped polysilicon layer 2 into the silicon substrate 1, i.e., the width of the P-type doped polysilicon layer 2 is greater than the width of the N-type doped polysilicon layer 4.

[0057] As one embodiment of the present disclosure, the ratio of the width of the P-type doped inner diffusion layer 3 to the width of the N-type doped inner diffusion layer 5 is 1-2 and not equal to 1, which can ensure that the width of the P-type doped inner diffusion layer 3 and the width of the N-type doped inner diffusion layer 5 are kept within a suitable range, maintain a high battery efficiency, and facilitate the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4. The width of the P-type doped inner diffusion layer 3 corresponds to the width of the P-type doped polysilicon layer 2, and the width of the N-type doped inner diffusion layer 5 corresponds to the width of the N-type doped polysilicon layer 4. By adjusting the width of the P-type doped polysilicon layer 2, the width of the P-type doped inner diffusion layer 3 can be changed accordingly. By adjusting the width of the N-type doped polysilicon layer 4, the width of the N-type doped inner diffusion layer 5 can be changed accordingly. The width of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4 can be flexibly set according to actual conditions.

[0058] As one embodiment of the present disclosure, the volume of the P-type doped inner diffusion layer 3 is greater than the volume of the N-type doped inner diffusion layer 5.

[0059] In this embodiment, the volume of the P-type doped inner diffusion layer 3 is greater than the volume of the N-type doped inner diffusion layer 5, which can increase the volume of the P-type doped inner diffusion layer 3 and further improve the emitter current collection efficiency of the back contact solar cell, thereby improving the battery efficiency. Specifically, the width or depth of the P-type doped polysilicon layer 2 can be increased to increase the volume of the P-type doped inner diffusion layer 3 formed by the diffusion of the P-type doped polysilicon layer 2 into the silicon substrate 1, i.e., the volume of the P-type doped polysilicon layer 2 is greater than the volume of the N-type doped polysilicon layer 4.

[0060] As one embodiment of the present disclosure, the ratio of the volume of the P-type doped inner diffusion layer 3 to the volume of the N-type doped inner diffusion layer 5 is 1-2 and not equal to 1.

[0061] In the embodiment, the ratio of the volume of the P-type doped inner extension layer 3 to the volume of the N-type doped inner extension layer 5 is greater than 1 and less than or equal to 2, which can ensure that the volume of the P-type doped inner extension layer 3 and the volume of the N-type doped inner extension layer 5 are kept within a suitable range, keep a high battery efficiency, and facilitate the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4. The width of the P-type doped inner extension layer 3 corresponds to the width of the P-type doped polysilicon layer 2, the width of the N-type doped inner extension layer 5 corresponds to the width of the N-type doped polysilicon layer 4, the depth d3 of the P-type doped inner extension layer 3 corresponds to the preparation heat treatment temperature and heat treatment time of the P-type doped polysilicon layer 2, and the depth d4 of the N-type doped inner extension layer 5 corresponds to the preparation heat treatment temperature and heat treatment time of the N-type doped polysilicon layer 4. Therefore, on the premise that the depth d3 of the P-type doped inner extension layer 3 is greater than the depth d4 of the N-type doped inner extension layer 5, setting the width of the P-type doped polysilicon layer 2 to be greater than or equal to the width of the N-type doped polysilicon layer 4 can make the volume of the P-type doped inner extension layer 3 greater than the volume of the N-type doped inner extension layer 5.

[0062] As one embodiment of the present disclosure, further comprising:

[0063] The first passivation layer 8 is arranged between the P-type doped inner extension layer 3 and the P-type doped polysilicon layer 2, and the first passivation layer 8 contains P-type dopants.

[0064] The second passivation layer 10 is arranged between the N-type doped inner extension layer 5 and the N-type doped polysilicon layer 4, and the second passivation layer 10 contains N-type dopants.

[0065] The doping concentration of the P-type dopants of the first passivation layer 8 is less than the doping concentration of the N-type dopants of the second passivation layer 10.

[0066] In the embodiment, the passivation layer 8 is specifically a silicon dioxide passivation layer. By arranging the first passivation layer 8 and the second passivation layer 10, and the doping concentration of the P-type dopants of the first passivation layer 8 being less than the doping concentration of the N-type dopants of the second passivation layer 10, the gettering effect of the N region is improved, thereby improving the battery efficiency.

[0067] As one embodiment of the present disclosure, the doping concentration of the P-type dopants of the P-type doped inner extension layer 3 is less than the doping concentration of the N-type dopants of the N-type doped inner extension layer 5, which can further improve the gettering effect of the N region.

[0068] As one embodiment of the present disclosure, the thickness of the N-type doped polysilicon layer 4 is greater than the thickness of the P-type doped polysilicon layer 2.

[0069] In the embodiment, the thickness d1 of the N-type doped polysilicon layer 4 is unchanged, and the thickness d2 of the P-type doped polysilicon layer 2 is reduced without affecting the effect of the N-type doped polysilicon layer 4, so as to reduce the etching difficulty of the P-type doped polysilicon, reduce the difficulty of the patterning process, and facilitate the patterning process of the P-type doped polysilicon. Moreover, reducing the thickness d2 of the P-type doped polysilicon layer 2 can reduce the boron diffusion difficulty, which is conducive to the boron diffusion process and facilitates the preparation of the P-type doped polysilicon layer 2 with a higher concentration. Furthermore, the thickness d1 of the N-type doped polysilicon layer 4 is greater than the thickness d2 of the P-type doped polysilicon layer 2, and the N-type doped polysilicon layer 4 is thicker than the P-type doped polysilicon layer 2, which can enhance the passivation effect and improve the cell efficiency. Moreover, since the back contact solar cell is prepared by first preparing the P-type doped polysilicon layer 2 on the whole surface and then preparing the N-type doped polysilicon layer 4, the P-type doped polysilicon in the N region needs to be etched and removed when the N-type doped polysilicon layer 4 is prepared. Therefore, by reducing the thickness of the P-type doped polysilicon layer 2, the etching difficulty of the P-type doped polysilicon is reduced, and the P-type doped polysilicon in the N region can be removed completely, which facilitates the preparation of the N-type doped polysilicon layer 4.

[0070] As an embodiment of the present disclosure, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 is 1-2, and is not equal to 1.

[0071] In the embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 2, which can reduce the etching difficulty of the P-type doped polysilicon layer 2, facilitate the patterning process of the P-type doped polysilicon layer 2, and be conducive to the boron diffusion process, reduce the boron diffusion difficulty, and facilitate the preparation of the P-type doped polysilicon layer 2 with a higher concentration. Moreover, and more importantly, it can prevent the metallization damage of the P-type doped polysilicon layer 2 from being too large or the contact resistance from being too large, and reduce the loss of cell efficiency.

[0072] For example, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 can be:

[0073] 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.

[0074] Optionally, in the case that the ratio of d1 and d2 is 1 to 2, the thickness d1 of the N-type doped polysilicon layer 4 is 100nm to 600nm, and the thickness d2 of the P-type doped polysilicon layer 2 can be 50nm to 300nm. When d1 and d2 are in the above range, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 4 are easy to achieve good doping effect, both have good passivation effect, while ensuring that the metallization damage is small and the contact resistance is small, and the cost is relatively low; in addition, the etching difficulty of the P-type doped polysilicon can be reduced, the patterning process of the P-type doped polysilicon is facilitated, and the boron diffusion process is facilitated, the boron diffusion difficulty is reduced, and the preparation of high-concentration P-type doped polysilicon layer 2 is facilitated.

[0075] For example, the thickness d1 of the N-type doped polysilicon layer 4 can be 100nm, or 105nm, or 135nm, or 145nm, or 173nm, or 185nm, or 200nm, or 240nm, or 285nm, or 300nm, or 301nm, or 342nm, or 367nm, or 370nm, or 420nm, or 456nm, or 482nm, or 500nm, or 550nm, or 570nm, or 590nm, or 600nm.

[0076] For example, the thickness d2 of the P-type doped polysilicon layer 2 can be 50nm, or 45nm, or 52nm, or 60nm, or 66.7nm, or 73nm, or 81nm, or 90nm, or 92nm, or 100nm, or 112nm, or 133nm, or 144nm, or 175nm, or 190nm, or 211nm, or 243nm, or 270nm, or 282nm, or 296nm, or 300nm.

[0077] As an embodiment of the present disclosure, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 is 1 to 1.5, and not equal to 1.

[0078] In this embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 4 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 1.5, which can reduce the processing cost of the N-type doped polysilicon layer 4 and the P-type doped polysilicon layer 2, facilitate the patterning process of the P-type doped polysilicon, and facilitate the boron diffusion process and the preparation of high-concentration P-type doped polysilicon layer 2; and can prevent the metallization damage of the P-type doped polysilicon layer 2 from being too large or the contact resistance from being too large, and reduce the loss of battery efficiency.

[0079] As an embodiment of the present disclosure, it further comprises:

[0080] a first metal electrode 6 located on the first region of the back surface of the silicon substrate 1 and in contact with the P-doped polysilicon layer 2;

[0081] a second metal electrode 7 located on the second region of the back surface of the silicon substrate 1 and in contact with the N-doped polysilicon layer 4.

[0082] In the embodiment, the depth of the metal crystal of the metal electrode into the P-doped polysilicon layer 2 and the N-doped polysilicon layer 4 can be controlled by controlling the temperature and time in the metallization process. In some embodiments, the depth of the metal crystal of the first metal electrode 6 into the P-doped polysilicon layer 2 is greater than the depth of the metal crystal of the second metal electrode 7 into the N-doped polysilicon layer 4, which can improve the contact effect of the first metal electrode 6 with the P-doped polysilicon layer 2, thereby improving the conversion efficiency of the cell.

[0083] As an embodiment of the present disclosure, the back contact solar cell further comprises a back passivation film layer 9 located on the surface of the P-doped polysilicon layer 2 and the N-doped polysilicon layer 4, to further improve the conversion efficiency of the back contact solar cell.

[0084] As an embodiment of the present disclosure, the silicon substrate 1 is further provided with a groove 12 between the P-doped polysilicon layer 2 and the N-doped polysilicon layer 4. The P-doped polysilicon layer 2 and the N-doped polysilicon layer 4 are physically isolated by the groove 12, which can further improve the isolation effect of the P-doped polysilicon layer 2 and the N-doped polysilicon layer 4, and further reduce the risk of short circuit or electric leakage. The width of the groove can be flexibly set according to actual needs, which is not limited herein.

[0085] As an embodiment of the present disclosure, the front surface of the silicon substrate 1 has a textured structure (not shown in the figure), which can achieve good light trapping effect and improve the conversion efficiency of the back contact solar cell. In addition, the front surface of the back contact solar cell can be provided with a front passivation anti-reflection film layer 11 to further improve the conversion efficiency of the back contact solar cell.

[0086] The present disclosure further provides a cell assembly comprising the back contact solar cell of the above-mentioned embodiments. It should be noted that the cell assembly and the back contact solar cell have the same or similar beneficial effects, and the related parts between the two can be mutually referred to, and to avoid repetition, the details are not described herein.

[0087] The present disclosure further provides a photovoltaic system comprising the cell assembly of the above-mentioned embodiments. It should be noted that the cell assembly and the back contact solar cell have the same or similar beneficial effects, and the related parts between the two can be mutually referred to, and to avoid repetition, the details are not described herein.

[0088] The embodiment of the present disclosure provides a back contact solar cell, by setting the depth of the P-type doped inner extension layer to be greater than the depth of the N-type doped inner extension layer, under the premise that the depth of the N-type doped inner extension layer is unchanged, by increasing the depth of the P-type doped inner extension layer, the emitter current collection efficiency of the back contact solar cell can be improved, so that the cell efficiency is improved.

[0089] The above only describes the preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A back-contact solar cell, comprising: A silicon substrate having a back side and a front side disposed opposite to each other; A P-type doped polycrystalline silicon layer is located in the first region on the back side of the silicon substrate; An N-type doped polycrystalline silicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region; A P-type doped inner extension layer is formed inside the silicon substrate and disposed close to the P-type doped polysilicon layer. An N-type doped inner extension layer is formed inside the silicon substrate and disposed close to the N-type doped polysilicon layer; The depth of the P-type doped inner extension layer is greater than the depth of the N-type doped inner extension layer.

2. The back-contact solar cell according to claim 1, wherein, The ratio of the depth of the P-type doped inner extension layer to the depth of the N-type doped inner extension layer is 1 to 4, and is not equal to 1.

3. The back-contact solar cell according to claim 1, wherein, The ratio of the depth of the P-type doped inner extension layer to the depth of the N-type doped inner extension layer is 1 to 2, and is not equal to 1.

4. The back-contact solar cell according to claim 1, wherein, The depth of the P-type doped inner extension layer is 30–800 nm; the depth of the N-type doped inner extension layer is 10–600 nm.

5. The back-contact solar cell according to claim 1, wherein, The width of the P-type doped inner extension layer is greater than the width of the N-type doped inner extension layer.

6. The back-contact solar cell according to claim 5, wherein, The ratio of the width of the P-type doped inner extension layer to the width of the N-type doped inner extension layer is 1 to 2, and is not equal to 1.

7. The back-contact solar cell according to claim 1, wherein, The volume of the P-type doped inner extension layer is greater than the volume of the N-type doped inner extension layer.

8. The back-contact solar cell according to claim 7, wherein, The ratio of the volume of the P-type doped inner extension layer to the volume of the N-type doped inner extension layer is 1 to 2, but not equal to 1.

9. The back-contact solar cell according to claim 1, wherein, The thickness of the N-type doped polycrystalline silicon layer is greater than the thickness of the P-type doped polycrystalline silicon layer.

10. The back-contact solar cell according to claim 9, wherein, The ratio of the thickness of the N-type doped polycrystalline silicon layer to the thickness of the P-type doped polycrystalline silicon layer is 1 to 2, but not equal to 1.

11. The back-contact solar cell according to claim 9, wherein, The ratio of the thickness of the N-type doped polycrystalline silicon layer to the thickness of the P-type doped polycrystalline silicon layer is 1 to 1.5, and not equal to 1.

12. The back-contact solar cell according to claim 1, wherein, Also includes: A first passivation layer is disposed between the P-type doped inner extension layer and the P-type doped polysilicon layer, the first passivation layer containing a P-type dopant; A second passivation layer is disposed between the N-type doped inner extension layer and the N-type doped polysilicon layer, the second passivation layer containing an N-type dopant; The doping concentration of the P-type dopant in the first passivation layer is less than the doping concentration of the N-type dopant in the second passivation layer.

13. The back-contact solar cell according to claim 1, wherein, The doping concentration of the P-type dopant in the P-type doped inner extension layer is less than the doping concentration of the N-type dopant in the N-type doped inner extension layer.

14. A battery assembly, wherein, Including the back-contact solar cell as described in any one of claims 1 to 13.

15. A photovoltaic system, wherein, Includes the battery assembly as described in claim 14.

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