Display panel, display device, and driving method

Abstract

Embodiments of the present disclosure provide a display panel, a display device, and a driving method. The display panel comprises: a plurality of sub-pixels, each sub-pixel comprising a light-emitting device and a pixel circuit coupled to a first electrode of the light-emitting device; and a plurality of driving control circuits, wherein the pixel circuits in an n-th row of sub-pixels are coupled to the first electrodes of the light-emitting devices in an (n+1)-th row of sub-pixels by means of at least one driving control circuit, and the driving control circuit is configured to, in response to a signal at a first control signal end, transmit first driving currents generated by the pixel circuits in the n-th row of sub-pixels and / or second driving currents generated on the basis of data voltage in the pixel circuits in the n-th row of sub-pixels to the light-emitting devices in the (n+1)-th row of sub-pixels. By coordinating the pixel circuits and the driving control circuits, the problem of luminance inconsistency between two adjacent rows of sub-pixels is mitigated, and the occurrence of black scan lines on the display panel is avoided, thereby improving the display effect and competitiveness of products.

Description

Display panel, display device and driving method

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202410832678.X, filed on June 25, 2024, and entitled "Display panel, display device and driving method", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of display, in particular to a display panel, a display device and a driving method. BACKGROUND

[0004] Organic light emitting diode (OLED), quantum dot light emitting diode (QLED), micro light emitting diode (Micro LED), mini light emitting diode (Mini LED) and other light emitting devices have the advantages of self-luminescence and low energy consumption, and are one of the hotspots in the field of current display device application research. Pixel circuits are generally used in display devices to drive light emitting devices to emit light. SUMMARY

[0005] The display panel provided by the embodiments of the present disclosure comprises: a plurality of sub-pixels, each of the sub-pixels comprising: a light emitting device and a pixel circuit coupled with a first electrode of the light emitting device;

[0006] A plurality of driving control circuits, the pixel circuit in the nth row of sub-pixels is coupled with the first electrode of the light emitting device in the (n+1)th row of sub-pixels through at least one of the driving control circuits, and the driving control circuit is configured to transmit the first driving current generated by the pixel circuit in the nth row of sub-pixels and / or the second driving current generated according to the data voltage in the pixel circuit in the nth row of sub-pixels to the light emitting device in the (n+1)th row of sub-pixels in response to the signal of the first control signal end; wherein n is a positive integer greater than 0.

[0007] In some possible implementations, the driving control circuit comprises: a first switch transistor;

[0008] A gate of the first switch transistor is coupled to the first control signal terminal, a first electrode of the first switch transistor is coupled to the light emitting device in the pixel circuit in the nth row of sub-pixels, and a second electrode of the first switch transistor is coupled to the light emitting device in the pixel circuit in the n+1th row of sub-pixels.

[0009] In some possible implementation manners, the pixel circuit further includes a first drive transistor.

[0010] The drive control circuit includes a second drive transistor and a second switch transistor.

[0011] A gate of the second drive transistor is coupled to a gate of the first drive transistor in the pixel circuit in the nth row of sub-pixels, a first electrode of the second drive transistor is coupled to a first electrode of the first drive transistor in the pixel circuit in the nth row of sub-pixels, and a second electrode of the second drive transistor is coupled to a first electrode of the second switch transistor.

[0012] A gate of the second switch transistor is coupled to the first control signal terminal, and a second electrode of the second switch transistor is coupled to the light emitting device in the n+1th row of sub-pixels.

[0013] In some possible implementation manners, the pixel circuit further includes a first drive transistor.

[0014] The drive control circuit includes a third drive transistor, a third switch transistor, and a fourth switch transistor.

[0015] A gate of the third drive transistor is coupled to a gate of the first drive transistor in the pixel circuit in the nth row of sub-pixels, a first electrode of the third drive transistor is coupled to a first electrode of the first drive transistor in the pixel circuit in the nth row of sub-pixels, and a second electrode of the third drive transistor is coupled to a first electrode of the third switch transistor.

[0016] A gate of the third switch transistor is coupled to the first control signal terminal, and a second electrode of the third switch transistor is coupled to a second electrode of the first drive transistor in the pixel circuit in the nth row of sub-pixels.

[0017] A gate of the fourth switch transistor is coupled to the first control signal terminal, a first electrode of the fourth switch transistor is coupled to the light emitting device in the pixel circuit in the nth row of sub-pixels, and a second electrode of the fourth switch transistor is coupled to the light emitting device in the n+1th row of sub-pixels.

[0018] In some possible implementation manners, one driving control circuit is arranged in one-to-one correspondence with each of the first to (N-1)th rows of sub-pixels, and the nth row of sub-pixels in the same column is coupled to the first electrode of the light-emitting device in the (n+1)th row of sub-pixels through the corresponding driving control circuit.

[0019] In some possible implementation manners, the driving control circuit is located between pixel circuits in adjacent two rows of sub-pixels.

[0020] In some possible implementation manners, the driving control circuit is located between pixel circuits in adjacent two columns of sub-pixels.

[0021] In some possible implementation manners, the driving control circuit is integrated into the pixel circuit of the corresponding sub-pixel.

[0022] In some possible implementation manners, the display panel further includes at least one row of virtual sub-pixels and a plurality of switch control circuits, and the switch control circuits are arranged in one-to-one correspondence with the virtual sub-pixels.

[0023] The virtual sub-pixel includes a virtual pixel circuit, the virtual pixel circuit is coupled to the light-emitting device in the first row of sub-pixels through the corresponding switch control circuit, and the switch control circuit is configured to provide a driving current generated by the virtual pixel circuit to the light-emitting device in the first row of sub-pixels in response to a signal of the first control signal end.

[0024] The display device provided by the embodiment of the present disclosure includes the display panel.

[0025] The driving method of the display panel provided by the embodiment of the present disclosure includes: controlling the pixel circuit in the sub-pixel to drive the light-emitting device to emit light row by row.

[0026] The pixel circuit works in a data writing stage, a reset stage and an emitting stage in sequence.

[0027] When the pixel circuit in the nth row of sub-pixels is in the emitting stage, the pixel circuit in the (n+1)th row of sub-pixels is in the data writing stage, and the driving control circuit connected between the pixel circuit in the nth row of sub-pixels and the first electrode of the light-emitting device in the (n+1)th row of sub-pixels transmits a first driving current generated by the pixel circuit in the nth row of sub-pixels and / or a second driving current generated according to a data voltage in the pixel circuit in the nth row of sub-pixels to the light-emitting device in the (n+1)th row of sub-pixels in response to a signal of the first control signal end.

[0028] In some possible implementation manners, the cut-off time of the effective level of the first control signal end in the driving control circuit corresponding to the nth row of pixel circuits is not earlier than the cut-off time of the data writing stage of the pixel circuit in the (n+1)th row of sub-pixels.

[0029] In some possible implementation manners, the time of loading the effective level of the first control signal end in the driving control circuit corresponding to the nth row of pixel circuits does not overlap with the reset stage of the pixel circuit in the (n+1)th row of sub-pixels. BRIEF DESCRIPTION OF DRAWINGS

[0030] FIG. 1 is a structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0031] FIG. 2 is another structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0032] FIG. 3 is still another structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0033] FIG. 4 is still another structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0034] FIG. 5 is a signal timing diagram provided by some embodiments of the present disclosure;

[0035] FIG. 6 is still another structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0036] FIG. 7 is still another structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0037] FIG. 8 is still another structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0038] FIG. 9 is still another structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0039] FIG. 10 is still another structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0040] FIG. 11 is still another structural schematic diagram of a display panel provided by some embodiments of the present disclosure;

[0041] FIG. 12 is another signal timing diagram provided by some embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present application with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. And the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0043] Unless otherwise defined, technical terms or scientific terms used in the present application shall have the common meaning understood by those skilled in the art to which the present application pertains. The terms "first", "second", and similar terms used in the present application do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0044] It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, but only serve to illustrate the content of the present application. And the same or similar reference numbers represent the same or similar elements or elements with the same or similar functions throughout.

[0045] The display device provided by the embodiments of the present application comprises a display panel, and the display area of the display panel comprises a plurality of pixel units arranged in an array. Each pixel unit comprises a plurality of sub-pixels. For example, the pixel unit can comprise a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing can be performed by red, green, and blue to realize color display. Alternatively, the pixel unit can comprise a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed by red, green, blue, and white to realize color display. Of course, in actual applications, the light-emitting colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0046] In the embodiments of the present disclosure, each sub-pixel includes a pixel circuit, and the pixel circuit includes a driving transistor and a light emitting device to drive the light emitting device to emit light, so that the display panel realizes the function of picture display. Due to process and device aging, etc., the threshold voltage Vth of the driving transistor will be non-uniform, which will cause the current flowing through different light emitting devices to change, resulting in uneven display brightness, thereby affecting the display effect of the entire image. In order to make the brightness of the display panel more uniform and the display more perfect, it is generally necessary to increase the data writing stage, so as to eliminate the influence of the threshold voltage Vth drift or non-uniformity of the driving transistor by internal compensation and other methods.

[0047] In the data writing stage, the pixel circuit in the sub-pixel is written with data row by row, at this time the light emitting device in the sub-pixel does not emit light and presents a dark state; in the light emitting stage, the light emitting device in the sub-pixel emits light and presents a bright state; the data writing stage is shorter than the light emitting stage in time, so the human eye cannot perceive it, that is, the human eye can only observe the uniform display in the light emitting stage. However, the camera can perceive it. For a display panel with a low refresh frequency (for example, less than 1000HZ), the camera shutter can capture the black scan line of the display panel when performing row-by-row data writing.

[0048] At present, the black scan line of the display panel can be eliminated by increasing the refresh frequency of the display panel. However, for a display panel with a low refresh frequency, there will still be a black scan line, so it is necessary to use other ways than increasing the refresh frequency to solve the problem of the black scan line.

[0049] Based on the above problems, the display panel provided by the embodiments of the present disclosure is shown in FIG. 1, which includes:

[0050] a plurality of sub-pixels spx, each sub-pixel spx includes a light emitting device L and a pixel circuit 10 coupled to a first electrode of the light emitting device L;

[0051] a plurality of driving control circuits 20, the pixel circuit 10 in the nth row of sub-pixels is coupled to the first electrode of the light emitting device L in the (n+1)th row of sub-pixels through at least one driving control circuit 20, and the driving control circuit 20 is configured to transmit the first driving current generated by the pixel circuit 10 in the nth row of sub-pixels and / or the second driving current generated according to the data voltage in the pixel circuit 10 in the nth row of sub-pixels to the light emitting device L in the (n+1)th row of sub-pixels in response to the signal of the first control signal end CS1; wherein n is a positive integer greater than 0.

[0052] The embodiment of the present disclosure can improve the problem that the luminous brightness of the nth row of sub-pixels is inconsistent with the luminous brightness of the (n+1)th row of sub-pixels, i.e., the luminous brightness between the two adjacent rows of sub-pixels is inconsistent, and avoid the problem of black scan lines in the display panel, thereby improving the display effect and competitiveness of the display product.

[0053] In the embodiment of the present disclosure, as shown in FIG. 2, the pixel circuit 10 further includes a first driving transistor M0; the driving control circuit 20 is configured to transmit the second driving current generated according to the data voltage in the pixel circuit 10 in the nth row of sub-pixels to the light emitting device L in the (n+1)th row of sub-pixels in response to the signal of the first control signal end CS1; wherein the driving control circuit 20 includes a second driving transistor T02 and a second switch transistor T2; the gate of the second driving transistor T02 is coupled with the gate of the first driving transistor M0 in the pixel circuit 10 in the nth row of sub-pixels, the first pole of the second driving transistor T02 is coupled with the first pole of the first driving transistor M0 in the pixel circuit 10 in the nth row of sub-pixels, and the second pole of the second driving transistor T02 is coupled with the first pole of the second switch transistor T2; the gate of the second switch transistor T2 is coupled with the first control signal end CS1, and the second pole of the second switch transistor T2 is coupled with the light emitting device L in the nth row of sub-pixels 10.

[0054] Wherein, the first driving current and the second driving current are the same, and the luminous brightness of the light emitting device L in the nth row of sub-pixels and the luminous brightness of the light emitting device L in the (n+1)th row of sub-pixels are the same.

[0055] Exemplarily, the second switch transistor T2 can be turned on under the control of the effective level of the first control signal transmitted on the first control signal end CS1, and can be turned off under the control of the ineffective level of the first control signal. For example, the second switch transistor T2 can be set as an N-type transistor, and the effective level of the first control signal is high level and the ineffective level of the first control signal is low level. Alternatively, the second switch transistor T2 can be set as a P-type transistor, and the effective level of the first control signal is low level and the ineffective level of the first control signal is high level.

[0056] The driving control circuit 20 in FIG. 2 of the present disclosure can ensure that the luminous brightness of the light emitting device in the nth row of sub-pixels is the same as the luminous brightness of the light emitting device in the (n+1)th row of sub-pixels, and the second driving transistor is provided, and the first driving transistor is provided in the pixel circuit, so that the luminous brightness of the light emitting device in the nth row of sub-pixels and the luminous brightness of the light emitting device in the (n+1)th row of sub-pixels can be ensured respectively, the problem of insufficient brightness of the light emitting device is avoided, and the problem of inconsistent luminous brightness between adjacent two rows of sub-pixels is improved, thereby avoiding the problem of black scan lines of the display panel, and improving the display effect.

[0057] In the embodiment of the present disclosure, the first driving transistor M0 and the second driving transistor T02 can be N-type transistors; wherein the first electrode of the first driving transistor M0 and the second driving transistor T02 can be the source thereof, the second electrode of the first driving transistor M0 and the second driving transistor T02 can be the drain thereof, and when the first driving transistor M0 and the second driving transistor T02 are in a saturated state, the current flows from the drain to the source thereof; of course, the first driving transistor M0 and the second driving transistor T02 can also be P-type transistors, and when the first driving transistor M0 and the second driving transistor T02 are in a saturated state, the current flows from the source to the drain thereof; which is not limited here.

[0058] And the light emitting device L generally realizes light emission under the action of the current when the first driving transistor M0 and the second driving transistor T02 are in a saturated state. Of course, in the embodiment of the present disclosure, only the case that the first driving transistor M0 and the second driving transistor T02 are P-type transistors is taken as an example for description, and for the case that the first driving transistor M0 and the second driving transistor T02 are N-type transistors, the design principle is the same as the present disclosure, and also belongs to the protection range of the present disclosure.

[0059] In the embodiments of the present disclosure, as shown in FIG. 2, the second electrode of the light emitting device L is coupled with the second power supply end VSS; and exemplarily, the light emitting device L can be an electroluminescent diode. For example, the light emitting device L can include at least one of an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), a micro light emitting diode (Micro LED), a mini light emitting diode (Mini LED), and the like. Exemplarily, the light emitting device L can include an anode, a light emitting layer, and a cathode which are arranged in a stack. Further, the light emitting layer can further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like. Of course, in actual applications, the specific structure of the light emitting device L can be determined according to the requirements of actual applications, which is not limited herein.

[0060] In the embodiments of the present disclosure, as shown in FIG. 2, the pixel circuit 10 further includes a data writing circuit coupled with the first electrode of the first drive transistor M0 and configured to provide a data voltage of a data signal end DA to the first electrode of the first drive transistor M0 in response to a signal of a first scan signal end SS1; wherein the data writing circuit includes a first transistor M1; a gate of the first transistor M1 is coupled with the first scan signal end SS1, a first electrode of the first transistor M1 is coupled with the first electrode of the first drive transistor M0, and a second electrode of the first transistor M1 is coupled with the data signal end DA.

[0061] Exemplarily, the first transistor M1 can be turned on under the control of an effective level of the first scan signal transmitted on the first scan signal end SS1, and can be turned off under the control of an ineffective level of the first scan signal. For example, the first transistor M1 can be set as an N-type transistor, and the effective level of the first scan signal is a high level and the ineffective level of the first scan signal is a low level. Alternatively, the first transistor M1 can be set as a P-type transistor, and the effective level of the first scan signal is a low level and the ineffective level of the first scan signal is a high level.

[0062] In the embodiment of the present disclosure, as shown in FIG. 2, the pixel circuit 10 further includes a conduction control circuit coupled with the second electrode and the gate electrode of the first driving transistor M0, configured to conduct the second electrode of the first driving transistor M0 with the gate electrode of the first driving transistor M0 in response to a signal of the first scan signal end SS1; wherein the conduction control circuit includes a second transistor M2 and a first capacitor C1; the gate electrode of the second transistor M2 is coupled with the first scan signal end SS1, the first electrode of the second transistor M2 is coupled with the second electrode of the first driving transistor M0, and the second electrode of the second transistor M2 is coupled with the gate electrode of the first driving transistor M0; the first electrode of the first capacitor C1 is coupled with the first power supply end VDD, and the second electrode of the first capacitor C1 is coupled with the gate electrode of the first driving transistor M0.

[0063] For example, the second transistor M2 can be set as an N-type transistor, and the effective level of the first scan signal is high level and the ineffective level of the first scan signal is low level. Alternatively, the second transistor M2 can be set as a P-type transistor, and the effective level of the first scan signal is low level and the ineffective level of the first scan signal is high level.

[0064] In the embodiment of the present disclosure, as shown in FIG. 2, the pixel circuit 10 further includes a reset circuit coupled with the gate electrode of the first driving transistor M0 and the light emitting device L, configured to provide the signal of the initialization signal end Vint to the gate electrode of the first driving transistor M0 in response to a signal of the first reset signal end RE1, and provide the signal of the initialization signal end Vint to the light emitting device L in response to a signal of the second reset signal end RE2; wherein the reset circuit includes a third transistor M3 and a fourth transistor M4; the gate electrode of the third transistor M3 is coupled with the first reset signal end RE1, the first electrode of the third transistor M3 is coupled with the gate electrode of the first driving transistor M0, and the second electrode of the third transistor M3 is coupled with the initialization signal end Vint; the gate electrode of the fourth transistor M4 is coupled with the second reset signal end RE2, the first electrode of the fourth transistor M4 is coupled with the light emitting device L, and the second electrode of the fourth transistor M4 is coupled with the initialization signal end Vint.

[0065] Exemplarily, the third transistor M3 can be turned on under the control of the active level of the first reset signal transmitted on the first reset signal terminal RE1, and can be turned off under the control of the inactive level of the first reset signal. For example, the third transistor M3 can be set as an N-type transistor, and the active level of the first reset signal is high level and the inactive level of the first reset signal is low level. Alternatively, the third transistor M3 can be set as a P-type transistor, and the active level of the first reset signal is low level and the inactive level of the first reset signal is high level.

[0066] Exemplarily, the fourth transistor M4 can be turned on under the control of the active level of the second reset signal transmitted on the second reset signal terminal RE2, and can be turned off under the control of the inactive level of the second reset signal. For example, the fourth transistor M4 can be set as an N-type transistor, and the active level of the second reset signal is high level and the inactive level of the second reset signal is low level. Alternatively, the fourth transistor M4 can be set as a P-type transistor, and the active level of the second reset signal is low level and the inactive level of the second reset signal is high level.

[0067] In the embodiment of the present disclosure, as shown in FIG. 2, the pixel circuit 10 further includes a light-emitting control circuit coupled with the first electrode of the first driving transistor M0, the second electrode of the first driving transistor M0 and the light-emitting device L, and configured to provide the signal of the first power supply terminal VDD to the first electrode of the first driving transistor M0 and turn on the second electrode of the first driving transistor M0 and the light-emitting device L in response to the signal of the light-emitting control signal terminal EM; wherein the light-emitting control circuit includes a fifth transistor M5 and a sixth transistor M6; the gate of the fifth transistor M5 is coupled with the light-emitting control signal terminal EM, the first electrode of the fifth transistor M5 is coupled with the first power supply terminal VDD, and the second electrode of the fifth transistor M5 is coupled with the first electrode of the first driving transistor M0; the gate of the sixth transistor M6 is coupled with the light-emitting control signal terminal EM, the first electrode of the sixth transistor M6 is coupled with the second electrode of the first driving transistor M0, and the second electrode of the sixth transistor M6 is coupled with the light-emitting device L.

[0068] Exemplarily, the fifth transistor M5 and the sixth transistor M6 can be turned on under the control of the active level of the light-emitting control signal transmitted on the light-emitting control signal terminal EM, and can be turned off under the control of the inactive level of the light-emitting control signal. For example, the fifth transistor M5 and the sixth transistor M6 can be set as N-type transistors, and the active level of the light-emitting control signal is high level and the inactive level of the light-emitting control signal is low level. Alternatively, the fifth transistor M5 and the sixth transistor M6 can also be set as P-type transistors, and the active level of the light-emitting control signal is low level and the inactive level of the light-emitting control signal is high level.

[0069] Exemplarily, the first electrode of the transistor described above can be the source electrode thereof, and the second electrode can be the drain electrode thereof. Alternatively, the first electrode can be the drain electrode thereof, and the second electrode can be the source electrode thereof. No limitation is made herein.

[0070] Generally, the leakage current of the transistor with the metal oxide semiconductor material as the active layer is small, and therefore, in order to reduce the leakage current, in some embodiments of the present disclosure, the material of the active layer of the transistor described above can include the metal oxide semiconductor material, for example, can be IGZO (Indium Gallium Zinc Oxide), and of course, can also be other metal oxide semiconductor materials, no limitation is made herein. In this way, the transistor described above can be set as an oxide transistor (Oxide Thin Film Transistor), so as to reduce the leakage current of the pixel circuit.

[0071] Generally, the transistor with the low temperature poly-silicon (LTPS) material as the active layer has high mobility, and can be made thinner and smaller, and has lower power consumption, etc., and in the specific implementation, the material of the active layer of the transistor described above can also be set as the low temperature poly-silicon material. In this way, the transistor described above can be set as an LTPS transistor, so as to realize high mobility, and can be made thinner and smaller, and has lower power consumption, etc.

[0072] Exemplarily, all the transistors in the pixel circuit and the driving control circuit of the present disclosure can be set as oxide transistors, or all the transistors in the pixel circuit and the driving control circuit of the present disclosure can be set as LTPS transistors, or part of the transistors in the pixel circuit and the driving control circuit of the present disclosure can be set as oxide transistors, and the other part of the transistors can be set as LTPS transistors.

[0073] In the embodiments of the present disclosure, the first power supply end VDD can be configured to load a constant first power supply voltage vdd, and the first power supply voltage vdd is generally positive. In addition, the second power supply end VSS can load a constant second power supply voltage vss, and the second power supply voltage vss can generally be a ground voltage or a negative value. In actual application, the specific values of the first power supply voltage vdd and the second power supply voltage vss can be designed and determined according to the actual application environment, no limitation is made herein.

[0074] The above is only an example to illustrate the specific structure of each circuit in the pixel circuit provided by the embodiments of the present disclosure, and in the specific implementation, the specific structure of the pixel circuit described above is not limited to the structure described above provided by the embodiments of the present disclosure, and can also be other structures known by those skilled in the art, as long as these are within the protection scope of the present disclosure, no limitation is made herein.

[0075] In the embodiments of the present disclosure, as shown in FIG. 1, one driving control circuit 20 is arranged in one-to-one correspondence with each sub-pixel spx in the first row to the (N-1)th row, and the nth row of sub-pixels spx in the same column are coupled through the corresponding driving control circuit 20 and the first electrode of the light emitting device L in the (n+1)th row of sub-pixels spx.

[0076] In the embodiments of the present disclosure, as shown in FIG. 1, the driving control circuit 20 is integrated in the pixel circuit 10 of the corresponding sub-pixel spx. Such an arrangement can save more space and improve the space utilization of the circuit.

[0077] In the embodiments of the present disclosure, as shown in FIG. 3, the driving control circuit 20 is located between the pixel circuits 10 in the adjacent two rows of sub-pixels spx. Such an arrangement can flexibly adjust the position of the driving control circuit and facilitate wiring and simplify circuit design.

[0078] In the embodiments of the present disclosure, as shown in FIG. 4, the driving control circuit 20 is located between the pixel circuits 10 in the adjacent two columns of sub-pixels spx. Such an arrangement can flexibly adjust the position of the driving control circuit and facilitate wiring and simplify circuit design.

[0079] In the embodiments of the present disclosure, the driving control circuit is integrated in the pixel circuit of the corresponding sub-pixel as an example.

[0080] The embodiments of the present disclosure provide a driving method of a display panel, including: controlling the pixel circuit in the sub-pixel to drive the light emitting device to emit light row by row.

[0081] The pixel circuit works in the data writing stage, the reset stage and the light emitting stage in sequence;

[0082] When the pixel circuit in the nth row of sub-pixels is in the light emitting stage, the pixel circuit in the (n+1)th row of sub-pixels is in the data writing stage, and the driving control circuit connected between the pixel circuit in the nth row of sub-pixels and the first electrode of the light emitting device in the (n+1)th row of sub-pixels transmits the first driving current generated by the pixel circuit in the nth row of sub-pixels and / or the second driving current generated according to the data voltage in the pixel circuit in the nth row of sub-pixels to the light emitting device in the (n+1)th row of sub-pixels in response to the signal of the first control signal end.

[0083] In the embodiments of the present disclosure, as shown in FIG. 5, the cutoff time t1 of the effective level of the first control signal end in the driving control circuit corresponding to the nth row of pixel circuits is not earlier than the cutoff time t2 of the data writing stage of the pixel circuit in the (n+1)th row of sub-pixels.

[0084] In the embodiment of the present disclosure, as shown in FIG. 5, the time t0 when the first control signal end in the driving control circuit corresponding to the nth row of pixel circuits is loaded with the effective level does not overlap with the reset stage F2 of the pixel circuit in the (n+1)th row of sub-pixels.

[0085] The working process of the circuit provided by the embodiment of the present disclosure will be described below by taking the circuit structure shown in FIG. 2 as an example and in combination with the signal timing diagram shown in FIG. 5.

[0086] As shown in FIG. 5, em(n) represents the light-emitting control signal of the light-emitting control signal end EM in the nth row of sub-pixels; re1(n) represents the first reset signal of the first reset signal end RE1 in the nth row of sub-pixels; ss1(n) represents the first scanning signal of the first scanning signal end SS1 in the nth row of sub-pixels; re2(n) represents the second reset signal of the second reset signal end RE2 in the nth row of sub-pixels; cs1(n) represents the first control signal of the first control signal end CS1 in the driving control circuit corresponding to the nth row of sub-pixels; em(n+1) represents the light-emitting control signal of the light-emitting control signal end EM in the (n+1)th row of sub-pixels; re1(n+1) represents the first reset signal of the first reset signal end RE1 in the (n+1)th row of sub-pixels; ss1(n+1) represents the first scanning signal of the first scanning signal end SS1 in the (n+1)th row of sub-pixels; and re2(n+1) represents the second reset signal of the second reset signal end RE2 in the (n+1)th row of sub-pixels.

[0087] When the pixel circuit in the nth row of sub-pixels is in the light-emitting stage F3, for the pixel circuit 10 in the nth row of sub-pixels, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the light-emitting control signal em(n), the second switch transistor T2 in the driving control circuit 20 corresponding to the nth row of sub-pixels is turned on under the control of the low level of the first control signal cs1(n); the first driving transistor M0 in the pixel circuit 10 in the nth row of sub-pixels generates a first driving current according to the data voltage; the second driving transistor T02 in the driving control circuit 20 corresponding to the nth row of sub-pixels generates a second driving current according to the data voltage; the turned-on fifth transistor M5 provides the signal of the first power supply end VDD to the first electrode of the first driving transistor M0, and the turned-on sixth transistor M6 turns on the second electrode of the first driving transistor M0 and the light-emitting device L, that is, provides the first driving current to the light-emitting device L in the nth row of sub-pixels, so that the light-emitting device L in the nth row of sub-pixels normally emits light; the turned-on second switch transistor T2 provides the second driving current to the light-emitting device L in the (n+1)th row of sub-pixels, so that the light-emitting device L in the (n+1)th row of sub-pixels also normally emits light;

[0088] At this time, the pixel circuit in the (n+1)th row of sub-pixels is in the data writing stage F1, for the pixel circuit 10 in the (n+1)th row of sub-pixels, first, the third transistor M3 is turned on under the control of the low level of the first reset signal re1(n), the signal of the initialization signal end Vint is provided to the gate of the first driving transistor M0, and the gate of the first driving transistor M0 is initialized; secondly, the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the first scanning signal ss1(n), the first transistor M1 that is turned on provides the data voltage of the data signal end DA to the first electrode of the first driving transistor M0, and the second transistor M2 that is turned on connects the second electrode of the first driving transistor M0 and the gate of the first driving transistor M0, so as to complete the compensation of the threshold voltage Vth of the first driving transistor M0 and the compensation of the threshold voltage Vth of the second driving transistor T02 in the driving control circuit 20 corresponding to the (n+1)th row of sub-pixels.

[0089] The embodiment of the present disclosure provides another structural schematic diagram of a driving control circuit, as shown in FIG. 6, which is deformed for the implementation in the above-mentioned embodiment. The differences between the present embodiment and the above-mentioned embodiment will be described below, and the same parts will not be described herein.

[0090] In the embodiment of the present disclosure, as shown in FIG. 6, the driving control circuit 20 is configured to transmit the first driving current generated by the pixel circuit 10 in the nth row of sub-pixels and the second driving current generated according to the data voltage in the pixel circuit 10 in the nth row of sub-pixels to the light emitting device L in the (n+1)th row of sub-pixels in response to the signal of the first control signal end CS1; wherein the driving control circuit 20 comprises: a third driving transistor T03, a third switch transistor T3 and a fourth switch transistor T4; the gate of the third driving transistor T03 is coupled with the gate of the first driving transistor M0 in the pixel circuit 10 in the nth row of sub-pixels, the first electrode of the third driving transistor T03 is coupled with the first electrode of the first driving transistor M0 in the pixel circuit 10 in the nth row of sub-pixels, and the second electrode of the third driving transistor T03 is coupled with the first electrode of the third switch transistor T3; the gate of the third switch transistor T3 is coupled with the first control signal end CS1, and the second electrode of the third switch transistor T3 is coupled with the second electrode of the first driving transistor T3 in the pixel circuit 10 in the nth row of sub-pixels; the gate of the fourth switch transistor T4 is coupled with the first control signal end CS1, the first electrode of the fourth switch transistor T4 is coupled with the light emitting device L in the pixel circuit 10 in the nth row of sub-pixels, and the second electrode of the fourth switch transistor T4 is coupled with the light emitting device L in the (n+1)th row of sub-pixels.

[0091] Compared with the driving control circuit in FIG. 2, the driving control circuit in the embodiment of the present disclosure can more accurately ensure that the driving currents transmitted to the light emitting devices in the nth row of sub-pixels and the light emitting devices in the (n+1)th row of sub-pixels are consistent in size, avoiding the problem of inconsistent driving current size caused by the process difference between the third driving transistor in the driving control circuit and the first driving transistor in the pixel circuit, that is, the driving control circuit in the embodiment of the present disclosure further ensures that the light emitting devices in the two adjacent rows of sub-pixels emit light with consistent brightness, thereby more effectively improving the black scan line problem of the display panel, and further improving the display effect and competitiveness of the product.

[0092] Next, taking the circuit structure shown in FIG. 6 as an example, the working process of the circuit provided in the embodiment of the present disclosure is described in combination with the signal timing diagram shown in FIG. 5.

[0093] When the pixel circuit in the nth row of sub-pixels is in the light emitting phase F3, for the pixel circuit 10 in the nth row of sub-pixels, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the light emitting control signal em(n), and the third switch transistor T3 and the fourth switch transistor T4 in the driving control circuit 20 corresponding to the nth row of sub-pixels are turned on under the control of the low level of the first control signal cs1(n); the first driving transistor M0 in the pixel circuit 10 in the nth row of sub-pixels generates a first driving current according to the data voltage; the third driving transistor T03 in the driving control circuit 20 corresponding to the nth row of sub-pixels generates a second driving current according to the data voltage; the fifth transistor M5 in the on state provides the signal of the first power supply end VDD to the first electrode of the first driving transistor M0; the third switch transistor T3 in the on state provides the second driving current to the first electrode of the sixth transistor M6; the sixth transistor M6 in the on state turns on the second electrode of the first driving transistor M0 and the light emitting device L, that is, provides the first driving current and the second driving current to the light emitting device L in the nth row of sub-pixels, so that the light emitting device L in the nth row of sub-pixels emits light normally; the fourth switch transistor T4 in the on state provides the first driving current and the second driving current to the light emitting device L in the (n+1)th row of sub-pixels, so that the light emitting device L in the (n+1)th row of sub-pixels also emits light normally;

[0094] At this time, the pixel circuit in the (n+1)th row of sub-pixels is in the data writing stage F1, for the pixel circuit 10 in the (n+1)th row of sub-pixels, first, the third transistor M3 is turned on under the control of the low level of the first reset signal re1(n), the signal of the initialization signal end Vint is provided to the gate of the first driving transistor M0, and the gate of the first driving transistor M0 is initialized; secondly, the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the first scanning signal ss1(n), the first transistor M1 that is turned on provides the data voltage of the data signal end DA to the first electrode of the first driving transistor M0, and the second transistor M2 that is turned on connects the second electrode of the first driving transistor M0 and the gate of the first driving transistor M0, so as to complete the compensation of the threshold voltage Vth of the first driving transistor M0 and the compensation of the threshold voltage Vth of the third driving transistor T03 in the driving control circuit 20 corresponding to the (n+1)th row of sub-pixels.

[0095] The embodiment of the present disclosure provides still another structural schematic diagram of a driving control circuit, as shown in FIG. 7, which is a transformation of the implementation in the above-mentioned embodiment. The differences between the present embodiment and the above-mentioned embodiment will be described below, and the same parts will not be described herein.

[0096] In the embodiment of the present disclosure, as shown in FIG. 7, the driving control circuit 20 is configured to transmit the first driving current generated by the pixel circuit 10 in the nth row of sub-pixels to the light emitting device L in the (n+1)th row of sub-pixels in response to the signal of the first control signal end CS1; wherein the driving control circuit 20 comprises: a first switch transistor T1; the gate of the first switch transistor T1 is coupled with the first control signal end CS1, the first electrode of the first switch transistor T1 is coupled with the light emitting device L in the pixel circuit 10 in the nth row of sub-pixels, and the second electrode of the first switch transistor T1 is coupled with the light emitting device L in the pixel circuit 10 in the (n+1)th row of sub-pixels.

[0097] Compared with the driving control circuit in FIG. 2, the driving control circuit in the embodiment of the present disclosure only needs one switch transistor, so that the production cost can be reduced, and the power consumption can also be reduced.

[0098] The working process of the circuit provided by the embodiment of the present disclosure will be described below by taking the circuit structure shown in FIG. 7 as an example and combining the signal timing diagram shown in FIG. 5.

[0099] When the pixel circuit in the nth row of sub-pixels is in the light-emitting stage F3, for the pixel circuit 10 in the nth row of sub-pixels, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the light-emitting control signal em(n), the first switch transistor T1 in the driving control circuit 20 corresponding to the nth row of sub-pixels is turned on under the control of the low level of the first control signal cs1(n); the first driving transistor M0 in the pixel circuit 10 in the nth row of sub-pixels generates a first driving current according to a data voltage; the turned-on fifth transistor M5 provides the signal of the first power supply end VDD to the first electrode of the first driving transistor M0; the turned-on sixth transistor M6 turns on the second electrode of the first driving transistor M0 and the light-emitting device L, that is, provides the first driving current to the light-emitting device L in the nth row of sub-pixels, so that the light-emitting device L in the nth row of sub-pixels normally emits light; the turned-on first switch transistor T1 provides the first driving current to the light-emitting device L in the (n+1)th row of sub-pixels, so that the light-emitting device L in the (n+1)th row of sub-pixels also normally emits light.

[0100] At this time, the pixel circuit in the (n+1)th row of sub-pixels is in the data writing stage F1, for the pixel circuit 10 in the (n+1)th row of sub-pixels, first, the third transistor M3 is turned on under the control of the low level of the first reset signal re1(n), and the signal of the initialization signal end Vint is provided to the gate of the first driving transistor M0 to initialize the gate of the first driving transistor M0; secondly, the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the first scanning signal ss1(n), the turned-on first transistor M1 provides the data voltage of the data signal end DA to the first electrode of the first driving transistor M0, and the turned-on second transistor M2 turns on the second electrode of the first driving transistor M0 and the gate of the first driving transistor M0, so as to complete the compensation of the threshold voltage Vth of the first driving transistor M0.

[0101] In the embodiment of the present disclosure, as shown in FIG. 8, further comprising: at least one row of virtual sub-pixels spx0 and a plurality of switch control circuits 40, the switch control circuit 40 is arranged one by one corresponding to the virtual sub-pixel spx0.

[0102] The virtual sub-pixel spx0 includes a virtual pixel circuit 30, the virtual pixel circuit 30 is coupled with the light-emitting device L in the first row of sub-pixels through the corresponding switch control circuit 40, and the switch control circuit 40 is configured to provide the driving current generated by the virtual pixel circuit 30 to the light-emitting device L in the first row of sub-pixels in response to the signal of the first control signal end CS1.

[0103] The present disclosure avoids the problem that the light emitting device in the first row of sub-pixels cannot emit light in the data writing stage by the cooperation of the virtual pixel circuit and the switch control circuit in the virtual sub-pixel, that is, avoids the problem that the brightness of the light emitting device in the first row of sub-pixels is inconsistent with that of the light emitting device in the second row of sub-pixels, better improves the black scan line problem of the display panel, and improves the display effect.

[0104] In the embodiment of the present disclosure, the virtual pixel circuit works in the data writing stage, the reset stage and the light emitting stage in turn, but since the virtual sub-pixel does not have a light emitting device, the virtual sub-pixel does not emit light.

[0105] In the embodiment of the present disclosure, as shown in FIGS. 9-11, the switch control circuit 40 includes a switch control transistor T0, the gate of the switch control transistor T0 is coupled with the first control signal end CS1, the first pole of the switch control transistor T0 is coupled with the second pole of the sixth transistor M6 in the virtual pixel circuit 30, and the second pole of the switch control transistor T0 is coupled with the first pole of the light emitting device L in the first row of sub-pixels.

[0106] Exemplarily, the switch control transistor T0 can be turned on under the control of the effective level of the first scanning signal transmitted on the first scanning signal end SS1, and can be turned off under the control of the ineffective level of the first scanning signal. For example, the switch control transistor T0 can be set as an N-type transistor, and the effective level of the first scanning signal is high level and the ineffective level of the first scanning signal is low level. Alternatively, the switch control transistor T0 can be set as a P-type transistor, and the effective level of the first scanning signal is low level and the ineffective level of the first scanning signal is high level.

[0107] In the embodiment of the present disclosure, the last row of sub-pixels in the display panel can be respectively and one-to-one correspondingly provided with a driving control circuit, and the first control signal end in the driving control circuit corresponding to the last row of sub-pixels is not loaded with an effective level signal. Such a setting can simplify the process and simplify the circuit arrangement.

[0108] In the embodiment of the present disclosure, the last row of sub-pixels in the display panel can not be provided with a driving control circuit. Such a setting can reduce the cost and reduce the power consumption.

[0109] Hereinafter, taking the circuit structure shown in FIG. 9 as an example, the working process of the circuit of the present disclosure is described in combination with the signal timing diagram shown in FIG. 12.

[0110] Wherein, as shown in Figure 12, em(0) represents the light emitting control signal of the light emitting control signal end EM in the virtual sub-pixel; re1(0) represents the first reset signal of the first reset signal end RE1 in the virtual sub-pixel; ss1(0) represents the first scanning signal of the first scanning signal end SS1 in the virtual sub-pixel; re2(0) represents the second reset signal of the second reset signal end RE2 in the virtual sub-pixel; cs1(0) represents the first control signal of the first control signal end CS1 in the corresponding switch control circuit in the virtual sub-pixel; em(1) represents the light emitting control signal of the light emitting control signal end EM in the first row of sub-pixels; re1(1) represents the first reset signal of the first reset signal end RE1 in the first row of sub-pixels; ss1(1) represents the first scanning signal of the first scanning signal end SS1 in the first row of sub-pixels; re2(1) represents the second reset signal of the second reset signal end RE2 in the first row of sub-pixels.

[0111] When the virtual pixel circuit in the virtual sub-pixel is in the light emitting stage F3, for the virtual pixel circuit 30 in the virtual sub-pixel, the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the low level of the light emitting control signal em(0), the switch control transistor TO in the switch control circuit 40 corresponding to the virtual sub-pixel is turned on under the control of the low level of the first control signal cs1(0); the first drive transistor M0 in the virtual pixel circuit 30 in the virtual sub-pixel generates a drive current according to the data voltage; the fifth transistor M5 provides the signal of the first power supply end VDD to the first electrode of the first drive transistor M0, the sixth transistor M6 turns on the second electrode of the first drive transistor M0 and the first electrode of the switch control transistor TO, that is, provides the drive current to the first electrode of the switch control transistor TO; the switch control transistor TO provides the drive current of the first electrode to the light emitting device L in the first row of sub-pixels, so that the light emitting device L in the first row of sub-pixels normally emits light when in the data writing stage F1;

[0112] At this time, the pixel circuit in the first row of the sub-pixels is in the data writing stage F1, for the pixel circuit 10 in the first row of the sub-pixels, first, the third transistor M3 is turned on under the control of the low level of the first reset signal re1(0), the signal of the initialization signal end Vi0t is provided to the gate of the first driving transistor M0, and the gate of the first driving transistor M0 is initialized; secondly, the first transistor M1 and the second transistor M2 are turned on under the control of the low level of the first scanning signal ss1(0), the first transistor M1 which is turned on provides the data voltage of the data signal end DA to the first electrode of the first driving transistor M0, and the second transistor M2 which is turned on connects the second electrode of the first driving transistor M0 with the gate of the first driving transistor M0, so as to complete the compensation of the threshold voltage Vth of the first driving transistor M0 and the compensation of the threshold voltage Vth of the second driving transistor T02 in the driving control circuit 20 corresponding to the first row of the sub-pixels.

[0113] Based on the same inventive concept, the embodiment of the present application further provides a display device comprising the display panel provided by the embodiment of the present application. The display device solves the problem in the same principle as the display panel, and therefore the implementation of the display device can be referred to the implementation of the display panel, and the repeated parts will not be described here.

[0114] In the embodiment of the present application, the display device can be any product or component with display function, such as mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc. The other essential components of the display device are understood by those skilled in the art, and will not be described here, nor should it be regarded as a limitation to the present application.

[0115] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the changes and modifications falling within the scope of the present application.

[0116] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, include: Multiple sub-pixels, each sub-pixel including: a light-emitting device and a pixel circuit coupled to a first pole of the light-emitting device; Multiple driving control circuits are provided. The pixel circuit in the nth row of sub-pixels is coupled to the first pole of the light-emitting device in the (n+1)th row of sub-pixels through at least one of the driving control circuits. The driving control circuit is configured to transmit a first driving current generated by the pixel circuit in the nth row of sub-pixels and / or a second driving current generated according to the data voltage in the pixel circuit in the nth row of sub-pixels to the light-emitting device in the (n+1)th row of sub-pixels in response to a signal at a first control signal terminal. Here, n is a positive integer greater than 0.

2. The display panel as claimed in claim 1, wherein, The drive control circuit includes: a first switching transistor; The gate of the first switching transistor is coupled to the first control signal terminal, the first terminal of the first switching transistor is coupled to the light-emitting device in the pixel circuit of the nth row of sub-pixels, and the second terminal of the first switching transistor is coupled to the light-emitting device in the pixel circuit of the (n+1)th row of sub-pixels.

3. The display panel as claimed in claim 1, wherein, The pixel circuit further includes: a first driving transistor; The drive control circuit includes: a second drive transistor and a second switching transistor; The gate of the second driving transistor is coupled to the gate of the first driving transistor in the pixel circuit of the nth row of sub-pixels, the first terminal of the second driving transistor is coupled to the first terminal of the first driving transistor in the pixel circuit of the nth row of sub-pixels, and the second terminal of the second driving transistor is coupled to the first terminal of the second switching transistor. The gate of the second switching transistor is coupled to the first control signal terminal, and the second terminal of the second switching transistor is coupled to the light-emitting device in the (n+1)th row of sub-pixels.

4. The display panel as claimed in claim 1, wherein, The pixel circuit further includes: a first driving transistor; The drive control circuit includes: a third drive transistor, a third switching transistor, and a fourth switching transistor; The gate of the third driving transistor is coupled to the gate of the first driving transistor in the pixel circuit of the nth row of sub-pixels, the first electrode of the third driving transistor is coupled to the first electrode of the first driving transistor in the pixel circuit of the nth row of sub-pixels, and the second electrode of the third driving transistor is coupled to the first electrode of the third switching transistor. The gate of the third switching transistor is coupled to the first control signal terminal, and the second terminal of the third switching transistor is coupled to the second terminal of the first driving transistor in the pixel circuit of the nth row of sub-pixels. The gate of the fourth switching transistor is coupled to the first control signal terminal, the first terminal of the fourth switching transistor is coupled to the light-emitting device in the pixel circuit of the nth row of sub-pixels, and the second terminal of the fourth switching transistor is coupled to the light-emitting device in the (n+1)th row of sub-pixels.

5. The display panel as described in any one of claims 1-4, wherein, Each sub-pixel in the first row to the (N-1)th row is provided with a corresponding driving control circuit. The sub-pixel in the nth row of the same column is coupled to the first pole of the light-emitting device in the (n+1)th row of the sub-pixel through the corresponding driving control circuit.

6. The display panel as claimed in claim 5, wherein, The drive control circuit is located between the pixel circuits in two adjacent rows of sub-pixels.

7. The display panel as claimed in claim 5, wherein, The drive control circuit is located between the pixel circuits in two adjacent columns of sub-pixels.

8. The display panel as claimed in claim 5, wherein, The drive control circuit is integrated into the pixel circuit of the corresponding sub-pixel.

9. The display panel according to any one of claims 1-4, wherein, Also includes: At least one row of virtual sub-pixels and multiple switch control circuits, wherein the switch control circuits are configured in a one-to-one correspondence with the virtual sub-pixels; The virtual sub-pixel includes a virtual pixel circuit, which is coupled to the light-emitting device in the first row of sub-pixels via a corresponding switch control circuit. The switch control circuit is configured to provide the driving current generated by the virtual pixel circuit to the light-emitting device in the first row of sub-pixels in response to a signal at the first control signal terminal.

10. A display device comprising a display panel as described in any one of claims 1-9.

11. A method for driving a display panel, wherein, include: The pixel circuits in each sub-pixel are controlled row by row to drive the light-emitting devices to emit light. The pixel circuit operates in the data writing stage, the reset stage, and the light emission stage in sequence. When the pixel circuit in the nth row of sub-pixels is in the light-emitting stage, the pixel circuit in the (n+1)th row of sub-pixels is in the data-writing stage. Furthermore, the driving control circuit connected between the first electrode of the pixel circuit in the nth row of sub-pixels and the light-emitting device in the (n+1)th row of sub-pixels responds to the signal at the first control signal terminal by transmitting the first driving current generated by the pixel circuit in the nth row of sub-pixels and / or the second driving current generated according to the data voltage in the pixel circuit in the nth row of sub-pixels to the light-emitting device in the (n+1)th row of sub-pixels.

12. The driving method for a display panel as described in claim 11, wherein, The cutoff time of the effective level of the first control signal terminal in the drive control circuit corresponding to the nth row pixel circuit is not earlier than the cutoff time of the data writing stage of the pixel circuit in the (n+1)th row sub-pixel.

13. The driving method for a display panel as described in claim 12, wherein, The time when the first control signal terminal of the drive control circuit corresponding to the nth row pixel circuit is loaded with an effective level does not overlap with the reset phase of the pixel circuit in the (n+1)th row sub-pixel.

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