Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises a pixel definition layer and a light-emitting device layer that are stacked; the pixel definition layer is provided with a plurality of pixel openings and a plurality of partition structures, at least some of the partition structures are in one-to-one correspondence with at least some of the pixel openings, and the partition structures are configured as closed structures surrounding the corresponding pixel openings; and in a plane where the display substrate is located, the light-emitting device layer comprises a plurality of light-emitting units divided by the plurality of partition structures, at least some of the light-emitting units are in one-to-one correspondence with at least some of the pixel openings, and the light-emitting units are at least partially located within the corresponding pixel openings.

Description

Display substrate, preparation method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202410824816.X, filed on June 24, 2024, and entitled "Display substrate, preparation method thereof and display device", the contents of which are to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] The embodiments of the present disclosure relate to, but are not limited to, the technical field of display, and in particular, to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0003] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. With the continuous development of display technology, a display device with an OLED as a light emitting device and a thin film transistor (TFT) for signal control has become the mainstream product in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a display substrate, comprising a pixel definition layer and a light emitting device layer stacked, a plurality of pixel openings and a plurality of partition structures are provided on the pixel definition layer, at least part of the partition structures correspond to at least part of the pixel openings one by one, the partition structure is set as a closed structure surrounding the corresponding pixel opening, in the plane where the display substrate is located, the light emitting device layer comprises a plurality of light emitting units divided by the plurality of partition structures, at least part of the light emitting units correspond to at least part of the pixel openings one by one, and at least part of the light emitting units are located in the corresponding pixel openings.

[0006] In an exemplary embodiment, in the direction perpendicular to the plane where the display substrate is located, the light emitting device layer comprises a plurality of light emitting device sub-layers, and the light emitting unit comprises a plurality of light emitting devices, different light emitting devices in the same light emitting unit are located in different light emitting device sub-layers; in the direction of the pixel definition layer pointing to the light emitting device layer, the light emitting device sub-layers comprise a first electrode layer, a light emitting structure layer and a second electrode layer in sequence, and the second electrode layer of one of the light emitting device sub-layers in the adjacent two light emitting device sub-layers is multiplexed as the first electrode layer of the other light emitting device sub-layer.

[0007] The partition structure comprises at least a plurality of lapping substructures, in the partition structure corresponding to a same pixel opening, the plurality of lapping substructures correspond to the plurality of light emitting device sublayers one by one, and the lapping substructures are arranged to be in lapping connection with the second electrode layers in the corresponding light emitting device sublayers.

[0008] In an example embodiment, in the same partition structure, the plurality of lapping substructures are arranged as a closed structure surrounding the corresponding pixel opening; in the plane where the display substrate is located, along the direction in which the pixel opening points to the corresponding partition structure, in the partition structure corresponding to a same pixel opening, the plurality of lapping substructures are arranged in sequence with a spacing, and the surface of the plurality of lapping substructures away from the pixel definition layer has a height relative to the surface of the pixel definition layer close to the light emitting device layer that increases in sequence, thereby sequentially dividing the plurality of light emitting device sublayers into a plurality of light emitting devices corresponding to the pixel opening.

[0009] In an example embodiment, in the plane where the display substrate is located, along the direction in which the pixel opening points to the corresponding partition structure, in the partition structure corresponding to a same pixel opening, the plurality of lapping substructures are sequentially in lapping connection with the plurality of second electrode layers along the direction in which the pixel definition layer points to the light emitting device layer.

[0010] In the direction perpendicular to the plane where the display substrate is located, the lapping substructure is arranged to at least disconnect the film layer structure between the second electrode layer in the light emitting device layer in lapping connection therewith and the pixel definition layer.

[0011] In an example embodiment, the partition structure further comprises a first isolation structure, in the direction perpendicular to the plane where the display substrate is located, the first isolation structure is located on the side of the pixel definition layer close to the light emitting device layer, in the partition structure corresponding to a same pixel opening, the first isolation structure is arranged as a closed structure surrounding the corresponding pixel opening, and in the direction in which the closed structure of the first isolation structure surrounds, the plurality of lapping substructures are arranged with a spacing through the first isolation structure; in the direction perpendicular to the plane where the display substrate is located, the height of the surface of the first isolation structure away from the pixel definition layer relative to the pixel definition layer is greater than the height of the surface of the light emitting device layer away from the pixel definition layer relative to the pixel definition layer.

[0012] In an example embodiment, the partition structure further comprises a second isolation structure, the second isolation structure is arranged as a closed structure surrounding the corresponding pixel opening, thereby dividing the light emitting device layer into a plurality of light emitting units, in the partition structure corresponding to a same pixel opening along the direction in which the pixel opening points to the partition structure, the plurality of lapping substructures are located between the corresponding pixel opening and the second isolation structure.

[0013] The second isolation structure is disposed on a side of the pixel definition layer close to the light emitting device layer in a direction perpendicular to a plane where the display substrate is located, and has a thickness greater than a thickness of the light emitting device layer and penetrating the light emitting device layer.

[0014] In an exemplary embodiment, the second isolation structures corresponding to the plurality of pixel openings are interconnected to form a grid-like structure.

[0015] In an exemplary embodiment, the partition structure further comprises a first cut-off structure, which is located on a side of the second isolation structure away from the pixel definition layer in a direction perpendicular to a plane where the display substrate is located, and has a size greater than a size of the corresponding second isolation structure in a direction of the pixel opening pointing to the corresponding partition structure.

[0016] In an exemplary embodiment, the plurality of light emitting device sub-layers comprises a first type of light emitting device sub-layer and at least one second type of light emitting device sub-layer, and the second type of light emitting device sub-layer is located on a side of the first type of light emitting device sub-layer away from the pixel definition layer in a direction perpendicular to a plane where the display substrate is located.

[0017] The plurality of overlapping sub-structures corresponding to the same pixel opening comprises a first type of overlapping sub-structure and at least one second type of overlapping sub-structure, the first type of overlapping sub-structure is in overlapping connection with the second electrode layer in the first type of light emitting device sub-layer, and the second type of overlapping sub-structure is in overlapping connection with the second electrode in the corresponding second type of light emitting device sub-layer.

[0018] In an exemplary embodiment, the first type of overlapping sub-structure comprises a first region located on a side of the pixel definition layer close to the light emitting device layer in a direction perpendicular to a plane where the display substrate is located, and a surface of the first region away from the pixel definition layer has a height relative to the pixel definition layer greater than or equal to a distance between a surface of the first type of light emitting device sub-layer away from the pixel definition layer and the pixel definition layer, and less than a distance between the second electrode layer in the second type of light emitting device closest to the first type of light emitting device sub-layer and the pixel definition layer.

[0019] The first type of overlapping sub-structure is in overlapping connection with the second electrode layer in the first type of light emitting device sub-layer through the first region.

[0020] In an example embodiment, in a direction perpendicular to a plane where the display substrate is located, the second type of overlap substructure includes a first region and a second region, the second region is located between the first region and the pixel definition layer, in the same second type of overlap substructure, a height of a surface of the first region away from the pixel definition layer relative to the pixel definition layer is greater than or equal to a distance between a surface of a corresponding second type of light emitting device sublayer away from the pixel definition layer and the pixel definition layer; a height of a surface of the second region away from the pixel definition layer relative to the pixel definition layer is greater than or equal to a distance between a surface of a first electrode layer in the corresponding second type of light emitting device sublayer away from the pixel definition layer and the pixel definition layer, and less than a distance between a second electrode layer in the corresponding second type of light emitting device sublayer and the pixel definition layer.

[0021] In the second type of overlap substructure, the first region is overlap connected with the second electrode layer in the corresponding second type of light emitting device sublayer, and a surface of the second region is provided with an insulating structure configured to electrically insulate the second region from the light emitting device layer.

[0022] In an example embodiment, in at least part of the second type of overlap substructure, a height of a surface of the first region away from the pixel definition layer relative to the pixel definition layer is less than a distance between a second electrode layer in a first type of adjacent light emitting device sublayer and the pixel definition layer, the first type of adjacent light emitting device sublayer is a light emitting device sublayer most adjacent to the corresponding second type of light emitting device sublayer and located on a side of the corresponding second type of light emitting device sublayer away from the pixel definition layer.

[0023] In an example embodiment, in a direction from the pixel definition layer to the light emitting device layer, the plurality of light emitting device sublayers at least sequentially include a first light emitting device sublayer, a second light emitting device sublayer, and a third light emitting device sublayer, the first type of light emitting device sublayer includes the first light emitting device sublayer, and the second type of light emitting device sublayer includes the second light emitting device sublayer and the third light emitting device sublayer; the plurality of overlap substructures includes a first overlap substructure, a second overlap substructure, and a third overlap substructure, the first type of overlap substructure includes the first overlap substructure, and the second type of overlap substructure includes the second overlap substructure and the third overlap substructure; the first overlap substructure is overlap connected with the first light emitting device sublayer, the second overlap substructure is overlap connected with the second light emitting device sublayer, and the third overlap substructure is overlap connected with the third light emitting device sublayer.

[0024] In a direction perpendicular to a plane where the display substrate is located, a height of a surface of the third lap joint substructure away from a side of the pixel definition layer relative to the pixel definition layer has the following relationship with thicknesses of film layers in the light emitting device layer: M1+C1+M2+C2+M3+C3

[0025] In a direction perpendicular to a plane where the display substrate is located, M1 is a thickness of a light emitting structure layer in a first light emitting device sublayer, M2 is a thickness of a light emitting structure layer in a second light emitting device sublayer, M3 is a thickness of a light emitting structure layer in a third light emitting device sublayer, C1 is a thickness of a second electrode in the first light emitting device sublayer, C2 is a thickness of a second electrode in the second light emitting device sublayer, C3 is a thickness of a second electrode in the third light emitting device sublayer, and H3 is a height of a surface of the third lap joint substructure away from a side of the pixel definition layer relative to the pixel definition layer.

[0026] In an example embodiment, in a direction perpendicular to a plane where the display substrate is located, a height of a surface of the second lap joint substructure away from a side of the pixel definition layer relative to the pixel definition layer has the following relationship with thicknesses of film layers in the light emitting device layer: M1+C1+M2+C2

[0027] In a direction perpendicular to a plane where the display substrate is located, H2 is a height of a surface of the second lap joint substructure away from a side of the pixel definition layer relative to the pixel definition layer.

[0028] In an example embodiment, in a direction perpendicular to a plane where the display substrate is located, a height of a surface of the first lap joint substructure away from a side of the pixel definition layer relative to the pixel definition layer has the following relationship with thicknesses of film layers in the light emitting device layer: M1+C1

[0029] In a direction perpendicular to a plane where the display substrate is located, H1 is a height of a surface of the first lap joint substructure away from a side of the pixel definition layer relative to the pixel definition layer.

[0030] In an example embodiment, in a direction perpendicular to a plane where the display substrate is located, a height of a surface of a second region in the second lap joint substructure away from a side of the pixel definition layer relative to the pixel definition layer has the following relationship with thicknesses of film layers in the light emitting device layer: M1+C1+(1 / 2)M2

[0031] In a direction perpendicular to a plane where the display substrate is located, W1 is a height of a surface of a second region in the second lap joint substructure away from a side of the pixel definition layer relative to the pixel definition layer.

[0032] In an example embodiment, in a direction perpendicular to a plane where the display substrate is located, a height of a surface of the second region in the third sub-lap structure away from a side of the pixel definition layer relative to the pixel definition layer is related to a thickness of a film layer in the light emitting device layer as follows: M1+C1+M2+C2+(1 / 2)M3

[0033] In a direction perpendicular to a plane where the display substrate is located, W2 is a height of a surface of the second region in the third sub-lap structure away from a side of the pixel definition layer relative to the pixel definition layer.

[0034] In an example embodiment, the partition structure further comprises a plurality of second cut-off structures, in the partition structure corresponding to a same pixel opening, the plurality of second cut-off structures correspond one-to-one to the plurality of sub-lap structures, in a direction of the pixel opening pointing to the corresponding partition structure, a size of the second cut-off structure is greater than a size of the corresponding sub-lap structure.

[0035] In a direction perpendicular to a plane where the display substrate is located, the second cut-off structure is located away from a side of the pixel definition layer.

[0036] In an example embodiment, in a cross-sectional structure in a direction of the pixel opening pointing to the corresponding partition structure, the second cut-off structure and the corresponding sub-lap structure form a T shape in cross section.

[0037] In an example embodiment, in a direction perpendicular to a plane where the display substrate is located, a height of a surface of the second cut-off structure away from a side of the pixel definition layer relative to the pixel definition layer is greater than a distance between a surface of a second electrode layer in a first type of adjacent light emitting device sub-layer away from the side of the pixel definition layer and the pixel definition layer, and is less than a distance between a surface of a corresponding light emitting device sub-layer away from the side of the pixel definition layer and the pixel definition layer, the first type of adjacent light emitting device sub-layer is a light emitting device sub-layer most adjacent to the corresponding light emitting device sub-layer and located away from a side of a second type of light emitting device sub-layer.

[0038] In an example embodiment, in a plane where the display substrate is located, on a same side of a center of the second cut-off structure in a direction of the pixel opening pointing to the corresponding partition structure, a difference between a size of the second cut-off structure and a size of the corresponding sub-lap structure is 0.1 microns to 0.6 microns; in a direction perpendicular to the plane where the display substrate is located, the size of the second cut-off structure is 2 nanometers to 25 nanometers.

[0039] In an example embodiment, in a plane in which the display substrate is located, in a direction along the pixel opening pointing to the corresponding partition structure, in the partition structure corresponding to the same pixel opening, the size of the sub-lap structure is 3 microns to 13 microns.

[0040] In an example embodiment, the partition structure further comprises a third cut-off structure, in the partition structure corresponding to the same pixel opening, in a direction along the pixel opening pointing to the corresponding partition structure, the size of the third cut-off structure is greater than the size of the corresponding sub-lap structure.

[0041] In a direction perpendicular to the plane in which the display substrate is located, the third cut-off structure is located on the side of the corresponding first isolation structure away from the pixel definition layer.

[0042] In an example embodiment, the display substrate further comprises a back plate and an anode layer, in a direction perpendicular to the plane in which the display substrate is located, the back plate is located on the side of the pixel definition layer away from the light emitting device layer, the anode layer is located between the back plate and the pixel definition layer, the anode layer comprises a plurality of anodes, at least part of the anodes correspond to at least part of the pixel openings and at least part of the light emitting units one by one, the orthographic projection of the pixel opening on the back plate is located within the orthographic projection of the corresponding anode on the back plate.

[0043] In the anode and the light emitting unit corresponding to the same pixel opening, the anode is multiplexed as the first electrode of the light emitting device closest to the side of the back plate in the light emitting unit.

[0044] In an example embodiment, a plurality of electrode traces are provided in the back plate, at least part of the electrode traces are electrically connected to at least part of the sub-lap structures one by one, in a direction perpendicular to the plane in which the display substrate is located, the sub-lap structure is provided to be electrically connected to the corresponding electrode trace at one end and to be lap-connected to the corresponding second electrode layer through the pixel definition layer at the other end.

[0045] In an example embodiment, in a direction perpendicular to the plane in which the display substrate is located, the thickness of the light emitting structure layer is 2000 angstroms to 4000 angstroms, the thickness of the first electrode layer is 8 nanometers to 55 nanometers, the thickness of the second electrode layer is 8 nanometers to 55 nanometers, and the thickness of the pixel definition layer is 0.5 microns to 3 microns.

[0046] In an example embodiment, the material of the first electrode layer and the second electrode layer is metal, in a direction perpendicular to the plane in which the display substrate is located, the thickness of the first electrode layer is 8 nanometers to 25 nanometers, and the thickness of the second electrode layer is 8 nanometers to 25 nanometers.

[0047] Alternatively, the material of the first electrode layer and the second electrode layer is a semiconductor oxide, the thickness of the first electrode layer is 8-55 nm in a direction perpendicular to the plane of the display substrate, and the thickness of the second electrode layer is 8-55 nm in the direction perpendicular to the plane of the display substrate.

[0048] In a second aspect, the embodiments of the present disclosure provide a display device, which comprises the display substrate described in any of the above embodiments.

[0049] In a third aspect, the embodiments of the present disclosure provide a method for manufacturing a display substrate, which comprises:

[0050] forming a pixel definition layer on one side of the back plate, the pixel definition layer being provided with a plurality of pixel openings;

[0051] forming a plurality of partition structures on the side of the pixel definition layer away from the back plate, at least part of the partition structures corresponding to at least part of the pixel openings one by one, the partition structures being arranged as closed structures surrounding the corresponding pixel openings;

[0052] forming a light-emitting device layer on the side of the partition structures away from the back plate, the light-emitting device layer comprising a plurality of light-emitting units divided by the plurality of partition structures in the plane of the display substrate, at least part of the light-emitting units corresponding to at least part of the pixel openings one by one, and at least part of the light-emitting units being located in the corresponding pixel openings.

[0053] Other aspects can become apparent from a consideration of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0054] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0055] FIG. 1 shows a structural schematic diagram of a display device provided by an embodiment of the present disclosure;

[0056] FIG. 2 shows a planar structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0057] FIG. 3 shows a planar structural schematic diagram of a display substrate provided by an embodiment of the present disclosure;

[0058] FIG. 4 shows a cross-sectional structural schematic diagram of FIG. 3 along A1-A1;

[0059] FIG. 5 shows a cross-sectional structural schematic diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0060] FIG. 6 shows a planar structure of a display substrate according to an embodiment of the present disclosure;

[0061] FIG. 7a shows a cross-sectional structure of a B1-B1 position in FIG. 6;

[0062] FIG. 7b shows a cross-sectional structure of a B11-B11 position in FIG. 6;

[0063] FIG. 8 shows a cross-sectional structure of a B2 position in FIG. 6;

[0064] FIG. 9 shows a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0065] FIG. 10 shows a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0066] FIG. 11 shows a cross-sectional structure of a B3 position in FIG. 9 and FIG. 10;

[0067] FIG. 12 shows a cross-sectional structure of an A2-A2 position in FIG. 9;

[0068] FIG. 13 shows a cross-sectional structure of a B4-B4 position in FIG. 10;

[0069] FIG. 14 shows a local enlarged structure in FIG. 5;

[0070] FIG. 15 shows a structure after removing a light emitting device layer in FIG. 14;

[0071] FIG. 16 shows a structure after removing a light emitting device layer in FIG. 13;

[0072] FIG. 17 shows a cross-sectional structure of an A2-A2 position in FIG. 9;

[0073] FIG. 18 shows a cross-sectional structure of a B4-B4 position in FIG. 10;

[0074] FIG. 19a shows a cross-sectional structure after forming a pixel definition layer according to an exemplary embodiment of the present disclosure;

[0075] FIG. 19b shows a cross-sectional structure after forming a lap via according to an exemplary embodiment of the present disclosure;

[0076] FIG. 19c shows a cross-sectional structure after forming a lap electrode pillar according to an exemplary embodiment of the present disclosure;

[0077] FIG. 19d shows a cross-sectional structure after forming a lap substructure according to an exemplary embodiment of the present disclosure;

[0078] FIG. 19e is a schematic view of a cross-sectional structure after forming a second cut-off structure according to an exemplary embodiment of the present disclosure;

[0079] FIG. 20 is a schematic view of a cross-sectional structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0080] FIG. 21 is a schematic view of a display device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0081] Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. Note that the present application can be implemented in various forms. In addition, those skilled in the art can understand that the present application can be carried out in other specific forms without changing the spirit or the substance thereof. Therefore, the present disclosure should not be interpreted as being limited to the following embodiments. Embodiments in the present disclosure and features in the embodiments can be combined with each other as long as there is no contradiction in combination. In order to keep the following description of the embodiments of the present disclosure clear and brief, detailed description of some known functions and known components is omitted. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to general design.

[0082] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the width-length ratio of the channel, the thickness and the interval of each film layer, and the width and the interval of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic views of structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0083] In the present specification, ordinal numbers such as "first", "second", and "third" are used to avoid confusion of components, and are not intended to limit in terms of numbers.

[0084] In the present specification, words indicating directions or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0085] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connected" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the actual situation.

[0086] In this specification, "electrically connected" includes the case where the constituent elements are connected together through an element having some electrical effect. The "element having some electrical effect" is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the "element having some electrical effect" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0087] In this specification, "parallel" means that the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes the case where the angle is -5° or more and 5° or less. In addition, "perpendicular" means that the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes the case where the angle is 85° or more and 95° or less.

[0088] In this specification, "film" and "layer" can be interchanged. For example, "conductive layer" can be replaced with "conductive film". Similarly, "insulating film" can be replaced with "insulating layer".

[0089] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly, and can be an approximate triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. There can be some small deformation due to tolerance, there can be an angle, an arc edge, and deformation, etc.

[0090] In this disclosure, "about" means not strictly limited boundaries, allowing values within the range of process and measurement errors.

[0091] FIG. 1 is a schematic view of the structure of a display device. As shown in FIG. 1, the display device can include a timing controller, a data signal driver, a scan signal driver, and a pixel array, and the pixel array can include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), and a plurality of sub-pixels Pxij.

[0092] In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data signal driver to the data signal driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver. The data signal driver can generate a data voltage to be provided to the data signal lines D1, D2, D3,..., and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driver can sample the gray scale value using the clock signal, and apply a data voltage corresponding to the gray scale value to the data signal lines D1 to Dn in units of sub-pixel behavior, n can be a natural number. The scan signal driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3,..., and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driver can sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver can be configured in the form of a shift register, and can generate a scan signal in a manner of sequentially transferring a scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of a clock signal, m can be a natural number. The sub-pixel array can include a plurality of pixel sub-PXij. Each pixel sub-PXij can be connected to a corresponding data signal line and a corresponding scan signal line, i and j can be natural numbers. The sub-pixel PXij can refer to a sub-pixel in which a transistor is connected to an i-th scan signal line and connected to a j-th data signal line.

[0093] FIG. 2 is a schematic diagram of a planar structure of a display device. As shown in FIG. 2, the display area of the display device can include a plurality of pixel units P (may be referred to as light emitting units) arranged in a matrix manner, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light emitting device. The pixel driving circuit in the sub-pixel is connected to a scan signal line and a data signal line, respectively, and the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line, and output a corresponding current to the light emitting device. The light emitting device in the sub-pixel is connected to the pixel driving circuit in the sub-pixel, respectively, and the light emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit in the sub-pixel.

[0094] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel emitting red (R) light, the second sub-pixel P2 can be a blue sub-pixel emitting blue (B) light, and the third sub-pixel P3 can be a green sub-pixel emitting green (G) light. In an example embodiment, the shape of the sub-pixel can be any one or more of a triangle, a square, a rectangle, a diamond, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons, and can be arranged in a horizontal side-by-side manner, a vertical side-by-side manner, an X shape, a cross shape, a pin shape, a square shape, a diamond shape, or a delta shape, without limitation in the present disclosure.

[0095] In an example embodiment, the number of sub-pixels included in a pixel unit is not limited to three, for example, a pixel unit can include four sub-pixels, without limitation in the present disclosure.

[0096] As shown in FIG. 2, the OLED display technology usually adopts a periodic arrangement of RGB three sub-pixels or RGBW four sub-pixels to realize full-color display, that is, one pixel includes three sub-pixels or four sub-pixels arranged in a tiling manner. This arrangement has the following problems: first, the sub-pixel aperture ratio needs to be balanced according to the device efficiency and service life performance of different colors, and the pixel aperture ratio of different colors can be different, and there is a problem of low pixel aperture ratio of at least part of the sub-pixels; second, since one pixel needs three or four sub-pixels, at least three pixel driving circuits need to be provided for driving the corresponding sub-pixels, resulting in an increase in signal traces in the driving backplane, difficulty in improving pixel density, and a corresponding increase in cost; third, the three sub-pixels or four sub-pixels are periodically arranged in a tiling manner, which makes it difficult to realize super-high pixel density (English full name: pixels per inch, abbreviated as PPI), that is, it is difficult to improve the pixel density. The RGB three sub-pixels are arranged in a stacked structure, and the lighting of different colors is controlled by time sharing to realize full-color display. The aperture ratio of such a structure can be about 3 times the aperture ratio of the structure shown in FIG. 2. In the case where the device performance does not change, the performance of the product can be greatly improved, the pixel density is about 3 times that of the product shown in FIG. 2, and the service life of the product can be improved by about three times. The RGB three sub-pixels are arranged in a stacked structure, and a fine metal mask (English full name: Fine Metal Mask, abbreviated as FMM) is used to prepare the organic light-emitting layer and the cathode electrode layer. The fine metal mask (FMM) has a high cost and is difficult to apply to large-size OLED display products.

[0097] The display substrate provided by the embodiments of the present disclosure can include a pixel definition layer, a light emitting device layer, a plurality of pixel openings and a plurality of partition structures on the pixel definition layer, at least part of the partition structures correspond to at least part of the pixel openings, the partition structures are arranged as closed structures surrounding the corresponding pixel openings, the light emitting device layer includes a plurality of light emitting units divided by the plurality of partition structures, and at least part of the light emitting units are located in the corresponding pixel openings.

[0098] The display substrate provided by the embodiments of the present disclosure can include a pixel definition layer, a light emitting device layer, a plurality of pixel openings and a plurality of partition structures on the pixel definition layer, at least part of the partition structures correspond to at least part of the pixel openings, the partition structures are arranged as closed structures surrounding the corresponding pixel openings, the light emitting device layer includes a plurality of light emitting units divided by the plurality of partition structures, and at least part of the light emitting units are located in the corresponding pixel openings.

[0099] As shown in FIGS. 3-5, FIG. 3 is a schematic diagram of a planar structure of a display substrate, FIG. 4 is a schematic diagram of a cross-sectional structure at position A1-A1 in FIG. 3, and FIG. 5 is a schematic diagram of an enlarged structure at a local position in FIG. 4. The display substrate provided by the embodiments of the present disclosure can include a pixel definition layer PDL and a light emitting device layer P0 stacked together, a plurality of pixel openings K1 and a plurality of partition structures 21 on the pixel definition layer PDL, at least part of the partition structures 21 corresponding to at least part of the pixel openings K1, the partition structures 21 arranged as closed structures surrounding the corresponding pixel openings K1, the light emitting device layer P0 including a plurality of light emitting units P divided by the plurality of partition structures 21 in a plane where the display substrate is located, at least part of the light emitting units P corresponding to at least part of the pixel openings K1, and at least part of the light emitting units P located in the corresponding pixel openings K1.

[0100] In the exemplary embodiments, the plurality of light emitting units P in the light emitting device layer P0 are divided by the plurality of partition structures 21, without the need of a high-cost fine metal mask (FMM), so that the cost can be reduced and the display substrate of large size can be prepared. The cost of an open mask is lower than that of the fine metal mask (FMM), and the pixel-level light emitting units are prepared by the open mask and the partition structures 21, so that the cost of preparing the display substrate can be greatly reduced, and in addition, the open mask is used to prepare the light emitting device layer P0, which can be applied to the display substrate of large size.

[0101] In an example embodiment, in a direction Z perpendicular to a plane where the display substrate is located, the light emitting device layer P0 can include a plurality of light emitting device sub-layers (for example, the plurality of light emitting device sub-layers can include P01, P02, P03), the light emitting unit P can include a plurality of light emitting devices (for example, the plurality of light emitting devices can include P11, P12, P13), in the same light emitting unit P, different light emitting devices can be located in different light emitting device sub-layers (for example, in the same light emitting unit P, a first light emitting device P11, a second light emitting device P12, and a third light emitting device P13 can be included, the first light emitting device P11 can be located in the first light emitting device sub-layer P01, the second light emitting device P12 can be located in the second light emitting device sub-layer P02, and the third light emitting device P13 can be located in the third light emitting device sub-layer P03); in a direction pointing to the light emitting device layer P0 along the pixel definition layer PDL, the light emitting device sub-layers can sequentially include a first electrode layer 110, a light emitting structure layer EL0, and a second electrode layer 120, in two adjacent light emitting device sub-layers, the second electrode layer 120 of one of the light emitting device sub-layers can be reused as the first electrode layer 110 of the other light emitting device sub-layer;

[0102] The partition structure 21 can include a plurality of lapping sub-structures (for example, the plurality of lapping sub-structures can include 211, 212, 213), in the partition structure 21 corresponding to the same pixel opening K1, the plurality of lapping sub-structures correspond to the plurality of light emitting device sub-layers one by one, and the lapping sub-structures are arranged to be lappingly connected with the second electrode layer 120 in the corresponding light emitting device sub-layer.

[0103] In an example embodiment, in the same partition structure 21, the plurality of lapping sub-structures are arranged as a closed structure surrounding the corresponding pixel opening K1; in the plane where the display substrate is located (in the plane where the first direction X and the second direction Y are located, the first direction X intersects the second direction Y), in the direction pointing to the corresponding partition structure 21 along the pixel opening K1, in the partition structure 21 corresponding to the same pixel opening K1, the plurality of lapping sub-structures are sequentially and spaced arranged, and the surface of the plurality of lapping sub-structures away from the pixel definition layer PDL side increases in height relative to the surface of the pixel definition layer PDL side close to the light emitting device layer P0, sequentially dividing the plurality of light emitting device sub-layers into a plurality of light emitting devices corresponding to the pixel opening K1. For example, the first light emitting device sub-layer P01 can be divided by the first lapping sub-structure 211 to form the first light emitting device P11, the second light emitting device sub-layer P02 can be divided by the second lapping sub-structure 212 to form the second light emitting device P12, and the third light emitting device sub-layer P03 can be divided by the third lapping sub-structure 213 to form the third light emitting device P13.

[0104] In an example embodiment, the number of light emitting device sub-layers is not limited to three, for example, the number of light emitting device sub-layers can be more than three, or less than three. In an example embodiment, in the partition structure 21 corresponding to the same pixel opening, the number of lap sub-structures is not limited to three, for example, the number of lap sub-structures can be more than three, or less than three. In an example embodiment, the number of light emitting device sub-layers can be the same as the number of lap sub-structures in the same partition structure 21, and each lap sub-structure in the partition structure 21 corresponds to one light emitting device sub-layer.

[0105] In an example embodiment, in the partition structure 21 corresponding to the same pixel opening K1, the plurality of lap sub-structures are sequentially connected to the plurality of second electrode layers 120 along the direction of the pixel definition layer PDL pointing to the light emitting device layer P0 in the plane of the display substrate;

[0106] In the direction Z perpendicular to the plane of the display substrate, the lap sub-structure can be configured to at least disconnect the film layer structure between the second electrode layer 120 and the pixel definition layer PDL in the light emitting device layer P0 to which it is connected. For example, the first lap sub-structure 121 can disconnect the light emitting structure layer EL0 and the second electrode layer 120 in the first light emitting device sub-layer P01 to form the corresponding first light emitting device P11; the second lap sub-structure 122 can disconnect the light emitting structure layer EL0, the second electrode layer 120 and the second light emitting device sub-layer P02 in the first light emitting device sub-layer P01 to form the corresponding second light emitting device P12; the third lap sub-structure 123 can disconnect the light emitting structure layer EL0, the second electrode layer 120 and the second light emitting device sub-layer P02, the third light emitting device sub-layer P03 in the first light emitting device sub-layer P01 to form the corresponding third light emitting device P13.

[0107] In an example embodiment, in the structure shown in FIGS. 3 to 5, along the direction of the pixel definition layer PDL pointing to the light emitting device layer P0, the light emitting device can include a first electrode 11, a light emitting structure EL, and a second electrode 12 sequentially stacked, and in the same light emitting unit P, the second electrode 12 of one of the two adjacent light emitting devices can be reused as the first electrode 11 of the other light emitting device;

[0108] In at least part of the light emitting devices of the same light emitting unit P, the first electrode 11, the light emitting structure EL, and the second electrode 12 are sequentially disconnected from the first electrode layer 110, the light emitting structure layer EL0, and the second electrode layer 120 in the corresponding light emitting device sublayer by the corresponding lap joint substructure. For example, the first electrode 11 can be disconnected from the first electrode layer 110 in the corresponding light emitting device sublayer by the corresponding lap joint substructure, the second electrode 12 can be disconnected from the second electrode layer 120 in the corresponding light emitting device sublayer by the corresponding lap joint substructure, and the light emitting structure EL0 can be disconnected from the light emitting structure layer EL0 in the corresponding light emitting device sublayer by the corresponding lap joint substructure.

[0109] In the example embodiment, as shown in FIGS. 6-8, FIG. 6 shows a schematic diagram of a planar structure of a display substrate, FIG. 7a shows a schematic diagram of a cross-sectional structure at position B1-B1 in FIG. 6, FIG. 7b shows a schematic diagram of a cross-sectional structure at position B11-B11 in FIG. 6, and FIG. 8 shows a schematic diagram of a cross-sectional structure at position B2 in FIG. 6. The partition structure 21 can further include a first isolation structure 31. In a direction perpendicular to the plane of the display substrate, the first isolation structure 31 can be located on a side of the pixel definition layer PDL close to the light emitting device layer P0. In the partition structure 21 corresponding to the same pixel opening K1, the first isolation structure 31 is arranged as a closed structure surrounding the corresponding pixel opening K1. In the direction in which the closed structure surrounded by the first isolation structure 31 extends, the plurality of lap joint substructures are arranged at intervals by the first isolation structure 31. In the example embodiment, in the direction perpendicular to the plane of the display substrate, the height of the surface of the first isolation structure 31 away from the pixel definition layer PDL relative to the pixel definition layer PDL is greater than the height of the surface of the light emitting device layer P0 away from the pixel definition layer PDL relative to the pixel definition layer PDL, which can ensure that the first isolation structure 31 divides the light emitting device into independent light emitting units P and avoids crosstalk between adjacent two light emitting units.

[0110] In the example embodiment, in the structure shown in FIGS. 6-8, the plurality of lap joint substructures in the same partition structure 21 are located in the same closed ring structure, and the spacing KD between adjacent two pixel openings K1 can be greatly reduced, which can improve the aperture ratio or the pixel density.

[0111] In the example embodiment, as shown in FIGS. 9-13, FIGS. 9 and 10 are schematic diagrams of planar structures of two display substrates, FIG. 11 is a schematic diagram of a cross-sectional structure of a B3 position in FIGS. 9 and 10, FIG. 12 is a schematic diagram of a cross-sectional structure of an A2-A2 position in FIG. 9, and FIG. 13 is a schematic diagram of a cross-sectional structure of a B4-B4 position in FIG. 10. The partition structure 21 can further include a second isolation structure 32. The second isolation structure 32 is arranged in a closed structure around a corresponding pixel opening K1, and divides the light-emitting device layer P0 into a plurality of light-emitting units P. In the partition structure 21 corresponding to the same pixel opening K1, the plurality of overlapping substructures are located between the corresponding pixel opening K1 and the second isolation structure 32.

[0112] In a direction Z perpendicular to the plane of the display substrate, the second isolation structure 32 is arranged on a side of the pixel definition layer PDL close to the light-emitting device layer P0. The thickness Z1 of the second isolation structure 32 is greater than the thickness Z2 of the light-emitting device layer P0, and penetrates the light-emitting device layer P0 to divide the second electrode layer 120 farthest from the pixel definition layer PDL. The light-emitting device sublayer farthest from the pixel definition layer PDL can be flexibly controlled to emit light, improving the flexibility of light-emitting control.

[0113] In the example embodiment, as shown in FIGS. 9 and 10, the second isolation structures 32 corresponding to the plurality of pixel openings K1 are connected to each other to form a grid-like structure.

[0114] In the example embodiment, in the same light-emitting unit P, the materials of the light-emitting structures of at least two light-emitting devices are different. The light-emitting unit can be lit by time-sharing control of the light-emitting of different light-emitting devices to realize display of different colors. Different materials in the light-emitting structure can emit light of different colors when lit.

[0115] In the example embodiment, the display substrate can further include a back plate BP and an anode layer AN0. In a direction Z perpendicular to the plane of the display substrate, the back plate BP can be located on a side of the pixel definition layer PDL away from the light-emitting device layer P0, and the anode layer AN0 can be located between the back plate BP and the pixel definition layer PDL. The anode layer AN0 can include a plurality of anodes AN. At least part of the anodes AN correspond one-to-one to at least part of the pixel openings K1 and at least part of the light-emitting units P. The orthographic projection of the pixel opening K1 on the back plate BP is located within the orthographic projection of the corresponding anode AN on the back plate BP.

[0116] In the anode AN and the light-emitting unit P corresponding to the same pixel opening K1, the anode AN can be reused as the first electrode 11 of the light-emitting device closest to the back plate BP in the light-emitting unit P.

[0117] In an exemplary embodiment, a plurality of electrode traces 10 can be provided in the back plate BP, at least part of the electrode traces 10 are electrically connected to at least part of the lapping substructures one by one, in the direction Z perpendicular to the plane where the display substrate is located, the lapping substructure can be provided to be electrically connected to the corresponding electrode trace 10 at one end, and to be lapping connected to the corresponding second electrode layer 120 through the pixel definition layer PDL at the other end (the lapping connection can be realized in a lapping manner).

[0118] In an exemplary embodiment, the plurality of light emitting device sublayers can include a first type of light emitting device sublayer and at least one second type of light emitting device sublayer, in the direction perpendicular to the plane where the display substrate is located, the second type of light emitting device sublayer can be located on the side of the first type of light emitting device sublayer (P01) away from the pixel definition layer PDL.

[0119] The plurality of lapping substructures corresponding to the same pixel opening K1 can include a first type of lapping substructure and at least one second type of lapping substructure, the first type of lapping substructure is lapping connected to the second electrode layer 12 in the first type of light emitting device sublayer, and the second type of lapping substructure is lapping connected to the second electrode 120 in the corresponding second type of light emitting device sublayer.

[0120] In an exemplary embodiment, in the structure shown in FIGS. 3 to 5, in the plane where the display substrate is located, along the direction of the pixel opening K1 pointing to the corresponding partition structure 21, the second type of lapping substructure can be located on the side of the first type of lapping substructure away from the corresponding pixel opening K1.

[0121] In an exemplary embodiment, as shown in FIGS. 14 to 16, FIG. 14 is an enlarged schematic view of a partial structure in FIG. 5, FIG. 15 is a structure schematic view after removing the light emitting device layer P0 in FIG. 14, and FIG. 16 is a structure schematic view after removing the light emitting device layer P0 in FIG. 13, in the direction Z perpendicular to the plane where the display substrate is located, the first type of lapping substructure can include a first region V1, the first region V1 can be located on the side of the pixel definition layer PDL close to the light emitting device layer P0, the surface of the first region V1 away from the pixel definition layer PDL has a height H1 relative to the pixel definition layer PDL, which is greater than or equal to the distance R1 between the surface of the first type of light emitting device sublayer away from the pixel definition layer PDL and the pixel definition layer PDL, and less than the distance L1 between the second electrode layer 120 in the second type of light emitting device closest to the first type of light emitting device sublayer and the pixel definition layer PDL.

[0122] The first type of lapping substructure can be lapping connected to the second electrode layer 120 in the first type of light emitting device sublayer through the first region V1.

[0123] In the exemplary embodiments, in the direction Z perpendicular to the plane where the display substrate is located, the second type of lapping substructure can include a first region V1 and a second region V2, the second region V2 is located between the first region V1 and the pixel definition layer PDL, in the same second type of lapping substructure, the height H of the surface of the first region V1 away from the pixel definition layer PDL relative to the pixel definition layer PDL is greater than or equal to the distance R between the surface of the corresponding second type of light emitting device sublayer away from the pixel definition layer PDL and the pixel definition layer PDL; the height W of the surface of the second region V2 away from the pixel definition layer PDL relative to the pixel definition layer PDL is greater than or equal to the distance J between the surface of the first electrode layer 110 in the corresponding second type of light emitting device sublayer away from the pixel definition layer PDL and the pixel definition layer PDL, and less than the distance L between the second electrode layer 120 in the corresponding second type of light emitting device sublayer and the pixel definition layer PDL.

[0124] In the second type of lapping substructure, the first region V1 is lapping connected with the second electrode layer 120 in the corresponding second type of light emitting device sublayer, and the surface of the second region V2 is provided with an insulating structure 22, the insulating structure 22 is configured to electrically insulate the second region V2 from the light emitting device layer P0, and the insulating structure 22 can avoid the corresponding lapping substructure from being electrically connected with the electrode layer other than the lapping second electrode layer 120.

[0125] In the exemplary embodiments, in the plane where the display substrate is located, in at least part of the second type of lapping substructure, the height H of the surface of the first region V1 away from the pixel definition layer PDL relative to the pixel definition layer PDL is less than the distance L between the second electrode layer 120 in the first type of adjacent light emitting device sublayer and the pixel definition layer PDL, and the first type of adjacent light emitting device sublayer is the light emitting device sublayer most adjacent to the corresponding second type of light emitting device sublayer and located on the side of the corresponding second type of light emitting device sublayer away from the pixel definition layer PDL, for example, the third light emitting device sublayer P03 is the light emitting device sublayer most adjacent to the second light emitting device sublayer P02.

[0126] In the exemplary embodiments, in the structures shown in FIGS. 3 to 5, in the plane where the display substrate is located, in the direction of the pixel opening K1 pointing to the corresponding partition structure 21, in the plurality of lapping substructures corresponding to the same pixel opening K1, in the second type of lapping substructure located in the middle position, the height H of the surface of the first region V1 away from the pixel definition layer PDL relative to the pixel definition layer PDL is less than the distance L between the second electrode layer 120 in the first type of adjacent light emitting device sublayer and the pixel definition layer PDL, and the first type of adjacent light emitting device sublayer is the light emitting device sublayer most adjacent to the corresponding second type of light emitting device sublayer and located on the side of the corresponding second type of light emitting device sublayer away from the pixel definition layer PDL.

[0127] In an example embodiment, the direction of the pixel definition layer PDL pointing to the light emitting device layer P0, the plurality of light emitting device sub-layers at least includes a first light emitting device sub-layer P01, a second light emitting device sub-layer P02, and a third light emitting device sub-layer P03, the first type of light emitting device sub-layer can include the first light emitting device sub-layer P01, and the second type of light emitting device sub-layer can include the second light emitting device sub-layer P02 and the third light emitting device sub-layer P03. The plurality of lap sub-structures can include a first lap sub-structure 211, a second lap sub-structure 212, and a third lap sub-structure 213, the first type of lap sub-structure can include the first lap sub-structure 211, and the second type of lap sub-structure can include the second lap sub-structure 212 and the third lap sub-structure 213; the first lap sub-structure 211 can be lap-connected with the first light emitting device sub-layer P01, the second lap sub-structure 212 can be lap-connected with the second light emitting device sub-layer P02, and the third lap sub-structure 213 can be lap-connected with the third light emitting device sub-layer P03.

[0128] In an example embodiment, in the structure shown in FIGS. 3-5, along the direction of the pixel opening K1 pointing to the corresponding partition structure 21, in the partition structure 21 corresponding to the same pixel opening K1, the plurality of lap sub-structures can include a first lap sub-structure 211, a second lap sub-structure 212, and a third lap sub-structure 213 in sequence, the first type of lap sub-structure can include the first lap sub-structure 211, and the second type of lap sub-structure can include the second lap sub-structure 212 and the third lap sub-structure 213.

[0129] In an example embodiment, in the structure shown in FIGS. 3-5, along the direction of the pixel definition layer PDL pointing to the light emitting device layer P0, in the same light emitting unit P, the plurality of light emitting devices can include a first light emitting device P11, a second light emitting device P12, and a third light emitting device P13 in sequence; the first light emitting device P11 can be formed by the corresponding first lap sub-structure 211 dividing the first light emitting device sub-layer P01, the second light emitting device P12 can be formed by the corresponding second lap sub-structure 212 dividing the second light emitting device sub-layer P02, and the third light emitting device P13 can be formed by the third lap sub-structure 213 dividing the third light emitting device sub-layer P03.

[0130] In the exemplary real-time manner, in the second lap joint substructure 212, the height H2 of the surface of the first region V1 away from the side of the pixel definition layer PDL relative to the pixel definition layer PDL is greater than or equal to the distance R2 between the surface of the second light emitting device sublayer P02 away from the side of the pixel definition layer PDL and the pixel definition layer PDL; the height W1 of the surface of the second region V2 away from the side of the pixel definition layer PDL relative to the pixel definition layer PDL is greater than or equal to the distance J1 between the surface of the first electrode layer 110 in the second light emitting device sublayer P02 away from the side of the pixel definition layer PDL and the pixel definition layer PDL, and less than the distance L2 between the second electrode layer 120 in the second light emitting device sublayer P02 and the pixel definition layer PDL.

[0131] In the exemplary real-time manner, in the third lap joint substructure 213, the height H3 of the surface of the first region V1 away from the side of the pixel definition layer PDL relative to the pixel definition layer PDL is greater than or equal to the distance R3 between the surface of the third light emitting device sublayer P03 away from the side of the pixel definition layer PDL and the pixel definition layer PDL; the height W2 of the surface of the second region V2 away from the side of the pixel definition layer PDL relative to the pixel definition layer PDL is greater than or equal to the distance J2 between the surface of the first electrode layer 110 in the third light emitting device sublayer P03 away from the side of the pixel definition layer PDL and the pixel definition layer PDL, and less than the distance L3 between the second electrode layer 120 in the third light emitting device sublayer P03 and the pixel definition layer PDL.

[0132] In the exemplary embodiment, the light emitted by the first light emitting device P11 can be red, the light emitted by the second light emitting device P12 can be green, and the light emitted by the third light emitting device P13 can be blue. Full-color display can be achieved by time-sharing control of the lighting of different light emitting devices in the light emitting unit P. The light emitting structure layer EL1 in the first light emitting device P11 can be a material that emits red light, the light emitting structure layer EL2 in the second light emitting device P12 can be a material that emits green light, and the light emitting structure layer EL3 in the third light emitting device P13 can be a material that emits blue light. The embodiments of the present disclosure are not limited to the first light emitting device P11 emitting red light, the second light emitting device P12 emitting green light, and the third light emitting device P13 emitting blue light. The actual situation can be set, for example, the second light emitting device P12 can emit red light, and the first light emitting device P11 can emit green light.

[0133] In the exemplary embodiments, the partition structure 21 adopts a ring-shaped closed structure, and the corresponding light-emitting structure layer and the electrode layer are cut off by controlling the height of the lapping sub-structure relative to the pixel definition layer PDL, and are connected to the corresponding second electrode layer 120, for example, in the structures shown in FIGS. 3-5: the light-emitting structure layer EL0 and the second electrode layer 120 in the first light-emitting device sub-layer P01 can be cut off by controlling the height H1 of the first lapping sub-junction 211 relative to the pixel definition layer PDL, and are connected to the second electrode layer 120 in the first light-emitting device sub-layer P01; the light-emitting structure layer EL0 and the second electrode layer 120 in the second light-emitting device sub-layer P02 can be cut off by controlling the height H2 of the second lapping sub-junction 212 relative to the pixel definition layer PDL, and are connected to the second electrode layer 120 in the second light-emitting device sub-layer P02; the light-emitting structure layer EL0 and the second electrode layer 120 in the third light-emitting device sub-layer P03 can be cut off by controlling the height H3 of the third lapping sub-junction 213 relative to the pixel definition layer PDL, and are connected to the third electrode layer 120 in the third light-emitting device sub-layer P03.

[0134] In the structures shown in FIGS. 12-13, the light-emitting device sub-layer farthest from the pixel definition layer PDL can be divided into multiple independent light-emitting devices by the second partition structure 32, and the flexibility of controlling the light-emitting of the light-emitting device sub-layer can be improved; in the structures shown in FIGS. 17-18, the light-emitting device layer P0 can be divided into multiple independent light-emitting units by the second partition structure 32, the flexibility of controlling the light-emitting of the light-emitting device sub-layer can be improved, and the crosstalk between the light-emitting units can be avoided.

[0135] In the exemplary embodiments, one end of the lapping sub-structure is electrically connected to the second electrode in the corresponding light-emitting device sub-layer, and the other end is electrically connected to the corresponding electrode trace 10, and the signal can be provided to the corresponding lapping sub-structure through the electrode trace 10, transmitted to the corresponding second electrode layer 120, so as to control the light-emitting of the corresponding light-emitting device sub-layer.

[0136] In the exemplary embodiments, in the direction Z perpendicular to the plane where the display substrate is located, the height H3 of the surface of the third lapping sub-structure 213 away from the pixel definition layer PDL relative to the pixel definition layer PDL has the following relationship with the thickness of the film layer in the light-emitting device layer P0: M1+C1+M2+C2+M3+C3<H3.

[0137] In the direction Z perpendicular to the plane where the display substrate is located, M1 is the thickness of the light-emitting structure layer E10 in the first light-emitting device sublayer P01, M2 is the thickness of the light-emitting structure layer E10 in the second light-emitting device sublayer P02, M3 is the thickness of the light-emitting structure layer E10 in the third light-emitting device sublayer P03, C1 is the thickness of the second electrode 12 in the first light-emitting device sublayer P01, C2 is the thickness of the second electrode 12 in the second light-emitting device sublayer P02, C3 is the thickness of the second electrode 12 in the third light-emitting device sublayer P03, and H3 is the height of the surface of the third lap joint substructure 213 away from the pixel definition layer PDL relative to the pixel definition layer PDL.

[0138] In the exemplary embodiment, in the direction Z perpendicular to the plane where the display substrate is located, the height H2 of the surface of the second lap joint substructure 212 away from the pixel definition layer PDL relative to the pixel definition layer PDL has the following relationship with the thicknesses of the film layers in the light-emitting device layer P0: M1+C1+M2+C2

[0139] In the direction perpendicular to the plane where the display substrate is located, H2 is the height of the surface of the second lap joint substructure 212 away from the pixel definition layer PDL relative to the pixel definition layer PDL.

[0140] In the exemplary embodiment, in the direction Z perpendicular to the plane where the display substrate is located, the height H1 of the surface of the first lap joint substructure 211 away from the pixel definition layer PDL relative to the pixel definition layer PDL has the following relationship with the thicknesses of the film layers in the light-emitting device layer P0: M1+C1

[0141] In the direction Z perpendicular to the plane where the display substrate is located, H1 is the height of the surface of the first lap joint substructure 211 away from the pixel definition layer PDL relative to the pixel definition layer PDL.

[0142] In the exemplary embodiment, in the direction Z perpendicular to the plane where the display substrate is located, the height W1 of the surface of the second region V2 in the second lap joint substructure 212 away from the pixel definition layer PDL relative to the pixel definition layer PDL has the following relationship with the thicknesses of the film layers in the light-emitting device layer P0: M1+C1+(1 / 2)M2

[0143] In the direction perpendicular to the plane where the display substrate is located, W1 is the height of the surface of the second region V2 in the second lap joint substructure 212 away from the pixel definition layer PDL relative to the pixel definition layer PDL.

[0144] In the exemplary embodiments, in the direction Z perpendicular to the plane where the display substrate is located, the height of the surface of the second region V2 in the third sub-lap structure 213 away from the side of the pixel definition layer PDL relative to the pixel definition layer PDL is related to the thickness of the film layer in the light-emitting device layer P0 as follows: M1+C1+M2+C2+(1 / 2)M3<W2<M1+C1+M2+C2+M3.

[0145] In the direction Z perpendicular to the plane where the display substrate is located, W2 is the height of the surface of the second region V2 in the third sub-lap structure 213 away from the side of the pixel definition layer PDL relative to the pixel definition layer PDL.

[0146] In the exemplary embodiments, as shown in FIGS. 11-13, the partition structure 21 can further include a first cut-off structure 24, which can be located on the side of the second isolation structure 32 away from the pixel definition layer PDL in the direction Z perpendicular to the plane where the display substrate is located; and the size of the first cut-off structure 24 is greater than the size of the corresponding second isolation structure 32 in the direction of the pixel opening pointing to the corresponding partition structure. In the exemplary embodiments, as shown in the structures of FIGS. 3-5, 12 and 14, the partition structure 21 can further include a plurality of second cut-off structures 23, which are arranged in sequence and correspond to a plurality of sub-lap structures in the direction of the pixel opening K1 pointing to the corresponding partition structure 21 in the plane where the display substrate is located, and the size of the second cut-off structure 23 is greater than the size of the corresponding sub-lap structure.

[0147] In the direction Z perpendicular to the plane where the display substrate is located, the second cut-off structure 23 is located on the side of the corresponding sub-lap structure away from the pixel definition layer PDL.

[0148] In the exemplary embodiments, in the cross-sectional structure in the direction of the pixel opening K1 pointing to the corresponding partition structure 21 (for example, the cross-sectional structure along the position of the A1-A1 dashed line in FIG. 3), the second cut-off structure 23 and the corresponding sub-lap structure form a T-shaped cross-section.

[0149] In the exemplary embodiments, in the direction Z perpendicular to the plane where the display substrate is located, the height H0 of the surface of the second cut-off structure 23 away from the pixel definition layer PDL relative to the pixel definition layer PDL is greater than the distance between the surface of the corresponding light emitting device sub-layer away from the pixel definition layer PDL and the pixel definition layer PDL, and is less than the distance between the surface of the second electrode layer 120 in the first type of adjacent light emitting device sub-layer away from the pixel definition layer PDL and the pixel definition layer PDL, the first type of adjacent light emitting device sub-layer being the light emitting device sub-layer most adjacent to the corresponding light emitting device sub-layer and located on the side of the corresponding second type of light emitting device sub-layer away from the pixel definition layer PDL. For example, the height H01 of the surface of the second cut-off structure 23 corresponding to the first sub-lap structure 211 away from the pixel definition layer PDL relative to the pixel definition layer PDL is greater than the distance R1 between the surface of the first light emitting device sub-layer P01 away from the pixel definition layer PDL and the pixel definition layer PDL, and is less than the distance R2 between the surface of the second electrode layer 120 in the second light emitting device sub-layer P02 away from the pixel definition layer PDL and the pixel definition layer PDL; the height H02 of the surface of the second cut-off structure 23 corresponding to the second sub-lap structure 212 away from the pixel definition layer PDL relative to the pixel definition layer PDL is greater than the distance R2 between the surface of the second light emitting device sub-layer P02 away from the pixel definition layer PDL and the pixel definition layer PDL, and is less than the distance R3 between the surface of the second electrode layer 120 in the third light emitting device sub-layer P03 away from the pixel definition layer PDL and the pixel definition layer PDL; the height H03 of the surface of the second cut-off structure 23 corresponding to the third sub-lap structure 213 away from the pixel definition layer PDL relative to the pixel definition layer PDL is greater than the distance R3 between the surface of the third light emitting device sub-layer P03 away from the pixel definition layer PDL and the pixel definition layer PDL.

[0150] In the example embodiment, the size a1 of the second cutting structure 23 is larger than the size a2 of the corresponding bridging substructure, and the second cutting structure 23 is located between the surface of the second electrode layer 120 away from the pixel definition layer and the first electrode layer 110 in the corresponding light emitting device sublayer, which can well cut the film layers in the light emitting device layer P0. For example, the second cutting structure 23 corresponding to the first bridging substructure 211 is located between the surface of the second electrode layer 120 away from the pixel definition layer and the first electrode layer 110 in the first light emitting device sublayer P01, which can well cut the first electrode layer 110 and the light emitting structure layer EL0 in the first light emitting device sublayer P01, and can effectively divide the first light emitting device sublayer P01 into independent first light emitting devices P11, avoiding crosstalk of the first light emitting devices P11 in different light emitting units P; the second cutting structure 23 corresponding to the second bridging substructure 212 is located between the surface of the second electrode layer 120 away from the pixel definition layer and the first electrode layer 110 in the second light emitting device sublayer P02, which can well cut the first electrode layer 110 and the light emitting structure layer EL0 in the second light emitting device sublayer P02, and can effectively divide the second light emitting device sublayer P02 into independent second light emitting devices P12, avoiding crosstalk of the second light emitting devices P12 in different light emitting units P; the second cutting structure 23 corresponding to the third bridging substructure 213 is located between the surface of the second electrode layer 120 away from the pixel definition layer and the first electrode layer 110 in the third light emitting device sublayer P03, which can well cut the first electrode layer 110 and the light emitting structure layer EL0 in the third light emitting device sublayer P03, and can effectively divide the third light emitting device sublayer P03 into independent third light emitting devices P13, avoiding crosstalk of the third light emitting devices P13 in different light emitting units P.

[0151] In the example embodiment, as shown in FIG. 15, in the plane of the display substrate, along the direction in which the pixel opening K1 points to the corresponding blocking structure 21, on the same side of the center of the second cutting structure 23, the difference a21 between the size of the second cutting structure 23 and the size of the corresponding bridging substructure can be 0.1 microns to 0.6 microns, for example, the value of a21 can be 0.1 microns to 0.5 microns; in the direction Z perpendicular to the plane of the display substrate, the size a3 of the second cutting structure 23 is 2 nanometers to 25 nanometers, for example, the value of a3 can be 5 nanometers to 20 nanometers.

[0152] In an example embodiment, as shown in FIG. 15, in the plane where the display substrate is located, along the direction of the pixel opening K1 pointing to the corresponding partition structure 21, in the partition structure 21 corresponding to the same pixel opening K1, the distance a4 between the two adjacent sub-lap structures is 3-13 microns, the size a1 of the sub-lap structure is 3-13 microns, and the size a2 of the second cut structure 23 is 2*a21+a1. For example, the value of a4 can be 5-10 microns, and the value of a1 can be 5-10 microns.

[0153] In an example embodiment, as shown in FIGS. 7a-8, 13, and 16, the partition structure 21 can further include a third cut structure 25. In the partition structure corresponding to the same pixel opening, along the direction of the pixel opening pointing to the corresponding partition structure, the size of the third cut structure 25 is greater than the size of the corresponding sub-lap structure. In the direction Z perpendicular to the plane where the display substrate is located, the third cut structure 25 can be located on the side of the corresponding first isolation structure 31 away from the pixel definition layer PDL, which can better divide the light-emitting device layer P0 to form multiple independent light-emitting units P, thereby avoiding crosstalk between adjacent pixel units P. In an example embodiment, in the plane where the display substrate is located, along the direction of the pixel opening K1 pointing to the corresponding partition structure 21, on the same side of the center of the third cut structure 25, the difference a65 between the size of the third cut structure 25 and the size of the corresponding sub-lap structure can be 0.1-0.6 microns. For example, the value of a65 can be 0.1-0.5 microns. In the direction Z perpendicular to the plane where the display substrate is located, the size a7 of the third cut structure 25 is 2-25 nanometers, for example, the value of a7 can be 5-20 nanometers. In the partition structure corresponding to the same pixel opening, along the direction of the pixel opening pointing to the corresponding partition structure, the size of the first isolation structure 31 can be consistent with the size of the corresponding sub-lap structure, which can both be a5. The value of a5 can be 3-13 microns, and the size a6 of the third cut structure 25 is 2*a65+a5. For example, the value of a5 can be 5-10 microns.

[0154] In an example embodiment, as shown in FIG. 16, in the plane where the display substrate is located, along the direction of the pixel opening K1 pointing to the corresponding partition structure 21, on the same side of the center of the first cut structure 24, the difference b21 between the size of the first cut structure 24 and the size of the second isolation structure 32 can be 0.1-0.6 microns, for example, the value of b21 can be 0.1-0.5 microns. In the direction Z perpendicular to the plane where the display substrate is located, the size b3 of the first cut structure 24 is 2-25 nanometers, for example, the value of b3 can be 5-20 nanometers.

[0155] In the example embodiment, the size b1 of the second isolation structure 32 is 3-13 microns in the direction of the pixel opening pointing to the corresponding partition structure, and the size b2 of the first cut-off structure 24 is 2*b21+b1, for example, the value of b1 can be 5-10 microns.

[0156] In the example embodiment, the thickness dimension (M1, M2, M3) of the light-emitting structure layer EL0 in the direction Z perpendicular to the plane of the display substrate can be 2000-4000 angstroms, the thickness dimension (C1, C2) of the first electrode layer 110 can be 8-55 nanometers, the thickness dimension (C1, C2, C3) of the second electrode layer 120 can be 8-55 nanometers, and the thickness dimension L0 of the pixel definition layer PDL can be 0.5-3 microns. For example, the value of M1, M2, M3 can be 2500-3500 angstroms, the value of C1, C2, C3 can be 10-50 nanometers, and the value of L0 can be 1-2 microns. The value of M1, M2, M3 is 2500-3500 angstroms, which can reduce the short circuit between adjacent two electrodes in the direction Z perpendicular to the plane of the display substrate.

[0157] In the example embodiment, the material of the first electrode layer 110 and the second electrode layer 120 can be metal, the thickness dimension of the first electrode layer 110 in the direction Z perpendicular to the plane of the display substrate can be 8-25 nanometers, and the thickness dimension of the second electrode layer 120 can be 8-25 nanometers; in the example embodiment, the material of the first electrode layer 110 and the second electrode layer 120 can be metal with good conductivity, for example, copper or aluminum, the thickness dimension of the first electrode layer 110 can be 10-20 nanometers, and the thickness dimension of the second electrode layer 120 can be 10-20 nanometers. In the example embodiment, the first electrode layer 110 and the second electrode layer 120 except the anode layer AN0 can be a semi-transparent and semi-reflective metal electrode, for example, aluminum Al, magnesium Mg, silver Ag, and the thickness of the first electrode layer 110 and the second electrode layer 120 is 10-20 nanometers, which can avoid the influence of the large thickness of the electrode layer on the light transmittance. The thickness of the anode layer AN0 can not be considered for light transmittance.

[0158] In an example embodiment, the material of the first electrode layer 110 and the second electrode layer 120 can be a semiconductor oxide (for example, indium zinc oxide IZO), the thickness of the first electrode layer 110 in the direction Z perpendicular to the plane of the display substrate can be 8-55 nm, and the thickness of the second electrode layer 120 in the direction Z perpendicular to the plane of the display substrate can be 8-55 nm. For example, the thickness of the first electrode layer 110 in the direction Z perpendicular to the plane of the display substrate can be 10-50 nm, and the thickness of the second electrode layer 120 in the direction Z perpendicular to the plane of the display substrate can be 10-50 nm. The anode layer AN0 does not need to have high light transmittance, and a thicker metal can be used. The thickness of the electrode layer other than the anode layer AN0 can use a semiconductor oxide with higher transparency to provide light transmittance.

[0159] In an example embodiment, as shown in FIG. 17, which is a schematic view of another A2-A2 position cross-sectional structure of FIG. 9, the second isolation structure 32 and the first cut-off structure 24 are provided, and the second cut-off structure 23 can not be provided on the side of the lap sub-structure away from the pixel definition layer (different from FIG. 12 in that the second cut-off structure 23 is not provided).

[0160] In an example embodiment, as shown in FIG. 18, which is a schematic view of another B4-B4 position cross-sectional structure of FIG. 10, the second isolation structure 32 and the first cut-off structure 24 are provided, and the third cut-off structure 25 can not be provided on the side of the lap sub-structure away from the pixel definition layer (different from FIG. 13 in that the third cut-off structure 25 is not provided).

[0161] In an example embodiment, the first cut-off structure 24, the second cut-off structure 23, the third cut-off structure 25, the first isolation structure 31, and the second isolation structure 32 can be made of an insulating material.

[0162] In an example embodiment, the preparation process of the display substrate shown in FIG. 5 can include the following operations.

[0163] (101) Forming a back plate.

[0164] In an example embodiment, the back plate BP can be provided with a pixel driving circuit for driving the light emitting unit, and an electrode trace 10 for providing a signal to the corresponding electrode in the light emitting unit P0.

[0165] (102) Forming an anode layer and a pixel definition layer on one side of the back plate.

[0166] In an example embodiment, as shown in FIG. 19a, an anode layer AN0 is formed on one side of the backplane, a pixel definition layer is formed on the side of the anode layer AN0 away from the backplane BP, the anode layer AN0 can include a plurality of anodes AN, the pixel definition layer PDL is provided with a plurality of pixel openings K1, the plurality of anodes AN correspond to the plurality of pixel openings K1 one-to-one, and the orthographic projection of the pixel opening K1 on the backplane BP at least partially overlaps the orthographic projection of the corresponding anode AN on the backplane BP, for example, the orthographic projection of the pixel opening K1 on the backplane BP can be located within the range of the orthographic projection of the corresponding anode AN on the backplane BP.

[0167] (103) Forming a lapping via on the side of the pixel definition layer away from the backplane.

[0168] In an example embodiment, forming a lapping via on the side of the pixel definition layer away from the backplane can include: depositing (which can be in the form of coating) a first insulating layer film on the side of the pixel definition layer PDL away from the backplane BP, and patterning the first insulating layer film by a photolithography process to form a first insulating layer 40, as shown in FIG. 19b, the first insulating layer can include a plurality of lapping vias VM, the lapping vias penetrating through the first insulating layer and the pixel definition layer, the plurality of lapping vias VM can correspond to the plurality of electrode traces 10 one-to-one, and the orthographic projection of the lapping via VM on the backplane at least partially overlaps the orthographic projection of the corresponding electrode trace 10 on the backplane BP.

[0169] (104) Forming a lapping substructure on the side of the first insulating layer away from the backplane.

[0170] In an example embodiment, forming a lapping substructure on the side of the first insulating layer away from the backplane can include: forming a lapping electrode pillar 210 by a sputtering process, as shown in FIG. 19c, and forming a first lapping substructure 211, a second lapping substructure 212, and a third lapping substructure 213 by a patterning process, as shown in FIG. 19d.

[0171] (105) Forming a second cut-off structure.

[0172] In an example embodiment, forming a second cut-off structure can include: depositing a second insulating layer film 50 on the backplane with the above-mentioned pattern, as shown in FIG. 19e, and patterning the second insulating layer film by a photolithography process to form a plurality of second cut-off structures 23, the plurality of second cut-off structures 23 corresponding to the plurality of lapping substructures one-to-one, and the second cut-off structure 23 is located on the side of the corresponding lapping substructure away from the backplane in the direction perpendicular to the plane in which the backplane is located.

[0173] (106) Forming a light-emitting device layer.

[0174] In the example embodiment, forming the light-emitting device layer P0 can include: sequentially depositing a plurality of film layers in the light-emitting device layer P0 on the back plate formed with the above-mentioned pattern through an open mask to form a structure as shown in FIG. 5.

[0175] In the example embodiment, the preparation method provided by the present disclosure is not limited to the above-mentioned steps (101) to (106). For example, a structure as shown in FIG. 20 can be formed by a process different from the above-mentioned steps (101) to (106), and the insulating structure 22 can extend into the pixel definition layer PDL.

[0176] The present disclosure provides a display device, as shown in FIG. 21, which can include the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, a wearable device, an AR or VR display device, a vehicle-mounted display device, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., and the present disclosure is not limited thereto.

[0177] The present disclosure provides a preparation method of a display substrate, which can include:

[0178] forming a pixel definition layer on one side of the back plate, the pixel definition layer being provided with a plurality of pixel openings;

[0179] forming a plurality of partition structures on the side of the pixel definition layer away from the back plate, at least part of the partition structures corresponding to at least part of the pixel openings one by one, the partition structures being arranged as closed structures surrounding the corresponding pixel openings;

[0180] forming a light-emitting device layer on the side of the partition structure away from the back plate, the light-emitting device layer including a plurality of light-emitting units divided by the plurality of partition structures in the plane of the display substrate, at least part of the light-emitting units corresponding to at least part of the pixel openings one by one, at least part of the light-emitting units being located in the corresponding pixel openings.

[0181] The display substrate provided by the present disclosure and the preparation method and the display device thereof include a pixel definition layer and a light-emitting device layer stacked thereon, the pixel definition layer is provided with a plurality of pixel openings and a plurality of partition structures, at least part of the partition structures corresponding to at least part of the pixel openings one by one, the partition structures being arranged as closed structures surrounding the corresponding pixel openings, and the light-emitting device layer includes a plurality of light-emitting units divided by the plurality of partition structures. In the scheme provided by the present disclosure, the plurality of light-emitting units in the light-emitting device layer are divided by the plurality of partition structures, which can reduce the high cost of preparing the display substrate, enable the preparation of large-size display products, and overcome the technical problems of high cost of preparing the display substrate by using a fine metal mask and difficulty in applying to large-size display products.

[0182] The following needs to be explained:

[0183] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0184] In the case of no conflict, the features in the embodiments of the present disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments.

[0185] Although the embodiments disclosed by the present disclosure are as above, the content described is only the embodiments adopted for the convenience of understanding the present disclosure, and is not used to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure. The patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, comprising a pixel definition layer and a light-emitting device layer stacked thereon, wherein the pixel definition layer is provided with a plurality of pixel openings and a plurality of partition structures, at least some of the partition structures correspond one-to-one with at least some of the pixel openings, and the partition structures are configured as closed structures surrounding the corresponding pixel openings. In the plane of the display substrate, the light-emitting device layer includes a plurality of light-emitting units formed by the plurality of partition structures, at least some of the light-emitting units correspond one-to-one with at least some of the pixel openings, and at least a portion of the light-emitting units are located in the corresponding pixel openings.

2. The display substrate according to claim 1, wherein, In a direction perpendicular to the plane of the display substrate, the light-emitting device layer includes multiple light-emitting device sub-layers, and the light-emitting unit includes multiple light-emitting devices. In the same light-emitting unit, different light-emitting devices are located in different light-emitting device sub-layers. In the direction from the pixel definition layer to the light-emitting device layer, the light-emitting device sub-layer sequentially includes a first electrode layer, a light-emitting structure layer, and a second electrode layer. In two adjacent light-emitting device sub-layers, the second electrode layer of one light-emitting device sub-layer is reused as the first electrode layer of the other light-emitting device sub-layer. The partition structure includes at least a plurality of overlapping substructures. In the partition structure corresponding to the same pixel opening, the plurality of overlapping substructures correspond one-to-one with the plurality of light-emitting device sublayers. The overlapping substructure is configured to overlap and connect with the second electrode layer in the corresponding light-emitting device sublayer.

3. The display substrate according to claim 2, wherein, In the same partition structure, the plurality of overlapping substructures are configured as closed structures surrounding the corresponding pixel openings; in the plane where the display substrate is located, along the direction from the pixel opening to the corresponding partition structure, in the partition structure corresponding to the same pixel opening, the plurality of overlapping substructures are arranged sequentially at intervals, and the height of the surface of the plurality of overlapping substructures away from the pixel definition layer increases sequentially relative to the surface of the pixel definition layer near the light-emitting device layer, thereby sequentially dividing the plurality of light-emitting device sublayers into a plurality of light-emitting devices corresponding to the pixel opening.

4. The display substrate according to claim 3, wherein, In the plane where the display substrate is located, along the direction from the pixel opening to the corresponding partition structure, in the partition structure corresponding to the same pixel opening, the plurality of overlapping substructures are sequentially overlapped and connected to the plurality of second electrode layers along the direction from the pixel definition layer to the light-emitting device layer; In a direction perpendicular to the plane of the display substrate, the overlapping substructure is configured to at least disconnect the film layer structure between the second electrode layer, which overlaps with the light-emitting device layer, and the pixel definition layer.

5. The display substrate according to claim 2, wherein, The partition structure further includes a first isolation structure. In a direction perpendicular to the plane of the display substrate, the first isolation structure is located on the side of the pixel definition layer closer to the light-emitting device layer. In the partition structure corresponding to the same pixel opening, the first isolation structure is configured as a closed structure surrounding the corresponding pixel opening. In the direction surrounded by the closed structure containing the first isolation structure, the plurality of overlapping substructures are spaced apart by the first isolation structure. In a direction perpendicular to the plane of the display substrate, the height of the surface of the first isolation structure away from the pixel definition layer relative to the pixel definition layer is greater than the height of the surface of the light-emitting device layer away from the pixel definition layer relative to the pixel definition layer.

6. The display substrate according to any one of claims 2 to 5, wherein, The partition structure further includes a second partition structure, which is configured as a closed structure surrounding the corresponding pixel opening, dividing the light-emitting device layer into multiple light-emitting units. Along the direction from the pixel opening to the partition structure, in the partition structure corresponding to the same pixel opening, the multiple overlapping substructures are located between the corresponding pixel opening and the second partition structure. In a direction perpendicular to the plane of the display substrate, the second isolation structure is disposed on the side of the pixel definition layer near the light-emitting device layer. The thickness of the second isolation structure is greater than the thickness of the light-emitting device layer and penetrates the light-emitting device layer.

7. The display substrate according to claim 6, wherein, The second isolation structures corresponding to the plurality of pixel openings are interconnected to form a mesh structure.

8. The display substrate according to claim 6, wherein, The partition structure further includes a first cutting structure, which is located on the side of the second isolation structure away from the pixel definition layer in a direction perpendicular to the plane of the display substrate; the size of the first cutting structure is larger than the size of the corresponding second isolation structure in the direction from the pixel opening to the corresponding partition structure.

9. The display substrate according to any one of claims 2 to 5, wherein, The plurality of light-emitting device sublayers include a first type of light-emitting device sublayer and at least one second type of light-emitting device sublayer. In a direction perpendicular to the plane where the display substrate is located, the second type of light-emitting device sublayer is located on the side of the first type of light-emitting device sublayer away from the pixel definition layer. Among the multiple overlapping substructures corresponding to the same pixel opening, there is a first type of overlapping substructure and at least one second type of overlapping substructure. The first type of overlapping substructure is overlapped with the second electrode layer in the first type of light-emitting device sublayer, and the second type of overlapping substructure is overlapped with the second electrode in the corresponding second type of light-emitting device sublayer.

10. The display substrate according to claim 9, wherein, In a direction perpendicular to the plane of the display substrate, the first type of overlapping substructure includes a first region. The first region is located on the side of the pixel definition layer closest to the light-emitting device layer. The height of the surface of the first region away from the pixel definition layer relative to the pixel definition layer is greater than or equal to the distance between the surface of the first type of light-emitting device sublayer away from the pixel definition layer and the pixel definition layer, and less than the distance between the second electrode layer of the second type of light-emitting device that is closest to the first type of light-emitting device sublayer and the pixel definition layer. The first type of overlapping substructure is connected to the second electrode layer in the first type of light-emitting device sublayer through the first region.

11. The display substrate according to claim 10, wherein, In a direction perpendicular to the plane of the display substrate, the second type of overlap substructure includes a first region and a second region. The second region is located between the first region and the pixel definition layer. In the same second type of overlap substructure, the height of the surface of the first region away from the pixel definition layer relative to the pixel definition layer is greater than or equal to the distance between the surface of the corresponding second type of light-emitting device sublayer away from the pixel definition layer and the pixel definition layer. The height of the surface of the second region away from the pixel definition layer relative to the pixel definition layer is greater than or equal to the distance between the surface of the first electrode layer in the corresponding second type of light-emitting device sublayer away from the pixel definition layer and the pixel definition layer, and less than the distance between the second electrode layer in the corresponding second type of light-emitting device sublayer and the pixel definition layer. In the second type of overlapping substructure, the first region is overlapped with the second electrode layer in the corresponding second type of light-emitting device sublayer, and the surface of the second region is provided with an insulating structure, which is configured to electrically insulate the second region from the light-emitting device layer.

12. The display substrate according to claim 11, wherein, In at least a portion of the second type of overlapping substructure, the height of the surface of the first region on the side away from the pixel definition layer relative to the pixel definition layer is less than the distance between the second electrode layer in the first type of adjacent light-emitting device sublayer and the pixel definition layer. The first type of adjacent light-emitting device sublayer is the light-emitting device sublayer that is closest to the corresponding second type of light-emitting device sublayer and is located on the side of the corresponding second type of light-emitting device sublayer away from the pixel definition layer.

13. The display substrate according to claim 11, wherein, From the pixel definition layer to the light-emitting device layer, the plurality of light-emitting device sub-layers include at least a first light-emitting device sub-layer, a second light-emitting device sub-layer, and a third light-emitting device sub-layer in sequence. The first type of light-emitting device sub-layer includes the first light-emitting device sub-layer, and the second type of light-emitting device sub-layer includes the second light-emitting device sub-layer and the third light-emitting device sub-layer. The plurality of overlapping sub-structures include a first overlapping sub-structure, a second overlapping sub-structure, and a third overlapping sub-structure. The first type of overlapping sub-structure includes the first overlapping sub-structure, and the second type of overlapping sub-structure includes the second overlapping sub-structure and the third overlapping sub-structure. The first overlapping sub-structure overlaps with the first light-emitting device sub-layer, the second overlapping sub-structure overlaps with the second light-emitting device sub-layer, and the third overlapping sub-structure overlaps with the third light-emitting device sub-layer. In a direction perpendicular to the plane of the display substrate, the height of the surface of the third overlapping substructure away from the pixel definition layer relative to the pixel definition layer, and the thickness of the film layer in the light-emitting device layer, are as follows: M1+C1+M2+C2+M3+C3 <H3; In the direction perpendicular to the plane of the display substrate, M1 is the thickness of the light-emitting structure layer in the first light-emitting device sublayer, M2 is the thickness of the light-emitting structure layer in the second light-emitting device sublayer, M3 is the thickness of the light-emitting structure layer in the third light-emitting device sublayer, C1 is the thickness of the second electrode in the first light-emitting device sublayer, C2 is the thickness of the second electrode in the second light-emitting device sublayer, C3 is the thickness of the second electrode in the third light-emitting device sublayer, and H3 is the height of the surface of the third overlapping substructure away from the pixel definition layer relative to the pixel definition layer.

14. The display substrate according to claim 13, wherein, In a direction perpendicular to the plane of the display substrate, the height of the surface of the second overlapping substructure away from the pixel definition layer relative to the pixel definition layer, and the thickness of the film layer in the light-emitting device layer, are related as follows: M1+C1+M2+C2 <H2<M1+C1+M2+C2+(1 / 2)M3; In a direction perpendicular to the plane of the display substrate, H2 is the height of the surface of the second overlapping substructure away from the pixel definition layer relative to the pixel definition layer.

15. The display substrate according to claim 13, wherein, In a direction perpendicular to the plane of the display substrate, the height of the surface of the first overlapping substructure away from the pixel definition layer relative to the pixel definition layer, and the thickness of the film layer in the light-emitting device layer, are related as follows: M1+C1 <H1<M1+C1+(1 / 2)M2; In a direction perpendicular to the plane of the display substrate, H1 is the height of the surface of the first overlapping substructure away from the pixel definition layer relative to the pixel definition layer.

16. The display substrate according to claim 13, wherein, In a direction perpendicular to the plane of the display substrate, the height of the surface of the second region in the second overlapping substructure away from the pixel definition layer relative to the pixel definition layer, and the thickness of the film layer in the light-emitting device layer, are related as follows: M1+C1+(1 / 2)M2 <W1<M1+C1+M2; In a direction perpendicular to the plane of the display substrate, W1 is the height of the surface of the second region in the second overlapping substructure away from the pixel definition layer relative to the pixel definition layer.

17. The display substrate according to claim 13, wherein, In a direction perpendicular to the plane of the display substrate, the height of the surface of the second region in the third overlapping substructure away from the pixel definition layer relative to the pixel definition layer, and the film thickness in the light-emitting device layer, are related as follows: M1+C1+M2+C2+(1 / 2)M3 <W2<M1+C1+M2+C2+M3; In a direction perpendicular to the plane of the display substrate, W2 is the height of the surface of the second region in the third overlapping substructure away from the pixel definition layer relative to the pixel definition layer.

18. The display substrate according to any one of claims 2 to 4, wherein, The partition structure further includes a plurality of second cutting structures. In the partition structure corresponding to the same pixel opening, the plurality of second cutting structures correspond one-to-one with the plurality of overlapping substructures. Along the direction from the pixel opening to the corresponding partition structure, the size of the second cutting structure is larger than the size of the corresponding overlapping structure. In a direction perpendicular to the plane of the display substrate, the second cutting structure is located on the side of the corresponding overlapping substructure away from the pixel definition layer.

19. The display substrate according to claim 18, wherein, In the cross-sectional structure along the direction of the pixel opening pointing to the corresponding partition structure, the cross-section of the second cutting structure and the corresponding overlapping substructure form a T-shape.

20. The display substrate according to claim 18, wherein, In a direction perpendicular to the plane of the display substrate, the height of the surface of the second cutting structure away from the pixel definition layer relative to the pixel definition layer is greater than the distance between the surface of the corresponding light-emitting device sublayer away from the pixel definition layer and the pixel definition layer, and less than the distance between the surface of the second electrode layer in the first type of adjacent light-emitting device sublayer away from the pixel definition layer and the pixel definition layer. The first type of adjacent light-emitting device sublayer is the light-emitting device sublayer closest to the corresponding light-emitting device sublayer and is located on the side of the corresponding second type of light-emitting device sublayer away from the pixel definition layer.

21. The display substrate according to claim 18, wherein, In the plane of the display substrate, along the direction from the pixel opening to the corresponding partition structure, on the same side of the center of the second cut structure, the difference between the size of the second cut structure and the size of the corresponding overlapping substructure is 0.1 micrometer to 0.6 micrometer; in the direction perpendicular to the plane of the display substrate, the size of the second cut structure is 2 nanometer to 25 nanometer.

22. The display substrate according to claim 18, wherein, In the plane where the display substrate is located, along the direction from the pixel opening to the corresponding partition structure, the size of the overlapping substructure in the partition structure corresponding to the same pixel opening is 3 micrometers to 13 micrometers.

23. The display substrate according to claim 5, wherein the partition structure further includes a third cutting structure, and in the partition structure corresponding to the same pixel opening, along the direction from the pixel opening to the corresponding partition structure, the size of the third cutting structure is larger than the size of the corresponding overlapping substructure; In a direction perpendicular to the plane of the display substrate, the third cutting structure is located on the side of the corresponding first isolation structure away from the pixel definition layer.

24. The display substrate according to any one of claims 2 to 5, wherein, The display substrate further includes a back plate and an anode layer. In a direction perpendicular to the plane of the display substrate, the back plate is located on the side of the pixel definition layer away from the light-emitting device layer. The anode layer is located between the back plate and the pixel definition layer. The anode layer includes a plurality of anodes. At least some anodes correspond one-to-one with at least some pixel openings and at least some light-emitting units. The orthographic projection of the pixel opening on the back plate is located within the range of the orthographic projection of the corresponding anode on the back plate. In the anode and light-emitting unit corresponding to the same pixel opening, the anode is reused as the first electrode of the light-emitting device closest to the back plate in the light-emitting unit.

25. The display substrate according to claim 24, wherein, The backplate has multiple electrode traces, and at least some of the electrode traces are electrically connected to at least some of the overlapping substructures. In the direction perpendicular to the plane of the display substrate, the overlapping substructure is configured such that one end is electrically connected to the corresponding electrode trace, and the other end passes through the pixel definition layer and overlaps with the corresponding second electrode layer.

26. The display substrate according to any one of claims 2 to 5, wherein, In a direction perpendicular to the plane of the display substrate, the thickness of the light-emitting structure layer is 2000 angstroms to 4000 angstroms, the thickness of the first electrode layer is 8 nanometers to 55 nanometers, the thickness of the second electrode layer is 8 nanometers to 55 nanometers, and the thickness of the pixel definition layer is 0.5 micrometers to 3 micrometers.

27. The display substrate according to claim 26, wherein, The first electrode layer and the second electrode layer are made of metal. In the direction perpendicular to the plane where the display substrate is located, the thickness of the first electrode layer is 8 nanometers to 25 nanometers, and the thickness of the second electrode layer is 8 nanometers to 25 nanometers. Alternatively, the first electrode layer and the second electrode layer are made of semiconductor oxide, and in the direction perpendicular to the plane of the display substrate, the thickness of the first electrode layer is 8 nanometers to 55 nanometers, and the thickness of the second electrode layer is 8 nanometers to 55 nanometers.

28. A display device comprising a display substrate as described in any one of claims 1 to 27.

29. A method for preparing a display substrate, comprising: A pixel definition layer is formed on one side of the back panel, and the pixel definition layer has multiple pixel openings; Multiple partition structures are formed on the side of the pixel definition layer away from the back plate, and at least some of the partition structures correspond one-to-one with at least some of the pixel openings. The partition structures are configured as closed structures surrounding the corresponding pixel openings. A light-emitting device layer is formed on the side of the partition structure away from the back plate. In the plane where the display substrate is located, the light-emitting device layer includes a plurality of light-emitting units formed by the plurality of partition structures. At least a portion of the light-emitting units correspond one-to-one with at least a portion of the pixel openings, and at least a portion of the light-emitting units are located in the corresponding pixel openings.

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