Semiconductor device

Abstract

The present invention provides a semiconductor device having reduced power consumption. This semiconductor device includes a first inverter, a second inverter, a first analog switch, a first transistor, and a capacitive element. In particular, the first inverter has a second transistor and a third transistor. Each of the first transistor and the second transistor is an IO transistor, and the third transistor is an Si transistor. An output terminal of the second inverter is connected to a first terminal of the first transistor, and a second terminal of the first transistor is connected to a first terminal of the capacitive element and an input terminal of the first inverter. An output terminal of the first inverter is connected to a first terminal of the first analog switch, and a second terminal of the first analog switch is connected to an input terminal of the second inverter. A gate of the first transistor is connected to a first interconnect, and a p-channel–side control terminal of the first analog switch is connected to the first interconnect.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] In recent years, efforts to combat global warming have become increasingly important. Energy consumption continues to increase, and carbon dioxide emissions, one of the causes of global warming, have yet to be reduced. Simply reducing energy consumption may actually result in a loss of convenience. To reduce energy consumption without sacrificing convenience, low-power consumption technologies are becoming extremely important.

[0004] In logic circuits that perform arithmetic processing, such as CPUs (Central Processing Units) and GPUs (Graphics Processing Units), transistors are becoming increasingly miniaturized and integrated to improve performance. Logic circuits have a circuit structure (also called CMOS (Complementary Metal-Oxide-Semiconductor)) that combines n-channel transistors (also called nMOS) and p-channel transistors (also called pMOS). In CMOS, power consumption increases due to factors such as leakage currents that accompany miniaturization of transistors and through currents that accompany switching between the on and off states of transistors.

[0005] Therefore, it has been studied to reduce the power consumption of a logic circuit by using a transistor including silicon in a channel formation region (referred to as a Si transistor in this specification) as a p-channel transistor and a transistor including an oxide semiconductor in a channel formation region (referred to as an OS transistor in this specification) as an n-channel transistor. For example, Patent Document 1 describes an inverter including a Si transistor as a p-channel transistor and an OS transistor as an n-channel transistor, as a logic circuit. Since the off-state current of an OS transistor is extremely small, the power consumption of the inverter can be reduced compared to when a Si transistor is used as an n-channel transistor.

[0006] JP 2023-10639 A

[0007] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] An inverter is one of the logic circuits that can be provided in the CPU, GPU, etc. For example, an inverter may be used in a flip-flop provided in the CPU, GPU, etc. In particular, since a flip-flop has a mechanism for latching data using an inverter loop including the inverter, it is desirable for the transistor included in the inverter to have a small off-current to reduce power consumption, as well as a high field-effect mobility to increase the operation speed for writing and reading.

[0009] Furthermore, when configuring a retention flip-flop, it is necessary to provide a backup circuit (sometimes referred to as a memory circuit in this specification) that can temporarily save data even when the power supply is interrupted. Furthermore, since the backup circuit often uses a backup power supply that is different from the power supply that is interrupted and backs up data using an inverter loop, the backup circuit must be provided with logic circuits, switches, etc. that operate on each power supply. Therefore, the area of ​​the backup circuit or the retention flip-flop including the backup circuit tends to be large.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption.An object of one embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time even when power is cut off.An object of one embodiment of the present invention is to provide a semiconductor device with increased driving speed.An object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area.An object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0012] Consider an inverter loop that can be included in a retention flip-flop. In one embodiment of the present invention, a transistor having indium oxide (also referred to as indium oxide) in a channel formation region (referred to as an IO transistor in this specification) is used as an n-channel transistor included in the inverter loop. Furthermore, the inverter loop includes a switch including an IO transistor and a capacitor, and data is backed up by the capacitor.

[0013] A configuration of one embodiment of the present invention will be described below.

[0014] (1) One embodiment of the present invention is a semiconductor device including a first inverter, a second inverter, a first analog switch, a first transistor, and a capacitor. The first inverter includes a second transistor and a third transistor. Each of the first transistor and the second transistor is an n-channel transistor including an oxide semiconductor in a channel formation region, and the third transistor is a p-channel transistor including silicon in a channel formation region. The oxide semiconductor includes indium.

[0015] The output terminal of the second inverter is electrically connected to the first terminal of the first transistor. The second terminal of the first transistor is electrically connected to the first terminal of the capacitance element and the input terminal of the first inverter. The output terminal of the first inverter is electrically connected to the first terminal of the first analog switch. The second terminal of the first analog switch is electrically connected to the input terminal of the second inverter. The gate of the first transistor is electrically connected to the first wiring. The p-channel side control terminal of the first analog switch is electrically connected to the first wiring.

[0016] The input terminals of the first inverter are the gates of the second transistor and the third transistor, and the output terminals of the first inverter are the first terminal of the second transistor and the first terminal of the third transistor.

[0017] (2) Alternatively, according to one embodiment of the present invention, in the above-described (1), each of the second inverter and the first analog switch may include a transistor including silicon in a channel formation region.

[0018] (3) Alternatively, in one aspect of the present invention, in the above (2), a configuration may be provided in which a first circuit layer and a second circuit layer are located above the first circuit layer.

[0019] In particular, the first circuit layer preferably includes a third transistor, a transistor included in the second inverter, and a transistor included in the first analog switch, and the second circuit layer preferably includes a first transistor and a second transistor.

[0020] (4) Alternatively, according to one aspect of the present invention, in the above (3), the circuit may further include a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a second analog switch, a third analog switch, and a fourth analog switch.

[0021] In particular, it is preferable that the output terminal of the third inverter is electrically connected to the first terminal of the second analog switch. It is also preferable that the second terminal of the second analog switch is electrically connected to the first terminal of the third analog switch and the input terminal of the fourth inverter. It is also preferable that the output terminal of the fourth inverter is electrically connected to the input terminal of the fifth inverter and the first terminal of the fourth analog switch. It is also preferable that the output terminal of the fifth inverter is electrically connected to the second terminal of the third analog switch. It is also preferable that the second terminal of the fourth analog switch is electrically connected to the input terminal of the sixth inverter, the input terminal of the second inverter, and the second terminal of the first analog switch.

[0022] (5) Alternatively, in one aspect of the present invention, in the above (4), the first circuit layer may include a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a second analog switch, a third analog switch, and a fourth analog switch.

[0023] In particular, it is preferable that each of the third to sixth inverters and the second to fourth analog switches has a transistor including silicon in a channel formation region.

[0024] In the inverter loop, which is the semiconductor device described in (1) above, by using the first transistor and the capacitance element, data can be retained even if the power supply to the inverter loop is cut off.

[0025] In addition, in the above (1), by using an IO transistor as the n-channel transistor of the first inverter, the drive frequency of the first inverter can be increased, thereby enabling faster data readout when power supply to the inverter loop is resumed.

[0026] Furthermore, by using the configurations (3) and (5) above, the Si transistors can be provided in the first layer, and the IO transistors can be provided in the second layer located above the first layer, thereby reducing the circuit area of ​​the semiconductor device.

[0027] Furthermore, the configuration of (4) above can form a retention flip-flop.

[0028] According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device capable of retaining data for a long period of time even when power is cut off can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with increased driving speed can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device can be provided.

[0029] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0030] 1A and 1B are circuit diagrams showing an example of the configuration of a semiconductor device, and FIG. 1C is a timing chart showing an example of the operation of the semiconductor device. FIG. 2A is a circuit diagram showing an example of the configuration of a semiconductor device, and FIG. 2B is a timing chart showing an example of the operation of the semiconductor device. FIGS. 3A and 3B are circuit diagrams showing an example of the configuration of a semiconductor device. FIG. 4 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 5 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 6 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 7 is a timing chart showing an example of the operation of the semiconductor device. FIG. 8 is a circuit diagram showing an example of the configuration of a semiconductor device. FIGS. 9A and 9B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 9C is a cross-sectional view illustrating an indium oxide film. FIG. 10 is a schematic perspective view showing an example of the configuration of a semiconductor device. FIGS. 11A and 11B are schematic plan views showing an example of the configuration of a circuit included in the semiconductor device. FIG. 12 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 13 is a schematic cross-sectional view showing an example of the configuration of a transistor included in the semiconductor device. 14A and 14B are cross-sectional schematic views showing an example of the configuration of a transistor included in a semiconductor device. FIGS. 15A, 15B, and 15C are cross-sectional schematic views showing an example of the configuration of a transistor included in a semiconductor device. FIG. 16 is a perspective schematic view showing an example of the configuration of a transistor included in a semiconductor device. FIGS. 17A and 17B are cross-sectional schematic views showing an example of the configuration of a capacitive element included in a semiconductor device. FIGS. 18A, 18B, 18C, and 18D are diagrams showing an example of electronic components. FIGS. 19A and 19B are diagrams showing an example of electronic equipment, and FIG. 19C is a diagram showing an example of a mainframe computer. FIG. 20 is a diagram showing an example of space equipment. FIG. 21 is a diagram showing an example of a storage system applicable to a data center. 22A1, 22A2, 22A3, 22A4, 22A5, 22A6, 22A7 and 22B1, 22B2, 22B3, 22B4, 22B5, and 22B6 are circuit diagrams for explaining electrical connections.

[0031] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. For example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0032] In this specification, "connection" includes, for example, "electrical connection."

[0033] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0034] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0035] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 22A1 and 22A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 22A3 , when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0036] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 22A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 22A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0037] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 22A6 and 22A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 22A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 22A6 and 22A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0038] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0039] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 22B1, 22B2, and 22B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 22B4 and 22B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 22B6. ​​Because A and V or B and V are connected via the source and drain of a transistor, it cannot be said that they are directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0040] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0041] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0042] Generally, examples of a "resistance element" include a circuit element having a resistance value higher than 0Ω, wiring having a resistance value higher than 0Ω, etc. Therefore, the "resistance element" described in this specification includes wiring, diodes, or coils having a resistance value. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 ９ It can be made smaller than Ω.

[0043] Generally, examples of "capacitance" include a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, and a region between a gate or back gate and a source or drain in a transistor having a capacitance value higher than 0 F. Furthermore, the terms "capacitance element," "parasitic capacitance," or "gate capacitance" may sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" may sometimes be replaced with the terms "capacitance element," "parasitic capacitance," or "gate capacitance."

[0044] Furthermore, a "capacitor" (including a "capacitor" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitor" can be rephrased as "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Furthermore, the terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The value of the electrostatic capacitance of a capacitor can be, for example, 0.05 fF or more and 10 pF or less. Furthermore, it can be, for example, 1 pF or more and 10 μF or less.

[0045] The switches described in this specification are described as having the function of being turned on or off and controlling whether or not a current flows, or as having the function of selecting and switching the path through which a current flows.

[0046] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0047] In addition, in this specification, the terms "conductive" or "conductive state" used when conductive layers are in direct contact with each other refer to a state in which a current can flow between the conductive layers, for example.

[0048] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0049] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. For example, an analog switch can be mentioned as an example of such a logic circuit. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0050] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive and non-conductive states.

[0051] The selector described herein may be, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, the selector described herein may be a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, the selector described herein may be, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, the selector may be a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, the selector may refer to a multiplexer or a demultiplexer. In particular, when inputting or outputting an analog potential or an analog current, the selector may refer to an analog multiplexer or an analog demultiplexer.

[0052] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain is sometimes referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain is sometimes referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0053] For example, an example of a transistor described herein may include a multi-gate transistor with two or more gate electrodes. The multi-gate structure allows the channel formation regions to be connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the transistor's breakdown voltage (reliability). Alternatively, the multi-gate structure can provide a flat Id-Vds characteristic when operating in the saturation region of the Id (source-drain current)-Vds (drain-source voltage) characteristic, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing the flat Id-Vds characteristic, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0054] Generally, the threshold voltage of a transistor is a voltage between the subthreshold region (weak inversion region) and the strong inversion region, and can be said to be the voltage at which switching between the subthreshold region and the strong inversion region occurs. In addition, as an example of a method for measuring the threshold voltage, Id is calculated based on the Id (source-drain current) - Vgs (gate-source voltage) characteristics. １／２ -Vgs characteristics are plotted, and Id １／２ Id on the tangent line where the slope of the -Vgs characteristic is maximum １／２ As another example, in the Id-Vgs characteristic where the drain potential is 1.2 V, Id=1.0×10 −１２ A is set as the threshold voltage.

[0055] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0056] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. A terminal, a wiring, etc. can also be referred to as a node.

[0057] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0058] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to the two wirings may be different from each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to the two wirings may be different from each other.

[0059] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0060] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the counter may be omitted in the claims. For example, a component with an ordinal number "first" in one embodiment of this specification may be a component with a different ordinal number such as "second" or "third" in other embodiments or claims. Furthermore, for example, a component with an ordinal number "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0061] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0062] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0063] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Or, in some cases or depending on the situation, the terms "film" and "layer" can be replaced with other terms without being used. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, the term "insulating layer" or "insulating film" can be changed to the term "insulator".

[0064] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0065] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0066] In addition, timing charts may be used in this specification to explain an operation method of a semiconductor device. The timing charts used in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. For example, to clearly illustrate the timing charts, two or more overlapping signals may be intentionally shifted.

[0067] In this specification, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OS), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor. Note that indium oxide is a metal oxide; therefore, the OS transistor described in this specification includes an IO transistor.

[0068] In this specification, nitrogen-containing metal oxides may also be collectively referred to as metal oxides, and nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0069] In this specification, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0070] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0071] In this specification, unless otherwise specified, the expression "A and B are equal" means that the ratio of one of A and B to the other is 0.9 or more and 1.1 or less. For example, the case where the ratio of B to A is 0.9 or more and 1.1 or less and the ratio of A to B is not 0.9 or more and 1.1 or less is also considered to be "A and B are equal." Furthermore, unless otherwise specified, the expression "A and B are approximately equal" means that the ratio of one of A and B to the other is 0.8 or more and 1.2 or less, is also considered to be "A and B are approximately equal." For example, the case where the ratio of B to A is 0.8 or more and 1.2 or less and the ratio of A to B is not 0.8 or more and 1.2 or less is also considered to be "A and B are approximately equal."

[0072] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0073] In addition, the content described in one embodiment can be applied, combined, or replaced with another content described in that embodiment and at least one of the content described in another embodiment.

[0074] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0075] Furthermore, a figure described in one embodiment can be combined with another portion of that figure and at least one figure described in one or more other embodiments to form even more figures.

[0076] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0077] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0078] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0079] Embodiment 1 In this embodiment, a memory circuit capable of backing up data, which is a semiconductor device of one embodiment of the present invention, will be described.

[0080] First, a conventional configuration of a memory circuit will be described. Note that the memory circuit may be called a backup circuit or the like.

[0081] 2A is a memory circuit capable of backing up data, and includes, as an example, inverters IV1, IV2, IVP, switches AS1, and AS2. Also shown in FIG. 2A are a power supply circuit PW and a power supply control logic circuit CTL located outside the memory circuit BUCZ.

[0082] Each of the inverters IV1, IV2, and IVP has a function of, when a signal that is digital data is input to the input terminal, outputting a signal that is the inverse of the logic of the signal to the output terminal.

[0083] 2A also shows wiring VDE and wiring VSE for supplying the power supply voltage from the power supply circuit PW to the inverters IV1, IV2, and IVP, respectively.

[0084] The power supply voltage may also be applied as a body voltage to the transistors included in each of the switches AS1 and AS2.

[0085] Note that, for example, a high power supply potential is applied to the wiring VDE from the power supply circuit PW, and a low power supply potential is applied to the wiring VSE from the power supply circuit PW.

[0086] Furthermore, as an example, the power supply circuit PW is configured independently of other power supply circuits. As a result, even if power supply circuits other than the power supply circuit PW are stopped, the power supply voltage can be supplied from the power supply circuit PW to each of the inverters IV1, IV2, and IVP. In particular, the power supply circuit PW is sometimes called a backup power supply. As will be described in more detail later, the power supply circuit PW is used in conjunction with a circuit that generates the signals CK and CKB.

[0087] Furthermore, electrical switches can be applied to each of the switches AS1 and AS2. For example, in FIG. 2A, analog switches are shown as electrical switches for each of the switches AS1 and AS2. Note that mechanical switches such as MEMS may also be applied to each of the switches AS1 and AS2.

[0088] Each of the switches AS1 and AS2 has a first control terminal and a second control terminal, and is turned on or off in response to control signals input to the first control terminal and the second control terminal, respectively.

[0089] For example, in this specification, each of switches AS1 and AS2 is assumed to be in an on state when a high-level potential is input to the first control terminal and a low-level potential is input to the second control terminal. Also, each of switches AS1 and AS2 is assumed to be in an off state when a low-level potential is input to the first control terminal and a high-level potential is input to the second control terminal. Therefore, in this specification, the first control terminal of an analog switch may be referred to as an n-channel side control terminal, and the second control terminal may be referred to as a p-channel side control terminal.

[0090] The memory circuit BUCZ also has, for example, a terminal IOT, a terminal CT, a terminal CBT, and a terminal ST.

[0091] The terminal IOT has a function as a terminal for inputting data to be backed up to the memory circuit BUCZ and a function as a terminal for outputting the backed-up data from the memory circuit BUCZ. Also, Fig. 2A shows an example in which a signal SIG corresponding to the data is input to the terminal IOT.

[0092] Furthermore, as an example, each of the terminals CT and CBT functions as a terminal for inputting a signal to the memory circuit BUCZ. The signal may be, for example, a variable potential representing a pulse potential or the like. In particular, the logic of the potential applied to the terminal CT is preferably the inverse of the logic of the potential applied to the terminal CBT. FIG. 2A illustrates an example in which the signal CK and the signal CKB are input to the terminal CT. As described above, the logic of the signal CK is preferably the inverse of the logic of the signal CKB. Furthermore, as will be described in detail later, the signals CK and CKB are control signals that control the switching of the switch AS1 between the on state and the off state. Furthermore, each of the signals CK and CKB may be a clock signal that alternates between a high-level potential and a low-level potential.

[0093] Furthermore, the terminal ST functions as a terminal for inputting a signal to the memory circuit BUCZ, for example. The signal can be, for example, a variable potential representing a pulse potential or the like. FIG. 2A also shows an example in which a signal generated by the power supply control logic circuit CTL is input to the terminal ST. Therefore, a signal from the power supply control logic circuit CTL is input to the input terminal of the inverter IVP and the second control terminal of the switch AS2. A signal whose logic is inverted by the inverter IVP is input to the first control terminal of the switch AS2. In other words, the signal generated by the power supply control logic circuit CTL serves as a control signal for controlling the switching of the switch AS2 between the on state and the off state.

[0094] The terminal IOT is connected to the input terminal of the inverter IV1, the first terminal of the switch AS1, and the first terminal of the switch AS2. The terminal CT is connected to the first control terminal of the switch AS1, and the terminal CBT is connected to the second control terminal of the switch AS1. The terminal ST is connected to the input terminal of the inverter IVP and the second control terminal of the switch AS2, and the output terminal of the inverter IVP is connected to the first control terminal of the switch AS2. The output terminal of the inverter IV1 is connected to the input terminal of the inverter IV2. The output terminal of the inverter IV2 is connected to the second terminal of the switch AS1 and the second terminal of the switch AS2.

[0095] In FIG. 2A, the connection point between the output terminal of the inverter IV1 and the input terminal of the inverter IV2 is indicated as a node SN.

[0096] As described above, the output terminal of the inverter IVP is connected to the first control terminal of the switch AS2, and the input terminal of the inverter IVP is connected to the second control terminal of the switch AS2 and the terminal ST. In addition, in FIG. 2A, the terminal ST of the memory circuit BUCZ is connected to the power supply control logic circuit CTL.

[0097] 2B shows a timing chart illustrating an operation example of the memory circuit BUC in FIG. 2A. Specifically, the timing chart shows potential changes of the terminal IOT, the node SN, the terminal CT, the terminal CBT, and the terminal ST in the periods T01 to T06. In addition, in the timing chart, a high-level potential is denoted as "High" and a low-level potential is denoted as "Low."

[0098] During periods T01, T02, and T06, a high-level potential is applied to the terminal ST from the power supply control logic circuit CTL. This causes a high-level potential to be applied to the input terminal of the inverter IVP, and a low-level potential is output from the output terminal of the inverter IVP. As a result, a low-level potential is applied to the first control terminal of the switch AS2 as a first control signal. Furthermore, a high-level potential is applied to the second control terminal of the switch AS2 as a second control signal. Therefore, the switch AS2 is in the off state during periods T01, T02, and T06.

[0099] Furthermore, from period T03 to period T05, a low-level potential is applied to terminal ST from power supply control logic circuit CTL. This also applies a low-level potential to the input terminal of inverter IVP, and a high-level potential is output from the output terminal of inverter IVP. As a result, a high-level potential is applied as a first control signal to the first control terminal of switch AS2. Furthermore, a low-level potential is applied as a second control signal to the second control terminal of switch AS2. Therefore, switch AS2 is in the on state from period T03 to period T05.

[0100] In addition, in the periods T01 to T06, the inverters IV1, IV2, and IVP are supplied with the high power supply potential and the low power supply potential from the power supply circuit PW, respectively, so that the inverters IV1, IV2, and IVP continue to operate without stopping in the periods T01 to T06.

[0101] In a period T01, a low-level potential is input to the terminal IOT as the signal SIG. The inverter IV1 inverts the logic of the signal SIG, and the potential of the node SN becomes a high-level potential.

[0102] Furthermore, during period T01, a high-level potential is applied to terminal CT as signal CK, and a low-level potential is applied to terminal CBT as signal CKB. As a result, a high-level potential is applied to the first control terminal of switch AS1, and a low-level potential is applied to the second control terminal of switch AS1, so that switch AS1 is turned on. At this time, in memory circuit BUCZ, data corresponding to signal SIG is latched by inverters IV1, IV2, and switch AS1. Specifically, a low-level potential is latched to terminal IOT, and a high-level potential is latched to node SN.

[0103] Therefore, the period T01 can be set as a period during which the memory circuit BUCZ latches data according to the signal SIG.

[0104] During the period T02, a low-level potential is applied to the terminal CT as the signal CK, and a high-level potential is applied to the terminal CBT as the signal CKB, so that a low-level potential is applied to the first control terminal of the switch AS1 and a high-level potential is applied to the second control terminal of the switch AS1, turning the switch AS1 off.

[0105] In the period T02, a high-level potential is input to the terminal IOT as the signal SIG. The inverter IV1 causes the potential of the node SN to become a low-level potential, which is a potential obtained by inverting the logic of the signal SIG. That is, compared to the period T01, the potential of the terminal IOT changes from a low-level potential to a high-level potential, and the potential of the node SN changes from a high-level potential to a low-level potential.

[0106] As described above, the period T02 can be set as a period during which the memory circuit BUCZ receives data according to the signal SIG.

[0107] During period T03, a high-level potential is applied to terminal CT as signal CK, and a low-level potential is applied to terminal CBT as signal CKB. As a result, a high-level potential is applied to the first control terminal of switch AS1, and a low-level potential is applied to the second control terminal of switch AS1, so that switch AS1 is in the ON state. Furthermore, during period T03, switch AS2 is in the ON state. At this time, data corresponding to signal SIG is latched in memory circuit BUCZ by inverters IV1, IV2, switch AS1, and switch AS2. Specifically, a high-level potential is latched to terminal IOT, and a low-level potential is latched to node SN.

[0108] Therefore, the period T03 can be a period in which the memory circuit BUCZ latches data according to the signal SIG, similar to the period T01.

[0109] Furthermore, during the period T04, the generation of the signal CK and the signal CKB stops. That is, during the period T04, the signal CK is not input to the terminal CT of the memory circuit BUCZ, and the signal CKB is not input to the terminal CBT of the memory circuit BUCZ, so that the potentials of the terminals CT and CBT are low. As a result, the switch AS1 is not set to an on state or an off state.

[0110] Since the switch AS2 is in the on state during the period T04, even if the supply of the signals CK and CKB is stopped, the memory circuit BUCZ can back up the data corresponding to the signal SIG using the inverters IV1, IV2, and the switch AS2.

[0111] During period T05, generation of signals CK and CKB resumes. Specifically, a high-level potential is input to terminal CT as signal CK, and a low-level potential is input to terminal CBT as signal CKB. As a result, a high-level potential is applied to the first control terminal of switch AS1, and a low-level potential is applied to the second control terminal of switch AS1, so that switch AS1 is turned on. Furthermore, during period T05, switch AS2 is turned on. During period T04, data corresponding to signal SIG was latched by inverters IV1, IV2, and switch AS2. During period T05, data corresponding to signal SIG is latched by switch AS1, inverters IV1, IV2, switch AS1, and switch AS2.

[0112] The period T05 can be a period in which the data latched in the periods T03 and T04 is restored from the memory circuit BUCZ to the terminal IOT.

[0113] In the period T06, a low-level potential is applied to the terminal CT as the signal CK, and a high-level potential is applied to the terminal CBT as the signal CKB, so that a low-level potential is applied to the first control terminal of the switch AS1 and a high-level potential is applied to the second control terminal of the switch AS1, turning the switch AS1 off.

[0114] As described above, the period T06 can be a period in which the memory circuit BUCZ receives data corresponding to the signal SIG, similar to the period T02. Therefore, although a high-level potential is applied as the signal SIG in the period T06, the signal SIG may be a low-level potential.

[0115] As in the above operation example, by using the memory circuit BUCZ and power supply circuit PW shown in Figure 2A, data can be backed up in the memory circuit BUCZ even if the supply of signals CK and CKB is stopped. However, when the memory circuit BUCZ is used, an inverter IVP is required to generate the first control signal for the switch AS2, which tends to increase the circuit area. Furthermore, since the memory circuit BUCZ requires the switch AS2, the number of circuit elements tends to increase.

[0116] <Configuration Example of Memory Circuit> One embodiment of the present invention is a memory circuit with a reduced number of circuit elements, which is achieved in consideration of the problems with the configuration of the memory circuit BUCZ in FIG. 2A. Furthermore, a backup power supply (power supply circuit PW) is not required to drive the memory circuit. Therefore, the use of the memory circuit can reduce power consumption.

[0117] 1A shows an example of a circuit diagram of the memory circuit BUC, which includes an inverter IV1, an inverter IVX, a switch AS1, a switch ASX, and a capacitor C1.

[0118] For the inverter IV1 shown in Fig. 1A, the description of the inverter IV1 in Fig. 2A can be referred to. Also, for the switch AS1 in Fig. 1A, the description of the switch AS1 in Fig. 2A can be referred to.

[0119] The memory circuit BUC also has, for example, a terminal IOT, a terminal CT, and a terminal CBT.

[0120] 1A can be an electrical switch, for example, which is turned on when a high-level potential is applied to its control terminal and turned off when a low-level potential is applied to its control terminal.

[0121] In particular, an OS transistor including an oxide semiconductor in a channel formation region is preferably used as an electrical switch used for the switch ASX. Because an OS transistor has a small off-state current, using an OS transistor as an electrical switch used for the switch ASX can reduce leakage current between the first terminal and the second terminal of the switch ASX in an off state. Furthermore, the oxide semiconductor preferably contains indium. Furthermore, it is more preferable to use an IO transistor including indium oxide (also referred to as indium oxide) in a channel formation region as the OS transistor in order to increase the on-state current. Furthermore, because an IO transistor has a high switching frequency, using an OS transistor as an electrical switch used for the switch ASX can speed up switching between the on state and the off state of the switch ASX.

[0122] 1A and 2A, the inverter IVX shown in Fig. 1A has a function of inverting the logic of digital data input to an input terminal and outputting the inverted logic to an output terminal. In particular, as described above, it is preferable to use an IO transistor as the n-channel transistor included in the inverter IVX shown in Fig. 1A.

[0123] As the n-channel transistor included in the inverter IVX, it is preferable to use an OS transistor. Since the OS transistor has a small off-current, by using the OS transistor as the n-channel transistor included in the inverter IVX, when a high-level potential is output from the output terminal of the inverter IVX, the leakage current flowing between the output terminal of the inverter IVX and the wiring for supplying the low power supply potential can be reduced. Further, since the channel formation region of the OS transistor contains an oxide semiconductor containing indium, the on-current of the OS transistor can be increased. Therefore, by including an oxide semiconductor containing indium in the channel formation region of the n-channel transistor included in the inverter IVX, the response speed in the inverter IVX can be increased. Further, by using an IO transistor as the OS transistor, the frequency characteristics of the transistor can be improved. Also, the on-current of the transistor can be increased. Note that indium oxide will be described in detail in Embodiment 2.

[0124] Further, as an example, a transistor containing silicon in the channel formation region (hereinafter referred to as a Si transistor) can be used for the p-channel transistor and the n-channel transistor included in the inverter IV1 shown in FIG. 1A. Similarly, as an example, a Si transistor can be used for the p-channel transistor and the n-channel transistor included in the switch AS1 shown in FIG. 1A.

[0125] Since the Si transistor has a large on-current, it is preferably used for a circuit that requires a high driving frequency such as a logic circuit. By using a Si transistor as the transistor included in each of the inverter IV1 and the switch AS1, the driving speed of the inverter IV1 and the switch AS1 can be increased.

[0126] In FIG. 1A, the terminal IOT is connected to the input terminal of the inverter IV1 and the first terminal of the switch AS1. The terminal CT is connected to the first control terminal of the switch AS1, and the terminal CBT is connected to the second control terminal of the switch AS1 and the control terminal of the switch ASX. The output terminal of the inverter IV1 is connected to the first terminal of the switch ASX. The second terminal of the switch ASX is connected to the input terminal of the inverter IVX and the first terminal of the capacitance element C1. The output terminal of the inverter IVX is connected to the second terminal of the switch AS1. The second terminal of the capacitance element C1 is connected to the wiring VE1.

[0127] 1A, the connection points between the second terminal of the switch ASX, the first terminal of the capacitance element C1, and the input terminal of the inverter IVX are indicated as nodes SN1, and the connection points between the output terminal of the inverter IVX and the second terminal of the switch AS1 are indicated as nodes SN2.

[0128] 1A, the inverter IV1 is connected to the wiring VE1 and the wiring VE2, and the inverter IVX is connected to the wiring VE1 and the wiring VE2.

[0129] For example, the wiring VE1 functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a low power supply potential, such as a ground potential or a negative potential. The fixed potential can be a potential equal to the potential of a low-level signal that each of the signal SIG, the signal CK, and the signal CKB can take. The fixed potential can also be a potential lower than the potential of a low-level signal that each of the signal SIG, the signal CK, and the signal CKB can take.

[0130] For example, the wiring VE2 functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a positive potential as a high power supply potential. The fixed potential can be a potential equal to the potential of a high-level signal that each of the signal SIG, the signal CK, and the signal CKB can take. The fixed potential can also be a potential higher than the potential of a low-level signal that each of the signal SIG, the signal CK, and the signal CKB can take.

[0131] Note that the wiring VE1 and the wiring VE2 are supplied with a high power supply potential and a low power supply potential from a power supply circuit whose operation can be stopped, rather than from the power supply circuit PW which is a backup power supply shown in FIG. 2A.

[0132] As described above, the wiring VE1 can be a wiring that supplies a low-level potential of the power supply voltage to each of the inverters IV1 and IVX, and the wiring VE2 can be a wiring that supplies a high-level potential of the power supply voltage to each of the inverters IV1 and IVX.

[0133] As described above, the wiring VE1 can be a wiring that applies a fixed potential to the capacitor C1 in order to hold a voltage.

[0134] 1A may be the same or different from each other. Similarly, the plurality of wirings VE2 shown in FIG. 1A may be the same or different from each other.

[0135] By using the transistor IMN1 as the electrical switch applied to the switch ASX and the transistor IMN2 as the n-channel transistor included in the inverter IVX, the memory circuit BUC in Fig. 1A can be rewritten as the memory circuit BUCA in Fig. 1B. Note that the transistor SMP2 shown in Fig. 1B is a p-channel transistor included in the inverter IVX.

[0136] A first terminal of the transistor SMP2 is connected to a first terminal of the transistor IMN2, a second terminal of the transistor SMP2 is connected to the wiring VE2, and a second terminal of the transistor IMN2 is connected to the wiring VE1.

[0137] 1B, the first terminal of the switch ASX can be one of the first terminal and the second terminal of the transistor IMN1, and the second terminal of the switch ASX can be the other of the first terminal and the second terminal of the transistor IMN1. The control terminal of the switch ASX can be the gate of the transistor IMN1. The input terminal of the inverter IVX can be the gate of the transistor SMP2 and the gate of the transistor IMN2, and the output terminal of the inverter IVX can be the first terminal of the transistor SMP2 and the first terminal of the transistor IMN2.

[0138] In each of the memory circuit BUC of FIG. 1A and the memory circuit BUCA of FIG. 1B, when a high-level potential is applied to the control terminal of the switch ASX, the switch ASX is in an on state. Furthermore, when a low-level potential is applied to the first control terminal of the switch AS1 and a high-level potential is applied to the second control terminal, the switch AS1 is in an off state. Furthermore, when a low-level potential is applied to the control terminal of the switch ASX, the switch ASX is in an off state. Furthermore, when a high-level potential is applied to the first control terminal of the switch AS1 and a low-level potential is applied to the second control terminal, the switch AS1 is in an on state. In other words, the switches ASX and AS1 are not in an on state or an off state at the same time.

[0139] 2A, when the number of transistors provided in each of inverters IV1, IV2, and IVP is two, and the number of transistors provided in each of switches AS1 and AS2 is two, the memory circuit BUCZ has a total of 10 transistors. On the other hand, in FIGS. 1A and 1B, when the number of transistors provided in each of inverters IV1 and IVX is two, the number of transistors provided in switch AS1 is two, and the number of transistors provided in switch ASX is one, the memory circuit BUC or memory circuit BUCA has a total of seven transistors and one capacitor. For these reasons, by using the memory circuit BUC or memory circuit BUCA, the number of circuit elements can be reduced compared to the memory circuit BUCZ, and the circuit area can be made smaller.

[0140] 1C shows a timing chart illustrating an operation example of the memory circuit BUC in FIG. 1A and the memory circuit BUCA in FIG. 1B. Specifically, the timing chart illustrates potential changes of the wiring VE2, the wiring VE1, the terminal CT, the terminal CBT, the terminal IOT, the node SN1, and the node SN2 in the periods T11 to T16. In addition, in the timing chart, a high-level potential is indicated as "High" and a low-level potential is indicated as "Low."

[0141] 1C, the supply of power supply voltage to the memory circuit BUC or the memory circuit BUCA is stopped. Note that potential changes of the wirings, terminals, and nodes during the period T14 will be described later.

[0142] In each of the periods T11 and T12, a clock signal is input to the terminal CT as the signal CK. Specifically, each of the periods T11 and T12 includes a period in which the signal CK transitions from a low-level potential to a high-level potential. Also, in each of the periods T11 and T12, a signal CKB, which is the inverted logic of the signal CK, is input to the terminal CBT. Specifically, each of the periods T11 and T12 includes a period in which the signal CKB transitions from a high-level potential to a low-level potential.

[0143] In a period T11, a high-level potential is input to the terminal IOT as the signal SIG, which causes the inverter IV1 to output a low-level potential to the output terminal.

[0144] During the period T11 when the potential of the terminal CT is low (the period when the potential of the signal CK is low and the potential of the signal CKB is high), a low potential is applied to the first control terminal of the switch AS1, and a high potential is applied to the second control terminal of the switch AS1. This turns the switch AS1 off. During the same period, a high potential is applied to the control terminal of the switch ASX, turning the switch ASX on.

[0145] During the period T11 when the potential of the terminal CT is low, the switch ASX is in the on state, and the low potential output from the output terminal of the inverter IV1 is input to the input terminal of the inverter IVX via the switch ASX. At this time, the potential of the node SN1 is ideally low.

[0146] In particular, by using an IO transistor as the transistor IMN1 used in the switch ASX, the on-state current of the transistor IMN1 can be increased, which can speed up the change in potential of the node SN1 and increase the operating speed of the memory circuit BUC or the memory circuit BUCA.

[0147] Furthermore, when a low-level potential is input to the input terminal of the inverter IVX, a high-level potential is output from the output terminal of the inverter IVX. At this time, the potential of the node SN2 becomes a high-level potential. Note that during the period T11 in which the potential of the terminal CT is a low-level potential, the switch AS1 is in an off state, and therefore the high-level potential output from the output terminal of the inverter IVX does not reach the terminal IOT or the input terminal of the inverter IV1.

[0148] Next, during the period T11 when the low-level potential of the terminal CT transitions to a high-level potential (the period when the potential of the signal CK is high and the potential of the signal CKB is low), a high-level potential is applied to the first control terminal of the switch AS1, and a low-level potential is applied to the second control terminal of the switch AS1. This turns the switch AS1 on. During the same period, a low-level potential is applied to the control terminal of the switch ASX, turning the switch ASX off.

[0149] When the switch ASX is turned off, the low-level potential of the node SN1 is held by the capacitance element C1.

[0150] Furthermore, since the low-level potential is maintained at the node SN1, the inverter IVX continues to output a high-level potential from its output terminal. Furthermore, since the switch AS1 is in an on state, the high-level potential output from the output terminal of the inverter IVX is applied to the terminal IOT and the input terminal of the inverter IV1 via the switch AS1.

[0151] During a period T12, a low-level potential is input to the terminal IOT as the signal SIG, which causes the inverter IV1 to output a high-level potential to the output terminal.

[0152] During the period T12 when the potential of the terminal CT is low (the period when the potential of the signal CK is low and the potential of the signal CKB is high), a low potential is applied to the first control terminal of the switch AS1, and a high potential is applied to the second control terminal of the switch AS1. This turns the switch AS1 off. During the same period, a high potential is applied to the control terminal of the switch ASX, turning the switch ASX on.

[0153] During the period T12 when the potential of the terminal CT is low, the switch ASX is on, and therefore the high-level potential output from the output terminal of the inverter IV1 is input to the input terminal of the inverter IVX via the switch ASX. At this time, the potential of the node SN1 is ideally high. Furthermore, as described above, by using an IO transistor as the transistor IMN1 used for the switch ASX, the on-state current of the transistor IMN1 can be increased, thereby increasing the operating speed of the memory circuit BUC or the memory circuit BUCA.

[0154] Furthermore, when a high-level potential is input to the input terminal of the inverter IVX, a low-level potential is output from the output terminal of the inverter IVX. At this time, the potential of the node SN2 becomes a low-level potential. Note that during the period T12 when the potential of the terminal CT is a low-level potential, the switch AS1 is in an off state, so the low-level potential output from the output terminal of the inverter IVX does not reach the terminal IOT or the input terminal of the inverter IV1.

[0155] Next, during period T12, during which the low-level potential of terminal CT transitions to a high-level potential (the period during which signal CK is at a high-level potential and signal CKB is at a low-level potential), a high-level potential is applied to the first control terminal of switch AS1, and a low-level potential is applied to the second control terminal of switch AS1. This causes switch AS1 to be in the ON state. During the same period, a low-level potential is applied to the control terminal of switch ASX, causing switch ASX to be in the OFF state.

[0156] When the switch ASX is turned off, the high-level potential of the node SN1 is held by the capacitor C1.

[0157] Furthermore, since the high-level potential is maintained at the node SN1, the inverter IVX continues to output a low-level potential from its output terminal. Furthermore, since the switch AS1 is in an on state, the low-level potential output from the output terminal of the inverter IVX is applied to the terminal IOT and the input terminal of the inverter IV1 via the switch AS1.

[0158] During period T13, the potential of terminal CT becomes low level and the potential of signal CKB becomes high level. As a result, a low level potential is applied to the first control terminal of switch AS1 and a high level potential is applied to the second control terminal of switch AS1. This turns switch AS1 off. During the same period, a high level potential is applied to the control terminal of switch ASX, turning switch ASX on.

[0159] When the switch ASX is turned on, conduction is established between the output terminal of the inverter IV1 and the first terminal of the capacitor C1, and the potential output from the output terminal of the inverter IV1 is written to the first terminal (node ​​SN1) of the capacitor C1. In particular, as described above, in the period T14, the supply of power supply voltage to the memory circuit BUC or the memory circuit BUCA is stopped. In other words, in the period T13, the potential is backed up to the node SN1.

[0160] As described above, in the periods T11 to T13, a low-level potential is input to the terminal CT and a high-level potential is input to the terminal CBT, so that the memory circuits BUC and BUCA can hold a potential corresponding to the signal SIG at the node SN1. Furthermore, if the off-state current (sometimes referred to as leakage current) of the switch ASX is extremely small, the potential can be held for a long period of time. For example, as described above, by using an IO transistor as the transistor IMN1 used for the switch ASX, the off-state current of the switch ASX can be made extremely small.

[0161] During the period T14, as described above, the supply of power supply voltage to the memory circuit BUC or the memory circuit BUCA is stopped. Specifically, for example, a low-level potential or a ground potential is applied to the wiring VE2. The potentials of the signals CK and CKB transmitted to the terminals CT and CBT, respectively, are set to low. The potential of the signal SIG transmitted to the terminal IOT is also set to low.

[0162] Because a low-level potential is applied to the terminal CBT as the signal CKB, a low-level potential is applied to the control terminal of the switch ASX. Therefore, the switch ASX is turned off. This causes the node SN1 to be in a floating state, and the potential of the node SN1 becomes a potential (high-level potential in FIG. 1C ) corresponding to the signal SIG input to the terminal IOT in the period T13. Furthermore, this potential is held by the capacitor C1 in the period T14.

[0163] Furthermore, since a low-level potential is applied to the terminal CT as the signal CK and a low-level potential is applied to the terminal CBT as the signal CKB, the switch AS1 cannot be determined to be in an on or off state. Specifically, the amount of current flowing through the switch AS1 may be smaller than in the on state and larger than in the off state. Note that when the potentials of the terminal IOT and the node SN2 are equal, the amount of current flowing through the switch AS1 is zero.

[0164] In addition, in the period T14, a low-level potential is applied to each of the wirings VE1 and VE2, and therefore, each of the inverters IV1 and IVX stops operating. In particular, until the wiring VE2 transitions to a low-level potential, a low-level potential may be output from each of the output terminals of the inverters IV1 and IVX. In particular, even when a low-level potential is output from the output terminal of the inverter IV1, the low-level potential from the output terminal of the inverter IV1 does not reach the node SN1 because the switch ASX is in an off state.

[0165] Furthermore, since the switch AS1 is not determined to be in an on state or an off state, a low-level potential from the output terminal of the inverter IVX may be applied to the terminal IOT and the input terminal of the inverter IV1. Note that since the potential of the signal SIG in the period T14 is a low-level potential, no charge flows between the terminal IOT and the input terminal of the inverter IV1 and the output terminal of the inverter IVX (node ​​SN2), and therefore power consumption can be kept low.

[0166] In the period T15, the supply of power supply voltage to the memory circuit BUC or the memory circuit BUCA is resumed. As a result, a high-level potential is applied to the wiring VE2 and a low-level potential is applied to the wiring VE1. A clock signal is also applied to each of the terminals CT and CBT. Specifically, in the period T15, a high-level potential included in the clock signal is applied to the terminal CT, and a low-level potential included in the clock signal is applied to the terminal CBT.

[0167] In the period T15, a low-level potential is input to the control terminal of the switch ASX, so that the switch ASX is turned off, and the potential of the node SN1 is maintained at a high level. Also, a high-level potential is input to the first control terminal of the switch AS1, and a low-level potential is input to the second control terminal of the switch AS1, so that the switch AS1 is turned on.

[0168] Furthermore, a high-level potential is applied to the wiring VE2, and a low-level potential is applied to the wiring VE1, thereby restarting the operations of the inverters IV1 and IVX. For example, in a period T15, a high-level potential is input to the input terminal of the inverter IVX as the potential at the node SN1, and therefore a low-level potential is output to the output terminal of the inverter IVX. Furthermore, since the switch AS1 is in an on state, a low-level potential output from the output terminal of the inverter IVX is applied to the terminal IOT and the input terminal of the inverter IV1. Furthermore, since the potential at the terminal IOT or a low-level potential is input to the input terminal of the inverter IV1 as the potential at the output terminal of the inverter IVX (node ​​SN1), a high-level potential is output to the output terminal of the inverter IV1. Note that since the switch ASX is in an off state, the high-level potential output from the output terminal of the inverter IV1 does not reach the node SN1.

[0169] In the period T16, similarly to the period T11, a high-level potential is applied to the terminal IOT as the signal SIG. Furthermore, the transition of the potential of the clock signals transmitted to the terminals CT and CBT in the period T16 is also the same as that of the clock signal in the period T11. Therefore, the description of the period T11 can be referred to for the operation in the period T16. As a result, in the period T16, a low-level potential can be written to the node SN1, and a high-level potential can be output from the output terminal of the inverter IVX to the terminal IOT and the input terminal of the inverter IV1.

[0170] By performing the operations in the above periods T11 to T16, data corresponding to the signal SIG can be held in the memory circuit BUC or the memory circuit BUCA, and a potential corresponding to the data can be output from the memory circuit BUC or the memory circuit BUCA to the terminal IOT.

[0171] <Modification of Memory Circuit> Next, a modification of the memory circuit BUCA described above will be described.

[0172] The memory circuit BUCB shown in FIG. 3A is a modification of the memory circuit BUCA shown in FIG. 1B, and differs from the memory circuit BUCA in that a back gate is provided for each of the transistors IMN1 and IMN2.

[0173] 3A, the transistor IMN1 included in the switch ASX has a back gate, which is connected to the wiring VE1, for example. The transistor IMN2 included in the inverter IVX also has a back gate, which is connected to the wiring VE1, for example.

[0174] By providing back gates for the transistors IMN1 and IMN2 and applying a low-level potential to the back gates from the wiring VE1, the threshold voltages of the transistors IMN1 and IMN2 can be increased. Increasing the threshold voltages of the transistors IMN1 and IMN2 can reduce the off-state current of the transistors. Therefore, the transistor IMN1 can prevent fluctuations in the potential of the node SN1 due to the off-state current. Furthermore, the transistor IMN2 can prevent an increase in power consumption due to the off-state current.

[0175] 3A, the wirings connected to the back gates of the transistors IMN1 and IMN2 may be different from the wiring VE1. For example, in order to increase the on-state current of the transistors IMN1 and IMN2, it is preferable to lower the threshold voltages of these transistors. Therefore, the wirings connected to the back gates of the transistors IMN1 and IMN2 may be wirings that apply a high-level potential, instead of the wiring VE1.

[0176] Furthermore, wirings connected to the back gates of the transistors IMN1 and IMN2 may be wirings that apply different potentials depending on the operation of the memory circuit BUCB. For example, when the memory circuit BUCB writes data to the node SN1, a high-level potential is preferably applied to the back gate of the transistor IMN1 in order to increase the on-state current of the transistor IMN1. Increasing the on-state current of the transistor IMN1 can increase the driving speed of the memory circuit BUCB. For example, when the supply of power supply voltage to the memory circuit BUCB is stopped, a low-level potential is preferably applied to the back gate of the transistor IMN1 in order to reduce the off-state current of the transistor IMN1. By reducing the off-state current of the transistor IMN1, the potential of the node SN1 can be held for a long period of time.

[0177] Furthermore, for example, when the inverter IVX is operating normally, it is preferable to apply a high-level potential to the back gate of the transistor IMN2. By applying a high-level potential to the back gate of the transistor IMN2, the threshold voltage of the transistor IMN2 is lowered, thereby increasing the on-state current of the transistor IMN2. This allows the driving speed of the inverter IVX to be increased. Furthermore, for example, when the supply of power supply voltage to the memory circuit BUCB is stopped, it is preferable to apply a low-level potential to the back gate of the transistor IMN2.

[0178] The memory circuit BUCC shown in FIG. 3B is a circuit diagram illustrating the circuit configuration of the inverter IV1 and the switch AS1 in the memory circuit BUCB shown in FIG. 3A.

[0179] 3B, inverter IV1 includes, as an example, transistors SMP1 and SMN1. Switch AS1 includes transistors SMP3 and SMN3. As shown in FIG. 3B, transistors SMP1 and SMP3 are each shown as p-channel transistors, and transistors SMN1 and SMN3 are each shown as n-channel transistors. As shown in FIG. 3B, switch AS1 can be an analog switch using p-channel and n-channel transistors.

[0180] As an example, each of the transistors SMP1, SMN1, SMP3, and SMN3 can be a Si transistor.

[0181] The gates of the transistors SMP1 and SMN1 can be used as input terminals of the inverter IV1. The first terminals of the transistors SMP1 and SMN1 can be used as output terminals of the inverter IV1. The first terminals of the transistors SMN3 and SMP3 can be used as first terminals of the switch AS1. The second terminals of the transistors SMN3 and SMP3 can be used as second terminals of the switch AS1. The gate of the transistor SMN3 can be used as a first control terminal of the switch AS1, and the gate of the transistor SMP3 can be used as a second control terminal of the switch AS1.

[0182] From the above, it can be said that the gates of transistors SMP1 and SMN1 are connected to the terminal IOT, the first terminal of transistor SMN3, and the first terminal of transistor SMP3, respectively. Also, it can be said that the first terminals of transistors SMP1 and SMN1 are connected to the first terminal of transistor IMN1, respectively. The second terminal of transistor SMP1 is connected to wiring VE2, and the second terminal of transistor SMN1 is connected to wiring VE1.

[0183] From the above, it can be said that the second terminal of the transistor SMP3 and the second terminal of the transistor SMN3 are connected to the first terminal of the transistor SMP2 and the first terminal of the transistor IMN2, respectively. It can also be said that the gate of the transistor SMN3 is connected to the terminal CT, and the gate of the transistor SMP3 is connected to the terminal CBT.

[0184] <Flip-Flop 1 Using Memory Circuit> Next, a flip-flop using the above-described memory circuit will be described.

[0185] Fig. 4 is a circuit diagram showing an example of the configuration of a flip-flop including the memory circuit BUC shown in Fig. 1A. As shown in Fig. 4, by fabricating a flip-flop FFA including the memory circuit BUC, it is possible to realize a flip-flop that can automatically perform backup and restore.

[0186] The flip-flop FFA shown in FIG. 4 is a retention flip-flop that has the functions of latching data corresponding to the signal IPS, outputting data with the logic of the data inverted as the signal OPS, and backing up the data corresponding to the signal IPS using the memory circuit BUC.

[0187] In FIG. 4, the flip-flop FFA has an inverter IV2, an inverter IV3, an inverter IV4, an inverter IV5, a switch AS2, a switch AS3, and a switch AS4 in addition to the memory circuit BUC.

[0188] In FIG. 4, the description of the inverter IV1 shown in FIG. 1A can be referred to for each of the inverters IV2 to IV5.

[0189] 4, the description of the switch AS1 shown in Fig. 1A can be referred to for each of the switches AS2 to AS4. In particular, in Fig. 4, each of the switches AS2 to AS4 will be described as an analog switch having a first control terminal and a second control terminal, similar to the switch AS1 in Fig. 1A.

[0190] The input terminal of inverter IV2 is connected to wiring IL, and the output terminal of inverter IV5 is connected to wiring OL. The first terminal of switch AS2 is connected to the output terminal of inverter IV2, and the second terminal of switch AS2 is connected to the input terminal of inverter IV3 and the first terminal of switch AS3. The output terminal of inverter IV3 is connected to the first terminal of switch AS4 and the input terminal of inverter IV4. The output terminal of inverter IV4 is connected to the second terminal of switch AS3. The second terminal of switch AS4 is connected to the terminal IOT of the memory circuit BUC and the input terminal of inverter IV5.

[0191] A wiring CKL is connected to each of the first control terminal of the switch AS2, the second control terminal of the switch AS3, the second control terminal of the switch AS4, and the terminal CT of the memory circuit BUC. A wiring CKL is also connected to each of the second control terminal of the switch AS2, the first control terminal of the switch AS3, the first control terminal of the switch AS4, and the terminal CBT of the memory circuit BUC.

[0192] 4, the connection point between the second terminal of the switch AS2, the input terminal of the inverter IV3, and the first terminal of the switch AS3 is indicated as node SN3, and the connection point between the output terminal of the inverter IV3, the first terminal of the switch AS4, and the input terminal of the inverter IV4 is indicated as node SN4.

[0193] The wiring IL functions as a wiring for transmitting an input signal to the flip-flop FFA. The wiring OL functions as a wiring for transmitting an output signal output from the flip-flop FFA. Note that FIG. 4 shows a signal IPS as the input signal and a signal OPS as the output signal. Note that the signals IPS and OPS can be treated as the signal SIG shown in FIG. 1A and the like.

[0194] Similarly to the inverter IV1, each of the inverters IV2 to IV5 is connected to a wiring VE2 that supplies a high power supply potential and a wiring VE1 that supplies a low power supply potential.

[0195] Furthermore, the flip-flop FFA shown in Fig. 4 may be changed to the flip-flop FFB shown in Fig. 5. The flip-flop FFB in Fig. 5 differs from the flip-flop FFA in Fig. 4 in that an inverter IVC is newly provided and that the wiring CKLB is not provided.

[0196] An input terminal of the inverter IVC is connected to a wiring CKL, and an output terminal of the inverter IVC is connected to a second control terminal of the switch AS2, a first control terminal of the switch AS3, a first control terminal of the switch AS4, and a terminal CBT of the memory circuit BUC. The inverter IVC is also connected to a wiring VE2 that applies a high power supply potential and a wiring VE1 that applies a low power supply potential.

[0197] 5, the inverter IVC receives the signal CK, which is used as a clock signal, from the input terminal, generates a signal by inverting the logic of the signal CK, and outputs it to the output terminal. That is, the inverter IVC generates the signal CKB as a signal by inverting the logic of the signal CK.

[0198] 5, by providing an inverter IVC, it is not necessary to route the wiring CKLB connected to the flip-flop FFB. This eliminates the need to provide the wiring CKLB, and therefore it is possible to reduce the circuit area of ​​a semiconductor device including the flip-flop FFB.

[0199] The flip-flop FFC in FIG. 6 is a circuit diagram in which the memory circuit BUCC in FIG. 3B is applied to the memory circuit BUC in the flip-flop FFB in FIG. 5, and the circuit configurations of the inverters IV2 to IV5, the inverter IVC, and the switches AS2 to AS4 are shown.

[0200] Each of the inverters IV2 to IV5 and the inverter IVC can be configured with one p-channel transistor and one n-channel transistor, similar to the inverter IV1 included in the memory circuit BUCC of FIG. 3B. Each of the p-channel transistor and the n-channel transistor can be a Si transistor. Regarding the connection configuration of each of the p-channel transistor and the n-channel transistor included in each of the inverters IV2 to IV5 and the inverter IVC, the description of the memory circuit BUCC of FIG. 3B can be referred to.

[0201] Each of the switches AS2 to AS4 can be configured with one p-channel transistor and one n-channel transistor, similar to the switch AS1 included in the memory circuit BUCC in Figure 3B. Each of the p-channel transistor and the n-channel transistor can be a Si transistor. For the connection configuration of each of the p-channel transistor and the n-channel transistor included in each of the switches AS2 to AS4, refer to the description of the memory circuit BUCC in Figure 3B.

[0202] 7 shows a timing chart illustrating an operation example of the flip-flop FFA in FIG. 4. Specifically, the timing chart illustrates potential changes of the wiring VE2, the wiring VE1, the wiring CKL, the wiring CKLB, the wiring IL, the node SN3, the node SN4, the terminal IOT, the node SN1, the node SN2, and the wiring OL during the periods T20 to T26. In addition, in the timing chart, a high-level potential is indicated as "High," and a low-level potential is indicated as "Low."

[0203] 7 is obtained by partially modifying and adding to the timing chart shown in Fig. 1C. Specifically, the timing chart of Fig. 7 includes the contents of the timing chart of the memory circuit BUC shown in Fig. 1C.

[0204] For example, each of the periods T21 to T26 shown in FIG. 7 includes potential changes of some of the terminals, wirings, and nodes in the periods T11 to T16 shown in FIG. 1C.

[0205] 7 includes, in addition to the potential change at the terminal CT shown in Fig. 1C, the potential changes at the first control terminal of the switch AS2, the second control terminal of the switch AS3, and the second control terminal of the switch AS4. Also, the potential change at the wiring CKLB shown in Fig. 7 includes, in addition to the potential change at the terminal CBT shown in Fig. 1C, the potential changes at the second control terminal of the switch AS2, the first control terminal of the switch AS3, and the first control terminal of the switch AS4.

[0206] Moreover, the potential changes at the terminal IOT, the node SN1, and the node SN2 shown in FIG. 7 are equal to the potential changes at the terminal IOT, the node SN1, and the node SN2 shown in FIG. 1C.

[0207] In particular, the period T24 in the timing chart of FIG. 7 is a period during which the supply of power supply voltage to the flip-flop FFA is stopped, similar to the period T14 in the timing chart of FIG. 1C.

[0208] In the operation example shown in the timing chart of FIG. 7 , when a high-level potential is applied to the wiring CKL and a low-level potential is applied to the wiring CKLB, the flip-flop FFA acquires first data transmitted from the wiring IL and writes the data to the nodes SN3 and SN4. Next, when the potential of the wiring CKL transitions from a high-level potential to a low-level potential and the potential of the wiring CKLB transitions from a low-level potential to a high-level potential, the first data is held in the inverter loop of the inverters IV3 and IV4. The first data is also written to the memory circuit BUC. The first data is output to the wiring OL.

[0209] When the potential of the wiring CKL transitions from low to high again and the potential of the wiring CKLB transitions from high to low again, the flip-flop FFA acquires the second data transmitted from the wiring IL at this timing and writes it to the nodes SN3 and SN4. The flip-flop FFA also holds the first data in the memory circuit BUC. The flip-flop FFA also continues to output the first data held in the memory circuit BUC to the wiring OL.

[0210] The above-mentioned specific operations will be explained below.

[0211] In the period T20, when a high-level potential is applied to the wiring CKL and a low-level potential is applied to the wiring CKLB, the switches AS2 and AS1 are turned on, the switches AS3 and AS4 are turned off, and the switch ASX is turned off.

[0212] When a high-level potential is applied to the wiring CKL and a low-level potential is applied to the wiring CKLB, a high-level potential is applied to the wiring IL as first data, and therefore a low-level potential is output from the output terminal of the inverter IV2. Furthermore, because the switch AS2 is on, the low-level potential output from the output terminal of the inverter IV2 reaches the node SN3. Furthermore, because a low-level potential is input to the input terminal of the inverter IV3, a high-level potential is output from the output terminal of the inverter IV3. In other words, the potential of the node SN4 becomes a high-level potential. As a result, the first data is written to the nodes SN3 and SN4 of the flip-flop FFA.

[0213] Since the switch AS4 is in an OFF state, the high-level potential output from the output terminal of the inverter IV3 does not reach the terminal IOT, the input terminal of the inverter IV1, or the input terminal of the inverter IV5.

[0214] At the timing when the period T20 transitions to the period T21, the high-level potential of the wiring CKL transitions to the low-level potential, and the low-level potential of the wiring CKLB transitions to the high-level potential. As a result, the switches AS2 and AS1 are switched off, the switches AS3 and AS4 are switched on, and the switch ASX is switched on.

[0215] When switch AS2 is turned off and switches AS3 and AS4 are turned on, the low level potential of node SN3 and the high level potential of node SN4 are held as first data by the inverter loop of inverters IV3 and IV4.

[0216] Furthermore, because the switch AS4 is in an on state, a high-level potential output from the output terminal of the inverter IV3 is transmitted as first data to the terminal IOT, the input terminal of the inverter IV1, and the input terminal of the inverter IV5. Specifically, the potentials of the terminal IOT, the input terminal of the inverter IV1, and the input terminal of the inverter IV5 become high-level potentials that are approximately equal to that of the node SN4.

[0217] Since a high-level potential is input to the input terminal of the inverter IV1, a low-level potential is output to the output terminal of the inverter IV1. Furthermore, since the switch ASX is in the on state, the low-level potential output from the output terminal of the inverter IV1 reaches the node SN1 and is written as the first data to the first terminal of the capacitive element C1. Furthermore, since a low-level potential is applied to the input terminal of the inverter IVX, a high-level potential is output from the output terminal of the inverter IVX. In other words, the potential of the node SN2 becomes a high-level potential. Furthermore, since the switch AS1 is in the off state, the high-level potential output from the output terminal of the inverter IVX does not reach the terminal IOT or the input terminal of the inverter IV1.

[0218] Furthermore, since a high-level potential is input to the input terminal of the inverter IV5, a low-level potential is output as the first data to the output terminal of the inverter IV5, which causes the potential of the wiring OL to become a low-level potential, and the first data is output to the wiring OL.

[0219] In the period T21, when the potential of the wiring CKL transitions from a low level to a high level and the potential of the wiring CKLB transitions from a high level to a low level, the switches AS2 and AS1 are turned on, the switches AS3 and AS4 are turned off, and the switch ASX is turned off.

[0220] While a high-level potential is applied to the wiring CKL and a low-level potential is applied to the wiring CKLB, a transition from a high-level potential to a low-level potential occurs in the wiring IL. The flip-flop FFA acquires data transmitted to the wiring IL at the timing when the potential of the wiring CKL transitions from a high-level potential to a low-level potential and the potential of the wiring CKLB transitions from a low-level potential to a high-level potential. Therefore, in the operation example of the timing chart of FIG. 7 , the flip-flop FFA acquires a low-level potential from the wiring IL as the second data. Therefore, the low-level potential from the wiring IL is input to the input terminal of the inverter IV2, and a high-level potential is output from the output terminal of the inverter IV2.

[0221] Furthermore, because switch AS2 is in the on state, the high-level potential output from the output terminal of inverter IV2 reaches node SN3. Furthermore, because a high-level potential is input to the input terminal of inverter IV3, a low-level potential is output to the output terminal of inverter IV3. In other words, the potential of node SN4 becomes low. As a result, second data is written to nodes SN3 and SN4 of flip-flop FFA.

[0222] Since the switch AS4 is in an OFF state, the high-level potential output from the output terminal of the inverter IV3 does not reach the terminal IOT, the input terminal of the inverter IV1, or the input terminal of the inverter IV5.

[0223] In the period T21, the switch ASX is turned off, and the node SN1 of the memory circuit BUC is brought into a floating state. In other words, a low-level potential is held at the node SN1 of the memory circuit BUC as the first data.

[0224] In addition, in period T21, the switch AS1 is turned on, and thus a high-level potential output from the output terminal of the inverter IVX is supplied as first data to the terminal IOT, the input terminal of the inverter IV1, and the input terminal of the inverter IV5. Also, since a high-level potential is input to the input terminal of the inverter IV1, a high-level potential is output to the output terminal of the inverter IV1. Note that, since the switch ASX is turned off, the high-level potential output from the output terminal of the inverter IV1 does not reach the node SN1.

[0225] Furthermore, since the high-level potential is input to the input terminal of the inverter IV5, the low-level potential continues to be output as the first data to the output terminal of the inverter IV5, which causes the potential of the wiring OL to become low, and the first data is output to the wiring OL.

[0226] As described above, when a clock signal is input to each of the wirings CKL and CKLB, the flip-flop FFA can acquire the first data transmitted from the wiring IL and write a potential corresponding to the first data to the nodes SN1, SN3, and SN4.

[0227] Furthermore, the flip-flop FFA can almost automatically hold the first data in the memory circuit BUC while the second data, which is input after the first data, is being written to the node SN3 and the node SN4, and can output the first data to the wiring OL during that time.

[0228] During period T22, when the potential of wiring CKL is at a high level potential and the potential of wiring CKLB is at a low level potential, similar to period T21, flip-flop FFA acquires a low level potential as the second data from wiring IL, writes a high level potential to node SN3, and writes a low level potential to node SN4. Also, at the timing of transitioning from period T22 to period T23, when the potential of wiring CKL transitions from a high level potential to a low level potential and the potential of wiring CKLB transitions from a low level potential to a high level potential, the low level potential written to node SN4 is input to the input terminal of inverter IV5, and a high level potential is output as the second data from the output terminal of inverter IV5 to wiring OL. At this time, the low level potential written to node SN4 is input to the input terminal of inverter IV1, and a high level potential is output as the second data from the output terminal of inverter IV1 to node SN1. Thereby, a high level potential is written to memory circuit BUC as the second data.

[0229] In period T24, as described above, the supply of the power voltage to memory circuit BUC or memory circuit BUC A is stopped. Specifically, for example, a low level potential or a ground potential is applied to wiring VE2. Also, the potentials of signals CK and signal CKB transmitted to each of wiring CKL and wiring CKLB are set to a low level potential. Also, the potential of signal SIG transmitted to terminal IOT is also set to a low level potential.

[0230] Regarding the operation of memory circuit BUC in period T24, reference can be made to the operation of memory circuit BUC in period T14 of the timing chart in FIG. 1C. Therefore, in period T24, memory circuit BUC continues to hold a high level potential as the second data at node SN1.

[0231] Since the wiring CKL is supplied with a low-level potential as the signal CK and the wiring CKLB is supplied with a low-level potential as the signal CKB, the switches AS2 to AS4 are not limited to being in an on state or an off state. Specifically, the amount of current flowing through each of the switches AS2 to AS4 may be smaller than in the on state and larger than in the off state.

[0232] In addition, in the period T24, a low-level potential is applied to each of the wirings VE1 and VE2, and therefore, each of the inverters IV2 to IV5 stops operating. Note that at this time, a low-level potential may be output from each of the output terminals of the inverters IV2 to IV5. Therefore, in the period T24, the potentials of the nodes SN3 and SN4 become low-level potentials. That is, the second data written to the nodes SN3 and SN4 in the period T23 is erased in this period T24.

[0233] As described above, in the flip-flop FFA, the supply of the power supply voltage is stopped during the period T24, and the data written to the nodes SN3 and SN4 is erased.

[0234] In the period T25, the supply of power supply voltage to the memory circuit BUC is resumed. As a result, a high-level potential is applied to the wiring VE2 and a low-level potential is applied to the wiring VE1. A clock signal is also applied to each of the terminals CT and CBT. Specifically, in the period T25, a high-level potential included in the clock signal is applied to the terminal CT, and a low-level potential included in the clock signal is applied to the terminal CBT.

[0235] As a result, the switches AS2 and AS1 are turned on, the switches AS3 and AS4 are turned off, and the switch ASX remains off.

[0236] Note that the operation of the memory circuit BUC in the period T25 can be seen from the operation of the memory circuit BUC in the period T15 in the timing chart of FIG. 1C . Therefore, in the period T25, in the memory circuit BUC, a high-level potential as the second data held in the node SN1 is input to the input terminal of the inverter IVX, and a low-level potential is output from the output terminal of the inverter IVX. Therefore, the potential of the node SN2 becomes a low-level potential. Furthermore, the low-level potential output from the output terminal of the inverter IVX is input to the inverter IV5 via the switch AS1 and the terminal IOT. As a result, a high-level potential is output as the second data from the output terminal of the inverter IV5 to the wiring OL. In other words, the second data is restored from the memory circuit BUC and output to the wiring OL.

[0237] Furthermore, in the period T25, because the switch AS2 is in the on state, the flip-flop FFA acquires a high-level potential as the third data from the wiring IL. As a result, a high-level potential is input to the input terminal of the inverter IV2, and a low-level potential is output from the output terminal of the inverter IV2. Therefore, the potential of the node SN3 becomes a low-level potential. Furthermore, because a low-level potential is input to the input terminal of the inverter IV3, a high-level potential is output from the output terminal of the inverter IV3. Therefore, the potential of the node SN4 becomes a high-level potential. As a result, in the flip-flop FFA, a low-level potential is held at the node SN3 and a high-level potential is held at the node SN4 as the third data.

[0238] In the period T26, when a low-level potential is applied to the wiring CKL and a high-level potential is applied to the wiring CKLB, a high-level potential is applied to the wiring IL. At this time, the potentials of the wirings CKL, CKLB, IL, and the nodes SN1 to SN4 are equal to the potentials of the wirings CKL, CKLB, IL, and the nodes SN1 to SN4 in the period T21. Therefore, for the operation of the flip-flop FFA when a low-level potential is applied to the wiring CKL and a high-level potential is applied to the wiring CKLB in the period T26, the description of the operation of the flip-flop FFA when a low-level potential is applied to the wiring CKL and a high-level potential is applied to the wiring CKLB in the period T21 can be referred to.

[0239] Therefore, a low-level potential is written to the node SN1 of the memory circuit BUC as the third data, and the low-level potential is output from the flip-flop FFA to the wiring OL as the third data.

[0240] In addition, in the period T26, when a high-level potential is applied to the wiring CKL and a low-level potential is applied to the wiring CKLB, the switches AS2 and AS1 are turned on, the switches AS3 and AS4 are turned off, and the switch ASX is turned off.

[0241] Note that the operation of the memory circuit BUC in the period T26 can be seen from the operation of the memory circuit BUC in the period T16 in the timing chart of FIG. 1C . Therefore, in the period T26, in the memory circuit BUC, the low-level potential held at the node SN1 as the third data is input to the input terminal of the inverter IVX, and a high-level potential is output from the output terminal of the inverter IVX. Therefore, the potential of the node SN2 becomes a high-level potential. Furthermore, the high-level potential output from the output terminal of the inverter IVX is input to the inverter IV5 via the switch AS1 and the terminal IOT. As a result, a low-level potential is output as the second data from the output terminal of the inverter IV5 to the wiring OL.

[0242] Furthermore, in the period T26, because the switch AS2 is in the on state, the flip-flop FFA acquires a high-level potential as the fourth data from the wiring IL. As a result, a high-level potential is input to the input terminal of the inverter IV2, and a low-level potential is output from the output terminal of the inverter IV2. Therefore, the potential of the node SN3 becomes a low-level potential. Furthermore, because a low-level potential is input to the input terminal of the inverter IV3, a high-level potential is output from the output terminal of the inverter IV3. Therefore, the potential of the node SN4 becomes a high-level potential. As a result, in the flip-flop FFA, a low-level potential is held at the node SN3 and a high-level potential is held at the node SN4 as the fourth data.

[0243] As described above, when the flip-flop FFA outputs data written to the nodes SN3 and SN4 to the wiring OL, the flip-flop FFA can simultaneously write the data to the memory circuit BUC. Furthermore, by cutting off the power supply voltage to the flip-flop FFA, the data written to the nodes SN3 and SN4 is erased. Furthermore, when the supply of power to the flip-flop FFA is resumed, the data written to the memory circuit BUC is restored and the data is output to the wiring OL. That is, the semiconductor device of one embodiment of the present invention can automatically back up data. Furthermore, due to the data backup, even if the power supply voltage is stopped and then resupplied, the semiconductor device can continue to output the data held before the power supply voltage was stopped to the wiring OL after the power supply voltage is resupplied.

[0244] <Flip-Flop 2 Using Memory Circuit> In the retention flip-flops shown in FIGS. 4 to 6 , the logic of data corresponding to the signal IPS and the logic of data corresponding to the signal OPS are inverted to each other. Specifically, for example, in the retention flip-flop shown in FIG. 4 described above, in the operation of the timing chart in FIG. 7 , the first data is latched as a high potential at the wiring IL, a low potential at the node SN3, and a high potential at the node SN4. The first data is latched as a high potential at the terminal IOT of the memory circuit BUC, a low potential at the node SN1, and a low potential at the wiring OL. The retention flip-flop according to one embodiment of the present invention is not limited thereto, and may be configured such that the logic of data corresponding to the signal IPS and the logic of data corresponding to the signal OPS are the same.

[0245] For example, the flip-flop FFD shown in Fig. 8 is a retention flip-flop in which an inverter IV6 is newly added to the flip-flop FFB of Fig. 5. Specifically, the input terminal of the inverter IV6 is connected to the output terminal of the inverter IV3 and the input terminal of the inverter IV4, and the output terminal of the inverter IV6 is connected to the first terminal of the switch AS4. Also, in Fig. 8, the connection point between the input terminal of the inverter IV6, the output terminal of the inverter IV3, and the input terminal of the inverter IV4 is designated as node SN4.

[0246] For other connection configurations, refer to the description of the connection configuration of the flip-flop FFB in FIG.

[0247] By using the flip-flop FFD of FIG. 8, the logic of the data input as the signal IPS can be made to match the logic of the data input as the signal OPS.

[0248] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0249] Embodiment 2 In this embodiment, indium oxide that can be used as a metal oxide for a channel formation region of the IO transistor according to one embodiment of the present invention described in the above embodiment will be described.

[0250] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0251] Indium oxide is a semiconductor material having physical properties that are completely different from oxide semiconductors such as In—Ga—Zn oxide (hereinafter referred to as IGZO, zinc oxide, etc.).

[0252] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 9A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 9B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0253] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 9B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 9A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 9A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 9A.

[0254] 9A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0255] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0256] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0257] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0258] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 9A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0259] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0260] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0261] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0262] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0263] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0264] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0265] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0266] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0267] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0268] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 9C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0269] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0270] 9C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the film and is released as water molecules.

[0271] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0272] The table below shows the properties of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in the table below, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, because the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in the table below, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0273]

[0274] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0275] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0276] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0277] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0278] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0279] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0280] Embodiment 3 In this embodiment, a configuration example of a memory circuit or a flip-flop, which is the semiconductor device described in Embodiment 1, will be described.

[0281] 10 is a perspective view schematically illustrating the semiconductor device described in the above embodiment. The semiconductor device SDV shown in FIG. 10 includes, as an example, a circuit layer SICL and a circuit layer IOCL. The circuit layer SICL is located below the circuit layer IOCL.

[0282] The stacked structure of the circuit layer SICL and the circuit layer IOCL can be fabricated by directly forming the circuit layer IOCL on the circuit layer SICL, or by mounting the circuit layer IOCL on a substrate on which circuit elements such as transistors and capacitors are provided.

[0283] The circuit layer SICL can be formed by, for example, providing circuit elements such as transistors and capacitors on a substrate. The substrate can be a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Other than semiconductor substrates, examples of usable substrates include an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Another example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Another example is polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or paper. If the manufacturing process of the semiconductor device SDV includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate.

[0284] In this embodiment, unless otherwise specified, the substrate included in the circuit layer SICL will be described as a semiconductor substrate having silicon.

[0285] By using a semiconductor substrate containing silicon as the substrate included in the circuit layer SICL and separately creating a low-resistance region and a semiconductor region in the semiconductor substrate, Si transistors can be formed in the circuit layer SICL. Furthermore, when the circuit layer IOCL is formed directly on top of the circuit layer SICL, it is preferable that the circuit layer IOCL includes an IO transistor. Since IO transistors can be formed not only on a semiconductor substrate but also on an insulating substrate, a conductive substrate, or even a conductive film, an insulating film, or a semiconductor film, they can be easily provided on the semiconductor substrate (on the circuit layer SICL) on which Si transistors are formed. As a result, the semiconductor device SDV can be configured to have a stacked structure of Si transistors and IO transistors.

[0286] 6 may be provided in the circuit layer IOCL. The transistors SMP1 to SMP3, SMN1, and SMN3 included in the memory circuit BUCC may be provided in the circuit layer SICL. The Si transistors included in the inverters IV2 to IV5, the inverter IVC, and the switches AS2 to AS4 may be provided in the circuit layer SICL.

[0287] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the circuit layer IOCL and the substrate is mounted on the circuit layer SICL, flip-chip bonding or wire bonding can be used. Alternatively, a first bonding layer may be provided on the circuit layer SICL side, a second bonding layer may be provided on the substrate of the circuit layer IOCL, and the first and second bonding layers may be bonded together using one or both of a surface activated bonding method and a hydrophilic bonding method, thereby mounting the circuit layer IOCL on the circuit layer SICL. For example, Cu-Cu (copper-copper) direct bonding may be used, in which copper (Cu) is used as the conductor contained in each of the first and second bonding layers and copper is bonded to each other.

[0288] <Example of layout of semiconductor device> Fig. 11A is a schematic plan view showing an example of a circuit configuration included in the circuit layer SICL shown in Fig. 10, and Fig. 11B is a schematic plan view showing an example of a circuit configuration included in the circuit layer IOCL shown in Fig. 10. In particular, each of Fig. 11A and Fig. 11B is an example of a schematic plan view showing the circuit configuration of a memory circuit BUCC included in the flip-flop FFC shown in Fig. 6.

[0289] 11A, the circuit layer SICL includes, for example, a conductive layer 131, a conductive layer 132, a conductive layer 135, conductive layers 136[1] to 136[5], a semiconductor region 171, a low-resistance region 172, a semiconductor region 173, and a low-resistance region 174. In order to clearly show the schematic plan view, insulating layers included in the circuit layer SICL are not shown in FIG.

[0290] 11B, the circuit layer IOCL includes, for example, a conductive layer 231, a conductive layer 232, a conductive layer 233, a conductive layer 235, a conductive layer 236, a conductive layer 237, conductive layers 136[1] to 136[5], and a semiconductor layer 251. Note that, in order to clearly show the schematic plan view, insulating layers included in the circuit layer IOCL are not shown in FIG.

[0291] 11A , consider a case where the channel formation regions of transistors SMN1, SMP1, SMP2, SMN3, and SMP3 are included in a single-crystal substrate made of silicon. That is, consider a case where transistors SMN1, SMP1, SMP2, SMN3, and SMP3 are each Si transistors. In this case, a circuit pattern including semiconductor region 171, low-resistance region 172, semiconductor region 173, and low-resistance region 174 can be formed on the single-crystal substrate by performing exposure and development processes, etching processes, resist stripping and cleaning processes, etc. Furthermore, semiconductor region 171, low-resistance region 172, semiconductor region 173, and low-resistance region 174 can be separately formed by adjusting the amount of carriers injected.

[0292] 11A , the transistors SMN1, SMP1, SMP2, SMN3, and SMP3 each have a fin-type transistor structure. A fin-type transistor structure is one in which, in a plan view, the channel width d5p, d5n, or d7p of the semiconductor region 173 is shorter than the channel width d0 of the low-resistance region 174. A fin-type transistor structure is one in which, in a cross-sectional view in the channel width direction, the semiconductor region 173 has a convex shape and the conductive layer 231 is formed so as to cover the convex shape of the semiconductor region 173. As described above, by forming the semiconductor region 173 to have a convex shape and the conductive layer 131 so as to cover the convex shape, the effective channel width of the semiconductor region 173 can be increased, thereby improving on-state characteristics. Furthermore, the contribution of the electric field from the conductive layer 131 to the inside of the semiconductor region 173 is increased, thereby reducing the off-state current. For this reason, by applying fin-type transistors to the transistors SMN1, SMP1, SMP2, SMN3, and SMP3, the on-characteristics of these transistors can be improved and the off-current can be reduced. Note that fin-type transistors will be described in detail later.

[0293] 11A, one or more selected from the transistors SMN1, SMP1, SMP2, SMN3, and SMP3 may be IO transistors instead of Si transistors. Also, the low resistance region included in the IO transistor may include a conductive layer.

[0294] For example, the conductive layer 131 is provided above the semiconductor region 171, the low-resistance region 172, the semiconductor region 173, or the low-resistance region 174. The conductive layer 131 also functions as a wiring and as the gates of the transistors SMN1, SMP1, SMP2, SMN3, and SMP3.

[0295] For example, the conductive layer 132 is provided above the semiconductor region 171 , the low resistance region 172 , the semiconductor region 173 , the low resistance region 174 , or the conductive layer 131 .

[0296] The conductive layer 132 functions as a terminal and / or a wiring. For example, a part of the conductive layer 132 has a region as a terminal IOT. A part of the conductive layer 131 that does not have a region as the terminal IOT may extend as a wiring VE1 or a wiring VE2.

[0297] The conductive layer 131 also functions as a terminal and / or wiring. For example, a portion of the conductive layer 131 has a region serving as a terminal CT, and another portion of the conductive layer 131 has a region serving as a terminal CBT. Although not shown in FIG. 11A , the conductive layer 131 having a region serving as a terminal CT may extend as wiring CKL. Similarly, the conductive layer 131 having a region serving as a terminal CBT may extend as wiring CKLB.

[0298] An insulating layer (not shown) functioning as a first interlayer film is provided between the semiconductor region 171, the low-resistance region 172, the semiconductor region 173, the low-resistance region 174, or the conductive layer 131 and the conductive layer 132. Openings are provided in a partial region of the insulating layer where the low-resistance region 172 and the conductive layer 132 overlap, a partial region of the insulating layer where the low-resistance region 174 and the conductive layer 132 overlap, and a partial region of the insulating layer where the conductive layer 131 and the conductive layer 132 overlap. An opening is also provided in a region of the insulating layer that overlaps with a conductive layer 136[2] (described later). A conductive layer 135 is embedded in these openings.

[0299] By embedding the conductive layer 135 in the opening of the insulating layer, for example, charge can move between the low-resistance region 172 and the conductive layer 132 via the conductive layer 135, and charge can move between the low-resistance region 174 and the conductive layer 132 via the conductive layer 135. Furthermore, charge can move between the conductive layer 131 and the conductive layer 132 via the conductive layer 135. That is, in FIG. 11A , the conductive layer 135 functions as a contact plug.

[0300] Furthermore, an insulating layer (not shown) functioning as a second interlayer film is provided above each of the semiconductor region 171, the low-resistance region 172, the semiconductor region 173, the low-resistance region 174, the conductive layer 131, and the conductive layer 132. In particular, an opening is provided in the insulating layer located on a portion of the upper surface of the conductive layer 131, and the conductive layer 136[3] and the conductive layer 136[4] are embedded in the opening. Furthermore, an opening is also provided in the insulating layer located on a portion of the upper surface of the conductive layer 132, and the conductive layer 136[1], the conductive layer 136[2], and the conductive layer 136[3] are embedded in the opening.

[0301] Each of the conductive layers 136[1] to 136[5] functions as a contact plug for establishing electrical connection with a circuit element included in the circuit layer IOCL.

[0302] 11B , each of the transistor IMN1 and the transistor IMN2 includes an island-shaped insulating layer, a semiconductor layer 251 formed on the insulating layer, a conductive layer 231 formed on the semiconductor layer 251, a gate insulating film formed on the semiconductor layer 251, and a conductive layer 232 formed on the gate insulating film. Each of the transistor IMN1 and the transistor IMN2 can have a GL (Gate Last) structure (also referred to as a TGSA (Trench Gate Self Align) or Top Gate Self Align) structure) described later.

[0303] For example, the semiconductor layer 251 is located below the conductive layers 231 and 232. For example, the conductive layer 235 is located above the conductive layers 231 and 232. For example, the conductive layer 233 is located above the conductive layer 235. For example, the conductive layer 236 is located above the conductive layer 235. For example, the conductive layer 237 is located above the conductive layer 236. The order of formation can be as follows: first, the semiconductor layer 251, second, the conductive layer 231, third, the conductive layer 232, fourth, the conductive layer 235, fifth, and sixth, the conductive layer 236.

[0304] In the circuit layer IOCL, a part of the conductive layer 231 functions as the source or drain of each of the transistors IMN1 and IMN2, for example.

[0305] In the circuit layer IOCL, a part of the conductive layer 232 functions as the gates of the transistor IMN1 and the transistor IMN2, for example.

[0306] The conductive layer 232 also functions as wiring for electrical connection with the circuit elements included in the circuit layer SICL. For this reason, the conductive layer 232 is connected to the conductive layer 136[3] that functions as a contact plug, for example.

[0307] An insulating layer can be provided between the semiconductor layer 251 and the conductive layer 232. In particular, the insulating layer may function as a gate insulating film of each of the transistor IMN1 and the transistor IMN2.

[0308] In addition, in the circuit layer IOCL, a part of the conductive layer 233 functions as one of a pair of electrodes of the capacitance element C1, for example. The conductive layer 233 also functions as wiring for electrical connection with the circuit elements included in the circuit layer SICL. Therefore, the conductive layer 233 is connected to the conductive layers 136[1], 136[2], 136[4], and 136[5], which function as contact plugs, for example.

[0309] An insulating layer (not shown) functioning as a third interlayer film is provided between the conductive layer 231 and the conductive layer 233. An opening is provided in a partial region of the insulating layer where the conductive layer 231 and the conductive layer 233 overlap each other, and a conductive layer 235 is embedded in the opening as a contact plug for connecting the conductive layer 231 and the conductive layer 233 to each other.

[0310] In addition, in the circuit layer IOCL, a part of the conductive layer 237 functions as the other of the pair of electrodes of the capacitor C1, for example.

[0311] An insulating layer (not shown) functioning as a fourth interlayer film is provided between the conductive layer 233 and the conductive layer 237. An opening is provided in a partial region of the insulating layer where the conductive layer 233 and the conductive layer 237 overlap each other, and a conductive layer 236 is embedded in the opening as a contact plug for connecting the conductive layer 233 and the conductive layer 237 to each other.

[0312] The conductive layers 131, 132, and 135 included in the circuit layer SICL, the conductive layers 231, 232, 233, 235, 236, and 237 included in the circuit layer IOCL, and the conductive layers 136[1] to 136[5] included in both the circuit layer SICL and the circuit layer IOCL each have a part functioning as a wiring, and therefore, it is preferable to use a material with high conductivity. Note that specific materials with high conductivity will be described later.

[0313] Each of the above-described conductive layers can be formed by, for example, lithography. Specifically, for example, when forming the conductive layer 231, a conductive material to be the conductive layer 231 can be formed by one or more methods selected from a sputtering method, a chemical vapor deposition (CVD) method, a pulsed laser deposition (PLD) method, and an atomic layer deposition (ALD) method, and then a desired pattern can be formed by lithography. Furthermore, conductive layers, semiconductor layers, and insulating layers other than the conductive layer 231 can also be formed by the same methods as above.

[0314] In this specification, the lithography method includes, for example, photolithography, ion beam lithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, and nanoimprinting.

[0315] Furthermore, an insulating layer can be provided between the conductive layer 233 and the conductive layer 237. In particular, in the region where the capacitor C1 is provided, the insulating layer formed so as to overlap between the conductive layer 233 and the conductive layer 237 is preferably an insulating layer that functions as a dielectric in the capacitor C1.

[0316] 11A, the capacitor C1 has a parallel plate structure. In addition, the conductive layers 233 and 237 are provided at higher positions than other conductive layers, so that an area for providing the capacitor can be easily secured, and the circuit area of ​​the memory circuit BUCC can be reduced.

[0317] 6, there is a portion where the transistors SMP2 and SMP3 are connected in series. In the schematic plan view of FIG. 11A, the transistors SMP2 and SMP3 are formed in a region where, from left to right, the low-resistance region 172, the semiconductor region 171, the low-resistance region 172, the semiconductor region 171, and the low-resistance region 172 are arranged side by side. In other words, in the schematic plan view of FIG. 11A, the transistors SMP2 and SMP3 can be formed so as to share the low-resistance region 172 located in the center. This reduces the area required for forming the transistors in the memory circuit BUCC. This also reduces the circuit area of ​​the semiconductor device SDV.

[0318] As described above, each of transistors SMN1, SMP1, SMP2, SMP3, and SMN3 can be a Si transistor. As described above, each of transistors IMN1 and IMN2 can be an IO transistor. By forming each of transistors SMN1, SMP1, SMP2, SMP3, and SMN3 as a Si transistor on a semiconductor substrate included in the circuit layer SICL, transistors IMN1 and IMN2 can be provided in the circuit layer IOCL above the circuit layer SICL. In this way, the memory circuit BUCC can be configured with Si transistors and IO transistors stacked on top of each other, thereby reducing the circuit area of ​​the memory circuit BUCC.

[0319] In addition, in the schematic plan view of FIG. 11A, the sizes (including channel lengths and channel widths) of the transistors SMN1, SMN3, SMP1, SMP2, and SMP3 are shown to be approximately equal to one another, but the sizes of the transistors listed above may be different from one another.

[0320] 11A, for example, the channel width d5n of transistor SMN1 is preferably longer than the channel width d7n of transistor SMN3. By making d5n longer than d7p, the on-current of transistor SMN1 can be made larger than the on-current of transistor SMN3. In particular, because transistor SMN1 is included in inverter IV1, increasing the on-current of transistor SMN1 can increase the driving speed of inverter IV1.

[0321] On the other hand, by making the channel width d7n of transistor SMN3 shorter than the channel width d5n of transistor SMN1, the off-current of transistor SMN3 can be made smaller than the off-current of transistor SMN1. In particular, because transistor SMN3 is included in switch AS1, reducing the off-current of transistor SMN3 can reduce the leakage current when switch AS1 is in the off state.

[0322] 11A, the channel length d6n of transistor SMN1 is preferably shorter than the channel length d8n of transistor SMN3. By making d6n shorter than d8p, the on-current of transistor SMN1 can be made larger than the on-current of transistor SMN3. In particular, because transistor SMN1 is included in inverter IV1, increasing the on-current of transistor SMN1 can increase the driving speed of inverter IV1.

[0323] On the other hand, by making the channel length d8n of transistor SMN3 longer than the channel length d6n of transistor SMN1, the off-state current of transistor SMN3 can be made smaller than the off-state current of transistor SMN1. In particular, because transistor SMN3 is included in switch AS1, reducing the off-state current of transistor SMN3 can reduce the leakage current when switch AS1 is in the off state.

[0324] The same applies to the transistors SMP1, SMP2, and SMP3. Therefore, by making the channel width d5p of the transistor SMP1 or SMP2 longer than the channel width d7p of the transistor SMP3, the on-current of the transistor SMP1 or SMP2 can be increased and the off-current of the transistor SMP3 can be reduced. Furthermore, by making the channel length d8p of the transistor SMP3 longer than the channel length d6p of the transistor SMP1 or SMP2, the off-current of the transistor SMP3 can be reduced and the on-current of the transistor SMP1 or SMP2 can be increased.

[0325] In addition, in the schematic plan view of FIG. 11B, the sizes (including the channel length and channel width) of the transistors IMN1 and IMN2 are shown as being approximately equal to each other, but the sizes of the transistors IMN1 and IMN2 may be different from each other.

[0326] 11B, the channel width d1 of the transistor IMN1 is preferably shorter than the channel width d3 of the transistor IMN2. By making d1 shorter than d3, the off-state current of the transistor IMN1 can be made smaller than the off-state current of the transistor IMN2. This allows data stored in the capacitor C1 to be held for a long period of time.

[0327] On the other hand, by making the channel width d3 of the transistor IMN2 longer than the channel width d1 of the transistor IMN1, the on-current of the transistor IMN2 can be made larger than the on-current of the transistor IMN1, thereby increasing the driving speed of the inverter IVX.

[0328] Specifically, for example, d1 is preferably 0.5 times or more and less than 1 time of d3, more preferably 0.1 times or more and less than 0.5 times, and even more preferably 0.01 times or more and less than 0.1 times.

[0329] Furthermore, the channel length d2 of the transistor IMN1 is preferably longer than the channel length d4 of the transistor IMN2. By making d2 longer than d4, the off-state current of the transistor IMN1 can be made smaller than that of the transistor IMN2. This allows data stored in the capacitor C1 to be held for a long period of time.

[0330] On the other hand, by making the channel length d4 of the transistor IMN2 longer than the channel length d2 of the transistor IMN1, the on-current of the transistor IMN2 can be made larger than the on-current of the transistor IMN1, thereby increasing the driving speed of the inverter IVX.

[0331] Specifically, for example, d4 is preferably greater than 1 time and less than 2 times d2, more preferably greater than 2 times and less than 10 times, and even more preferably greater than 10 times and less than 100 times.

[0332] Each of the channel widths d1 and d3 is, for example, preferably 1000 μm or more and 3000 μm or less, more preferably 100 μm or more and less than 1000 μm, even more preferably 10 μm or more and less than 100 μm, even more preferably 1000 nm or more and less than 10 μm, even more preferably 100 nm or more and less than 1000 nm, and even more preferably 10 nm or more and less than 100 nm.

[0333] Furthermore, each of the channel lengths d2 and d4 is, for example, preferably 1000 μm or more and 3000 μm or less, more preferably 100 μm or more and less than 1000 μm, even more preferably 10 μm or more and less than 100 μm, even more preferably 1000 nm or more and less than 10 μm, even more preferably 100 nm or more and less than 1000 nm, and even more preferably 10 nm or more and less than 100 nm.

[0334] <Cross-sectional structure example> Next, a specific cross-sectional structure example of the semiconductor device SDV shown in FIGS. 10, 11A, and 11B will be described. FIG. 12 is a cross-sectional schematic view of the dashed line D1 - D2 shown in FIGS. 11A and 11B, respectively.

[0335] FIG. 12 shows a cross-sectional schematic view of the circuit layer SICL and the circuit layer IOCL. Note that FIG. 12 shows a configuration in which the circuit layer IOCL is formed directly on the circuit layer SICL.

[0336] In FIG. 12, the transistors SMP2 and SMP3 included in the circuit layer SICL are illustrated. The transistors SMP2 and SMP3 are provided on the substrate 101, and include a conductive layer 131 that functions as a gate, insulating layers 161 and 111 that function as a gate insulating film, semiconductor regions 173a and 173b that include a part of the substrate 101, and low-resistance regions 174a, 174b, and 174c that function as a source region or a drain region that includes a part of the substrate. Note that in the above description, each of the transistors SMP2 and SMP3 is a p-channel transistor, but the structure of an n-channel transistor may be the same as the structures of the transistors SMP2 and SMP3 shown in FIG. 12. Further, as the substrate 101, for example, a single crystal silicon substrate can be used.

[0337] Also, the low-resistance regions 174a, 174b, and 174c shown in FIG. 12 are the low-resistance region 174 shown in FIG. 11A separated by region. Therefore, in this specification, the low-resistance regions 174a, 174b, and 174c may be collectively referred to as the low-resistance region 174. Similarly, the semiconductor regions 173a and 173b shown in FIG. 12 are the semiconductor region 173 shown in FIG. 11A separated by region. Therefore, in this specification, the semiconductor regions 173a and 173b may be collectively referred to as the semiconductor region 173.

[0338] 12, the semiconductor region 173 and the low-resistance region 174 included in the transistor SMP2 and the transistor SMP3 are each formed by providing an element isolation layer 102 in the substrate 101. It can also be said that the element isolation layer 102 is provided to isolate a plurality of transistors formed on the substrate 101. The element isolation layer 102 can be formed using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0339] 12, the semiconductor region 173 (part of the substrate 101) in which the channel is formed has a convex shape as shown in Fig. 13. Fig. 13 is a schematic cross-sectional view of the transistor SMP2 taken along the channel width direction of the transistor SMP2.

[0340] The side and top surfaces of the semiconductor region 173 are covered with a conductive layer 131 via an insulating layer 161. The conductive layer 131 may be made of a material that adjusts the work function. Such transistors SMP2 and SMP3 are also called fin-type transistors because they utilize the convex portions of the semiconductor substrate. An insulating layer that functions as a mask for forming the convex portions may be provided in contact with the tops of the convex portions. While the case where the convex portions are formed by processing a portion of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0341] 12 is an example, and the structure is not limited to this, and it is preferable to use appropriate transistors depending on the circuit configuration or driving method. Furthermore, although not shown in FIG. 12, the same structure as that of the transistors SMP2 and SMP3 can also be applied to the transistors SMP1, SMN1, and SMN3.

[0342] Between each structure, a wiring layer provided with an interlayer film, wiring, and plugs may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0343] 12, an insulating layer 112, an insulating layer 181, and an insulating layer 113 are stacked in this order as an interlayer film over the transistor SMP2 and the transistor SMP3. A conductive layer 136 and the like are embedded in the insulating layer 112. A conductive layer 132 and the like are embedded in the insulating layer 181 and the insulating layer 113. The conductive layer 136 and the conductive layer 132 function as contact plugs or wirings.

[0344] The insulating layer serving as an interlayer film may also serve as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 112 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method to improve the planarity.

[0345] A wiring layer may be provided over the insulating layer 113 and the conductive layer 132. For example, in FIG. 12 , an insulating layer 182, an insulating layer 114, an insulating layer 115, and an insulating layer 116 are stacked in this order over the insulating layer 113 and the conductive layer 132. A conductive layer 134 is formed in the insulating layer 182, the insulating layer 114, and the insulating layer 115. The conductive layer 134 functions as a contact plug or a wiring.

[0346] An insulating layer 116 is provided on the insulating layer 115 and the conductive layer 134. It is preferable that contact plugs or wiring for connection to an upper circuit (for example, a circuit element included in the circuit layer IOCL) be embedded in the insulating layer 116.

[0347] 12 also illustrates some of the circuit elements included in the circuit layer IOCL. Specifically, Fig. 12 illustrates the transistor IMN2 and the capacitive element C1 included in the memory circuit BUCC shown in Figs. 6 and 11B.

[0348] 12, the transistor IMN2 is formed on an insulating layer 281. The capacitance element C1 is formed on an insulating layer 285. The insulating layer 285 is located above the insulating layer 281. Therefore, the capacitance element C1 is located above the transistor IMN2.

[0349] Note that each of the insulating layers 281 and 285 preferably functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layer 281 and the insulating layer 285 can prevent the permeation of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (for example, N ２ O, NO or NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., through which the oxygen is less likely to permeate). Note that for materials that can be used for the insulating layer 281 and the insulating layer 285, the description of the insulating layer in the section on constituent materials of a transistor can be referred to.

[0350] The transistor IMN2 includes a conductive layer 231a and a conductive layer 231b. The conductive layer 231a functions as one of a source electrode and a drain electrode of the transistor IMN2, and the conductive layer 231b functions as the other of the source electrode and the drain electrode of the transistor IMN2.

[0351] The conductive layer 231a is connected to a conductive layer 233_1 through a conductive layer 235_1 having a function as a plug. Similarly, the conductive layer 231b is connected to a conductive layer 233_2 through a conductive layer 235_2 having a function as a plug.

[0352] The conductive layer 233_2 functions as one of a pair of electrodes of the capacitor C1.

[0353] The conductive layers 235_1 and 235_2 are conductive layers that will become the conductive layers 235a and 235b described later. Therefore, the conductive layers 235_1 and 235_2 can be formed using materials that can be used for the conductive layers 235a and 235b, respectively.

[0354] The transistor IMN2 further includes a conductive layer 232, which functions as a gate electrode of the transistor IMN2.

[0355] In addition, the conductive layer 232 is connected to a conductive layer 233_3 through a conductive layer 235_3 having a function as a plug.

[0356] For the conductive layer 235_3, a material that can be used for the conductive layers 235a and 235b can be used.

[0357] Between the transistor IMN2 and the capacitor C1, insulating layers 213 and 214 functioning as interlayer films are formed. Note that openings are provided in the insulating layers 213 and 214 in regions overlapping with the gate electrodes of the transistor IMN2, and a conductive layer 235_3 is embedded in the openings as plugs. Similarly, openings are provided in regions overlapping with the source and drain electrodes of the transistor IMN2, and a conductive layer 235_1 and a conductive layer 235_2 are embedded in the openings as plugs.

[0358] The conductive layer 233_2 which functions as one of a pair of electrodes of the capacitor C1 is formed to be embedded in the insulating layer 217 over the insulating layer 285.

[0359] In addition, a conductive layer 237 that functions as the other of the pair of electrodes of the capacitor C1 is provided above one of the pair of electrodes of the capacitor C1 and a part of the insulating layer 217, with an insulating layer 241 that functions as a dielectric interposed therebetween.

[0360] Note that for the insulating layer 241, refer to the description of the insulating layer 441 described later.

[0361] By embedding the conductive layer 233_2, which functions as one of the pair of electrodes of the capacitor C1, in the insulating layer 217, the conductive layer, which functions as one of the pair of electrodes of the capacitor C1, and the insulating layer 217 can be planarized to be flush with each other. This allows the insulating layer 241 and the conductive layer 237, which functions as the other of the pair of electrodes of the capacitor C1, to be formed with good flatness on the upper surfaces of the conductive layer 233_2, which functions as one of the pair of electrodes of the capacitor C1, and the insulating layer 217, which have good flatness. By improving the flatness of both the pair of electrodes of the capacitor C1 and the insulating layer 241, localized concentration of the electric field can be suppressed, and as a result, leakage current between the pair of electrodes of the capacitor C1 can be prevented. Furthermore, one of the pair of electrodes of the capacitor C1 (here, the lower electrode) has a smaller area than the other of the pair of electrodes of the capacitor C1 (here, the upper electrode). This configuration makes it possible to suppress local electric field concentration that can occur in the dielectric film (insulating film sandwiched between a pair of electrodes) of the capacitance element C1, thereby realizing a highly reliable semiconductor device.

[0362] For example, by configuring the capacitor C1 included in the memory circuit BUC described above, it is possible to prevent leakage current between the pair of electrodes of the capacitor C1 that occurs between the node SN1 and the wiring VE1. Therefore, in the memory circuit BUC, fluctuations in the potential of the node SN1 due to the leakage current can be prevented, and the potential of the node SN1 can be maintained for a long period of time. Furthermore, localized electric field concentration can be suppressed in the insulating layer 241, which is the dielectric of the capacitor C1, and therefore the reliability of the memory circuit BUC including the capacitor C1 can be improved.

[0363] 12, a conductive layer functioning as a back gate may be provided below the island-shaped semiconductor layer of each transistor in the transistor IMN2. By providing a back gate in the transistor IMN2 and changing the potential of the back gate, the threshold voltage of the transistor can be changed. Note that the transistor IMN1 may also be provided with a back gate, similar to the transistor IMN2.

[0364] For example, by providing a back gate to the transistor IMN1, the influence of an external electric field can be reduced and the transistor IMN1 can be stably maintained in an off state. Therefore, data written to the capacitor C1 can be stably held. In this way, providing a back gate stabilizes the operation of the memory circuit BUC and improves the reliability of the memory circuit BUC.

[0365] As the semiconductor layers in which the channels of the transistors IMN1 and IMN2 are formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used, as described in the above embodiment. As another example, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can be used.

[0366] Note that the transistors IMN1 and IMN2 preferably use an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. Since the oxide semiconductor has a band gap of 2 eV or more, the off-state current is significantly small. Therefore, the power consumption of the memory circuit BUC can be reduced. In particular, the indium oxide described in Embodiment 2 is preferably used as the oxide semiconductor.

[0367] Furthermore, a transistor including an oxide semiconductor in a channel formation region operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. Therefore, the transistor operates stably even in a high-temperature environment and exhibits high reliability.

[0368] Note that when a back gate is provided in a transistor, it is preferable not to provide a conductive layer near the back gate in order to avoid formation of parasitic capacitance with the back gate.

[0369] While the above description has been given for the transistors SMP2, SMP3, and IMN2 shown in FIG. 12 , the same applies to other transistors included in the semiconductor device SDV. For example, in the flip-flop FFC of FIG. 6 , the transistors SMN1 and SMN3 included in the memory circuit BUCC can refer to the above description of the transistors SMP2 and SMP3. Furthermore, the transistor IMN1 included in the memory circuit BUCC can refer to the above description of the transistor SMN2. Furthermore, the transistors included in the inverters IV2 to IV5, inverter IVC, and switches AS2 to AS4 of the flip-flop FFC of FIG. 6 can refer to the above description of the transistors SMP2, SMP3, and IMN2.

[0370] <<Transistor Configuration Example 1>> Next, a specific configuration example of a transistor called a GL structure that can be applied to the transistor IMN2 shown in Fig. 12 and the transistor IMN1 not shown in Fig. 12 will be described. The transistor IMN shown in Fig. 14A and Fig. 14B is an example of a transistor with a GL structure that can be applied to the transistor IMN2 in Fig. 12.

[0371] In particular, FIG. 14A shows a schematic cross-sectional view of the transistor IMN in the channel length direction, and FIG. 14B shows a schematic cross-sectional view of the transistor IMN in the channel width direction.

[0372] 14A and 14B , for example, the transistor IMN includes a semiconductor layer 251a, a semiconductor layer 251b, a conductive layer 231a, a conductive layer 231b, a conductive layer 232a, a conductive layer 232b, a conductive layer 235a, a conductive layer 235b, a conductive layer 239a, a conductive layer 239b, an insulating layer 211, an insulating layer 281, an insulating layer 212, an insulating layer 261, an insulating layer 262, an insulating layer 263, an insulating layer 264, an insulating layer 282, an insulating layer 283, an insulating layer 213, and an insulating layer 214. Note that the transistor IMN may not include all of the above-described components. For example, although the conductive layers 239a and 239b function as a backgate electrode of the transistor IMN, the transistor IMN may not include the conductive layers 239a and 239b.

[0373] Materials that can be used for the conductive layer, insulating layer, and semiconductor layer will be described later.

[0374] Here, the conductive layers 239a and 239b may be collectively referred to as conductive layers 239. The conductive layers 231a and 231b may be collectively referred to as conductive layers 231. The conductive layers 235a and 235b may be collectively referred to as conductive layers 235. The semiconductor layers 251a and 251b may be collectively referred to as semiconductor layers 251.

[0375] The conductive layer 239 and the insulating layer 212 are disposed above a substrate (not shown in FIGS. 14A and 14B ). In particular, the conductive layer 239 is preferably embedded in the insulating layer 212. In the transistor IMN shown in FIGS. 14A and 14B , the conductive layer 239 has a stacked structure including a conductive layer 239a and a conductive layer 239b. Specifically, the conductive layer 239a is preferably provided in contact with the bottom surface and sidewall of an opening provided in the insulating layer 212. The conductive layer 239b is preferably provided so as to be embedded in a recess formed in the conductive layer 239a. In the transistor IMN shown in FIGS. 14A and 14B , the height of the top surface of the conductive layer 239b is approximately the same as the height of the top surface of the conductive layer 239a and the height of the top surface of the insulating layer 212.

[0376] The insulating layer 212 functions as a planarizing film that flattens steps caused by plugs or the like, similar to the insulating layer 112. Therefore, the insulating layer 212 can be made of a material that functions as a planarizing film, similar to the insulating layer 112. Furthermore, by using a material with a low dielectric constant for the insulating layer 212, the parasitic capacitance between wirings can be reduced.

[0377] For this reason, the insulating layer 212 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer 212 can be made of, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are particularly preferred because they can easily form regions containing oxygen that is released by heating. Alternatively, the insulating layer 212 can be made of, for example, a resin. The material used for the insulating layer 212 may be an appropriate combination of the above-mentioned insulating materials.

[0378] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0379] The semiconductor layer 251 and the conductive layer 232 are disposed in a region overlapping the conductive layer 239. The semiconductor layer 251b is disposed on the semiconductor layer 251a. The conductive layers 231a and 231b are disposed on the semiconductor layer 251b and spaced apart from each other. The insulating layer 213 is disposed on the conductive layers 231a and 231b. In particular, an opening is formed in the insulating layer 213 in a region between the conductive layers 231a and 231b. The conductive layer 232 is disposed in the opening. The insulating layer 264 is disposed between the semiconductor layer 251b, the conductive layer 231a, the conductive layer 231b, and the insulating layer 213 and the conductive layer 232. Here, as shown in FIGS. 14A and 14B , it is preferable that the top surface of the conductive layer 232 substantially coincides with the top surfaces of the insulating layer 264 and the insulating layer 213.

[0380] 14A , a region 271a may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 231a and in its vicinity. Similarly, a region 271b may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 231b and in its vicinity. In this case, the region 271a functions as one of a source region and a drain region, and the region 271b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the region 271a and the region 271b.

[0381] By providing the conductive layers 231a and 231b in contact with the semiconductor layer 251, the oxygen concentration in the regions 271a and 271b may be reduced. Furthermore, a metal compound layer containing a metal contained in the conductive layer 231a and components of the semiconductor layer 251 may be formed in the region 271a. Similarly, a metal compound layer containing a metal contained in the conductive layer 232b and components of the semiconductor layer 251 may be formed in the region 271b. Furthermore, the regions 271a and 271b may have high impurity concentrations, such as hydrogen, nitrogen, and metal elements. In such cases, the carrier concentrations in the regions 271a and 271b increase, and the regions 271a and 271b become low-resistance regions. That is, the source and drain regions are n-type regions with a higher carrier concentration than the channel formation region. These regions may be referred to as low-resistance regions.

[0382] On the other hand, the channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0383] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0384] Note that when the carrier concentration of the semiconductor layer 251 is reduced, the impurity concentration in the semiconductor layer 251 is reduced to reduce the density of defect states. In this specification, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic. Note that an oxide semiconductor (or a metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or a metal oxide).

[0385] In order to stabilize the electrical characteristics of the transistor IMN, it is effective to reduce the impurity concentration of the channel formation region in the semiconductor layer 251. Furthermore, in order to reduce the impurity concentration of the semiconductor layer 251, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 251 refer to, for example, elements other than the main components constituting the semiconductor layer 251. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0386] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 251. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0387] In a transistor using an oxide semiconductor for the semiconductor layer 251, impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, and the transistor's electrical characteristics are likely to fluctuate, which may result in poor reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0388] In response to this problem, an insulating layer containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulating layer to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor IMN may decrease. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of a semiconductor device including the transistor may vary. Furthermore, if oxygen supplied from the insulating layer to the oxide semiconductor diffuses into a conductive layer such as a gate electrode, a source electrode, or a drain electrode, the conductive layer may be oxidized, and the conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

[0389] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is preferable to reduce H in the source and drain regions. Ｏ It is preferable to prevent the amount of H from being excessively reduced. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductive layer 232, the conductive layer 231a, the conductive layer 231b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductive layer 232, the conductive layer 231a, the conductive layer 231b, and the like. Note that hydrogen in the oxide semiconductor is V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0390] 14A and 14B , the side surfaces of the conductive layers 231a and 231b facing the conductive layer 232 have a substantially vertical shape. Note that the transistor IMN shown in FIGS. 14A and 14B is not limited thereto, and the angle formed between the side surface and the bottom surface of the conductive layers 231a and 231b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductive layers 231a and 231b may have a plurality of surfaces.

[0391] Note that the transistor IMN has a two-layer structure in which the semiconductor layer 251a and the semiconductor layer 251b are stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof, but the present invention is not limited to this. For example, the semiconductor layer 251b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the semiconductor layer 251a and the semiconductor layer 251b may have a stacked structure of two or more layers.

[0392] The conductive layer 232 functions as a first gate electrode (sometimes referred to as a top gate electrode or a front gate electrode) of the transistor, and as described above, the conductive layer 231a and the conductive layer 231b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 232 is formed so as to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layer 231a and the conductive layer 231b. Here, the conductive layer 232, the conductive layer 231a, and the conductive layer 231b are formed in a self-aligned manner with respect to the opening of the insulating layer 213. That is, in the transistor IMN, the first gate electrode can be disposed between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 232 can be formed without providing a margin for alignment, which reduces the area occupied by the transistor IMN. This allows the circuit area of ​​the semiconductor device SDV described above to be reduced.

[0393] Note that the transistor IMN can be formed by forming an island-shaped stack of layers over an insulating layer 262, the stack of layers including an insulating layer 263 (described later), a semiconductor layer 251, and a conductive layer that will become the conductive layer 231a and the conductive layer 231b. Next, an insulating layer 282 and an insulating layer 213 (collectively referred to here as an interlayer film) are stacked in this order above the island-shaped stack of layers and above the insulating layer 262. An opening is then formed in a region of the interlayer film that overlaps the island-shaped stack of layers, and an insulating layer 264 and a conductive layer 232 are provided in this order in the opening. In particular, it is preferable to simultaneously form the conductive layer 231a and the conductive layer 231b by forming an opening in the interlayer film. In this specification, a transistor structure in which an opening reaching the island-shaped stack of layers and an interlayer film are formed in the interlayer film, and a conductive layer that will become the first gate electrode of the transistor is provided to fill the opening is referred to as a GL structure. Such a structure may also be called a TGSA structure.

[0394] 14A and 14B , the conductive layer 232 is shown as having a two-layer structure. Here, the conductive layer 232 preferably includes a conductive layer 232a and a conductive layer 232b disposed on the conductive layer 232a. For example, the conductive layer 232a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 232b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 232a.

[0395] The conductive layer 232a is preferably made of a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or a conductive material that has a function of suppressing diffusion of oxygen.

[0396] Furthermore, since the conductive layer 232a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 232b caused by oxygen contained in the insulating layer 213, etc. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0397] The conductive layer 232b is preferably a conductive layer with high conductivity. For example, the conductive layer 232b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 232b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0398] For the conductive layers 231a and 231b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 231a and 231b. When a conductive material containing metal and nitrogen is used for the conductive layers 231a and 231b, the conductive layers 231a and 231b become conductive layers containing at least metal and nitrogen. For example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion can be selected from the materials that can be used for the conductive layers 232a and 232b described above.

[0399] In the transistor IMN, conductive layers 235a and 235b are provided on the top surfaces of the conductive layers 231a and 231b as plugs for connecting the source electrode and the drain electrode of the transistor IMN. For example, the conductive layers 235a and 235b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0400] Furthermore, for example, the conductive layer 235 a and the conductive layer 235 b can have a stacked structure including a plurality of layers. In particular, it is preferable to stack a conductive material having a function of suppressing permeation of impurities such as water and hydrogen and a material with high conductivity.

[0401] The conductive layer 239 may function as a second gate electrode (which may be referred to as a bottom gate electrode or a back gate electrode). In this case, the potential applied to the conductive layer 239 may be changed independently of the potential applied to the conductive layer 232, thereby reducing the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 239, the V ｔｈ Therefore, when a negative potential is applied to the conductive layer 239, the drain current when the potential applied to the conductive layer 232 is 0 V can be made smaller than when no negative potential is applied.

[0402] 14B , the conductive layer 239 preferably extends as a wiring also in a region outside the end portion intersecting with the channel width direction of the semiconductor layer 251. That is, outside the side surface of the semiconductor layer 251 in the channel width direction, the conductive layer 239 and the conductive layer 232 preferably overlap with each other with an insulating layer interposed therebetween.

[0403] 14A, the conductive layer 232 preferably includes a conductive layer 232a provided inside the insulating layer 264 and a conductive layer 232b provided so as to be embedded inside the conductive layer 232a. Although the conductive layer 232 has a two-layer stacked structure in FIGS. 14A and 14B, the present invention is not limited to this. For example, the conductive layer 232 may have a single-layer structure or a stacked structure of three or more layers.

[0404] 14A and 14B , the transistor IMN preferably includes an insulating layer 211 disposed on a substrate (not shown in FIGS. 14A and 14B ), an insulating layer 281 disposed on the insulating layer 211, an insulating layer 212 disposed on the insulating layer 281, a conductive layer 239 disposed so as to be embedded in the insulating layer 212, an insulating layer 261 disposed on the insulating layer 212 and the conductive layer 239, an insulating layer 262 disposed on the insulating layer 261, and an insulating layer 263 disposed on the insulating layer 262. A semiconductor layer 251 a is preferably disposed on the insulating layer 263.

[0405] 14A and 14B, an insulating layer 282 is preferably disposed between the insulating layer 262, the insulating layer 263, the semiconductor layer 251a, the semiconductor layer 251b, the conductive layer 231a, the conductive layer 231b, and the insulating layer 213. Here, the insulating layer 282 is preferably in contact with the side surface of the insulating layer 264, the top and side surfaces of the conductive layer 231a, the top and side surfaces of the conductive layer 231b, the side surfaces and top surfaces of the semiconductor layer 251a, the semiconductor layer 251b, and the insulating layer 263, and the top surface of the insulating layer 262, as shown in FIG.

[0406] An insulating layer 283 and an insulating layer 214 which function as interlayer films are preferably provided over the transistor IMN. Here, the insulating layer 283 is preferably provided in contact with top surfaces of the conductive layer 232, the insulating layer 264, and the insulating layer 213. In this case, the top surface of the insulating layer 213 is preferably planarized.

[0407] It is preferable to provide a conductive layer 235 (conductive layer 235a and conductive layer 235b) that is connected to the transistor IMN and functions as a plug. Therefore, the conductive layer 235 is provided in contact with the inner walls of the openings of the insulating layer 282, the insulating layer 213, the insulating layer 283, and the insulating layer 214. In particular, a first conductive layer of the conductive layer 235 may be provided in contact with the inner walls, and a second conductive layer of the conductive layer 235 may be provided on a side surface of the first conductive layer. Here, the height of the top surface of the conductive layer 235 can be made approximately the same as the height of the top surface of the insulating layer 214.

[0408] Specifically, for example, a first conductive layer of the conductive layer 235a is provided in contact with one of the inner walls of two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 235a is formed in contact with the side surface thereof. Note that the conductive layer 231a is located in part of the bottom of the opening, and the conductive layer 235a is in contact with the conductive layer 231a. Similarly, for example, a first conductive layer of the conductive layer 235b is provided in contact with the other inner wall of the two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 235b is formed in contact with the side surface thereof. Note that the conductive layer 231b is located in part of the bottom of the opening, and the conductive layer 235b is in contact with the conductive layer 231b.

[0409] Note that although the transistor IMN has a structure in which the first conductive layer of the conductive layer 235 and the second conductive layer of the conductive layer 235 are stacked, one embodiment of the present invention is not limited to this. For example, the conductive layer 235 may have a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0410] 14B , in a region of the semiconductor layer 251b that does not overlap with the conductive layer 231, in other words, in the channel formation region of the semiconductor layer 251, the conductive layer 232 is arranged to cover the side surface of the semiconductor layer 251. This makes it easier for the electric field of the conductive layer 232, which functions as the first gate electrode, to act on the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 232. This increases the on-current of the transistor IMN and improves its frequency characteristics.

[0411] For example, the insulating layer 213 preferably has a lower dielectric constant than the insulating layer 262. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layer 213 preferably uses, as a material with a low dielectric constant, one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies.

[0412] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0413] The upper surfaces of the insulating layers 213 may be planarized, so that the insulating layers 213 also function as planarizing films.

[0414] As described above, the insulating layer 213 can be formed using a material similar to that of the insulating layer 212 .

[0415] <<Constituent Materials of Transistor>> Next, the materials that constitute the transistor IMN will be described.

[0416] [Metal Oxide (Oxide Semiconductor)] The transistor IMN preferably includes a metal oxide that functions as an oxide semiconductor and that includes a channel formation region. In particular, the indium oxide described in Embodiment 2 is suitable as the metal oxide.

[0417] Note that, in the following, not only indium oxide but also various metal oxides that become the channel formation region of the transistor IMN will be described.

[0418] The metal oxide to be used as the channel formation region of the transistor IMN preferably has a band gap of, for example, 2 eV or more, preferably 2.5 eV or more. Specifically, in the case of the transistor IMN in FIGS. 14A and 14B, the semiconductor layer 251 preferably uses a metal oxide that functions as an oxide semiconductor.

[0419] Note that metal oxide structures are divided into single-crystal structures and other structures (non-single-crystal structures). Examples of non-single-crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures can be used. However, use of a crystalline metal oxide, such as a CAAC structure or an nc structure, is preferable because a highly reliable semiconductor device can be obtained.

[0420] As described in the above embodiment, the metal oxide preferably contains at least indium. In particular, it is preferable that it contains indium and zinc. In addition to these, it is preferable that the element M is contained. The element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, it is preferable that the element M is one or more of aluminum, gallium, yttrium, and tin. It is even more preferable that the element M contains one or both of gallium and tin.

[0421] Examples of the metal oxide include indium oxide (also referred to as In oxide or indium oxide), gallium oxide (also referred to as Ga oxide or gallium oxide), zinc oxide (also referred to as Zn oxide or zinc oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO"), and aluminum. Examples of usable materials include zinc oxide (Al—Zn oxide, also referred to as “AZO”), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as “IAZO”), indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide, also referred to as “IGZO”), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide, also referred to as “IGZTO”), and indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide, also referred to as “IGAZO” or “IAGZO”). Alternatively, examples of usable materials include silicon-containing indium tin oxide, gallium tin oxide (Ga—Sn oxide), and aluminum tin oxide (Al—Sn oxide).

[0422] As described above, the metal oxide preferably contains indium. Specifically, it is preferable to use indium oxide as the metal oxide. It is particularly preferable to use crystalline indium oxide.

[0423] The metal oxide can be preferably formed by a sputtering method or an ALD method. When the metal oxide is formed by a sputtering method, a film with high crystallinity or high film density can be formed. Furthermore, when the metal oxide is formed by an ALD method, atoms can be deposited layer by layer, which has advantages such as enabling film formation with fewer defects such as pinholes, excellent film coverage, and low-temperature film formation. After the metal oxide is formed, it is preferable to perform an impurity removal treatment to remove impurities (typically, impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of the impurity removal treatment include plasma treatment, microwave plasma treatment, and heat treatment. The impurity removal treatment can also serve as a treatment to enhance the crystallinity of the metal oxide. By performing a treatment to enhance the crystallinity of the oxide semiconductor layer, a highly reliable transistor can be realized.

[0424] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0425] 14A and 14B , a conductive layer functioning as a source electrode or a drain electrode, for example, the conductive layer 231 a and the conductive layer 231 b shown in FIG. 14A and 14B , is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, an alloy containing two or more of the above metal elements, or an alloy combining two or more of the above metal elements. Furthermore, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used for the conductive layer. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. In addition, the conductive layer may be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus), or a silicide (e.g., nickel silicide).

[0426] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0427] 14A and 14B , a conductive layer functioning as a second gate electrode, for example, the conductive layer 239 shown in FIGS. 14A and 14B , is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, a conductive material that has a function of suppressing the diffusion of oxygen is preferably used. In particular, examples of conductive materials that have a function of suppressing the diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0428] In addition to the above, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.

[0429] The conductive layer functioning as the first gate electrode, for example, the conductive layer 232 shown in Figures 14A and 14B, is preferably a conductive layer having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferably a conductive material having a function of suppressing the diffusion of oxygen. Examples of conductive materials having a function of suppressing the diffusion of oxygen include tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Furthermore, by providing a conductive material containing oxygen as the conductive layer, oxygen desorbed from the conductive material is more easily supplied to the channel formation region.

[0430] The conductive layer functioning as the first gate electrode is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductive layer also functions as a wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductive layer may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0431] The conductive layer may be formed using, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon. The conductive layer may be formed using, for example, indium gallium zinc oxide containing nitrogen. The use of such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like to be captured.

[0432] [Insulating Layer] Examples of the insulating layer 281, the insulating layer 261, the insulating layer 262, the insulating layer 263, and the insulating layer 283 included in the transistor IMN include an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide.

[0433] The insulating layer 281 that can be provided in the transistor preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the semiconductor layer of the transistor IMN from the substrate side. Similarly, the insulating layer 283 that can be provided in the transistor preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the semiconductor layer of the transistor IMN from above the circuit layer IOCL. Therefore, the insulating layer preferably uses an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of preventing the diffusion of oxygen (i.e., through which the oxygen is less likely to permeate).

[0434] Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include, for example, insulating layers containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used as a single layer or a stack. Specifically, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0435] The second gate insulating film in contact with the metal oxide contained in the channel formation region, for example, the insulating layers 261 to 263 shown in FIGS. 14A and 14B, preferably has oxygen released therefrom by heating. In this specification, oxygen released by heating may be referred to as excess oxygen. For example, silicon oxide or silicon oxynitride is preferably used as appropriate for the second gate insulating film. By providing an insulating layer containing oxygen in contact with the metal oxide, oxygen vacancies in the metal oxide can be reduced, and the reliability of the transistor can be improved.

[0436] Specifically, it is preferable to use an oxide material from which part of oxygen is released by heating as the insulating layer. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms by thermal desorption spectrometry (TDS) is 1.0×10 １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３More preferably, 2.0×10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C. or 100° C. to 400° C. In particular, by performing the TDS analysis at a temperature in the range of 100° C. to 700° C., the amount of released oxygen in accordance with the manufacturing process of a transistor can be evaluated.

[0437] Furthermore, the insulating layer included in the transistor may preferably contain an oxide of one or both of aluminum and hafnium, which are insulating materials. Examples of insulating layers containing an oxide of one or both of aluminum and hafnium include aluminum oxide and hafnium oxide. Another example is an oxide containing aluminum and hafnium (hafnium aluminate). When such a material is used to form an insulating layer around a transistor, the insulating layer can function as a layer that suppresses oxygen release and the intrusion of impurities such as hydrogen from the periphery of the transistor into the metal oxide.

[0438] Furthermore, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to an insulating layer included in a transistor. Alternatively, these insulating layers may be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulating layer.

[0439] The insulating layer included in the transistor may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a so-called high-k material such as (BST) may be used as a single layer or a laminate.

[0440] 14A and 14B , an insulating layer serving as a first gate insulating film, for example, the insulating layer 264, is preferably disposed in contact with the upper surface of the metal oxide. The insulating layer can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable to heat.

[0441] <<Configuration Example 2 of Transistor>> Next, a configuration example of a vertical channel transistor will be described.

[0442] 15A to 15C show examples of the configuration of a vertical channel transistor, in which the source electrode and the drain electrode are located at different heights and the current flowing through the semiconductor layer flows in the height direction, i.e., the channel length direction has a component in the height direction (vertical direction).

[0443] Note that the transistors illustrated in FIGS. 15A to 15C may also be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, or the like, other than vertical channel transistors.

[0444] In this specification, in a vertical channel transistor, one of the source electrode and the drain electrode located at the bottom may be referred to as a bottom electrode, and the other of the source electrode and the drain electrode located at the top may be referred to as an top electrode.

[0445] In particular, Fig. 15A shows a schematic plan view of an example of a transistor 300, which is a vertical channel transistor, and Figs. 15B and 15C show schematic cross-sectional views of the transistor 300. Fig. 15B is a schematic cross-sectional view taken along dashed line A1-A2 in Fig. 15A, and Fig. 15C is a schematic cross-sectional view taken along dashed line A3-A4 in Fig. 15A. Fig. 15B shows an excerpt of the transistors included in the circuit layer IOCL. Fig. 16 shows a schematic perspective view of the transistor 300 shown in Figs. 15A to 15C and the surrounding wiring.

[0446] The transistor 300 shown in FIGS. 15A-15C can be used in place of a GL structure transistor such as the transistor IMN2 shown in FIG.

[0447] The structure of a transistor 300, which is a vertical channel transistor, will be described with reference to FIGS. 15A to 15C and 16. FIG.

[0448] As an example, the transistor 300 includes a conductive layer 331 that functions as a wiring or an electrode, a conductive layer 332 that functions as a wiring or an electrode, a semiconductor layer 351 that is an active layer of the transistor 300, an insulating layer 361 that functions as a gate insulating film of the transistor 300, a conductive layer 333 that functions as a gate of the transistor 300, and a conductive layer 334 that functions as a wiring.

[0449] The conductive layer 331 is provided above the insulating layer 311, which functions as an interlayer film. Furthermore, the conductive layer 331 functions as wiring, and therefore extends along the direction of the dashed dotted line A3-A4 in the schematic plan view of FIG. 15A .

[0450] For example, the conductive layer that can be used for the transistor IMN described above can be used for the conductive layer 331. The same applies to conductive layers 332 to 334 described later.

[0451] An insulating layer 312 functioning as an interlayer film and a conductive layer 332 are formed in this order on the insulating layer 311 and the conductive layer 331. The conductive layer 332 functions as a wiring and therefore extends along the direction of the dashed dotted line A1-A2 in the schematic plan view of FIG.

[0452] Furthermore, openings reaching the conductive layer 331 are formed in the insulating layer 312 and the conductive layer 332 in regions overlapping with the conductive layer 331. A semiconductor layer 351 is formed on the side surfaces and bottom of the openings. That is, the semiconductor layer 351 is formed on the top surface of the conductive layer 331, the side surfaces of the insulating layer 312, and the side surfaces of the conductive layer 332. The semiconductor layer 351 is also formed on part of the top surface of the conductive layer 332. An insulating layer 361 is provided so as to be in contact with the conductive layer 332 and the semiconductor layer 351 inside and outside the openings. A conductive layer 333 is formed on the top surface and side surfaces of the insulating layer 361 so as to fill the openings.

[0453] An insulating layer 313 functioning as an interlayer film is formed on the top surface of the insulating layer 361 and the top surface of the conductive layer 333. An opening reaching the conductive layer 333 is formed in the insulating layer 313 in a region overlapping with the conductive layer 333. A conductive layer 334 is embedded in the side surface and bottom of the opening. Note that part of the conductive layer 334 may be formed on the top surface of the insulating layer 313. The insulating layer 314 functioning as an interlayer film is formed on the insulating layer 313 and the conductive layer 334.

[0454] Furthermore, the conductive layer 334 functions as wiring and therefore extends along the direction of the dotted line A3-A4 in the schematic plan view of FIG. 15A.

[0455] For example, an insulating material with a low dielectric constant is preferably used for the insulating layers 311 to 314. By using an insulating material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layers 311 to 314 can each be made of a material that can be used for the insulating layer 212 or the insulating layer 213 described above.

[0456] The insulating layer 361 has a function as a gate insulating film, and therefore, for example, a material that can be used for the insulating layer 264 can be used for the insulating layer 361 .

[0457] Part of the conductive layer 331 functions as one of the source electrode and the drain electrode of the transistor 300. Part of the conductive layer 332 functions as the other of the source electrode and the drain electrode of the transistor 300. Part or all of the conductive layer 333 functions as a gate electrode of the transistor 300.

[0458] As described above, by forming the insulating layer, the conductive layer, and the semiconductor layer, a vertical channel transistor can be formed in which the channel length direction has a component in the height direction (vertical direction). The channel length of the transistor 300 depends on the film thickness of the insulating layer 312. The thinner the insulating layer 312, the shorter the channel length, and therefore the larger the on-current of the transistor 300 can be. On the other hand, the thicker the insulating layer 312, the longer the channel length, and therefore the smaller the off-current of the transistor 300 can be.

[0459] Furthermore, the wirings connecting the source, drain, or gate of the vertical channel transistor are not formed in the same process but in different processes. As a result, the wirings connecting the source, drain, or gate of the vertical channel transistor have overlapping regions in a plan view. Since the wirings connecting the source, drain, or gate of the vertical channel transistor are provided at different heights, the parasitic capacitance generated in each wiring can be reduced. This allows the driving frequency of the transistor 300 to be increased, and the driving speed of the semiconductor device SDV, etc. to be increased.

[0460] <<Configuration Example of Capacitor Element>> Although FIG. 12 shows a flat-plate type capacitative element as the capacitative element C1, the semiconductor device SDV may be provided with a capacitative element other than a flat-plate type capacitative element.

[0461] 17A and 17B show a capacitive element 400 which is a vertical capacitive element, rather than the flat capacitive element shown in Fig. 12. Fig. 17A shows a schematic cross-sectional view of the capacitive element 400, and Fig. 17B shows a schematic plan view of the capacitive element 400.

[0462] 17A includes, as an example, a portion of conductive layer 431, a portion of conductive layer 432, a portion of conductive layer 433, and an insulating layer 441. Note that FIG. 17A excerpts conductive layer 434, insulating layer 411, insulating layer 412, insulating layer 413, and insulating layer 414 as materials formed around capacitor element 400. FIG. 17B is a plan view along dashed-dotted line B1-B2 in FIG. 17A , illustrating insulating layer 412, conductive layer 432, insulating layer 441, and conductive layer 433. The dashed line in FIG. 17B represents an edge 473 of conductive layer 433 provided on insulating layer 441.

[0463] The conductive layer 431 functions as a wiring for connecting to one of a pair of electrodes of the capacitor 400. For the conductive layer 431, the description of the conductive layer 331 in FIGS.

[0464] Part of the conductive layer 432 functions as one of a pair of electrodes of the capacitor 400, part of the conductive layer 433 functions as the other of the pair of electrodes of the capacitor 400, and the insulating layer 441 functions as a dielectric of the capacitor 400. For example, the conductive layer 431 can be formed using a material that can be used for the conductive layer 331 in FIGS. 15A to 15C and 16. For the conductive layer 432, a material that can be used for the conductive layer 331 or the conductive layer 334 can be used.

[0465] The insulating layer 441 functions as a dielectric of the capacitive element 400. For example, it is preferable to use a high-k material as the insulating layer 441. Specifically, as one example, a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide can be used for the insulating layer 441. Alternatively, as another example, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use hafnium oxide having an amorphous structure. Furthermore, as another example, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ By using a high dielectric constant material for the dielectric of the capacitance element C1p or the capacitance element C2p, the capacitance value can be increased, and the voltage written to the capacitance element C1p or the capacitance element C2p can be held for a long period of time.

[0466] The capacitive element 400 can be a ferroelectric capacitor by using a material that can have ferroelectricity for the insulating layer 441. Unlike paraelectric materials, materials that can have ferroelectricity maintain their internal dielectric polarization even when no voltage is applied (this is sometimes called remanent polarization).

[0467] Moreover, a conductive layer 434 is formed on the conductive layer 433 .

[0468] The insulating layer 411 functions as a base film for forming the conductive layer 431. The insulating layer 412 functions as an interlayer film for separating the conductive layer 431 and the conductive layer 432. The insulating layer 413 functions as an interlayer film for forming a conductive layer 434, which functions as a wiring, above the conductive layer 433. Note that the insulating layer 413 has openings in regions where the conductive layers 433 and 434 overlap, and the conductive layers 433 and 434 are connected through the openings. The insulating layer 414 is an interlayer film provided above the conductive layer 434. Note that the descriptions of the insulating layers 311 to 314 in FIGS. 15B and 15C can be referred to for the insulating layers 411 to 414, respectively.

[0469] The capacitor 400 shown in FIG. 17A illustrates a configuration in which the upper surface of the conductive layer 431 has a recess. The recess can be formed by forming an opening in the insulating layer 412. Therefore, it can be said that the opening includes the side surface of the insulating layer 412 and the bottom surface of the recess in the conductive layer 431. Therefore, the side surface of the insulating layer 412 may be referred to as the side surface of the opening, and the recess in the conductive layer 431 may be referred to as the bottom of the opening. Furthermore, the side wall of the opening includes the side surface of the insulating layer 412. In particular, FIG. 17A illustrates a first region 471 below the opening and a second region 472 above the opening as the side surface of the insulating layer 412. Furthermore, each of the first region 471 and the second region 472 can be said to be the side surface of the opening. Note that the side wall of the opening may also include the side surface of the recess in the conductive layer 431.

[0470] The conductive layer 431 has a recess at a position overlapping the opening of the insulating layer 412, which increases the contact area between the conductive layer 431 and the conductive layer 432 compared to when the conductive layer 431 does not have the recess. This reduces the contact resistance between the conductive layer 431 and the conductive layer 432, which will be described later.

[0471] The conductive layer 432 has a region with rounded corners within the recess of the conductive layer 431. By having this region within the recess, electric field concentration in the insulating layer 441 near this region can be suppressed more effectively than, for example, when the recess has a right angle or an acute angle (a corner). Furthermore, the end of the conductive layer 432 is located at a position lower in height from the reference plane than the top surface of the insulating layer 412. In other words, the conductive layer 432 is located in a first region 471 of the opening of the insulating layer 412. Furthermore, the insulating layer 441 is provided on the top surface of the conductive layer 432, a second region 472 of the opening of the insulating layer 412, and the top surface of the insulating layer 412. Furthermore, the conductive layer 433 is provided on the insulating layer 441 so as to fill the opening of the insulating layer 412.

[0472] The end of the conductive layer 432 is positioned on the side surface of the opening of the insulating layer 412, thereby suppressing electric field concentration in the insulating layer 441 near the end. As described above, suppressing electric field concentration in the insulating layer 441 suppresses dielectric breakdown of the insulating layer 441, thereby providing a highly reliable computing device. Furthermore, since the capacitor 400 has a pair of electrodes provided in the opening of the insulating layer 412, the circuit area of ​​the capacitor 400 in a planar view is smaller than that of a flat capacitor. Therefore, by using the capacitor 400 shown in FIG. 17A as the capacitor included in the circuit, the area of ​​the circuit can be reduced.

[0473] For example, in the memory circuit BUC described in the above embodiment, by using the above-described capacitor 400 as the capacitor C1, leakage current between the pair of electrodes of the capacitor C1, which occurs between the node SN1 and the wiring VE1, can be prevented. Therefore, in the memory circuit BUC, fluctuations in the potential of the node SN1 due to the leakage current can be prevented, and the potential of the node SN1 can be maintained for a long period of time. Furthermore, local electric field concentration on the dielectric of the capacitor C1 can be suppressed, thereby improving the reliability of the memory circuit BUC. Furthermore, since the area of ​​the capacitor C1 in a plan view can be reduced, the circuit area of ​​the memory circuit BUC can be reduced. This also leads to a reduction in the circuit area of ​​the semiconductor device SDV.

[0474] The capacitance value of the capacitor 400 is proportional to the area of ​​a region where the conductive layer 432, the insulating layer 441, and the conductive layer 433 overlap each other. This region can be, for example, a region where the conductive layer 432 and the insulating layer 441 are in contact with each other. Therefore, the height d from the bottom of the opening in the insulating layer 412 to the edge of the conductive layer 432 provided on the side surface of the opening is ｕ The area of ​​the region can be increased by increasing the length d. ｋ When this is the case, d ｕ is d ｋ For example, d ｕ is d ｋ In order to obtain the effect of suppressing electric field concentration in the insulating layer 441 at the end portion of the conductive layer 432 or its vicinity, it is preferable that the ratio of d ｕ is d ｋ It is preferable that the value is 95% or less or 85% or less of d ｕ For example, ｋ It is preferable that the ratio is 80% or more and 85% or less, or 80% or more and 95% or less.

[0475] Furthermore, the capacitance value of the capacitance element 400 is inversely proportional to the distance between the conductive layer 432 and the conductive layer 433, for example, in the schematic plan view of FIG. 17B . Specifically, the capacitance value is inversely proportional to the film thickness of the insulating layer 441. Therefore, in the schematic cross-sectional view of FIG. 17A or the schematic plan view of FIG. 17B , the film thickness of the insulating layer 441 is preferably 100 nm or less, more preferably 50 nm or less, and even more preferably 10 nm or less. Furthermore, to increase the voltage resistance of the capacitance element 400, the film thickness of the insulating layer 441 is preferably 1 nm or more, more preferably 5 nm or more, and even more preferably 10 nm or more. Therefore, the film thickness of the insulating layer 441 is preferably 2 nm or more and 8 nm or less, or 8 nm or more and 12 nm or less, for example.

[0476] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0477] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as Data Centers (DCs)) that can use the arithmetic device described in the above embodiments will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the arithmetic device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0478] [Electronic Component] Fig. 18A shows a perspective view of electronic component 1700. Electronic component 1700 shown in Fig. 18A has substrate 1701, semiconductor device 1710 on substrate 1701, and mold 1711. In particular, semiconductor device 1710 is sealed by mold 1711. Note that Fig. 18A omits some parts in order to show the inside of electronic component 1700.

[0479] The substrate 1701 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.

[0480] Electronic component 1700 is provided with, for example, lead frame 1712. A portion of lead frame 1712 located on substrate 1701 is covered with mold 1711, and another portion of lead frame 1712 is exposed to the outside of mold 1711. In particular, lead frame 1712 exposed to the outside of mold 1711 functions as, for example, a terminal for mounting electronic component 1700 on a printed circuit board.

[0481] Inside mold 1711, electrode pads 1713 are provided on lead frame 1712, and electrode pads 1713 are connected to semiconductor device 1710 via wires 1714. Electronic component 1700 is mounted on a printed circuit board, for example, by contacting lead frame 1712 with wiring on the printed circuit board. In this way, a mounted board is completed by combining multiple electronic components and connecting them on the printed circuit board.

[0482] Next, the semiconductor device 1710 will be described. For example, as shown in FIG. 18B , the semiconductor device 1710 includes a drive circuit layer 1715 and a memory layer 1716. The memory layer 1716 may be configured with a plurality of stacked cell arrays. The cell array may include the arithmetic cells and drive cells, or memory cells, described in the above embodiments. The stacked configuration of the drive circuit layer 1715 and the memory layer 1716 may be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology (e.g., TSV (Through Silicon Via)) or bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 1715 and the memory layer 1716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved, in which memory is formed directly on a processor. The on-chip memory configuration enables faster operation of the interface between the processor and memory. For example, by using the arithmetic unit described in the above embodiment as the processor, it is possible to speed up the transmission of first data (for example, weighting coefficients) from the memory to the arithmetic unit.

[0483] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0484] Furthermore, it is preferable that the multiple memory cell arrays included in the memory layer 1716 are formed using IO transistors and the multiple memory cell arrays are monolithically stacked. By configuring the multiple memory cell arrays as a monolithic stack, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used in the memory layer 1716, it is more difficult to achieve a monolithic stacked configuration than IO transistors. Therefore, it can be said that IO transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0485] The semiconductor device 1710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0486] Next, Fig. 18C shows a modified example of electronic component 1700. Electronic component 1700A shown in Fig. 18C differs from electronic component 1700 in that it does not use lead frame 1712, but has electrodes 1733 provided on the bottom of substrate 1701. Electrodes 1733 function as connection terminals for mounting electronic component 1700A on a printed circuit board.

[0487] In FIG. 18C, an example of forming the electrode 1733 with solder balls is shown. By providing solder balls in a matrix form at the bottom of the substrate 1701, BGA (Ball Grid Array) mounting can be realized. For this reason, through holes (via holes) are provided in the substrate 1701, and a conductive layer 1732 that functions as wiring is provided in these holes. On the substrate 1701, an electrode pad 1713 is provided so as to contact above the conductive layer 1732, and below the substrate 1701, an electrode 1733 is provided so as to contact below the conductive layer 1732.

[0488] Also, the electrode 1733 may be formed with conductive pins instead of solder balls. By providing conductive pins in a matrix form at the bottom of the substrate 1701, PGA (Pin Grid Array) mounting can be realized.

[0489] Further, the electronic component 1700A can be mounted on other substrates using various mounting methods not limited to BGA and PGA. Examples of the mounting methods include, for example, SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0490] Also, the electronic component of one aspect of the present invention may be in the form of SiP (System in Package) or MCM (Multi Chip Module). For example, the electronic component 1700C shown in FIG. 18D has an interposer 1731 provided on a package substrate 1734 (printed substrate), and a semiconductor device 1735 and a plurality of semiconductor devices 1710 are provided on the interposer 1731.

[0491] 18D illustrates an example in which the semiconductor device 1710 is used as a high bandwidth memory (HBM). For example, the semiconductor device 1735 can be used as an arithmetic circuit in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0492] The package substrate 1734 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, similar to the substrate 1701. The interposer 1731 may be, for example, a silicon interposer or a resin interposer.

[0493] The interposer 1731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 1731 also functions to connect the integrated circuits provided on the interposer 1731 to electrodes provided on the package substrate 1734. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 1731, and the integrated circuits and the package substrate 1734 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0494] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0495] Furthermore, in SiP and MCM using silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on the interposer.

[0496] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 1700C, the width of the terminal pitch becomes an issue, and it may be difficult to provide the large number of wirings required to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked configuration using IO transistors is preferable. Also, for example, a memory cell array stacked using TSVs and a monolithically stacked memory cell array can be combined. Furthermore, a structure combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array is sometimes called a hybrid structure.

[0497] Furthermore, if the temperature of the electronic component 1700C increases due to heat generated by electric current or the like, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 1700C may be degraded. Therefore, it is preferable to provide a heat sink (heat sink) on the electronic component 1700C. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 1731. For example, in the electronic component 1700C described in this embodiment, it is preferable to align the height of the semiconductor device 1710 and the semiconductor device 1735.

[0498] [Electronic Device] Next, a perspective view of an electronic device 6500 is shown in FIG. 19A . The electronic device 6500 shown in FIG. 19A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The computing device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.

[0499] 19B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a memory circuit. The computing device of one embodiment of the present invention can be used for the display unit 6615, the control device 6616, and the like.

[0500] The arithmetic circuit of one embodiment of the present invention is preferably used for the control devices 6509 and 6616 because power consumption can be reduced. Furthermore, the speed of the operation of the artificial neural network can be increased.

[0501] [Mainframe] Next, Fig. 19C shows a perspective view of multiple mainframe computers 5600 installed in a server room or the like. The mainframe computer 5600 shown in Fig. 19C has multiple rack-mounted computers 5620 stored in a rack 5610. The mainframe computer 5600 is sometimes called a supercomputer.

[0502] The computer 5620 has a motherboard, which is provided with a plurality of slots, a plurality of connection terminals, etc. For example, one or a plurality of PC cards can be inserted into the slot.

[0503] The PC card is an example of a processing board equipped with a processing unit such as a CPU, a GPU, etc. For example, the electronic component 1700 can be used as the processing unit.

[0504] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0505] [Space Equipment] A computing device according to one embodiment of the present invention can be suitably used in space equipment (for example, equipment having a function of processing and storing information).

[0506] The computing device of one embodiment of the present invention may include an IO transistor. The IO transistor exhibits small variations in electrical characteristics due to radiation exposure. In other words, the IO transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the IO transistor can be suitably used in outer space.

[0507] Fig. 20 shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Fig. 20, a planet 6804 is shown in outer space. Note that outer space refers to an altitude of 100 km or higher, for example, but outer space described in this specification includes the thermosphere, mesosphere, and stratosphere.

[0508] 20 , a battery management system (also referred to as BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an IO transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0509] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0510] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0511] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received, for example, by a receiver on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0512] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory circuit. Note that the control device 6807 is preferably an arithmetic device according to one embodiment of the present invention. IO transistors have smaller fluctuations in electrical characteristics due to radiation exposure than Si transistors. That is, IO transistors have high reliability even in an environment where radiation may be incident, and can be preferably used.

[0513] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0514] Although an artificial satellite is used as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the computing device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0515] As described above, IO transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance than Si transistors.

[0516] [Data Center] The computing device according to one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power source for maintaining the data, and ensuring cooling equipment required for maintaining the data. Furthermore, it is preferable that the data center has a function for performing data calculations, and it is even more preferable that the calculation speed is fast.

[0517] By using the computing device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required for computation and increase the computation speed.

[0518] Furthermore, the computing device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the computing device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0519] Fig. 21 shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 21 has a plurality of servers 7001sb as hosts 7001 (illustrated as Host computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0520] The host 7001 functions as a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0521] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM (Dynamic Random Access Memory), which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0522] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0523] By using IO transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.Furthermore, by using a stacked memory cell array, miniaturization is possible.

[0524] Note that the application of the computing device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of the above-mentioned components, devices, data centers, and the like, the use of the computing device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the computing device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0525] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0526] ASX: switch, BUC: memory circuit, BUCA: memory circuit, BUCB: memory circuit, BUCC: memory circuit, BUCZ: memory circuit, CBT: terminal, CK: signal, CKB: signal, CKL: wiring, CKLB: wiring, CT: terminal, CTL: control logic circuit, FFA: flip-flop, FFB: flip-flop, FFC: flip-flop, FFD: flip-flop, IL: wiring, IMN: transistor, IOCL: circuit layer, IOT: terminal, IPS: signal, IVC: inverter, IVP: inverter, IVX: inverter, OL: wiring, OPS: signal, PW : power supply circuit, SDV: semiconductor device, SICL: circuit layer, SIG: signal, SN: node, ST: terminal, T11: period, T12: period, T13: period, T14: period, T15: period, T16: period, T20: period, T21: period, T22: period, T23: period, T24: period, T25: period, T26: period, TrP: transistor, TrQ: transistor, VDE: wiring, VSE: wiring, 101: substrate, 102: element isolation layer, 111: insulating layer, 112: insulating layer, 113: insulating layer, 114: insulating layer, 115: insulating layer, 116: insulating layer, 131: conductive layer, 132: Conductive layer, 134: conductive layer, 135: conductive layer, 136[1]: conductive layer, 136[2]: conductive layer, 136[3]: conductive layer, 136[4]: conductive layer, 136[5]: conductive layer, 136: conductive layer, 161: insulating layer, 171: semiconductor region, 172: low resistance region, 173: semiconductor region, 173a: semiconductor region, 173b: semiconductor region, 174: low resistance region, 174a: low resistance region, 174b: low resistance region, 174c: low resistance region, 181: insulating layer, 182: insulating layer, 211: insulating layer, 212: insulating layer, 213: insulating layer, 214: insulating layer, 217: insulating layer, 231: conductive layer , 231a: conductive layer, 231b: conductive layer, 232: conductive layer, 232a: conductive layer, 232b: conductive layer, 233: conductive layer, 233_1: conductive layer, 233_2: conductive layer, 233_3: conductive layer, 235: conductive layer, 235_1: conductive layer, 235_2: conductive layer, 235_3: conductive layer, 235a: conductive layer, 235b: conductive layer, 236: conductive layer, 237: conductive layer, 239: conductive layer, 239a: conductive layer, 239b: conductive layer, 241: insulating layer, 251: semiconductor layer, 251a: semiconductor layer, 251b: semiconductor layer, 261: insulating layer, 262: insulating layer, 263: insulating layer, 264: insulating layer,271a: region, 271b: region, 281: insulating layer, 282: insulating layer, 283: insulating layer, 285: insulating layer, 300: transistor, 311: insulating layer, 312: insulating layer, 313: insulating layer, 314: insulating layer, 331: conductive layer, 332: conductive layer, 333: conductive layer, 334: conductive layer, 351: semiconductor layer, 361: insulating layer, 400: capacitor element, 411: insulating layer, 412: insulating layer, 413: insulating layer, 414: insulating layer, 431: conductive layer, 432: conductive layer, 433: conductive layer, 434: conductive layer, 441: insulating layer, 471: first region, 472: second region, 473: edge, 1700: electronic component, 1700A: electronic component, 1700C: electronic component, 1701: substrate, 1710: semiconductor device, 1711: mold, 1712: lead frame, 1713: electrode pad, 1714: wire, 1715: drive circuit layer, 1716: memory layer, 1731: interposer, 1732 : Conductive layer, 1733: Electrode, 1734: Package substrate, 1735: Semiconductor device, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 6500: Electronic device, 6501: Housing, 6502: Display unit, 6503: Power button, 6504: Button, 6505: Speaker, 6506: Microphone, 6507: Camera, 6508: Light source, 6509: Control device, 6600: Electronic device, 6611: Housing, 6612: Keyboard, 6 613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device,

Claims

1. A transistor includes a first inverter, a second inverter, a first analog switch, a first transistor, and a capacitance element, wherein the first inverter includes a second transistor and a third transistor, wherein each of the first transistor and the second transistor is an n-channel transistor including an oxide semiconductor in a channel formation region, the oxide semiconductor including indium, and the third transistor is a p-channel transistor including silicon in a channel formation region, wherein an output terminal of the second inverter is electrically connected to a first terminal of the first transistor, and a second terminal of the first transistor is electrically connected to a first terminal of the capacitance element and an input terminal of the first inverter, wherein an output terminal of the first inverter is electrically connected to a first terminal of the first analog switch, and a second terminal of the first analog switch is electrically connected to an input terminal of the second inverter, wherein a gate of the first transistor is electrically connected to a first wiring, and a p-channel side control terminal of the first analog switch is electrically connected to the first wiring, and wherein input terminals of the first inverter are the gate of the second transistor and the gate of the third transistor, an output terminal of the first inverter is a first terminal of the second transistor and a first terminal of the third transistor.

2. A semiconductor device according to claim 1, wherein the second inverter and the first analog switch each have a transistor containing silicon in a channel forming region.

3. A semiconductor device according to claim 2, comprising a first circuit layer and a second circuit layer located above the first circuit layer, wherein the first circuit layer comprises the third transistor, a transistor included in the second inverter, and a transistor included in the first analog switch, and the second circuit layer comprises the first transistor and the second transistor.

4. A semiconductor device according to claim 3, comprising a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a second analog switch, a third analog switch and a fourth analog switch, wherein the output terminal of the third inverter is electrically connected to the first terminal of the second analog switch, the second terminal of the second analog switch is electrically connected to the first terminal of the third analog switch and the input terminal of the fourth inverter, the output terminal of the fourth inverter is electrically connected to the input terminal of the fifth inverter and the first terminal of the fourth analog switch, the output terminal of the fifth inverter is electrically connected to the second terminal of the third analog switch, and the second terminal of the fourth analog switch is electrically connected to the input terminal of the sixth inverter, the input terminal of the second inverter and the second terminal of the first analog switch.

5. A semiconductor device according to claim 4, wherein the first circuit layer has the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the second analog switch, the third analog switch, and the fourth analog switch, each of which has a transistor including silicon in a channel forming region.

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