Power conversion device

Abstract

An inverter (10) includes a multilevel circuit having a plurality of switching elements (Q1 to Q4), converts first to third DC voltages supplied from a DC positive bus (L1), a DC neutral point bus (L2), and a DC negative bus (L3) into AC voltages, and supplies the AC voltages to a load. A control device superimposes, on a sinusoidal voltage command value, a third harmonic of the voltage command value to generate a reference AC voltage. The control device compares the reference AC voltage with a carrier signal having a peak-peak value corresponding to the DC voltage between the DC positive bus and the DC negative bus and generates a gate signal for turning on and off the plurality of switching elements (Q1-Q4). The control device detects the load factor of the power conversion device from the detection value of output current by a current detector (11). In a first case where the load factor is larger than a predetermined threshold value, the control device increases the amount of superimposition of the third harmonic wave with respect to the voltage command value as compared with a second case where the load factor is equal to or less than the threshold value.

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] Japanese Patent Laid-Open Publication No. 3-82396 (Patent Document 1) discloses a pulse width modulation (PWM) inverter device. This inverter device includes a DC power supply, an inverter including a switching element and diodes connected in antiparallel, a reference voltage generator that outputs a reference voltage waveform that serves as a reference for the output frequency and output voltage, a carrier generator that outputs a carrier wave, a PWM circuit that compares the reference voltage waveform with the carrier wave and generates a gate signal for a switching signal, a drive circuit that drives the switching element upon receiving the gate signal from the PWM circuit, and an output frequency setter that sets the carrier frequency.

[0003] Japanese Patent Application Publication No. 3-82396

[0004] There is an inverter (three-level inverter) that includes a multilevel circuit that converts a positive DC voltage, a neutral voltage, and a negative DC voltage into an AC voltage, and converts DC power into AC power to supply to a load. The multilevel circuit includes first to fourth switching elements and first to fourth diodes connected in anti-parallel to the first to fourth switching elements, respectively.

[0005] In such an inverter, when the first to fourth switching elements are turned on and off in accordance with the gate signal of the PWM circuit, the power loss of the first and second switching elements is greater than the power loss of the third and fourth switching elements because the voltage applied to the first and second switching elements is greater than the voltage applied to the third and fourth switching elements. Therefore, heat tends to be concentrated in the first and second switching elements. This tendency becomes more pronounced when the inverter is operating under overload.

[0006] To prevent damage to the first and second switching elements due to overheating, it is necessary to select switching elements that can withstand heat concentration and to design a cooling structure that suppresses heat concentration. On the other hand, if the inverter is operated below its rated load during normal operation and the time during which the inverter operates under overload is short, the above-mentioned measures to prevent heat concentration may be excessively designed for the operation of the power conversion device. As a result, there is a concern that the power conversion device will unnecessarily increase in cost and size.

[0007] The present disclosure has been made to solve such problems, and an object of the present disclosure is to distribute heat concentration on some switching elements during overload operation in a power conversion device including an inverter with a multilevel circuit.

[0008] [Correction based on Rule 91 05.03.2025] A power conversion apparatus according to one embodiment of the present disclosure includes a variable DC power supply, a first capacitor, a second capacitor, an inverter, a current detector for detecting the inverter's output current, and a control device. The variable DC power supply is connected between a DC positive bus and a DC negative bus. The first capacitor is connected between the DC positive bus and a DC neutral bus. The second capacitor is connected between the DC neutral bus and a DC negative bus. The inverter includes a multilevel circuit having multiple switching elements and converts first to third DC voltages supplied from the DC positive bus, the DC neutral bus, and the DC negative bus into AC voltages and supplies the AC voltages to a load. The control device performs pulse-width modulation control of the on / off drive of the multiple switching elements. The control device generates a reference AC voltage by superimposing a third harmonic of a sinusoidal voltage command value on a voltage command value. The control device is configured to compare a carrier signal having a peak-to-peak value corresponding to the DC voltage between a DC positive bus and a DC negative bus with a reference AC voltage to generate gate signals for driving a plurality of switching elements to turn on and off. The control device detects the load factor of the power conversion device from the output current detected by the current detector. In a second case where the load factor is greater than a predetermined threshold, the control device increases the amount of third harmonic superimposition on the voltage command value compared to a first case where the load factor is equal to or less than the threshold.

[0009] According to the present disclosure, in a power conversion device including an inverter having a multilevel circuit, it is possible to distribute heat concentration on some switching elements during overload operation.

[0010] 1 is a circuit block diagram showing the configuration of an uninterruptible power supply to which a power conversion apparatus according to the present embodiment is applied. FIG. 2 is a block diagram showing an example of the hardware configuration of a control device. FIG. 3 is a circuit block diagram showing the configuration of an inverter and its peripheral parts. FIG. 4 is a block diagram showing the configuration of a portion of the control device related to control of the inverter. FIG. 5 is a diagram showing the waveform of a reference AC voltage. FIG. 6 is a circuit block diagram showing the configuration of a gate control circuit. FIG. 7 is a time chart showing waveforms of a reference AC voltage, a triangular wave signal, and a gate signal. FIG. 8 is a block diagram showing an example of the configuration of a third harmonic generating circuit. FIG. 9 is a block diagram showing an example of the configuration of a reference voltage generating circuit. FIG. 10 is a block diagram showing the configuration of a portion of the control device related to control of a converter and a bidirectional chopper. FIG. 11 is a time chart showing waveforms of a reference AC voltage, a triangular wave signal, and a gate signal in an overload region. FIG. 12 is a diagram showing simulation results of power loss occurring in an inverter. FIG. 13 is a circuit block diagram showing a first modified example of the present embodiment. FIG. 14 is a circuit block diagram showing a second modified example of the present embodiment. FIG. 15 is a circuit block diagram showing a third modified example of the present embodiment.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0012] 1 is a circuit block diagram showing the configuration of an uninterruptible power supply 1 to which a power conversion device according to an embodiment of the present disclosure is applied. The uninterruptible power supply 1 first converts three-phase AC power from a commercial AC power supply 21 into DC power, and then converts the DC power into three-phase AC power to supply to a load 24. In order to simplify the drawing and explanation, only a portion of the circuit corresponding to one phase (e.g., U phase) of the three phases (U phase, V phase, W phase) is shown in FIG. 1 .

[0013] 1, the uninterruptible power supply 1 includes an AC input terminal T1, a bypass input terminal T2, a battery terminal T3, and an AC output terminal T4. The AC input terminal T1 receives AC power at a commercial frequency from a commercial AC power supply 21. The bypass input terminal T2 receives AC power at a commercial frequency from a bypass AC power supply 22. The bypass AC power supply 22 may be a commercial AC power supply or a generator.

[0014] The battery terminal T3 is connected to a battery 23. The battery 23 stores DC power. The battery 23 corresponds to an example of a "power storage device." An electric double capacitor or a flywheel may be connected instead of the battery 23. The AC output terminal T4 is connected to a load 24. The load 24 is driven by AC power supplied from the uninterruptible power supply 1.

[0015] The uninterruptible power supply 1 further includes electromagnetic contactors 2, 8, 14, and 16, current detectors 3 and 11, capacitors 4, 9, and 13, reactors 5 and 12, a converter 6, a bidirectional chopper 7, an inverter 10, a semiconductor switch 15, an operation unit 17, and a control device 18.

[0016] The electromagnetic contactor 2 and the reactor 5 are connected in series between the AC input terminal T1 and the AC node of the converter 6. The electromagnetic contactor 2 is controlled by a control device 18. When AC power is being supplied normally from the commercial AC power supply 21 (when the commercial AC power supply 21 is operating normally), the electromagnetic contactor 2 is turned on. When AC power is no longer being supplied normally from the commercial AC power supply 21 (when the commercial AC power supply 21 experiences a power outage), the electromagnetic contactor 2 is turned off. The current detector 3 detects the AC input current Ii flowing between the commercial AC power supply 21 and the converter 6, and provides a signal Iif indicating the detected value to the control device 18.

[0017] The instantaneous value of the AC input voltage Vi appearing at the node N1 between the electromagnetic contactor 2 and the reactor 5 is detected by the control device 18. The control device 18 determines whether a power outage has occurred based on the detected value of the AC input voltage Vi. The control device 18 also controls the converter 6 and the like in synchronization with the AC input voltage Vi.

[0018] Capacitor 4 is connected to node N1. Capacitor 4 and reactor 5 form a low-pass filter that passes AC power of the commercial frequency from commercial AC power supply 21 to converter 6 and prevents a signal of the switching frequency generated in converter 6 from passing to commercial AC power supply 21.

[0019] The converter 6 is controlled by the control device 18, and when the commercial AC power supply 21 is normal, converts AC power into DC power and outputs it to the DC line L1. The output voltage of the converter 6 can be controlled to a desired value. The DC line L1 constitutes a "DC positive bus." The converter 6 corresponds to one embodiment of a "variable DC power supply."

[0020] In the event of a power outage in the commercial AC power supply 21, the operation of the converter 6 is stopped. The capacitor 9 is connected to the DC line L1 and smooths the voltage of the DC line L1. The instantaneous value of the DC voltage VDC appearing on the DC line L1 is detected by the control device 18. When the commercial AC power supply 21 is functioning normally, the control device 18 controls the converter 6 so that the DC voltage VDC on the DC line L1 becomes the reference DC voltage VDC*.

[0021] DC line L1 is connected to a high-voltage side node of bidirectional chopper 7, and a low-voltage side node of bidirectional chopper 7 is connected to battery terminal T3 via electromagnetic contactor 8. Electromagnetic contactor 8 is turned on when uninterruptible power supply 1 is in use and turned off, for example, during maintenance of uninterruptible power supply 1 and battery 23. The instantaneous value of voltage VB across terminals of battery 23 that appears at battery terminal T3 is detected by control device 18.

[0022] The bidirectional chopper 7 is controlled by the control device 18, and when the commercial AC power supply 21 is operating normally, the bidirectional chopper 7 stores the DC power generated by the converter 6 in the battery 23. When the commercial AC power supply 21 experiences a power outage, the bidirectional chopper 7 supplies the DC power of the battery 23 to the inverter 10 via the DC line L1. The instantaneous value of the voltage VB across the battery 23 appearing at the battery terminal T3 is detected by the control device 18. The bidirectional chopper 7 corresponds to one embodiment of a "variable DC power supply."

[0023] The control device 18 controls the bidirectional chopper 7 so that the battery voltage VB becomes equal to the reference DC voltage VB* when the commercial AC power supply 21 is normal, and controls the bidirectional chopper 7 so that the DC voltage VDC of the DC line L1 becomes equal to the reference DC voltage VDC* when the commercial AC power supply 21 is in a power outage. The DC line L1 is connected to a DC node of the inverter 10.

[0024] The inverter 10 is controlled by a control device 18. The inverter 10 converts DC power supplied from the converter 6 or the bidirectional chopper 7 (variable DC power supply) via a DC line L1 into AC power of a commercial frequency and outputs the AC power to an output node (AC terminal) 10 a.

[0025] That is, when the commercial AC power supply 21 is operating normally, the inverter 10 converts DC power supplied from the converter 6 via the DC line L1 into AC power, and when the commercial AC power supply 21 experiences a power outage, it converts DC power supplied from the battery 23 via the bidirectional chopper 7 into AC power. The output voltage of the inverter 10 can be controlled to a desired value.

[0026] An output node 10a (AC terminal) of the inverter 10 is connected to a first terminal (node ​​N2) of an electromagnetic contactor 14 via a reactor 12, and a second terminal of the electromagnetic contactor 14 is connected to an AC output terminal T4. A capacitor 13 is connected to the node N2. The reactor 12 and the capacitor 13 form a low-pass filter that passes AC power of the commercial frequency generated by the inverter 10 to the AC output terminal T4 and prevents signals of the switching frequency generated by the inverter 10 from passing to the AC output terminal T4.

[0027] The electromagnetic contactor 14 is controlled by the control device 18, and is turned on in an inverter power supply mode in which the AC power generated by the inverter 10 is supplied to the load 24, and is turned off in a bypass power supply mode in which the AC power from the bypass AC power supply 22 is supplied to the load 24.

[0028] The instantaneous value of the AC output voltage Vo appearing at node N2 is detected by control device 18. Current detector 11 detects the current Io flowing between inverter 10 and load 24, and provides a signal Iof indicating the detected value to control device 18. The output current Io of inverter 10 corresponds to the "load current." Control device 18 controls inverter 10 so that the AC output voltage Vo becomes the reference AC voltage Vo*.

[0029] The semiconductor switch 15 includes a pair of thyristors connected in anti-parallel to each other and is connected between the bypass input terminal T2 and the AC output terminal T4. The electromagnetic contactor 16 is connected in parallel to the semiconductor switch 15. The semiconductor switch 15 is controlled by a control device 18, and is normally turned off, but is instantly turned on in the event of a failure in the inverter 10, and supplies AC power from the bypass AC power supply 22 to the load 24. The semiconductor switch 15 is turned off a predetermined time after being turned on.

[0030] The electromagnetic contactor 16 is turned off in an inverter power supply mode in which the AC power generated by the inverter 10 is supplied to the load 24, and is turned on in a bypass power supply mode in which the AC power from the bypass AC power supply 22 is supplied to the load 24. Furthermore, when the inverter 10 fails, the electromagnetic contactor 16 is turned on and supplies the AC power from the bypass AC power supply 22 to the load 24.

[0031] The operation unit 17 includes a plurality of buttons operated by the user of the uninterruptible power supply 1, an image display unit that displays various information, etc. By operating the operation unit 17, the user can turn the power supply of the uninterruptible power supply 1 on and off, and select one of the modes such as the bypass power supply mode and the inverter power supply mode.

[0032] The control device 18 controls the entire uninterruptible power supply 1 based on the AC input voltage Vi, the AC input current Ii, the DC voltage VDC, the terminal voltage VB of the battery 23, the AC output voltage Vo, the AC output current Io, the reference DC voltages VDC* and VB*, the reference AC voltage Vo*, and signals from the operation unit 17.

[0033] 2 is a block diagram showing an example of the hardware configuration of the control device 18. Typically, the control device 18 can be configured by a microcomputer in which a predetermined program is stored in advance.

[0034] 2, the control device 18 includes a CPU (Central Processing Unit) 102, a memory 104, and an input / output (I / O) circuit 106. The CPU 102, the memory 104, and the I / O circuit 106 can exchange data with one another via a bus 108. Programs are stored in a partial area of ​​the memory 104, and the CPU 102 executes these programs to realize various functions described below. The I / O circuit 106 inputs and outputs signals and data to and from the outside of the control device 18.

[0035] 2, at least a part of the control device 18 may be configured using a circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), or at least a part of the control device 18 may be configured using an analog circuit.

[0036] Fig. 3 is a circuit block diagram showing the configuration of the inverter 10 shown in Fig. 1 and its peripheral parts. As shown in Fig. 3, DC lines L1 to L3 are connected between the converter 6 and the inverter 10. DC line L2 is connected to the neutral point NP and is set to the neutral point voltage (e.g., 0 V). DC line L2 constitutes a "DC neutral point bus" and DC line L3 constitutes a "DC negative bus."

[0037] The capacitor 9 includes two capacitors 9a and 9b. The capacitor 9a is connected between the DC lines L1 and L2. The capacitor 9b is connected between the DC lines L2 and L3. The capacitor 9a corresponds to an example of a "first capacitor," and the capacitor 9b corresponds to an example of a "second capacitor."

[0038] When the commercial AC power supply 21 is operating normally, the converter 6 converts AC power from the commercial AC power supply 21 into DC power and supplies it to the DC lines L1 to L3. At this time, the converter 6 charges each of the capacitors 9a and 9b so that the DC voltage VDC between the DC lines L1 and L3 becomes the reference DC voltage VDC*, the DC voltage VDCa between the DC lines L1 and L2 becomes VDC* / 2, and the DC voltage VDCb between the DC lines L2 and L3 becomes VDC* / 2. The DC voltage VDC is the sum of the DC voltages VDCa and VDCb (VDC = VDCa + VDCb).

[0039] The voltages of the DC lines L1, L2, and L3 are set to a positive DC voltage (+VDC* / 2), a neutral point voltage (0 V), and a negative DC voltage (-VDC* / 2), respectively. When the commercial AC power supply 21 fails, the operation of the converter 6 is stopped.

[0040] When the commercial AC power supply 21 is normal, the bidirectional chopper 7 stores the DC power generated by the converter 6 in the battery 23. At this time, the bidirectional chopper 7 charges the battery 23 so that the voltage VB between the terminals of the battery 23 becomes the reference DC voltage VB*.

[0041] When the commercial AC power supply 21 experiences a power outage, the bidirectional chopper 7 supplies DC power from the battery 23 to the inverter 10. At this time, the bidirectional chopper 7 charges each of the capacitors 9a and 9b so that the DC voltage VDC between the DC lines L1 and L3 becomes the reference DC voltage VDC* and the inter-terminal voltages VDCa and VDCb of the capacitors 9a and 9b each become VDC* / 2.

[0042] When the commercial AC power supply 21 is operating normally, the inverter 10 converts the DC power generated by the converter 6 into AC power of the commercial frequency and supplies it to the load 24. When the commercial AC power supply 21 experiences a power outage, the inverter 10 converts the DC power generated by the bidirectional chopper 7 into AC power of the commercial frequency and supplies it to the load 24.

[0043] The inverter 10 is configured by a multilevel circuit that generates a commercial frequency AC output voltage Vo based on a positive DC voltage (first DC voltage), a neutral point voltage (second DC voltage), and a negative DC voltage (third DC voltage) supplied from DC lines L1 to L3.

[0044] Specifically, inverter 10 includes insulated gate bipolar transistors (IGBTs) Q1 to Q4 and diodes D1 to D4. IGBTs Q1 to Q4 correspond to an example of "first to fourth switching elements." In FIG. 3, IGBTs (insulated gate bipolar transistors) are used as the switching elements, but any semiconductor element such as a metal oxide semiconductor field effect transistor (MOSFET) can be used.

[0045] Diodes D1 to D4 are connected in antiparallel to IGBTs Q1 to Q4, respectively. Diodes D1 to D4 are provided to pass a freewheeling current when the corresponding IGBT is turned off. If the switching elements are MOSFETs, diodes D1 to D4 may be configured as parasitic diodes (body diodes).

[0046] IGBT Q1 (first switching element) is connected between DC line L1 (DC positive bus) and output node 10a (AC terminal). The collector of IGBT Q1 is connected to DC line L1, and the emitter is connected to output node 10a.

[0047] IGBT Q2 (second switching element) is connected between DC line L2 (DC neutral bus) and output node 10a. The collector of IGBT Q2 is connected to output node 10a, and the emitter thereof is connected to DC line L3.

[0048] The collectors of IGBT Q3 (third switching element) and IGBT Q4 (fourth switching element) are connected to each other, and the emitters thereof are connected to DC line L2 and output node 10a, respectively. Output node 10a is connected to node N2 via reactor 12.

[0049] In inverter 10, during a first period when reference AC voltage Vo* is positive, IGBTs Q2 and Q4 are turned off and on, respectively, and IGBTs Q1 and Q3 are alternately turned on. During a second period when reference AC voltage Vo* is negative, IGBTs Q1 and Q3 are turned off and on, respectively, and IGBTs Q2 and Q4 are alternately turned on.

[0050] During the first period, when IGBT Q1 is turned on, a positive DC voltage is output from DC line L1 to output node 10a via IGBT Q1. Furthermore, when IGBT Q3 is turned on, output node 10a is connected to DC line L2 via diode D4 and IGBT Q3, and DC line L2 is connected to output node 10a via diode D3 and IGBT Q4, so that output node 10a is at the neutral point voltage. Therefore, during the first period, a positive DC voltage and the neutral point voltage are alternately output to output node 10a.

[0051] During the second period, when IGBT Q2 is turned on, output node 10a is connected to DC line L3 via IGBT Q2, and output node 10a is set to a negative DC voltage. Furthermore, when IGBT Q4 is turned on, DC line L2 is connected to output node 10a via diode D3 and IGBT Q4, and output node 10a is connected to DC line L2 via diode D4 and IGBT Q3, and output node 10a is set to the neutral point voltage. Therefore, during the second period, a negative DC voltage and the neutral point voltage are alternately output to output node 10a.

[0052] Fig. 4 is a block diagram showing the configuration of a portion of the control device 18 that is related to the control of the inverter 10. The function of each block shown in Fig. 4 can be realized by at least one of software processing and hardware processing by the control device 18.

[0053] 4, control device 18 is configured to perform pulse width modulation (PWM) control of the on / off driving of IGBTs Q1 to Q4 (FIG. 3) that make up the multilevel circuit. Specifically, control device 18 includes a reference voltage generation circuit 31, a voltage detector 32, subtractors 33 and 35, an output voltage control circuit 34, an output current control circuit 36, a load factor detector 37, a third harmonic generation circuit 38, an adder 39, a reference voltage generation circuit 40, and a gate control circuit 41.

[0054] The reference voltage generating circuit 31 generates a reference AC voltage Vr, which is a sinusoidal signal of commercial frequency. The phase of the reference AC voltage Vr is synchronized with the phase of the AC input voltage Vi of a corresponding phase (e.g., U phase) among the three phases (U phase, V phase, and W phase).

[0055] The voltage detector 32 detects the instantaneous value of the AC output voltage Vo at the node N2 (FIG. 1) and outputs a signal Vof indicating the detected value. The subtractor 33 calculates the deviation ΔVo between the reference AC voltage Vr and the output signal Vof of the voltage detector 32.

[0056] The output voltage control circuit 34 performs a proportional or proportional-integral operation on the deviation ΔVo to generate a current command value Ior. A subtractor 35 determines the deviation ΔIo between the current command value Ior and the signal Iof from the current detector 11. The output current control circuit 36 ​​performs a proportional or proportional-integral operation on the deviation ΔIo to generate a voltage command value Vor. The voltage command value Vor is a sinusoidal signal at the commercial frequency.

[0057] Load factor detector 37 detects the load factor LF of uninterruptible power supply 1 based on signal Iof from current detector 11 and the rated current of uninterruptible power supply 1, and outputs a signal φLF indicating the detected value to third harmonic generating circuit 38 and reference voltage generating circuit 40. In this specification, the load factor LF indicates the ratio of the load current, with the output current Io (load current) of inverter 10 being 100% when it becomes the rated current (i.e., rated load).

[0058] The third harmonic generating circuit 38 generates a third harmonic 3f·k1 to be superimposed on the voltage command value Vor. The third harmonic generating circuit 38 sets a superimposition amount k1 of the third harmonic on the voltage command value Vor based on the load factor LF detected by the load factor detector 37. This superimposition amount k1 is the ratio of the amplitude of the third harmonic 3f to the amplitude of the voltage command value Vor. The third harmonic generating circuit 38 multiplies a sine wave signal 3f having a frequency three times the frequency of the voltage command value Vor (i.e., the commercial frequency) by the superimposition amount k1 to generate the third harmonic 3f·k1. The third harmonic generating circuit 38 will be described in detail later.

[0059] The adder 39 generates the reference AC voltage Vo* by adding the voltage command value Vor from the output current control circuit 36 ​​and the third harmonic 3f·k1 from the third harmonic generating circuit 38. Fig. 5 is a diagram showing the waveform of the reference AC voltage Vo*.

[0060] The reference AC voltages Vou*, Vov*, and Vow* of the three phases (U phase, V phase, and W phase) when the superposition amount k1 of the third harmonic 3f is set to 1 / 6 are determined by the following equations (1) to (3).

[0061]

[0062]

[0063]

[0064] However, E ０ is the peak-to-peak value of a triangular wave signal, which will be described later, and is equal to half the magnitude of the DC voltage VDC (E ０ = VDC / 2).

[0065] Here, since the maximum value of sin θ+(1 / 6) sin(3θ) is √3 / 2, even if α=2 / √3, the maximum value of the reference AC voltage Vo* is the peak-to-peak value E of the triangular wave signal. ０ (i.e., VDC / 2) or less. This makes it possible to turn on and off IGBTs Q1 to Q4 in PWM over the entire period of reference AC voltage Vo*.

[0066] In addition, in the sine wave comparison method in which the voltage command value Vor, which is a sine wave, is compared with a triangular wave signal, the maximum value of the fundamental wave amplitude of the outputtable phase voltage Vo is VDC / 2, and the maximum value of the fundamental wave amplitude of the line voltage is √3 / 2 times VDC≈0.87 VDC.

[0067] In contrast, in the method shown in FIG. 5 in which the third harmonic 3f·k1 is superimposed on the voltage command value Vor, the third harmonic is cancelled out, so that the maximum value of the fundamental wave amplitude of the line voltage becomes VDC, and the voltage utilization rate can be increased by approximately 15.5% compared to the sine wave comparison method.

[0068] 4, the reference voltage generating circuit 40 generates a reference DC voltage VDC* based on the load factor LF detected by the load factor detector 37. The reference voltage generating circuit 40 will be described in detail later.

[0069] The gate control circuit 41 generates gate signals φ1 to φ4 for controlling the inverters 10 of the corresponding phases. Fig. 6 is a circuit block diagram showing the configuration of the gate control circuit 41. As shown in Fig. 6, the gate control circuit 41 includes an oscillator 51, triangular wave generators 52 and 53, comparators 54 and 55, buffers 56 and 58, and NOT circuits 57 and 59.

[0070] The oscillator 51 outputs a clock signal having a frequency sufficiently higher than the commercial frequency. The triangular wave generators 52 and 53 output triangular wave signals Cua and Cub, respectively, having the same frequency as the output clock signal of the oscillator 51. The triangular wave signal Cua is a signal that varies on the positive side. The triangular wave signal Cub is a signal that varies on the negative side. The triangular wave signals Cua and Cub correspond to an example of a "carrier wave signal." The carrier wave signal may be a sawtooth wave.

[0071] The triangular wave generators 52 and 53 adjust the peak-to-peak values ​​of the triangular wave signals Cua and Cub based on the reference DC voltage VDC* provided by the reference voltage generating circuit 40 (FIG. 4). The triangular wave generators 52 and 53 set the peak-to-peak values ​​of the triangular wave signals Cua and Cub to half the magnitude of the reference DC voltage VDC*. Note that half the reference DC voltage VDC* is greater than the amplitude of the reference AC voltage Vo*.

[0072] As a result, the peak-to-peak values ​​of the triangular wave signals Cua and Cub become larger than the amplitude of the reference AC voltage Vo*, and the IGBTs are turned on and off at every cycle of the triangular wave signals, thereby enabling the inverter 10 to generate an AC output voltage Vo having an amplitude proportional to the amplitude of the reference AC voltage Vo*.

[0073] The comparator 54 compares the reference AC voltage Vo* with the triangular wave signal Cua from the triangular wave generator 52, and outputs a PWM signal φ54 indicating the comparison result. The frequency of the PWM signal φ54 is determined based on the frequency of the triangular wave signal Cua. The pulse width of the PWM signal φ54 varies based on the level of the reference AC voltage Vo*.

[0074] The comparator 55 compares the reference AC voltage Vo* with the triangular wave signal Cub from the triangular wave generator 53, and outputs a PWM signal φ55 indicating the comparison result. The frequency of the PWM signal φ55 is determined based on the frequency of the triangular wave signal Cub. The pulse width of the PWM signal φ55 varies based on the level of the reference AC voltage Vo*.

[0075] The buffer 56 supplies the PWM signal φ54 as a gate signal φ1 to the inverter 10. The NOT circuit 57 inverts the PWM signal φ54 and supplies it to the inverter 10 as a gate signal φ3.

[0076] The buffer 58 supplies the PWM signal φ55 as a gate signal φ2 to the inverter 10. The NOT circuit 59 inverts the PWM signal φ55 and supplies the inverted signal to the inverter 10 as a gate signal φ4.

[0077] 7 is a time chart showing the waveforms of the reference AC voltage Vo*, the triangular wave signals Cua and Cub, and the gate signals φ1 to φ4. As shown in FIG. 5, the reference AC voltage Vo* is a signal obtained by adding the third harmonic 3f·k1 to the voltage command value Vor, which is a sinusoidal signal at the commercial frequency. In FIG. 7, the amount k1 of the third harmonic superimposed on the voltage command value Vor is set to 1 / 6.

[0078] The minimum value of the triangular wave signal Cua is 0 V, and its maximum value is higher than the positive peak value of the reference AC voltage Vo*. The maximum value of the triangular wave signal Cub is 0 V, and its minimum value is lower than the negative peak value of the reference AC voltage Vo*. The triangular wave signals Cua and Cub are in-phase signals, and the phases of the triangular wave signals Cua and Cub are synchronized with the phase of the reference AC voltage Vo*. The frequencies of the triangular wave signals Cua and Cub are higher than the frequency (commercial frequency) of the reference AC voltage Vo*.

[0079] As shown in Figures 7(A) and (B), when the level of the triangular wave signal Cua is higher than the reference AC voltage Vo*, the gate signal φ1 becomes L level, and when the level of the triangular wave signal Cua is lower than the reference AC voltage Vo*, the gate signal φ1 becomes H level.

[0080] In the first period when the reference AC voltage Vo* is positive, the pulse width of the gate signal φ1 increases as the reference AC voltage Vo* increases. In the second period when the reference AC voltage Vo* is negative, the gate signal φ1 is fixed at the L level. As shown in Figures 7B and 7E, the gate signal φ3 is an inverted version of the gate signal φ1.

[0081] As shown in Figures 7(A) and (C), when the level of the triangular wave signal Cub is lower than the reference AC voltage Vo*, the gate signal φ2 becomes L level, and when the level of the triangular wave signal Cub is higher than the reference AC voltage Vo*, the gate signal φ2 becomes H level.

[0082] During the first period when the reference AC voltage Vo* is positive, the gate signal φ2 is fixed at the L level. During the second period when the reference AC voltage Vo* is negative, the pulse width of the gate signal φ2 increases as the reference AC voltage Vo* decreases. As shown in Figures 7C and 7D, the gate signal φ4 is an inverted version of the gate signal φ2.

[0083] During periods (t0 to t1, t2 to t3, t4 to t5, t6 to t7, etc.) when gate signals φ1 and φ2 are both at L level and gate signals φ3 and φ4 are both at H level, IGBTs Q1 and Q2 are both turned off and IGBTs Q3 and Q4 are turned on, thereby outputting the neutral point voltage (0 V) of DC line L2 to output node 10a via IGBTs Q3 and Q4.

[0084] During periods (t1 to t2, t3 to t4, t5 to t6, etc.) when gate signals φ1 and φ4 are both at H level and gate signals φ2 and φ3 are both at L level, IGBTs Q1 and Q4 are both turned on and IGBTs Q2 and Q3 are turned off, causing the positive DC voltage (+VDC / 2) on DC line L1 to be output to output node 10a via IGBT Q1.

[0085] During periods when gate signals φ2 and φ3 are both at H level and gate signals φ1 and φ4 are both at L level (t7 to t8, t9 to t10, t11 to t12, t13 to t14, etc.), IGBTs Q2 and Q3 are both on and IGBTs Q1 and Q4 are off, causing the negative DC voltage (−VDC / 2) on DC line L3 to be output to output node 10a via IGBT Q2.

[0086] As shown in Figures 7B to 7E, when the waveforms of the gate signals φ1 to φ4 change, an AC output voltage Vo having the same waveform as the reference AC voltage Vo* shown in Figure 7A is output between node N2 and neutral point NP. Note that although Figures 7A to 7E show the waveforms of the reference AC voltage Vo* and signals Cua, Cub, and φ1 to φ4 corresponding to the U phase, the waveforms of the reference AC voltages and signals corresponding to the V phase and W phase are similar. However, the phases of the reference AC voltages and signals corresponding to the U phase, V phase, and W phase are shifted by 120 degrees.

[0087] Although the AC output voltages Vou, Vov, and Vow of the U, V, and W phases each have a third harmonic superimposed on them, the line voltages (Vuv = Vou - Vov, Vvw = Vov - Vow, Vwu = Vow - Vou) become sinusoidal signals of the commercial frequency because the third harmonics are cancelled out.

[0088] As described above, by adopting a method of superimposing the third harmonic 3f·k1 on the voltage command value Vor for PWM control of the inverter 10, the voltage utilization rate can be improved compared to the sine wave comparison method.

[0089] On the other hand, the power loss of IGBTs Q1 and Q2 tends to be larger than the power loss of IGBTs Q3 and Q4 in inverter 10. The power loss of an IGBT includes conduction loss, which is the power loss that occurs when the IGBT is conducting, and switching loss (SW loss), which is the power loss that occurs when the IGBT performs a switching operation.

[0090] In both the power loss of IGBTs Q1 and Q2 and the power loss of IGBTs Q3 and Q4, the conduction loss is greater than the switching loss. The conduction loss of an IGBT is proportional to the product of the IGBT's on-resistance, collector current, and on-time. The switching loss of an IGBT is proportional to the product of the maximum collector-emitter voltage of the IGBT, the maximum collector current of the IGBT, the IGBT's switching time (turn-on time + turn-off time), and the switching frequency.

[0091] In addition, if SiC-MOSFETs are used instead of IGBTs for the first to fourth switching elements that make up inverter 10, SW loss is significantly reduced, and therefore conduction loss becomes dominant in the power loss of each switching element.

[0092] This tendency for the conduction loss of IGBTs Q1 and Q2 to be greater than the conduction loss of IGBTs Q3 and Q4 becomes more pronounced in the overload region where the load factor exceeds the rated load, because in the overload region, the collector current of the IGBT increases as the load current increases.

[0093] Due to this relationship in the magnitude of conduction loss, heat is concentrated in IGBTs Q1 and Q2 in inverter 10. In particular, in the overload region, the difference in conduction loss between IGBTs Q1 and Q2 and IGBTs Q3 and Q4 increases, which can make the concentration of heat in IGBTs Q1 and Q2 even more pronounced.

[0094] To prevent damage to IGBTs Q1 and Q2 due to overheating, it is necessary to select switching elements that can withstand thermal damage and to design a cooling structure that can suppress heat concentration in IGBTs Q1 and Q2. On the other hand, in the operation of uninterruptible power supply 1, if inverter 10 operates below the rated load during normal operation and the period of overload operation is shorter than the period of normal operation, the above-mentioned measures against heat concentration may be excessively designed for the operation of uninterruptible power supply 1. As a result, there is a concern that uninterruptible power supply 1 will be unnecessarily increased in cost and size.

[0095] To address such concerns, in this embodiment, the amount k1 of third harmonic superimposition on the voltage command value Vor is variably set according to the load factor LF of the uninterruptible power supply 1. Specifically, in the third harmonic generating circuit 38 shown in Fig. 4, the amount k1 of third harmonic superimposition on the voltage command value Vor is increased in the overload region.

[0096] As will be described later, increasing the amount of third harmonic superposition k1 reduces the proportion of the on-period of IGBTs Q1 and Q2 in one period of reference AC voltage Vo*, while increasing the proportion of the on-period of IGBTs Q3 and Q4. This reduces the amount of current through IGBTs Q1 and Q2, thereby reducing the conduction loss of IGBTs Q1 and Q2, and increases the amount of current through IGBTs Q3 and Q4, thereby increasing the conduction loss of IGBTs Q3 and Q4. As a result, the imbalance between the power loss of IGBTs Q1 and Q2 and the power loss of IGBTs Q3 and Q4 is reduced, and heat concentration in IGBTs Q1 and Q2 can be dispersed.

[0097] Fig. 8 is a block diagram showing an example of the configuration of the third harmonic generating circuit 38 shown in Fig. 4. As shown in Fig. 8, the third harmonic generating circuit 38 includes a superposition amount setting unit 60 and a multiplier 61.

[0098] The superimposition amount setting unit 60 sets the superimposition amount k1 of the third harmonic with respect to the voltage command value Vor based on the load factor LF indicated by the output signal φLF of the load factor detector 37. In one aspect, as shown in FIG. 8 , the superimposition amount setting unit 60 sets the superimposition amount k1 from the load factor LF by referring to a predetermined relationship between the load factor LF and the superimposition amount k1.

[0099] In the above relationship, in the region where the load factor LF is equal to or less than the threshold value Lth (first case), the superposition amount k1 is set to 1 / 6. On the other hand, in the region where the load factor LF exceeds the threshold value Lth (second case), the superposition amount k1 is set to a value greater than 1 / 6. This threshold value Lth is set to, for example, the rated load (100%). However, the threshold value Lth may be set to a value less than the rated load (100%) depending on the degree of imbalance between the power loss of IGBTs Q1 and Q2 and the power loss of IGBTs Q3 and Q4.

[0100] In the example of FIG. 8 , in the region where the load factor LF exceeds the threshold value Lth (second case), the superimposition amount k1 is set to continuously increase as the load factor LF increases. However, the relationship between the load factor LF and the superimposition amount k1 in this region is not limited to this. For example, in response to the load factor LF exceeding the threshold value Lth, the superimposition amount k1 may be increased from 1 / 6 to a value greater than 1 / 6. Alternatively, in the region where the load factor LF exceeds the threshold value Lth, the superimposition amount k1 may be increased in stages as the load factor LF increases.

[0101] As the superposition amount k1 of the third harmonic increases, the waveform of the reference AC voltage Vo* deviates from the original sinusoidal waveform of the voltage command value Vor. Therefore, distortion due to the third harmonic may occur in the waveforms of the line voltages of the AC output voltages Vou, Vov, and Vow of the U, V, and W phases (Vuv = Vou - Vov, Vvw = Vov - Vow, Vwu = Vow - Vou). Distortion in the waveforms of the line voltages may interfere with the operation of the load 24. Therefore, as shown in FIG. 8 , an upper limit k1max is set for the superposition amount k1. This upper limit k1max can be set through experimentation or simulation so as not to interfere with the operation of the load 24.

[0102] The multiplier 61 multiplies the superposition amount k1 set by the superposition amount setting unit 60 by a sine wave signal 3f having a frequency three times the frequency of the voltage command value Vor (i.e., the commercial frequency) to generate a third harmonic 3f·k1.

[0103] Here, as shown in the above equations (1) to (3), when the superposition amount k1 is 1 / 6, the maximum value of the reference AC voltage Vo* is equal to or less than the peak-to-peak value of the triangular wave signal (i.e., VDC / 2). On the other hand, when the superposition amount k1 is greater than 1 / 6, the maximum value of the reference AC voltage Vo* is greater than the peak-to-peak value of the triangular wave signal (i.e., VDC / 2). In this case, the IGBT does not perform on / off operation during the period when the reference AC voltage Vo* is greater than the peak-to-peak value of the triangular wave signal, which causes problems such as loss of proportionality between the amplitude of the AC output voltage Vo and the amplitude of the reference AC voltage Vo* and an increase in harmonic components of the AC output voltage Vo.

[0104] To avoid this problem, it is necessary to increase the peak-to-peak value of the triangular wave signal (i.e., VDC / 2) in accordance with an increase in the superimposition amount k1 of the third harmonic. Therefore, in this embodiment, the reference DC voltage VDC* is increased in accordance with the superimposition amount k1 of the third harmonic. This causes the IGBTs Q1 to Q4 to be constantly in on-off operation.

[0105] Fig. 9 is a block diagram showing an example of the configuration of the reference voltage generating circuit 40 shown in Fig. 4. As shown in Fig. 9, the reference voltage generating circuit 40 includes an increase amount setting unit 71 and a multiplier 72.

[0106] The increase amount setting unit 71 sets the increase amount k2 of the reference DC voltage VDC* based on the load factor LF indicated by the output signal φLF of the load factor detector 37. In one aspect, as shown in FIG. 9 , the increase amount setting unit 71 sets the increase amount k2 from the load factor LF by referring to a predetermined relationship between the load factor LF and the increase amount k2.

[0107] In the above relationship, in the region where the load factor LF is equal to or less than the threshold value Lth (first case), the increase amount k2 is set to 1.0. On the other hand, in the region where the load factor LF exceeds the threshold value Lth (second case), the increase amount k2 is set to a value greater than 1.0.

[0108] In the example of Fig. 9, in the region where the load factor LF exceeds the threshold value Lth (second case), the increase amount k2 is set to continuously increase as the load factor LF increases. However, the relationship between the load factor LF and the increase amount k2 in this region is not limited to this. For example, the increase amount k2 may be increased from 1.0 to a value greater than 1.0 as the load factor LF exceeds the threshold value Lth. Alternatively, in the region where the load factor LF exceeds the threshold value Lth, the increase amount k2 may be increased in stages as the load factor LF increases.

[0109] Note that as the reference DC voltage VDC* (i.e., the DC voltage VDC) is increased, SW losses in the switching elements of the converter 6, the bidirectional chopper 7, and the inverter 10 increase, which may reduce the operating efficiency of the uninterruptible power supply 1. For this reason, an upper limit k2max is set for the increase amount k2, as shown in Fig. 9. This upper limit k2max can be set based on the minimum DC voltage VDC necessary to ensure the on / off operation of the IGBTs, taking into account the upper limit k1max of the superposition amount k1.

[0110] The multiplier 72 multiplies the reference value VDCr of the reference DC voltage VDC* by the increase amount k2 set by the increase amount setting unit 71 to generate the reference DC voltage VDC*=VDCr×k2.

[0111] Returning to FIG. 1 , the control device 18 controls the converter 6 or the bidirectional chopper 7 so that the DC voltage VDC between the DC lines L1 and L3 becomes the reference DC voltage VDC*, the DC voltage VDCa between the DC lines L1 and L2 becomes VDC* / 2, and the DC voltage VDCb between the DC lines L2 and L3 becomes VDC* / 2.

[0112] 10 is a block diagram showing the configuration of a portion of the control device 18 that is related to the control of the converter 6 and the bidirectional chopper 7. The control device 18 further includes a power failure detector 62, a reference voltage generation circuit 64, and a control unit 65.

[0113] The power failure detector 62 detects whether a power failure has occurred in the commercial AC power supply 21 based on the AC input voltage Vi supplied from the commercial AC power supply 21, and outputs a power failure detection signal φF indicating the detection result to the control unit 65. The power failure detector 62 determines that a power failure has occurred in the commercial AC power supply 21, for example, when the effective value of the AC input voltage Vi falls below a lower limit value. When the commercial AC power supply 21 is operating normally, the power failure detection signal φF is set to an H level. When a power failure has occurred in the commercial AC power supply 21, the power failure detection signal φF is set to an L level.

[0114] 9 , the reference voltage generating circuit 40 generates the reference DC voltage VDC* based on the load factor LF indicated by the output signal φLF of the load factor detector 37. The reference voltage generating circuit 40 outputs the generated reference DC voltage VDC* to the control unit 65.

[0115] The reference voltage generating circuit 64 generates a reference DC voltage VB* according to the type of the battery 23 and outputs it to the control unit 65. The reference DC voltage VB* is a DC voltage that is applied to the battery 23 when the battery 23 is charged.

[0116] The control unit 65 controls the converter 6 and the bidirectional chopper 7 based on the signal φF from the power failure detector 62, the reference DC voltage VDC* from the reference voltage generation circuit 40, the reference DC voltage VB* from the reference voltage generation circuit 64, the DC voltage VDC between the DC lines L1 and L3, the voltage VB between the terminals of the battery 23, and the AC input current Ii indicated by the output signal Iif of the current detector 3, etc.

[0117] Specifically, when the power failure detection signal φF is at H level (when the commercial AC power supply 21 is normal), the control unit 65 controls the converter 6 so that the DC voltage VDC becomes the reference DC voltage VDC*, the DC voltage VDCa between the DC lines L1 and L2 becomes VDC* / 2, and the DC voltage VDCb between the DC lines L2 and L3 becomes VDC* / 2. The control unit 65 also controls the bidirectional chopper 7 so that the voltage VB between the terminals of the battery 23 becomes the reference DC voltage VB*.

[0118] When the power failure detection signal φF is at an L level (when the commercial AC power supply 21 experiences a power failure), the control unit 65 stops the operation of the converter 6. The control unit 65 controls the bidirectional chopper 7 so that the DC voltage VDC becomes the reference DC voltage VDC*, the DC voltage VDCa between the DC lines L1 and L2 becomes VDC* / 2, and the DC voltage VDCb between the DC lines L2 and L3 becomes VDC* / 2.

[0119] FIG. 11 is a time chart showing the waveforms of the reference AC voltage Vo*, the triangular wave signals Cua and Cub, and the gate signals φ1 to φ4 in the overload region, and is to be compared with FIG.

[0120] 11, the reference AC voltage Vo* is a signal obtained by adding the voltage command value Vor and the third harmonic 3f·k1, as in FIG. 7. However, in FIG. 11, the amount k1 of superimposition of the third harmonic on the voltage command value Vor is set to a value greater than 1 / 6 (for example, k1=1 / 3). Therefore, the maximum value of the reference AC voltage Vo* is greater than the maximum value of the reference AC voltage Vo* shown in FIG.

[0121] In addition, in FIG. 11, the peak-to-peak values ​​of the triangular wave signals Cua and Cub are increased by increasing the reference DC voltage VDC* (ie, the DC voltage VDC) in accordance with an increase in the reference AC voltage Vo*.

[0122] 11 and 7 , it can be seen that increasing the superimposed amount k1 of the third harmonic increases the oscillation of the waveform of the reference AC voltage Vo* due to the third harmonic. As shown in (A), (B), and (E) of FIG. 11 , during the first period when the reference AC voltage Vo* is positive, the oscillation of the reference AC voltage Vo* causes the pulse width of the gate signal φ1 to decrease while the pulse width of the gate signal φ3 to increase compared to FIG. 7 . As shown in (A), (C), and (D) of FIG. 11 , during the second period when the reference AC voltage Vo* is negative, the oscillation of the reference AC voltage Vo* causes the pulse width of the gate signal φ2 to decrease while the pulse width of the gate signal φ4 to increase compared to FIG. 7 .

[0123] In this way, during the first period when reference AC voltage Vo* is positive, increasing the superimposed amount k1 of the third harmonic reduces the proportion of the on-period of IGBT Q1 during the first period, while increasing the proportion of the on-period of IGBT Q3. The decrease in the proportion of the on-period of IGBT Q1 reduces the amount of current flowing through IGBT Q1 during the first period, thereby reducing the conduction loss of IGBT Q1. Meanwhile, the increase in the proportion of the on-period of IGBT Q3 increases the amount of current flowing through IGBT Q3 during the first period, thereby increasing the conduction loss of IGBT Q3.

[0124] During the second period when the reference AC voltage Vo* is negative, increasing the superimposed amount k1 of the third harmonic reduces the proportion of the on-period of IGBT Q2 during the second period, while increasing the proportion of the on-period of IGBT Q4. The decrease in the proportion of the on-period of IGBT Q2 reduces the amount of current flowing through IGBT Q2 during the second period, thereby reducing the conduction loss of IGBT Q2. On the other hand, the increase in the proportion of the on-period of IGBT Q4 increases the amount of current flowing through IGBT Q4 during the second period, thereby increasing the conduction loss of IGBT Q4.

[0125] As a result, in the overload region, the conduction loss of IGBTs Q1 and Q2 decreases while the conduction loss of IGBTs Q3 and Q4 increases, thereby reducing the imbalance between the power loss of IGBTs Q1 and Q2 and the power loss of IGBTs Q3 and Q4 and making it possible to disperse heat concentration in IGBTs Q1 and Q2.

[0126] 12 shows the results of a simulation of the power loss occurring in the inverter 10. FIG. 12 is a diagram for explaining the breakdown of the power loss occurring in the inverter 10 in the overload region.

[0127] The left side of Fig. 12 shows a breakdown of the power loss when the superimposition amount k1 of the third harmonic is 1 / 6. The right side of Fig. 12 shows a breakdown of the power loss when the superimposition amount k1 of the third harmonic is 1 / 2.

[0128] 12, when k1 = 1 / 6, the conduction loss of IGBTs Q1 and Q2 is about three times larger than the conduction loss of IGBTs Q3 and Q4. Furthermore, the ratio of the power loss of IGBTs Q1 and Q2 to the power loss of IGBTs Q3 and Q4 is 4:1, which means there is a large imbalance between the power loss of IGBTs Q1 and Q2 and the power loss of IGBTs Q3 and Q4.

[0129] Referring to the right side of FIG. 12 , by increasing k1 from 1 / 6 to 1 / 2, the conduction loss of IGBTs Q1 and Q2 is reduced by approximately 10%. In contrast, the conduction loss of IGBTs Q3 and Q4 is increased by approximately 60%. The conduction loss of IGBTs Q1 and Q2 is approximately 1.8 times the conduction loss of IGBTs Q3 and Q4. The ratio of the power loss of IGBTs Q1 and Q2 to the power loss of IGBTs Q3 and Q4 is 2:1, improving the imbalance between the power loss of IGBTs Q1 and Q2 and the power loss of IGBTs Q3 and Q4.

[0130] 12, by increasing the superimposition amount k1 of the third harmonic, the power loss generated in inverter 10 increases, but the imbalance between the power loss in IGBTs Q1 and Q2 and the power loss in IGBTs Q3 and Q4 is improved, and it can be seen that the heat concentration in IGBTs Q1 and Q2 is dispersed. This makes it possible to relax measures against the heat concentration in IGBTs Q1 and Q2 during overload operation, and therefore makes it possible to suppress increases in the cost and size of uninterruptible power supply 1.

[0131] (Modifications of the Present Embodiment) Figure 13 is a circuit block diagram showing a first modification of the present embodiment, and is a diagram to be compared with Figure 3. Inverter 10 according to the first modification differs from inverter 10 shown in Figure 3 in that IGBT Q3 and IGBT Q4 are connected in reverse. That is, the emitters of IGBTs Q3 and Q4 are connected to each other, and the collectors of IGBTs Q3 and Q4 are connected to output node 10a and DC line L2, respectively. The first modification provides the same effects as the above-described embodiment.

[0132] Fig. 14 is a circuit block diagram showing a second modification of the present embodiment, and is a diagram to be compared with Fig. 3. Inverter 10 according to the second modification differs from inverter 10 shown in Fig. 3 in the connection relationship between IGBTs Q3 and Q4 and diodes D3 and D4.

[0133] The collector of IGBT Q3 is connected to the cathode of diode D4, and the emitter of IGBT Q3 is connected to DC line L2. The anode of diode D4 is connected to output node 10a. The collector of IGBT Q4 is connected to the cathode of diode D3, and the emitter of IGBT Q4 is connected to output node 10a. The anode of diode D3 is connected to DC line L2. In the second modified example, the same effects as in the above-described embodiment can be obtained.

[0134] Fig. 15 is a circuit block diagram showing a third modification of the present embodiment, and is a diagram to be compared with Fig. 3. The inverter 10 according to the third modification has a different configuration from the inverter 10 shown in Fig. 3.

[0135] As shown in Figure 15, inverter 10 includes IGBTs Q1 to Q4 and diodes D1 to D6. The collector of IGBT Q1 (first switching element) is connected to DC line L1, and the emitter of IGBT Q1 is connected to the collector of IGBT Q4 (fourth switching element). The emitter of IGBT Q4 is connected to output node 10a. The collector of IGBT Q3 (third switching element) is connected to output node 10a, and the emitter of IGBT Q3 is connected to the collector of IGBT Q2 (second switching element). The emitter of IGBT Q2 is connected to DC line L3.

[0136] Diodes D1 to D4 are connected in anti-parallel to IGBTs Q1 to Q4, respectively. Diode D5 (fifth diode) has its anode connected to the emitter of IGBT Q3 and its cathode connected to DC line L2. Diode D6 (sixth diode) has its anode connected to DC line L2 and its cathode connected to the collector of IGBT Q4.

[0137] In inverter 10, during a first period, IGBTs Q2 and Q4 are turned off and on, respectively, and IGBTs Q1 and Q3 are alternately turned on. During a second period, IGBTs Q1 and Q3 are turned off and on, respectively, and IGBTs Q2 and Q4 are alternately turned on.

[0138] During the first period, when IGBT Q1 is turned on, a positive DC voltage is output from DC line L1 to output node 10a via IGBTs Q1 and Q4. Furthermore, when IGBT Q3 is turned on, output node 10a is connected to DC line L2 via IGBT Q3 and diode D5, and DC line L2 is connected to output node 10a via diode D6 and IGBT Q4, so that output node 10a is at the neutral point voltage. Therefore, during the first period, a positive DC voltage and a neutral point voltage are alternately output to output node 10a.

[0139] During the second period, when IGBT Q2 is turned on, output node 10a is connected to DC line L3 via IGBTs Q2 and Q3, and output node 10a is set to a negative DC voltage. Furthermore, when IGBT Q4 is turned on, DC line L2 is connected to output node 10a via diode D6 and IGBT Q4, and output node 10a is connected to DC line L2 via IGBT Q3 and diode D5, and output node 10a is set to the neutral point voltage. Therefore, during the second period, a negative DC voltage and a neutral point voltage are alternately output to output node 10a.

[0140] The configuration and operation of control device 18 are similar to those shown in Figures 4 to 6 and 8 to 10, and therefore description thereof will not be repeated. The waveforms of reference AC voltage Vo*, triangular wave signals Cua and Cub, and gate signals φ1 to φ4 are as shown in Figures 7 and 11. Therefore, the third modified example can achieve the same effects as the above-described embodiment.

[0141] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0142] 1 Uninterruptible power supply, 2, 8, 14, 16 Electromagnetic contactor, 3, 11 Current detector, 4, 9, 9a, 9b, 13 Capacitor, 5, 12 Reactor, 6 Converter, 7 Bidirectional chopper, 10 Inverter, 15 Semiconductor switch, 17 Operation unit, 18 Control device, 21 Commercial AC power supply, 22 Bypass AC power supply, 23 Battery, 24 Load, 31, 40, 64 Reference voltage generation circuit, 32 Voltage detector, 33, 35 Subtractor, 34 Output voltage control circuit, 36 Output current control circuit, 37 Load factor detector, 38 Third harmonic generation circuit, 39 Adder, 41 Gate control circuit, 51 Oscillator, 52, 53 Triangular wave generator, 54, 55 Comparator, 56, 58 Buffer, 60 Superposition amount setting unit, 61, 72 Multiplier, 62 Power outage detector, 65 Control unit, 71 increase amount setting unit, 102 CPU, 104 memory, 106 I / O circuit, 108 bus, L1 to L3 DC lines, T1 AC input terminal, T2 bypass input terminal, T3 battery terminal, T4 AC output terminal.

Claims

1. [Amendment based on Rule 91 05.03.2025] A power conversion device comprising: a variable DC power supply connected between a DC positive bus and a DC negative bus; a first capacitor connected between the DC positive bus and a DC neutral bus; a second capacitor connected between the DC neutral bus and the DC negative bus; an inverter including a multilevel circuit having a plurality of switching elements, which converts first to third DC voltages supplied from the DC positive bus, the DC neutral bus, and the DC negative bus into AC voltages and supplies the AC voltages to a load; a current detector which detects the output current of the inverter; and a control device which performs pulse width modulation control of the on / off driving of the plurality of switching elements, wherein the control device generates a reference AC voltage by superimposing a third harmonic of a sinusoidal voltage command value on the voltage command value, a control device configured to compare a carrier signal having a peak-to-peak value corresponding to the DC voltage between the DC positive bus and the DC negative bus with the reference AC voltage to generate gate signals for driving the plurality of switching elements on and off, the control device detecting a load factor of the power conversion device from a detection value of the output current by the current detector, and increasing the amount of superimposition of the third harmonic on the voltage command value in a second case where the load factor is greater than a predetermined threshold value compared to a first case where the load factor is equal to or less than the threshold value.

2. The power conversion device according to claim 1, wherein in the second case, the control device increases the amount of superimposition of the third harmonic on the voltage command value in response to an increase in the load factor.

3. The power conversion device according to claim 1, wherein the control device sets the amount of superimposition of the third harmonic to 1 / 6 in the first case, and sets the amount of superimposition of the third harmonic to a value greater than 1 / 6 in the second case.

4. [Correction based on Rule 91 05.03.2025] The power conversion device according to claim 1, wherein the control device is configured to control the variable DC power supply so that the DC voltage between the DC positive bus and the DC negative bus becomes a reference DC voltage, and the control device increases the reference DC voltage in the second case compared to the first case.

5. The power conversion device according to claim 4, wherein in the second case, the control device increases the reference DC voltage in response to an increase in the load factor so that the peak-to-peak value of the carrier signal is equal to or greater than the amplitude of the reference AC voltage.

6. The multilevel circuit includes: an AC terminal receiving the AC voltage; a first switching element connected between the DC positive bus and the AC terminal; a second switching element connected between the DC negative bus and the AC terminal; a third switching element connected between the DC neutral bus and the AC terminal; a fourth switching element connected between a first terminal of the third switching element and the AC terminal or between a second terminal of the third switching element and the DC neutral bus; and first to fourth diodes connected in anti-parallel to the first to fourth switching elements, respectively; and the control device alternately turns on the first and third switching elements during a first period in which the reference AC voltage is positive, and maintains the first and third switching elements in an off state and an on state, respectively, during a second period in which the reference AC voltage is negative, 6. The power conversion device according to claim 1, wherein the second and fourth switching elements are alternately turned on during the second period, and the second and fourth switching elements are maintained in an off state and an on state, respectively, during the first period.

7. The multilevel circuit includes: an AC terminal receiving the AC voltage; a first switching element connected between the DC positive bus and the AC terminal; a third switching element connected between the DC neutral bus and the AC terminal; a second switching element connected between a first terminal of the third switching element and the DC negative bus; a fourth switching element connected between a first terminal of the first switching element and the AC terminal; first to fourth diodes connected in anti-parallel to the first to fourth switching elements, respectively; a fifth diode connected between the first terminal of the third switching element and the DC neutral bus; and a sixth diode connected between the DC neutral bus and the first terminal of the first switching element; and the control device alternately turns on the first and third switching elements during a first period in which the reference AC voltage is positive, and maintains the first and third switching elements in an off state and an on state, respectively, during a second period in which the reference AC voltage is negative.

6. The power conversion device according to claim 1, wherein the second and fourth switching elements are alternately turned on during the second period, and the second and fourth switching elements are maintained in an off state and an on state, respectively, during the first period.

8. The power conversion device according to claim 4 or 5, wherein the variable DC power supply includes a converter that converts an AC voltage supplied from an AC power supply into the first to third DC voltages and supplies them to the DC positive bus, the DC neutral bus, and the DC negative bus, and the control device controls the converter so that the DC voltage between the DC positive bus and the DC negative bus becomes the reference DC voltage when the AC power supply is operating normally.

9. The power conversion device according to claim 8, wherein the variable DC power supply further includes a bidirectional chopper that exchanges DC power between the DC positive bus, the DC neutral bus, and the DC negative bus and a power storage device, and wherein the control device, in the event of a power outage of the AC power supply, stops operation of the converter and controls the bidirectional chopper so that the DC voltage between the DC positive bus and the DC negative bus becomes the reference DC voltage.

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