Display drive circuit and display device

Abstract

[Problem] To make it possible to prevent variation in writing voltages of a plurality of signal lines with a small circuit scale. [Solution] A display drive circuit comprises: a signal generation circuit that generates a first signal having a signal level which changes in accordance with time or a signal level which is in accordance with a pixel signal; and an output circuit that outputs, to an output line, a second signal obtained by correcting the signal level of the first signal in accordance with a signal level of the output line. The output circuit has a differential circuit that outputs a third signal in accordance with a signal difference between the first signal and the second signal, and an output circuit that generates the second signal on the basis of the third signal.

Description

Display driver circuit and display device

[0001] The present disclosure relates to a display driver circuit and a display device.

[0002] In a display device, a drive circuit is known that drives multiple signal lines using a ramp voltage whose voltage level changes over time. When multiple signal lines are connected to an output node of a ramp voltage generation circuit, the write voltage of the signal lines may fluctuate due to parasitic capacitance between adjacent signal lines. To address this, a display drive circuit has been proposed that feeds back the voltage of the output node of the ramp voltage generation circuit and controls the ramp voltage according to the feedback voltage (see Patent Document 1).

[0003] Also, a signal line driver circuit has been proposed that provides a switch between a positive-side operational amplifier and a negative-side operational amplifier and an output buffer to switch connections depending on polarity inversion, thereby shortening the settling time (see Patent Document 2).Also, a signal line driver circuit for a display device has been proposed that switches connections between a positive-side or negative-side D / A converter and an output amplifier depending on polarity, thereby enabling data cross control to function normally (see Patent Document 3).

[0004] International Publication No. 2023 / 182100 JP 2009-162789 A JP 2011-059501 A

[0005] In the technology of Patent Document 1, multiple capacitors are required for each signal line to feedback control the ramp voltage, which increases the circuit size. Also, parasitic capacitance may be added to the capacitor for feedback control, and this parasitic capacitance may cause fluctuations in the write voltage of the signal line even when feedback control of the ramp voltage is performed.

[0006] Patent Documents 2 and 3 do not assume that the write voltage for each signal line is generated from a ramp voltage, and therefore cannot solve the above-mentioned problem of Patent Document 1.

[0007] Therefore, the present disclosure provides a display driver circuit and a display device that can suppress fluctuations in the write voltage of each signal line with a small circuit scale.

[0008] In order to solve the above problems, according to the present disclosure, there is provided a display driving circuit comprising: a signal generating circuit that generates a first signal having a signal level that changes over time or a signal level that corresponds to a pixel signal; and an output circuit that outputs a second signal, the signal level of which is corrected according to the signal level of an output line, to the output line, wherein the output circuit has: a differential circuit that outputs a third signal that corresponds to a signal difference between the first signal and the second signal; and an output circuit that generates the second signal based on the third signal.

[0009] The differential circuit may have a first differential circuit that outputs the third signal, and a second differential circuit that outputs an offset signal that is included in the second signal and has a fixed voltage level, and the output circuit may alternately select the third signal or the offset signal to generate the second signal.

[0010] The third signal may be a signal whose voltage level can change over time, and the second signal may be a signal that alternates between a first period in which the voltage level can change over time and is generated based on the third signal, and a second period in which the voltage level is fixed and is generated based on the offset signal.

[0011] The output line may include a first output line and a second output line, and the output circuit may have: a first output circuit that outputs the second signal to the first output line; and a second output circuit that outputs the second signal to the second output line, wherein while the first output circuit outputs the second signal for the first period, the second output circuit outputs the second signal for the second period, and while the first output circuit outputs the second signal for the second period, the second output circuit outputs the second signal for the first period.

[0012] The first signal may be a ramp voltage whose voltage level changes over time, and the power supply may include a load circuit arranged on a feedback path between the first output circuit and the second output circuit, and the signal generating circuit may control a current flowing through the load circuit in accordance with the ramp voltage and a reference voltage.

[0013] The signal generating circuit may include a comparator that compares the ramp wave voltage with the reference voltage, and a holding circuit that holds a comparison result signal of the comparator, and the signal generating circuit may control the current flowing through the load circuit based on the comparison result signal.

[0014] The output circuit may include a switch that switches between inputting the second signal output from the first output circuit to the comparator and inputting it to the second differential circuit, and that alternately switches between inputting the second signal output from the second output circuit to the comparator and inputting it to the second differential circuit.

[0015] The first differential circuit may output the third signal according to a voltage difference between a feedback voltage input via the load circuit and a first reference voltage.

[0016] While one of the first output circuit and the second output circuit is outputting the second signal whose voltage level changes over time from the first reference voltage, the other output circuit may output the second signal at a substantially constant voltage level according to the second reference voltage.

[0017] The first output circuit and the second output circuit may alternately switch, every one or more frame periods, between outputting the second signal whose voltage level changes with time, and outputting the second signal whose voltage level is approximately constant according to the second reference voltage.

[0018] The pixel pixel circuit may further include a signal line voltage generation circuit connected to the first output line and the second output line, which holds the voltage level of the second signal at a timing corresponding to the signal level of the pixel signal to generate signal line voltages for the first signal line and the second signal line.

[0019] The first signal lines or the second signal lines may be alternately connected for each of one or more pixel rows including a plurality of pixels aligned in the column direction.

[0020] The output circuit may alternately output the second signal in the first period or the second period to the output line.

[0021] The first signal is a ramp voltage whose voltage level changes over time, and the output circuit comprises: a load circuit arranged on a feedback path of the output circuit; a comparator that compares the ramp voltage with a reference voltage; and a holding circuit that holds a comparison result signal of the comparator; the signal generating circuit controls a current to be flowed to the load circuit based on the comparison result signal; and the output circuit may have a switch that switches whether the second signal is input to the comparator or the second differential circuit.

[0022] The output circuit may alternately switch within one frame period between outputting the second signal whose voltage level changes with time and outputting the second signal whose voltage level is approximately constant according to a second reference voltage.

[0023] The pixel pixel may further include a signal line voltage generating circuit connected to the output line, which generates a signal line voltage for the signal line by holding the voltage level of the second signal at a timing according to the signal level of the pixel signal.

[0024] The signal generating circuit may generate the first signal at a signal level corresponding to the pixel signal, and the first differential circuit may output the third signal corresponding to the signal difference between the first signal and the second signal.

[0025] The signal generation circuit may include: a resistor ladder circuit including a plurality of resistors connected in series and parallel, and outputting voltage signals with different voltage levels from between the plurality of resistors; and a selector that selects each of the plurality of voltage signals output from the resistor ladder circuit based on the value of each bit of a bit string of the pixel signal, and combines the selected voltage signals to generate the first signal.

[0026] The signal voltage generating circuit may be connected to the output line, and may generate a signal line voltage for the signal line by maintaining the signal level of the second signal in synchronization with the timing at which the voltage level of the second signal changes.

[0027] The present disclosure also provides a display device comprising: a display unit having a plurality of pixels arranged in a first direction and a second direction; and a plurality of signal lines arranged at predetermined intervals in the first direction and supplying a signal line voltage to two or more pixels arranged in the second direction; and a display drive circuit that drives the plurality of signal lines, wherein the display drive circuit comprises: a signal generation circuit that generates a first signal having a signal level that changes with time or a signal level that corresponds to a pixel signal; and an output circuit that outputs a second signal to the output line, the second signal having a signal level corrected for the first signal according to the signal level of the output line, and the output circuit has: a differential circuit that outputs a third signal that corresponds to the signal difference between the first signal and the second signal; and an output circuit that generates the second signal based on the third signal.

[0028] 1 is a block diagram showing the overall configuration of a display device according to a first embodiment of the present disclosure. FIG. 1 is a block diagram showing an example of the internal configuration of a horizontal logic circuit and a horizontal analog circuit. FIG. 2 is a voltage waveform diagram of a ramp voltage, a PWM signal, and a signal line voltage. FIG. 3 is a block diagram showing an example of the internal configuration of a display drive circuit and a pixel array unit. FIG. 4 is a block diagram showing the configuration of a main part of a display drive circuit according to a first embodiment of the present disclosure. FIG. 5 is an operation timing diagram of the display drive circuit of FIG. 5. FIG. 6 is a circuit diagram of an output buffer according to the first embodiment of the present disclosure. FIG. 7 is a block diagram showing the configuration of a lamp drive circuit according to a first comparative example. FIG. 8 is a block diagram showing the configuration of a lamp drive circuit according to a second comparative example. FIG. 9 is a circuit diagram of an output buffer according to a first modified example of FIG. 7. FIG. 10 is a circuit diagram of an output buffer according to a second modified example of FIG. 7. FIG. 11 is a block diagram showing the configuration of a main part of a display drive circuit according to a third embodiment of the present disclosure. FIG. 12 is an operation timing diagram of the display drive circuit of FIG. 13. FIG. 14 is a block diagram showing the configuration of a main part of a display drive circuit according to a fourth embodiment of the present disclosure. 17A . 17B is a block diagram showing a first configuration of a resistor ladder circuit. 17C is a block diagram showing a second configuration of a resistor ladder circuit. 17D is a block diagram showing a third configuration of a resistor ladder circuit. 17E is a diagram showing a connection configuration of signal lines and the like of a display drive circuit according to a fifth embodiment of the present disclosure. 17F is a diagram showing a connection configuration of signal lines and the like of a display drive circuit according to a first modified example of FIG. 17A. 17G is a diagram showing a connection configuration of signal lines and the like of a display drive circuit according to a second modified example of FIG. 17A. 17H is a diagram showing a connection configuration of signal lines and the like of a display drive circuit according to a third modified example of FIG. 17A. 17H is a diagram showing a connection configuration of signal lines and the like of a display drive circuit according to a fourth modified example of FIG. 17A. 17H is a diagram showing a connection configuration of signal lines and the like of a display drive circuit according to a fifth modified example of FIG. 17A. 17H is a diagram showing a connection configuration of signal lines and the like of a display drive circuit according to a sixth modified example of FIG. 17A. 17H is a block diagram showing a schematic configuration of a display device according to a sixth embodiment of the present disclosure. 17I is a block diagram showing an example of the internal configuration of the horizontal analog circuit of FIGS. 1 and 18. 17I is a circuit diagram of a pixel circuit according to a first specific example. 17I is a circuit diagram of a pixel circuit according to a second specific example. 17I is a circuit diagram of a pixel circuit according to a third specific example. 17I is a circuit diagram of a pixel circuit according to a fourth specific example. 10A to 10C are circuit diagrams of a pixel circuit according to a fifth specific example, a circuit diagram of a pixel circuit according to a sixth specific example, a circuit diagram of a pixel circuit according to a seventh specific example, and a circuit diagram of a pixel circuit according to an eighth specific example.10. A circuit diagram of a pixel circuit according to a ninth specific example. A diagram showing an example of the appearance of a first head-mounted display. A diagram showing an example of the appearance of a second head-mounted display. A front view of a digital still camera. A rear view of a digital still camera. A diagram showing an example of the appearance of a television device. A diagram showing an example of the appearance of a smartphone. A diagram showing an example of the interior of a vehicle as seen from the rear of the vehicle. A diagram showing an example of the interior of a vehicle as seen from the left rear of the vehicle.

[0029] Hereinafter, embodiments of a display driver circuit and a display device will be described with reference to the drawings. The following description will focus on the main components of the display driver circuit and the display device, but the display driver circuit and the display device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0030] Fig. 1 is a block diagram showing the overall configuration of a display device 1 according to a first embodiment of the present disclosure. The display device 1 in Fig. 1 shows the overall configuration of, for example, a micro OLED (Organic Light Emitting Display). Note that, as will be described later, the display device 1 according to the present disclosure is not necessarily limited to a micro OLED, and can be applied to various display devices 1 such as a liquid crystal display device.

[0031] The display device 1 in FIG. 1 includes an input / output interface unit (I / O) 2, a gamma generation circuit 3, a power supply circuit 4, a high-speed interface unit (high-speed I / F) 5, a control circuit 6, a vertical logic circuit 7, a vertical analog circuit 8, a horizontal logic circuit 9, a horizontal analog circuit 10, and a pixel array unit (display unit) 11.

[0032] 1 , at least the horizontal analog circuit 10 is referred to as a display drive circuit 20. The display drive circuit 20 may be interpreted as including at least one of the control circuit 6, the horizontal logic circuit 9, the vertical logic circuit 7, and the vertical analog circuit 8 in addition to the horizontal analog circuit 10.

[0033] The input / output interface unit 2 inputs and outputs pixel data, various control signals, etc. The gamma generation circuit 3 generates a gamma voltage for correcting the signal line voltage in the pixel array unit 11. The gamma generation circuit 3 is not an essential component and may be omitted.

[0034] The high-speed interface unit 5 inputs and outputs control signals and the like that need to be input and output at high speed, among the signals input and output by the input / output interface unit 2 .

[0035] The control circuit 6 generates various control signals for controlling each section in the display device 1. The control circuit 6 also controls the timing at which each pixel in the pixel array section 11 is driven.

[0036] The vertical logic circuit 7 performs control to drive a plurality of scanning lines arranged at regular intervals in the vertical direction (second direction) Y in the pixel array unit 11, based on a control signal from the control circuit 6. The vertical logic circuit 7 is composed of digital circuits such as logic gates and flip-flops.

[0037] The vertical analog circuit 8 drives a plurality of scanning lines in synchronization with the signal output from the vertical logic circuit 7. The vertical analog circuit 8 is composed of analog circuits such as transistors.

[0038] The horizontal logic circuit 9 performs control to drive a plurality of signal lines arranged at regular intervals in the horizontal direction (first direction) X in the pixel array unit 11, based on a control signal from the control circuit 6. The horizontal logic circuit 9 is composed of digital circuits such as logic gates and flip-flops.

[0039] The horizontal analog circuit 10 drives a plurality of signal lines in synchronization with the signals output from the horizontal logic circuit 9. The horizontal analog circuit 10 is composed of analog circuits such as transistors.

[0040] The pixel array section 11 has a plurality of scanning lines arranged at regular intervals in the vertical direction Y, a plurality of signal lines arranged at regular intervals in the horizontal direction X, and a plurality of pixels arranged at the points where the plurality of scanning lines and the plurality of signal lines intersect.

[0041] 2 is a block diagram showing an example of the internal configuration of the horizontal logic circuit 9 and the horizontal analog circuit 10. The horizontal logic circuit 9 has a shift register (S / R) 13, a plurality of first latches (1st latches) 14, a plurality of second latches (2nd latches) 15, a plurality of digital comparators 16, and a plurality of PWM generation circuits 18. The first latches 14, the second latches 15, the digital comparators 16, and the PWM generation circuits 18 are provided for each signal line SIGn.

[0042] The shift register 13 sequentially shifts and outputs externally input video data pixel by pixel. The first latches 14 sequentially hold the pixel data output from the shift register 13. The second latches 15 simultaneously hold the pixel data at the timing when the first latches 14 hold the corresponding pixel data.

[0043] The plurality of digital comparators 16 compare the data held in the plurality of second latches 15 with the count value of the synchronous counter 17 to determine whether or not they match, and output a signal indicating the comparison result.

[0044] The PWM generating circuits 18 start generating pulse signals in response to the PWMST signal, and generate PWM signals having pulse widths until a match is detected by the corresponding digital comparators 16 .

[0045] The horizontal analog circuit 10 includes a plurality of level shifters 19 , a lamp driving circuit 21 , and a signal line voltage generating circuit 22 .

[0046] The plurality of level shifters 19 convert the voltage levels of the plurality of PWM signals.

[0047] The lamp driving circuit 21 generates a ramp voltage whose voltage level changes over time and outputs it to an output line (lamp wiring). The lamp driving circuit 21 is a characteristic part of the display device 1 according to the present disclosure, and will be described in detail later.

[0048] The signal line voltage generation circuit 22 generates the signal line voltage by maintaining the voltage level of the ramp voltage at a timing corresponding to the signal level of the pixel signal. More specifically, the signal line voltage generation circuit 22 maintains the voltage level of the ramp voltage at the falling edge of the PWM signal.

[0049] The signal line voltage generation circuit 22 has a plurality of PWM switches 23 connected to a plurality of signal lines SIGn. One end of each PWM switch 23 is connected to a corresponding signal line SIGn, and a ramp voltage is input to the other end of each PWM switch 23. Each PWM switch 23 is turned on when the corresponding PWM signal is at a high level, and turned off when the corresponding PWM signal is at a low level.

[0050] 3 is a voltage waveform diagram of a ramp voltage, a PWM signal, and a signal line voltage. As shown in FIG. 3, the ramp voltage w1 is a voltage signal whose voltage level changes linearly for each horizontal (1H) line. The voltage level of the ramp voltage w1 in FIG. 3 decreases linearly for each horizontal line, but as will be described later, a ramp voltage whose voltage level increases linearly, a triangular ramp voltage, or a ramp voltage whose voltage level changes nonlinearly can also be applied.

[0051] Each PWM switch 23 in the signal line voltage generation circuit 22 is turned on while the corresponding PWM signal is at high level, and supplies a ramp voltage to the corresponding signal line SIGn. Each PWM switch 23 is turned off at timing t1 or t2 when the PWM signal transitions to low level, and the corresponding signal line SIGn maintains the voltage level of the ramp voltage at that timing, which becomes the signal line voltage w3 or w4.

[0052] FIG. 4 is a block diagram showing an example of the internal configuration of the display drive circuit 20 and the pixel array unit 11. FIG. 4 shows an example in which one pixel column arranged in the vertical direction Y of the pixel array unit 11 is driven by two lamp wirings (a first output line RLa and a second output line RLb). In the example of FIG. 4, two lamp drive circuits 21 are arranged at both ends in the vertical direction Y. The two lamp drive circuits 21 are connected to different lamp wirings. Also, in FIG. 4, two signal lines connected to the two lamp wirings are arranged for each pixel column. Each signal line extends in the vertical direction Y and is connected to multiple pixels. Of four pixels adjacent in the vertical direction Y in each pixel column, two adjacent pixels are driven by one lamp wiring, and the remaining two adjacent pixels are driven by the other lamp wiring. The configuration of FIG. 4 is used to realize 2SIG drive, which will be described later.

[0053] Specifically, the lamp driving circuit 21 includes a first lamp driving circuit 21a that outputs a ramp voltage to a first output line RLa, and a second lamp driving circuit 21b that outputs a ramp voltage to a second output line RLb.

[0054] The first output line RLa is connected to the signal lines SIGk_A and SIG(k+1)_A via the PWM switch 23. The second output line RLb is connected to the signal lines SIGk_B and SIG(k+1)_B via the PWM switch 23.

[0055] Hereinafter, the signal lines connected to the first output line RLa (SIGk_A and SIG(k+1)_A in FIG. 4) and the signal lines connected to the second output line RLb (SIGk_B and SIG(k+1)_B in FIG. 4) will also be referred to as the first signal line and the second signal line, respectively.

[0056] The first signal line is connected to the pixel 11a in the pixel array section 11. The second signal line is connected to the pixel 11b in the pixel array section 11.

[0057] Each of the pixels 11a and 11b in the pixel array unit 11 includes, for example, a transistor 12a and a light-emitting element 12b. A first signal line or a second signal line is connected to the gate of the transistor 12a, and a signal line voltage is supplied to the transistor 12a. The transistor 12a applies a current corresponding to the signal line voltage to the light-emitting element 12b. This causes the light-emitting element 12b to emit light with a brightness corresponding to the signal line voltage.

[0058] The above-described configurations of the pixels 11a and 11b are simplified, and the pixels 11a and 11b may actually have multiple transistors, capacitors, etc. Furthermore, there are multiple variations in the configurations of the pixels and pixel circuits. Details of the pixels and pixel circuits will be described later.

[0059] 4, each pixel column extending in the vertical direction Y in the pixel array unit 11 includes two pixels 11a and 11b connected to two different output lines (i.e., a first output line RLa and a second output line RLb). The configuration in Fig. 4 has the feature that the time during which a signal line voltage can be written to the pixels can be doubled compared to a configuration in which one pixel column is connected to one common output line.

[0060] 4 shows an example in which two first signal lines (i.e., signal lines SIGk_A and SIG(k+1)_A) and two second signal lines (i.e., signal lines SIGk_B and SIG(k+1)_B) are alternately connected to a plurality of pixels aligned in the vertical direction Y, but the arrangement of the signal lines is not limited to this. For example, a configuration in which the first signal lines or the second signal lines are alternately connected for every one or more pixel rows aligned in the vertical direction Y is also possible.

[0061] The pixel array unit 11 may have a configuration in which one pixel column is connected to one common output line (the first output line RLa or the second output line RLb), or one pixel column may include pixels connected to a third output line or the like other than the first output line RLa and the second output line RLb.

[0062] Fig. 5 is a block diagram showing the configuration of a main part of a display drive circuit 20 according to the first embodiment of the present disclosure. The display drive circuit 20 in Fig. 5 includes at least a horizontal analog circuit 10. The horizontal analog circuit 10 in Fig. 5 has a lamp drive circuit 21 and a signal line voltage generation circuit 22.

[0063] 3, the signal line voltage generation circuit 22 converts a digital signal (PWM signal) input to the PWM switch 23 into a signal line voltage, which is an analog signal, based on the ramp wave voltage output by the lamp drive circuit 21. In this specification, the lamp drive circuit 21 and the signal line voltage generation circuit 22 shown in FIG. 5 are also collectively referred to as a RAMPDAC (RAMP digital to analog converter).

[0064] The lamp driving circuit 21 includes a signal generating circuit 31 , an output buffer (output circuit) 32 , and a current control circuit (integrator) 33 .

[0065] The signal generating circuit 31 outputs a first signal which is a ramp voltage whose voltage level changes over time. The signal generating circuit 31 includes, for example, a variable current source 34. The variable current source 34 outputs the first signal based on a comparison result signal (described later) output from the current control circuit 33. One end of the variable current source 34 is connected to the power supply voltage node, and the other end is connected to the input node of the output buffer 32.

[0066] The output buffer 32 outputs a second signal to an output line (ramp wiring) RL. The output buffer 32 has an output node to which the output line RL is connected. The output line RL includes a first output line RLa and a second output line RLb. The second signal is a signal obtained by correcting the signal level of the first signal input from the signal generating circuit 31 in accordance with the signal level of the output line RL. In other words, the output buffer 32 performs feedback control of the output signal (second signal) to the output line RL.

[0067] The PWM switch 23 is connected to the first output line RLa and the second output line RLb, and holds the voltage level of the second signal at a timing according to the signal level of the pixel signal to generate signal line voltages for the first signal line and the second signal line.

[0068] The output buffer 32 has a load circuit 41, a differential circuit (differential stage) 42, a RAMPEN switch 43, a PRCG switch 44, an output circuit (output stage) 45, a first switching circuit (switch) 46, a second switching circuit 47, and a third switching circuit 48.

[0069] The differential circuit 42 has a first differential circuit (first differential stage) 51 and a second differential circuit (second differential stage) 52. The output circuit 45 has a first output circuit (first output stage) 53 and a second output circuit (second output stage) 54.

[0070] The load circuit 41 is disposed on a feedback path of the output circuit 45. One end of the load circuit 41 is connected to the output node of the output circuit 45 and the output line RL via the first switching circuit 46, and the other end is connected to the input node of the first differential circuit 51. The load circuit 41 includes, for example, a first capacitor 41a. The load circuit 41 may also include a resistor element, a diode, or the like.

[0071] The current flowing through the load circuit 41 is controlled by the variable current source 34. The load circuit 41 inputs, to the first differential circuit 51, a feedback voltage VFB_A that corresponds to the signal level of the second signal output to the output line RL and the current controlled by the variable current source 34.

[0072] The first differential circuit 51 has a first input node to which the first reference voltage VG0 is input, and a second input node to which the feedback voltage VFB_A is input via the load circuit 41. The first differential circuit 51 outputs a third signal corresponding to the voltage difference between the first reference voltage VG0 and the feedback voltage VFB_A. The third signal is a signal that serves as the base of the second signal output by the output buffer 32.

[0073] The feedback voltage VFB_A is a voltage obtained by feedback-controlling the first signal output from the signal generating circuit 31 based on the second signal output to the output line RL. The first differential circuit 51 outputs a third signal corresponding to the signal difference between the first and second signals based on the feedback voltage VFB_A.

[0074] The RAMPEN switch 43 is turned on or off based on the logic of the RAMPEN signal. The RAMPEN switch 43 is connected between the output node of the signal generating circuit 31 (i.e., one end of the variable current source 34) and the second input node of the first differential circuit 51. When the RAMPEN switch 43 is turned on, the current output from the signal generating circuit 31 flows to the load circuit 41, and the ramp voltage (i.e., the signal level of the second signal), which is the output voltage of the output buffer 32, decreases over time. When the RAMPEN switch 43 is turned off, no current flows from the signal generating circuit 31 to the load circuit 41, and the signal level of the second signal is maintained.

[0075] The PRCG switch 44 is turned on or off based on the logic of a precharge (PRCG) signal. The PRCG switch 44 is connected in parallel to the load circuit 41. The PRCG switch 44 is turned on for a predetermined period immediately after one horizontal line period starts, and short-circuits both ends of the load circuit 41.

[0076] The second differential circuit 52 has a first input node to which the second reference voltage VOFS is input and a second input node to which the feedback voltage VFB_B is input. The second input node of the second differential circuit 52 is connected to the output node of the output circuit 45 and the output line RL via the first switching circuit 46. That is, the feedback voltage VFB_B has a voltage level corresponding to the signal level of the second signal. The second differential circuit 52 outputs an offset signal of a substantially constant voltage level corresponding to the voltage difference between the second reference voltage VOFS and the feedback voltage VFB_B. Like the third signal, the offset signal is a signal that serves as the base of the second signal.

[0077] As described above, the first differential circuit 51 outputs a third signal whose voltage level can change over time, whereas the second differential circuit 52 differs in that it outputs an offset signal whose voltage level is fixed.

[0078] Either the third signal or the offset signal is input to the first output circuit 53 and the second output circuit 54. The first output circuit 53 and the second output circuit 54 generate second signals based on the input signals. The first output circuit 53 outputs the second signal to the first output line RLa. The second output circuit 54 outputs the second signal to the second output line RLb.

[0079] The first output circuit 53 and the second output circuit 54 invert the logic of the input signal and output the inverted signal. That is, the second signal output by the first output circuit 53 and the second output circuit 54 is, for example, an inverted signal of the signal (third signal or offset signal) input from the input node.

[0080] The first output circuit 53 is switched by the second switching circuit 47 to be connected to either the first differential circuit 51 or the second differential circuit 52. The second output circuit 54 is switched by the third switching circuit 48 to be connected to either the first differential circuit 51 or the second differential circuit 52. When the first output circuit 53 is connected to either the first differential circuit 51 or the second differential circuit 52, the second output circuit 54 is connected to the other of the first differential circuit 51 or the second differential circuit 52.

[0081] That is, the third signal is input from the first differential circuit 51 to either the first output circuit 53 or the second output circuit 54. Based on the input third signal, either one of the first output circuit 53 or the second output circuit 54 outputs a second signal (hereinafter also referred to as a second signal having a ramp waveform) whose voltage level changes over time from the first reference voltage VG0.

[0082] Furthermore, while one of the above is outputting the second signal having a ramp waveform, the other receives an offset signal from the second differential circuit 52. Based on the input offset signal, the other outputs a second signal having a substantially constant voltage level corresponding to the second reference voltage VOFS (hereinafter also referred to as a second signal having an offset level).

[0083] The second signals output by the first output circuit 53 and the second output circuit 54 are input to the load circuit 41 and the current control circuit 33, or are input as a feedback voltage VFB_B to the second differential circuit 52. When one of the first output circuit 53 and the second output circuit 54 outputs the second signal to the load circuit 41 and the current control circuit 33, the other outputs the second signal to the second differential circuit 52.

[0084] The first switching circuit 46 switches whether the second signal output from the first output circuit 53 is input to the comparator 35 or the second differential circuit 52, and also switches whether the second signal output from the second output circuit 54 is input to the comparator 35 or the second differential circuit.

[0085] Specifically, the first switching circuit 46 has, for example, switches 46a, 46b, 46c, and 46d. The switch 46a switches between connecting and disconnecting the output node of the first output circuit 53 and the input nodes of the load circuit 41 and the current control circuit 33. The switch 46b switches between connecting and disconnecting the output node of the first output circuit 53 and the second input node of the second differential circuit 52. The switch 46c switches between connecting and disconnecting the output node of the second output circuit 54 and the second input node of the second differential circuit 52. The switch 46d switches between connecting and disconnecting the output node of the second output circuit 54 and the input nodes of the load circuit 41 and the current control circuit 33.

[0086] The second switching circuit 47 includes, for example, switches 47 a, 47 b, 47 c, and 47 d. The switches 47 a and 47 c switch between connecting or not connecting the two output nodes of the first differential circuit 51 and the two input nodes of the first output circuit 53. The switches 47 b and 47 d switch between connecting or not connecting the two output nodes of the second differential circuit 52 and the two input nodes of the first output circuit 53.

[0087] The third switching circuit 48 includes, for example, switches 48a, 48b, 48c, and 48d. The switches 48a and 48c switch between connecting or disconnecting the two output nodes of the second differential circuit 52 and the two input nodes of the second output circuit 54. The switches 48b and 48d switch between connecting or disconnecting the two output nodes of the first differential circuit 51 and the two input nodes of the second output circuit 54.

[0088] The switches 46a, 46c, 47a, 47c, 48a, and 48c are turned on or off based on the logic of the SIG_VOFSSEL signal, and the switches 46b, 46d, 47b, 47d, 48b, and 48d are turned on or off based on the logic of an inverted signal of the SIG_VOFSSEL signal (xSIG_VOFSSEL signal).

[0089] For example, when the SIG_VOFSSEL signal is at a high level, the switches 46a, 46c, 47a, 47c, 48a, and 48c are turned on, and the switches 46b, 46d, 47b, 47d, 48b, and 48d are turned off.

[0090] As a result, the output node of the first differential circuit 51 is connected to the input node of the first output circuit 53, and a second signal having a ramp waveform is output to the first output line RLa. Also, the output node of the first output circuit 53 is connected to the load circuit 41 and the current control circuit 33, and a second signal having a ramp waveform is output to the load circuit 41 and the current control circuit 33, just like the first output line RLa.

[0091] The output node of the second differential circuit 52 is connected to the input node of the second output circuit 54, and a second signal of an offset level is output to the second output line RLb. The output node of the second output circuit 54 is connected to the output node of the second differential circuit 52, and a second signal of an offset level is output to the second input node of the second differential circuit 52, similar to the second output line RLb.

[0092] When the SIG_VOFSSEL signal is at a low level, the switches 46a, 46c, 47a, 47c, 48a, and 48c are turned off, and the switches 46b, 46d, 47b, 47d, 48b, and 48d are turned on, thereby outputting the second signal of the offset level to the first output line RLa and outputting the second signal of the ramp waveform to the second output line RLb.

[0093] Regardless of the logic of the SIG_VOFSSEL signal, the second signal having a ramp waveform is output to the load circuit 41 and the current control circuit 33. Furthermore, regardless of the logic of the SIG_VOFSSEL signal, the second signal having an offset level is output to the second input node of the second differential circuit 52.

[0094] The current control circuit 33 controls the current generated by the signal generation circuit 31 based on the voltage difference between the second signal having a ramp waveform input from the output buffer 32 and the reference voltage VREF. The current control circuit 33 includes a comparator (differential amplifier) ​​35, a holding circuit 36, an SMPL switch 37, and a resistance element 38.

[0095] The comparator 35 has a first input node to which the reference voltage VREF is input and a second input node to which the second signal is input. The comparator 35 compares the second signal having a ramp waveform with the reference voltage VREF and outputs a comparison result signal. The comparison result signal of the comparator 35 is input to the variable current source 34. In other words, the comparator 35 controls the current flowing through the load circuit 41 in accordance with the second signal having a ramp waveform and the reference voltage VREF.

[0096] The holding circuit 36 ​​holds the comparison result signal output from the comparator 35. One end of the holding circuit 36 ​​is connected to the second input node of the comparator 35, and the other end is connected to the output node of the comparator 35. The holding circuit 36 ​​has, for example, a second capacitor 36a. The holding circuit 36 ​​may also have a configuration including a resistor element, a diode, or the like.

[0097] The SMPL switch 37 and the resistive element 38 are connected between the second input node of the comparator 35 and the output node of the output buffer 32. That is, the second signal is input to the second input node of the comparator 35 via the SMPL switch 37 and the resistive element 38.

[0098] 5 shows an example in which the resistive element 38 is arranged on the output node side of the output buffer 32, and the SMPL switch 37 is arranged on the second input node side of the comparator 35. However, the present invention is not limited to this, and the SMPL switch 37 may be arranged on the output node side of the output buffer 32, and the resistive element 38 may be arranged on the second input node side of the comparator 35.

[0099] The SMPL switch 37 is turned on or off based on the logic of the SMPL signal. The SMPL switch 37 is turned on for a predetermined period after the PWM signal transitions from high level to low level within one horizontal line period. When the SMPL switch 37 is turned on, the second signal output from the output buffer 32 is input to the comparator 35 via the SMPL switch 37. While the SMPL switch 37 is on, the comparator 35 compares the second signal with the reference voltage VREF and outputs a comparison result signal. While the SMPL switch 37 is off, the hold circuit 36 ​​continues to hold the comparison result signal output by the comparator 35 immediately before the SMPL switch 37 was turned on.

[0100] As a result, the signal generating circuit 31 controls the current flowing to the load circuit 41 in the output buffer 32 based on the comparison result signal held by the holding circuit 36. As described above, the current generated by the signal generating circuit 31 is supplied to the load circuit 41 only while the RAMPEN switch 43 is on.

[0101] 6 is an operation timing diagram of the display drive circuit 20 of FIG. 5. FIG. 6 illustrates two one-horizontal line periods. Of the two one-horizontal line periods, the first one-horizontal line period is a period during which the second signal of a ramp waveform is output to the first output line RLa. The first one-horizontal line period has periods T1 to T3. The second one-horizontal line period is a period during which the second signal of a ramp waveform is output to the second output line RLb. The second one-horizontal line period has periods T4 to T6.

[0102] During periods T1 to T3, the SIG_VOFSSEL signal goes high, connecting the output node of the first differential circuit 51 to the input node of the first output circuit 53. Also, connecting the output node of the first output circuit 53 to the load circuit 41 and the current control circuit 33.

[0103] During period T1, the PRCG signal goes high and the PRCG switch 44 turns on. This shorts both ends of the load circuit 41, i.e., the second input node of the first differential circuit 51 and the output node of the first output circuit 53. As the signal level of the third signal output by the first output circuit 53 increases, the ramp voltage of the first output line RLa rises to a first reference voltage (precharge voltage) VG0. The first reference voltage VG0 is, for example, a power supply voltage.

[0104] Thereafter, in period T2, the RAMPEN signal goes high and turns on the RAMPEN switch 43. As a result, current from the variable current source 34 flows to the load circuit 41 via the RAMPEN switch 43, and the signal level of the third signal of the first output circuit 53 and the voltage level of the first output line RLa decrease over time. While the RAMPEN switch 43 is on, the voltage level of the ramp voltage of the first output line RLa changes over time.

[0105] Thereafter, when the RAMPEN signal transitions from high to low, the period T2 ends and the period T3 begins. At this time, the RAMPEN switch 43 turns off, current stops flowing from the variable current source 34 to the load circuit 41, and the ramp voltage of the first output line RLa becomes a constant voltage level VG255.

[0106] During period T3, the SMPL signal temporarily transitions to a high level. As a result, the ramp voltage on the first output line RLa is supplied to the second input node of the comparator 35 in the current control circuit 33 via the SMPL switch 37. The comparator 35 outputs a comparison result signal between the ramp voltage and the reference voltage and stores the comparison result signal in the second capacitor 36a. The comparison result signal stored in the second capacitor 36a during period T3 is used to determine the current flowing from the variable current source 34 during the next horizontal line period.

[0107] As described above, the current control circuit 33 can control the current flowing from the variable current source 34 during the next horizontal line period based on the comparison result signal between the ramp voltage and the reference voltage. As a result, even if fluctuations in coupling capacitance occur between adjacent signal lines, the current flowing to the load circuit 41 can be adjusted in accordance with the fluctuations in the ramp voltage due to the coupling capacitance, thereby suppressing variations in the ramp voltage. This makes it possible to suppress variations in brightness within the pixel array unit 11, thereby improving the display quality of the display device 1.

[0108] During periods T1 to T3, the output node of the second differential circuit 52 is connected to the input node of the second output circuit 54, and the output node of the second output circuit 54 is connected to the second input node of the second differential circuit 52. As a result, the second output circuit 54 outputs an offset signal of a constant signal level, and the second output line RLb has a constant voltage level VOFS.

[0109] During periods T4 to T6, the SIG_VOFSSEL signal goes low. This connects the output node of the first differential circuit 51 to the input node of the second output circuit 54. The output node of the second output circuit 54 is also connected to the load circuit 41 and the current control circuit 33. The output node of the second differential circuit 52 is also connected to the input node of the first output circuit 53, and the output node of the first output circuit 53 is also connected to the second input node of the second differential circuit 52.

[0110] During periods T4 to T6, the ramp voltage of the second output line RLb changes in the same manner as the ramp voltage of the first output line RLa during periods T1 to T3. That is, during period T4, the PRCG signal goes high and the PRCG switch 44 turns on, causing the ramp voltage of the second output line RLb to rise to the first reference voltage VG0. During period T5, the RAMPEN signal goes high and the RAMPEN switch 43 turns on, causing the ramp voltage of the second output line RLb to change in voltage level over time. During period T6, the RAMPEN signal goes low and the RAMPEN switch 43 turns off, causing the ramp voltage of the second output line RLb to reach a constant voltage level VG255. During period T6, the SMPL signal temporarily transitions to high, causing the comparator 35 to output a comparison result signal between the ramp voltage of the second output line RLb and the reference voltage, and the comparison result signal is stored in the second capacitor 36a. On the other hand, during the period T4 to T6, the first output line RLa is at a constant voltage level VOFS.

[0111] After the period T6, the operations of the periods T1 to T6 are repeated in the same manner.

[0112] 6, the first output circuit 53 and the second output circuit 54 alternately select the third signal or the offset signal to output the second signal. The second signal alternates between a first period in which the voltage level may change depending on time and is generated based on the third signal, and a second period in which the voltage level is fixed and is generated based on the offset signal.

[0113] 6, periods T1 to T3 are the first period for the first output circuit 53 and the second period for the second output circuit 54. Furthermore, periods T4 to T6 are the second period for the first output circuit 53 and the first period for the second output circuit 54. That is, while the first output circuit 53 outputs the second signal for the first period, the second output circuit 54 outputs the second signal for the second period, and while the first output circuit 53 outputs the second signal for the second period, the second output circuit 54 outputs the second signal for the first period. The first period and the second period alternate every horizontal line period.

[0114] The driving method of FIG. 6 is also referred to as 2SIG driving in this specification, since the first output line RLa and the second output line RLb are driven simultaneously.

[0115] 7 is a circuit diagram of the output buffer 32 according to the first embodiment of the present disclosure. The first differential circuit 51 includes a current source 60a and transistors 61a, 62a, 63a, 64a, 65a, 66a, 67a, 68a, 69a, and 70a. The first output circuit 53 includes transistors 71a, 72a, 73a, and 74a. The transistors 61a, 62a, 67a, 68a, 69a, 70a, 72a, and 74a are, for example, nMOS (n-channel metal-oxide-semiconductor) transistors. The transistors 63a, 64a, 65a, 66a, 71a, and 73a are, for example, pMOS (p-channel metal-oxide-semiconductor) transistors.

[0116] The gate of the transistor 61a is a first input node to which a first reference voltage VG0 is input. The gate of the transistor 62a is a second input node to which a feedback voltage VFB_A is input. The sources of the transistors 61a and 62a are connected to one end of the current source 60a. The other end of the current source 60a is, for example, grounded. In this specification, the current source 60a and the transistors 61a and 62a are also referred to as a differential circuit main part 75a.

[0117] The sources of the transistors 63a, 64a, 65a, and 66a are connected to, for example, a power supply voltage node. The gate and drain of the transistor 63a are short-circuited and connected to the drain of the transistor 61a. The gate and drain of the transistor 64a are short-circuited and connected to the drain of the transistor 62a. The gate of the transistor 65a is connected to the drain of the transistor 61a. The gate of the transistor 66a is connected to the drain of the transistor 62a. The drain of the transistor 66a is connected to the first output node of the first differential circuit 51.

[0118] The transistors 67a, 68a, 69a, and 70a form a cascode current mirror circuit. The drain of the transistor 67a is connected to the drain of the transistor 65a and to the gates of the transistors 69a and 70a. The gate of the transistor 67a is connected to the gate of the transistor 68a. The source of the transistor 67a is connected to the drain of the transistor 69a. The source of the transistor 68a is connected to the drain of the transistor 70a. The drain of the transistor 68a is connected to the second output node of the first differential circuit 51. The sources of the transistors 69a and 70a are, for example, grounded.

[0119] A first output node of the first differential circuit 51 is connected to a first input node of the first output circuit 53 when the switch 47a is on, and is connected to a first input node of the second output circuit 54 when the switch 47b is on. A second output node of the first differential circuit 51 is connected to a second input node of the first output circuit 53 when the switch 47c is on, and is connected to a second input node of the second output circuit 54 when the switch 47d is on.

[0120] The source of the transistor 71a, the drain of the transistor 72a, and the gate of the transistor 73a are connected to a first input node of the first output circuit 53. The drain of the transistor 71a, the source of the transistor 72a, and the gate of the transistor 74a are connected to a second input node of the first output circuit 53.

[0121] A predetermined bias voltage is applied to the gates of the transistors 71a and 72a, respectively. In this specification, the transistors 71a and 72a are also referred to as a class AB bias circuit 76a.

[0122] The transistors 73a and 74a are cascode-connected. The source of the transistor 73a is connected to, for example, a power supply voltage node. The source of the transistor 74a is connected to, for example, ground. The drains of the transistors 73a and 74a are connected to the output node of the first output circuit 53. In this specification, the transistors 73a and 74a are also referred to as an output circuit main portion 77a.

[0123] The second differential circuit 52 includes a current source 60b and transistors 61b, 62b, 63b, 64b, 65b, 66b, 67b, 68b, 69b, and 70b. The gate of the transistor 61b serves as a first input node to which a second reference voltage VOFS is input. The gate of the transistor 62b serves as a second input node to which a feedback voltage VFB_B is input. The second differential circuit 52 also includes a differential circuit main section 75b. The circuit configuration of the second differential circuit 52 is similar to that of the first differential circuit 51.

[0124] The second output circuit 54 has transistors 71b, 72b, 73b, and 74b. The second output circuit 54 also has a class AB bias circuit 76b and an output circuit main section 77b. The circuit configuration of the second output circuit 54 is similar to that of the first output circuit 53.

[0125] The lamp driving circuit 21 according to the first embodiment of the present disclosure realizes the function of outputting a ramp voltage using a differential circuit 42 and an output circuit 45. Furthermore, switching circuits (i.e., a second switching circuit 47 and a third switching circuit 48) are provided between the differential circuit 42 and the output circuit 45, and these switching circuits switch the connection between the first differential circuit 51 and the second differential circuit 52 that constitute the differential circuit 42 and the first output circuit 53 and the second output circuit 54 that constitute the output circuit 45. This allows the number of capacitors in the output buffer 32 to be reduced, thereby reducing the circuit size. Furthermore, there is no need to provide a switch between the output line (ramp wiring) connected to the output node of the output buffer 32 and the signal line voltage generation circuit 22, thereby shortening the settling time of the output line.

[0126] The features of the first embodiment of the present disclosure will be described below in comparison with other circuit configurations.

[0127] Fig. 8 is a block diagram showing the configuration of a lamp drive circuit 901 (and a display drive circuit 900) according to a first comparative example. The lamp drive circuit 901 in Fig. 8 differs from the lamp drive circuit 21 in Fig. 5 in that it does not have the first differential circuit 51, the second differential circuit 52, the first output circuit 53, the second output circuit 54, the first switching circuit 46, the second switching circuit 47, and the third switching circuit 48.

[0128] The lamp driving circuit 901 of FIG. 8 includes an output buffer 902a that applies a ramp voltage and an offset voltage to the first output line RLa, and an output buffer 902b that applies a ramp voltage and an offset voltage to the second output line RLb.

[0129] The output buffer 902a includes an amplifier 903a, a load circuit 904a, and a PRCG switch 905a. The output buffer 902b includes an amplifier 903b, a load circuit 904b, and a PRCG switch 905b.

[0130] 5 , the amplifier 903a outputs a ramp voltage during the first period and outputs an offset voltage during the second period. A first reference voltage VG0 is applied to a first input node of the amplifier 903a during the first period, and a second reference voltage VOFS is applied to a second input node of the amplifier 903a. A feedback voltage is applied from the load circuit 904a to a second input node of the amplifier 903a. The amplifier 903a compares the voltage applied to the first input node with the voltage applied to the second input node, and outputs a comparison result signal.

[0131] The load circuit 904a is disposed on the feedback path of the amplifier 903a. More specifically, the load circuit 904a is connected between the second input node and the output node. The load circuit 904a has a capacitor. The PRCG switch 905a is connected in parallel to the load circuit 904a. The PRCG switch 905a is turned on during a predetermined period immediately after the start of one horizontal line period (more specifically, during a period corresponding to period T1 in FIG. 6 ), and shorts both ends of the load circuit 904a, i.e., the second input node and the output node of the amplifier 903a.

[0132] The circuit configuration of the output buffer 902b is the same as that of the output buffer 902a. The output buffers 902a and 902b alternate between a first period and a second period every horizontal line period, similar to the first output circuit 53 and the second output circuit 54 in Fig. 5. When one of the output buffers 902a and 902b is in the first period in which it outputs a ramp voltage, the other is in the second period in which it outputs an offset voltage.

[0133] The lamp driving circuit 901 in FIG. 8 includes a RAMPEN switching unit 906. The RAMPEN switching unit 906 includes RAMPEN switches 906a and 906b. The RAMPEN switch 906a switches whether or not the output buffer 902a and the variable current source 34 are connected. The RAMPEN switch 906a is turned on during a portion of the first period of the output buffer 902a (more specifically, during a period corresponding to period T2 in FIG. 6). This causes a current from the variable current source 34 to flow through the load circuit 904a, causing the feedback voltage input to the second input node of the amplifier 903a to decrease over time, enabling the amplifier 903a to output a ramp voltage.

[0134] The lamp driving circuit 901 in FIG. 8 includes an SMPL switching unit 907. The SMPL switching unit 907 includes SMPL switches 907a and 907b. The SMPL switch 907a switches whether or not the output buffer 902a is connected to the comparator 35. The SMPL switch 907a is temporarily turned on before the first period of the output buffer 902a ends (specifically, during the period corresponding to period T3 in FIG. 6). This causes the comparator 35 to output a comparison result signal between the ramp voltage and the reference voltage and store the comparison result signal in the holding circuit 36.

[0135] The RAMPEN switch 906b switches whether the output buffer 902b is connected to the variable current source 34. The SMPL switch 907b switches whether the output buffer 902b is connected to the comparator 35. The operations of the RAMPEN switch 906b and the SMPL switch 907b are similar to those of the RAMPEN switch 906a and the SMPL switch 907a.

[0136] As described above, amplifier 903a outputs a ramp voltage during the first period and an offset voltage during the second period. Amplifier 903b operates in the same manner as amplifier 903a. That is, the configuration of lamp driving circuit 901 in FIG. 8 can also perform driving in the same manner as lamp driving circuit 21 in FIG. 5.

[0137] However, there are several problems with the configuration of the lamp driving circuit 901 in Figure 8. The first problem is that the lamp driving circuit 901 requires at least three capacitors. Specifically, the lamp driving circuit 901 requires a capacitor for the load circuit 904a in the output buffer 902a, a capacitor for the load circuit 904b in the output buffer 902b, and a second capacitor 36a in the current control circuit 33. This increases the circuit area.

[0138] The second problem is that the voltages applied to the first input nodes of the amplifiers 903a and 903b must be switched between the first reference voltage VG0 and the second reference voltage VOFS for each horizontal line period during the operation of the lamp driving circuit 901. When switching the first input nodes between the first reference voltage VG0 and the second reference voltage VOFS, the gamma voltage corresponding to the ramp voltage output from the lamp driving circuit 901 fluctuates, which may cause deviations in the write voltages of the signal lines.

[0139] A third problem is errors caused by parasitic capacitance. In the lamp driving circuit 901, parasitic capacitances 908a, 908b, and 908c may be formed between the second input node of the amplifier 903a, the second input node of the amplifier 903b, and the second input node of the comparator 35 and a reference voltage node (e.g., a ground node), respectively. The parasitic capacitances 908a, 908b, and 908c cause errors in the output signals of the amplifier 903a, the amplifier 903b, and the comparator 35, respectively. In particular, if there is a capacitance difference between the parasitic capacitances 908a and 908b, different errors will occur in the output signals of the amplifiers 903a and 903b, causing a difference in the write voltages to the first output line RLa and the second output line RLb, deteriorating the write voltage characteristics.

[0140] Compared to the lamp driving circuit 901 of Fig. 8, the lamp driving circuit 21 of Fig. 5 requires only two capacitors, the first capacitor 41a and the second capacitor 36a. That is, the lamp driving circuit 21 of Fig. 5 can eliminate one capacitor from the lamp driving circuit 901 of Fig. 8, thereby reducing the circuit area.

[0141] 5, the voltage applied to the first input node of the first differential circuit 51 can be fixed to the first reference voltage VG0, and the voltage applied to the first input node of the second differential circuit 52 can be fixed to the second reference voltage VOFS. This eliminates the need to switch the voltages at the first input nodes of the first differential circuit 51 and the second differential circuit 52, and makes it possible to suppress fluctuations in the gamma voltage and the write voltage of the signal line.

[0142] Furthermore, by reducing the number of capacitors, the influence of parasitic capacitance is reduced, and fluctuations in the ramp voltage can be suppressed.

[0143] Fig. 9 is a block diagram showing the configuration of a lamp drive circuit 911 (and a display drive circuit 910) according to a second comparative example. Similar to the lamp drive circuit 901 in Fig. 8, the lamp drive circuit 911 in Fig. 9 does not have the first differential circuit 51, the second differential circuit 52, the first output circuit 53, the second output circuit 54, the first switching circuit 46, the second switching circuit 47, and the third switching circuit 48.

[0144] The lamp driving circuit 911 in FIG. 9 includes an output buffer 912a that outputs a ramp voltage, an output buffer 912b that outputs an offset voltage, a switching unit 914 that switches whether the output buffer 912a is connected to the first output line RLa or the second output line RLb, and a switching unit 915 that switches whether the output buffer 912b is connected to the first output line RLa or the second output line RLb.

[0145] The output buffer 912a includes an amplifier 913a, a load circuit 41, a RAMPEN switch 43, and a PRCG switch 44. The amplifier 913a has a first input node to which a first reference voltage VG0 is input and a second input node to which a feedback voltage is input. The output node of the amplifier 913a is connected to the switching unit 914 and the SMPL switch 37.

[0146] The load circuit 41 is connected between the second input node and the output node of the amplifier 913a. The PRCG switch 44 is connected in parallel with the load circuit 41. The RAMPEN switch 43 switches whether or not the amplifier 913a and the load circuit 41 are connected to the variable current source 34. The operations of the load circuit 41, the RAMPEN switch 43, and the PRCG switch 44 are the same as those in FIG. 5 .

[0147] The output buffer 912b includes an amplifier 913b. The amplifier 913b has a first input node to which the second reference voltage VOFS is input and a second input node to which the feedback voltage is input. The output node of the amplifier 913b is short-circuited to the second input node and is connected to the switching unit 915.

[0148] The switching unit 914 has a switch 914a that switches whether the output buffer 912a and the first output line RLa are connected or not, and a switch 914b that switches whether the output buffer 912a and the second output line RLb are connected or not. The switching unit 915 has a switch 915a that switches whether the output buffer 912b and the first output line RLa are connected or not, and a switch 915b that switches whether the output buffer 912b and the second output line RLb are connected or not.

[0149] When the switches 914a and 915b are turned on and the switches 914b and 915a are turned off, a ramp voltage is output to the first output line RLa and an offset voltage is output to the second output line RLb. When the switches 914b and 915a are turned on and the switches 914a and 915b are turned off, an offset voltage is output to the first output line RLa and a ramp voltage is output to the second output line RLb. In other words, the configuration of the lamp driving circuit 911 in Figure 9 allows for driving in the same way as the lamp driving circuit 21 in Figure 5.

[0150] However, the lamp driving circuit 911 in Figure 9 requires switching units 914 and 915 between the output nodes of the amplifiers 913a and 913b and the output line RL. The locations where the switching units 914 and 915 are located are locations where the driving current of the pixel loads is concentrated. For this reason, switches with low on-resistance and large area must be used for the switching units 914 and 915, which increases the circuit area. Furthermore, the on-resistance of the switching units 914 and 915 may lengthen the settling time.

[0151] In contrast, the lamp driving circuit 21 of Fig. 5 is characterized in that the output signals to the first output line RLa and the second output line RLb are switched by the second switching circuit 47 and the third switching circuit 48 arranged between the differential circuit 42 and the output circuit 45. The amount of current between the differential circuit 42 and the output circuit 45 is relatively small compared to the amount of current between the output node of the output circuit 45 and the output line RL. Therefore, the second switching circuit 47 and the third switching circuit 48 can reduce the switch area, thereby reducing the circuit area. Furthermore, the second switching circuit 47 and the third switching circuit 48 can shorten the settling time.

[0152] There are several possible modifications to the locations of the second switching circuit 47 and the third switching circuit 48. Fig. 10A is a circuit diagram of an output buffer 32a according to a first modification of Fig. 7. The output buffer 32a in Fig. 10A is characterized in that the second switching circuit 47 and the third switching circuit 48 are disposed in front of the class AB bias circuits 76a and 76b and in the current mirror circuit.

[0153] Specifically, one end of switch 47a in second switching circuit 47 is connected to the gate of transistor 64a, and the other end is connected to the gate of transistor 66a. One end of switch 47b is connected to the gate of transistor 64a, and the other end is connected to the gate of transistor 66b. One end of switch 47c is connected to the gate of transistor 67a, and the other end is connected to the gate of transistor 68a. One end of switch 47d is connected to the gate of transistor 67a, and the other end is connected to the gate of transistor 68b.

[0154] 10A does not have transistors 69a and 70a, and transistors 67a and 68a form a current mirror circuit. The gate and drain of the transistor 67a are connected to each other. The sources of the transistors 67a and 68a are, for example, grounded.

[0155] The transistors 66a and 68a are also arranged in the first output circuit 53. The drain of the transistor 66a is connected to the gate of the transistor 73a. The drain of the transistor 68a is connected to the gate of the transistor 74a.

[0156] The second differential circuit 52, the third switching circuit 48, and the second output circuit 54 in Fig. 10A have the same circuit configurations as the first differential circuit 51, the second switching circuit 47, and the first output circuit 53 in Fig. 10A, respectively. The same applies to Figs. 10B to 10D described below.

[0157] Fig. 10B is a circuit diagram of an output buffer 32b according to a second modification of Fig. 7. The output buffer 32b in Fig. 10B is characterized in that the second switching circuit 47 and the third switching circuit 48 are connected to the differential circuit main parts 75a and 75b.

[0158] Specifically, one end of the switch 47a in the second switching circuit 47 is connected to the drain of the transistor 61a and the other end is connected to the gate of the transistor 66a. One end of the switch 47b is connected to the drain of the transistor 61a and the other end is connected to the gate of the transistor 66b. One end of the switch 47c is connected to the drain of the transistor 62a and the other end is connected to the gate of the transistor 65a. One end of the switch 47d is connected to the drain of the transistor 62a and the other end is connected to the gate of the transistor 65b.

[0159] The output buffer 32a in Fig. 10B does not have transistors 69a and 70a, and similarly to Fig. 10A, transistors 67a and 68a form a current mirror circuit. Also, transistors 63a, 64a, 65a, 66a, 67a, and 68a are arranged in the first output circuit 53. The gate and drain of transistor 63a are connected to the gate of transistor 66a. The gate and drain of transistor 64a are connected to the gate of transistor 65a.

[0160] 10C is a circuit diagram of an output buffer 32c according to a third modification of FIG. 7. The output buffer 32c of FIG. 10C differs from the output buffer 32b of FIG. 10B in that transistors 63a and 64a are arranged within the first differential circuit 51. The gate and drain of the transistor 63a are connected to the drain of the transistor 61a. The gate and drain of the transistor 64a are connected to the drain of the transistor 62a.

[0161] Fig. 10D is a circuit diagram of an output buffer 32d according to a fourth modification of Fig. 7. The output buffer 32d in Fig. 10D is characterized in that a second switching circuit 47 and a third switching circuit 48 are arranged in the subsequent stages of the class AB bias circuits 76a and 76b.

[0162] Specifically, one end of switch 47a in second switching circuit 47 is connected to the drain of transistor 66a and the other end is connected to the gate of transistor 73a. One end of switch 47b is connected to the drain of transistor 66a and the other end is connected to the gate of transistor 73b. One end of switch 47c is connected to the drain of transistor 68a and the other end is connected to the gate of transistor 74a. One end of switch 47d is connected to the drain of transistor 68a and the other end is connected to the gate of transistor 74b.

[0163] The transistors 71a and 72a are arranged in the first differential circuit 51. The source of the transistor 71a and the drain of the transistor 72a are connected to the drain of the transistor 66a. The drain of the transistor 71a and the source of the transistor 72a are connected to the drain of the transistor 68a.

[0164] As described above, the display drive circuit 20 according to the first embodiment of the present disclosure has an output buffer 32 connected to an output line (lamp wiring) configured in two stages, that is, a differential circuit 42 and an output circuit 45, and is provided with a second switching circuit 47 and a third switching circuit 48 that switch the connection between the first and second differential circuits 51, 52 that configure the differential circuit 42 and the first and second output circuits 53, 54 that configure the output circuit 45. This allows the number of capacitors in the output buffer 32 to be reduced, thereby enabling the circuit area to be smaller than that of the display drive circuit 900 in FIG. 8 .

[0165] Furthermore, it is no longer necessary to connect a switching circuit between the output line connected to the output node of the output buffer 32 and the signal line voltage generation circuit 22, thereby shortening the settling time of the ramp voltage on the output line. Furthermore, compared to the display drive circuit 900 of Fig. 8 , the display drive circuit 20 according to the present disclosure does not need to switch the voltage applied to the input node of the output circuit 45 between the first reference voltage VG0 and the second reference voltage VOFS, and can suppress errors between the gamma voltage and the write voltage of the signal line caused by switching the input node to the first reference voltage VG0 or the second reference voltage VOFS.

[0166] Furthermore, the display drive circuit 20 according to the present disclosure can reduce the number of capacitors compared to the display drive circuit 900 in Fig. 8, thereby suppressing errors in the ramp voltage caused by parasitic capacitance formed around the capacitors. In particular, it is possible to prevent deviations in the write voltages of the first output line RLa and the second output line RLb caused by differences in the parasitic capacitance.

[0167] Furthermore, the display drive circuit 20 according to the present disclosure can reduce the circuit area of ​​the switch and shorten the settling time of the switch compared to the display drive circuit 910 .

[0168] That is, the display driver circuit 20 according to the present disclosure can improve the write voltage characteristics when switching the operating state of the pixel.

[0169] (Second embodiment) In the first embodiment, two output lines (ramp wiring) are connected to the output buffer 32 to perform 2SIG drive, whereas in the second embodiment, one output line (ramp wiring) is connected to the output buffer 32 to perform 1SIG drive.

[0170] Fig. 11 is a block diagram showing the configuration of a main part of a display drive circuit 80 according to a second embodiment of the present disclosure. The display drive circuit 80 of Fig. 11 differs from the display drive circuit 20 of Fig. 5 in that it does not have the second output circuit 54 and the third switching circuit 48 in the output buffer 32e.

[0171] 11 drives one output line RL (i.e., the first output line RLa) by one first output circuit 53. In this specification, the driving method of the display drive circuit 80 is referred to as 1SIG driving, as described above.

[0172] 11 switches whether the second signal output from the first output circuit 53 is input to the comparator 35 or the second differential circuit 52. The first switching circuit 81 includes, for example, switches 81a and 81b.

[0173] For example, when the SIG_VOFSSEL signal is at a high level, the switch 81a is turned on. When the switch 81a is turned on, the first switching circuit 81 connects the output node of the first output circuit 53 to the second input node of the second differential circuit 52 and inputs the second signal to the second differential circuit 52. When the SIG_VOFSSEL signal is at a low level, the switch 81b is turned on. When the switch 81b is turned on, the first switching circuit 81 connects the output node of the first output circuit 53 to the load circuit 41 and the current control circuit 33 and inputs the second signal to the comparator 35.

[0174] 11 switches between connecting the input node of the first output circuit 53 to the output node of the first differential circuit 51 and connecting the input node of the second differential circuit 52. The second switching circuit 82 includes, for example, switches 82a, 82b, 82c, and 82d.

[0175] For example, when the SIG_VOFSSEL signal is at a high level, the switches 82a and 82c are turned on. When the switches 82a and 82c are turned on, the second switching circuit 82 connects the input node of the first output circuit 53 to the output node of the second differential circuit 52. When the SIG_VOFSSEL signal is at a low level, the switches 82b and 82d are turned on. When the switches 82b and 82d are turned on, the second switching circuit 82 connects the input node of the first output circuit 53 to the output node of the first differential circuit 51.

[0176] Fig. 12 is an operation timing diagram of the display drive circuit 80 of Fig. 11. One horizontal line period is illustrated in Fig. 12. The one horizontal line period of Fig. 12 has periods T11 to T14.

[0177] During period T11, the SIG_VOFSSEL signal goes high. This connects the output node of the second differential circuit 52 and the input node of the first output circuit 53. Furthermore, the second signal output by the first output circuit 53 is input to the second input node of the second differential circuit 52. This causes the first output circuit 53 to output an offset signal with a constant signal level, and the first output line RLa goes to a constant voltage level VOFS. In other words, period T11 corresponds to the second period during which the voltage level of the first output line RLa is fixed.

[0178] During periods T12 to T14, the SIG_VOFSSEL signal is at a low level. This connects the output node of the first differential circuit 51 to the input node of the first output circuit 53. Furthermore, the output node of the first output circuit 53 is connected to the load circuit 41 and the current control circuit 33. The operation of the first output circuit 53 during periods T12 to T14 is the same as the operation of the first output circuit 53 during periods T1 to T3 in FIG. 6. In other words, the period T12 to T14 corresponds to a first period during which a ramp voltage whose voltage level changes over time is applied to the first output line RLa.

[0179] As shown in FIG. 12, the first output circuit 53 alternately outputs the second signal of the first period or the second period to the first output line RLa within one horizontal line period.

[0180] 5 is applicable not only to the 2SIG drive display drive circuit 20 but also to the 1SIG drive display drive circuit 80. In the 1SIG drive display drive circuit 80, the circuit area can be reduced compared to the display drive circuits 900 and 910 in FIGS. 8 and 9, and the write accuracy resulting from the transition of the differential stage input waveform and the settling characteristics can be improved.

[0181] Third Embodiment In the first and second embodiments, an example has been described in which a ramp voltage is output from the output buffer 32, but a signal voltage corresponding to a pixel signal may be output from the output buffer 32. The role of the signal line voltage generation circuit 22 a connected to an output line connected to the output buffer 32 according to the third embodiment is different from that of the signal line voltage generation circuit 22 in the first and second embodiments.

[0182] 13 is a block diagram showing the configuration of a main part of a display drive circuit 80a according to a third embodiment of the present disclosure. The display drive circuit 80a in FIG. 13 includes a signal generation circuit 91 in a drive circuit 90 that generates a first signal VSIG having a signal level corresponding to a pixel signal.

[0183] The signal generating circuit 91 is, for example, a DAC. In particular, Fig. 13 illustrates an example in which the signal generating circuit 91 is an RDAC (Resistor-string DAC).

[0184] The signal generation circuit 91 receives, for example, a first reference voltage VG0, a third reference voltage VG255, and a data signal DATA. The data signal DATA is, for example, a digital signal having a bit value corresponding to the signal level of the pixel signal. The voltage level of the first signal VSIG output by the signal generation circuit 91 changes between the first reference voltage VG0 and the third reference voltage VG255 based on the data signal DATA.

[0185] The drive circuit 90 includes an output buffer 32f. The output buffer 32f has a configuration compatible with 1SIG drive, similar to the output buffer 32e of FIG. 11. Specifically, the output buffer 32f includes a first differential circuit 51, a second differential circuit 52, a first output circuit 53, a first switching circuit 81, and a second switching circuit 82. Note that the output buffer 32f can also be configured to support 2SIG drive, similar to the output buffer 32 of FIG. 5.

[0186] 11 in that it does not have a load circuit 41, a RAMPEN switch 43, or a PRCG switch 44. A switch 81a in a first switching circuit 81 switches whether to connect the output node of the first output circuit 53 to the second input node of the second differential circuit 52. A switch 81b switches whether to connect the output node of the first output circuit 53 to the second input node of the first differential circuit 51.

[0187] A first signal VSIG corresponding to the pixel signal is applied from the signal generating circuit 91 to a first input node of the first differential circuit 51. When the switches 82b, 82d, and 81b are on, a second signal VFB_A output by the first output circuit 53 is input to a second input node of the first differential circuit 51. The first differential circuit 51 outputs a third signal corresponding to the signal difference between the first signal VSIG and the second signal VFB_A.

[0188] A second reference voltage VOFS is applied to a first input node of the second differential circuit 52. A second input node of the second differential circuit 52 receives the second signal VFB_B output by the first output circuit 53 when the switches 82a, 82c, and 81a are on.

[0189] 11 in that the driving circuit 90 does not have a current control circuit 33. In addition, the driving circuit 90 differs from the lamp driving circuit 21 of FIG.

[0190] 13 includes a signal line voltage generation circuit 22b. The signal line voltage generation circuit 22b holds the signal level of the second signal output from the output buffer 32f in synchronization with the timing at which the voltage level of the second signal changes, and generates a signal line voltage for the signal line SIGn.

[0191] The display drive circuit 80a has a plurality of SEL switches 23b connected to a plurality of signal lines SIGn. One end of each SEL switch 23b is connected to a corresponding signal line SIGn, and the other end of each SEL switch 23b is connected to an output line RL. Each SEL switch 23b is turned on when the corresponding SEL signal is at a high level, and turned off when the corresponding SEL signal is at a low level.

[0192] Fig. 14 is an operation timing diagram of the display drive circuit 80a of Fig. 13. One horizontal line period is illustrated in Fig. 14. The one horizontal line period of Fig. 14 has periods T21 and T22.

[0193] During period T21, the SIG_VOFSSEL signal is at a high level. This connects the output node of the second differential circuit 52 and the input node of the first output circuit 53. The first output circuit 53 outputs an offset signal with a constant signal level, causing the first output line RLa to have a constant voltage level VOFS. Period T21 corresponds to a second period during which the voltage level of the first output line RLa is fixed.

[0194] The SEL signals go high at the start of the period T21 and go low at the end of the period T21, so that the SEL switches 23b in the signal line voltage generating circuit 22a are turned on during the period T21, and the voltage VOFS of the first output line RLa is held on the signal lines SIGn.

[0195] During a period T22, the SIG_VOFSSEL signal is at a low level, thereby connecting the output node of the first differential circuit 51 and the input node of the first output circuit 53. As a result, the second signal output by the first output circuit 53 has a voltage level corresponding to the first signal VSIG output by the signal generation circuit 91.

[0196] The signal generation circuit 91 changes the voltage level of the first signal VSIG at a predetermined timing. In response, the voltage level of the second signal output to the first output line RLa changes. The multiple SEL signals sequentially go high in synchronization with the timing at which the voltage level of the second signal changes. The SEL signal that has gone high goes low in synchronization with the timing at which the voltage level of the second signal next changes. As a result, each SEL switch 23b in the signal line voltage generation circuit 22a turns on at the timing at which the voltage level of the second signal changes, and the voltage level of the second signal at that timing is held on each of the multiple signal lines SIGn. Period T22 is a first period during which the voltage level of the first output line RLa changes at a predetermined timing.

[0197] In this specification, the driving method of FIG. 14 is also called a voltage follower method.

[0198] As described above, in the display drive circuit 80a according to the third embodiment, when a voltage follower system is adopted to drive the output line RL, the output buffer 32f connected to the output line RL has a two-stage configuration consisting of a differential circuit 42 and an output circuit 45, and the connection between the first and second differential circuits 51, 52 constituting the differential circuit 42 and the output circuit 45 is switched by a second switching circuit 82. This allows the number of capacitors to be reduced, as in the first and second embodiments, and the circuit size to be reduced. Furthermore, since there is no need to connect a switching circuit between the output line RL and the signal line voltage generation circuit 22a, the settling time of the signal voltage on the output line RL can be shortened.

[0199] In a fourth embodiment, an output buffer generates a signal voltage using, for example, an R2RDAC. The R2RDAC has a resistor ladder circuit that uses a plurality of resistors of two types each having a double resistance value to generate a signal voltage according to a pixel signal.

[0200] Fig. 15 is a block diagram showing the configuration of a main part of a display drive circuit 80b according to a fourth embodiment of the present disclosure. A signal generation circuit 91 in Fig. 15 has a resistor ladder circuit 92. The signal generation circuit 91 in Fig. 15 is, for example, an R2RDAC (R-2R Ladder DAC). Note that the signal generation circuit 91 may also be a binary weighted DAC, which will be described later.

[0201] The drive circuit 90 of Fig. 15 includes an output buffer 32g. The output buffer 32g of Fig. 15 has a configuration similar to that of the output buffer 32e of Fig. 11. A load circuit 41 in the output buffer 32g includes, for example, a resistor 41b. A first reference voltage VG0 is applied to a first input node of a first differential circuit 51. A first signal VSIG is applied to a second input node of the first differential circuit 51. The first signal VSIG has a signal level that corresponds to the resistance ratio between the resistor in the resistor ladder circuit 92 and the resistor 41b in the load circuit 41.

[0202] The display drive circuit 80b in Fig. 15 has a configuration compatible with 1SIG drive, but may have a configuration compatible with 2SIG drive, similar to the display drive circuit 80a in Fig. 13. The drive method of the display drive circuit 80b in Fig. 15 is the same as the drive method in Fig. 14.

[0203] 16A to 16C are block diagrams respectively showing first to third configuration examples of the resistor ladder circuit 92. The resistor ladder circuit 92a shown in Fig. 16A includes a resistor 93a, a plurality of resistors 93b, a plurality of resistors 93c, and a plurality of selectors 94.

[0204] The resistor ladder circuit 92a has a first input node to which a first reference voltage VG0 is input and a second input node to which a third reference voltage VG255 is input. One end of a resistor 93a is connected to the first input node. A plurality of resistors 93b are connected in series to the other end of the resistor 93a. The resistor 93a is also connected to the second input node via the plurality of resistors 93b. One end of a resistor 93c is connected between the resistors 93a and 93b, between the stages of the plurality of resistors 93b, and between the resistor 93b and the second input node. A selector 94 is connected to the other end of each of the plurality of resistors 93c.

[0205] Voltages b0 to b(n-1) corresponding to the corresponding bit values ​​of the data signal DATA corresponding to the pixel signal are input to the selectors 94. Based on the corresponding voltages b0 to b(n-1), the selectors 94 switch between connecting the resistor 93c to the first input node or connecting it to the output node of the resistor ladder circuit 92a.

[0206] The multiple resistors 93b have the same unit resistance value R. The resistor 93a and the multiple resistors 93c have a resistance value 2R that is twice the unit resistance value R. In other words, the resistor ladder circuit 92a has an R-2R ladder structure that is composed of the resistor 93b with a resistance value R and the resistors 93a and 93c with a resistance value 2R.

[0207] The plurality of selectors 94 connect the resistor 93c to the output node of the resistor ladder circuit 92a when the corresponding voltages b0 to b(n-1) are at a high level, thereby outputting a voltage signal having a voltage level corresponding to the resistance value of the resistor 93c or a voltage level corresponding to the combined resistance value of the resistor 93c and one or more resistors 93b arranged between the resistor 93c and the second input node.

[0208] That is, the selectors 94 select whether or not to output the voltage signals having different voltage levels to the output nodes, respectively. The resistor ladder circuit 92a combines the selected voltage signals to generate the first signal.

[0209] Resistor ladder circuit 92b shown in FIG. 16B differs from resistor ladder circuit 92a shown in FIG. 16A in that a current source 95 is connected to the second input node.

[0210] The resistor ladder circuits 92a and 92b shown in Figures 16A and 16B constitute an R2R DAC. In contrast, the resistor ladder circuit 92c shown in Figure 16C constitutes a binary weighted DAC. The resistor ladder circuit 92c in Figure 16C includes multiple resistors 93d and multiple selectors 94.

[0211] One ends of the plurality of resistors 93d are connected in parallel to the output node of the resistor ladder circuit 92c. The other ends of the plurality of resistors 93d are connected to the selector 94. The plurality of selectors 94 switch, based on the corresponding voltages b0 to b(n-1), whether the resistor 93d is connected to a first input node to which the first reference voltage VG0 is input or to a second input node to which the third reference voltage VG255 is input.

[0212] The plurality of resistors 93d have resistance values ​​that are powers of 2 of the unit resistance value R that are different from one another.

[0213] Similar to the resistor ladder circuit 92a in FIG. 16A, the resistor ladder circuit 92c in FIG. 16C combines voltage signals selected by a plurality of selectors 94 to generate a first signal.

[0214] As described above, the display drive circuit according to the fourth embodiment includes a resistor ladder circuit such as an R2RDAC and a Binary Weighted DAC, and an output buffer 32g. However, by configuring the output buffer 32g in the same manner as the output buffer 32f in FIG. 13, the same effects as those of the third embodiment can be obtained.

[0215] Fifth Embodiment The lamp drive circuits, output lines (lamp wiring), and signal lines shown in the first and second embodiments can be connected in various ways. Representative connection forms will be described below in order.

[0216] 17A is a diagram showing a connection configuration of a lamp drive circuit, output lines (lamp wiring), and signal lines in a display drive circuit 20 according to the fifth embodiment. In Fig. 17A, the lamp drive circuit 21 including the signal generation circuit 31, output buffer 32, and current control circuit 33 shown in the first and second embodiments is arranged at an end of the pixel array section 11 in the horizontal direction X. This allows the lamp drive circuit 21 to be arranged without affecting the display of the pixels 30.

[0217] 17A shows an example in which a pixel 30 is composed of three sub-pixels 30r, 30g, and 30b of red, green, and blue. Sub-pixels of the same color are arranged in the vertical direction Y of the pixel array unit 11, and a signal line is arranged for each column of sub-pixels arranged in the vertical direction Y. One end of each signal line is connected to a lamp wiring (output line RL) via a corresponding PWM switch.

[0218] 17B is a diagram showing a connection configuration of the lamp drive circuit, output lines (lamp wiring), and signal lines according to a first modification of the fifth embodiment. In FIG. 17B, the lamp drive circuits 21 are arranged on both sides of the pixel array unit 11 in the horizontal direction X. This allows the wiring resistance on the output lines RL to be smaller than when the lamp drive circuit 21 is arranged on one side, and the voltage drop of the ramp voltage due to the wiring resistance can be suppressed. Furthermore, when the lamp drive circuit 21 is arranged on only one side, the wiring width of the output lines RL needs to be increased. However, by providing the lamp drive circuits 21 on both sides, the wiring width of the output lines RL can be reduced.

[0219] 17C is a diagram showing a connection configuration of lamp drive circuits, output lines (lamp wiring), and signal lines according to a second modification of the fifth embodiment. In Fig. 17C, a lamp drive circuit 21 is arranged for each signal line group including two or more signal lines in the horizontal direction X. This allows the wiring resistance on the output line RL to be smaller and the wiring width of the output line RL to be narrower than in Figs. 17A and 17B.

[0220] 17D is a diagram showing a connection configuration of lamp drive circuits, output lines (lamp wiring), and signal lines according to a third modification of the fifth embodiment. In Fig. 17D, a plurality of output lines RL corresponding to a plurality of lamp drive circuits 21 are connected to each other by resistor elements Rrl. By optimizing the resistance value of the resistor elements Rrl, it is possible to prevent adverse effects on the waveform of the ramp voltage.

[0221] 17E is a diagram showing a connection configuration of lamp drive circuits, output lines (lamp wiring), and signal lines according to a fourth modification of the fifth embodiment. The display drive circuit 20 in Fig. 17E has two lamp drive circuits 21 (hereinafter referred to as a first lamp drive circuit 21a and a second lamp drive circuit 21b) arranged for each signal line group including two or more signal lines arranged in the horizontal direction X, and the first lamp drive circuit 21a is connected to an output line RL that supplies a signal line voltage to the signal lines in the odd-numbered columns, and the second lamp drive circuit 21b is connected to an output line RL that supplies a signal line voltage to the signal lines in the even-numbered columns.

[0222] FIG. 17E shows an example in which each pixel is composed of three sub-pixels of red, green, and blue, and three signal lines corresponding to the three sub-pixels are alternately connected to the first lamp driving circuit 21a and the second lamp driving circuit 21b.

[0223] 17F is a diagram showing a connection configuration of lamp drive circuits, output lines (lamp wiring), and signal lines according to a fifth modification of the fifth embodiment. The display drive circuit 20 in FIG. 17F has lamp drive circuits 21 provided for each signal line group on both sides in the vertical direction Y. This reduces the wiring resistance on the signal lines.

[0224] 17G is a diagram showing a connection configuration of lamp drive circuits, output lines (lamp wiring), and signal lines according to a sixth modification of the fifth embodiment. The display drive circuit 20 in FIG. 17G has a separate lamp drive circuit 21 for each color. Therefore, the display drive circuit 20 in FIG. 17G has three times the number of lamp drive circuits 21 as the display drive circuit 20 in FIG. 17E.

[0225] As a modification of the display drive circuit 20 in Fig. 17G, as shown in Fig. 17F, a plurality of lamp drive circuits 21 may be arranged for each color on both sides in the vertical direction Y. In this case, twice the number of lamp drive circuits 21 as in Fig. 17G is provided.

[0226] The arrangement of the lamp drive circuit 21 shown in FIGS. 17A to 17G can also be applied to the drive circuits 90 according to the third and fourth embodiments.

[0227] In this way, in the fifth embodiment, the placement location and number of lamp driving circuits 21 can be optimized so as to minimize the wiring resistance on the output line RL.

[0228] Sixth Embodiment A display device 1 to which the display drive circuits 20 according to the first to fifth embodiments of the present disclosure can be applied does not necessarily have the same block configuration as that shown in Fig. 1. The display drive circuits 20 according to the first to fifth embodiments can also be applied to a display device having a block configuration different from that shown in Fig. 1.

[0229] Fig. 18 is a block diagram showing a schematic configuration of a display device 1a according to a sixth embodiment of the present disclosure. The display device 1a in Fig. 18 is, for example, a liquid crystal display device. The display device 1a in Fig. 18 is characterized in that a display portion and a driver portion are physically separated. The driver portion has a display drive circuit 20 according to any one of the first to fifth embodiments.

[0230] 18 includes a pixel array unit (display unit) 11, a source driver IC 20a, and a gate driver IC 20b. Signals are transmitted between the pixel array unit 11 and the source driver IC 20a and gate driver IC 20b via, for example, a flexible printed circuit board. The source driver IC 20a and gate driver IC 20b may be integrated into a single semiconductor chip.

[0231] The source driver IC 20a has an input / output interface unit (I / O) 2, a gamma generation circuit 3, a power supply circuit 4, a high-speed interface unit 5 (high-speed I / F), a control circuit 6, a horizontal logic circuit 9, and a horizontal analog circuit 10. The gate driver IC 20 has a vertical logic circuit 7 and a vertical analog circuit 8.

[0232] The display device 1a in Fig. 18 has a configuration that is effective when the pixel array unit 11 is relatively large, whereas the display device 1 shown in Fig. 1 is suitable for application to a microdisplay IC in which a display and a driver are integrated. The display drive circuit 20 and pixel array unit 11 in Fig. 1 can be arranged on the same semiconductor substrate.

[0233] 1, the display drive circuit 20 and the pixel array unit 11 may be stacked on two or more semiconductor substrates. Specifically, a first substrate on which the pixel array unit 11 is arranged and a second substrate on which the input / output interface unit 2 (I / O) other than the pixel array unit 11, the gamma generation circuit 3, the power supply circuit 4, the high-speed interface unit 5 (high-speed I / F), the control circuit 6, the vertical logic circuit 7, the vertical analog circuit 8, the horizontal logic circuit 9, and the horizontal analog circuit 10 are arranged may be joined and signal transmitted between them by Cu-Cu bonding, bumps, vias, or the like.

[0234] Fig. 19 is a block diagram showing an example of the internal configuration of the horizontal analog circuit 10 of Fig. 1 and Fig. 18. The horizontal analog circuit 10 of Fig. 19 includes a plurality of lamp drive circuits 21, each of which is formed by a signal line group including two or more signal lines arranged in the horizontal direction X, as shown in Fig. 17C etc.

[0235] In this way, the display driver circuit 20 according to the first to fifth embodiments can be built into the display device 1 in FIG. 1 or the display device 1a in FIG.

[0236] 1 has a pixel circuit including a light-emitting element such as an organic EL element for each pixel. Various modifications are possible for the specific circuit configuration of the pixel circuit. Representative circuit configurations are described below.

[0237] In the following description, only the essential components in this disclosure, such as other circuits necessary for display, are shown, but the pixels of the display device 1 also include other components not shown that are necessary for displaying images, etc.

[0238] Although each transistor below is shown as either n-type or p-type, these are shown as non-limiting examples, and the polarity of the transistor is not particularly important as long as it operates properly.

[0239] The light-emitting element in the following description is, for example, an LED (Light Emitting Diode). LEDs include OLEDs used in micro LED displays and OELs (Organic Electro Luminescence) used in organic EL displays. The light-emitting element may have a cathode connected to a ground voltage and emit light by a current flowing from the anode. As another example, the pixel may change its emission intensity by controlling liquid crystal.

[0240] 20A shows an example of the configuration of a pixel PIX. The pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. The transistors MN02 and MN03 are N-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of transistor MN02 is connected to a control line WSL, the other of the source and drain is connected to a signal line SGL, and one of the source and drain is connected to the gate of transistor MN03 and one end of capacitor C01. One end of capacitor C01 is connected to one of the source and drain of transistor MN02 and the gate of transistor MN03, and the other end is connected to one of the source and drain of transistor MN03 and the anode of the light-emitting element EL. The gate of transistor MN03 is connected to one of the source and drain of transistor MN02 and one end of capacitor C01, the other of the source and drain is connected to the power supply line VCCP, and one of the source and drain is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN03 and the other end of capacitor C01, and the cathode is connected to power supply line Vcath. The voltage of power supply line VCCP is switched between a first voltage and a second voltage lower than the first voltage as appropriate.

[0241] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During a period when the voltage of power supply line VCCP is at a first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. During a period when the voltage of power supply line VCCP is at a second voltage, light-emitting element EL is turned off.

[0242] (Second Specific Example) Figure 20B shows another example of the configuration of pixel PIX. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the gate of transistor MP14 and the other end of capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to one end of capacitor C12, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14, and the other end is connected to the other of the source and drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the source and drain of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the other of the source and drain of transistor MP12 and the other end of capacitor C12, one of its source and drain is connected to the other of the source and drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the other of its source and drain is connected to the anode of the light-emitting element EL and one of the source and drain of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP14 and the anode of the light-emitting element EL, and the other of its source and drain is connected to the power supply line VSS.

[0243] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0244] The transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0245] (Third Specific Example) Figure 20C shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to the gate of transistor MN24 and one end of capacitor C21. One end of capacitor C21 is connected to one of the source and drain of transistor MN22 and the gate of transistor MN24, and the other end is connected to one of the source and drain of transistor MN24, the other of the source and drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the other of its source and drain is connected to a power supply line VCCP, and one of its source and drain is connected to the other of the source and drain of transistor MN24. The gate of transistor MN24 is connected to one of the source and drain of transistor MN22 and one end of capacitor C21, the other of the source and drain is connected to one of the source and drain of transistor MN23, one of the source and drain is connected to the other end of capacitor C21, the other of the source and drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the other of the source and drain is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the anode of the light-emitting element EL, and one of the source and drain is connected to power supply line VSS.

[0246] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0247] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0248] 20D shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the gate of transistor MP33, the other of the source and drain of transistor MP34, and the other end of capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other of the source and drain of transistor MP34. The gate of transistor MP34 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP35, the other of its source and drain is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP34, and the other of its source and drain is connected to one of the source and drain of transistor MP36 and the anode of the light-emitting element EL. The gate of transistor MP36 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP35 and the anode of the light-emitting element EL, and the other of its source and drain is connected to the power supply line VSS.

[0249] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0250] The transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0251] 20E shows another example of the configuration of pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, and its gate is connected to control line WSL2, one of its source and drain is connected to signal line SGL1, and the other of its source and drain is connected to signal line SGL2.

[0252] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. The transistors MP42 to MP46 are P-type MOSFETs. The gate of the transistor MP42 is connected to the control line WSL1, one of its source and drain is connected to the signal line SGL2, and the other of its source and drain is connected to the gate of the transistor MP43 and the other end of the capacitor C41. One end of the capacitor C41 is connected to the power supply line VCCP, and the other end is connected to the other of the source and drain of the transistor MP42 and the gate of the transistor MP43. The gate of the transistor MP43 is connected to the other of the source and drain of the transistor MP42 and the other end of the capacitor C41, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the sources and drains of the transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP45, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP44, and the other of its source and drain is connected to one of the source and drain of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP45 and the anode of the light-emitting element EL, and the other of its source and drain is connected to power supply line VSS.

[0253] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied to signal line SGL1. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0254] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0255] 20F shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in the display area Da, and the display area Da is arranged between the first control unit Ct1 and the second control unit Ct2.

[0256] The first control unit Ct1 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. One end of the transmission gate TG45 receives a pixel signal, and the other end is connected to a signal line SGL1. One end of the transmission gate TG46 is connected to a signal line SGL2, and the other end is connected to a power supply line Vorst. One end of the capacitor C61 is connected to the signal line SGL1, and the other end is connected to a power supply line VSS1. The gate of transistor MP56 is connected to a control line INIL, one of its source and drain is connected to a power supply line Vini, and the other is connected to a signal line SGL2. The gate of transistor MP57 is connected to a control line ELL, one of its source and drain is connected to a power supply line Vel, and the other is connected to a signal line SGL2.

[0257] The second control unit Ct2 includes a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. One end of the transmission gate TG72 is connected to a signal line SGL1, and the other end is connected to the other of the source and drain of the transistor MP73 and one end of a capacitor C82. The gate of the transistor MP73 is connected to a control line REFL, one of the source and drain is connected to a power supply line Vref, and the other of the source and drain is connected to the other end of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the other end of the transmission gate TG72 and the other of the source and drain of the transistor MP73, and the other end is connected to a signal line SGL2.

[0258] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. The transistors MP121 to MP125 are P-type MOSFETs. The gate of the transistor MP122 is connected to the control line WSL, one of the source and drain is connected to the signal line SGL2, and the other of the source and drain is connected to the gate of the transistor MP121 and the other end of the capacitor C132. One end of the capacitor C132 is connected to the power supply line Vel, and the other end is connected to the other of the source and drain of the transistor MP122 and the gate of the transistor MP121. The gate of the transistor MP121 is connected to the other of the source and drain of the transistor MP122 and the other end of the capacitor C132, one of the source and drain is connected to the power supply line Vel, and the other of the source and drain is connected to one of the sources and drains of the transistors MP123 and MP124. The gate of transistor MP123 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP124 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP123, and the other of its source and drain is connected to one of the source and drain of transistor MP125 and the anode of the light-emitting element EL. The gate of transistor MP125 is connected to the control line AZSL, the other of its source and drain is connected to the power supply line Vorst, and one of its source and drain is connected to the other of the source and drain of transistor MP124 and the anode of the light-emitting element EL.

[0259] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied to one end of transmission gate TG45. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124 are connected to signal line SGL2. While transistor MP125 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on the signal on control line INIL, transistor MP57 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP56 is turned on, signal line SGL2 is set to the voltage of power supply line Vini, and when transistor MP57 is turned on, signal line SGL2 is set to the voltage of power supply line Vel. When transistor MP73 is turned on, one end of capacitor C82 is set to the voltage of power supply line Vref, thereby being initialized.

[0260] The transistors MP121 to MP125, MP56, and MP57 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0261] 20G shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the other of the source and drain of transistor MP53 and one of the source and drain of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, one of its source and drain is connected to a power supply line VCCP, and the other of its source and drain is connected to the other of the source and drain of transistor MP52 and one of the source and drain of transistor MP54. The gate of transistor MP54 is connected to one of the source and drain of transistor MP55, the other of the source and drain of transistor MP57, and the other end of capacitor C51, with one of its source and drain connected to the other of the sources and drains of transistors MP52 and MP53, and the other connected to one of the sources and drains of transistors MP58 and MP59. Capacitor C51 has one end connected to the power supply line VCCP, and the other end connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other of the source and drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. The gate of transistor MP55 is connected to control line AZSL1, with one of its source and drain connected to the gate of transistor MP54, the other of the source and drain of transistor MP57, and the other end of capacitor C51, and the other connected to one of the source and drain of transistor MP56. The gate of the transistor MP56 is connected to the control line AZSL1, one of the source and drain is connected to the other of the source and drain of the transistor MP55, and the other of the source and drain is connected to the power supply line VSS.The gate of transistor MP57 is connected to the control line WSL, the other of its source and drain is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other end of capacitor C51, and one of its source and drain is connected to the other of the source and drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the other of its source and drain is connected to one of the source and drain of transistor MP57, and one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP59. The gate of transistor MP59 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP58, and the other of its source and drain is connected to one of the source and drain of transistor MP60 and the anode of the light-emitting element EL. The gate of the transistor MP60 is connected to the control line AZSL2, one of the source and drain is connected to the other of the source and drain of the transistor MP59 and the anode of the light-emitting element EL, and the other of the source and drain is connected to the power supply line VSS.

[0262] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0263] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0264] (Eighth Specific Example)

[0265] 20H shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0266] The pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, and the other of its source and drain is connected to a signal line SGL and one of the source and drain of the transistor MP64, and one of its source and drain is connected to the other of the source and drain of the transistor MP64, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, and one of its source and drain is connected to the signal line SGL and the other of the source and drain of the transistor MN63, and the other of the source and drain is connected to one of the source and drain of the transistor MN63, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of capacitor C62 may be connected to the power supply line VSS3 (not shown).The gate of transistor MN65 is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, and one end of capacitors C61 and C62, the other of its source and drain is connected to the power supply line VCCP, and one of its source and drain is connected to the other of the sources and drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the other of its source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN67, and one of its source and drain is connected to power supply line VSS1. The gate of transistor MN67 is connected to control line DSL, the other of its source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and one of its source and drain is connected to the anode of the light-emitting element EL. Alternatively, the transistor MN67 and the control line DSL may be omitted, and one of the source and drain of the transistor MN65 may be connected to the other of the source and drain of the transistor MN66 and the anode of the light-emitting element EL.

[0267] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0268] The transistors MN63, MP64, MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0269] 20I shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to one of the source and drain of transistor MN74 and the other of the source and drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and one of the source and drain of transistor MN76, and the other end is connected to the other of the source and drain of transistor MN77, one of the source and drain of transistor MN75, and the anode of the light-emitting element EL. The gate of transistor MN73 is connected to control line DLS1, the other of its source and drain is connected to power supply line VCCP, one of its source and drain is connected to the other of transistor MN74 and the other of transistor MN76. The gate of transistor MN74 is connected to one of the source and drain of transistor MN76 and one end of capacitor C71, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN76, one of its source and drain is connected to one of the source and drain of transistor MN72 and the other of the source and drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the other of its source and drain is connected to one of the source and drain of transistor MN72 and one of the source and drain of transistor MN74, and one of its source and drain is connected to the other end of capacitor C71, the other of the source and drain of transistor MN77, and the anode of light-emitting element EL.The gate of transistor MN76 is connected to control line AZSL, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN74, one of its source and drain is connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to control line AZSL, the other of its source and drain is connected to the other end of capacitor C71, one of the source and drain of transistor MN75, and the anode of light-emitting element EL, and one of its source and drain is connected to power supply line VSS.

[0270] With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 is turned on and off based on the signal on control line DSL1, and transistor MN75 is turned on and off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current corresponding to the voltage across capacitor C71 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal on control line AZSL. While transistor MN77 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0271] The transistors MN72 to MN77 may be transistors using low temperature polysilicon (LTPS), and the transistor MN76 may be a transistor using an oxide semiconductor.

[0272] (Application Examples of Display Device 1 According to the Present Disclosure) Next, application examples of the display device 1 described in the above embodiment and modified examples will be described.

[0273] 21 is a diagram showing an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0274] (Second Application Example) FIG. 22 is a diagram illustrating an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a displayed image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0275] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0276] (Third Application Example) Figures 23A and 23B show an example of the appearance of a digital still camera 130, with Figure 23A showing a front view and Figure 23B showing a rear view. This digital still camera 130 is an interchangeable lens single-lens reflex camera and has a camera main body 131, an imaging lens unit 132, a grip unit 133, a monitor 134, and an electronic viewfinder 135. The imaging lens unit 312 is an interchangeable lens unit and is provided near the center of the front of the camera main body 311. The grip unit 133 is provided on the left side of the front of the camera main body 311, and the photographer holds this grip unit 133. The monitor 134 is provided to the left of the center of the back of the camera main body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera main body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0277] 24 is a diagram illustrating an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0278] 25 is a diagram illustrating an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information, and an operation unit 152 that includes buttons and the like that accept operation inputs by a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0279] (Sixth Application Example) Figures 26A and 26B are diagrams showing an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 26A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 26B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0280] The vehicle in Figures 26A and 26B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 106.

[0281] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 26A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0282] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0283] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0284] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0285] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0286] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0287] The rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurement of the body temperature of the rear seat passengers using a temperature sensor.

[0288] The techniques according to the above-described embodiments can be applied to the center display 201, console display 202, head-up display 203, digital rearview mirror 204, steering wheel display 205, and rear entertainment display 206.

[0289] The present technology may be configured as follows: (1) A display drive circuit comprising: a signal generation circuit that generates a first signal having a signal level that varies over time or a signal level that corresponds to a pixel signal; and an output circuit that outputs a second signal obtained by correcting the signal level of the first signal according to the signal level of an output line to the output line, wherein the output circuit has: a differential circuit that outputs a third signal that corresponds to a signal difference between the first signal and the second signal; and an output circuit that generates the second signal based on the third signal. (2) The display drive circuit according to (1), wherein the differential circuit has: a first differential circuit that outputs the third signal; and a second differential circuit that outputs an offset signal whose voltage level included in the second signal is fixed, wherein the output circuit alternately selects the third signal or the offset signal to generate the second signal. (3) The display drive circuit according to (2), wherein the third signal is a signal whose voltage level can change over time, and the second signal is a signal which alternates between a first period in which the voltage level can change over time and which is generated based on the third signal, and a second period in which the voltage level is fixed and which is generated based on the offset signal. (4) The display drive circuit according to (3), wherein the output line includes a first output line and a second output line, and the output circuit has: a first output circuit which outputs the second signal to the first output line, and a second output circuit which outputs the second signal to the second output line, and while the first output circuit outputs the second signal in the first period, the second output circuit outputs the second signal in the second period, and while the first output circuit outputs the second signal in the second period, the second output circuit outputs the second signal in the first period. (5) The display drive circuit according to (4), wherein the first signal is a ramp voltage whose voltage level changes over time, and further comprising a load circuit arranged on a feedback path of the first output circuit and the second output circuit, and the signal generating circuit controls the current flowing in the load circuit according to the ramp voltage and a reference voltage.(6) The display drive circuit according to (5), comprising: a comparator that compares the ramp voltage with the reference voltage; and a holding circuit that holds a comparison result signal of the comparator, wherein the signal generation circuit controls a current to be passed to the load circuit based on the comparison result signal. (7) The display drive circuit according to (6), wherein the output circuit has a switch that switches between inputting the second signal output from the first output circuit to the comparator and inputting it to the second differential circuit, and alternately switches between inputting the second signal output from the second output circuit to the comparator and inputting it to the second differential circuit. (8) The display drive circuit according to any one of (5) to (7), wherein the first differential circuit outputs the third signal according to a voltage difference between a feedback voltage input via the load circuit and a first reference voltage. (9) The display drive circuit according to (8), wherein, while one of the first output circuit or the second output circuit outputs the second signal whose voltage level changes over time from the first reference voltage, the other outputs the second signal at a substantially constant voltage level corresponding to a second reference voltage. (10) The display drive circuit according to (9), wherein the first output circuit and the second output circuit alternately switch between outputting the second signal whose voltage level changes over time and outputting the second signal at a substantially constant voltage level corresponding to the second reference voltage every one or more frame periods. (11) The display drive circuit according to any one of (4) to (10), comprising a signal line voltage generation circuit connected to the first output line and the second output line, which holds the voltage level of the second signal at a timing corresponding to the signal level of the pixel signal to generate signal line voltages for the first signal line and the second signal line. (12) The display drive circuit according to (11), wherein the first signal line or the second signal line is alternately connected for one or more pixel rows including a plurality of pixels arranged in a column direction. (13) The display drive circuit according to (3), wherein the output circuit alternately outputs the second signal in the first period or the second period to the output line.(14) The display drive circuit according to (13), wherein the first signal is a ramp voltage whose voltage level changes over time, the display drive circuit comprising: a load circuit arranged on a feedback path of the output circuit; a comparator that compares the ramp voltage with a reference voltage; and a holding circuit that holds a comparison result signal of the comparator, wherein the signal generation circuit controls a current to be passed to the load circuit based on the comparison result signal, and the output circuit has a switch that switches between inputting the second signal to the comparator and inputting it to the second differential circuit. (15) The display drive circuit according to (13) or (14), wherein the output circuit alternately switches within one frame period between outputting the second signal whose voltage level changes over time and outputting the second signal at a substantially constant voltage level corresponding to a second reference voltage. (16) The display drive circuit according to any one of (13) to (15), further comprising: a signal line voltage generation circuit connected to the output line and that holds the voltage level of the second signal at a timing corresponding to the signal level of the pixel signal to generate a signal line voltage for a signal line. (17) The display drive circuit according to (3), wherein the signal generation circuit generates the first signal having a signal level corresponding to the pixel signal, and the first differential circuit outputs the third signal corresponding to the signal difference between the first signal and the second signal. (18) The display drive circuit according to (17), wherein the signal generation circuit includes: a resistor ladder circuit including a plurality of resistors connected in series and parallel and outputting voltage signals with different voltage levels from between the plurality of resistors, and a selector that selects each of the plurality of voltage signals output from the resistor ladder circuit according to a value of each bit of a bit string of the pixel signal and combines the selected voltage signals to generate the first signal. (19) The display drive circuit according to (17) or (18), further comprising: a signal line voltage generation circuit connected to the output line and configured to hold the signal level of the second signal in synchronization with a timing at which the voltage level of the second signal changes and generate a signal line voltage for a signal line.(20) A display device comprising: a display unit having a plurality of pixels arranged in a first direction and a second direction; and a plurality of signal lines arranged at a predetermined interval in the first direction and supplying a signal line voltage to two or more pixels arranged in the second direction; and a display drive circuit that drives the plurality of signal lines, wherein the display drive circuit comprises: a signal generation circuit that generates a first signal having a signal level that changes with time or a signal level that corresponds to a pixel signal; and an output circuit that outputs a second signal to the output line, the second signal having a signal level corrected for the first signal according to the signal level of the output line, and the output circuit comprises: a differential circuit that outputs a third signal that corresponds to the signal difference between the first signal and the second signal; and an output circuit that generates the second signal based on the third signal.

[0290] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0291] 1, 1a Display device, 2 Input / output interface unit, 3 Gamma generation circuit, 4 Power supply circuit, 5 High-speed interface unit, 6 Control circuit, 7 Vertical logic circuit, 8 Vertical analog circuit, 9 Horizontal logic circuit, 10 Horizontal analog circuit, 11 Pixel array unit, 11a, 11b, 30 Pixel, 12a, 61a, 61b, 62a, 62b, 63a, 63b, 64a, 64b, 65a, 65b, 66a, 66b, 67a, 67b, 68a, 68b, 69a, 69b, 70a, 70b, 71a, 71b, 72a, 72b, 73a, 73b, 74a, 74b Transistor, 12b Light-emitting element, 13 Shift register, 14 First latch, 15 Second latch, 16 Digital comparator, 17 Synchronous counter, 18 PWM generation circuit, 19 Level shifter, 20, 80, 80a, 80b, 900, 910 Display drive circuit, 21, 901, 911 Lamp drive circuit, 21a First lamp drive circuit, 21b Second lamp drive circuit, 22, 22a, 22b Signal line voltage generation circuit, 23 PWM switch, 23b SEL switch, 30b, 30g, 30r Subpixel, 31, 91 Signal generation circuit, 32, 32a, 32b, 32c, 32d, 32e, 32f, 32g, 902a, 902b, 912a, 912b Output buffer, 33 Current control circuit, 34 Variable current source, 35 Comparator, 36 Holding circuit, 36a Second capacitor, 37, 907a, 907b SMPL switch, 38 Resistance element, 41, 904a, 904b Load circuit, 41a First capacitor, 41b, 93, 93a, 93b, 93c, 93d Resistor, 42 Differential circuit, 43, 906a, 906b RAMPEN switch, 44, 905a, 905b PRCG switch, 45 Output circuit, 46, 81 First switching circuit, 46a, 46b, 46c, 46d, 47a, 47b, 47c, 47d, 48a, 48b, 48c, 48d, 81a, 81b, 82a, 82b, 82c, 82d, 914a, 914b, 915a, 915b Switch, 47, 82 Second switching circuit, 48 Third switching circuit, 51 First differential circuit, 52 Second differential circuit, 53 First output circuit, 54 Second output circuit, 60a, 60b, 95 Current source, 75a, 75b Differential circuit main part, 76a, 76b Class AB bias circuit, 77a, 77b Output circuit main part, 90 Drive circuit, 92, 92a, 92b,92c resistor ladder circuit, 94 selector, 106 rear entertainment display, 110 head mounted display, 111, 151 display unit, 112 ear hook unit, 120 head mounted display, 121 main body unit, 122 arm unit, 123 lens barrel unit, 128 glasses, 129 lens, 130 digital still camera, 131, 311 camera main body unit, 132 photographing lens unit, 133 grip unit, 134 monitor, 135 electronic viewfinder, 140 television device, 141 video display screen unit, 142 front panel, 143 filter glass, 150 smartphone, 152 operation unit, 200 vehicle, 201 center display, 202 console display, 203 head-up display, 204 digital rear mirror, 205 steering wheel display, 206 Rear entertainment display, 261 dashboard, 262 driver's seat, 263 passenger seat, 264 center console, 265 shift lever, 266 windshield, 267 steering wheel, 312 imaging lens unit, 903a, 903b, 913a, 913b amplifier, 906 RAMPEN switching unit, 907 SMPL switching unit, 908a, 908b, 908c parasitic capacitance, 914, 915 switching unit,

Claims

1. A display driver circuit comprising: a signal generation circuit that generates a first signal whose signal level varies over time or whose signal level corresponds to a pixel signal; and an output circuit that outputs a second signal to an output line, the second signal being obtained by correcting the signal level of the first signal according to the signal level of the output line, wherein the output circuit has: a differential circuit that outputs a third signal corresponding to the signal difference between the first signal and the second signal; and an output circuit that generates the second signal based on the third signal.

2. The display drive circuit according to claim 1, wherein the differential circuit comprises a first differential circuit that outputs the third signal and a second differential circuit that outputs an offset signal whose voltage level is fixed and is included in the second signal, and the output circuit alternately selects the third signal or the offset signal to generate the second signal.

3. The display drive circuit according to claim 2, wherein the third signal is a signal whose voltage level can change over time, and the second signal is a signal that alternates between a first period in which the voltage level can change over time and is generated based on the third signal, and a second period in which the voltage level is fixed and is generated based on the offset signal.

4. The display drive circuit according to claim 3, wherein the output lines include first output lines and second output lines, the output circuit has a first output circuit that outputs the second signal to the first output line, and a second output circuit that outputs the second signal to the second output line, and while the first output circuit outputs the second signal for the first period, the second output circuit outputs the second signal for the second period, and while the first output circuit outputs the second signal for the second period, the second output circuit outputs the second signal for the first period.

5. A display drive circuit as claimed in claim 4, wherein the first signal is a ramp voltage whose voltage level changes over time, and further comprising a load circuit arranged on a feedback path between the first output circuit and the second output circuit, and the signal generation circuit controls the current flowing in the load circuit in accordance with the ramp voltage and a reference voltage.

6. The display drive circuit according to claim 5, comprising: a comparator that compares the ramp voltage with the reference voltage; and a holding circuit that holds a comparison result signal from the comparator, wherein the signal generation circuit controls the current flowing through the load circuit based on the comparison result signal.

7. The display drive circuit according to claim 6, wherein the output circuit has a switch that switches between inputting the second signal output from the first output circuit to the comparator and inputting it to the second differential circuit, and that alternately switches between inputting the second signal output from the second output circuit to the comparator and inputting it to the second differential circuit.

8. The display drive circuit according to claim 5, wherein the first differential circuit outputs the third signal according to a voltage difference between a feedback voltage input via the load circuit and a first reference voltage.

9. The display drive circuit according to claim 8, wherein, while one of the first output circuit and the second output circuit is outputting the second signal whose voltage level changes over time from the first reference voltage, the other output circuit outputs the second signal at a substantially constant voltage level according to the second reference voltage.

10. A display drive circuit according to claim 9, wherein the first output circuit and the second output circuit alternately switch between outputting the second signal whose voltage level changes with time and outputting the second signal whose voltage level is approximately constant according to the second reference voltage, every one or more horizontal line periods.

11. The display driver circuit according to claim 4, further comprising a signal line voltage generation circuit connected to the first output line and the second output line, which holds the voltage level of the second signal at a timing according to the signal level of the pixel signal to generate signal line voltages for the first signal line and the second signal line.

12. The display driver circuit according to claim 11, wherein the first signal lines or the second signal lines are alternately connected for each of one or more pixel rows including a plurality of pixels aligned in the column direction.

13. The display driver circuit according to claim 3, wherein the output circuit alternately outputs the second signal in the first period or the second period to the output line.

14. A display driver circuit as described in claim 13, wherein the first signal is a ramp voltage whose voltage level changes over time, the display driver circuit comprising: a load circuit arranged on a feedback path of the output circuit; a comparator that compares the ramp voltage with a reference voltage; and a holding circuit that holds a comparison result signal of the comparator; the signal generating circuit controls a current to be passed through the load circuit based on the comparison result signal; and the output circuit has a switch that switches whether the second signal is input to the comparator or the second differential circuit.

15. The display drive circuit according to claim 13, wherein the output circuit alternately switches within one frame period between outputting the second signal whose voltage level changes with time and outputting the second signal whose voltage level is approximately constant according to a second reference voltage.

16. The display driver circuit according to claim 13, further comprising a signal line voltage generating circuit connected to the output line, which holds the voltage level of the second signal at a timing according to the signal level of the pixel signal to generate a signal line voltage for the signal line.

17. The display drive circuit according to claim 3, wherein the signal generation circuit generates the first signal at a signal level corresponding to the pixel signal, and the first differential circuit outputs the third signal corresponding to the signal difference between the first signal and the second signal.

18. The display drive circuit according to claim 17, wherein the signal generation circuit comprises: a resistor ladder circuit including a plurality of resistors connected in series and parallel, and outputting voltage signals with different voltage levels from between the plurality of resistors; and a selector that selects each of the plurality of voltage signals output from the resistor ladder circuit based on the value of each bit in the bit string of the pixel signal, and combines the selected voltage signals to generate the first signal.

19. The display driver circuit according to claim 17, further comprising a signal line voltage generating circuit connected to the output line, which generates a signal line voltage for the signal line by maintaining the signal level of the second signal in synchronization with the timing at which the voltage level of the second signal changes.

20. A display device comprising: a display unit having a plurality of pixels arranged in a first direction and a second direction; and a plurality of signal lines arranged at predetermined intervals in the first direction and supplying a signal line voltage to two or more pixels arranged in the second direction; and a display drive circuit for driving the plurality of signal lines, wherein the display drive circuit comprises: a signal generation circuit for generating a first signal having a signal level that changes with time or a signal level corresponding to a pixel signal; and an output circuit for outputting to the output line a second signal obtained by correcting the signal level of the first signal according to the signal level of the output line, wherein the output circuit comprises: a differential circuit for outputting a third signal corresponding to the signal difference between the first signal and the second signal; and an output circuit for generating the second signal based on the third signal.

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