Waveform shaping circuit and semiconductor integrated circuit

Abstract

A first pull-up switch 106 and a second pull-down switch 112 are CMOS switches driven by a first input signal INp and an output #INp of a first inversion buffer 102. A second pull-up switch 110 and a first pull-down switch 108 are CMOS switches driven by a second input signal INn and an output #INn of a second inversion buffer 104. A latch circuit 114 is connected to a first node n1 and a second node n2. A first output buffer 116 and a second output buffer 118 receive a voltage Vn1 of the first node n1 and a voltage Vn2 of the second node n2.

Description

Waveform shaping circuit and semiconductor integrated circuit

[0001] The present disclosure relates to a waveform shaping circuit.

[0002] In digital circuits and analog-digital mixed circuits, differential or single-ended pulse signals are used for clock signals, data signals, and various control signals.

[0003] An ideal differential pulse signal has a duty cycle of 50%, a waveform in which the slopes (rise time, fall time) of the positive and negative edges are equal, and the cross point is located at the midpoint of the signal amplitude. However, the differential pulse signal deviates from the ideal state due to the effects of PVT (process, voltage, temperature) or the effects of the circuit through which the differential pulse signal propagates.

[0004] For example, differential pulse signals are used to control CMOS switches (transfer gates) in chopper amplifiers and A / D converters. If the cross point of these differential pulse signals is shifted, the noise cancellation effect of the CMOS switch is lost.

[0005] Furthermore, an ideal single-ended pulse signal has a duty cycle of 50% and a waveform in which the slopes of the positive and negative edges are equal, but if the waveform deviates from the ideal, it can lead to a reduction in the timing margin of the logic circuit in the subsequent stage.

[0006] JP 2011-228849 A

[0007] [Summary] The present disclosure has been made in light of the above circumstances, and one exemplary purpose of an embodiment thereof is to provide a waveform shaping circuit capable of generating a differential signal whose cross point is located at the midpoint of the signal amplitude.

[0008] An aspect of the present disclosure relates to a waveform shaping circuit for shaping a differential input signal including a first input signal and a second input signal. The waveform shaping circuit includes a first inverting buffer that inverts the first input signal, a second inverting buffer that inverts the second input signal, a first node, a second node, and a complementary metal oxide semiconductor (CMOS) connected between a power supply line and the first node, receiving the first input signal at a first control terminal and receiving an output signal of the first inverting buffer at a second control terminal. the first pull-up switch is a CMOS switch connected between a first node and a ground line and receives a second input signal at a first control terminal and an output signal of the second inverting buffer at a second control terminal; the second pull-up switch is a CMOS switch connected between a power supply line and the second node and receives the second input signal at a first control terminal and an output signal of the second inverting buffer at a second control terminal; the second pull-down switch is a CMOS switch connected between the second node and the ground line and receives the first input signal at a first control terminal and an output signal of the first inverting buffer at a second control terminal; a latch circuit connected between the first node and the second node; a first output buffer having an input terminal connected to the first node; and a second output buffer having an input terminal connected to the second node.

[0009] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention.

[0010] FIG. 1 is a circuit diagram of a waveform shaping circuit according to an embodiment. FIG. 2 is a waveform diagram illustrating the operation of the waveform shaping circuit of FIG. 1. FIG. 3 is a waveform diagram illustrating the operation of a waveform shaping circuit according to comparative technique 1. FIG. 4 is a waveform diagram illustrating the operation of a waveform shaping circuit according to comparative technique 2. FIG. 5 is a circuit diagram of a waveform shaping circuit according to an embodiment. FIG. 6 is a circuit diagram showing another configuration example of a latch circuit. FIG. 7 is a circuit diagram of a semiconductor integrated circuit including a waveform shaping circuit. FIG. 8 is a circuit diagram of a semiconductor integrated circuit including a waveform shaping circuit. FIG. 9 is a circuit diagram of a semiconductor integrated circuit including a waveform shaping circuit. FIG. 10 is a circuit diagram of a semiconductor integrated circuit including a waveform shaping circuit.

[0011] DETAILED DESCRIPTION (Summary of the Embodiments) A summary of some exemplary embodiments of the present disclosure will be provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the detailed description that follows, and is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0012] A waveform shaping circuit according to one embodiment shapes a differential input signal including a first input signal and a second input signal. The waveform shaping circuit includes a first inverting buffer that inverts the first input signal, a second inverting buffer that inverts the second input signal, a first node, a second node, and a complementary metal oxide semiconductor (CMOS) connected between a power supply line and the first node, receiving the first input signal at a first control terminal and receiving an output signal of the first inverting buffer at a second control terminal. the first pull-up switch is a CMOS switch connected between a first node and a ground line and receives a second input signal at a first control terminal and an output signal of the second inverting buffer at a second control terminal; the second pull-up switch is a CMOS switch connected between a power supply line and the second node and receives the second input signal at a first control terminal and an output signal of the second inverting buffer at a second control terminal; the second pull-down switch is a CMOS switch connected between the second node and the ground line and receives the first input signal at a first control terminal and an output signal of the first inverting buffer at a second control terminal; a latch circuit connected between the first node and the second node; a first output buffer having an input terminal connected to the first node; and a second output buffer having an input terminal connected to the second node.

[0013] The pull-up switch and pull-down switch, which are CMOS switches, turn on and off in response to the differential input switch, resulting in the generation of a differential first signal and a differential second signal at the first node and the second node. Therefore, by adjusting the size (drive capability) of the pull-up switch and the pull-down switch, the crosspoint of the first signal generated at the first node and the second signal generated at the second node can be shaped to near the midpoint. Furthermore, by providing a latch circuit that operates as a positive feedback circuit, the crosspoint of the first and second signals can be shaped while increasing the slew rate. Furthermore, by providing a first output buffer and a second output buffer at the output stage, the first node and the second node can be isolated from the load, and the slew rates of the first and second signals are not affected by the load.

[0014] In one embodiment, the drive capability of the latch circuit may be lower than the drive capabilities of the first pull-up switch, the first pull-down switch, the second pull-up switch, and the second pull-down switch.

[0015] In one embodiment, the first inverting buffer and the second inverting buffer may be an inverter, a NOR gate, or a NAND gate.

[0016] A semiconductor integrated circuit according to an embodiment may include an SR latch and any one of the waveform shaping circuits described above that receives the non-inverted output signal and the inverted output signal of the SR latch.

[0017] A semiconductor integrated circuit according to an embodiment may include a differential level shifter and any one of the waveform shaping circuits described above that receives an output from the differential level shifter.

[0018] A semiconductor integrated circuit according to an embodiment may include a single-ended / differential conversion circuit that receives a single-ended signal, and any one of the waveform shaping circuits described above that receives an output signal from the single-ended / differential conversion circuit.

[0019] A semiconductor integrated circuit according to an embodiment may include a CMOS switch and any one of the waveform shaping circuits described above that drives the CMOS switch.

[0020] (Embodiments) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0021] In this specification, "a state in which component A is connected to component B" includes a case in which component A and component B are directly physically connected to each other, and a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their connection.

[0022] Similarly, "a state in which component C is provided between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected to each other, but also a case in which they are indirectly connected to each other via other components that do not substantially affect the electrical connection state between them or that do not impair the functions or effects achieved by their combination.

[0023] 1 is a circuit diagram of a waveform shaping circuit 100 according to an embodiment. The waveform shaping circuit 100 receives a first input signal IN ｐ and the second input signal IN ｎ and outputs differential output signals OUTp and OUTn after shaping.

[0024] The waveform shaping circuit 100 includes a first inverting buffer 102, a second inverting buffer 104, a first node n1, a second node n2, a first pull-up switch 106, a first pull-down switch 108, a second pull-up switch 110, a second pull-down switch 112, a latch circuit 114, a first output buffer 116, and a second output buffer 118.

[0025] The first inverting buffer 102 receives the first input signal IN ｐ The second inverting buffer 104 inverts the second input signal IN ｎ Invert.

[0026] The first inverting buffer 102 and the second inverting buffer 104 can be configured as an inverter (negation gate), a NOR gate, or a NAND gate.

[0027] The first pull-up switch 106 includes a CMOS switch connected between the power supply line VDD and the first node n1. A first input signal IN ｐ is input to its second control terminal (the gate of the PMOS transistor side), and the output signal #IN of the first inverting buffer 102 is input to its second control terminal (the gate of the PMOS transistor side). ｐ is entered.

[0028] The first pull-down switch 108 includes a CMOS switch connected between the first node n1 and the ground line VSS. A first control terminal of the CMOS switch receives a second input signal IN ｎ is input to its second control terminal, and the output signal #IN of the second inverting buffer 104 is input to its second control terminal. ｎ is entered.

[0029] The second pull-up switch 110 includes a CMOS switch connected between the power supply line VDD and the second node n2. A first control terminal of the CMOS switch receives a second input signal IN ｎ is input to its second control terminal, and the output signal #IN of the second inverting buffer 104 is input to its second control terminal. ｎ is entered.

[0030] The second pull-down switch 112 includes a CMOS switch connected between the second node n2 and the ground line. A first control terminal of the CMOS switch receives the first input signal IN ｐ is input to its second control terminal, and the output signal #IN of the first inverting buffer 102 is input to its second control terminal. ｐ is entered.

[0031] That is, the first pull-up switch 106 and the second pull-down switch 112 share two signals IN ｐ , #IN ｐ The first pull-down switch 108 and the second pull-up switch 110 are controlled by two common signals IN ｎ , #IN ｎ is controlled by

[0032] The latch circuit 114 is connected between the first node n1 and the second node n2 and may be any of two cross-coupled inverters, two cross-coupled NAND gates, or two cross-coupled NOR gates.

[0033] The first output buffer 116 has an input terminal connected to the first node n1, and the second output buffer 118 has an input terminal connected to the second node n2.

[0034] The above is the configuration of the waveform shaping circuit 100. Next, the operation thereof will be described.

[0035] 2 is a waveform diagram illustrating the operation of the waveform shaping circuit 100 of FIG. 2. In FIG. 2, from top to bottom, a differential input signal IN ｐ , IN ｎ , the first pull-up switch 106, the first inverting buffer 102, and the output #IN of the second inverting buffer 104 ｐ , #IN ｎ , a voltage (referred to as a first voltage) Vn1 at the first node n1, a voltage (referred to as a second voltage) Vn2 at the second node n2, and an output signal OUT ｐ , OUT ｎ is shown.

[0036] First input signal IN ｐ is high, the second input signal IN ｎ When #IN goes low, the output #IN of the first inverting buffer 102 ｐ is low, the output of the second inverting buffer 104 #IN ｎ transitions to high. At this time, the first pull-up switch 106 and the second pull-down switch 112 are turned on, and the second pull-up switch 110 and the first pull-down switch 108 are turned off.

[0037] Since the first pull-up switch 106 is on, the first node n1 is pulled up, and the first voltage Vn1 transitions to a high voltage. Since the second pull-down switch 112 is on, the second node n2 is pulled down, and the second voltage Vn2 transitions to a low voltage. Here, the first pull-up switch 106 and the second pull-down switch 112 receive the same signal IN ｐ and #IN ｐ Therefore, the rise rate of the first voltage Vn1 and the fall rate of the second voltage Vn2 are the same. Therefore, the cross point CP1 can be positioned near the midpoint of the amplitude.

[0038] First input signal IN ｐ is low, the second input signal IN ｎ When #IN goes high, the output #IN of the first inverting buffer 102 ｐ is high, the output of the second inverting buffer 104 is #IN ｎtransitions to low. At this time, the second pull-up switch 110 and the first pull-down switch 108 are turned on, and the first pull-up switch 106 and the second pull-down switch 112 are turned off.

[0039] Since the second pull-up switch 110 is on, the second node n2 is pulled up, and the second voltage Vn2 transitions to a high voltage. Since the first pull-down switch 108 is on, the first node n1 is pulled down, and the first voltage Vn1 transitions to a low voltage. Here, the first pull-down switch 108 and the second pull-up switch 110 are connected to the same signal IN ｎ and #IN ｎ Since the first voltage Vn1 and the second voltage Vn2 are controlled by a combination of the above, the fall rate (slew rate) of the first voltage Vn1 and the rise rate of the second voltage Vn2 are the same.

[0040] In addition, the shaped signal output is driven by the latch circuit 114 using positive feedback, thereby increasing the slew rate.

[0041] Furthermore, the cross points CP1 and CP2 can be positioned at the midpoint of the amplitude by adjusting the sizes of the first pull-up switch 106, the first pull-down switch 108, the second pull-up switch 110, the second pull-down switch 112, and the latch circuit 114. In this case, since the rising / falling signals are driven complementarily between the differential signals, the cross points of the adjusted signals are not significantly affected by PVT fluctuations.

[0042] Outputs OUT of the first output buffer 116 and the second output buffer 118 ｐ , OUT ｎ is an ideal differential signal with the cross point located at the midpoint of the amplitude.

[0043] The output OUT of the waveform shaping circuit 100 ｐ , OUT ｎ does not necessarily have to be used as a differential signal, and only one of them may be used as a single-ended signal.

[0044] The above is the operation of the waveform shaping circuit 100. The advantages of the waveform shaping circuit 100 will be explained in comparison with the comparative technology.

[0045] 3 is a waveform diagram illustrating the operation of a waveform shaping circuit according to comparative technique 1. Comparative technique 1 does not include the latch circuit 114. In comparative technique 1, the first voltage Vn1 and the second voltage Vn2 have the same speed (slew rate) of rising and falling edges, but the lack of the latch circuit 114 makes them slightly slower than those in the embodiment.

[0046] Furthermore, since there is no latch circuit 114, the cross point of the first voltage Vn1 and the second voltage Vn2 cannot be adjusted, and the cross point is biased toward the ground voltage Vss side from the amplitude midpoint. ｐ , OUT ｎ The cross point of the signal also shifts from the midpoint of the amplitude.

[0047] In this embodiment, the positive feedback of the latch circuit 114 can increase the speed of the rising edge and the falling edge, and further position the cross point at the midpoint of the amplitude.

[0048] 4 is a waveform diagram illustrating the operation of a waveform shaping circuit according to comparative technique 2. In comparative technique 2, the first inverting buffer 102, the second inverting buffer 104, the first pull-up switch 106, the first pull-down switch 108, the second pull-up switch 110, and the second pull-down switch 112 are omitted, and the first node n1 and the second node n2 are connected to the input differential signal IN ｐ , IN ｎ The motor is directly driven by the motor.

[0049] In this case, the input differential signal IN ｐ , IN ｎ However, the waveform of the output signal OUT is directly shaped by the latch circuit 114, but is significantly affected by the circuit preceding the waveform shaping circuit 100. If the output impedance of the circuit preceding the waveform shaping circuit 100 is high, that is, if its performance is low, significant waveform distortion occurs in the first voltage Vn1 and the second voltage Vn2, as shown in FIG. ｐ , OUT ｎ The crossover point is biased significantly upward.

[0050] If the driving capability of the latch circuit 114 is reduced in order to suppress waveform distortion, the effect of waveform shaping will be weakened.

[0051] Thus, in comparative technique 2, there is a trade-off between waveform shaping and distortion.

[0052] In contrast to this, in the embodiment, the first node n1 and the second node n2 are driven not by the circuit preceding the waveform shaping circuit 100, but by the first pull-up switch 106, the first pull-down switch 108, the second pull-up switch 110, and the second pull-down switch 112. Therefore, by independently designing the drive capabilities of the four switches 106, 108, 110, and 112 and the drive capability of the latch circuit 114, it becomes possible to perform waveform shaping while suppressing waveform distortion.

[0053] Specifically, the drive capability of the latch circuit 114 is preferably lower than the drive capabilities of the first pull-up switch 106, the first pull-down switch 108, the second pull-up switch 110, and the second pull-down switch 112. The drive capability can be rephrased as W / L (gate width / gate length) of a MOS transistor.

[0054] 5 is a circuit diagram of a waveform shaping circuit 100 according to one embodiment. The first inverting buffer 102 and the second inverting buffer 104 are inverters. The first output buffer 116 and the second output buffer 118 are also inverters. The latch circuit 114 is composed of two cross-coupled inverters. The first output buffer 116 and the second output buffer 118 may each be composed of a plurality of inverters connected in series.

[0055] 6 is a circuit diagram showing another example of the configuration of the latch circuit 114. The left latch circuit 114a includes two cross-coupled NOR gates. The center latch circuit 114b includes two cross-coupled NAND gates. The right latch circuit 114c includes two cross-coupled NAND gates, and is configured so that an enable signal is input to one input terminal of each of the two NAND gates.

[0056] Next, an application circuit of the waveform shaping circuit 100 will be described.

[0057] (Application Circuit 1) FIG. 7 is a circuit diagram of a semiconductor integrated circuit 200A including a waveform shaping circuit 100. As shown in FIG.

[0058] The semiconductor integrated circuit 200A receives a primary digital signal D ｉｎ to the isolated secondary side. The semiconductor integrated circuit 200A includes an SR latch (SR flip-flop) 202, a first transformer 204, a second transformer 206, a driver 208, and a waveform shaping circuit 100.

[0059] The driver 208 generates a set pulse current Is in response to a positive edge of the digital signal Din and generates a reset pulse current Ir in response to a negative edge of the digital signal Din. The set pulse current Is is supplied to the primary winding of the transformer 204. The SR latch 202 on the secondary side is set in response to the set pulse signal generated in the secondary winding of the transformer 204. The reset pulse current Ir is supplied to the primary winding of the transformer 206. The SR latch 202 on the secondary side is reset in response to the reset pulse signal generated in the secondary winding of the transformer 206. The output Q and inverted output \Q of the SR latch 202 are differential signals (\ represents inversion).

[0060] If the outputs Q, \Q of the SR latch 202 include a NOR gate, they will have an asymmetric waveform with the cross point located below the midpoint of the amplitude. In this case, if the output Q of the SR latch 202 is used directly on the secondary side, the high period will be shorter than that of the original input digital signal Din. Conversely, if the SR latch 202 includes a NAND gate, they will have an asymmetric waveform with the cross point located above the midpoint of the amplitude, and if the output Q of the SR latch 202 is used directly on the secondary side, the high period will be longer than that of the original input digital signal Din.

[0061] The waveform shaping circuit 100 converts the differential signals Q and \Q into a differential input signal IN ｐ , IN ｎ The output signal is received as a signal, shaped into a waveform, and output. Ｐ , OUT ｎ is the original input digital signal D ｉｎThe two outputs of the waveform shaping circuit 100 may be used as differential signals, or one may be used as a single-ended signal.

[0062] (Application Circuit 2) FIG. 8 is a circuit diagram of a semiconductor integrated circuit 200B including the waveform shaping circuit 100. As shown in FIG.

[0063] The semiconductor integrated circuit 200B includes a differential level shifter 210 and a waveform shaping circuit 100. The differential level shifter 210 outputs a differential signal S having a signal level lower than the power supply voltage VDD of the waveform shaping circuit 100. ｐ , S ｎ and a differential signal IN ｐ , IN ｎ Level shift up to.

[0064] The differential level shifter 210 includes PMOS transistors MP11, MP12, MP13, and MP14, and NMOS transistors MN11 and MN12. The output signal IN ｐ , IN ｎ In the case of the output of the NOR type SR latch, the cross point is located below the midpoint of the amplitude.

[0065] The waveform shaping circuit 100 converts the output signal IN ｐ , IN ｎ By shaping the signal, an ideal differential signal OUT ｐ , OUT ｎ can be generated.

[0066] (Application Circuit 3) FIG. 9 is a circuit diagram of a semiconductor integrated circuit 200C including the waveform shaping circuit 100. As shown in FIG.

[0067] The semiconductor integrated circuit 200C includes a single-ended / differential conversion circuit 220, a waveform shaping circuit 100, and a CMOS switch 240. The single-ended / differential conversion circuit 220 converts a single-ended input signal S ＩＮ differential signal IN ｐ , IN ｎThe configuration of the single-ended / differential conversion circuit 220 is not particularly limited, but in this example, it includes inverters 222, 224, 226, and 228 and a transfer gate (CMOS switch) 229. The waveform shaping circuit 100 converts the differential signal IN ｐ , IN ｎ Format the following.

[0068] Differential output OUT of waveform shaping circuit 100 ｐ , OUT ｎ is suitable for driving the CMOS switch 250. The CMOS switch 250 is used in a chopper amplifier, an auto-zero amplifier, an A / D converter, etc. ｐ , OUT ｎ has an ideal waveform, making it easier to cancel clock feedthrough and charge injection.

[0069] (Application Circuit 4) FIG. 10 is a circuit diagram of a semiconductor integrated circuit 200D including the waveform shaping circuit 100. As shown in FIG.

[0070] The semiconductor integrated circuit 200D includes a single-ended / differential conversion circuit 230 and a waveform shaping circuit 100. The single-ended / differential conversion circuit 220 converts a single-ended input signal S ＩＮ differential signal IN ｐ , IN ｎ The single-ended to differential conversion circuit 230 includes an inverter 232 and an SR latch 234. The waveform shaping circuit 100 converts the differential signal IN ｐ , IN ｎ Format the following.

[0071] Alternatively, only one of the differential outputs OUTp and OUTn may be used as a single-ended signal. Even when used as a single-ended signal, variations in the signal pulse width and the duty cycle of the periodic signal (clock) can be suppressed by suppressing the difference in rise / fall time caused by PVT fluctuations.

[0072] (Additional Note) The following techniques are disclosed in this specification.

[0073] (Item 1) A waveform shaping circuit that shapes a differential input signal including a first input signal and a second input signal, comprising: a first inverting buffer that inverts the first input signal; a second inverting buffer that inverts the second input signal; a first node; a second node; a first pull-up switch that is a CMOS (Complementary Metal Oxide Semiconductor) switch connected between a power supply line and the first node, and receiving the first input signal at a first control terminal and an output signal of the first inverting buffer at a second control terminal; a first pull-down switch that is a CMOS switch connected between the first node and a ground line, and receiving the second input signal at a first control terminal and an output signal of the second inverting buffer at a second control terminal; and a second pull-up switch that is a CMOS switch connected between the power supply line and the second node, and receiving the second input signal at a first control terminal and an output signal of the second inverting buffer at a second control terminal. a second pull-down switch that is a CMOS switch connected between the second node and the ground line, receiving the first input signal at a first control terminal and receiving the output signal of the first inverting buffer at a second control terminal; a latch circuit connected between the first node and the second node; a first output buffer having an input terminal connected to the first node; and a second output buffer having an input terminal connected to the second node.

[0074] (Item 2) The waveform shaping circuit according to item 1, wherein the drive capability of the latch circuit is lower than the drive capabilities of the first pull-up switch, the first pull-down switch, the second pull-up switch, and the second pull-down switch.

[0075] (Item 3) The waveform shaping circuit according to item 1, wherein the first inverting buffer and the second inverting buffer are either an inverter, a NOR gate, or a NAND gate.

[0076] (Item 4) A semiconductor integrated circuit comprising: an SR latch; and the waveform shaping circuit according to any one of items 1 to 3, which receives a non-inverted output signal and an inverted output signal of the SR latch.

[0077] (Item 5) A semiconductor integrated circuit comprising: a differential level shifter; and the waveform shaping circuit according to any one of items 1 to 3, which receives an output from the differential level shifter.

[0078] (Item 6) A semiconductor integrated circuit comprising: a single-ended / differential conversion circuit that receives a single-ended signal; and the waveform shaping circuit according to any one of items 1 to 3 that receives an output signal from the single-ended / differential conversion circuit.

[0079] (Item 7) A semiconductor integrated circuit comprising: a CMOS switch; and the waveform shaping circuit according to any one of items 1 to 3 that drives the CMOS switch.

[0080] The present disclosure relates to a waveform shaping circuit.

[0081] 100...waveform shaping circuit, n1...first node, n2...second node, 102...first inverting buffer, 104...second inverting buffer, 106...first pull-up switch, 108...first pull-down switch, 110...second pull-up switch, 112...second pull-down switch, 114...latch circuit, 116...first output buffer, 118...second output buffer, 200...semiconductor integrated circuit, 202...SR latch, 204...first transformer, 206...second transformer, 208...driver, 210...differential level shifter, 220, 230...single-ended / differential conversion circuit, 250...CMOS switch

Claims

1. A waveform shaping circuit for shaping a differential input signal including a first input signal and a second input signal, comprising: a first inverting buffer that inverts the first input signal; a second inverting buffer that inverts the second input signal; a first node; a second node; a first pull-up switch that is a CMOS (Complementary Metal Oxide Semiconductor) switch connected between a power supply line and the first node, and receiving the first input signal at a first control terminal and an output signal of the first inverting buffer at a second control terminal; a first pull-down switch that is a CMOS switch connected between the first node and a ground line, and receiving the second input signal at a first control terminal and an output signal of the second inverting buffer at a second control terminal; and a second pull-up switch that is a CMOS switch connected between the power supply line and the second node, and receiving the second input signal at a first control terminal and an output signal of the second inverting buffer at a second control terminal. a second pull-down switch that is a CMOS switch connected between the second node and the ground line, receiving the first input signal at a first control terminal and receiving the output signal of the first inverting buffer at a second control terminal; a latch circuit connected between the first node and the second node; a first output buffer having an input terminal connected to the first node; and a second output buffer having an input terminal connected to the second node.

2. The waveform shaping circuit according to claim 1, wherein the drive capability of said latch circuit is lower than the drive capabilities of said first pull-up switch, said first pull-down switch, said second pull-up switch, and said second pull-down switch.

3. The waveform shaping circuit according to claim 1 or 2, wherein the first inverting buffer and the second inverting buffer are either an inverter, a NOR gate, or a NAND gate.

4. A semiconductor integrated circuit comprising: an SR latch; and the waveform shaping circuit according to claim 1 or 2, which receives a non-inverted output signal and an inverted output signal of said SR latch.

5. A semiconductor integrated circuit comprising: a differential level shifter; and the waveform shaping circuit according to claim 1 or 2, which receives an output from the differential level shifter.

6. A semiconductor integrated circuit comprising: a single-ended / differential conversion circuit that receives a single-ended signal; and the waveform shaping circuit according to claim 1 or 2 that receives an output signal from the single-ended / differential conversion circuit.

7. A semiconductor integrated circuit comprising: a CMOS switch; and the waveform shaping circuit according to claim 1 or 2 that drives the CMOS switch.

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