Semiconductor memory device

Abstract

The present invention provides a layout structure that, for a mask read only memory (ROM), suppresses a decrease in operation speed without an increase in area. In this semiconductor memory device, a memory cell (M00) is provided with a nanosheet FET that is provided between a bit line (21) and ground power supply wiring (11), has a gate connected to a word line (41), and has a drain connected to the bit line (21). The bit line (21) is formed in a wiring layer on the front surface side of the nanosheet FET, and the ground power supply wiring (11) is formed in a wiring layer on the back surface side of the nanosheet FET. The memory cell (M00) stores data depending on the presence or absence of connection between a source of the nanosheet FET and the ground power supply wiring (11).

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device, and more particularly to a layout structure of a mask ROM (Read Only Memory).

[0002] A mask ROM includes an array of memory cells, each of which is programmed and manufactured to have a fixed data state. The transistors that make up the memory cells are provided between a bit line and VSS, and the word line is connected to the gate. Bit data "1" or "0" is stored depending on whether the source or drain is connected to the bit line or VSS. The presence or absence of a connection is achieved, for example, by the presence or absence of a contact or via.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved increased integration density, reduced operating voltage, and improved operating speed through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, such as finFETs (field-effect transistors) and nanosheet FETs, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched.

[0004] Patent Document 1 discloses a layout structure of a ROM memory cell using a nanosheet FET.

[0005] International Publication No. 2023 / 157724

[0006] In the mask ROM described in Patent Document 1, at least one of the bit line and the power supply line is provided in a buried wiring layer. The wiring in the buried wiring layer cannot be provided overlapping the transistor (nanosheet). Therefore, the wiring width of the wiring formed in the buried wiring layer cannot be increased, resulting in increased wiring resistance and a decrease in operating speed. Furthermore, increasing the wiring width of the wiring formed in the buried wiring layer increases the area of ​​the mask ROM.

[0007] The present disclosure provides a layout structure for a mask ROM that suppresses a decrease in operating speed without increasing the area.

[0008] In a first aspect of the present disclosure, a semiconductor memory device comprises a ROM memory cell, a word line extending in a first direction, a bit line extending in a second direction perpendicular to the first direction, and a ground power wiring extending in the second direction, wherein the ROM memory cell comprises a nanosheet FET having a gate connected to the word line and a drain connected to the bit line, and stores data depending on whether or not there is an electrical connection between the source of the nanosheet FET and the ground power wiring, wherein the bit line is formed in a first wiring layer on the surface side of the nanosheet FET and overlaps with the nanosheet FET in a planar view, and the ground power wiring is formed in a second wiring layer on the back side of the nanosheet FET and overlaps with the nanosheet FET in a planar view.

[0009] According to this aspect, the ROM memory cell includes a nanosheet FET whose gate is connected to a word line and whose drain is connected to a bit line. The ROM memory cell stores data based on whether or not the source of the nanosheet FET is electrically connected to a ground power supply wiring. The ground power supply wiring is formed in a second wiring layer on the back side of the nanosheet FET, overlapping the nanosheet FET in a planar view. This allows the wiring width of the ground power supply wiring to be increased without increasing the area of ​​the mask ROM. This reduces the resistance of the ground power supply wiring, thereby improving the operating speed and stability of the mask ROM.

[0010] In a second aspect of the present disclosure, a semiconductor memory device comprises a ROM memory cell, a word line extending in a first direction, a bit line extending in a second direction perpendicular to the first direction, and a ground power wiring extending in the second direction, wherein the ROM memory cell comprises a nanosheet FET having a gate connected to the word line and a drain connected to the bit line, and stores data depending on whether or not there is an electrical connection between the source of the nanosheet FET and the ground power wiring, wherein the ground power wiring is formed in a first wiring layer on the surface side of the nanosheet FET and overlaps with the nanosheet FET in a planar view, and the bit line is formed in a second wiring layer on the back side of the nanosheet FET and overlaps with the nanosheet FET in a planar view.

[0011] According to this aspect, the ROM memory cell includes a nanosheet FET whose gate is connected to a word line and whose drain is connected to a bit line. The ROM memory cell stores data based on whether or not the source of the nanosheet FET is electrically connected to the ground power supply wiring. The bit line is formed in a second wiring layer on the back side of the nanosheet FET, overlapping the nanosheet FET in a planar view. This allows the wiring width of the bit line to be increased without increasing the area of ​​the mask ROM. This reduces the resistance of the bit line, thereby improving the operating speed and stability of the mask ROM.

[0012] In a third aspect of the present disclosure, a semiconductor memory device comprises a ROM memory cell, a word line extending in a first direction, a bit line extending in a second direction perpendicular to the first direction, and a ground power wiring extending in the second direction, wherein the ROM memory cell comprises a nanosheet FET having a gate connected to the word line, a source connected to the bit line or the ground power wiring, and a drain connected to the bit line or the ground power wiring, and data is stored depending on whether the source and drain of the nanosheet FET are connected to the same line or different lines of the bit line and the ground power wiring, wherein the bit line is formed in either a first wiring layer on the surface side of the nanosheet FET or a second wiring layer on the back side of the nanosheet FET, and overlaps with the nanosheet FET in a planar view, and the ground power wiring is formed in the other of the first wiring layer or the second wiring layer, and overlaps with the nanosheet FET in a planar view.

[0013] According to this aspect, the ROM memory cell includes a nanosheet FET whose gate is connected to a word line. The source and drain of the nanosheet FET are connected to a bit line or a ground power wiring. The ROM memory cell stores data depending on whether the source and drain of the nanosheet FET are connected to the same line or different lines among the bit line and the ground power wiring. Here, the bit line or the ground power wiring is formed in a second wiring layer on the back side of the nanosheet FET so as to overlap with the nanosheet FET in a planar view, so that the wiring width of the bit line or the ground power wiring can be increased without increasing the area of ​​the mask ROM. This allows the resistance value of the bit line or the ground power wiring to be reduced, thereby improving the operating speed and operating stability of the mask ROM.

[0014] According to the present disclosure, it is possible to provide a layout structure for a mask ROM that suppresses a decrease in operating speed without increasing the area.

[0015] 2A to 2C are cross-sectional views of the layout structure of FIG. 2. A plan view showing an example of the layout structure of a semiconductor memory device according to a first modification of the first embodiment. A plan view showing an example of the layout structure of a semiconductor memory device according to a second modification of the first embodiment. A plan view showing an example of the layout structure of a semiconductor memory device according to a third modification of the first embodiment. A plan view showing an example of the layout structure of a semiconductor memory device according to a fourth modification of the first embodiment. A circuit diagram showing the configuration of a contact-type mask ROM as an example of a semiconductor memory device according to a second embodiment. A plan view showing an example of the layout structure of a semiconductor memory device according to a first modification of the second embodiment.

[0016] Hereinafter, embodiments will be described with reference to the drawings. In this specification, "VDD" and "VSS" refer to power supply voltages or the power supply itself. In addition, in this specification, the source and drain regions of a transistor are referred to as the "nodes" of the transistor as appropriate. In other words, one node of a transistor refers to the source or drain of the transistor, and both nodes of a transistor refer to the source and drain of the transistor.

[0017] 1 is a circuit diagram showing the configuration of a contact-type mask ROM as an example of a semiconductor memory device. In the mask ROM shown in FIG. 1, whether the source of a memory cell transistor is connected to a ground line VSS via a contact or not corresponds to "0" or "1" in the stored data.

[0018] In FIG. 1, the mask ROM includes a memory cell array 3 , a column decoder 2 , and a sense amplifier 18 .

[0019] The memory cell array 3 is configured by arranging memory cells Mij (i = 0 to m, j = 0 to n) of N-type MOS transistors in a matrix. The gates of the memory cells Mij are connected to word lines WLi in common in the row direction, and the drains are connected to bit lines BLj in common in the column direction. The source of the memory cell Mij is connected to the ground potential VSS when the stored data is set to "0", and is not connected to the ground potential VSS when the stored data is set to "1".

[0020] The column decoder 2 is composed of N-type MOS transistors Cj, whose drains are all connected in common, whose gates are connected to respective column selection signal lines CLj, and whose sources are connected to respective bit lines BLj.

[0021] The sense amplifier 18 includes a precharge P-type MOS transistor 5, an inverter 8 that determines the output data of the memory cell Mij, and an inverter 9 that buffers the output signal of the inverter 8. A precharge signal NPR is input to the gate of the P-type MOS transistor 5, a power supply voltage VDD is supplied to the source, and the drain is connected to the common drain of the N-type MOS transistor Cj. The inverter 8 receives a signal SIN from the common drain of the N-type MOS transistor Cj and determines the output data of the memory cell Mij. The inverter 9 receives an output signal SOUT from the inverter 8 and outputs the stored data of the memory cell Mij.

[0022] The operation of the mask ROM of FIG. 1 will be described by taking as an example the case where data is read from memory cell M00.

[0023] First, among the column selection signal lines CLj, CL0 is set to high level and the other CL1 to CLn are set to low level. As a result, among the transistors constituting the column decoder 2, C0 is turned on and the other C1 to Cn are turned off. Also, the word line WL0 is transitioned from low level, which indicates a non-selected state, to high level, which indicates a selected state.

[0024] Next, the precharge signal NPR is changed from high level to low level, and the precharge P-type MOS transistor 5 is turned on.

[0025] Here, when the source of memory cell M00 is connected to ground potential VSS, the current capability of memory cell M00 is greater than that of precharge P-type MOS transistor 5, and therefore input signal SIN of inverter 8 has a voltage lower than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 is held at a high level, and output signal OUT of inverter 9 is held at a low level.

[0026] On the other hand, when the source of memory cell M00 is not connected to the ground potential VSS, bit line BL0 is charged by precharge P-type MOS transistor 5, and input signal SIN of inverter 8 becomes a voltage higher than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 becomes low level, and output signal OUT of inverter 9 becomes high level.

[0027] That is, when the source of the memory cell is connected to VSS, a low level is output (storage data "0"), and when the source of the memory cell is not connected to VSS, a high level is output (storage data "1").

[0028] In addition, the mask ROM of the present disclosure may store the value of each memory cell by connecting / disconnecting the memory cell to VSS, or by connecting / disconnecting the memory cell to a bit line.

[0029] 2 and 3 are diagrams showing an example of the layout structure of the mask ROM according to the first embodiment, with Fig. 2 being a plan view of the memory cell array and Figs. 3(a) to 3(c) being cross-sectional views in the horizontal direction in a plan view of the memory cell array of Fig. 2. Fig. 3(a) is a cross-section along line X1-X1', Fig. 3(b) is a cross-section along line X2-X2', and Fig. 3(c) is a cross-section along line X3-X3'.

[0030] 2 and other plan views, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). Note that the X direction is the direction in which the gate wiring and word lines extend, and the Y direction is the channel direction and the direction in which the bit lines extend.

[0031] In each drawing of the first embodiment, the letter "D" is attached to the contact that determines the stored value of the memory cell.

[0032] FIG. 2 corresponds to a layout for (2×2) bits. The dashed lines indicate the frame of a memory cell for one bit. That is, FIG. 2 shows a configuration in which two memory cells are arranged in the X direction and two in the Y direction. In the Y direction, the memory cells are arranged in an inverted manner in every other column in the Y direction. In FIG. 2, the two memory cells in the left column of the drawing correspond, from bottom to top, to memory cells M00 and M10 in the circuit diagram of FIG. 1, and the two memory cells in the right column of the drawing correspond, from bottom to top, to memory cells M01 and M11 in the circuit diagram of FIG. 1.

[0033] 2 and 3, power supply wirings 11 and 12 extending in the Y direction are formed in the BM0 wiring layer. The BM0 wiring layer is a wiring layer provided on the back side of the transistors in the semiconductor chip. The power supply wirings 11 and 12 supply VSS.

[0034] In the M1 wiring layer, bit lines 21 and 22 extending in the Y direction are formed. The M1 wiring layer is a wiring layer located above the transistors in the semiconductor chip, i.e., provided on the surface side of the transistors. The bit lines 21 and 22 correspond to bit lines BL0 and BL1, respectively. The power supply wiring 11 and the bit line 21 overlap in a planar view. The power supply wiring 12 and the bit line 22 overlap in a planar view.

[0035] Here, in a semiconductor chip, the back side of a transistor refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the transistor are stacked, and the side on which local wiring, metal wiring, etc. connected to the transistor are stacked is called the front side of the transistor.

[0036] An active region 31 that constitutes the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 11 and below the bit line 21. The active region 31 overlaps the power supply wiring 11 and the bit line 21 in a planar view. The active region 31 includes nanosheets 32a and 32b that become the channel of the N-type nanosheet FET. The active region 31 also includes portions 33a, 33b, and 33c that become the source or drain of the N-type nanosheet FET.

[0037] An active region 35 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 12 and below the bit line 22. The active region 35 overlaps the power supply wiring 12 and the bit line 22 in a planar view. The active region 35 includes nanosheets 36a and 36b that become the channel of the N-type nanosheet FET. The active region 35 also includes portions 37a, 37b, and 37c that become the source or drain of the N-type nanosheet FET.

[0038] Gate wirings 41 and 42 are formed extending in parallel in the X direction. The gate wiring 41 surrounds the outer peripheries of the nanosheets 32a and 36a in the X and Z directions via a gate insulating film (not shown). The gate wiring 42 surrounds the outer peripheries of the nanosheets 32b and 36b in the X and Z directions via a gate insulating film (not shown). That is, the gate wiring 41 corresponds to the word line WL0 and is connected to the gates of the nanosheet FETs provided in the memory cells M00 and M01. The gate wiring 42 corresponds to the word line WL1 and is connected to the gates of the nanosheet FETs provided in the memory cells M10 and M11.

[0039] Dummy gate wirings 43 and 44 are formed to extend in the X direction. The dummy gate wirings 43 and 44 supply VSS.

[0040] Local interconnects 51 and 52 are formed extending in the X direction. In FIG. 2 and other drawings, the local interconnect is denoted as LI. The local interconnect 51 is connected to a portion 33b of the active region 31 that serves as a common drain for the nanosheet FETs provided in the memory cells M00 and M10. The local interconnect 52 is connected to a portion 37b of the active region 35 that serves as a common drain for the nanosheet FETs provided in the memory cells M01 and M11.

[0041] The local wiring 51 is connected to the bit line 21 via a contact 61. The local wiring 52 is connected to the bit line 22 via a contact 62.

[0042] The presence or absence of contacts 71, 72, 73, and 74 determines the stored value of the memory cell. When formed, contact 71 connects portion 33a of active region 31 to power supply wiring 11. When formed, contact 72 connects portion 33c of active region 31 to power supply wiring 11. When formed, contact 73 connects portion 37a of active region 35 to power supply wiring 12. When formed, contact 74 connects portion 37c of active region 35 to power supply wiring 12.

[0043] 2 and 3, in the BM0 wiring layer, the power supply wiring 11, 12 is arranged so as to overlap with the nanosheet FET in a plan view. Therefore, the wiring width of the power supply wiring 11, 12 can be increased, and the wiring resistance is reduced, thereby improving the operating speed and stability of the mask ROM. In addition, an increase in the area of ​​the mask ROM can be suppressed.

[0044] Furthermore, in the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this embodiment, the contacts 71, 72, 73, and 74 for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time for changing the memory value of the memory cell.

[0045] That is, in the method for manufacturing a semiconductor memory device according to the present disclosure, for example, a step of forming word lines, bit lines, and a plurality of nanosheet FETs on a semiconductor substrate is performed, and after this step, contacts for connecting the sources of the nanosheet FETs to ground power wiring are formed on the back side of the plurality of nanosheet FETs according to the data to be stored, and then ground power wiring is formed on the wiring layer on the back side.

[0046] As described above, according to this embodiment, the ROM memory cell is provided between the bit lines 21, 22 and the ground power wiring 11, 12, and includes a nanosheet FET whose gate is connected to the word lines 41, 42 and whose drain is connected to the bit lines 21, 22. The ROM memory cell stores data depending on whether or not the source of the nanosheet FET is electrically connected to the ground power wiring 11, 12. Here, the ground power wiring 11, 12 is formed in the BM0 wiring layer on the back side of the nanosheet FET, overlapping the nanosheet FET in a planar view. This allows the wiring width of the ground power wiring 11, 12 to be increased without increasing the area of ​​the mask ROM. This allows the resistance value of the ground power wiring 11, 12 to be reduced, thereby improving the operating speed and stability of the mask ROM.

[0047] <Modification 1> Fig. 4 is a plan view showing the layout structure of a mask ROM according to Modification 1 of the first embodiment. In this modification, wirings 25a, 25b, and 25c extending in the Y direction are provided in the M1 wiring layer. The wirings 25a, 25b, and 25c supply VSS. The other configurations are the same as those in Fig. 2.

[0048] The wiring 25a, 25b, and 25c function as shield wiring between the bit lines, suppressing crosstalk noise between the bit lines. This improves the stability of the operation of the mask ROM. Furthermore, by connecting the power supply wiring in the BM0 wiring layer and the wiring that supplies VSS in the M1 wiring layer outside the memory cell array, the power supply can be strengthened, thereby improving the operating speed and stability of the mask ROM.

[0049] In FIG. 4, the wirings 25a, 25b, and 25c are arranged at the boundaries of the ROM memory cells, but the positions where they are arranged are not limited to this.

[0050] 5 is a plan view showing the layout structure of a mask ROM according to a second modification of the first embodiment. This modification corresponds to the first embodiment in which the wiring layers of the bit lines and the VSS power supply wiring are interchanged. That is, in this modification, the bit lines are arranged in the BM0 wiring layer, and the VSS power supply wiring is arranged in the M1 wiring layer.

[0051] 5, bit lines 13 and 14 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 13 and 14 correspond to bit lines BL0 and BL1, respectively. Furthermore, power supply lines 23 and 24 extending in the Y direction are formed in the M1 wiring layer. The power supply lines 23 and 24 supply VSS. The bit line 13 and the power supply line 23 overlap in a plan view. The bit line 14 and the power supply line 24 overlap in a plan view.

[0052] The active region 31 overlaps with the bit line 13 and the power supply wiring 23 in a planar view. A portion 33b of the active region 31 is connected to the bit line 13 via a contact 63. The active region 35 overlaps with the bit line 14 and the power supply wiring 24 in a planar view. A portion 37b of the active region 35 is connected to the bit line 14 via a contact 64.

[0053] Local interconnections 53, 54, 55, and 56 are formed extending in the X direction. The local interconnections 53 and 54 are connected to portions 33a and 33c, respectively, of the active region 31. The local interconnections 55 and 56 are connected to portions 37a and 37c, respectively, of the active region 35.

[0054] The presence or absence of contacts 75, 76, 77, and 78 determines the stored value of a memory cell. When formed, contact 75 connects local interconnect 53 and power supply interconnect 23. When formed, contact 76 connects local interconnect 54 and power supply interconnect 23. When formed, contact 77 connects local interconnect 55 and power supply interconnect 24. When formed, contact 78 connects local interconnect 56 and power supply interconnect 24.

[0055] 5, in the BM0 wiring layer, the bit lines 13 and 14 are arranged so as to overlap with the nanosheet FET in a planar view. This allows the wiring width of the bit lines 13 and 14 to be increased, thereby reducing their wiring resistance, thereby improving the operating speed and stability of the mask ROM. In addition, it is possible to suppress an increase in the area of ​​the mask ROM.

[0056] That is, according to this modification, the ROM memory cell is provided between the bit lines 13, 14 and the ground power supply wiring 23, 24, and includes a nanosheet FET whose gate is connected to the word lines 41, 42 and whose drain is connected to the bit lines 13, 14. The ROM memory cell stores data depending on whether or not the source of the nanosheet FET is electrically connected to the ground power supply wiring 23, 24. Here, the bit lines 13, 14 are formed in the BM0 wiring layer on the back side of the nanosheet FET, overlapping the nanosheet FET in a planar view. This allows the wiring width of the bit lines 13, 14 to be increased without increasing the area of ​​the mask ROM. This allows the resistance value of the bit lines 13, 14 to be reduced, thereby improving the operating speed and stability of the mask ROM.

[0057] Furthermore, in this modification, similar to the above-described modification 1, power supply wiring for supplying VSS may be arranged between the bit lines in the BM0 wiring layer. The arranged power supply wiring functions as shield wiring between the bit lines and suppresses crosstalk noise between the bit lines. This improves the stability of the operation of the ROM memory cells.

[0058] <Modification 3> Figure 6 is a plan view showing an example of the layout structure of a mask ROM according to Modification 3 of the first embodiment. In this modification, the transistor of each memory cell is composed of two nanosheet FETs arranged adjacent to each other in the Y direction and sharing a source. That is, similar to Figure 2, Figure 6 shows a configuration in which two memory cells are arranged in the X direction and two in the Y direction. The two memory cells in the left column of the figure correspond, from bottom to top, to memory cells M00 and M10, respectively, in the circuit diagram of Figure 1, and the two memory cells in the right column of the figure correspond, from bottom to top, to memory cells M01 and M11, respectively, in the circuit diagram of Figure 1.

[0059] 6, power supply wirings 111 and 112 extending in the Y direction are formed in the BM0 wiring layer. The power supply wirings 111 and 112 supply VSS. Bit lines 121 and 122 extending in the Y direction are formed in the M1 wiring layer. The bit lines 121 and 122 correspond to the bit lines BL0 and BL1, respectively. The power supply wiring 111 and the bit line 121 overlap in a planar view. The power supply wiring 112 and the bit line 122 overlap in a planar view.

[0060] An active region 131 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 111 and below the bit line 121. The active region 131 overlaps the power supply wiring 111 and the bit line 121 in a planar view. The active region 131 includes nanosheets 132a, 132b, 132c, and 132d that become the channel of the N-type nanosheet FET. The active region 131 also includes portions 133a, 133b, 133c, 133d, and 133e that become the source or drain of the N-type nanosheet FET.

[0061] An active region 135 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 112 and below the bit line 122. The active region 135 overlaps the power supply wiring 112 and the bit line 122 in a planar view. The active region 135 includes nanosheets 136a, 136b, 136c, and 136d that become the channel of the N-type nanosheet FET. The active region 135 also includes portions 137a, 137b, 137c, 137d, and 137e that become the source or drain of the N-type nanosheet FET.

[0062] Gate wirings 141, 142, 143, and 144 are formed extending in parallel in the X direction. Gate wiring 141 surrounds the outer peripheries of nanosheets 132a and 136a in the X and Z directions via a gate insulating film (not shown). Gate wiring 142 surrounds the outer peripheries of nanosheets 132b and 136b in the X and Z directions via a gate insulating film (not shown). Gate wiring 143 surrounds the outer peripheries of nanosheets 132c and 136c in the X and Z directions via a gate insulating film (not shown). Gate wiring 144 surrounds the outer peripheries of nanosheets 132d and 136d in the X and Z directions via a gate insulating film (not shown).

[0063] That is, the gate wirings 141 and 142 correspond to the word line WL0 and are connected to the gates of the nanosheet FETs provided in the memory cells M00 and M01. The gate wirings 143 and 144 correspond to the word line WL1 and are connected to the gates of the nanosheet FETs provided in the memory cells M10 and M11.

[0064] Local interconnections 151, 152, 153, 154, 155, and 156 are formed extending in the X direction. The local interconnection 151 is connected to a portion 133a of the active region 131. The local interconnection 152 is connected to a portion 133c of the active region 131. The local interconnection 153 is connected to a portion 133e of the active region 131. The local interconnection 154 is connected to a portion 137a of the active region 135. The local interconnection 155 is connected to a portion 137c of the active region 135. The local interconnection 156 is connected to a portion 137e of the active region 135.

[0065] The local interconnects 151, 152, and 153 are connected to the bit line 121 via contacts. The local interconnects 154, 155, and 156 are connected to the bit line 122 via contacts.

[0066] The presence or absence of contacts 171, 172, 173, and 174 determines the stored value of a memory cell. When formed, contact 171 connects portion 133b of active region 131 to power supply wiring 111. When formed, contact 172 connects portion 133d of active region 131 to power supply wiring 111. When formed, contact 173 connects portion 137b of active region 135 to power supply wiring 112. When formed, contact 174 connects portion 137d of active region 135 to power supply wiring 112.

[0067] 6, in the BM0 wiring layer, the power supply wiring 111, 112 is arranged so as to overlap with the nanosheet FET in a planar view. Therefore, the wiring width of the power supply wiring 111, 112 can be increased, and the wiring resistance is reduced, thereby improving the operating speed and stability of the mask ROM. In addition, an increase in the area of ​​the mask ROM can be suppressed.

[0068] Furthermore, in the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this modification, the contacts 171, 172, 173, and 174 for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time required to change the memory value of the memory cell.

[0069] 6, the M1 wiring layer is provided with wirings 125a, 125b, and 125c extending in the Y direction. The wirings 125a, 125b, and 125c supply VSS. The wirings 125a, 125b, and 125c function as shield wirings between the bit lines and suppress crosstalk noise between the bit lines. This improves the stability of the operation of the ROM memory cells. Note that the wirings 125a, 125b, and 125c do not necessarily have to be provided.

[0070] 7 is a plan view showing the layout structure of a mask ROM according to Modification 4 of the first embodiment. This modification corresponds to Modification 3, in which the wiring layers of the bit lines and the VSS power supply wiring are swapped. That is, in this modification, the bit lines are arranged in the BM0 wiring layer, and the VSS power supply wiring is arranged in the M1 wiring layer.

[0071] 7, bit lines 113 and 114 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 113 and 114 correspond to bit lines BL0 and BL1, respectively. Furthermore, power supply lines 123 and 124 extending in the Y direction are formed in the M1 wiring layer. The power supply lines 123 and 124 supply VSS. The bit line 113 and the power supply line 123 overlap in a plan view. The bit line 114 and the power supply line 124 overlap in a plan view.

[0072] The active region 131 overlaps with the bit line 113 and the power supply wiring 123 in a planar view. Portions 133a, 133c, and 133e of the active region 131 are connected to the bit line 113 via contacts. The active region 135 overlaps with the bit line 114 and the power supply wiring 124 in a planar view. Portions 137a, 137c, and 137e of the active region 135 overlap with the bit line 114 via contacts in a planar view.

[0073] Local interconnections 157, 158, 159, and 160 are formed extending in the X direction. The local interconnections 157 and 158 are connected to portions 133b and 133d, respectively, of the active region 131. The local interconnections 159 and 160 are connected to portions 137b and 137d, respectively, of the active region 135.

[0074] The presence or absence of contacts 175, 176, 177, and 178 determines the stored value of a memory cell. When formed, contact 175 connects local interconnect 157 to power supply interconnect 123. When formed, contact 176 connects local interconnect 158 ​​to power supply interconnect 123. When formed, contact 177 connects local interconnect 159 to power supply interconnect 124. When formed, contact 178 connects local interconnect 160 to power supply interconnect 124.

[0075] 7, in the BM0 wiring layer, the bit lines 113 and 114 are arranged so as to overlap with the nanosheet FET in a plan view. This allows the wiring width of the bit lines 113 and 114 to be increased, thereby reducing their wiring resistance, thereby improving the operating speed and stability of the mask ROM. In addition, it is possible to suppress an increase in the area of ​​the mask ROM.

[0076] 7, the BM0 wiring layer is provided with wirings 115a, 115b, and 115c extending in the Y direction. The wirings 115a, 115b, and 115c supply VSS. The wirings 115a, 115b, and 115c function as shield wirings between the bit lines and suppress crosstalk noise between the bit lines. This improves the stability of the operation of the ROM memory cells. Note that the wirings 115a, 115b, and 115c do not necessarily have to be provided.

[0077] Second Embodiment Fig. 8 is a circuit diagram showing the configuration of a mask ROM as an example of a semiconductor memory device. In the mask ROM of Fig. 8, whether the source and drain of a memory cell transistor are connected to the same line or different lines out of a bit line and a ground power supply line corresponds to "1" or "0" of stored data.

[0078] 8, the mask ROM includes a memory cell array 3A, a column decoder 2, and a sense amplifier 18.

[0079] The memory cell array 3A is configured by arranging memory cells Mij (i = 0 to m, j = 0 to n) of N-type MOS transistors in a matrix. The gates of the memory cells Mij are connected to word lines WLi in common in the row direction. The source and drain of the memory cell Mij are connected to bit lines BLj or to a ground power supply wiring VSS. When the data stored in the memory cell Mij is set to "0", one of the source and drain is connected to the bit line BLj and the other is connected to the ground power supply wiring VSS. On the other hand, when the data stored in the memory cell Mij is set to "1", both the source and drain are connected to the bit line BLj or the ground power supply wiring VSS.

[0080] The column decoder 2 is composed of N-type MOS transistors Cj, whose drains are all connected in common, whose gates are connected to respective column selection signal lines CLj, and whose sources are connected to respective bit lines BLj.

[0081] The sense amplifier 18 includes a precharge P-type MOS transistor 5, an inverter 8 that determines the output data of the memory cell Mij, and an inverter 9 that buffers the output signal of the inverter 8. A precharge signal NPR is input to the gate of the P-type MOS transistor 5, a power supply voltage VDD is supplied to the source, and the drain is connected to the common drain of the N-type MOS transistor Cj. The inverter 8 receives a signal SIN from the common drain of the N-type MOS transistor Cj and determines the output data of the memory cell Mij. The inverter 9 receives an output signal SOUT from the inverter 8 and outputs the stored data of the memory cell Mij.

[0082] The operation of the mask ROM shown in Fig. 8 will be described below, taking as an example the case where data is read from memory cells M00 and M10.

[0083] First, among the column selection signal lines CLj, CL0 is set to high level and the other CL1 to CLn are set to low level. As a result, among the transistors constituting the column decoder 2, C0 is turned on and the other C1 to Cn are turned off. Also, the word line WL0 is transitioned from low level, which indicates a non-selected state, to high level, which indicates a selected state.

[0084] Next, the precharge signal NPR is changed from high level to low level, and the precharge P-type MOS transistor is turned on.

[0085] One of the source and drain of memory cell M00 is connected to bit line BL0, and the other is connected to ground power supply wiring VSS. Therefore, current flows from bit line BL0 to ground power supply wiring VSS via memory cell M00, and input signal SIN of inverter 8 becomes a voltage lower than the switching level of inverter 8. Therefore, output signal SOUT of inverter 8 remains high, and output signal OUT of inverter 9 remains low.

[0086] When data in the memory cell M10 is to be read, the word line WL1 is transitioned from a low level indicating a non-selected state to a high level indicating a selected state.

[0087] Both the source and drain of memory cell M10 are connected to bit line BL0. Therefore, no current flows through bit line BL0, and input signal SIN of inverter 8 becomes a voltage higher than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 becomes low level, and output signal OUT of inverter 9 becomes high level.

[0088] That is, when one of the source and drain of the memory cell is connected to a bit line and the other is connected to a ground power supply wiring, a low level is output (storage data "0"), and when both the source and drain of the memory cell are connected to a bit line or a ground power supply wiring, a high level is output (storage data "1").

[0089] FIG. 9 is a diagram showing an example of the layout structure of a mask ROM according to the second embodiment, and is a plan view of a memory cell array. FIG. 9 corresponds to a layout for (2×4) bits. Dashed lines indicate the frame of a memory cell for one bit. That is, FIG. 9 shows a configuration in which memory cells are arranged two in the X direction and four in the Y direction. For example, the two memory cells in the bottom row of the drawing correspond to memory cells M00 and M01 in the circuit diagram of FIG. 8, and the two memory cells in the row above them correspond to memory cells M10 and M11 in the circuit diagram of FIG. 8.

[0090] In the configuration of Figure 9, each memory cell is composed of one nanosheet FET. Note that the memory cell may have two or more nanosheet FETs. Furthermore, the cross-sectional structure is the same as that of the first embodiment and can be easily inferred from the cross-sectional view of Figure 3, etc., so the cross-sectional view is omitted here.

[0091] 9 , power supply wiring 211 and 212 extending in the Y direction are formed in the BM0 wiring layer. The power supply wiring 211 and 212 supply VSS. Bit lines 221 and 222 extending in the Y direction are formed in the M1 wiring layer. The bit lines 221 and 222 correspond to the bit lines BL0 and BL1, respectively. The power supply wiring 211 and the bit line 221 overlap in a planar view. The power supply wiring 212 and the bit line 222 overlap in a planar view.

[0092] An active region 231 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 211 and below the bit line 221. The active region 231 overlaps the power supply wiring 211 and the bit line 221 in a planar view. The active region 231 includes nanosheets 232a, 232b, 232c, and 232d that become the channel of the N-type nanosheet FET. The active region 231 also includes portions 233a, 233b, 233c, 233d, and 233e that become the source or drain of the N-type nanosheet FET.

[0093] An active region 235 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 212 and below the bit line 222. The active region 235 overlaps the power supply wiring 212 and the bit line 222 in a planar view. The active region 235 includes nanosheets 236a, 236b, 236c, and 236d that become the channel of the N-type nanosheet FET. The active region 235 also includes portions 237a, 237b, 237c, 237d, and 237e that become the source or drain of the N-type nanosheet FET.

[0094] Gate wirings 241, 242, 243, and 244 are formed extending in parallel in the X direction. The gate wiring 241 surrounds the outer peripheries of the nanosheets 232a and 236a in the X and Z directions via a gate insulating film (not shown). The gate wiring 242 surrounds the outer peripheries of the nanosheets 232b and 236b in the X and Z directions via a gate insulating film (not shown). The gate wiring 243 surrounds the outer peripheries of the nanosheets 232c and 236c in the X and Z directions via a gate insulating film (not shown). The gate wiring 244 surrounds the outer peripheries of the nanosheets 232d and 236d in the X and Z directions via a gate insulating film (not shown). That is, the gate wirings 241, 242, 243, and 244 correspond to the word lines WL0, WL1, WL2, and WL3, respectively.

[0095] Local wirings 251a, 251b, 251c, 251d, 251e, 252a, 252b, 252c, 252d, and 252e are formed extending in the X direction. The local wirings 251a, 251b, 251c, 251d, and 251e are connected to portions 233a, 233b, 233c, 233d, and 233e, respectively, of the active region 231. The local wirings 252a, 252b, 252c, 252d, and 252e are connected to portions 237a, 237b, 237c, 237d, and 237e, respectively, of the active region 235.

[0096] Contacts 261, 262, 263, 264, and 265 connect the VSS power supply wiring in the BM0 wiring layer to the active region. Contacts 271, 272, 273, 274, and 275 connect the local wiring to the bit lines in the M1 wiring layer. Contacts 261, 262, 263, 264, and 265 and contacts 271, 272, 273, 274, and 275 determine the memory value of the memory cell. That is, each memory cell stores data "1" when both nodes are connected to the VSS power supply wiring via contacts or when both nodes are connected to the bit lines via contacts. On the other hand, each memory cell stores data "0" when one node is connected to the VSS power supply wiring via contacts and the other node is connected to the bit line via contacts.

[0097] 9 , memory cell M00 has one node connected to VSS power supply line 211 in the BM0 wiring layer via contact 261, and the other node connected to bit line 221 in the M1 wiring layer via contact 271, and therefore stores data "0." Memory cell M10 has both nodes connected to bit line 221 in the M1 wiring layer via contacts 271 and 272, and therefore stores data "1." Memory cell M01 has one node connected to bit line 222 in the M1 wiring layer via contact 273, and the other node connected to VSS power supply line 212 in the BM0 wiring layer via contact 264, and therefore stores data "0." Memory cell M11 has one node connected to VSS power supply line 212 in the BM0 wiring layer via contact 264, and therefore stores data "0."

[0098] 9, in the BM0 wiring layer, the power supply wiring 211, 212 is arranged so as to overlap with the nanosheet FET in a planar view. Therefore, the wiring width of the power supply wiring 211, 212 can be increased, which reduces the wiring resistance and improves the operating speed and stability of the mask ROM. In addition, it is possible to suppress an increase in the area of ​​the mask ROM.

[0099] 9, the M1 wiring layer is provided with wirings 225a, 225b, and 225c extending in the Y direction. The wirings 225a, 225b, and 225c supply VSS. The wirings 225a, 225b, and 225c function as shield wiring between the bit lines and suppress crosstalk noise between the bit lines. This improves the stability of the operation of the mask ROM. Note that the wirings 225a, 225b, and 225c do not necessarily have to be provided.

[0100] As described above, according to this embodiment, the ROM memory cell is provided between the bit lines 221, 222 and the ground power wiring 211, 212, and includes a nanosheet FET whose gate is connected to the word lines 241, 242, 243, 244. The source and drain of the nanosheet FET are connected to the bit lines 221, 222 or the ground power wiring 211, 212. The ROM memory cell stores data depending on whether the source and drain of the nanosheet FET are connected to the same or different bit lines or ground power wiring. Here, the ground power wiring 211, 212 is formed in the BM0 wiring layer on the back side of the nanosheet FET, overlapping the nanosheet FET in a planar view. This allows the wiring width of the ground power wiring 211, 212 to be increased without increasing the area of ​​the mask ROM. This allows the resistance value of the ground power wiring 211, 212 to be reduced, thereby improving the operating speed and stability of the mask ROM.

[0101] 10 is a plan view showing the layout structure of a mask ROM according to a first modification of the second embodiment. This modification corresponds to the second embodiment in which the wiring layers of the bit lines and the VSS power supply wiring are interchanged. That is, in this modification, the bit lines are arranged in the BM0 wiring layer, and the VSS power supply wiring is arranged in the M1 wiring layer.

[0102] 10, bit lines 213 and 214 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 213 and 214 correspond to bit lines BL0 and BL1, respectively. Furthermore, power supply lines 223 and 224 extending in the Y direction are formed in the M1 wiring layer. The power supply lines 223 and 224 supply VSS. The bit line 213 and the power supply line 223 overlap in a planar view. The bit line 214 and the power supply line 224 overlap in a planar view.

[0103] The active region 231 overlaps with the bit line 213 and the power supply wiring 223 in a planar view. The active region 235 overlaps with the bit line 214 and the power supply wiring 224 in a planar view. The local wirings 251a, 251b, 251c, 251d, and 251e are connected to portions 233a, 233b, 233c, 233d, and 233e of the active region 231, respectively. The local wirings 252a, 252b, 252c, 252d, and 252e are connected to portions 237a, 237b, 237c, 237d, and 237e of the active region 235, respectively.

[0104] Contacts 281, 282, 283, 284, and 285 connect bit lines in the BM0 wiring layer to the active regions. Contacts 291, 292, 293, 294, and 295 connect local wiring to VSS power supply wiring in the M1 wiring layer. Contacts 281, 282, 283, 284, and 285 and contacts 291, 292, 293, 294, and 295 determine the memory value of the memory cell. That is, each memory cell stores data "1" when both nodes are connected to the VSS power supply wiring via contacts or when both nodes are connected to the bit line BL via contacts. On the other hand, each memory cell stores data "0" when one node is connected to the VSS power supply wiring via contacts and the other node is connected to the bit line BL via contacts.

[0105] 10 , memory cell M00 has one node connected to VSS power supply line 223 in the M1 wiring layer via contact 291, and the other node connected to bit line 213 in the BM0 wiring layer via contact 281, and therefore stores data "0." Memory cell M10 has both nodes connected to bit line 213 in the BM0 wiring layer via contacts 281 and 282, and therefore stores data "1." Memory cell M01 has one node connected to bit line 214 in the BM0 wiring layer via contact 283, and the other node connected to VSS power supply line 224 in the M1 wiring layer via contact 294, and therefore stores data "0." Memory cell M11 has one node connected to VSS power supply line 224 in the M1 wiring layer via contact 294, and the other node connected to bit line 214 in the BM0 wiring layer via contact 284, and therefore stores data "0."

[0106] 10, in the BM0 wiring layer, the bit lines 213 and 214 are arranged so as to overlap with the nanosheet FET in a planar view. Therefore, the wiring width of the bit lines 213 and 214 can be increased, and the wiring resistance is reduced, thereby improving the operating speed and stability of the mask ROM. In addition, an increase in the area of ​​the mask ROM can be suppressed.

[0107] 10, the BM0 wiring layer is provided with wirings 215a, 215b, and 215c extending in the Y direction. The wirings 215a, 215b, and 215c supply VSS. The wirings 215a, 215b, and 215c function as shield wirings between the bit lines and suppress crosstalk noise between the bit lines. This improves operational stability. Note that the wirings 215a, 215b, and 215c do not necessarily have to be provided.

[0108] As described above, according to this modification, the ROM memory cell is provided between the bit lines 213 and 214 and the ground power supply wiring 223 and 224, and includes a nanosheet FET whose gate is connected to the word lines 241, 242, 243, and 244. The source and drain of the nanosheet FET are connected to the bit lines 213 and 214 or the ground power supply wiring 223 and 224. The ROM memory cell stores data depending on whether the source and drain of the nanosheet FET are connected to the same or different bit lines and ground power supply wiring. Here, the bit lines 213 and 214 are formed in the BM0 wiring layer on the back side of the nanosheet FET, overlapping the nanosheet FET in a planar view. This allows the wiring width of the bit lines 213 and 214 to be increased without increasing the area of ​​the mask ROM. This reduces the resistance of the bit lines 213 and 214, thereby improving the operating speed and stability of the mask ROM.

[0109] In the above-described embodiment, the nanosheet FET has three overlapping sheets in a planar view, and the cross-sectional shape of the sheets is rectangular, but the number and cross-sectional shape of the nanosheet FET are not limited to this.

[0110] The present disclosure enables the operating speed and stability of a mask ROM to be improved without increasing the area, and is therefore useful for, for example, miniaturizing semiconductor chips and improving their performance.

[0111] 11, 12 Ground power supply wiring 13, 14 Bit lines 21, 22 Bit lines 23, 24 Ground power supply wiring 25a, 25b, 25c Ground power supply wiring 31, 35 Active area 32a, 32b, 36a, 36b Nanosheet 41, 42 Word lines 51, 52, 53, 54, 55, 56 Local wiring 71, 72, 73, 74, 75, 76, 77, 78 Contacts 111, 112 Ground power supply wiring 113, 114 Bit lines 121, 122 Bit lines 123, 124 Ground power supply wiring 131, 135 Active area 141, 142, 143, 144 Word lines 171, 172, 173, 174, 175, 176, 177, 178 Contacts 211, 212 Ground power supply wiring 213, 214 Bit lines 221, 222 Bit lines 223, 224 Ground power supply wiring 231, 235 Active areas 241, 242, 243, 244 Word lines 261, 262, 263, 264, 265 271, 272, 273, 274, 275 Contacts 281, 282, 283, 284, 285 291, 292, 293, 294, 295 Contacts Mij (i=0 to m, j=0 to n) Memory cell BLj Bit line WLi Word line

Claims

1. A semiconductor memory device comprising: a ROM (Read Only Memory) memory cell; a word line extending in a first direction; a bit line extending in a second direction perpendicular to the first direction; and a ground power wiring extending in the second direction, wherein the ROM memory cell comprises a nanosheet FET (Field Effect Transistor) having a gate connected to the word line and a drain connected to the bit line, and stores data depending on whether or not there is an electrical connection between the source of the nanosheet FET and the ground power wiring, wherein the bit line is formed in a first wiring layer on the surface side of the nanosheet FET and overlaps with the nanosheet FET in a planar view, and the ground power wiring is formed in a second wiring layer on the back side of the nanosheet FET and overlaps with the nanosheet FET in a planar view.

2. A semiconductor memory device according to claim 1, wherein the ROM memory cell stores data depending on the presence or absence of a contact connecting the source of the nanosheet FET and the ground power supply wiring.

3. A semiconductor memory device according to claim 1, comprising: a second bit line formed in said first wiring layer and extending in said second direction; and a second ground power supply wiring formed in said first wiring layer, disposed between said bit line and said second bit line, and extending in said second direction.

4. A semiconductor memory device according to claim 1, comprising a second word line extending in the first direction, wherein the ROM memory cell overlaps the bit line and the ground power wiring in a planar view, has a gate connected to the second word line, a drain connected to the bit line, and comprises a second nanosheet FET sharing a source with the nanosheet FET, and stores data depending on whether the source shared by the nanosheet FET and the second nanosheet FET is connected to the ground power wiring.

5. A semiconductor memory device comprising: a ROM (Read Only Memory) memory cell; a word line extending in a first direction; a bit line extending in a second direction perpendicular to the first direction; and a ground power wiring extending in the second direction, wherein the ROM memory cell comprises a nanosheet FET (Field Effect Transistor) having a gate connected to the word line and a drain connected to the bit line, and stores data depending on whether or not there is an electrical connection between the source of the nanosheet FET and the ground power wiring, wherein the ground power wiring is formed in a first wiring layer on the surface side of the nanosheet FET and overlaps with the nanosheet FET in a planar view, and the bit line is formed in a second wiring layer on the back side of the nanosheet FET and overlaps with the nanosheet FET in a planar view.

6. A semiconductor memory device according to claim 5, wherein the ROM memory cell includes a first local wiring extending in the first direction and connected to the source of the nanosheet FET, and stores data depending on the presence or absence of a contact connecting the first local wiring to the ground power supply wiring.

7. A semiconductor memory device according to claim 5, comprising: a second bit line formed in said second wiring layer and extending in said second direction; and a second ground power supply wiring formed in said second wiring layer, disposed between said bit line and said second bit line, and extending in said second direction.

8. A semiconductor memory device according to claim 5, further comprising a second word line extending in the first direction, wherein the ROM memory cell overlaps the bit line and the ground power wiring in a planar view, has a gate connected to the second word line, a drain connected to the bit line, and a second nanosheet FET sharing a source with the nanosheet FET, and stores data depending on whether or not there is an electrical connection between the source shared by the nanosheet FET and the second nanosheet FET and the ground power wiring.

9. A semiconductor memory device comprising: a ROM (Read Only Memory) memory cell; a word line extending in a first direction; a bit line extending in a second direction perpendicular to the first direction; and a ground power wiring extending in the second direction; wherein the ROM memory cell comprises a nanosheet FET (Field Effect Transistor) having a gate connected to the word line, a source connected to the bit line or the ground power wiring, and a drain connected to the bit line or the ground power wiring, and data is stored depending on whether the source and drain of the nanosheet FET are connected to the same line or different lines of the bit line and the ground power wiring; the bit line is formed in either a first wiring layer on the front side of the nanosheet FET or a second wiring layer on the back side of the nanosheet FET, and overlaps with the nanosheet FET in a planar view; and the ground power wiring is formed in the other of the first wiring layer or the second wiring layer, and overlaps with the nanosheet FET in a planar view.

10. A semiconductor memory device according to claim 9, wherein the bit lines are formed in the first wiring layer, and the ground power supply wiring is formed in the second wiring layer.

11. A semiconductor memory device according to claim 10, comprising: a second bit line formed in the first wiring layer and extending in the second direction; and a second ground power supply wiring formed in the first wiring layer, disposed between the bit line and the second bit line, and extending in the second direction.

12. A semiconductor memory device according to claim 9, wherein the ground power supply wiring is formed in the first wiring layer, and the bit line is formed in the second wiring layer.

13. A semiconductor memory device according to claim 12, comprising: a second bit line formed in the second wiring layer and extending in the second direction; and a second ground power supply wiring formed in the second wiring layer, disposed between the bit line and the second bit line, and extending in the second direction.

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