Semiconductor device and manufacturing method therefor

Abstract

The present application provides a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a semiconductor epitaxial layer, wherein a plurality of semiconductor units are arranged on the semiconductor epitaxial layer; each semiconductor unit comprises a plurality of cells adjacent to each other, and each cell comprises a first doped region and a second doped region; the first doped region comprises a primary body region and a plurality of secondary body regions; the primary body region has a plurality of vertexes, and each vertex is connected to one secondary body region; each secondary body region extends from a vertex to a center point between the vertex and a correspondingly adjacent vertex, and is connected to a corresponding secondary body region extending from the correspondingly adjacent vertex; the second doped region is arranged in the primary body region; the second doped region and the first doped region have different conductivity types. In the semiconductor device, the reverse voltage of the semiconductor device is effectively increased, and the on-resistance is effectively reduced.

Description

Semiconductor device and method of manufacturing the same TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] As a core component in power electronic systems, power semiconductor devices have been an important electronic component indispensable to modern life, and are widely used in consumer electronics, automotive electronic systems, smart grids, various industrial equipment, locomotives, aerospace, and ship systems. Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs) have become mainstream devices in the high-voltage and high-frequency field due to their high input impedance, good temperature stability, excellent high-frequency and high-voltage performance, and large safe operating area.

[0003] In existing SiC MOSFET devices, it is necessary to further improve the current density of SiC MOSFETs and reduce the on-resistance. One way is to adjust the cell design and use a polygonal cell shape design to reduce the on-resistance by increasing the channel density. However, in this way, the electric field intensity at the top corners of the polygon is large, which leads to a decrease in reverse withstand voltage. In order to meet the reverse withstand voltage, the parameters of the epitaxy or implantation need to be adjusted, which leads to an increase in on-resistance. TECHNICAL SOLUTION

[0004] The semiconductor device and the method of manufacturing the same provided by the present application aim to solve the problems of low reverse withstand voltage and large on-resistance in existing semiconductor devices.

[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a semiconductor device, comprising a semiconductor epitaxial layer, wherein a plurality of semiconductor units are arranged on the semiconductor epitaxial layer; the semiconductor unit comprises a plurality of adjacent cells, and each cell comprises:

[0006] a first doped region extending from a first surface of the semiconductor epitaxial layer to the inside of the semiconductor epitaxial layer; the first doped region comprises a main body region and a plurality of auxiliary body regions; the main body region has a plurality of top corners, and the auxiliary body regions extend along the top corners to the center points between the corresponding adjacent top corners and are connected with the corresponding auxiliary body regions extending from the corresponding adjacent top corners;

[0007] a second doped region arranged in the main body region and extending from the first surface of the semiconductor epitaxial layer to the inside of the semiconductor epitaxial layer; the second doped region has a different conductivity type from the first doped region;

[0008] The second doped region is annular, and is spaced apart from the edge of the main region, and the radial distance between the second doped region and the edge of the main region is greater than the width of the fourth doped region.

[0009] To solve the above technical problems, another technical solution adopted by the present application is: a semiconductor device includes a semiconductor epitaxial layer; the semiconductor epitaxial layer includes:

[0010] a plurality of cells; the plurality of cells are arranged in a two-dimensional array; the plurality of cells have a JFET region therebetween; the cell has a plurality of top corners; each of the cells includes:

[0011] a first doped region extending from a first surface of the semiconductor epitaxial layer towards the interior of the semiconductor epitaxial layer;

[0012] a second doped region disposed in the first doped region, and the second doped region extends from the first surface of the semiconductor epitaxial layer towards the interior of the semiconductor epitaxial layer; the second doped region is different from the first doped region in conductivity type;

[0013] a fourth doped region disposed on the JFET region; the fourth doped region extends from the surface of the semiconductor epitaxial layer towards the interior of the semiconductor epitaxial layer; and the center region of the JFET region contains the center of the fourth doped region;

[0014] The fourth doped region extends from the center region of the JFET region to the adjacent top corner of the adjacent cell and is connected with the first doped region; the fourth doped region is the same as the first doped region in conductivity type;

[0015] The second doped region is annular, and is spaced apart from the edge of the main region, and the radial distance between the second doped region and the edge of the main region is greater than the width of the fourth doped region.

[0016] To solve the above technical problems, another technical solution adopted by the present application is: a semiconductor device includes a semiconductor epitaxial layer; the semiconductor epitaxial layer includes:

[0017] forming a first mask layer on a first surface of a semiconductor epitaxial layer;

[0018] patterning the first mask layer to form a plurality of first openings; the first openings include a main opening and a sub-opening, the sidewall of the main opening has a corner, and the sub-opening is communicated with the corner of the main opening;

[0019] lightly doping the first surface of the semiconductor epitaxial layer exposed by the first opening to form a first doped region; the first doped region comprises a main body region and a sub-body region; the main body region has a top corner, and the sub-body region is connected with the top corner;

[0020] forming a polysilicon layer with a thickness of 0.1-1um on the first surface side of the semiconductor epitaxial layer to form a second mask layer; the second mask layer covers the patterned first mask layer and the first doped region; the polysilicon layer comprises a first polysilicon layer covering the top surface of the patterned first mask layer, a second polysilicon layer covering the side surface of the first opening, and a third polysilicon layer covering the main body region of the first doped region; the thickness of the second polysilicon layer is greater than the width of the sub-opening;

[0021] patterning the second mask layer to form a plurality of second openings; the projection of the second opening on the first doped region is located in the main body region;

[0022] heavily doping at least part of the first doped region exposed by the second opening to form a second doped region; the thickness of the second doped region is less than the thickness of the first doped region; the second doped region is different from the first doped region in conductivity type; the second doped region is annular;

[0023] removing the patterned first mask layer and the patterned second mask layer. Advantages

[0024] Different from the prior art, the application provides a semiconductor device, which comprises a semiconductor epitaxial layer, and a plurality of semiconductor units are arranged on the semiconductor epitaxial layer; the semiconductor unit comprises a plurality of cells adjacent to each other, each cell comprises a first doped region and a second doped region; wherein the first doped region extends from a first surface of the semiconductor epitaxial layer to the inside of the semiconductor epitaxial layer; the first doped region comprises a main body region and a plurality of auxiliary body regions; the main body region has a plurality of top corners, the auxiliary body region extends to the center point between the corresponding adjacent top corners along the top corner, and is connected with the corresponding auxiliary body region extended by the corresponding adjacent top corner; the second doped region is arranged in the main body region, and the second doped region extends from the first surface of the semiconductor epitaxial layer to the inside of the semiconductor epitaxial layer; the second doped region is different from the first doped region in the type of electric conduction; the third doped region is arranged in the main body region, and the third doped region extends from the first surface of the semiconductor epitaxial layer to the inside of the semiconductor epitaxial layer; the third doped region is connected with the second doped region; wherein the second doped region is annular, the second doped region is arranged at a distance from the edge of the main body region, and the radial distance between the second doped region and the edge of the main body region is greater than the width of the auxiliary body region. By arranging the main body region and the auxiliary body region in the first doped region, and connecting the top corner of the main body region with the auxiliary body region, the channel length of the cell at the top corner is increased, the electric field intensity at the top corner is reduced, and the reverse withstand voltage of the semiconductor device is effectively improved; at the same time, by connecting the auxiliary body regions of the adjacent cells in the diagonal direction with each other, the P-type injection of the center of the field effect transistor in the diagonal direction is increased, the electric field intensity of the center of the JFET in the diagonal direction is reduced, and the reverse withstand voltage of the semiconductor device is further improved; in this way, by improving the reverse withstand voltage of the semiconductor device, the situation that the on-resistance rises is avoided, and the on-resistance is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] Fig. 1 is a structural schematic diagram of a semiconductor device provided by the first embodiment of the application;

[0026] Fig. 2 is a sectional view of the semiconductor device shown in Fig. 1 along the line A-A;

[0027] Fig. 3a is a structural schematic diagram of a semiconductor device provided by the second embodiment of the application;

[0028] Fig. 3b is a structural schematic diagram of a semiconductor device provided by the third embodiment of the application;

[0029] Fig. 4 is a structural schematic diagram of a semiconductor device provided by the fourth embodiment of the application;

[0030] Fig. 5 is a flow chart of a preparation method of a semiconductor device provided by an embodiment of the application;

[0031] Fig. 6 is a structural schematic diagram of step S1 shown in Fig. 5;

[0032] Fig. 7a is a structural schematic diagram of step S2 shown in Fig. 5;

[0033] Fig. 7b is a top view of the structure shown in Fig. 7a;

[0034] Fig. 8a is a structural schematic diagram of step S3 shown in Fig. 5;

[0035] Fig. 8b is a top view of the structure shown in Fig. 8a;

[0036] Fig. 9 is a structural schematic diagram of step S4 shown in Fig. 5;

[0037] Fig. 10a is a structural schematic diagram of step S5 shown in Fig. 5;

[0038] Fig. 10b is a top view of the structure shown in Fig. 10a;

[0039] Fig. 11 is a structural schematic diagram of step S6 shown in Fig. 5;

[0040] Fig. 12 is a structural schematic diagram of step S7 shown in Fig. 5;

[0041] Fig. 13 is a structural schematic diagram of forming a third doped region.

[0042] Explanation of reference numerals:

[0043] 100 - semiconductor epitaxial layer; 1 - semiconductor unit; 2 - cell; 3 - first mask layer; 4 - second mask layer; 5 - third mask layer; 6 - gate structure; 7 - insulating layer; 8 - source layer; 9 - drain layer; 10 - first surface; 21 - first doped region; 22 - second doped region; 23 - third doped region; 30 - first opening; 31 - shielding layer; 32 - support layer; 40 - second opening; 41 - first polysilicon layer; 42 - second polysilicon layer; 43 - third polysilicon layer; 211 - main body region; 212 - auxiliary body region; 301 - main opening; 302 - auxiliary opening; 2111 - first part; 2112 - second part; 2120 - fourth doped region; 2111a - top corner; 2111b - side part; 2120a - extension part. Embodiment of the present application

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0045] The terms "first", "second", "third", etc. in the present application are only for descriptive purpose and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.

[0046] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive or alternative embodiments. It is explicitly and implicitly understood that the embodiments described herein can be combined with other embodiments.

[0047] The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0048] Referring to FIGS. 1-2, FIG. 1 is a structural schematic diagram of a semiconductor device provided by a first embodiment of the present application; and FIG. 2 is a sectional view of the semiconductor device shown in FIG. 1 along line A-A. The present application provides a semiconductor device, which can include a semiconductor epitaxial wafer including a substrate and a semiconductor epitaxial layer 100 disposed on a surface of the substrate, and a plurality of semiconductor units 1 disposed on the semiconductor epitaxial layer 100; wherein the semiconductor unit 1 can include a plurality of cells 2 adjacent to each other. Specifically, a side surface of the semiconductor epitaxial layer 100 away from the substrate is a first surface 10. Wherein the semiconductor epitaxial layer 100 can be a SiC N-type epitaxial layer, the thickness thereof can be 5-60um, the doping concentration of the semiconductor epitaxial layer 100 can be 1x1018-2x1019cm-3, and the doping type thereof can be N-type. The semiconductor epitaxial layer 100 can be formed by epitaxial growth on the substrate. 15 cm -3 10 16 cm -3 ; and the cell 2 can include a first doped region 21 and a second doped region 22.

[0049] As shown in FIG. 2, the first doped region 21 extends from the first surface 10 of the semiconductor epitaxial layer 100 towards the interior of the semiconductor epitaxial layer 100. Specifically, in combination with FIG. 1 and FIG. 2, the first doped region 21 can further include a main body region 211 and a plurality of sub-body regions 212; the main body region 211 has a plurality of vertices, each sub-body region 212 is connected with adjacent vertices; and the sub-body region 212 extends along the vertex to the center point between the corresponding adjacent vertices, and is connected with the corresponding sub-body region 212 extending from the corresponding adjacent vertices. The first doped region 21 can be of a second conductivity type.

[0050] The second doped region 22 is disposed in the main body region 211; and the second doped region 22 extends from the first surface 10 of the semiconductor epitaxial layer 100 towards the interior of the semiconductor epitaxial layer 100; specifically, the second doped region 22 covers part of the main body region 211, and the projection of the second doped region 22 on the first doped region 21 in the thickness direction Z is located in the main body region 211. The second doped region 22 is of a different conductivity type from the first doped region 21; specifically, the second doped region 22 can be of a first conductivity type.

[0051] The second doped region 22 is annular and is spaced apart from the edge of the main body region 211; the outer contour thereof is the same as the shape of the main body region 211, and the corners of the second doped region 22 are arc-shaped to further reduce the electric field strength. The radial distance b between the second doped region 22 and the edge of the main body region 211 is greater than the width c of the sub-body region 212, so that the sub-body region 212 can be completely covered by the second polysilicon layer 42 in the process, avoiding the situation that ions are implanted into the sub-body region 212 in the preparation process of forming the second doped region 22.

[0052] Specifically, by providing that the first doped region 21 includes the main body region 211 and the sub-body region 212, and connecting the vertices of the main body region 211 with the sub-body region 212, the channel length of the cell 2 at the vertices is increased, the electric field strength at the vertices is reduced, and the reverse withstand voltage of the semiconductor device is effectively improved; at the same time, by connecting the sub-body regions 212 of the adjacent cells in the diagonal direction with each other, the P-type implantation of the center of the Junction Field-Effect Transistor (JFET) in the diagonal direction is increased, the electric field strength of the center of the JFET in the diagonal direction is reduced, and the reverse withstand voltage of the semiconductor device is further improved; in this way, by improving the reverse withstand voltage of the semiconductor device, the situation of the on-resistance rising is avoided, and the on-resistance is effectively reduced.

[0053] As shown in FIG. 1, in specific embodiments, the main body region 211 is polygonal; it can be understood that setting the main body region 211 of the first doped region 21 to be polygonal can effectively increase the channel density, thereby reducing the on-resistance. Specifically, the polygon has at least four sides, and can be any one of a square, a rectangle, a hexagon, and an octagon, etc. Preferably, the polygon is a regular polygon.

[0054] The main body region 211 has a plurality of vertices, the number of the sub-body regions 212 is a plurality, and each of the plurality of sub-body regions 212 corresponds to one of the plurality of vertices, and the plurality of sub-body regions 212 are arranged along the circumferential direction of the main body region 211 to surround the main body region 211; each vertex is connected with one sub-body region 212, thereby increasing the channel length at each vertex, effectively reducing the electric field strength at the vertex, and further effectively improving the reverse withstand voltage of the semiconductor device.

[0055] As shown in FIG. 1, in specific embodiments, the sub-body region 212 extends along the diagonal of the polygon, and the sub-body regions 212 of the opposite two vertices of the two polygons adjacent along the diagonal direction of the polygon are connected with each other; to further increase the channel length at the vertex, thereby further improving the reverse withstand voltage of the semiconductor device. Specifically, the plurality of cells 2 are arranged in a two-dimensional array; wherein the main body region 211 can be a quadrilateral, and in this embodiment, the main body region 211 is a square and has four vertices; it can be understood that each cell 2 also has four sub-body regions 212 connected with the four vertices respectively. Wherein each sub-body region 212 extends along the diagonal of the corresponding vertex from the vertex of the main body region 211 to the direction away from the main body region 211, and is connected with the sub-body region 212 of the opposite vertex in the adjacent cell 2 along the diagonal direction; to increase the channel length at the vertex, thereby improving the reverse withstand voltage of the semiconductor device.

[0056] Of course, in other embodiments, the shape of the main body region 211 can also be set to a rectangle, a regular hexagon, or a regular octagon, etc., as long as the different input capacitances (Ciss), output capacitances (Coss), and feedback capacitances (Crss) are adjusted to be applied to different scenarios; the specific parameters can be referred to the prior art, which will not be described here.

[0057] In combination with FIG. 1 and FIG. 2, in specific embodiments, the cell 2 can further include a third doped region 23; the third doped region 23 is arranged in the main body region 211, and the third doped region 23 extends from the first surface 10 of the semiconductor epitaxial layer 100 to the inside of the semiconductor epitaxial layer 100; specifically, in the plane perpendicular to the stacking direction Z, the third doped region 23 is connected with the second doped region, and covers another part of the main body region 211. Wherein the third doped region 23 has the same conductivity type as the first doped region 21, specifically, the third doped region 23 can be of the second conductivity type, and the ion doping concentration of the third doped region 23 is greater than the ion doping concentration of the first doped region 21.

[0058] The second doped region 22 is arranged around the circumferential periphery of the third doped region 23; specifically, the annular second doped region 22 is arranged around the center of the cell 2, and the third doped region 23 is arranged in the central part surrounded by the second doped region 22.

[0059] The first doped region 21 can be understood as a well region of the semiconductor device, the second doped region 22 can be understood as a source region of the semiconductor device, and the third doped region 23 can be understood as a well contact region of the semiconductor device.

[0060] The main body region 211 further includes a first part 2111 not covered by the second doped region 22 and not covered by the third doped region 23, and a second part 2112 covered by the second doped region 22 and the third doped region 23. The first part 2111 is annular and arranged around the circumferential periphery of the second doped region 22, and is located between the edge of the main body region 211 and the edge of the second doped region 22. Specifically, the first part 2111 includes a plurality of top corners 2111a and a side part 2111b connecting the plurality of top corners 2111a; it can be understood that when the main body region 211 is quadrilateral, the first part includes four top corners 2111a and four side parts 2111b connecting the four top corners 2111a.

[0061] As shown in FIG. 1, the width a of each top corner 2111a in the first direction X is greater than the width b of the side part 2111b, so as to increase the channel length of the cell 2 at the top corner, so that the electric field strength at the top corner is reduced, effectively improving the reverse withstand voltage of the semiconductor device. The first direction X is the extension direction of the diagonal of the main body region 211.

[0062] In specific embodiments, the width c of each sub-body region 212 is less than or equal to twice the width b of the side part 2111b. In combination with FIG. 10b, it can be understood by those skilled in the art that in the process of masking and implanting to form the second doped region 22, the side part 2111b and the sub-body region 212 need to be covered by the second polysilicon layer 42, and the second polysilicon layer 42 is formed by growing polysilicon on the surface of the semiconductor epitaxial layer 100 and the surface of the first mask layer 3; therefore, the width c of the sub-body region 212 needs to be less than or equal to twice the width b of the side part 2111b, so that the sub-body region 212 can be completely covered by the second polysilicon layer 42 in the process, avoiding the situation that ions are implanted into the sub-body region 212 in the preparation process of implanting to form the second doped region 22.

[0063] Specifically, in combination with FIG. 1 and FIG. 2, the width d of the second doped region 22 is greater than 0.5 um; for example, the width d of the second doped region 22 can be any value among 0.5 um, 0.8 um, 1 um, 1.2 um and 1.5 um. The width a of the top corner 2111a along the first direction X is 0.4-1.4 um; for example, the width a of the top corner 2111a along the first direction X can be any value among 0.4 um, 0.5 um, 0.8 um, 1 um and 1.4 um. The width b of the side edge part 2111b is 0.3-1 um; for example, the width b of the side edge part 2111b can be any value among 0.3 um, 0.35 um, 0.5 um, 0.8 um and 1 um. The width c of the sub-body region is less than twice b, and is 0.6-2 um; for example, the width c of the sub-body region can be any value among 0.6 um, 1 um, 1.5 um and 2 um, and can also be different along the diagonal.

[0064] As shown in FIG. 1, in specific embodiments, the semiconductor unit 1 has a JFET region between adjacent cells 2; wherein the connection of the plurality of sub-body regions 212 connected with the plurality of adjacent top corners 2111a in different cells 2 is located in the center region of the JFET region. Preferably, the center of the JFET region is located at the connection of the four sub-body regions 212 connected with the four adjacent top corners 2111a in different cells 2. By arranging the sub-body region 212 in the center region of the JFET region, the P-type implantation of the center of the JFET region can be increased, the electric field intensity of the center of the JFET region in the diagonal direction is reduced, the reverse withstand voltage of the semiconductor device is further improved, and the leakage current is effectively reduced.

[0065] Specifically, the semiconductor unit 1 can include four adjacent cells 2, the cells 2 are arranged in a two-dimensional array, and the main body region 211 is a quadrilateral; wherein each cell 2 can be a quadrilateral and has four top corners 2111a, and the four sub-body regions 212 connected with the four adjacent top corners 2111a in the four cells 2 are connected with each other, and the connection is located in the center region of the JFET region.

[0066] Referring to FIG. 3a, FIG. 3a is a structural schematic diagram of a semiconductor device according to the second embodiment of the present application; in specific embodiments, the semiconductor device is a MOSFET device, and the semiconductor device can further include a gate structure 6, an insulating layer 7, a source layer 8, and a drain layer 9, etc. The gate structure 6 is disposed on the first surface 10 of the semiconductor epitaxial layer 100 and located between two adjacent cells 2 and covers the first doped region 21 of each cell 2, wherein the gate structure 6 includes a gate and a gate dielectric layer wrapping the gate; the insulating layer 7 is disposed on the gate structure 6 and extends to the first surface 10 of the semiconductor epitaxial layer 100 to insulate the gate structure 6 from the source layer 8, and the insulating layer 7 has a gap at a position corresponding to each cell 2 to expose at least part of the third doped region 23 and / or the second doped region 22 in each cell 2; the source layer 8 is disposed on a side of the insulating layer 7 away from the semiconductor epitaxial layer 100 and covers the insulating layer 7, and the source layer 8 is electrically connected to each cell 2 through the gap on the insulating layer 7; and the drain layer 9 is disposed on a side of the semiconductor epitaxial layer 100 away from the source layer 8. The specific structures and functions of the above-mentioned structural elements are the same as or similar to those in the prior art, and for details, please refer to the prior art, which will not be described here.

[0067] The first doped region 21 and the third doped region 23 can be of a second conductivity type, and the second doped region 22 can be of a first conductivity type; the first conductivity type is one of a P-type doped semiconductor or an N-type doped semiconductor, and the second conductivity type is the other of the P-type doped semiconductor or the N-type doped semiconductor. For example, the first doped region 21 can be a P-type lightly doped region to adjust the hole concentration and accurately control the electrical conductivity of the first doped region 21; specifically, the thickness of the first doped region 21 can be 0.8-2 um, and the doping concentration of the first doped region 21 can be 5x10 16 cm -3 -5x10 18 cm -3 . The second doped region 22 can be an N-type heavily doped region to increase the conductivity of the second doped region 22 and improve the current transmission efficiency; specifically, the thickness of the second doped region 22 can be 0.3-1 um, and the doping concentration of the second doped region 22 can be 1x10 19 cm -3 -1x10 20 cm -3 . The third doped region 23 can be a P-type heavily doped region; the thickness thereof can be 0.3-1 um, and the doping concentration of the third doped region 23 can be 1x10 18 cm -3 -1x10 20 cm -3 .

[0068] Of course, in some other embodiments, the first doped region 21 can also be an N-type lightly doped region, the second doped region 22 can be a P-type heavily doped region, and the third doped region 23 can be an N-type heavily doped region.

[0069] Referring to FIG. 3b, FIG. 3b is a structural schematic diagram of a semiconductor device provided by a third embodiment of the present application; the structure of the semiconductor device provided by the third embodiment of the present application is basically the same as that of the semiconductor device provided by the first embodiment of the present application, and the difference lies in that, in the third embodiment of the present application, the semiconductor unit 1 includes three cells 2 adjacent to each other, the cells 2 are arranged in a two-dimensional array, and the main body region 211 is a hexagon. Specifically, each cell 2 can be a hexagon and has six vertexes, the auxiliary body region 212 extends along the vertexes to the center points between the adjacent three cells 2, and the auxiliary body regions 212 extended by the corresponding and adjacent three vertexes of the three adjacent cells 2 are connected to each other.

[0070] The embodiments of the present application provide a semiconductor device, which includes a semiconductor epitaxial layer 100, and a plurality of semiconductor units 1 arranged on the semiconductor epitaxial layer 100; each semiconductor unit 1 includes a plurality of cells 2 adjacent to each other, and each cell 2 includes a first doped region 21 and a second doped region 22; the first doped region 21 extends from a first surface 10 of the semiconductor epitaxial layer 100 to the inside of the semiconductor epitaxial layer 100; the first doped region 21 includes a main body region 211 and a plurality of auxiliary body regions 212; the main body region 211 has a plurality of vertexes 2111a, the auxiliary body region 212 extends along the vertexes to the center points between the corresponding adjacent vertexes, and is connected to the corresponding auxiliary body region 212 extended by the corresponding adjacent vertexes; the second doped region 22 is arranged in the main body region 211, and extends from the first surface 10 of the semiconductor epitaxial layer 100 to the inside of the semiconductor epitaxial layer 100; the second doped region 22 is different from the first doped region 21 in the type of conduction; the second doped region 22 is annular, and is arranged at a distance from the edge of the main body region 211, and the radial distance between the second doped region 22 and the edge of the main body region 211 is greater than the width of the auxiliary body region 212. By arranging the main body region 211 and the auxiliary body region 212 in the first doped region 21, and connecting the vertexes 2111a of the main body region 211 to the auxiliary body region 212, the channel length of the cell 2 at the vertexes is increased, the electric field intensity at the vertexes is reduced, and the reverse withstand voltage of the semiconductor device is effectively improved; meanwhile, by connecting the auxiliary body regions 212 of the adjacent cells 2 in the diagonal direction to each other, the P-type injection of the field effect transistor center in the diagonal direction is increased, the electric field intensity of the JFET center in the diagonal direction is reduced, and the reverse withstand voltage of the semiconductor device is further improved; in this way, by improving the reverse withstand voltage of the semiconductor device, the situation of the on-resistance rising is avoided, and the on-resistance is effectively reduced.

[0071] Referring to FIG. 4, FIG. 4 is a structural schematic diagram of a semiconductor device provided by a fourth embodiment of the present application; the present application also provides a semiconductor device, which comprises a semiconductor epitaxial wafer, the semiconductor epitaxial wafer comprising a substrate and a semiconductor epitaxial layer 100 arranged on a surface of the substrate, and specifically, a side surface of the semiconductor epitaxial layer 100 away from the substrate is a first surface 10. The semiconductor epitaxial layer 100 can be a SiC N-type epitaxial layer, the thickness of the semiconductor epitaxial layer 100 can be 5-60 um, and the doping concentration of the semiconductor epitaxial layer 100 can be 1×10 15 cm -3 to 2×10 16 cm -3 . The semiconductor epitaxial layer 100 comprises a plurality of cells 2 and a fourth doped region 2120.

[0072] The plurality of cells 2 are arranged in a two-dimensional array on the semiconductor epitaxial layer 100, and the plurality of cells 2 have a JFET region therebetween. Each cell 2 has a plurality of vertices, and each cell 2 comprises a first doped region 21 and a second doped region 22. The first doped region 21 extends from the first surface 10 of the semiconductor epitaxial layer 100 to the interior of the semiconductor epitaxial layer 100, and the first doped region 21 can be of a second conductivity type.

[0073] The second doped region 22 is arranged in the first doped region 21, and the second doped region 22 extends from the first surface 10 of the semiconductor epitaxial layer 100 to the interior of the semiconductor epitaxial layer 100; specifically, the second doped region 22 covers part of the first doped region 21, and the projection of the second doped region 22 on the semiconductor epitaxial layer 100 in the thickness direction Z is located in the first doped region 21. The second doped region 22 is different from the first doped region 21 in conductivity type, and specifically, the second doped region 22 can be of a first conductivity type.

[0074] The fourth doped region 2120 is arranged on the JFET region between the cells 2, the fourth doped region 2120 extends from the first surface 10 of the semiconductor epitaxial layer 100 to the interior of the semiconductor epitaxial layer 100, and the center of the JFET region contains the center of the fourth doped region; preferably, the center of the fourth doped region 2120 coincides with the center of the JFET region. The fourth doped region 2120 extends from the center of the JFET region to the adjacent vertex of the adjacent cell 2 and is connected with the first doped region 21. The fourth doped region and the first doped region are of the same conductivity type, and specifically, the fourth doped region 2120 can be of the second conductivity type, and the ion doping concentration of the fourth doped region 2120 can be equal to the ion doping concentration of the first doped region 21. Specifically, the fourth doped region 2120 can be a shielding region.

[0075] The second doped region 22 is annular and is arranged at a distance from the edge of the first doped region 21; the outer contour of the second doped region 22 is the same as the shape of the first doped region 21, and the corners of the second doped region 22 are circular arcs to further reduce the electric field strength. The radial distance b between the second doped region 22 and the edge of the first doped region 21 is greater than the width c of the fourth doped region 2120, so that the fourth doped region 2120 can be completely covered by the mask layer in the process.

[0076] By arranging the fourth doped region 2120 at the center of the JFET region between the cells 2 and connecting the fourth doped region 2120 to the top corners of the cells 2, the P-type injection at the center of the JFET region is increased, the electric field strength at the center of the JFET region in the diagonal direction is reduced, the reverse withstand voltage of the semiconductor device is further improved, and the situation of the on-resistance rising is avoided, effectively reducing the on-resistance.

[0077] As shown in FIG. 4, in specific embodiments, the cell 2 can further include a third doped region 23 arranged in the first doped region 21, and the third doped region 23 extends from the first surface 10 of the semiconductor epitaxial layer 100 towards the inside of the semiconductor epitaxial layer 100; specifically, in the plane perpendicular to the stacking direction Z, the third doped region 23 is connected to the second doped region 22 and covers another part of the main body region 211. The third doped region 23 has the same conductivity type as the first doped region 21, specifically, the third doped region 23 can be of the second conductivity type, and the ion doping concentration of the third doped region 23 is greater than the ion doping concentration of the first doped region 21.

[0078] The first doped region 21 further includes a first part 2111 not covered by the second doped region 22 and not covered by the third doped region 23, the first part 2111 is annular and arranged around the circumferential periphery of the second doped region 22; the first part 2111 includes a plurality of top corners 2111a and a side part 2111b connecting the plurality of top corners 2111a.

[0079] The fourth doped region 2120 can be radial, and the fourth doped region 2120 can include a plurality of extension parts 2120a, each extension part 2120a is connected to an adjacent top corner 2111a of an adjacent cell 2. Specifically, the extension direction of the extension part 2120a coincides with the extension direction of the diagonal of the cell 2, and the extension part 2120a extends from the center of the fourth doped region 2120 to the adjacent top corner 2111a.

[0080] The width a of each top corner 2111a in the first direction X is greater than the width b of the side part 2111b, so as to increase the channel length of the cell 2 at the top corner, so that the electric field strength at the top corner is reduced, effectively improving the reverse withstand voltage of the semiconductor device.

[0081] Referring to FIGS. 5-13, FIG. 5 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present application; FIG. 6 is a schematic diagram of a structure of step S1 shown in FIG. 5; FIG. 7a is a schematic diagram of a structure of step S2 shown in FIG. 5; FIG. 7b is a top view of the structure shown in FIG. 7a; FIG. 8a is a schematic diagram of a structure of step S3 shown in FIG. 5; FIG. 8b is a top view of the structure shown in FIG. 8a; FIG. 9 is a schematic diagram of a structure of step S4 shown in FIG. 5; FIG. 10a is a schematic diagram of a structure of step S5 shown in FIG. 5; FIG. 10b is a top view of the structure shown in FIG. 10a; FIG. 11 is a schematic diagram of a structure of step S6 shown in FIG. 5; and FIG. 12 is a schematic diagram of a structure of step S7 shown in FIG. 5.

[0082] The present application also provides a method for manufacturing a semiconductor device, which is used for manufacturing the semiconductor device according to any one of the above embodiments; the method specifically comprises the following steps:

[0083] Step S1: forming a first mask layer on a first surface of a semiconductor epitaxial layer.

[0084] In a specific implementation, as shown in FIG. 6, the semiconductor epitaxial layer 100 can be a SiC N-type epitaxial layer, and the thickness of the semiconductor epitaxial layer 100 can be 5-60 um. The doping concentration of the semiconductor epitaxial layer 100 can be 1x10 15 cm -3 -2x10 16 cm -3 Specifically, the semiconductor epitaxial layer 100 has a first surface 10, and the first mask layer 3 includes a shielding layer 31 and a support layer 32. Step S1 specifically comprises the following steps:

[0085] Step S11: depositing a shielding layer with a thickness of 30-60 nm on the first surface of the semiconductor epitaxial layer.

[0086] In a specific implementation, the shielding layer 31 can be deposited on the first surface 10 of the semiconductor epitaxial layer 100 by using a low pressure chemical vapor deposition (LPCVD) device. The thickness of the shielding layer 31 is 30-60 nm, for example, the thickness of the shielding layer 31 can be any one of 30 nm, 40 nm, 45 nm, 50 nm and 60 nm. Specifically, the shielding layer 31 can include a silicon oxide layer or a silicon nitride layer.

[0087] Step S12: depositing a support layer with a thickness of 1-2 um on a surface of the shielding layer away from the semiconductor epitaxial layer.

[0088] In the implementation, the support layer 32 can be formed by depositing on the side surface of the shielding layer 31 away from the semiconductor epitaxial layer 100 through LPCVD; the thickness of the support layer 32 is 1-2 um, for example, the thickness of the support layer 32 can be any value in 1 um, 1.2 um, 1.5 um, 1.8 um and 2 um. Specifically, the support layer 32 can include a silicon oxide layer.

[0089] Step S2: patterning the first mask layer to form a plurality of first openings.

[0090] In the implementation, as shown in FIG. 7a, the first mask layer 3 is etched by using a photoetching machine and an ICP device to pattern the first mask layer 3 to form the first openings 30. As shown in FIG. 7b, the first openings 30 can include a main opening 301 and a plurality of sub-openings 302. The main opening 301 is in a square shape, the plurality of main openings 301 are in the first mask layer 3 and the sidewall of the main opening 301 has a corner at the four top corners of the square; the number of the sub-openings 302 is four, and each sub-opening 302 is in communication with the corner of the main opening 301. In this way, the semiconductor epitaxial layer 100 corresponding to the sub-opening 302 can also be subjected to P-type implantation.

[0091] Step S3: lightly doping the first surface of the part of the semiconductor epitaxial layer exposed through the first openings to form a first doped region.

[0092] In the implementation, as shown in FIG. 8a, the first surface 10 of the part of the semiconductor epitaxial layer 100 exposed through the first openings 30 is implanted with P-type ions multiple times at 500°C by using a high-temperature ion implantation device to form the first doped regions 21 in a two-dimensional array on the semiconductor epitaxial layer 100. The first doped regions 21 can be of the second conductivity type.

[0093] Specifically, the implantation energy is 450 keV, 280 keV and 120 keV respectively, and the implantation dose is 2×10 13 cm -2 , 1×10 13 cm -2 and 3×10 13 cm -2 respectively; the first doped regions 21 are P-type lightly doped regions. As shown in FIG. 8b, the first doped regions 21 include a main region 211 corresponding to the main opening 301 and a sub-region 212 corresponding to the sub-opening 302; the main region 211 has a top corner, and the sub-region 212 is connected to the top corner. Specifically, the main region 211 is a polygon having a plurality of top corners, and each top corner is connected to a sub-region 212. In this embodiment, the main region 211 is preferably a square having four top corners; the number of the sub-regions 212 corresponding to each main region 211 is four.

[0094] Of course, in some other embodiments, N-type implantation can also be performed on the exposed first surface 10 of the partial semiconductor epitaxial layer 100 through the first opening 30.

[0095] Step S4: forming a second mask layer on the first surface side of the semiconductor epitaxial layer.

[0096] In the specific implementation, as shown in FIG. 9, a polycrystalline silicon material is deposited and grown on the exposed first surface 10 of the partial semiconductor epitaxial layer 100 and the surface of the first mask layer 3 to form the second mask layer 4; so that the second mask layer 4 covers the patterned first mask layer 3 and the first doped region 21; and the second mask layer 4 can include a polycrystalline silicon layer.

[0097] Specifically, step S4 further includes growing a polycrystalline silicon layer with a thickness of 0.1-1um. A polycrystalline silicon is prepared by decomposing silane (SiH4) at a low temperature of 450-700℃ using an LPCVD method; and the deposition rate is 50-500A / min. The polycrystalline silicon layer includes a first polycrystalline silicon layer 41 covering the top surface of the patterned first mask layer 3, a second polycrystalline silicon layer 42 covering the side surface of the first opening 30, and a third polycrystalline silicon layer 43 covering the main body region 211 of the first doped region 21. In combination with FIG. 7b, the thickness b of the second polycrystalline silicon layer 42 is greater than half of the width c of the secondary opening 302; so that the second polycrystalline silicon layer 42 can completely fill the secondary opening 302, thereby completely covering the secondary body region 212; to avoid the situation that the subsequent process of forming the second doped region 22 causes adverse effects on the secondary body region 212.

[0098] Step S5: patterning the second mask layer to form a plurality of second openings.

[0099] In the specific implementation, as shown in FIG. 10a, the projection of the second opening 40 on the first doped region 21 is located in the main body region 211, and the projection of the second opening 40 on the first doped region 21 is annular and surrounds the center of the main opening 301. Specifically, step S5 further includes:

[0100] Step S51: forming a second opening on the third polycrystalline silicon layer, and keeping the second polycrystalline silicon layer in the secondary opening covering the secondary body region.

[0101] Specifically, in combination with FIG. 10b, the third polycrystalline silicon layer 43 is etched using a mask to form an annular second opening 40, and the second polycrystalline silicon layer 42 in the secondary opening 302 is kept covering the secondary body region 212; to avoid the situation that the subsequent process of forming the second doped region 22 causes adverse effects on the secondary body region 212. Specifically, the part of the third polycrystalline silicon layer 43 located in the center of the annular second opening 40 is reserved as a mask for implanting N-type ions to form the second doped region 22 in the subsequent process.

[0102] Step S52: Remove the first polysilicon layer.

[0103] Specifically, the first polysilicon layer 41 located on the top surface of the patterned first mask layer 3 is removed using a mask etching method.

[0104] Step S6: Redoping at least a portion of the first doped region exposed through the second opening to form a second doped region.

[0105] In a specific embodiment, as shown in FIG11, N-type ions are repeatedly implanted into the first surface 10 of the exposed annular semiconductor epitaxial layer 100 through the second opening 40 at 500°C using a high-temperature ion implantation device to form an annular second doped region 22. The second doped region 22 has a different conductivity type than the first doped region 21; specifically, the second doped region 22 can be of the first conductivity type. In other embodiments, P-type implantation can also be performed on the first surface 10 of the exposed annular semiconductor epitaxial layer 100 through the second opening 40.

[0106] It is understood that, in specific embodiments, the first conductivity type is either a P-type doped semiconductor or an N-type doped semiconductor, and the second conductivity type is either a P-type doped semiconductor or an N-type doped semiconductor.

[0107] Specifically, the injection energies were 200keV, 100keV, and 30keV, and the injection doses were 5×10⁻⁶. 14 cm -2 2×10 14 cm -2 3×10 14 cm -2 The second doped region 22 is an N-type heavily doped region. The thickness f of the second doped region 22 is less than the thickness e of the first doped region 21; that is, along the thickness direction Z, the portion of the first doped region 21 that is close to the first surface 10 and corresponds to the second opening 40 forms the second doped region 22.

[0108] Step S7: Remove the patterned first mask layer and the patterned second mask layer.

[0109] Specifically, as shown in Figure 12, a wet etching process can be used to remove the remaining first mask layer 3 and second mask layer 4. Then, a third mask layer 5 is deposited on the first surface 10 of the semiconductor epitaxial layer 100 and patterned to expose the portion of the main body region 211 surrounded by the second doped region 22.

[0110] After step S7, the process may further include: redoping a portion of the undoped region of the first doped region to form a third doped region.

[0111] In a specific embodiment, as shown in Figure 13, which is a schematic diagram of the structure forming the third doped region, P-type ions are repeatedly implanted into a portion of the undoped area of ​​the first doped region 21 through a patterned third mask layer 5 at 500°C using a high-temperature ion implantation device to form the third doped region 23. Specifically, the implantation energies are 180keV, 120keV, 80keV, 60keV, and 30keV, and the implantation doses are 3×10⁻⁶. 14 cm -2 2×10 14 cm -2 4×10 14 cm -2 2×10 14 cm -2 3×10 14 cm -2 The third doped region 23 is a heavily p-type doped region. The thickness g of the third doped region 23 is less than the thickness e of the first doped region 21.

[0112] Specifically, the steps for forming the third doped region may include: heavily doping the portion of the first doped region surrounding the second doped region to form the third doped region.

[0113] In a specific embodiment, the second doped region 22 can be annular; after the third mask layer 5 is patterned, the portion of the first doped region 21 surrounded by the second doped region 22 is exposed; after P-type ions are implanted through the opening of the third mask layer 5, the portion of the first doped region 21 close to the first surface 10 and surrounded by the second doped region 22 forms the third doped region 23. The third doped region 23 has the same conductivity type as the first doped region 21; specifically, the third doped region 23 can be of the first conductivity type.

[0114] Following the step of forming the third doped region, the process may further include forming a gate structure, an insulating layer, a source layer, and a drain layer to form a semiconductor device. These processes are the same as or similar to relevant processes in the prior art, and can be found in the prior art for details, which will not be elaborated here.

[0115] The preparation method of the semiconductor device provided by the embodiments of the present application specifically comprises the following steps: first, forming a first mask layer 3 on a first surface 10 of a semiconductor epitaxial layer 100; then, patterning the first mask layer 3 to form a plurality of first openings 30; then, performing light doping on the first surface 10 of the semiconductor epitaxial layer 100 exposed through the first openings 30 to form a first doped region 21; then, forming a second mask layer 4 on one side of the first surface 10 of the semiconductor epitaxial layer 100; then, patterning the second mask layer 4 to form a plurality of second openings 40; then, performing heavy doping on the first doped region 21 exposed through the second openings 40 to form a second doped region 22; and then, removing the patterned second mask layer 4. In this way, a precise top corner injection structure is realized by using a self-alignment method, the method has good controllability and has better practicability.

[0116] The above description is merely an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation obtained by using the content of the present application specification and drawings, or directly or indirectly applied to other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A semiconductor device comprising a semiconductor epitaxial layer on which a plurality of semiconductor cells are provided; characterized by, The semiconductor unit comprises a plurality of cells adjacent to each other, each of the cells comprising: a first doped region extending from a first surface of the semiconductor epitaxial layer towards an interior of the semiconductor epitaxial layer; the first doped region comprising a main body region and a plurality of sub-body regions; the main body region having a plurality of apexes, the sub-body regions extending along the apexes towards a center point between corresponding adjacent apexes and connecting the corresponding adjacent apexes; a second doped region disposed in the main body region and extending from the first surface of the semiconductor epitaxial layer towards the interior of the semiconductor epitaxial layer; the second doped region being different from the first doped region in a conductive type; wherein the second doped region is annular, and the second doped region is spaced apart from an edge of the main body region, and a radial distance between the second doped region and the edge of the main body region is greater than a width of the sub-body region.

2. The semiconductor device of claim 1, wherein: the semiconductor unit comprises three cells adjacent to each other, the cells being arranged in a two-dimensional array; the main body region is hexagonal; the sub-body regions extend along the apexes towards a center point between the three adjacent cells and connect the sub-body regions extended by the three adjacent apexes of the three adjacent cells.

3. The semiconductor device of claim 1, wherein the cell further comprises: a third doped region disposed in the main body region and extending from the first surface of the semiconductor epitaxial layer towards the interior of the semiconductor epitaxial layer; the third doped region is connected to the second doped region; the third doped region is the same as the first doped region in the conductive type; and an ion doping concentration of the third doped region is greater than an ion doping concentration of the first doped region; the main body region further comprises a first portion not covered by the second doped region and not covered by the third doped region, the first portion being annular and disposed around a circumferential periphery of the second doped region; wherein the first portion comprises a plurality of the apexes and a side portion connecting the plurality of the apexes; each of the apexes has a width along a first direction greater than a width of the side portion; the first direction is an extension direction of a diagonal line of the main body region.

4. The semiconductor device of claim 3, wherein: a width of the second doped region is greater than 0.5 um; a width of the apex along the first direction is 0.4-1.4 um; a width of the side portion is 0.3-1 um; a width of the sub-body region is 0.6-2 um.

5. The semiconductor device of claim 1, wherein the semiconductor unit has a JFET region between the adjacent cells; wherein a connection of a plurality of the sub-body regions connected to a plurality of the adjacent apexes in different cells is located in a central region of the JFET region.

6. The semiconductor device according to claim 5, wherein the semiconductor unit comprises four cells adjacent to each other, the cells being arranged in a two-dimensional array; the main body region is quadrangular; each of the cells has four apexes.

7. The semiconductor device of any one of claims 1-6, wherein: The semiconductor device is a MOSFET device, further comprising a gate structure, an insulating layer, a source layer, and a drain layer; The second doped region is of a first conductivity type; the first doped region and the third doped region are of a second conductivity type; the first conductivity type is one of a P-type doped semiconductor or an N-type doped semiconductor, and the second conductivity type is the other of the P-type doped semiconductor or the N-type doped semiconductor.

8. A semiconductor device comprising a semiconductor epitaxial layer; characterized by, The semiconductor epitaxial layer comprises: a plurality of cells; the plurality of cells are arranged in a two-dimensional array; the plurality of cells have a JFET region therebetween; the cells have a plurality of top corners; each of the cells comprises: a first doped region extending from a first surface of the semiconductor epitaxial layer towards an interior of the semiconductor epitaxial layer; a second doped region disposed within the first doped region and extending from the first surface of the semiconductor epitaxial layer towards the interior of the semiconductor epitaxial layer; the second doped region is of a different conductivity type than the first doped region; a fourth doped region disposed on the JFET region; the fourth doped region extends from a surface of the semiconductor epitaxial layer towards the interior of the semiconductor epitaxial layer; and a center region of the JFET region contains a center of the fourth doped region; wherein the fourth doped region extends from the center region of the JFET region to an adjacent top corner of an adjacent cell and connects with the first doped region; the fourth doped region is of the same conductivity type as the first doped region; the second doped region is annular, and the second doped region is spaced apart from an edge of the first doped region, and a radial distance between the second doped region and the edge of the first doped region is greater than a width of the fourth doped region.

9. The semiconductor device of claim 8, wherein, The cell further comprises: a third doped region disposed within the first doped region and extending from the first surface of the semiconductor epitaxial layer towards the interior of the semiconductor epitaxial layer; the third doped region is adjacent to the second doped region; the third doped region is of the same conductivity type as the first doped region; and an ion doping concentration of the third doped region is greater than an ion doping concentration of the first doped region; the first doped region further comprises a first portion not covered by the second doped region and not covered by the third doped region, the first portion is annular and disposed around a peripheral of the second doped region; the first portion comprises a plurality of the top corners and a side portion connecting the plurality of the top corners; a width of each of the top corners in a first direction is greater than a width of the side portion; the first direction is an extension direction of a diagonal line of the first doped region.

10. The semiconductor device of claim 9, wherein: the fourth doped region is radial, the fourth doped region comprises a plurality of extension portions connected to the top corners; and an extension direction of the extension portions coincides with an extension direction of a diagonal line of the cell.

11. A method of manufacturing a semiconductor device, characterized by, comprises: forming a first mask layer on a first surface of a semiconductor epitaxial layer; patterning the first mask layer to form a plurality of first openings; The first opening includes a main opening and a sub opening, a side wall of the main opening has a corner, and the sub opening is communicated with the corner of the main opening; The first surface of the semiconductor epitaxial layer exposed through the first opening is lightly doped to form a first doped region; the first doped region includes a main body region and a sub body region; the main body region has a top corner, and the sub body region is connected with the top corner; A polysilicon layer with a thickness of 0.1-1um is grown on the first surface of the semiconductor epitaxial layer to form a second mask layer; the second mask layer covers the patterned first mask layer and the first doped region; the polysilicon layer includes a first polysilicon layer covering the top surface of the patterned first mask layer, a second polysilicon layer covering the side surface of the first opening, and a third polysilicon layer covering the main body region of the first doped region; the thickness of the second polysilicon layer is greater than the width of the sub opening; The second mask layer is patterned to form a plurality of second openings; the projection of the second opening on the first doped region is located in the main body region; At least part of the first doped region exposed through the second opening is heavily doped to form a second doped region; the thickness of the second doped region is less than the thickness of the first doped region; The second doped region is different from the first doped region in conductive type; The second doped region is annular; The patterned first mask layer and the patterned second mask layer are removed.

12. The method of claim 11, wherein The main body region is polygonal and has a plurality of top corners, each of which is connected with a sub body region.

13. The method of producing a semiconductor device according to claim 11 or 12, wherein The step of forming the first mask layer on the first surface of the semiconductor epitaxial layer includes: A shielding layer with a thickness of 30-60nm is deposited on the first surface of the semiconductor epitaxial layer; the shielding layer includes a silicon oxide layer or a silicon nitride layer; A support layer with a thickness of 1-2um is deposited on the surface of the shielding layer away from the semiconductor epitaxial layer; the support layer includes a silicon oxide layer.

14. The method of producing a semiconductor device according to Claim 13, wherein The step of patterning the second mask layer includes: The second opening is formed on the third polysilicon layer, and the second polysilicon layer in the sub opening covers the sub body region; the second opening is annular.

15. The method of producing a semiconductor device according to Claim 14, wherein The step of heavily doping at least part of the first doped region exposed through the second opening to form a second doped region further includes: Part of the region of the first doped region which is not heavily doped is heavily doped to form a third doped region; the third doped region is of a second conductive type; the ion doping concentration of the third doped region is greater than the ion doping concentration of the first doped region; and the thickness of the third doped region is less than the thickness of the first doped region.

16. The method of producing a semiconductor device according to Claim 15, wherein The step of heavily doping part of the first doped region which is not heavily doped to form a third doped region includes: Part of the first doped region surrounded by the second doped region is heavily doped to form a third doped region.

17. The method of producing a semiconductor device according to claim 11 or 15, wherein The method further includes forming a gate structure, an insulating layer, a source layer, and a drain layer. The second doped region is of a first conductivity type; the first doped region and the third doped region are of a second conductivity type; the first conductivity type is one of a P-type doped semiconductor or an N-type doped semiconductor, and the second conductivity type is the other of the P-type doped semiconductor or the N-type doped semiconductor. The second doped region is of a first conductivity type; the first doped region and the third doped region are of a second conductivity type; the first conductivity type is one of a P-type doped semiconductor or an N-type doped semiconductor, and the second conductivity type is the other of the P-type doped semiconductor or the N-type doped semiconductor.

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