Array substrate, display panel, and display device

Abstract

The present disclosure provides an array substrate, a display panel, and a display device. The array substrate comprises: a base substrate, comprising a display area and a non-display area; a plurality of binding terminals, located in the non-display area and comprising a plurality of first binding terminals and a plurality of second binding terminals; at least one sensing signal line, located in the non-display area and electrically connected to at least some of the first binding terminals; a first signal line, located on the side of the at least one sensing signal line distant from the display area and electrically connected to at least one second binding terminal; and a second signal line, located between the first signal line and the at least one sensing signal line, wherein the orthographic projection of the second signal line on the base substrate overlaps the orthographic projection of at least part of the sensing signal line on the base substrate, the second signal line is electrically connected to at least one second binding terminal, and at least one floating second binding terminal is arranged between the second binding terminal corresponding to the second signal line and the second binding terminal corresponding to the first signal line.

Description

Array substrate, display panel and display device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202410881805.5, filed on July 2, 2024, and entitled "Array substrate, display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to an array substrate, a display panel and a display device. BACKGROUND

[0004] For decades, the development of the television industry has undergone tremendous changes, from heavy black and white televisions to color televisions, and now to large-screen intelligentization. The innovation technology has never stopped changing. With the product update iteration and the higher requirements of the general public for display products, it is necessary to continuously break through traditional technology and innovate. In addition to the development in terms of low cost, high transmittance and high contrast, it is also proposed to set sensors on display products, such as adding light and temperature sensing designs, to improve the user experience. SUMMARY

[0005] The array substrate, the display panel and the display device provided by the present disclosure have the following specific solutions.

[0006] In one aspect, the present disclosure provides an array substrate, comprising:

[0007] a substrate, comprising a display area and a non-display area located on at least one side of the display area;

[0008] a plurality of binding terminals located in the non-display area, the plurality of binding terminals comprising a plurality of first binding terminals and a plurality of second binding terminals;

[0009] at least one sensing signal line located in the non-display area, the at least one sensing signal line being electrically connected to at least part of the first binding terminals;

[0010] a first signal line located on a side of the at least one sensing signal line away from the display area, the first signal line being electrically connected to at least one of the second binding terminals;

[0011] A second signal line is located between the first signal line and the at least one sensing signal line, a projection of the second signal line on the substrate substrate overlaps with a projection of at least part of the sensing signal line on the substrate substrate; the second signal line is electrically connected with the at least one second binding terminal, and there is at least one second binding terminal arranged in a floating manner between the second binding terminal corresponding to the second signal line and the second binding terminal corresponding to the first signal line.

[0012] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a common electrode bus, a common electrode line and a plurality of connection lines are further included in the non-display area, wherein,

[0013] The common electrode bus is located on a side of the at least one sensing signal line close to the display area, the common electrode line is located on a side of at least part of the sensing signal line away from the display area, and the plurality of connection lines are connected between the common electrode bus and the common electrode line.

[0014] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a plurality of fan-out lines are further included in the non-display area, a projection of the plurality of fan-out lines on the substrate substrate intersects with a projection of the common electrode bus on the substrate substrate;

[0015] The fan-out line includes an inclined portion, the plurality of fan-out lines are divided into a plurality of groups, and the inclined portions of adjacent two groups of the fan-out lines extend in opposite directions;

[0016] The connection line includes a widened portion, and a projection of the widened portion on the substrate substrate is located within a projection of a gap between the inclined portions of adjacent two groups of the fan-out lines on the substrate substrate.

[0017] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, the connection line further includes a connection portion connecting the widened portion and the common electrode line;

[0018] The second signal line includes a first wire portion and a first switching portion located between the common electrode bus and the common electrode line; wherein the first wire portion is arranged to be disconnected at the connection portion; the first switching portion is arranged to cross the connection portion in different layers, and the first wire portion on both sides of the first switching portion and the connection portion is electrically connected.

[0019] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, a plurality of first electrostatic discharge structures are further included in the non-display area, and the plurality of first electrostatic discharge structures are connected between the plurality of fan-out lines and the first wire portion.

[0020] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second electrostatic discharge structures between the plurality of first electrostatic discharge structures and the widened portion, and the plurality of second electrostatic discharge structures are connected between the first wiring portion and the widened portion.

[0021] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second electrostatic discharge structures between the plurality of first electrostatic discharge structures and the widened portion, and the plurality of second electrostatic discharge structures are connected between the first wiring portion and the widened portion.

[0022] The first sensing portion is discontinuously arranged at the connection portion, the second switching portion is cross-layered and arranged with the connection portion, and the second switching portion is electrically connected with the first sensing portion on both sides of the connection portion.

[0023] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second electrostatic discharge structures between the plurality of first electrostatic discharge structures and the widened portion, and the plurality of second electrostatic discharge structures are connected between the first wiring portion and the widened portion.

[0024] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second electrostatic discharge structures between the plurality of first electrostatic discharge structures and the widened portion, and the plurality of second electrostatic discharge structures are connected between the first wiring portion and the widened portion.

[0025] The at least one sensing signal line comprises a temperature sensing signal line, and the temperature sensing signal line comprises a first temperature sensing wiring portion between the first sub-common electrode line and the second sub-common electrode line.

[0026] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second electrostatic discharge structures between the plurality of first electrostatic discharge structures and the widened portion, and the plurality of second electrostatic discharge structures are connected between the first wiring portion and the widened portion.

[0027] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second electrostatic discharge structures between the plurality of first electrostatic discharge structures and the widened portion, and the plurality of second electrostatic discharge structures are connected between the first wiring portion and the widened portion.

[0028] The temperature sensing signal line further comprises a second temperature sensing wiring portion and a third switching portion, the third switching portion is cross-layered and arranged with the third sub-common electrode line, and the third switching portion connects the first temperature sensing wiring portion and the second temperature sensing wiring portion.

[0029] In some embodiments, the array substrate provided by the embodiments of the present disclosure further comprises a plurality of second electrostatic discharge structures between the plurality of first electrostatic discharge structures and the widened portion, and the plurality of second electrostatic discharge structures are connected between the first wiring portion and the widened portion.

[0030] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the at least one sensing signal line further comprises a temperature sensing signal line, and the temperature sensing signal line comprises the first sensing part and the second switching part.

[0031] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the second signal line further comprises a second wiring part and at least two fourth switching parts; wherein,

[0032] One of the fourth switching parts is arranged at the overlapping position of the second signal line and the sensing signal line;

[0033] The second wiring part extends from the corresponding second binding terminal of the second signal line to the overlapping position, and the second wiring part comprises at least one broken line, and the broken second wiring part is electrically connected through the fourth switching part.

[0034] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the first signal line is a ground line, and the second signal line is a data signal detection line.

[0035] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, further comprising a feedback line located on the side of the second signal line away from the first signal line.

[0036] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, further comprising a plurality of transistors located in the non-display area, and the plurality of sensing signal lines comprise a first light sensing signal line, a second light sensing signal line, and a plurality of third light sensing signal lines; wherein,

[0037] The first light sensing signal line is electrically connected to the gate of the plurality of transistors, the second light sensing signal line is electrically connected to the first electrode of the plurality of first transistors, and different third light sensing signal lines are electrically connected to different transistors.

[0038] On the other hand, the embodiments of the present disclosure provide a display panel, comprising the array substrate provided by the embodiments of the present disclosure, and a facing substrate opposite to the array substrate.

[0039] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the array substrate comprises a plurality of transistors located in the non-display area;

[0040] The facing substrate comprises a black matrix and a color resistance, wherein the black matrix covers part of the transistors, and the color resistance covers the remaining transistors.

[0041] On the other hand, the embodiments of the present disclosure provide a display device, comprising the display panel provided by the embodiments of the present disclosure, and a backlight module located on the light entering side of the display panel. Attached Figure Description

[0042] Figure 1 is a schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0043] Figure 2a is an enlarged structural schematic diagram of region Z1 in Figure 1;

[0044] Figure 2b is an enlarged structural schematic diagram of region Z2 in Figure 2a;

[0045] Figure 3 is a schematic diagram of another structure of the array substrate provided in the embodiments of this disclosure;

[0046] Figure 4 is a schematic diagram of a structure near any of the connecting lines in Figure 3;

[0047] Figure 5 is a schematic diagram of another structure near any of the connecting lines in Figure 3;

[0048] Figure 6 is a magnified structural diagram of region Z3 in Figure 3;

[0049] Figure 7 is an enlarged structural diagram of region Z4 in Figure 1;

[0050] Figure 8 is an equivalent circuit diagram for detecting ambient light provided in an embodiment of this disclosure;

[0051] Figure 9 is a schematic diagram of the structure of the discrete transistor provided in an embodiment of this disclosure;

[0052] Figure 10 is a schematic diagram of the structure of the display panel provided in an embodiment of this disclosure;

[0053] Figure 11 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation

[0054] For the purposes of the present disclosure, the goals, technical solutions, and advantages of the embodiments will be more clearly understood from the following description of the embodiments of the present disclosure, taken in conjunction with the accompanying drawings. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, and the like are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. A sharp angle illustrated can typically be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not to be construed as limiting to the region. The purpose of the regions illustrated in the figures is to more conceptually illustrate the logical proximity between illustrated regions for an intraoperative tool to be used in the surgical procedure. Furthermore, the same or similar reference numerals are used in different drawings to denote the same or similar elements or components having the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and structures incorporated herein will be omitted.

[0055] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The use of the terms "first", "second", and the like, does not imply any order, quantity, or importance, but rather are used to distinguish one element from another. The terms "comprises", "comprising", "includes", "including" and the like, means encompassing, and therefore specifies the presence and avoids the exclusion of not only the listed components but also other components not specifically listed. The terms "connected", "coupled", and the like, are not limited to direct or physical connections or couplings, but can include indirect coupling between connected items or intervening items therebetween allowing a signal to be sent therebetween. The terms "inner", "outer", "upper", "lower", and the like, are used only to describe relative positions to the absolute positions of the described objects, and can change accordingly when the absolute positions of the described objects change.

[0056] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, or be indirectly on the other element or layer with intervening elements or layers. When an element or layer is referred to as being "set on" one side of another element or layer, it can be directly on the side of the other element or layer, or be indirectly on the side of the other element or layer with intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, or "directly connected to" another element or layer, there are no intervening elements or layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0057] The TFT LCD market is increasingly competitive, and with the development of high frequency, high brush, high PPI, etc. gradually slowing down, fat module, screen-enabled is another way to improve product competitiveness.

[0058] In some embodiments, the temperature sensing and light sensing products are a kind of fat module, which gives the screen temperature detector function for real-time detection of panel temperature and adjustment of video tailing, and gives the light detector function for real-time adjustment of backlight brightness and color temperature according to light intensity. However, since the ground (GND) line is adjacent to the ADD line, after the panel increases the temperature sensing and light sensing design, the temperature sensing and light sensing signal lines overlap with the data signal detection line (ADD Line, used to detect whether the data line has a broken line defect in the array test stage) in the plane, so in the static electricity test, the binding terminal corresponding to the GND line will release static electricity to the binding terminal corresponding to the ADD line, which may further cause the ADD line to release static electricity at the overlapping place with the temperature sensing and light sensing, affecting the temperature sensing and light sensing detection function.

[0059] To improve the above technical problems, the array substrate provided by the embodiments of the present disclosure is provided, and FIG. 1 shows a structure schematic diagram of the array substrate provided by the embodiments of the present disclosure. FIG. 2a is an enlarged structure schematic diagram of the Z1 region in FIG. 1 (it should be noted that the terminal structure of the display area data line between the terminal corresponding to the clock signal line CLK and the terminal corresponding to the sensing signal line 103 is omitted in FIG. 2a), and FIG. 2b is an enlarged structure schematic diagram of the Z2 region in FIG. 2a. As can be seen from FIG. 1, FIG. 2a and FIG. 2b, the array substrate provided by the embodiments of the present disclosure comprises:

[0060] The substrate 101 includes a display area AA and a non-display area BB located on at least one side of the display area AA. Optionally, the non-display area BB includes a first non-display area BB1 provided with a binding area BD, a second non-display area BB2 opposite to the first non-display area BB1, and a third non-display area BB3 connecting the first non-display area BB1 and the second non-display area BB2. In some embodiments, the display area AA includes an array of red sub-pixel areas, green sub-pixel areas, blue sub-pixel areas, etc. The substrate 101 is a substrate allowing visible light to pass through, such as glass, quartz, plastic, etc.

[0061] A plurality of binding terminals 102 are located in the non-display area BB, for example, the plurality of binding terminals 102 are located in the binding area BD of the first non-display area BB1. The plurality of binding terminals 102 can include a plurality of first binding terminals pd1 and a plurality of second binding terminals pd2. Optionally, the number, size, and structure of the binding terminals 102 in each binding area BD can be the same or different, and in each binding area BD, the plurality of first binding terminals pd1 are located on the left and / or right side of the plurality of second binding terminals pd2. For example, in the left binding area BD, the plurality of first binding terminals pd1 are located on the right side of the plurality of second binding terminals pd2. In the right binding area BD, the plurality of first binding terminals pd1 are located on the left side of the plurality of second binding terminals pd2. In the middle binding area BD, the plurality of first binding terminals pd1 are located on the left and right sides of the plurality of second binding terminals pd2. In some embodiments, the binding terminal 102 can be located in the gate metal layer and the transparent electrode layer at the same time, and the pattern of the binding terminal 102 located in the gate metal layer and the pattern of the binding terminal 102 located in the transparent electrode layer are electrically connected through at least one via hole, and the via hole is located in the pattern range of the gate metal layer.

[0062] At least one sensing signal line 103 is located in the non-display area BB, and the at least one sensing signal line 103 is electrically connected with at least part of the first binding terminals pd1. Optionally, the sensing signal line 103 is integrally provided with the pattern of the gate metal layer of the corresponding first binding terminal pd1. In some embodiments, in order to reduce the contact resistance and enhance the electrical connection effect, one sensing signal line 103 can be electrically connected with at least two first binding terminals pd1, and after all the sensing signal lines 103 are electrically connected with the corresponding first binding terminals pd1, there can still be some first binding terminals pd1 left. Referring to FIG. 2a, dummy binding terminals can be provided between the at least two first binding terminals pd1.

[0063] The first signal line 104 is located on the side of the sensing signal line 103 away from the display area AA, and the first signal line 104 is electrically connected with at least one second binding terminal pd2. Optionally, the first signal line 104 is integrally arranged with the pattern of the gate metal layer contained in the corresponding second binding terminal pd2. In some embodiments, to reduce the contact resistance and enhance the electrical connection effect, the first signal line 104 can be electrically connected with at least two second binding terminals pd2.

[0064] The second signal line 105 is located between the first signal line 104 and the sensing signal line 103, and the orthogonal projection of the second signal line 105 on the substrate 101 intersects with at least part of the orthogonal projection of the sensing signal line 103 on the substrate 101. The second signal line 105 is electrically connected with at least one second binding terminal pd2. Optionally, the second signal line 105 is integrally arranged with the pattern of the gate metal layer contained in the corresponding second binding terminal pd2, and the corresponding second binding terminal pd2 of the second signal line 105 has at least one floating second binding terminal pd2 between the corresponding second binding terminal pd2 of the first signal line 104.

[0065] In some embodiments, the first signal line 104, the corresponding second binding terminal pd2 of the second signal line 105, and the corresponding first binding terminal pd1 of the sensing signal line 103 can be located in the same binding area BD. Alternatively, the first signal line 104 and the corresponding second binding terminal pd2 of the second signal line 105 are located in the left and right binding areas BD, and the corresponding first binding terminal pd1 of the sensing signal line 103 is located in the middle binding area BD.

[0066] In some embodiments, the first signal line 104 can be a GND line, and the second signal line 105 can be an ADD line. In the related art, the first signal line 104 and the second signal line 105 are respectively electrically connected with two second binding terminals pd2, as shown in FIG. 2b. In the present disclosure, the first signal line 104 can be electrically connected with two second binding terminals pd2, and the second signal line 105 can be electrically connected with one second binding terminal pd2. In this way, the binding mode of the first signal line 104 can be kept unchanged, the compatibility with the related art can be enhanced, and the other second binding terminal pd2 corresponding to the second signal line 105 in the related art can be floatingly arranged. In this case, as shown in FIG. 2b, the first signal line 104 includes a first lead-out line p1 led out from the corresponding second binding terminal pd2, and the second signal line 105 includes a second lead-out line p2 extended from the corresponding second binding terminal pd2. At least part of the width of the second lead-out line p2 is smaller than the width of the first lead-out line p1.

[0067] In the array substrate provided in the embodiments of the present disclosure, by arranging at least one floating second binding terminal pd2 between the second binding terminal pd2 corresponding to the second signal line 105 and the second binding terminal pd2 corresponding to the first signal line 104, the distance between the second binding terminal pd2 corresponding to the second signal line 105 and the second binding terminal pd2 corresponding to the first signal line 104 can be increased, the anti-static capability at this position can be increased, the risk of static electricity on the second binding terminal pd2 corresponding to the second signal line 105 being transferred to the second binding terminal pd2 corresponding to the first signal line 104 can be reduced, and then the probability of static breakdown of the sensing signal line 103 crossing the second signal line 105 at the crossing position can be reduced, thereby improving the influence of static electricity on the light sensing and temperature sensing detection effect.

[0068] In some embodiments, FIG. 3 is another structural schematic diagram of the array substrate provided in the embodiments of the present disclosure, and FIG. 4 is a structural schematic diagram of a position near any connection line 106 in FIG. 3. As shown in FIG. 3 and FIG. 4, in the array substrate provided in the embodiments of the present disclosure, in the second non-display area BB2, the common electrode bus 107 is located on the side of the sensing signal line 103 close to the display area AA, the common electrode bus 107 can be electrically connected with the common electrode of the display area AA, and the common electrode line 108 is located on the side of at least part of the sensing signal line 103 away from the display area AA. Optionally, the common electrode bus 107 and the common electrode line 108 are electrically connected through a plurality of connection lines 106, and the connection lines 106 are integrally arranged with the common electrode line 108 and the common electrode bus 107. In some embodiments, the connection lines 106, the common electrode bus 107 and the common electrode line 108 can be located in the gate metal layer (Gate).

[0069] In the above embodiments, the common voltage signal (VCOM) on the common electrode line 108 is introduced into the common electrode bus 107 and then into the display area AA in a metal direct connection manner, which is beneficial to increasing the signal strength of VCOM in the display area AA; and after static electricity is introduced into the distal common electrode line 108, the static electricity can be rapidly dispersed in the plane through the plurality of connection lines 106, thereby improving the anti-static capability.

[0070] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 4, a plurality of fan-out lines 109 can be arranged in the second non-display area BB2, the plurality of fan-out lines 109 can be integrally arranged corresponding to a plurality of data lines of the display area AA, the orthogonal projection of the plurality of fan-out lines 109 on the substrate 101 intersects with the orthogonal projection of the common electrode bus 107 on the substrate 101; the fan-out line 109 includes an inclined portion 109', the plurality of fan-out lines 109 can be divided into a plurality of groups, the extension directions of the inclined portions 109' of the adjacent two groups of fan-out lines 109 are opposite, for example, the inclined portion 109' of one group of fan-out lines 109 extends obliquely to the left and down, and the inclined portion 109' of another group of fan-out lines 109 extends obliquely to the right and down; the connection line 106 can include a widened portion 1061, the orthogonal projection of the widened portion 1061 on the substrate 101 is located in the orthogonal projection of the gap between the inclined portions 109' of the adjacent two groups of fan-out lines 109 on the substrate 101, thereby reducing the risk of disconnection of the connection line 106.

[0071] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 4, the connection line 106 can further include a connection portion 1062 connecting the widened portion 1061 and the common electrode line 108; the second signal line 105 includes a first wire portion 1051 and a first adapter portion 1052 located between the common electrode bus 107 and the common electrode line 108; wherein the first wire portion 1051 is arranged to be disconnected at the connection portion 1062; the first adapter portion 1052 is arranged to cross the connection portion 1062 in different layers (for example, the connection portion 1062 is located in the gate metal layer, and the first adapter portion 1052 is located in the transparent electrode layer or the source-drain metal layer), and the first adapter portion 1052 is electrically connected with the first wire portion 1051 on both sides of the connection portion 1062, thereby realizing the cross-line connection of the first wire portion 1051.

[0072] In some embodiments, the material of the transparent electrode layer of the present disclosure can include at least one transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), etc.; the material of the gate metal layer can include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc., the layer where the gate line is located can be a single-layer structure or a laminated structure, for example, the gate metal layer is a single-layer structure composed of a molybdenum metal layer; the material of the source-drain metal layer can include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc., the source-drain metal layer can be a single-layer structure or a laminated structure, for example, the source-drain metal layer is a laminated structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer.

[0073] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 4, a plurality of first electrostatic discharge structures (also referred to as electrostatic protection units EU) 110 can also be arranged in the second non-display area BB2, and the plurality of first electrostatic discharge structures 110 can be connected between the plurality of fan-out lines 109 and the first wiring part 1051, at this time, the first wiring part 1051 functions as a short ring. As can be seen from FIG. 4, the present disclosure can further arrange a second electrostatic discharge structure 111 between the plurality of first electrostatic discharge structures 110 and the widened part 1061, and the second electrostatic discharge structure 111 is connected between the first wiring part 1051 and the widened part 1061, so that the static electricity on the data line can be discharged to the connection line 106 in turn through the fan-out line 109, the first electrostatic discharge structure 110, the first wiring part 1051 and the second electrostatic discharge structure 111, thereby improving the anti-static capability.

[0074] In some embodiments, FIG. 5 is another schematic view of the structure near any connection line 106 in FIG. 3. As shown in FIG. 4 and FIG. 5, at least part of the sensing signal line 103 in the present disclosure can include a first sensing part 1031 and a second switching part 1032 between the first wiring part 1051 and the common electrode line 108; wherein the first sensing part 1031 is arranged to be disconnected at the connection part 106; the second switching part 1032 is arranged to be staggered with the connection part 1062, and the second switching part 1032 is electrically connected with the first sensing part 1031 on both sides of the connection part 1062, thereby realizing the cross-layer connection of the first sensing part 1031 at the connection part 1062 through the second switching part 1032. In some embodiments, the first sensing part 1031 is located in the gate metal layer, and the second switching part 1032 is located in the transparent electrode layer or the source-drain metal layer.

[0075] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 4 and FIG. 5, the sensing signal line 103 includes a temperature sensing signal line TS and a plurality of light sensing signal lines AS, and the light sensing signal line AS includes the first sensing part 1031 and the second switching part 1032. Optionally, in FIG. 5, the temperature sensing signal line TS can also include the first sensing part 1031 and the second switching part 1032, and the cross-line design at the connection line 106 is added, and the light sensing and temperature sensing performance can be realized with little change in other structures or signal lines of the display panel, thereby showing good compatibility.

[0076] The temperature sensing probe usually utilizes the property that the resistance of the metal changes with temperature, so that the corresponding temperature can be obtained by detecting the resistance of the temperature sensing signal line TS. However, there are problems of uniformity of the metal film thickness and uniformity of the etching reference (Base) in the panel manufacturing process, and the temperature sensing design panel needs to be recalibrated before leaving the factory, so the single temperature calibration (that is, detecting the actual resistance of the temperature sensing signal line TD at a specific temperature, and judging whether the difference between the actual resistance and the theoretical resistance corresponding to the specific temperature is within the error allowed range) has the fastest production speed. To meet the conditions of single temperature calibration, the metal for making the temperature sensing signal line TS needs to be a single metal or a single metal resistance ratio. The scheme shown in FIG. 5, the first trace part 1051 of the temperature sensing signal line TS needs to be cross-connected at a plurality of connection lines 106, and the single metal resistance ratio of the temperature sensing signal line TS will decrease, and the calibration will be difficult. However, if the connection line 106 is cross-connected, the VCOM signal strength and the static electricity dissipation capability of the in-plane DPO side (that is, the layer where the second non-display area BB2 is located) will be adversely affected. Therefore, considering that the temperature sensing signal line TS cannot be too far away from the display area AA, the present disclosure divides the common electrode line 108 into two parts and directly connects the metals at the two corners of the DPO side, and the temperature sensing signal line TS passes through the two parts of the common electrode line 108, so that the temperature sensing signal line TS has only two cross connections with the common electrode line 108 near the corner of the non-display area BB on the DPO side, the number of cross connections is greatly reduced, the resistance ratio of the single metal is increased, and the single temperature calibration is facilitated. Specifically, as shown in FIGS. 4 and 6, in the second non-display area BB2, the common electrode line 108 can include a first sub-common electrode line 1081, a second sub-common electrode line 1082 and a third sub-common electrode line 1083 located in the gate metal layer, wherein the first sub-common electrode line 1081 is located between the second sub-common electrode line 1082 and the display area AA, the third sub-common electrode line 1083 is close to the corner of the side where the second non-display area BB2 is located, and the third sub-common electrode line 1083 is connected between the first sub-common electrode line 1081 and the second sub-common electrode line 1082; the temperature sensing signal line TS includes a first temperature sensing trace part TS1 (which can be located in the gate metal layer) located between the first sub-common electrode line 1081 and the second sub-common electrode line 1082, a second temperature sensing trace part TS2 (which can be located in the gate metal layer) located at least between the second signal line 105 (specifically, the second trace part 1053 of the second signal line 105) and the first sub-common electrode line 1081, and a third switching part TS3 (which can be located in the transparent electrode layer or the source-drain metal layer) connecting the first temperature sensing trace part TS1 and the second temperature sensing trace part TS2, in order to avoid short circuiting, the third switching part TS3 of the present disclosure intersects with the third sub-common electrode line 1083 in different layers.

[0077] In some embodiments, in order to facilitate monitoring the resistance of the temperature sensing signal line TS at different temperatures, the resistance of the temperature sensing signal line TS is preferably as large as possible. Based on this, as shown in FIGS. 4-6, the present disclosure can be configured such that the first temperature sensing trace portion TS1 includes a plurality of folded portions integrally arranged to make full use of the wiring space, so that the length of the first temperature sensing trace portion TS1 is large and the resistance is large.

[0078] In some embodiments, FIG. 7 is an enlarged structural schematic view of the Z4 region in FIG. 1. As shown in FIGS. 1 and 7, the second signal line 105 can further include a second trace portion 1053 and at least two fourth transition portions 1054; one of the fourth transition portions 1054 is arranged at the intersection position of the second signal line 105 and the sensing signal line 103; the second trace portion 1053 extends from the corresponding second binding terminal pd2 of the second signal line 105 to the intersection position, and the second trace portion 1053 includes at least one broken line, and the broken second trace portion 1053 is electrically connected through the fourth transition portion 1054. By breaking the second trace portion 1053 at least once, it is beneficial to reduce the accumulation of static electricity on the second trace portion 1053 and improve the anti-static capability. In addition, in some embodiments, the second trace portion 1053 can be located in the gate metal layer, and the fourth transition portion 1054 can be located in the source-drain metal layer or the transparent electrode layer. In the case where the fourth transition portion 1054 is located in the transparent electrode layer, because the Rs resistance of the transparent electrode layer is large and the film thickness is thin, it is easy to heat and break. Therefore, even if the second trace portion 1053 introduces static electricity, the fourth transition portion 1054, as a bridging bridge, is first melted before the static electricity enters the intersection position with the sensing signal line 103, and the static electricity cannot enter the intersection area of the second signal line 105 and the sensing signal line 103, and cannot conduct static electricity to the sensing signal line 103.

[0079] In some embodiments, as shown in FIGS. 1 and 7, the sensing signal line 103 can further include a second sensing portion 1033 and a fifth transition portion 1034 located between the gate driving circuit region GOA (including the gate driving circuit and the gate driving circuit signal line) and the display region AA in the third non-display region BB3, wherein the fifth transition portion 1034 is arranged to intersect the common electrode line 108 in different layers, and the second sensing portion 1033 is electrically connected to the first sensing portion 1031 through the fifth transition portion 1034. Optionally, the second sensing portion 1033 is located in the gate metal layer, and the fifth transition portion 1034 is located in the source-drain metal layer or the transparent electrode layer.

[0080] In some embodiments, FIG. 8 is an equivalent circuit diagram of detecting ambient light provided by an embodiment of the present disclosure, as shown in FIG. 8, the array substrate provided by an embodiment of the present disclosure further includes a plurality of transistors (e.g., TL1, TL2, TL3, TD) located in the non-display area BB (e.g., the second non-display area BB2 and / or the third non-display area BB3), and the plurality of sensing signal lines 103 include a first light sensing signal line ASG, a second light sensing signal line ASD, and a plurality of third light sensing signal lines (e.g., ASS1, ASS2, ASS3, ASS4); wherein the first light sensing signal line ASG is electrically connected with the gate of the plurality of transistors (e.g., TL1, TL2, TL3, TD), the second light sensing signal line ASD is electrically connected with the first electrode of the plurality of transistors (e.g., TL1, TL2, TL3, TD), and different third light sensing signal lines (e.g., ASS1, ASS2, ASS3, ASS4) are electrically connected with different transistors (e.g., TL1, TL2, TL3, TD). In some embodiments, the TL1 transistor is covered by a red color resist R, the TL2 transistor is covered by a green color resist G, the TL3 transistor is covered by a blue color resist B, and the TD transistor is covered by a black matrix BM, wherein the TD transistor can be used as a reference group, and in combination with the TL1 transistor, the TL2 transistor, and the TL3 transistor, the ambient light brightness and color temperature can be detected. In some embodiments, in order to reduce the occupied space of the transistor and achieve a narrow frame design, each transistor can be composed of a plurality of separated transistors RU in parallel, and the structure of the separated transistor RU is shown in FIG. 9.

[0081] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 1, 2a, 4 to 7, the array substrate can further include a feedback line (Feed) 112 located on the side of the second signal line 105 away from the first signal line 104 (the feedback line is used to monitor the change of the common signal on the side away from the binding area, and the common signal can be compensated according to the change of the common signal), an initial trigger signal line (STV) 113, a clock signal line CLK, dummy lines DY and alignment marks MK located in the transparent electrode layer and / or the gate metal layer, dummy transistors DYT located in the non-display area BB, a third electrostatic discharge structure 114 connecting the common electrode line 108 and the first signal line 104, and a fourth electrostatic discharge structure 115 connecting the common electrode line 108 and the second signal line 105, and the like. And the common electrode line 108 can extend from the second non-display area BB2 to the first non-display area BB1 through the third non-display area BB3, and be electrically connected with the second binding terminal pd2 in the first non-display area BB1. Optionally, the second binding terminal pd2 corresponding to the common electrode line 108 is located between the second binding terminal pd2 corresponding to the second signal line 105 and the second binding terminal pd2 corresponding to the feedback line 112. In addition, in order to ensure the curing effect of the sealant (Seal), a hollow structure can be arranged on the trace with a large line width (for example, the common electrode line 108, the GND line, and the ADD line). For other essential components in the array substrate, those skilled in the art should understand that they are understood, and will not be described here again, and should not be regarded as a limitation on the present disclosure.

[0082] Based on the same inventive concept, the embodiments of the present disclosure provide a display panel. FIG. 10 is a structural schematic diagram of a display panel provided by the embodiments of the present disclosure. As shown in FIG. 10, the display panel of the present disclosure includes the above-mentioned array substrate 001 provided by the embodiments of the present disclosure, and a counter substrate 002 opposite to the array substrate 001. Since the problem solving principle of the display panel is similar to that of the above-mentioned array substrate, the implementation of the display panel can be referred to the embodiments of the above-mentioned array substrate, and the repeated parts will not be described here again.

[0083] In some embodiments, in the display panel provided by the embodiments of the present disclosure, as shown in FIG. 8, the counter substrate 002 includes a black matrix BM and a color resistance CF, the black matrix BM covers the TD transistor, and the color resistance CF covers the TL1, TL2, and TL3 transistors, so that the detection of the ambient light brightness and the color temperature can be considered.

[0084] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 10, a liquid crystal layer 003 can also be arranged between the array substrate 001 and the opposite substrate 002, a first polarizer 004 can be arranged on the side of the array substrate 001 away from the opposite substrate 002, a second polarizer 005 can be arranged on the side of the opposite substrate 002 away from the array substrate 001, and the polarization direction of the first polarizer 004 is perpendicular to the polarization direction of the second polarizer 005. It should be understood by those skilled in the art that other essential components in the display panel are also understood, and are not described here in detail, nor should they be regarded as a limitation on the present disclosure.

[0085] Based on the same inventive concept, the embodiments of the present disclosure provide a display device, as shown in FIG. 11, which includes the above-mentioned display panel PNL provided in the embodiments of the present disclosure, and a backlight module BLU located on the light-in side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side type backlight module. Optionally, the side type backlight module can include a lamp strip, a reflector sheet, a light guide plate, a diffusion sheet, a prism group, etc., and the lamp strip is located on one side of the light guide plate in the thickness direction. The direct type backlight module can include a matrix light source, a reflector sheet, a diffusion plate, and a brightness enhancement film, etc., which are arranged in a stacked manner on the light-out side of the matrix light source, and the reflector sheet includes openings arranged opposite to the positions of the lamp beads in the matrix light source. The lamp beads in the lamp strip and the lamp beads in the matrix light source can be light emitting devices (LEDs), such as quantum dot light emitting devices.

[0086] In some embodiments, the lamp beads can also be micro light emitting devices (such as Mini LED, Micro LED), etc. Micro light emitting devices of sub-millimeter level or even micron level are as self-luminous devices as organic light emitting devices (OLEDs). Like organic light emitting devices, they have a series of advantages such as high brightness, ultra-low delay, and ultra-large viewing angle. And because inorganic light emitting devices emit light based on metal semiconductors with more stable properties and lower resistance, they have the advantages of lower power consumption, longer service life, and better resistance to high and low temperatures compared to organic light emitting devices that emit light based on organic matter. When micro light emitting devices are used as backlight sources, they can achieve more precise dynamic backlight effects, effectively improve screen brightness and contrast, and also solve the glare phenomenon caused by traditional dynamic backlight between bright and dark areas of the screen, and optimize the visual experience.

[0087] In some embodiments, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as a display, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigation device, a smart watch, a fitness wristband, a personal digital assistant, and the like. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through wires, signal lines, and the like arranged additionally. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate array, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate array, programmable array logic, programmable logic device, and the like. In addition, the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or arrange different components.

[0088] Although the preferred embodiments of the present disclosure have been described, those skilled in the art who are informed of the basic inventive concept can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0089] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The application relates to a substrate, which comprises a display area and a non-display area on at least one side of the display area. The substrate further comprises a plurality of binding terminals, a plurality of sensing signal lines, a first signal line, a second signal line, a common electrode bus, a common electrode line, a plurality of connection lines, a plurality of fan-out lines, a plurality of first electrostatic discharge structures, and a plurality of second electrostatic discharge structures. The plurality of binding terminals are located in the non-display area and comprise a plurality of first binding terminals and a plurality of second binding terminals. The plurality of sensing signal lines are located in the non-display area and are electrically connected to at least part of the first binding terminals. The first signal line is located on a side of the plurality of sensing signal lines away from the display area and is electrically connected to at least one of the second binding terminals. The second signal line is located between the first signal line and the plurality of sensing signal lines, and the orthographic projection of the second signal line on the substrate and the orthographic projection of at least part of the plurality of sensing signal lines on the substrate overlap with each other.

2. The array substrate of claim 1, wherein, The second signal line is electrically connected to the at least one of the second binding terminals, and the second binding terminal corresponding to the second signal line and the second binding terminal corresponding to the first signal line have at least one of the second binding terminals arranged in a floating manner. The common electrode bus is located on a side of the plurality of sensing signal lines close to the display area, the common electrode line is located on a side of at least part of the plurality of sensing signal lines away from the display area, and the plurality of connection lines are connected between the common electrode bus and the common electrode line.

3. The array substrate of claim 2, wherein, The plurality of fan-out lines are located in the non-display area and the orthographic projection of the plurality of fan-out lines on the substrate and the orthographic projection of the common electrode bus on the substrate cross each other. The fan-out line comprises an inclined portion, the plurality of fan-out lines are divided into a plurality of groups, and the extension directions of the inclined portions of adjacent two groups of the fan-out lines are opposite. The connection line comprises a widened portion, and the orthographic projection of the widened portion on the substrate is located in the orthographic projection of the gap between the inclined portions of adjacent two groups of the fan-out lines on the substrate.

4. The array substrate of claim 3, wherein, The connection line further comprises a connecting portion connecting the widened portion and the common electrode line. The second signal line comprises a first wire portion and a first switching portion located between the common electrode bus and the common electrode line.

5. The array substrate of claim 4, wherein, The first wire portion is arranged in a disconnected manner at the connecting portion.

6. The array substrate of claim 4 or 5, wherein, The first switching portion and the connecting portion are arranged in a cross manner in different layers, and the first wire portions on both sides of the first switching portion and the connecting portion are electrically connected.

7. The array substrate according to any one of claims 4 to 6, wherein, The plurality of first electrostatic discharge structures are connected between the plurality of fan-out lines and the first wire portion. The plurality of second electrostatic discharge structures are connected between the first wire portion and the widened portion. At least part of the plurality of sensing signal lines comprises a first sensing portion and a second switching portion located between the first wire portion and the common electrode line. The first sensing portion is arranged in a disconnected manner at the second switching portion. The first sensing part is discontinuously arranged at the connecting part; the second connecting part is arranged in a different layer from the connecting part and is electrically connected to the first sensing part on both sides of the connecting part.

8. The array substrate of claim 7, wherein, The at least one sensing signal line includes a plurality of light sensing signal lines, and the light sensing signal lines include the first sensing part and the second connecting part.

9. The array substrate of claim 8, wherein, The common electrode line includes a first sub-common electrode line and a second sub-common electrode line arranged integrally, and the first sub-common electrode line is located between the second sub-common electrode line and the display area. The at least one sensing signal line includes a temperature sensing signal line, and the temperature sensing signal line includes a first temperature sensing trace part located between the first sub-common electrode line and the second sub-common electrode line.

10. The array substrate of claim 9, wherein, The first temperature sensing trace part includes a plurality of fold line parts arranged integrally.

11. The array substrate of claim 9 or 10, wherein, The common electrode line further includes a third sub-common electrode line connected to the first sub-common electrode line and the second sub-common electrode line. The temperature sensing signal line further includes a second temperature sensing trace part and a third connecting part, and the third connecting part is arranged in a different layer from the third sub-common electrode line and is electrically connected to the first temperature sensing trace part and the second temperature sensing trace part.

12. The array substrate of claim 11, wherein, The third sub-common electrode line is located at a corner of the non-display area opposite to a side on which the plurality of binding terminals are located.

13. The array substrate of claim 8, wherein, The at least one sensing signal line further includes a temperature sensing signal line, and the temperature sensing signal line includes the first sensing part and the second connecting part.

14. The array substrate of any one of claims 1 to 13, wherein, The second signal line further includes a second trace part and at least two fourth connecting parts. One of the fourth connecting parts is arranged at an overlapping position of the second signal line and the sensing signal line. The second trace part extends from a corresponding second binding terminal of the second signal line to the overlapping position, and the second trace part includes at least one discontinuous line, and the discontinuous second trace part is electrically connected through the fourth connecting part.

15. The array substrate according to any one of claims 1 to 14, wherein, The first signal line is a ground line, and the second signal line is a data signal detection line.

16. The array substrate of any one of claims 1 to 15, wherein, A feedback line is further arranged on a side of the second signal line away from the first signal line.

17. The array substrate of any one of claims 1 to 16, wherein, A plurality of transistors are further arranged in the non-display area, the plurality of sensing signal lines include a first light sensing signal line, a second light sensing signal line, and a plurality of third light sensing signal lines. The first light sensing signal line is electrically connected to a gate electrode of the plurality of transistors, the second light sensing signal line is electrically connected to a first electrode of the plurality of first transistors, and different third light sensing signal lines are electrically connected to different transistors.

18. A display panel, wherein, The array substrate includes a plurality of transistors arranged in the non-display area.

19. The display panel of claim 18, wherein, The opposite substrate includes a black matrix and a color resistance, and the black matrix covers part of the transistors, and the color resistance covers the remaining transistors. The display panel includes a backlight module arranged on a light incident side of the display panel.

20. A display device comprising: ​

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