Display substrate and preparation method therefor, and display apparatus

Abstract

A display substrate and a preparation method therefor, and a display apparatus. The display substrate comprises a plurality of circuit units. Each circuit unit comprises a pixel drive circuit, a first initial signal line, a second initial signal line and a third initial signal line, wherein the pixel drive circuit at least comprises a first transistor, a seventh transistor and an eighth transistor, the first initial signal line is connected to a first electrode of the first transistor, the second initial signal line is connected to a first electrode of the seventh transistor, and the third initial signal line is connected to a first electrode of the eighth transistor; and in at least one unit row, the pixel drive circuits in at least two adjacent circuit units share the first electrode of the first transistor, the pixel drive circuits in at least two adjacent circuit units share the first electrode of the seventh transistor, and the pixel drive circuits in at least two adjacent circuit units share the first electrode of the eighth transistor. In the present disclosure, pixel drive circuits share nodes, which is conductive to achieving a high resolution.

Description

Display substrate, preparation method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202410875079.6, filed on July 1, 2024, and entitled "Display substrate, preparation method thereof and display device", the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0003] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a driving structure layer disposed on a substrate and a light emitting structure layer disposed on a side of the driving structure layer away from the substrate, the driving structure layer comprises a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprises a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line; the pixel driving circuit at least comprises a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor and an eighth transistor as a third initialization transistor, the first initial signal line is connected with a first electrode of the first transistor, the second initial signal line is connected with a first electrode of the seventh transistor, and the third initial signal line is connected with a first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share the first electrode of the eighth transistor.

[0006] In an exemplary embodiment, the first transistor includes at least a first active layer, and the first initial signal line is connected to a first region of the first active layer through a sixth connection electrode; in at least one unit row, the pixel driving circuit in adjacent circuit units shares the sixth connection electrode.

[0007] In an exemplary embodiment, the seventh transistor includes at least a seventh active layer, and the second initial signal line is connected to a first region of the seventh active layer through a second initial connection block; in at least one unit row, the pixel driving circuit in adjacent circuit units shares the second initial connection block.

[0008] In an exemplary embodiment, the eighth transistor includes at least an eighth active layer, and the third initial signal line is connected to a first region of the eighth active layer through a seventh connection electrode; in at least one unit row, the pixel driving circuit in adjacent circuit units shares the seventh connection electrode.

[0009] In an exemplary embodiment, the first initial signal line, the second initial signal line, and the third initial signal line extend along a first direction, and the driving structure layer further includes a first initial connection line, a second initial connection line, and a third initial connection line extending along a second direction, the first direction and the second direction intersecting; the first initial connection line is connected to the first initial signal line through a sixth connection electrode, forming a meshed communication structure for transmitting the first initial signal, or the second initial connection line is connected to the second initial signal line through an eighth connection electrode, forming a meshed communication structure for transmitting the second initial signal, or the third initial connection line is connected to the third initial signal line through a seventh connection electrode, forming a meshed communication structure for transmitting the third initial signal.

[0010] In an exemplary embodiment, the first initial connection line, the second initial connection line, and the third initial connection line are respectively arranged between adjacent unit columns, and the first initial connection line, the second initial connection line, the third initial connection line, and the second initial connection line are periodically arranged in the first direction.

[0011] In an example embodiment, the light-emitting structure layer includes at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units include at least a first anode, the blue light-emitting units include at least a second anode, the first green light-emitting units include at least a third anode, and the second green light-emitting units include at least a fourth anode, at least one of the first anode, the second anode, the third anode, and the fourth anode includes a main body portion and a connecting portion connected to each other, a first end of the connecting portion is connected to the main body portion, and a second end of the connecting portion is connected to an anode connection electrode in the pixel driving circuit through an anode via hole; a normal projection of the main body portion of the third anode and the main body portion of the fourth anode on the substrate at least partially overlaps with a normal projection of the first initial connection line on the substrate, or a normal projection of the main body portion of the third anode and the main body portion of the fourth anode on the substrate at least partially overlaps with a normal projection of the second initial connection line on the substrate, or a normal projection of the main body portion of the third anode and the main body portion of the fourth anode on the substrate at least partially overlaps with a normal projection of the third initial connection line on the substrate.

[0012] In an example embodiment, in a direction perpendicular to the substrate, the driving structure layer includes at least a first conductive layer disposed on the substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate, the first initial signal line, the second initial signal line, and the third initial signal line are disposed in at least one of the second conductive layer and the third conductive layer, and the first initial connection line, the second initial connection line, and the third initial connection line are disposed in the fourth conductive layer.

[0013] In an example embodiment, the driving structure layer further includes a first planar layer disposed on a side of the third conductive layer away from the substrate, and the fourth conductive layer is disposed on a side of the first planar layer away from the substrate; at least one circuit unit further includes a connection via hole, and the third initial connection line is connected to the seventh connection electrode through the connection via hole; and at least another circuit unit further includes a dummy via hole, and the first initial connection line and / or the second initial connection line is at least partially disposed in the dummy via hole.

[0014] In an example embodiment, the light-emitting structure layer includes at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units include at least a first anode, the blue light-emitting units include at least a second anode, the first green light-emitting units include at least a third anode, and the second green light-emitting units include at least a fourth anode, at least one of the first anode, the second anode, the third anode, and the fourth anode includes a main body portion and a connecting portion connected to each other, a first end of the connecting portion is connected to the main body portion, and a second end of the connecting portion is connected to an anode connection electrode in the pixel driving circuit through an anode via hole; a normal projection of the main body portion of the third anode on the substrate at least partially overlaps a normal projection of the connecting via hole on the substrate, and a normal projection of the main body portion of the fourth anode on the substrate at least partially overlaps a normal projection of the dummy via hole on the substrate; or, a normal projection of the main body portion of the third anode on the substrate at least partially overlaps a normal projection of the dummy via hole on the substrate, and a normal projection of the main body portion of the fourth anode on the substrate at least partially overlaps a normal projection of the connecting via hole on the substrate.

[0015] In an example embodiment, the light-emitting structure layer includes at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units include at least a first anode, the blue light-emitting units include at least a second anode, the first green light-emitting units include at least a third anode, and the second green light-emitting units include at least a fourth anode, at least one of the first anode, the second anode, the third anode, and the fourth anode includes a main body portion and a connecting portion connected to each other, a first end of the connecting portion is connected to the main body portion, and a second end of the connecting portion is connected to an anode connection electrode in the pixel driving circuit through an anode via hole; a normal projection of the main body portion of the third anode on the substrate at least partially overlaps a normal projection of the connecting via hole on the substrate, and a normal projection of the main body portion of the fourth anode on the substrate at least partially overlaps a normal projection of the dummy via hole on the substrate; or, a normal projection of the main body portion of the third anode on the substrate at least partially overlaps a normal projection of the dummy via hole on the substrate, and a normal projection of the main body portion of the fourth anode on the substrate at least partially overlaps a normal projection of the connecting via hole on the substrate.

[0016] In an exemplary embodiment, the eighth connection electrode includes a connection electrode strip and a connection electrode block, the connection electrode strip has a shape of a strip shape extending along the second direction, the connection electrode block has a shape of a block shape, a first end of the connection electrode strip is connected with the second initial signal line, a second end of the connection electrode strip extends in a direction away from the second initial signal line and is connected with the connection electrode block, and the second initial connection line is connected with the connection electrode block through a via hole; the at least one circuit unit further includes a dummy electrode strip, a first end of the dummy electrode strip is connected with the second initial signal line, and a second end of the dummy electrode strip extends in a direction away from the second initial signal line; the connection electrode strip and the dummy electrode strip are alternately arranged in the first direction.

[0017] In an exemplary embodiment, the at least one circuit unit further includes a dummy electrode block and a dummy via hole, the dummy electrode block has a shape of a block shape and is connected with the second end of the dummy electrode strip, a projection of the dummy via hole on the substrate is located within a range of a projection of the dummy electrode block on the substrate, and the first initial connection line and / or the third initial connection line is / are at least partially arranged in the dummy via hole.

[0018] In an exemplary embodiment, the connection electrode block and the dummy electrode block are located on a straight line extending along the first direction.

[0019] In an exemplary embodiment, the light-emitting structure layer includes at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units include at least a first anode, the blue light-emitting units include at least a second anode, the first green light-emitting units include at least a third anode, the second green light-emitting units include at least a fourth anode, at least one of the first anode, the second anode, the third anode, and the fourth anode includes a main body portion and a connection portion connected with each other, a first end of the connection portion is connected with the main body portion, and a second end of the connection portion is connected with an anode connection electrode in the pixel driving circuit through an anode via hole; a projection of the main body portion of the third anode on the substrate at least partially overlaps with a projection of the connection electrode strip on the substrate, and a projection of the main body portion of the fourth anode on the substrate at least partially overlaps with a projection of the dummy electrode strip on the substrate; or, a projection of the main body portion of the third anode on the substrate at least partially overlaps with a projection of the dummy electrode strip on the substrate, and a projection of the main body portion of the fourth anode on the substrate at least partially overlaps with a projection of the connection electrode strip on the substrate.

[0020] In an exemplary embodiment, the pixel driving circuit further comprises a second transistor as a compensation transistor and a third transistor as a driving transistor, a first electrode of the second transistor is connected with a second electrode of the first transistor and a gate electrode of the third transistor respectively, and a second electrode of the second transistor is connected with a second electrode of the third transistor; the first transistor and the second transistor are double-gate structures.

[0021] In an exemplary embodiment, the driving structure layer further comprises a plurality of data signal lines extending along a second direction, a plurality of first connection lines extending along a first direction, and a plurality of second connection lines extending along the second direction, the first direction and the second direction intersecting; at least one data signal line is connected with a plurality of pixel driving circuits of one unit column, first ends of the plurality of first connection lines are connected with the plurality of data signal lines correspondingly, and second ends of the plurality of first connection lines are connected with the plurality of second connection lines correspondingly.

[0022] In an exemplary embodiment, the light-emitting structure layer comprises at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units comprise at least first anodes, the blue light-emitting units comprise at least second anodes, the first green light-emitting units comprise at least third anodes, and the second green light-emitting units comprise at least fourth anodes, at least one of the first anodes, the second anodes, the third anodes, and the fourth anodes comprises a main body portion and a connecting portion connected with each other, a first end of the connecting portion is connected with the main body portion, and a second end of the connecting portion is connected with an anode connection electrode in the pixel driving circuit through an anode via hole; a normal projection of the main body portion of the first anode and a normal projection of the main body portion of the second anode on the substrate at least partially overlap with a normal projection of the second connection lines on the substrate.

[0023] In an exemplary embodiment, the driving structure layer further comprises a data connection electrode, the second connection lines are connected with the data connection electrode through the via holes; a normal projection of the data connection electrode on the substrate is located within a range of the normal projection of the main body portion of the first anode on the substrate, and / or a normal projection of the data connection electrode on the substrate is located within a range of the normal projection of the main body portion of the second anode on the substrate.

[0024] In another aspect, the present disclosure also provides a display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and at least one initial signal line; the pixel driving circuit comprising at least one initialization transistor, and the initial signal line being connected with the initialization transistor through a connection electrode; in at least one unit row, two initialization transistors in adjacent circuit units are connected with the connection electrode through a same via, or two connection electrodes in adjacent circuit units are connected with the initial signal line through a same via.

[0025] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0026] In another aspect, the present disclosure also provides a preparation method of a display substrate, comprising:

[0027] forming a driving structure layer on a substrate; the driving structure layer comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line; the pixel driving circuit comprising at least a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor and an eighth transistor as a third initialization transistor, the first initial signal line being connected with a first electrode of the first transistor, the second initial signal line being connected with a first electrode of the seventh transistor, and the third initial signal line being connected with a first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share the first electrode of the eighth transistor;

[0028] forming a light-emitting structure layer on the driving structure layer.

[0029] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings are included to provide a further understanding of the present disclosure, and constitute a part of this specification that is made of the description of the present disclosure, together with the embodiments of the present disclosure, for explaining the technical scheme of the present disclosure, and do not constitute a limitation to the technical scheme of the present disclosure.

[0031] FIG. 1 is a structural schematic diagram of a display device;

[0032] FIG. 2 is a structural schematic diagram of a display substrate;

[0033] FIG. 3 is a planar structural schematic diagram of a display area in a display substrate;

[0034] FIG. 4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate;

[0035] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit;

[0036] FIG. 6 is a schematic diagram of a structure of a data connection line according to an exemplary embodiment of the present disclosure;

[0037] FIG. 7 is a schematic diagram of a structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0038] FIG. 8 is a schematic diagram of another structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0039] FIG. 9 is a schematic diagram after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure;

[0040] FIGS. 10A and 10B are schematic diagrams after forming a first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0041] FIGS. 11A and 11B are schematic diagrams after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0042] FIG. 12 is a schematic diagram after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0043] FIGS. 13A, 13B and 13C are schematic diagrams after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0044] FIG. 14 is a schematic diagram after forming a fifth insulating layer and a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0045] FIGS. 15A and 15B are schematic diagrams after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0046] FIG. 16 is a schematic diagram after forming a second planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0047] FIGS. 17A and 17B are schematic diagrams after forming an anode conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0048] FIG. 17C is a schematic diagram of a positional relationship between the anode conductive layer and the third conductive layer in FIG. 17A.

[0049] Explanation of reference numerals: 11-first active layer; 12-second active layer; 13-third active layer; 14-fourth active layer; 15-fifth active layer; 16-sixth active layer; 17-seventh active layer; 18-eighth active layer; 21-first scan signal line; 22-second scan signal line; 23-third scan signal line; 24-emission signal line; 31-first plate; 32-second plate; 33-opening; 34-plate connecting strip; 41-first initial signal line; 42-second initial signal line; 43-third initial signal line; 51-first connecting electrode; 52-second connecting electrode; 53-third connecting electrode; 54-fourth connecting electrode; 55-fifth connecting electrode; 56-sixth connecting electrode; 57-seventh connecting electrode; 58-eighth connecting electrode; 59-virtual electrode strip; 61-first shielding electrode; 62-second shielding electrode; 63-third shielding electrode; 64-fourth shielding electrode; 71-first power supply line; 72-data signal line; 73-anode connecting electrode; 80-data lead-out line; 81-first connecting line; 82-second connecting line; 83-data connecting electrode; 84-data connecting block; 90A-first anode; 90B-second anode; 90C-third anode; 90D-fourth anode; 91-first initial connecting line; 92-second initial connecting line; 93-third initial connecting line; 100-display area; 101-substrate; 102-driving structure layer; 103-emission structure layer; 104-encapsulation structure layer; 200-bonding area; 300-bezel area. DETAILED DESCRIPTION

[0050] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically explain the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0051] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0052] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of components, and are not intended to be limited in terms of quantity.

[0053] In the present specification, for the convenience of explanation, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0054] In the present specification, unless specifically defined and limited otherwise, the terms "mount", "connected", "connected" should be broadly understood. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or the communication between two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0055] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0056] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0057] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0058] In this specification, "parallel" means a state where the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0059] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0060] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or the like. In this specification, "about" means that a value includes a range of error due to a process and measurement.

[0061] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, an emission driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the emission driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the emission driver is connected with a plurality of emission signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and an emission unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the emission signal line, and the data signal line respectively, and the emission unit can include an emission device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the emission driver to the emission driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn by using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value by using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. The scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The emission driver can generate emission signals to be provided to the emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the emission driver can sequentially provide the emission signal having an off-level pulse to the emission signal lines E1 to Eo. The emission driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0062] FIG. 2 is a structural schematic diagram of a display substrate. As shown in FIG. 2, the display substrate can include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 can be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij being configured to display dynamic pictures or still images, and the display area 100 can be referred to as an active area (AA). In an exemplary embodiment, the display substrate can adopt a flexible substrate, and thus the display substrate can be deformable, for example, curled, bent, folded, or rolled up.

[0063] In an exemplary embodiment, the binding area 200 can include, in sequence along a direction away from the display area, an outgoing line area, a bending area, a driving chip area, and a binding pin area, the outgoing line area being connected to the display area 100 and including at least data outgoing lines. The bending area can be connected to the outgoing line area and can include at least a composite insulating layer provided with a groove configured to bend the binding area to the back of the display area. The driving chip area can include an integrated circuit (IC) configured to be connected to the plurality of data outgoing lines. The binding pin area can include a bonding pad configured to be connected to an external flexible printed circuit (FPC).

[0064] In an exemplary embodiment, the frame area 300 can include, in sequence along a direction away from the display area 100, a circuit area, a power line area, a crack dam area, and a cutting area. The circuit area can be connected to the display area 100 and can include at least a gate drive circuit connected to a scanning signal line and a light-emitting signal line in the display area 100. The power line area can be connected to the circuit area and can include at least a frame power lead extending along a direction parallel to an edge of the display area and connected to a cathode in the display area 100. The crack dam area can be connected to the power line area and can include at least a plurality of cracks provided on a composite insulating layer. The cutting area can be connected to the crack dam area and can include at least a cutting groove provided on the composite insulating layer, the cutting groove being configured to be cut by a cutting device along the cutting groove after all film layers of the display substrate are prepared.

[0065] In an exemplary embodiment, the outgoing line area in the binding area 200 and the power line area in the frame area 300 can be provided with an isolation dam, the isolation dam can extend along a direction parallel to an edge of the display area, forming a ring structure surrounding the display area 100, and the edge of the display area is an edge on one side of the display area, the binding area, or the frame area.

[0066] FIG. 3 is a schematic diagram of a planar structure of a display region in a display substrate. As shown in FIG. 3, the display region can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel can include a circuit unit and a light-emitting unit, and the circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit can include a light-emitting device connected to the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0067] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, the third sub-pixel P3 can be a first green sub-pixel (G1) that emits green light, and the fourth sub-pixel P4 can be a second green sub-pixel (G2) that emits green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG manner.

[0068] In other example embodiments, the pixel unit P can include three sub-pixels arranged in a horizontal parallel manner or a vertical parallel manner, and the present disclosure does not limit the arrangement of the three sub-pixels.

[0069] FIG. 4 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of four sub-pixels in the display region. As shown in FIG. 4, in a plane perpendicular to the display substrate, the display region can include a driving structure layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display region can include other film layers, such as a touch structure layer, and the present disclosure does not limit the film layers.

[0070] In an example embodiment, the substrate 101 can be a flexible substrate or can be a rigid substrate. The driving structure layer 102 can include a plurality of circuit units, each of which can include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can include a plurality of light-emitting units, each of which can include a light-emitting device that can include at least an anode, an organic light-emitting layer, and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, the organic light-emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulating structure layer 104 can include a first encapsulating layer, a second encapsulating layer, and a third encapsulating layer stacked together, the first encapsulating layer and the third encapsulating layer can be made of inorganic material, and the second encapsulating layer can be made of organic material, the second encapsulating layer being arranged between the first encapsulating layer and the third encapsulating layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0071] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit. In an example embodiment, the pixel driving circuit can be of a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit can include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and is connected to 9 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, light-emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0072] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first terminal of the storage capacitor C, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0073] In an example embodiment, the first terminal of the storage capacitor C is connected to the first node N1, and the second terminal of the storage capacitor C is connected to the first power supply line VDD.

[0074] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1.

[0075] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0076] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0077] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0078] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the emission signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0079] In an exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the emission signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0080] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the third scan signal line S3, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0081] In an exemplary embodiment, the gate electrode of the eighth transistor T8 is connected to the third scan signal line S3, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0082] In the example implementation, the pixel driving circuit can realize normal driving and low-frequency driving. In a scenario where the refresh rate requirement is not high, low-frequency refresh can be used to save power consumption. When normally driven, the driving timing of the pixel driving circuit can include four stages of initialization, compensation, data writing, and light emission. When low-frequency driven, the driving timing of the pixel driving circuit can include six stages of initialization, compensation, data writing, light emission, adjustment, and re-light emission. In the adjustment stage, the eighth transistor T8 is used to write a third initial signal (bias voltage) to the first electrode of the third transistor T3, so that the bias state of the third transistor T3 is consistent with the bias state when the data signal is just written. This can not only improve the stability of the working state of the driving transistor and improve the low-frequency flicker (Fliker), but also effectively improve the hysteresis of the third transistor, which is conducive to improving the afterimage and improving the display effect.

[0083] In the example implementation, the first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

[0084] In the example implementation, the first power supply line VDD is configured to provide a constant first power supply signal to the pixel driving circuit, the second power supply line VSS is configured to provide a constant second power supply signal to the light emitting device, and the first power supply signal is a high-level signal and the second power supply signal is a low-level signal. The first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3 are configured to provide constant first initial signals, second initial signals, and third initial signals to the pixel driving circuit, respectively, which are not limited in the present disclosure.

[0085] In the example implementation, the first transistor T1 to the eighth transistor T8 in the pixel driving circuit can be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 can include P-type transistors and N-type transistors.

[0086] In an example embodiment, the first transistor T1 to the eighth transistor T8 can adopt a low temperature poly-silicon transistor, or can adopt an oxide transistor, or can adopt a low temperature poly-silicon transistor and an oxide transistor. The active layer of the low temperature poly-silicon transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon transistor and the oxide transistor on one display substrate forms an LTPO (Low Temperature Polycrystalline+Oxide) display substrate, which can take advantage of both and can achieve low-frequency driving, reduce power consumption, and improve display quality.

[0087] With the development of OLED display technology, consumers have increasingly high requirements for display products in terms of display effect and display quality, and narrow frame has become a new trend in the development of display products. Therefore, the narrowing of the frame or even the frameless design is increasingly valued in the design of OLED display products. In a display substrate, the data signals of the integrated circuit in the binding area need to be introduced into the wider display area in a fanout manner through the data lead-out lines, so that the lead-out line area occupies a larger space, resulting in a larger lower frame width.

[0088] To reduce the width of the lower frame, an example embodiment of the present disclosure provides a display substrate adopting a fanout in panel (FIP) structure. A plurality of data connection lines are arranged in the display area. The data connection lines can include first connection lines and second connection lines. The first ends of the plurality of first connection lines are connected to the plurality of data signal lines in the display area in a corresponding manner. The second ends of the plurality of first connection lines are connected to the first ends of the plurality of second connection lines in a corresponding manner. The second ends of the plurality of second connection lines extend to the binding area and are connected to the integrated circuit in a corresponding manner through the plurality of lead-out lines in the lead-out line area. Since the lead-out line area does not need to be provided with fan-shaped diagonal lines, the width of the lead-out line area is reduced, thereby reducing the width of the lower frame.

[0089] FIG. 6 is a structural schematic diagram of a data connection line according to an exemplary embodiment of the present disclosure, the data connection line adopting a FIP structure. As shown in FIG. 6, in a plane parallel to the display substrate, the display substrate can include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. The driving structure layer of the display area 100 can include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines 72, a plurality of first connection lines 81, and a plurality of second connection lines 82, at least one circuit unit can include a pixel driving circuit configured to output a corresponding current to the connected light emitting device. The light emitting structure layer of the display area 100 can include a plurality of light emitting units, at least one light emitting unit can include a light emitting device connected with the pixel driving circuit of the corresponding circuit unit, the light emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0090] In an exemplary embodiment, the circuit unit referred to in the present disclosure refers to an area divided according to the pixel driving circuit, and the light emitting unit referred to in the present disclosure refers to an area divided according to the light emitting device. In an exemplary embodiment, the position of the light emitting unit orthogonally projected on the substrate can correspond to the position of the circuit unit orthogonally projected on the substrate, or the position of the light emitting unit orthogonally projected on the substrate can not correspond to the position of the circuit unit orthogonally projected on the substrate.

[0091] In an exemplary embodiment, the plurality of circuit units arranged in sequence along the first direction X can be referred to as a unit row, the plurality of circuit units arranged in sequence along the second direction Y can be referred to as a unit column, the plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X and the second direction Y intersect each other.

[0092] In an exemplary embodiment, the first direction X can be a unit row direction, the second direction Y can be a unit column direction, and the first direction X and the second direction Y can be perpendicular to each other.

[0093] In the example embodiment, the first connecting line 81 can be in a straight line shape or a broken line shape extending along the first direction X, and the data signal line 72 and the second connecting line 82 can be in a straight line shape or a broken line shape extending along the second direction Y. A plurality of data signal lines 72 are arranged in a set interval along the first direction X, at least one data signal line 72 is connected to a plurality of pixel driving circuits in a unit column, and the data signal line 72 is configured to provide a data signal to the connected pixel driving circuit. The first end of at least one first connecting line 81 is connected to a data signal line 72, the second end is connected to the first end of a second connecting line 82, and the second end of the second connecting line 82 is connected to a data lead-out line 80 after extending to the binding area, so that the data signal line 72 in the display area is connected to the data lead-out line 80 in the binding area 200 through the first connecting line 81 and the second connecting line 82, forming an FIP structure (also referred to as an FIAA structure). In the example embodiment, the first connecting line 81 and the second connecting line 82 are collectively referred to as a data connecting line.

[0094] In the example embodiment, the binding area 200 can include a lead-out line area, a bending area, a driving chip area, and a binding pin area arranged in sequence away from the display area, the lead-out line area is connected to the display area, and the bending area is connected to the lead-out line area. The lead-out line area can be provided with a plurality of data lead-out lines 80, and the plurality of data lead-out lines 80 extend away from the display area. The first end of a part of the data lead-out lines 80 is connected to the second connecting line 82 in the display area 100, and the first end of another part of the data lead-out lines 80 is connected to the data signal line 72 in the display area 100. The second end of all the data lead-out lines 80 is connected to the integrated circuit of the driving chip area after crossing the bending area along the second direction Y, so that the integrated circuit applies a data signal to the data signal line through the data lead-out line and the data connecting line. Since the first connecting line 81 and the second connecting line 82 are arranged in the display area, the length of the lead-out line area in the second direction Y can be effectively reduced, the lower frame width is greatly reduced, the screen-to-body ratio is improved, and the full-screen display is facilitated.

[0095] In the example embodiment, the number of data connecting lines in the display area can be the same as the number of data signal lines, and each data signal line is connected to a lead-out line through a data connecting line. Alternatively, the number of data connecting lines in the display area can be less than the number of data signal lines, and a part of the data signal lines in the display area are connected to the lead-out line through the data connecting line, and the other part of the data signal lines are directly connected to the lead-out line, which is not limited in the present disclosure.

[0096] The exemplary embodiments of the present disclosure provide a display substrate, comprising a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the driving structure layer comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line; the pixel driving circuit comprising a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor and an eighth transistor as a third initialization transistor, the first initial signal line being connected with a first electrode of the first transistor, the second initial signal line being connected with a first electrode of the seventh transistor, and the third initial signal line being connected with a first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share the first electrode of the eighth transistor.

[0097] In the exemplary embodiments, the first transistor at least comprises a first active layer, the first initial signal line is connected with a first region of the first active layer through a sixth connection electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the sixth connection electrode.

[0098] In the exemplary embodiments, the seventh transistor at least comprises a seventh active layer, the second initial signal line is connected with a first region of the seventh active layer through a second initial connection block; in at least one unit row, the pixel driving circuits in adjacent circuit units share the second initial connection block.

[0099] In the exemplary embodiments, the eighth transistor at least comprises an eighth active layer, the third initial signal line is connected with a first region of the eighth active layer through a seventh connection electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the seventh connection electrode.

[0100] In the exemplary embodiments, the pixel driving circuit further comprises a second transistor as a compensation transistor and a third transistor as a driving transistor, a first electrode of the second transistor being connected with a second electrode of the first transistor and a gate electrode of the third transistor respectively, and a second electrode of the second transistor being connected with a second electrode of the third transistor; the first transistor and the second transistor are double-gate structures.

[0101] In an example embodiment, the driving structure layer further comprises a plurality of data signal lines extending along the second direction, a plurality of first connection lines extending along the first direction, and a plurality of second connection lines extending along the second direction, the first direction and the second direction intersecting; at least one data signal line is connected to the plurality of pixel driving circuits of one unit column, first ends of the plurality of first connection lines are connected to the plurality of data signal lines correspondingly, and second ends of the plurality of first connection lines are connected to the plurality of second connection lines correspondingly.

[0102] FIG. 7 is a structural schematic diagram of a display substrate according to an example embodiment of the present disclosure, which illustrates the structure of 8 circuit units of one circuit row (Mth unit row) and 8 circuit columns (Nth unit column to N+7th unit column). As shown in FIG. 7, in a direction perpendicular to the display substrate, the display substrate can at least include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. In a plane parallel to the substrate, the driving structure layer can include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit can include a pixel driving circuit, and the pixel driving circuit can be connected to a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light-emitting signal line 24, a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a first power supply line 71, and a data signal line 72, respectively. The first scan signal line 21 to the third scan signal line 23 are configured to provide the pixel driving circuit with a first scan signal to a third scan signal, respectively; the light-emitting signal line 24 is configured to provide the pixel driving circuit with a light-emitting control signal; the first initial signal line 41 to the third initial signal line 43 are configured to provide the pixel driving circuit with a first initial signal to a third initial signal, respectively; the first power supply line 71 is configured to provide the pixel driving circuit with a first power supply signal; and the data signal line 72 is configured to provide the pixel driving circuit with a data signal. Wherein the plurality of signal lines connected to the pixel driving circuit can be located within the circuit unit.

[0103] In an example embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the light-emitting signal line 24, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 can have a shape of a straight line or a broken line with a main body part extending along the first direction X; and the first power supply line 71 and the data signal line 72 can have a shape of a straight line or a broken line with a main body part extending along the second direction Y.

[0104] In the present disclosure, A extending along a direction of B means that A can include a main portion and a sub-portion connected to the main portion, the main portion is a line, a line segment or a bar-shaped body, the main portion extends along the direction of B, and the length of the main portion extending along the direction of B is greater than the length of the sub-portion extending along other directions. In the following description, "A extending along the direction of B" means "the main portion of A extending along the direction of B".

[0105] In an exemplary embodiment, the pixel driving circuit can include at least a storage capacitor and eight polysilicon transistors. The eight polysilicon transistors can include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting control transistor, a sixth transistor T6 as a second light emitting control transistor, a seventh transistor T7 as a second initialization transistor, and an eighth transistor T8 as a third initialization transistor, and the storage capacitor can include a first plate and a second plate stacked.

[0106] In an exemplary embodiment, the first transistor T1 and the second transistor T2 can be transistors of a double-gate structure.

[0107] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line 22, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2 and the first plate of the storage capacitor (also the gate electrode of the third transistor T3), respectively. The gate electrode of the second transistor T2 is connected to the first scan signal line 21, and the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, respectively. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, the first electrode of the fourth transistor T4 is connected to the data signal line 72, and the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The gate electrode of the fifth transistor T5 is connected to the light emitting signal line 24, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line 24, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected to the third scan signal line 23, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected to the third scan signal line 23, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.

[0108] In the exemplary embodiment, in at least one circuit unit, the first scan signal line 21 can be disposed on the side of the storage capacitor (third transistor T3) in the opposite direction of the second direction Y, the first initial signal line 41 can be disposed on the side of the first scan signal line 21 away from the storage capacitor, and the second scan signal line 22 can be disposed on the side of the first initial signal line 41 away from the storage capacitor, i.e., the first initial signal line 41 is disposed between the first scan signal line 21 and the second scan signal line 22. The light emission signal line 24 can be disposed on the side of the storage capacitor in the second direction Y, the third scan signal line 23 can be disposed on the side of the light emission signal line 24 away from the storage capacitor, the second initial signal line 42 can be disposed on the side of the third scan signal line 23 away from the storage capacitor, and the third initial signal line 43 can be disposed on the side of the second initial signal line 42 away from the storage capacitor, i.e., the second initial signal line 42 and the third initial signal line 43 are both disposed on the side of the third scan signal line 23 away from the storage capacitor.

[0109] In the exemplary embodiment, in at least one unit row, the pixel drive circuits in adjacent circuit units can be symmetrically disposed relative to a column center line, which can be a straight line located between two adjacent unit columns and extending along the second direction Y. For example, the pixel drive circuits in the Nth unit column and the (N+1)th unit column can be symmetrically disposed relative to the column center line. For another example, the pixel drive circuits in the (N+1)th unit column and the (N+2)th unit column can be symmetrically disposed relative to the column center line. In the exemplary embodiment, N can be a positive integer greater than 1.

[0110] In the exemplary embodiment, in at least one unit row, the pixel drive circuits in adjacent circuit units can share the first electrode of the first transistor T1, the pixel drive circuits in adjacent circuit units can share the first electrode of the seventh transistor T7, and the pixel drive circuits in adjacent circuit units can share the first electrode of the eighth transistor T8. For example, the pixel drive circuits in the Nth unit column and the (N+1)th unit column can share the first electrode of the first transistor T1. The pixel drive circuits in the (N+1)th unit column and the (N+2)th unit column can share the first electrode of the seventh transistor T7, and the pixel drive circuits in the Nth unit column and the (N+1)th unit column can share the first electrode of the eighth transistor T8.

[0111] In the exemplary embodiment, in at least one circuit unit, the first transistor T1 can include at least a first active layer, the first initial signal line 41 can be connected to the first region of the first active layer through a sixth connection electrode 56, and the sixth connection electrode 56 can serve as the first electrode of the first transistor T1. In at least one unit row, the first active layers in adjacent circuit units can be an integrated structure connected to each other, the pixel drive circuits in adjacent circuit units share the first region of the first active layer, and the pixel drive circuits in adjacent circuit units share the sixth connection electrode 56.

[0112] In the example embodiment, in at least one circuit unit, the seventh transistor T7 can include at least a seventh active layer, the second initial signal line 42 can be connected to a first region of the seventh active layer through a second initial connection block 42-1, and the second initial connection block 42-1 can serve as a first electrode of the seventh transistor T7. In at least one unit row, the seventh active layers in adjacent circuit units can be an integral structure connected to each other, the pixel driving circuits in adjacent circuit units share the first region of the seventh active layer, and the pixel driving circuits in adjacent circuit units share the second initial connection block 42-1.

[0113] In the example embodiment, in at least one circuit unit, the eighth transistor T8 can include at least an eighth active layer, the third initial signal line 43 can be connected to a first region of the eighth active layer through a seventh connection electrode 57, and the seventh connection electrode 57 can serve as a first electrode of the eighth transistor T8. In at least one unit row, the first regions of the eighth active layers in adjacent circuit units can be symmetrically arranged with respect to the column center line, the seventh connection electrodes 57 in adjacent circuit units can be symmetrically arranged with respect to the column center line, and the seventh connection electrodes 57 in adjacent circuit units can be an integral structure connected to each other.

[0114] In the example embodiment, the driving structure layer can further include at least one first initial connection line 91, at least one second initial connection line 92, and at least one third initial connection line 93. The first initial connection line 91, the second initial connection line 92, and the third initial connection line 93 can have a shape of a straight line or a broken line extending along the second direction Y and can be arranged between two data signal lines 72 in adjacent unit columns, respectively. The two data signal lines 72 in adjacent unit columns can be symmetrically arranged with respect to the corresponding initial connection line.

[0115] In the example embodiment, the first initial connection line 91 can be connected to the first initial signal line 41 through the sixth connection electrode 56 to form a mesh communication structure for transmitting the first initial signal. The second initial connection line 92 can be connected to the second initial signal line 42 through the eighth connection electrode 58 to form a mesh communication structure for transmitting the second initial signal. The third initial connection line 93 can be connected to the third initial signal line 43 through the seventh connection electrode 57 to form a mesh communication structure for transmitting the third initial signal.

[0116] In an exemplary embodiment, the first initial connection lines 91, the second initial connection lines 92, the third initial connection lines 93 and the second initial connection lines 92 can be periodically arranged in the first direction X. For example, the first initial connection lines 91 can be arranged between the data signal lines 72 of the Nth unit column and the N+lth unit column, the second initial connection lines 92 can be arranged between the data signal lines 72 of the N+2th unit column and the N+3th unit column, and between the data signal lines 72 of the N+6th unit column and the N+7th unit column, and the third initial connection lines 93 can be arranged between the data signal lines 72 of the N+4th unit column and the N+5th unit column.

[0117] In an exemplary embodiment, two second initial connection lines 92 and one third initial connection line 93 can be arranged between two first initial connection lines 91 adjacent in the first direction X, one first initial connection line 91 or one third initial connection line 93 can be arranged between two second initial connection lines 92 adjacent in the first direction X, and one first initial connection line 91 and two second initial connection lines 92 can be arranged between two third initial connection lines 93 adjacent in the first direction X.

[0118] In an exemplary embodiment, the driving structure layer can further include at least one first connection line 81 and at least one second connection line 82, the shape of the first connection line 81 can be a straight line or a broken line extending in the first direction X, and the shape of the second connection line 82 can be a straight line or a broken line extending in the second direction Y. The at least one first connection line 81 is connected with the data signal line 72 and the second connection line 82 respectively, forming a structure in which the data connection line is located in the display area.

[0119] In an exemplary embodiment, in the second direction Y, the at least one first connection line 81 can be arranged between the second scan signal line 22 and the first initial signal line 41. In the first direction X, the at least one second connection line 82 can be arranged between the first power supply 71 of the partial adjacent unit columns, and the two first power supplies 71 in the adjacent unit columns can be symmetrically arranged with respect to the second connection line 8.

[0120] In an example embodiment, two circuit units can be spaced apart between adjacent second connection lines 82 in the first direction X. For example, the second connection line 82 can be provided between the first power supply 71 of the N-1th unit column and the Nth unit column. For another example, the second connection line 82 can be provided between the first power supply 71 of the N+1th unit column and the N+2th unit column. For another example, the second connection line 82 can be provided between the first power supply 71 of the N+3th unit column and the N+4th unit column. For another example, the second connection line 82 can be provided between the first power supply 71 of the N+5th unit column and the N+6th unit column. For another example, the second connection line 82 can be provided between the first power supply 71 of the N+7th unit column and the N+8th unit column.

[0121] In an example embodiment, the second connection line 82 and the initial connection line (the first initial connection line 91, the second initial connection line 92, and the third initial connection line 93) can be alternately provided in the first direction X.

[0122] In an example embodiment, the at least one circuit unit can further include a first shield electrode 61, which can be connected with the third initial signal line 43. A projection of the first shield electrode 61 on the substrate at least partially overlaps a projection of a first active layer between two gate electrodes of the first transistor T1 on the substrate, and the first shield electrode 61 and the first active layer between the two gate electrodes of the first transistor T1 form a coupling capacitor.

[0123] In an example embodiment, the at least one circuit unit can further include a second shield electrode 62, which is connected with the first initial signal line 41. A projection of the second shield electrode 62 on the substrate at least partially overlaps a projection of a second active layer between two gate electrodes of the second transistor T2 on the substrate, and the second shield electrode 62 and the second active layer between the two gate electrodes of the second transistor T2 form a coupling capacitor.

[0124] In an example embodiment, the at least one circuit unit can further include a third shield electrode 63, which is connected with the first initial signal line 41. A projection of the third shield electrode 63 on the substrate at least partially overlaps a projection of a second region of the first active layer on the substrate, and a projection of the third shield electrode 63 on the substrate at least partially overlaps a projection of the first connection line 81 on the substrate. The projection of the first connection line 81 on the substrate and the projection of the second region of the first active layer on the substrate have an overlapping region, and the projection of the third shield electrode 63 on the substrate can include the overlapping region.

[0125] In the example embodiment, the at least one circuit unit can further include a fourth shielding electrode 64 connected with the first initial signal line 41. In the first direction X, the fourth shielding electrode 64 can be located between the first electrode of the second transistor T2 (also the second electrode of the first transistor T1) and the first electrode of the fourth transistor T4.

[0126] In the example embodiment, in the direction perpendicular to the substrate, the driving structure layer can include at least a first conductive layer disposed on the substrate, a second conductive layer disposed on the side of the first conductive layer away from the substrate, a third conductive layer disposed on the side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on the side of the third conductive layer away from the substrate. The first initial signal line 41 and the second initial signal line 42 can be disposed in the second conductive layer, the third initial signal line 43 and the first connection line 81 can be disposed in the third conductive layer, and the second connection line 82, the first initial connection line 91, the second initial connection line 92, and the third initial connection line 93 can be disposed in the fourth conductive layer.

[0127] FIG. 8 is a structural schematic diagram of another display substrate of an example embodiment of the present disclosure, illustrating the structure of the fourth conductive layer and the anode conductive layer. As shown in FIG. 8, in the direction perpendicular to the display substrate, the light-emitting structure layer can include at least an anode conductive layer disposed on the side of the driving structure layer away from the substrate, a pixel definition layer disposed on the side of the anode conductive layer away from the substrate, an organic light-emitting layer disposed on the side of the pixel definition layer away from the substrate, a cathode layer disposed on the side of the organic light-emitting layer away from the substrate, and an encapsulation structure layer disposed on the side of the cathode layer away from the substrate. In the direction parallel to the display substrate, the light-emitting structure layer can include at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units can include at least a first anode 90A, the blue light-emitting units can include at least a second anode 90B, the first green light-emitting units can include at least a third anode 90C, the second green light-emitting units can include at least a fourth anode 90D, and the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D can be all disposed in the anode conductive layer.

[0128] In the example embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D can include a main body part 90-1 and a connecting part 90-2 connected with each other, a first end of the connecting part 90-2 is connected with the main body part 90-1, and a second end of the connecting part 90-2 extends in a direction away from the main body part 90-1 and is connected with the anode connection electrode 73 in the pixel driving circuit through an anode via hole.

[0129] In the example embodiment, the orthographic projection of the main body part of the first anode 90A and the main body part of the second anode 90B on the substrate at least partially overlaps with the orthographic projection of the second connecting line 82 on the substrate, while the orthographic projection of the main body part of the third anode 90C and the main body part of the fourth anode 90D on the substrate does not overlap with the orthographic projection of the second connecting line 82 on the substrate, i.e. the second connecting line 82 is only arranged below the anodes of the red light emitting unit and the blue light emitting unit.

[0130] In the example embodiment, the orthographic projection of the main body part of the third anode 90C and the main body part of the fourth anode 90D on the substrate at least partially overlaps with the orthographic projection of the initial connecting line on the substrate, while the orthographic projection of the main body part of the first anode 90A and the main body part of the second anode 90B on the substrate does not overlap with the orthographic projection of the initial connecting line on the substrate, i.e. the initial connecting line is only arranged below the anodes of the first green light emitting unit and the second green light emitting unit. The initial connecting line can be the first initial connecting line 91, or can be the second initial connecting line 92, or can be the third initial connecting line 93.

[0131] The preparation process of the substrate is exemplarily illustrated below by the example embodiment. The "patterning process" in the present disclosure includes deposition of a film layer, coating photoresist on the film layer, mask exposure, development, etching, stripping of photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development, etc. for organic materials. The deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, the coating can use any one or more of spraying, spin coating and inkjet printing, and the etching can use any one or more of dry etching and wet etching, which are not limited by the present disclosure. The "film" refers to a film of a certain material made on a substrate by deposition, coating or other processes. If the "film" does not need to be patterned during the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" needs to be patterned during the entire manufacturing process, it is referred to as a "film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the example embodiment of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0132] In the example embodiment, taking 8 circuit units in one unit row and 8 unit columns as an example, the preparation process of the substrate can include the following operations.

[0133] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern can include sequentially depositing a first insulating thin film and a semiconductor thin film on a substrate, patterning the semiconductor thin film through a patterning process, forming a first insulating layer disposed on the substrate, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 9.

[0134] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit can include at least a first active layer 11 of a first transistor T1 to an eighth active layer 18 of an eighth transistor T8, and the first active layer 11 to the seventh active layer 17 can be an integrated structure connected to each other, and the eighth active layer 18 is separately disposed.

[0135] In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12, and the fourth active layer 14 can be located on the side opposite to the second direction Y of the third active layer 13, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, the seventh active layer 17, and the eighth active layer 18 can be located on the second direction Y of the third active layer 13.

[0136] In an exemplary embodiment, the shape of the third active layer 13 can be an "Ω" shape, the shape of the first active layer 11 can be an "n" shape, the shape of the second active layer 12, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 can be an "L" shape, and the shape of the fourth active layer 14 and the eighth active layer 18 can be an "I" shape.

[0137] In the example embodiment, the first to eighth active layers 11 to 18 can each include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer can be connected to each other, and the second region 11-2 of the first active layer can serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer can be connected to each other, and the first region 13-1 of the third active layer can serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer can be connected to each other, and the second region 12-2 of the second active layer can serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the first region 18-2 of the eighth active layer can be provided separately.

[0138] In the example embodiment, the semiconductor layer patterns of adjacent cell columns can be provided in mirror symmetry with respect to a column center line. For example, the first to eighth active layers 11 to 18 in the Nth cell column and the N+1th cell column can be provided in mirror symmetry with respect to the column center line. For another example, the first to eighth active layers 11 to 18 in the N+1th cell column and the N+2th cell column can be provided in mirror symmetry with respect to the column center line.

[0139] In the example embodiment, the positions and shapes of the first to eighth active layers 11 to 18 of adjacent cell rows can be substantially the same.

[0140] In the example embodiment, in at least one unit row, the first active layer 11 in part of the adjacent circuit units can be an integral structure connected to each other, and the first active layer 11 in two circuit units can share the same first region 11-1 of the first active layer. For example, the two circuit units in the Nth unit column and the N+1th unit column can share the same first region 11-1 of the first active layer. For another example, the two circuit units in the N+2th unit column and the N+3th unit column can share the same first region 11-1 of the first active layer. For another example, the two circuit units in the N+4th unit column and the N+5th unit column can share the same first region 11-1 of the first active layer. The disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connection electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by setting the first transistor T1 in the adjacent circuit units to be mirror set and share the first region of the first active layer.

[0141] In the example embodiment, the first region of the first active layer can be used as the first electrode of the first transistor T1, and the pixel driving circuits in the adjacent circuit units sharing the first electrode of the first transistor T1 can be the pixel driving circuits in the adjacent circuit units sharing the first region of the first active layer.

[0142] In the example embodiment, in at least one unit row, the seventh active layer 17 in part of the adjacent circuit units can be an integral structure connected to each other, and the seventh active layer 17 in two circuit units can share the same first region 17-1 of the seventh active layer. For example, the two circuit units in the N+1th unit column and the N+2th unit column can share the same first region 17-1 of the seventh active layer. For another example, the two circuit units in the N+3th unit column and the N+4th unit column can share the same first region 17-1 of the seventh active layer. For another example, the two circuit units in the N+5th unit column and the N+6th unit column can share the same first region 17-1 of the seventh active layer. The disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connection electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by setting the seventh transistor T7 in the adjacent circuit units to be mirror set and share the first region of the seventh active layer.

[0143] In the example embodiment, the first region of the seventh active layer can be used as the first electrode of the seventh transistor T7, and the pixel driving circuits in the adjacent circuit units sharing the first electrode of the seventh transistor T7 can be the pixel driving circuits in the adjacent circuit units sharing the first region of the seventh active layer.

[0144] In the example embodiment, in at least one unit row, the eighth active layer 18 in some adjacent circuit units can be arranged in mirror symmetry relative to the column center line and close to the column center line, which is conducive to sharing the first electrode of the eighth transistor T8 by adjacent circuit units, can effectively reduce the lateral wiring space, reduce the number of vias, reduce the area occupied by the pixel driving circuit, and is conducive to realizing high resolution.

[0145] In the example embodiment, the semiconductor layer can adopt polycrystalline silicon (p-Si), i.e., the first transistor T1 to the eighth transistor T8 are LTPS transistors. In the example embodiment, the patterning process for patterning the semiconductor thin film can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, dehydrogenating the amorphous silicon thin film, and crystallizing the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form a semiconductor layer pattern.

[0146] (2) Forming a first conductive layer pattern. In the example embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the first conductive thin film by a patterning process to form a second insulating layer covering the semiconductor layer and a first conductive layer pattern disposed on the second insulating layer, as shown in FIGS. 10A and 10B, FIG. 10B is a plan view of the first conductive layer in FIG. 10A. In the example embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0147] In the example embodiment, the first conductive layer pattern of each circuit unit in the display substrate can at least include a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light-emitting signal line 24, and a first plate 31 of a storage capacitor.

[0148] In the example embodiment, the shape of the first plate 31 of the storage capacitor can be a rectangular shape, and the corner of the rectangular shape can be provided with a chamfer or a groove. The orthographic projection of the first plate 31 on the substrate at least partially overlaps the orthographic projection of the third active layer on the substrate, and the first plate 31 can simultaneously serve as the lower plate of the storage capacitor and the gate electrode of the third transistor T3.

[0149] In the example embodiment, the shape of the first scan signal line 21 can be a straight line or a polyline extending along the first direction X, and the first scan signal line 21 can be disposed on the side opposite to the second direction Y of the first plate 31. The region where the first scan signal line 21 overlaps the fourth active layer can serve as the gate electrode of the fourth transistor T4, so that the first scan signal line 21 can control the conduction or disconnection of the fourth transistor T4.

[0150] In the example embodiment, the first scan signal line 21 can be provided with a gate block 21-1, the shape of the gate block 21-1 can be a strip shape extending along the second direction Y, a first end of the gate block 21-1 is connected to a side of the first scan signal line 21 away from the first plate 31, and a second end of the gate block 21-1 extends away from the first plate 31. The area where the first scan signal line 21 and the gate block 21-1 overlap the second active layer can serve as the gate electrode of the second transistor T2 of the double-gate structure, so that the first scan signal line 21 can control the conduction or disconnection of the second transistor T2. In the example embodiment, the double-gate structure of the second transistor T2 can reduce the leakage of the second transistor T2, which is conducive to low-frequency driving of the pixel driving circuit.

[0151] In the example embodiment, the second scan signal line 22 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged on a side of the first scan signal line 21 away from the first plate 31. The area where the second scan signal line 22 overlaps the first active layer can serve as the gate electrode of the first transistor T1 of the double-gate structure, so that the second scan signal line 22 can control the conduction or disconnection of the first transistor T1. In the example embodiment, the double-gate structure of the first transistor T1 can reduce the leakage of the first transistor T1, which is conducive to low-frequency driving of the pixel driving circuit.

[0152] In the example embodiment, the third scan signal line 23 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged on a side of the first plate 31 along the second direction Y. The area where the third scan signal line 23 overlaps the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the third scan signal line 23 overlaps the eighth active layer can serve as the gate electrode of the eighth transistor T8, so that the third scan signal line 23 can control the conduction or disconnection of the seventh transistor T7 and the eighth transistor T8.

[0153] In the example embodiment, the light-emitting signal line 24 can be in the shape of a straight line or a broken line extending along the first direction X, and can be arranged between the first plate 31 and the third scan signal line 23. The area where the light-emitting signal line 24 overlaps the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 24 overlaps the sixth active layer can serve as the gate electrode of the sixth transistor T6, so that the light-emitting signal line 24 can control the conduction or disconnection of the fifth transistor T5 and the sixth transistor T6.

[0154] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light-emitting signal line 24 can be non-equal-width broken lines, and the width of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light-emitting signal line 24 at the position where the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light-emitting signal line 24 overlap the semiconductor layer can be greater than the width of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light-emitting signal line 24 at other positions.

[0155] In an exemplary embodiment, the first conductive layer pattern of adjacent unit columns can be arranged in mirror symmetry with respect to the column center line. For example, the positions and shapes of the first conductive layers in the Nth unit column and the N+1th unit column can be arranged in mirror symmetry with respect to the column center line. For another example, the positions and shapes of the first conductive layers in the N+1th unit column and the N+2th unit column can be arranged in mirror symmetry with respect to the column center line.

[0156] In an exemplary embodiment, the positions and shapes of the first conductive layers of adjacent unit rows can be substantially the same.

[0157] In an exemplary embodiment, after the first conductive layer pattern is formed, the first semiconductor layer can be subjected to a conductorization process using the first conductive layer as a shield. The first semiconductor layer in the region shielded by the first conductive layer forms the channel regions of the first transistor T1 to the eighth transistor T8, and the first semiconductor layer in the region not shielded by the first conductive layer is conductorized, i.e., the first regions and the second regions of the first active layer to the eighth active layer are conductorized.

[0158] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by a patterning process, forming a third insulating layer covering the first conductive layer pattern, and forming a second conductive layer pattern on the third insulating layer, as shown in FIG. 11A and FIG. 11B, which is a plan view of the second conductive layer in FIG. 11A. In an exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0159] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate at least includes: a second plate 32 of a storage capacitor, a first initial signal line 41, a third initial signal line 43, a first shielding electrode 61, a second shielding electrode 62, a third shielding electrode 63 and a fourth shielding electrode 64.

[0160] In an exemplary embodiment, the outline of the second plate 32 of the storage capacitor can be rectangular, and the corners of the rectangular shape can be provided with chamfers or grooves. The orthographic projection of the second plate 32 on the substrate at least partially overlaps the orthographic projection of the first plate 31 on the substrate, and the second plate 32 can serve as the upper plate of the storage capacitor, and the first plate 31 and the second plate 32 constitute the storage capacitor.

[0161] In an example embodiment, the second plate 32 is provided with an opening 33, the opening 33 can be in a block shape (e.g. a rectangular shape), and can be located in a middle region of the second plate 32, so that the second plate 32 forms a ring shape. The opening 33 exposes the third insulating layer covering the first plate 31, and a projection of the first plate 31 on the substrate contains a projection of the opening 33 on the substrate. In an example embodiment, the opening 33 is configured to accommodate a tenth via to be formed later, the tenth via is located in the opening 33 and exposes the first plate 31, so that a first connecting electrode to be formed later is connected to the first plate 31.

[0162] In an example embodiment, the second plate 32 can be provided with a plate connecting strip 34. The plate connecting strip 34 can be in a straight line shape or a broken line shape extending along the first direction X, and the plate connecting strip 34 can be provided on one side of the second plate 32 in the first direction X or on the side opposite to the first direction X. The first end of the plate connecting strip 34 is connected to the second plate 32 in the current circuit unit, and the second end of the plate connecting strip 34 is connected to the second plate 32 in the adjacent circuit unit in the first direction X.

[0163] In an example embodiment, in at least one circuit unit, the second plate 32 and the plate connecting strip 34 can be an integrated structure connected to each other.

[0164] In an example embodiment, in one unit row, the second plates 32 in some adjacent circuit units can be an integrated structure connected to each other. For example, the second plate 32 in the Nth unit column and the second plate 32 in the N+1th unit column are connected to each other through the plate connecting strip 34, forming an integrated structure connected to each other. For another example, the second plate 32 in the N+2th unit column and the second plate 32 in the N+3th unit column are connected to each other through the plate connecting strip 34, forming an integrated structure connected to each other. For another example, the second plate 32 in the N+4th unit column and the second plate 32 in the N+5th unit column are connected to each other through the plate connecting strip 34, forming an integrated structure connected to each other. Since the second plate 32 in each circuit unit is connected to the first power supply line to be formed later, by forming the second plates 32 in some adjacent circuit units into an integrated structure connected to each other, the second plates in the integrated structure can be reused as power signal lines, so that the second plates in adjacent circuit units have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0165] In an example embodiment, the first initial signal line 41 can be in a shape of a straight line or a broken line extending along the first direction X, and can be arranged between the first scan signal line 21 and the second scan signal line 22. The first initial signal line 41 can be provided with a first initial connection block 41-1 in a shape of a block (e.g., a rectangle). In the first direction X, the first initial connection block 41-1 can be arranged between part of the adjacent circuit units, and in the second direction Y, the first initial connection block 41-1 can be arranged on the side of the first initial signal line 41 close to the first scan signal line 21 and connected to the first initial signal line 41. In an example embodiment, the first initial connection block 41-1 is configured to be connected to the first region of the first active layer through a sixth connection electrode formed later.

[0166] In an example embodiment, the first initial signal line 41 and the plurality of first initial connection blocks 41-1 in one unit row can be an integrated structure connected to each other.

[0167] In an example embodiment, part of the two adjacent circuit units in one unit row can share the same first initial connection block 41-1. For example, the two circuit units in the Nth unit column and the N+1th unit column can share the same first initial connection block 41-1. For another example, the two circuit units in the N+2th unit column and the N+3th unit column can share the same first initial connection block 41-1. For another example, the two circuit units in the N+4th unit column and the N+5th unit column can share the same first initial connection block 41-1. By arranging part of the adjacent circuit units to share the first initial connection block 41-1, the present disclosure can effectively reduce the horizontal wiring space, reduce the number of vias and connection electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution.

[0168] In an example embodiment, the third initial signal line 43 can be in a shape of a straight line or a broken line extending along the first direction X, and can be arranged on the side of the third scan signal line 23 away from the second plate 32. The third initial signal line 43 can be provided with a third initial connection block 43-1 in a shape of a block (e.g., a rectangle). In the first direction X, the third initial connection block 43-1 can be arranged between part of the adjacent circuit units, and in the second direction Y, the third initial connection block 43-1 can be arranged on the side of the third initial signal line 43 away from the second plate 32 and connected to the third initial signal line 43. In an example embodiment, the third initial connection block 43-1 is configured to be connected to the first region of the eighth active layer through a seventh connection electrode formed later.

[0169] In an exemplary embodiment, the third initial signal line 43 and the plurality of third initial connection blocks 43-1 in one unit row can be an integrated structure connected to each other.

[0170] In an exemplary embodiment, two circuit units in one unit row that are partially adjacent can share the same third initial connection block 43-1. For example, two circuit units in the Nth unit column and the (N+1)th unit column can share the same third initial connection block 43-1. For another example, two circuit units in the (N+2)th unit column and the (N+3)th unit column can share the same third initial connection block 43-1. For another example, two circuit units in the (N+4)th unit column and the (N+5)th unit column can share the same third initial connection block 43-1. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connection electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by setting the third initial connection block 43-1 shared by the partially adjacent circuit units.

[0171] In an exemplary embodiment, the first shielding electrode 61 can be in the shape of a block (such as a rectangle) and can be arranged on the third initial signal line 43 and connected to the third initial signal line 43. The orthographic projection of the first shielding electrode 61 on the substrate at least partially overlaps the orthographic projection of the first active layer between the two gate electrodes in the first transistor T1 on the substrate, and the first shielding electrode 61 and the first active layer between the two gate electrodes in the first transistor T1 form a coupling capacitor. In an exemplary embodiment, the first shielding electrode 61 is configured to shield the node between the two gate electrodes in the first transistor T1 on the one hand, to avoid the influence of data voltage jump on the first transistor T1, and to reduce the influence of data voltage jump on the normal operation of the pixel driving circuit, and on the other hand, to reduce the leakage of the first transistor T1 by using the coupling capacitor and to improve the display effect.

[0172] In an exemplary embodiment, the third initial signal line 43 and the first shielding electrode 61 in at least one circuit unit can be an integrated structure connected to each other.

[0173] In the example embodiment, the second shielding electrode 62 can be in a block shape (e.g., a rectangular shape), and can be disposed on the first initial signal line 41. A first end of the second shielding electrode 62 is connected to a side of the first initial signal line 41 close to the first scan signal line 21, and a second end of the second shielding electrode 62 extends toward the first scan signal line 21. A projection of the second shielding electrode 62 on the substrate at least partially overlaps a projection of the second active layer between the two gate electrodes of the second transistor T2 on the substrate. The second shielding electrode 62 and the second active layer between the two gate electrodes of the second transistor T2 form a coupling capacitor. In the example embodiment, the second shielding electrode 62 is configured to shield a node between the two gate electrodes of the second transistor T2, to avoid the influence of data voltage jump on the second transistor T2, to reduce the influence of data voltage jump on the normal operation of the pixel driving circuit, and on the other hand, to reduce the leakage of the second transistor T2 by using the coupling capacitor, and to improve the display effect.

[0174] In the example embodiment, in at least one circuit unit, the first initial signal line 41 and the third shielding electrode 63 can be an integrated structure connected to each other.

[0175] In the example embodiment, in at least one unit row, the second shielding electrodes 62 in some adjacent circuit units can be connected to each other to form an integrated structure. For example, the second shielding electrode 62 in the N+1th unit column and the second shielding electrode 62 in the N+2th unit column can be an integrated structure connected to each other. For another example, the second shielding electrode 62 in the N+3th unit column and the second shielding electrode 62 in the N+4th unit column can be an integrated structure connected to each other. For another example, the second shielding electrode 62 in the N+5th unit column and the second shielding electrode 62 in the N+6th unit column can be an integrated structure connected to each other.

[0176] In the example embodiment, the third shielding electrode 63 can be in a block shape (e.g., a rectangular shape), and can be disposed on and connected to the first initial signal line 41. A projection of the third shielding electrode 63 on the substrate at least partially overlaps a projection of the second region of the first active layer on the substrate. In the example embodiment, the third shielding electrode 63 is configured to shield the subsequently formed first connection line, to avoid the influence of data voltage jump in the first connection line on the first transistor T1 and the second transistor T2, to reduce the influence of data voltage jump on the normal operation of the pixel driving circuit, and to improve the display effect.

[0177] In the example embodiment, in at least one circuit unit, the first initial signal line 41 and the third shielding electrode 63 can be an integrated structure connected to each other.

[0178] In the example embodiment, the fourth shielding electrode 64 can have a strip shape extending along the second direction Y, a first end of the fourth shielding electrode 64 is connected to the first initial signal line 41 on the side close to the first scan signal line 21, and a second end of the fourth shielding electrode 64 extends toward the direction close to the first scan signal line 21. In the first direction X, the fourth shielding electrode 64 can be located between the first region of the second active layer (also the second region of the first active layer) and the first region of the fourth active layer, i.e., between the first electrode of the second transistor T2 (also the second electrode of the first transistor T1) and the first electrode of the fourth transistor T4. In the example embodiment, since the first region of the fourth active layer is connected to the subsequently formed data signal line, and the second region of the first active layer (also the first region of the second active layer) is connected to the subsequently formed first connection electrode as the first node N1, the fourth shielding electrode 64 is arranged between the first node N1 and the data signal line, which can avoid the influence of the data signal line on the first node N1, reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0179] In the example embodiment, in at least one circuit unit, the first initial signal line 41 and the fourth shielding electrode 64 can be an integrated structure connected to each other.

[0180] In the example embodiment, in at least one unit row, the first initial signal line 41, the plurality of second shielding electrodes 62, the plurality of third shielding electrodes 63, and the plurality of fourth shielding electrodes 64 can be an integrated structure connected to each other.

[0181] In the example embodiment, the second conductive layer patterns of adjacent unit columns can be arranged in mirror symmetry with respect to the column center line. For example, the positions and shapes of the second conductive layers in the Nth unit column and the N+1th unit column can be arranged in mirror symmetry with respect to the column center line. For another example, the positions and shapes of the second conductive layers in the N+1th unit column and the N+2th unit column can be arranged in mirror symmetry with respect to the column center line.

[0182] In the example embodiment, the positions and shapes of the second conductive layers of adjacent unit rows can be substantially the same.

[0183] (4) Forming a fourth insulating layer pattern. In the example embodiment, forming the fourth insulating layer pattern can include: on the substrate on which the aforementioned patterns are formed, depositing a fourth insulating thin film, and patterning the fourth insulating thin film by using a patterning process to form a fourth insulating layer covering the second conductive layer, and the fourth insulating layer is provided with a plurality of vias, as shown in FIG. 12.

[0184] In an example embodiment, the plurality of vias of each circuit unit in the display substrate at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, and a thirteenth via V13.

[0185] In an example embodiment, the first via V1 is configured to expose a surface of the first region of the first active layer by etching away the second insulating layer, the third insulating layer, and the fourth insulating layer in the first via V1, and the first via V1 is configured to connect the sixth connection electrode to be formed subsequently to the first region of the first active layer through the first via V1.

[0186] In an example embodiment, since the first active layer in part of the adjacent circuit units shares the first region of the first active layer, part of the adjacent two circuit units can share the same first via V1. For example, the two circuit units in the Nth unit column and the (N+1)th unit column can share the same first via V1. For another example, the two circuit units in the (N+2)th unit column and the (N+3)th unit column can share the same first via V1. For another example, the two circuit units in the (N+4)th unit column and the (N+5)th unit column can share the same first via V1. The present disclosure can effectively reduce the number of vias and reduce the area occupied by the pixel driving circuit by configuring the adjacent circuit units to share the first via V1, which is conducive to achieving high resolution.

[0187] In an example embodiment, the second via V2 is configured to expose a surface of the second region of the first active layer (also the first region of the second active layer) by etching away the second insulating layer, the third insulating layer, and the fourth insulating layer in the second via V2, and the second via V2 is configured to connect the first connection electrode to be formed subsequently to the second region of the first active layer (also the first region of the second active layer) through the second via V2.

[0188] In an example embodiment, the third via V3 is configured to expose a surface of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) by etching away the second insulating layer, the third insulating layer, and the fourth insulating layer in the third via V3, and the third via V3 is configured to connect the fifth connection electrode to be formed subsequently to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through the third via V3.

[0189] In an example embodiment, the fourth via V4 is configured such that the second connection electrode formed subsequently is connected to the first region of the fourth active layer through the fourth via V4.

[0190] In an example embodiment, the fifth via V5 is configured such that the third connection electrode formed subsequently is connected to the first region of the fifth active layer through the fifth via V5.

[0191] In an example embodiment, the sixth via V6 is configured such that the fourth connection electrode formed subsequently is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the sixth via V6.

[0192] In an example embodiment, the seventh via V7 is configured such that the second initial connection block formed subsequently is connected to the first region of the seventh active layer through the seventh via V7.

[0193] In an example embodiment, since the seventh active layer in part of the adjacent circuit units shares the same first region of the seventh active layer, part of the two adjacent circuit units can share the same seventh via V7. For example, the two circuit units in the (N+1)th unit column and the (N+2)th unit column can share the same seventh via V7. For another example, the two circuit units in the (N+3)th unit column and the (N+4)th unit column can share the same seventh via V7. For another example, the two circuit units in the (N+5)th unit column and the (N+6)th unit column can share the same seventh via V7. The present disclosure can effectively reduce the number of vias and reduce the occupied area of the pixel driving circuit by setting the adjacent circuit units to share the seventh via V7, which is conducive to achieving high resolution.

[0194] In an example embodiment, the eighth via V8 is configured such that the seventh connection electrode formed subsequently is connected to the first region of the eighth active layer through the via.

[0195] In an example embodiment, the ninth via V9 is configured such that the fifth connection electrode formed subsequently is connected to the second region of the eighth active layer through the via.

[0196] In an example embodiment, the tenth via V10 is configured such that the first connection electrode formed subsequently is connected to the first plate 31 through the via.

[0197] In an example embodiment, the eleventh via V11 is configured such that the third connection electrode formed subsequently is connected to the second plate 32 through the via.

[0198] In an example embodiment, the twelfth via V12 is configured such that the sixth connection electrode formed subsequently is connected to the first initial connection block 41-1 through the via.

[0199] In the example embodiment, the first initial signal line 41 in part of the adjacent circuit units shares the same first initial connection block 41-1, and thus the two circuit units in part of the adjacent circuit units can share the same twelfth via V12. For example, the two circuit units in the Nth unit column and the (N+1)th unit column can share the same twelfth via V12. For another example, the two circuit units in the (N+2)th unit column and the (N+3)th unit column can share the same twelfth via V12. For another example, the two circuit units in the (N+4)th unit column and the (N+5)th unit column can share the same twelfth via V12. The present disclosure can effectively reduce the number of vias and reduce the area occupied by the pixel driving circuit by setting the adjacent circuit units to share the twelfth via V12, which is conducive to achieving high resolution.

[0200] In the example embodiment, the thirteenth via V13 is located within the range of the third initial connection block 43-1 of the third initial signal line 43 on the substrate, the fourth insulating layer in the thirteenth via V13 is etched to expose the surface of the third initial connection block 43-1, and the thirteenth via V13 is configured to connect the seventh connection electrode formed subsequently to the third initial connection block 43-1 through the via.

[0201] In the example embodiment, the third initial signal line 43 in part of the adjacent circuit units shares the same third initial connection block 43-1, and thus the two circuit units in part of the adjacent circuit units can share the same thirteenth via V13. For example, the two circuit units in the Nth unit column and the (N+1)th unit column can share the same thirteenth via V13. For another example, the two circuit units in the (N+2)th unit column and the (N+3)th unit column can share the same thirteenth via V13. For another example, the two circuit units in the (N+4)th unit column and the (N+5)th unit column can share the same thirteenth via V13. The present disclosure can effectively reduce the number of vias and reduce the area occupied by the pixel driving circuit by setting the adjacent circuit units to share the thirteenth via V13, which is conducive to achieving high resolution.

[0202] (5) Forming a third conductive layer pattern. In the example embodiment, forming the third conductive layer can include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, and patterning the third conductive film by using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIGS. 13A, 13B and 13C, FIG. 13B is a plan view of one type of third conductive layer in FIG. 13A, and FIG. 13C is a plan view of another type of third conductive layer in FIG. 13A. In the example embodiment, the third conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0203] In an exemplary embodiment, the third conductive layer of each circuit unit in the display substrate at least includes: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, and a second initial signal line 42.

[0204] In an exemplary embodiment, the shape of the first connection electrode 51 can be a strip shape with a main body portion extending along the second direction Y, a first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through a second via V2, and a second end of the first connection electrode 51 is connected to the first plate 31 through a tenth via V10. Since the first plate 31 serves as the gate electrode of the third transistor T3, the first connection electrode 51 realizes the interconnection between the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate 31 of the storage capacitor, forming the first node N1 of the pixel driving circuit.

[0205] In an exemplary embodiment, the shape of the second connection electrode 52 can be a block shape (such as a rectangular shape), the second connection electrode 52 is connected to the first region of the fourth active layer through a fourth via V4, and the second connection electrode 52 is configured to be connected to the subsequently formed data signal line.

[0206] In an exemplary embodiment, the shape of the third connection electrode 53 can be a strip shape extending along the second direction Y, a first end of the third connection electrode 53 is connected to the first region of the fifth active layer through a fifth via V5, and a second end of the third connection electrode 53 is connected to the second plate 32 through an eleventh via V11, and the third connection electrode 53 is configured to be connected to the subsequently formed first power supply line. In an exemplary embodiment, the third connection electrode 53 realizes the interconnection between the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor, and the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor have the same potential.

[0207] In an exemplary embodiment, an electrode connection line 53-1 is provided on the third connection electrode 53. The shape of the electrode connection line 53-1 can be a straight line shape or a polyline shape extending along the first direction X, the electrode connection line 53-1 can be provided on one side of the third connection electrode 53 along the first direction X or on the opposite side of the first direction X, a first end of the electrode connection line 53-1 is connected to the third connection electrode 53 in the current circuit unit, and a second end of the electrode connection line 53-1 is connected to the third connection electrode 53 in the adjacent circuit unit along the first direction X.

[0208] In an exemplary embodiment, in at least one circuit unit, the third connection electrode 53 and the electrode connection line 53-1 can be an integrated structure connected to each other.

[0209] In an example embodiment, in one unit row, the third connection electrodes 53 in part of the adjacent circuit units can be an integrated structure connected to each other. For example, the third connection electrode 53 in the N+1 unit column and the third connection electrode 53 in the N+2 unit column are connected to each other through the electrode connection line 53-1 to form an integrated structure connected to each other. For another example, the third connection electrode 53 in the N+3 unit column and the third connection electrode 53 in the N+4 unit column are connected to each other through the electrode connection line 53-1 to form an integrated structure connected to each other. For another example, the third connection electrode 53 in the N+5 unit column and the third connection electrode 53 in the N+6 unit column are connected to each other through the electrode connection line 53-1 to form an integrated structure connected to each other. Since the third connection electrode 53 in each circuit unit is connected to the first power supply line formed subsequently, by forming the third connection electrodes 53 in part of the adjacent circuit units into an integrated structure connected to each other, the third connection electrodes 53 in the integrated structure can be reused as a power supply signal line, which can ensure that the third connection electrodes 53 in the adjacent circuit units have the same potential, is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0210] In an example embodiment, in one unit row, since the second plates 32 in part of the adjacent circuit units are connected to each other through the plate connection strips 34, the third connection electrodes 53 in part of the adjacent circuit units are connected to each other through the electrode connection lines 53-1, and the third connection electrodes 53 are connected to the second plates 32, it is realized that the first poles of the plurality of fifth transistors T5 and the second plates 32 of the plurality of storage capacitors in one unit row have the same potential, which effectively improves the uniformity of the panel, avoids display defects of the display substrate, and ensures the display effect of the display substrate.

[0211] In an example embodiment, the fourth connection electrode 54 can be in the shape of a block (such as a rectangle), the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the sixth via V6, and the fourth connection electrode 54 is configured to be connected to the anode connection electrode formed subsequently.

[0212] In the example embodiment, the fifth connection electrode 55 can have a strip shape extending along the second direction Y, a first end of the fifth connection electrode 55 is connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through the third via V3, and a second end of the fifth connection electrode 55 is connected to the second region of the eighth active layer through the ninth via V9. In the example embodiment, the fifth connection electrode 55 realizes the interconnection between the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, forming the second node N2 of the pixel driving circuit.

[0213] In the example embodiment, the sixth connection electrode 56 can have a strip shape extending along the second direction Y, a first end of the sixth connection electrode 56 is connected to the first region of the first active layer through the first via V1, and a second end of the sixth connection electrode 56 is connected to the first initial connection block 41-1 through the twelfth via V12. The sixth connection electrode 56 can serve as the first electrode of the first transistor T1, and since the first initial connection block 41-1 is connected to the first initial signal line 41, the first initial signal line 41 writes the first initial signal to the first region of the first active layer.

[0214] In the example embodiment, since the first regions of the first active layers of the two adjacent circuit units are shared, the first initial connection block 41-1 is shared, and the twelfth via V12 is shared, the two adjacent circuit units can share the same sixth connection electrode 56, i.e., the pixel driving circuits in the adjacent circuit units share the same first electrode of the first transistor T1. For example, the two circuit units in the Nth unit column and the N+1th unit column can share the same sixth connection electrode 56. For another example, the two circuit units in the N+2th unit column and the N+3th unit column can share the same sixth connection electrode 56. For another example, the two circuit units in the N+4th unit column and the N+5th unit column can share the same sixth connection electrode 56. The present disclosure can effectively reduce the number of connection electrodes and reduce the occupied area of the pixel driving circuit by arranging the adjacent circuit units to share the sixth connection electrode 56, which is conducive to realizing high resolution.

[0215] In some other embodiments, the first regions of the first active layers of the two adjacent circuit units can not be connected, the first active layers of the two adjacent circuit units can not be an integral structure, i.e., the first active layers of the two adjacent circuit units are disconnected, the first regions of the first active layers of the two circuit units can be connected through the shared sixth connection electrode 56, the sixth connection electrode 56 can serve as the first electrode of the first transistor T1, and the pixel driving circuits in the adjacent circuit units share the same first electrode of the first transistor T1, which is not limited in the present disclosure.

[0216] In an example embodiment, the seventh connection electrode 57 can have a strip shape extending along the first direction X, a first end of the seventh connection electrode 57 is connected with the first region of the eighth active layer through the eighth via V8, and a second end of the seventh connection electrode 57 is connected with the third initial connection block 43-1 through the thirteenth via V13. The seventh connection electrode 57 can serve as a first electrode of the eighth transistor T8. Since the third initial connection block 43-1 is connected with the third initial signal line 43, the third initial signal line 43 can write a third initial signal to the first region of the eighth active layer.

[0217] In an example embodiment, in at least one unit row, the seventh connection electrodes 57 in some adjacent circuit units can be mirror-symmetrical relative to the column center line, and the seventh connection electrodes 57 in two adjacent circuit units can be an integrated structure connected with each other, and the two circuit units can share the second end of the same seventh connection electrode 57, i.e., the pixel driving circuits in adjacent circuit units share the first electrode of the eighth transistor T8. For example, the seventh connection electrodes 57 in two circuit units in the Nth unit column and the N+1th unit column can be an integrated structure connected with each other. For another example, the seventh connection electrodes 57 in two circuit units in the N+2th unit column and the N+3th unit column can be an integrated structure connected with each other. For another example, the seventh connection electrodes 57 in two circuit units in the N+4th unit column and the N+5th unit column can be an integrated structure connected with each other. By setting the seventh connection electrodes 57 in adjacent circuit units as an integrated structure connected with each other, the present disclosure can effectively reduce the occupied space of the connection electrode and reduce the occupied area of the pixel driving circuit, which is conducive to realizing high resolution.

[0218] In some other embodiments, the first region of the eighth active layer in two adjacent circuit units can be connected with each other, and the eighth active layer in the two adjacent circuit units can be an integrated structure connected with each other, and the first region of the eighth active layer can serve as the first electrode of the eighth transistor T8, so that the pixel driving circuits in adjacent circuit units share the first electrode of the same eighth transistor T8, which is not limited in the present disclosure.

[0219] In the example embodiment, the second initial signal line 42 can be in a straight line shape or a zigzag shape extending along the first direction X, and can be arranged on the side of the third initial signal line 43 close to the second plate 32. The second initial signal line 42 can be provided with a second initial connecting block 42-1 in a block shape (e.g., a rectangular shape). In the first direction X, the second initial connecting block 42-1 can be arranged between part of the adjacent circuit units, and in the second direction Y, the second initial connecting block 42-1 can be arranged on the side of the second initial signal line 42 away from the second plate 32 and connected to the second initial signal line 42. The second initial connecting block 42-1 can be connected to the first region of the seventh active layer through a seventh via V7. The second initial connecting block 42-1 can serve as the first electrode of the seventh transistor T7. Since the second initial connecting block 42-1 is connected to the second initial signal line 42, the second initial signal line 42 can write the second initial signal to the first region of the seventh active layer.

[0220] In the example embodiment, the second initial signal line 42 and the plurality of second initial connecting blocks 42-1 in one unit row can be an integrated structure connected to each other.

[0221] In the example embodiment, since the two adjacent circuit units share the same first region of the seventh active layer and share the same seventh via V7, the two adjacent circuit units in one unit row can share the same second initial connecting block 42-1, i.e., the pixel driving circuits in the adjacent circuit units share the first electrode of the seventh transistor T7. For example, the two circuit units in the N+1th unit column and the N+2th unit column can share the same second initial connecting block 42-1. For another example, the two circuit units in the N+3th unit column and the N+4th unit column can share the same second initial connecting block 42-1. For another example, the two circuit units in the N+5th unit column and the N+6th unit column can share the same second initial connecting block 42-1. The present disclosure can effectively reduce the lateral wiring space, reduce the number of vias and connection electrodes, reduce the occupied area of the pixel driving circuit, and facilitate the realization of high resolution by arranging the second initial connecting block 42-1 shared by the adjacent circuit units.

[0222] In some other embodiments, the first region of the seventh active layer of the two adjacent circuit units can not be connected, i.e., the seventh active layer of the two adjacent circuit units is not an integrated structure, i.e., the seventh active layer of the two adjacent circuit units is disconnected, and the first region of the seventh active layer of the two circuit units can be connected through the shared second initial connecting block 42-1, which can serve as the first electrode of the seventh transistor T7, so that the pixel driving circuits in the adjacent circuit units share the same first electrode of the seventh transistor T7. The present disclosure does not limit this.

[0223] In an example embodiment, the third conductive layer can further include an eighth connection electrode 58 and a dummy connection electrode 59.

[0224] In an example embodiment, in the first direction X, the eighth connection electrode 58 can be disposed between part of the adjacent circuit units, and in the second direction Y, the eighth connection electrode 58 can be disposed on the side of the second initial signal line 42 close to the second plate 32.

[0225] In an example embodiment, the eighth connection electrode 58 can include a connection electrode strip 58-1 and a connection electrode block 58-2. The connection electrode strip 58-1 can have a shape of a strip extending along the second direction Y, and the connection electrode block 58-2 can have a shape of a block (e.g., a rectangular shape). A first end of the connection electrode strip 58-1 is connected to the second initial signal line 42, and a second end of the connection electrode strip 58-1 extends toward the direction close to the second plate 32 and is connected to the connection electrode block 58-2, which is configured to be connected to the second initial connection line to be formed later.

[0226] In an example embodiment, a normal projection of the connection electrode block 58-2 on the substrate at least partially overlaps a normal projection of the plate connection strip 34 on the substrate.

[0227] In an example embodiment, in at least one circuit unit, the second initial signal line 42, the connection electrode strip 58-1, and the connection electrode block 58-2 can be an integrated structure connected to each other.

[0228] In an example embodiment, between the adjacent eighth connection electrodes 58 in the first direction X, there can be 4 circuit units. For example, the eighth connection electrode 58 can be disposed between the N+2 unit column and the N+3 unit column. For another example, the eighth connection electrode 58 can be disposed between the N+6 unit column and the N+7 unit column.

[0229] In an example embodiment, in the first direction X, the dummy connection electrode 59 can be disposed between part of the adjacent circuit units, and in the second direction Y, the dummy connection electrode 59 can be disposed on the side of the second initial signal line 42 close to the second plate 32.

[0230] In the example embodiment, the dummy connection electrode 59 can include a dummy electrode strip 59-1 and a dummy electrode block 59-2. The dummy electrode strip 59-1 can have a shape of a strip extending along the second direction Y, and the dummy electrode block 59-2 can have a shape of a block (e.g., a rectangle). The first end of the dummy electrode strip 59-1 can be connected to the second initial signal line 42, and the second end of the dummy electrode strip 59-1 can be connected to the dummy electrode block 59-2 after extending toward the second plate 32. In the example embodiment, the dummy electrode strip 59-1 is configured to overlap with the subsequently formed anode, so as to improve the uniformity of the anode.

[0231] In the example embodiment, the dummy electrode block 59-2 can have a footprint on the substrate that at least partially overlaps with a footprint of the plate connection strip 34 on the substrate.

[0232] In the example embodiment, the second initial signal line 42, the dummy electrode strip 59-1, and the dummy electrode block 59-2 can be in at least one circuit unit.

[0233] In the example embodiment, four circuit units can be arranged between adjacent dummy connection electrodes 59 in the first direction X. For example, the dummy connection electrode 59 can be arranged between the Nth unit column and the (N+1)th unit column. For another example, the dummy connection electrode 59 can be arranged between the (N+4)th unit column and the (N+5)th unit column.

[0234] In the example embodiment, one dummy connection electrode 59 can be arranged between adjacent eighth connection electrodes 58 in the first direction X, and one eighth connection electrode 58 can be arranged between adjacent dummy connection electrodes 59 in the first direction X, i.e., the eighth connection electrodes 58 and the dummy connection electrodes 59 can be arranged alternately in the first direction X.

[0235] In the example embodiment, the eighth connection electrode 58 in one circuit unit and the dummy connection electrode 59 in another circuit unit can have substantially the same position and shape, and the connection electrode block 58-2 and the dummy electrode block 59-2 can be located on the same straight line extending along the first direction X.

[0236] In some other embodiments, the display substrate can only include the dummy electrode strip 59-1 but not the dummy electrode block 59-2, as shown in FIG. 13C, which is not limited in the present disclosure.

[0237] In the example embodiment, the third conductive layer can further include a first connection line 81. The first connection line 81 can have a shape of a straight line or a broken line extending along the first direction X, and can be located between the second scan signal line 22 and the first initial signal line 41.

[0238] In an example embodiment, the first connection line 81 has an overlapping area with the second region of the first active layer on the substrate, and the third shielding electrode 63 can cover the overlapping area, so that the third shielding electrode 63 can shield the first connection line 81, avoid the influence of the data voltage jump in the first connection line 81 on the first transistor T1 and the second transistor T2, reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0239] In an example embodiment, the first connection line 81 has an overlapping area with the second region of the first active layer on the substrate, and the third shielding electrode 63 can cover the overlapping area, so that the third shielding electrode 63 can shield the first connection line 81, avoid the influence of the data voltage jump in the first connection line 81 on the first transistor T1 and the second transistor T2, reduce the influence of the data voltage jump on the normal operation of the pixel driving circuit, and improve the display effect.

[0240] In an example embodiment, the first connection line 81 in at least one circuit unit can be provided with a first break K1, and the first break K1 can cut off the first connection line 81, so that the first connection line 81 on both sides of the first break K1 is insulated from each other.

[0241] In an example embodiment, at least one first break K1 can be arranged in the circuit unit of the Nth unit column, and the first break K1 has an overlapping area with the third shielding electrode 63 on the substrate.

[0242] In an example embodiment, the first break K1 can be located within the range of the third shielding electrode 63 on the substrate, so that the third shielding electrode 63 can pad the first break K1 from below, effectively eliminate the film layer difference in different regions, and be conducive to eliminating shadows and avoiding the appearance of the display substrate.

[0243] In an example embodiment, the first connection line 81 can include a first connection sub-line 81-1 located on one side of the first break K1 in the first direction X and a second connection sub-line 81-2 located on the other side of the first break K1 in the first direction X, the first connection sub-line 81-1 is configured to be connected with a data signal line in the display area, and the second connection sub-line 81-2 is configured as a first dummy line.

[0244] In an example embodiment, the second connection sub-line 81-2 as the first dummy line can not be connected with any signal line, or can be connected with the first power supply line, or can be connected with the second power supply line, which is not limited in the present disclosure.

[0245] In an example embodiment, the third conductive layer can further include a data connection electrode 83. The data connection electrode 83 can have a shape of a bar extending along the second direction Y. In the first direction X, the data connection electrode 83 can be disposed between partially adjacent circuit units. In the second direction Y, the data connection electrode 83 can be disposed on a side of the first connection line 81 close to the second plate 32, and the data connection electrode 83 is configured to be connected with a second connection line to be formed later.

[0246] In an example embodiment, between the data connection electrodes 83 adjacent in the first direction X, 2 circuit units can be spaced. For example, the data connection electrode 83 can be disposed between the Nth unit column and the (N+1)th unit column. For another example, the data connection electrode 83 can be disposed between the (N+2)th unit column and the (N+3)th unit column. For another example, the data connection electrode 83 can be disposed between the (N+4)th unit column and the (N+5)th unit column. For another example, the data connection electrode 83 can be disposed between the (N+6)th unit column and the (N+7)th unit column.

[0247] In an example embodiment, the data connection electrode 83 can include at least a first connection sub-block 83-1, a second connection sub-block 83-2, and a connection sub-bar 83-3. The first connection sub-block 83-1 and the second connection sub-block 83-2 can have a shape of a block (e.g., a rectangle) configured to be connected with a second connection line to be formed later. The connection sub-bar 83-3 can have a shape of a bar extending along the second direction Y, and can be disposed between the first connection sub-block 83-1 and the second connection sub-block 83-2, with one end of the connection sub-bar 83-3 connected with the first connection sub-block 83-1 and the other end of the connection sub-bar 83-3 connected with the second connection sub-block 83-2.

[0248] In an example embodiment, in at least one circuit unit, the first connection sub-block 83-1, the second connection sub-block 83-2, and the connection sub-bar 83-3 can be an integrated structure connected with each other.

[0249] In an example embodiment, a normal projection of the data connection electrode 83 on the substrate can at least partially overlap with a normal projection of the second shielding electrode 62 on the substrate.

[0250] In an example embodiment, a normal projection of the first connection sub-block 83-1 in the data connection electrode 83 on the substrate can be located within a range of a normal projection of the second shielding electrode 62 on the substrate.

[0251] In the example embodiment, the at least one circuit unit can further include a data connection block 84. The data connection block 84 can have a shape of a strip extending along the second direction Y. In the first direction X, the data connection block 84 can be disposed between the partially adjacent circuit units. In the second direction Y, the data connection block 84 can be disposed between the first connection sub-line 81-1 and the data connection electrode 83. A first end of the data connection block 84 is connected to the first connection sub-line 81-1, and a second end of the data connection block 84 is connected to the data connection electrode 83. Since the first connection sub-line 81-1 and the data connection electrode 83 are connected together through the data connection block 84, and the data connection electrode 83 is configured to be connected to the subsequently formed second connection line, the data connection block 84 can achieve the interconnection between the first connection sub-line 81-1 and the second connection line.

[0252] In the example embodiment, the first connection sub-line 81-1, the data connection electrode 83, and the data connection block 84 in the at least one circuit unit can be an integrated structure connected to each other.

[0253] In the example embodiment, the data connection block 84 can be disposed between the Nth-1 unit column and the Nth unit column, and the data connection electrode 83 between the Nth+1 unit column and the Nth+2 unit column, between the Nth+3 unit column and the Nth+4 unit column, between the Nth+5 unit column and the Nth+6 unit column, and between the Nth+7 unit column and the Nth+8 unit column can not be connected to the second connection sub-line 81-2.

[0254] In the example embodiment, the third conductive layer patterns (except for the data connection blocks and the first breaks) of the adjacent unit columns can be disposed in mirror symmetry with respect to the column center line. For example, the positions and shapes of the third conductive layers in the Nth unit column and the Nth+1 unit column can be disposed in mirror symmetry with respect to the column center line. For another example, the positions and shapes of the second conductive layers in the Nth+1 unit column and the Nth+2 unit column can be disposed in mirror symmetry with respect to the column center line.

[0255] In the example embodiment, the positions and shapes of the third conductive layers of the adjacent unit rows can be substantially the same.

[0256] (6) Forming a fifth insulating layer and a first planar layer pattern. In the example embodiment, forming the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a fifth insulating thin film, then coating a first planar thin film, and patterning the first planar thin film and the fifth insulating thin film by using a patterning process, to form a fifth insulating layer covering the fourth conductive layer pattern and a first planar layer disposed on the fifth insulating layer, the first planar layer and the fifth insulating layer being provided with a plurality of vias, as shown in FIG. 14.

[0257] In an exemplary embodiment, the plurality of vias in each circuit unit in the display substrate at least includes: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0258] In an exemplary embodiment, the twenty-first via V21 has a projection on the substrate within a projection of the second connection electrode 52 on the substrate, the first planar layer and the fifth insulating layer in the twenty-first via V21 are removed to expose a surface of the second connection electrode 52, and the twenty-first via V21 is configured to allow a data signal line formed subsequently to connect to the second connection electrode 52 through the via.

[0259] In an exemplary embodiment, the twenty-second via V22 has a projection on the substrate within a projection of the third connection electrode 53 on the substrate, the first planar layer and the fifth insulating layer in the twenty-second via V22 are removed to expose a surface of the third connection electrode 53, and the twenty-second via V22 is configured to allow a first power supply line formed subsequently to connect to the third connection electrode 53 through the via.

[0260] In an exemplary embodiment, the twenty-third via V23 has a projection on the substrate within a projection of the fourth connection electrode 54 on the substrate, the first planar layer and the fifth insulating layer in the twenty-third via V23 are removed to expose a surface of the fourth connection electrode 54, and the twenty-third via V23 is configured to allow an anode connection electrode formed subsequently to connect to the fourth connection electrode 54 through the via.

[0261] In an exemplary embodiment, the at least one circuit unit can further include a twenty-fourth via V24. The twenty-fourth via V24 has a projection on the substrate within a projection of the data connection electrode 83 on the substrate, the first planar layer and the fifth insulating layer in the twenty-fourth via V24 are removed to expose a surface of the data connection electrode 83, and the twenty-fourth via V24 is configured to allow a second connection line formed subsequently to connect to the data connection electrode 83 through the via.

[0262] In an exemplary embodiment, there can be 2 circuit units between adjacent twenty-fourth vias V24 in the first direction X. For example, the twenty-fourth via V24 can be disposed between an N-1th unit column and an Nth unit column. For another example, the twenty-fourth via V24 can be disposed between an N+1th unit column and an N+2th unit column. For another example, the twenty-fourth via V24 can be disposed between an N+3th unit column and an N+4th unit column. For another example, the twenty-fourth via V24 can be disposed between an N+5th unit column and an N+6th unit column. For another example, the twenty-fourth via V24 can be disposed between an N+7th unit column and an N+8th unit column.

[0263] In an example embodiment, the twenty-fourth via V24 can be two. One twenty-fourth via V24 has a projection on the substrate within the projection of the first connection sub-block 83-1 on the substrate, and the other twenty-fourth via V24 has a projection on the substrate within the projection of the second connection sub-block 83-2 on the substrate.

[0264] In an example embodiment, the at least one circuit unit can further include a twenty-fifth via V25. The twenty-fifth via V25 has a projection on the substrate within the projection of the sixth connection electrode 56 on the substrate, the first planar layer and the fifth insulating layer within the twenty-fifth via V25 are removed to expose a surface of the sixth connection electrode 56, and the twenty-fifth via V25 is configured to allow a first initial connection line formed subsequently to connect to the sixth connection electrode 56 through the via.

[0265] In an example embodiment, eight circuit units can be spaced between adjacent twenty-fifth vias V25 in the first direction X. For example, the twenty-fifth via V25 can be disposed between the Nth unit column and the (N+1)th unit column. For another example, the twenty-fifth via V25 can be disposed between the (N+8)th unit column and the (N+9)th unit column.

[0266] In an example embodiment, the at least one circuit unit can further include a twenty-sixth via V26. The twenty-sixth via V26 has a projection on the substrate within the projection of the connection electrode block 58-2 of the eighth connection electrode 58 on the substrate, the first planar layer and the fifth insulating layer within the twenty-sixth via V26 are removed to expose a surface of the connection electrode block 58-2, and the twenty-sixth via V26 is configured to allow a second initial connection line formed subsequently to connect to the connection electrode block 58-2 through the via.

[0267] In an example embodiment, four circuit units can be spaced between adjacent twenty-sixth vias V26 in the first direction X. For example, the twenty-sixth via V26 can be disposed between the (N+2)th unit column and the (N+3)th unit column. For another example, the twenty-sixth via V26 can be disposed between the (N+6)th unit column and the (N+7)th unit column.

[0268] In an example embodiment, the at least one circuit unit can further include a twenty-seventh via V27. The twenty-seventh via V27 has a projection on the substrate within the projection of the seventh connection electrode 57 on the substrate, the first planar layer and the fifth insulating layer within the twenty-seventh via V27 are removed to expose a surface of the seventh connection electrode 57, and the twenty-seventh via V27 is configured to allow a third initial connection line formed subsequently to connect to the seventh connection electrode 57 through the via.

[0269] In an example embodiment, eight circuit units can be spaced between the twenty-seventh via V27 and the twenty-eighth via V28 in the first direction X. For example, the twenty-seventh via V27 can be disposed between the N+4th unit column and the N+5th unit column. For another example, the twenty-seventh via V27 can be disposed between the N+12th unit column and the N+13th unit column.

[0270] In an example embodiment, the at least one circuit unit can further include a twenty-eighth via V28. A projection of the twenty-eighth via V28 on the substrate is within a projection of the seventh connection electrode 57 on the substrate, a first planar layer within the twenty-eighth via V28 is removed to expose a surface of the fifth insulating layer covering the seventh connection electrode 57, and the twenty-eighth via V28 is configured to cause a subsequent first initial connection line and a subsequent second initial connection line to exhibit substantially the same topography as a subsequent third initial connection line.

[0271] In an example embodiment, the twenty-seventh via V27 can be referred to as a connection via, the twenty-eighth via V28 can be referred to as a dummy via, a position and a shape of the twenty-seventh via V27 in one circuit unit can be substantially the same as a position and a shape of the twenty-eighth via V28 in another circuit unit, except that the first planar layer and the fifth insulating layer within the twenty-seventh via V27 are removed to expose a surface of the seventh connection electrode 57, which can enable connection between the third initial connection line and the seventh connection electrode 57, whereas the first planar layer within the twenty-eighth via V28 is removed only, and the seventh connection electrode 57 is still covered by the fifth insulating layer, so that the subsequent first initial connection line or the subsequent second initial connection line will not be connected to the seventh connection electrode 57.

[0272] In an example embodiment, the twenty-seventh via V27 and the twenty-eighth via V28 can be located on a same straight line extending along the first direction X.

[0273] In an example embodiment, for the layout in which the twenty-seventh via V27 is disposed between the N+4th unit column and the N+5th unit column, the twenty-eighth via V28 can be disposed between the Nth unit column and the N+1th unit column, between the N+2th unit column and the N+3th unit column, and between the N+6th unit column and the N+7th unit column, respectively.

[0274] In the example implementation, the at least one circuit unit can further include a twenty-ninth via V29. A projection of the twenty-ninth via V29 on the substrate is located within a projection of a dummy electrode block 59-2 of the dummy connection electrode 59 on the substrate, a first planar layer in the twenty-ninth via V29 is removed to expose a surface of a fifth insulating layer covering the dummy electrode block 59-2, and the twenty-ninth via V29 is configured to make a morphology of a first initial connection line and a third initial connection line formed subsequently substantially the same as a morphology of a second initial connection line formed subsequently, thereby improving not only uniformity of an etching process but also uniformity of an anode formed subsequently.

[0275] In the example implementation, four circuit units can be spaced between adjacent twenty-ninth vias V29 in the first direction X. For example, the twenty-ninth via V29 can be arranged between an Nth unit column and an N+1th unit column. For another example, the twenty-ninth via V29 can be arranged between an N+4th unit column and an N+5th unit column.

[0276] In the example implementation, the twenty-sixth via V26 can be referred to as a connection via, the twenty-ninth via V29 can be referred to as a dummy via, a position and a shape of the twenty-sixth via V26 in one circuit unit can be substantially the same as a position and a shape of the twenty-ninth via V29 in another circuit unit, except that a first planar layer and a fifth insulating layer in the twenty-sixth via V26 are removed to expose a surface of the eighth connection electrode 58, thereby enabling connection between the second initial connection line and the eighth connection electrode 58, while only the first planar layer in the twenty-ninth via V29 is removed, and the dummy connection electrode 59 is still covered by the fifth insulating layer, so that the first initial connection line or the third initial connection line formed subsequently will not be connected to the dummy connection electrode 59.

[0277] In the example implementation, the twenty-sixth via V26 and the twenty-ninth via V29 can be located on the same straight line extending along the first direction X.

[0278] In some other embodiments, the display substrate can not be provided with the fifth insulating layer, which is not limited in the present disclosure. For the case that the display substrate is not provided with the fifth insulating layer, the present process can include: directly coating the first planar film on the substrate with the pattern formed thereon, patterning the first planar film by using a half-tone or gray-tone patterning process, forming the first planar layer covering the fourth conductive layer pattern, and the first planar layer being provided with a plurality of vias. The first planar layer in the twenty-sixth via V26 and the twenty-seventh via V27 serving as the connection vias is removed completely, and the surfaces of the seventh connection electrode 57 and the eighth connection electrode 58 are exposed respectively, so that the corresponding initial connection lines can be connected with the seventh connection electrode 57 and the eighth connection electrode 58 respectively. The first planar layer in the twenty-eighth via V28 and the twenty-ninth via V29 serving as the dummy vias is removed partially, and the seventh connection electrode 57 and the dummy connection electrode 59 are still covered by the first planar layer, so that the corresponding initial connection lines formed subsequently will not be connected with the seventh connection electrode 57 and the dummy connection electrode 59. The half-tone or gray-tone patterning process can be used to retain the first planar layer with a partial thickness in the dummy vias, while the first planar layer in the other vias is removed completely.

[0279] (7) Forming the fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer can include: on the substrate with the pattern formed thereon, depositing a fourth conductive film, patterning the fourth conductive film by using a patterning process, and forming the fourth conductive layer disposed on the first planar layer. As shown in FIGS. 15A and 15B, FIG. 15B is a plan view of the fourth conductive layer in FIG. 15A. In an exemplary embodiment, the fourth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0280] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate at least includes: a first power line 71, a data signal line 72, and an anode connection electrode 73.

[0281] In an exemplary embodiment, the first power line 71 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the first power line 71 is connected with the third connection electrode 53 through the twenty-second via V22. Since the third connection electrode 53 is connected with the second plate 32 and the first region of the fifth active layer respectively through the vias, the first power line 71 can write the first power signal to the second plate 32 and the first electrode of the fifth transistor T5.

[0282] In an exemplary embodiment, the first power line 71 can be a variable-width broken line, and a projection of the first power line 71 on the substrate at least partially overlaps with a projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 is a first node N1 of the pixel driving circuit, the first power line 71 with a constant potential can shield the first node N1, avoid the influence of data voltage jump on the first node N1, improve the working stability of the pixel driving circuit, and improve the display effect.

[0283] In an exemplary embodiment, the projection of the first power line 71 on the substrate can contain the projection of the first connection electrode 51 on the substrate, that is, the first power line 71 can completely cover the first connection electrode 51.

[0284] In an exemplary embodiment, the projection of the first power line 71 on the substrate can contain the projection of the first break K1 on the substrate, so that the first power line 71 can shield the first break K1 from above, effectively eliminating the film layer difference between different regions, which is conducive to eliminating shadows and avoiding appearance defects of the display substrate.

[0285] In an exemplary embodiment, the data signal line 72 can be a straight line or a broken line with a main body extending along the second direction Y, and the data signal line 72 is connected to the second connection electrode 52 through the twenty-first via V21. Since the second connection electrode 52 is connected to the first region of the fourth active layer through the via, the data signal line 72 can write data signals to the first electrode of the fourth transistor T4.

[0286] In an exemplary embodiment, the projection of the data signal line 72 on the substrate does not overlap with the channel region of the first transistor T1 to the eighth transistor T8 on the substrate, which can avoid signal crosstalk caused by data voltage jump of the data signal line 72, avoid the influence of data voltage jump on the first transistor T1 to the eighth transistor T8, improve the working stability of the pixel driving circuit, and improve the display effect.

[0287] In an exemplary embodiment, the anode connection electrode 73 can be a strip shape extending along the second direction Y, the anode connection electrode 73 is connected to the fourth connection electrode 54 through the twenty-third via V23, and the anode connection electrode 73 is configured to be connected to the anode formed subsequently. Since the fourth connection electrode 54 is connected to the second region (also the second region of the seventh active layer) of the sixth active layer through the via, the pixel driving circuit can output a driving current to the light emitting device.

[0288] In the example embodiment, the fourth conductive layer can further include a second connection line 82. The second connection line 82 can have a shape of a straight line or a broken line with a main body extending along the second direction Y. In the first direction X, the second connection line 82 can be arranged between the first power lines 71 of the adjacent unit columns, and in the second direction Y, the second connection lines 82 can be arranged at intervals. One of the second connection lines 82 can be connected to the first connection sub-block 83-1 through a twenty-fourth via V24, and the other of the second connection lines 82 can be connected to the second connection sub-block 83-2 through another twenty-fourth via V24, thereby realizing the connection of the two second connection lines 82.

[0289] In the example embodiment, the second connection line 82 in the at least one circuit unit can be provided with a second break K2, which can cut off the second connection line 82 so that the second connection lines 82 on both sides of the second break K2 are insulated from each other.

[0290] In the example embodiment, the orthographic projection of the at least one second break K2 on the substrate at least partially overlaps the orthographic projection of the second initial connection block 42-1 on the substrate.

[0291] In the example embodiment, the orthographic projection of the second break K2 on the substrate can be located within the range of the orthographic projection of the second initial connection block 42-1 on the substrate, so that the second initial connection block 42-1 can pad the second break K2 from below, which can effectively eliminate the film layer difference in different areas, facilitate the elimination of shadows, and avoid the appearance defects of the display substrate.

[0292] In the example embodiment, the second connection line 82 can include a third connection sub-line 82-3 located on the second direction Y side of the second break K2 and a fourth connection sub-line 82-4 located on the opposite side of the second direction Y of the second break K1, the third connection sub-line 82-3 is configured to be connected with the data lead-out line in the binding area, and the fourth connection sub-line 82-4 is configured as a second dummy line.

[0293] In the example embodiment, the fourth connection sub-line 82-4 as the second dummy line can not be connected with any signal line, or can be connected with the first power line, or can be connected with the second power line, which is not limited in the present disclosure.

[0294] In the example embodiment, two circuit units can be spaced between the second connection lines 82 adjacent to each other in the first direction X. For example, the second connection line 82 can be arranged between the first power supply lines 71 of the (N-1)th unit column and the Nth unit column. For another example, the second connection line 82 can be arranged between the first power supply lines 71 of the (N+1)th unit column and the (N+2)th unit column. For another example, the second connection line 82 can be arranged between the first power supply lines 71 of the (N+3)th unit column and the (N+4)th unit column. For another example, the second connection line 82 can be arranged between the first power supply lines 71 of the (N+5)th unit column and the (N+6)th unit column. For another example, the second connection line 82 can be arranged between the first power supply lines 71 of the (N+7)th unit column and the (N+8)th unit column.

[0295] In the example embodiment, since the data connection electrode 83 arranged between the (N-1)th unit column and the Nth unit column is connected with the first connection sub-line 81-1 through the data connection block 84, the first connection sub-line 81-1 is configured to be connected with the data signal line in the display area, and the second connection line 82 is configured to be connected with the data lead-out line in the binding area, the mutual connection between the first connection line 81 extending along the first direction X of the main body part and the second connection line 82 extending along the second direction Y of the main body part is achieved, and the data lead-out line in the binding area is connected with the data signal line in the display area through the first connection line 81 and the second connection line 82.

[0296] In the example embodiment, in the first direction X, the second connection line 82 can be arranged between the adjacent first power supply lines 71, and the first power supply line 71 with a constant potential can shield the influence of the data voltage jump of the second connection line 82 on the key node of the pixel driving circuit, improve the working stability of the pixel driving circuit, and improve the display effect.

[0297] In the example embodiment, the fourth conductive layer can further include a first initial connection line 91. The first initial connection line 91 can have a shape of a straight line or a broken line extending along the second direction Y of the main body part, can be arranged between the data signal lines 72 of part of the adjacent unit columns, and can be connected with the sixth connection electrode 56 through the twenty-fifth via hole V25. Since the sixth connection electrode 56 is connected with the first initial connection block 41-1, and the first initial connection block 41-1 is connected with the first initial signal line 41, the first initial signal line 41 extending along the first direction X and the first initial connection line 91 extending along the second direction Y form a meshed transmission structure of the first initial signal, which can effectively reduce the resistance of the first initial signal line, reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0298] In the example embodiment, the first initial signal lines 41 can be arranged in each unit row, the first initial connection lines 91 can be arranged in part of the unit columns, and 8 circuit units can be arranged between adjacent first initial connection lines 91 in the first direction X. For example, the first initial connection lines 91 can be arranged between the data signal lines 72 of the Nth unit column and the N+1th unit column. For another example, the first initial connection lines 91 can be arranged between the data signal lines 72 of the N+8th unit column and the N+9th unit column.

[0299] In the example embodiment, the fourth conductive layer can further include second initial connection lines 92. The second initial connection lines 92 can be in a straight line shape or a broken line shape with a main body portion extending along the second direction Y, can be arranged between the data signal lines 72 of part of adjacent unit columns, and can be connected to the connection electrode blocks 58-2 through the twenty-sixth vias V26. Since the connection electrode blocks 58-2 are connected to the connection electrode strips 58-1, and the connection electrode strips 58-1 are connected to the second initial signal lines 42, a meshed connection structure for transmitting the second initial signal is formed by the second initial signal lines 42 extending along the first direction X and the second initial connection lines 92 extending along the second direction Y, the resistance of the second initial signal lines can be effectively reduced, the voltage drop of the second initial signal can be reduced, the uniformity of the second initial signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display quality and display performance can be improved.

[0300] In the example embodiment, the second initial signal lines 42 can be arranged in each unit row, the second initial connection lines 92 can be arranged in part of the unit columns, and 4 circuit units can be arranged between adjacent second initial connection lines 92 in the first direction X. For example, the second initial connection lines 92 can be arranged between the data signal lines 72 of the N+2th unit column and the N+3th unit column. For another example, the second initial connection lines 92 can be arranged between the data signal lines 72 of the N+6th unit column and the N+7th unit column.

[0301] In the example embodiment, the fourth conductive layer can further include a third initial connection line 93. The third initial connection line 93 can be in a straight line shape or a broken line shape with a main body portion extending along the second direction Y, can be arranged between the data signal lines 72 of the partially adjacent unit columns, and can be connected to the seventh connection electrode 57 through the twenty-seventh via hole V27. Since the seventh connection electrode 57 is connected to the third initial connection block 43-1, and the third initial connection block 43-1 is connected to the third initial signal line 43, a meshed communication structure for transmitting the third initial signal in a mesh shape is formed by the third initial signal line 43 extending along the first direction X and the third initial connection line 93 extending along the second direction Y, the resistance of the third initial signal line can be effectively reduced, the voltage drop of the third initial signal can be reduced, the uniformity of the third initial signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display quality and display performance can be improved.

[0302] In the example embodiment, the third initial signal line 43 can be arranged in each unit row, the third initial connection line 93 can be arranged in the partially unit columns, and there can be 8 circuit units between the adjacent third initial connection lines 93 along the first direction X. For example, the third initial connection line 93 can be arranged between the data signal lines 72 of the N+4th unit column and the N+5th unit column. For another example, the third initial connection line 93 can be arranged between the data signal lines 72 of the N+12th unit column and the N+13th unit column.

[0303] In the example embodiment, the first initial connection line 91, the second initial connection line 92, the third initial connection line 93, and the second initial connection line 92 can be periodically arranged along the first direction X, two second initial connection lines 92 and one third initial connection line 93 can be arranged between the adjacent two first initial connection lines 91 along the first direction X, one first initial connection line 91 or one third initial connection line 93 can be arranged between the adjacent two second initial connection lines 92 along the first direction X, and one first initial connection line 91 and two second initial connection lines 92 can be arranged between the adjacent two third initial connection lines 93 along the first direction X. Along the first direction X, the first initial connection line 91 can be arranged between the two second initial connection lines 92, the second initial connection line 92 can be arranged between the first initial connection line 91 and the third initial connection line 93, and the third initial connection line 93 can be arranged between the two second initial connection lines 92.

[0304] In the example embodiment, the first initial connection line 91 and the second initial connection line 92 can also fill the twenty-eighth via V28, that is, the first initial connection line 91 and the second initial connection line 92 are at least partially disposed in the dummy via. Since only the first planar layer is removed in the twenty-eighth via V28, the seventh connection electrode 57 is still covered by the fifth insulating layer, or only a partial thickness of the first planar layer is removed in the twenty-eighth via V28, the seventh connection electrode 57 is still covered by the first planar layer, so the first initial connection line 91 and the second initial connection line 92 are not connected to the seventh connection electrode 57.

[0305] In the example embodiment, the first initial connection line 91 and the second initial connection line 92 filling the twenty-eighth via V28 can present a morphology that is substantially the same as the morphology presented by the third initial connection line 93 connecting the seventh connection electrode 57 through the twenty-seventh via V27. This not only enables different regions to achieve the same display effect under transmitted and reflected light, realizes shadow elimination, effectively avoids the occurrence of appearance defects and mura of the display substrate, improves display quality and display performance, but also improves the uniformity of the subsequently formed anode.

[0306] In the example embodiment, the first initial connection line 91 and the third initial connection line 93 can also fill the twenty-ninth via V29, that is, the first initial connection line 91 and the third initial connection line 93 are at least partially disposed in the dummy via. Since only the first planar layer is removed in the twenty-ninth via V29, the dummy connection electrode 59 is still covered by the fifth insulating layer, or only a partial thickness of the first planar layer is removed in the twenty-ninth via V29, the dummy connection electrode 59 is still covered by the first planar layer, so the first initial connection line 91 and the third initial connection line 93 are not connected to the dummy connection electrode 59.

[0307] In the example embodiment, the first initial connection line 91 and the third initial connection line 93 filling the twenty-ninth via V29 can present a morphology that is substantially the same as the morphology presented by the second initial connection line 92 connecting the eighth connection electrode 58 through the twenty-sixth via V26. This not only enables different regions to achieve the same display effect under transmitted and reflected light, realizes shadow elimination, effectively avoids the occurrence of appearance defects and mura of the display substrate, improves display quality and display performance, but also improves the uniformity of the subsequently formed anode.

[0308] In the example embodiment, the first initial connection line 91, the second initial connection line 92, and the third initial connection line 93 are disposed between adjacent data signal lines 72. The first initial connection line 91, the second initial connection line 92, and the third initial connection line 93 having a constant potential can shield the influence between the data signal lines 72, improve the working stability of the pixel driving circuit, and improve the display effect.

[0309] In an example embodiment, the fourth conductive layer pattern of adjacent unit columns (except the second break) can be disposed in mirror symmetry relative to the column center line. For example, the position and shape of the fourth conductive layer in the Nth unit column and the N+1th unit column can be disposed in mirror symmetry relative to the column center line. For another example, the position and shape of the fourth conductive layer in the N+1th unit column and the N+2th unit column can be disposed in mirror symmetry relative to the column center line.

[0310] In an example embodiment, the position and shape of the fourth conductive layer of adjacent unit rows can be substantially the same.

[0311] (8) Forming a second planar layer pattern. In an example embodiment, forming the second planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a second planar film, patterning the second planar film using a patterning process, forming a second planar layer covering the fourth conductive layer pattern, the second planar layer being provided with a plurality of anode vias V30, as shown in FIG. 16.

[0312] In an example embodiment, the orthographic projection of each circuit unit anode via V30 in the display substrate on the substrate is within the range of the orthographic projection of the anode connection electrode 73 on the substrate, the second planar layer in the anode via V30 is removed, exposing the surface of the anode connection electrode 73, and the anode via V30 is configured to enable the anode to be connected to the anode connection electrode 73 through the via formed subsequently.

[0313] So far, the driving structure layer of the present embodiment has been prepared on the substrate. In a plane parallel to the display substrate, the driving structure layer can include a plurality of circuit units, each of which can include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

[0314] In a direction perpendicular to the display substrate, the driving structure layer can include, in sequence on the substrate, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first planar layer, a fourth conductive layer, and a second planar layer. The semiconductor layer can include at least an active layer of a plurality of polysilicon transistors, the first conductive layer can include at least a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, and a first plate of a storage capacitor, the second conductive layer can include at least a first initial signal line, a third initial signal line, and a second plate of a storage capacitor, the third conductive layer can include at least a first connection line, a second initial signal line, and a plurality of connection electrodes, and the fourth conductive layer can include at least a first power supply line, a second connection line, and a data signal line.

[0315] In some other embodiments, the first, second and third initial signal lines can be disposed in at least one of the second and third conductive layers, which are not limited in the present disclosure. For example, the second initial signal line can be disposed in the second conductive layer, and the first and third initial signal lines can be disposed in the third conductive layer. For another example, the first, second and third initial signal lines can all be disposed in the second conductive layer. For yet another example, the first, second and third initial signal lines can all be disposed in the third conductive layer.

[0316] In the exemplary embodiments, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In the exemplary embodiments, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer stacked on a glass carrier plate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate. The first and second inorganic material layers are also called barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0317] In the exemplary embodiments, the first, second, third, fourth and fifth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, multiple layers or a composite layer. The first, second, third and fourth conductive layers can be a metal material such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo), etc., or can be an alloy material composed of metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), etc., and can be a single layer structure or a multi-layer composite structure such as Ti / Al / Ti, etc. The first and second planar layers can be an organic material such as resin or polyimide.

[0318] In the exemplary embodiments, after the preparation of the driving structure layer is completed, the light-emitting structure layer can be prepared on the driving structure layer, and the preparation process of the light-emitting structure layer can include the following operations.

[0319] (9) forming an anode conductive layer pattern. In an example embodiment, forming the anode conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing an anode conductive thin film, patterning the anode conductive thin film using a patterning process, forming an anode conductive layer disposed on the second planar layer, the anode conductive layer including at least a plurality of anode patterns, as shown in FIGS. 17A and 17B, FIG. 17B being a plan view of the anode conductive layer in FIG. 17A.

[0320] In an example embodiment, the plurality of anode patterns can include a first anode 90A located at a red light-emitting unit that emits red light, a second anode 90B located at a blue light-emitting unit that emits blue light, a third anode 90C located at a first green light-emitting unit that emits green light, and a fourth anode 90D located at a second green light-emitting unit that emits green light, the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D can be respectively connected to the anode connection electrode 73 of the circuit unit in which they are located through an anode via V30.

[0321] In an example embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D can include a main body part 90-1 and a connecting part 90-2 connected to each other, the main body part 90-1 can have a rhombus shape, the corner of the rhombus shape can be provided with a rounded chamfer, the connecting part 90-2 can have a strip shape, the first end of the connecting part 90-2 is connected to the main body part 90-1, and the second end of the connecting part 90-2 extends away from the main body part 90-1 and is connected to the anode connection electrode 73 through the anode via V30.

[0322] In an example embodiment, the orthographic projection of the main body part of the first anode 90A and the main body part of the second anode 90B on the substrate at least partially overlaps with the orthographic projection of the second connection line 82 on the substrate, and the orthographic projection of the main body part of the third anode 90C and the main body part of the fourth anode 90D on the substrate does not overlap with the orthographic projection of the second connection line 82 on the substrate, i.e. the second connection line 82 is only disposed below the anodes of the red light-emitting unit and the blue light-emitting unit.

[0323] In an example embodiment, the orthographic projection of the main body part of the third anode 90C and the main body part of the fourth anode 90D on the substrate at least partially overlaps with the orthographic projection of the initial connection line on the substrate, and the orthographic projection of the main body part of the first anode 90A and the main body part of the second anode 90B on the substrate does not overlap with the orthographic projection of the initial connection line on the substrate, i.e. the initial connection line is only disposed below the anodes of the first green light-emitting unit and the second green light-emitting unit. The initial connection line can be the first initial connection line 91, or can be the second initial connection line 92, or can be the third initial connection line 93.

[0324] In the example embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D can have a first center line O1 and a second center line O2, the first center line O1 can be a straight line passing through the geometric center of the body portion of the corresponding anode and extending along the first direction X, and the second center line O2 can be a straight line passing through the geometric center of the body portion of the corresponding anode and extending along the second direction Y.

[0325] In the example embodiment, the body portion of the first anode 90A and the body portion of the second anode 90B each have a projection on the substrate that at least partially overlaps with the projections on the substrate of the three signal lines. The three signal lines can be two first power supply lines 71 and a second connection line 82 located in the fourth conductive layer, the second connection line 82 can be located between the two first power supply lines 71, the projection on the substrate of the second connection line 82 at least partially overlaps with the projection on the substrate of the second center line O2, and the positions of the two first power supply lines 71 can be substantially symmetrically arranged relative to the second connection line 82. In this way, the number of signal lines of the SD2 layer under the body portion of the first anode 90A and the body portion of the second anode 90B at multiple positions is substantially the same, and the signal lines under each anode are symmetrically arranged, which can ensure the flatness and uniformity of the first anode 90A and the second anode 90B, not only can ensure that the light emitting performances of the two light emitting devices are substantially the same, but also can improve the left-right color deviation asymmetry, and can avoid defects such as screen-out watermark caused by the height difference of the anodes, thereby improving the quality of the display substrate.

[0326] In the example embodiment, the body portion of the third anode 90C and the body portion of the fourth anode 90D each have a projection on the substrate that at least partially overlaps with the projections on the substrate of the three signal lines. The three signal lines can be two data signal lines 72 and an initial connection line located in the fourth conductive layer, the initial connection line can be located between the two data signal lines 72, the projection on the substrate of the initial connection line at least partially overlaps with the projection on the substrate of the second center line O2, and the positions of the two data signal lines 72 can be substantially symmetrically arranged relative to the initial connection line. The initial connection line can be a first initial connection line 91, or can be a second initial connection line 92, or can be a third initial connection line 93. In this way, the number of signal lines of the SD2 layer under the body portion of the third anode 90C and the body portion of the fourth anode 90D at multiple positions is substantially the same, and the signal lines under each anode are symmetrically arranged, which can ensure the flatness and uniformity of the third anode 90C and the fourth anode 90D, not only can ensure that the light emitting performances of the two light emitting devices are substantially the same, but also can improve the left-right color deviation asymmetry, and can avoid defects such as screen-out watermark caused by the height difference of the anodes, thereby improving the quality of the display substrate.

[0327] FIG. 17C is a schematic view of the positional relationship between the anode conductive layer and the third conductive layer in FIG. 17A. As shown in FIG. 17C, the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D overlap with the signal lines and the plurality of electrodes in the third conductive layer.

[0328] In an example embodiment, the first anode 90A and the second anode 90B each have a body portion, and the orthographic projections of the body portions of the first anode 90A and the second anode 90B on the substrate at least partially overlap with the orthographic projections of the two lateral lines on the substrate. The two lateral lines can be the first connection line 81 and the electrode connection line 53-1 in the third conductive layer. In the second direction Y, the first connection line 81 can be located on one side of the first center line O1, and the electrode connection line 53-1 can be located on the other side of the first center line O1. The first connection line 81 and the electrode connection line 53-1 can be arranged substantially symmetrically with respect to the first center line O1. In this way, the number of lateral lines of the SD1 layer under the body portions of the first anode 90A and the second anode 90B at multiple positions is substantially the same, and the lateral lines under each anode are arranged symmetrically, which can ensure the flatness and uniformity of the first anode 90A and the second anode 90B. Not only can the light emitting performance of the two light emitting devices be substantially the same, but the left-right color deviation asymmetry can also be improved. In addition, defects such as screen-out watermark caused by the height difference of the anodes can be avoided, and the quality of the display substrate is improved.

[0329] In an example embodiment, the first anode 90A and the second anode 90B each have a body portion, and the orthographic projections of the body portions of the first anode 90A and the second anode 90B on the substrate at least partially overlap with the orthographic projections of the three vertical electrodes on the substrate. The three vertical electrodes can be the two first connection electrodes 51 and the data connection electrode 83 in the third conductive layer. The data connection electrode 83 can be located between the two first connection electrodes 51. The orthographic projection of the data connection electrode 83 on the substrate at least partially overlaps with the orthographic projection of the second center line O2 on the substrate, and the two first connection electrodes 51 can be arranged substantially symmetrically with respect to the data connection electrode 83. In this way, the number of vertical electrodes of the SD1 layer under the body portions of the first anode 90A and the second anode 90B at multiple positions is substantially the same, and the vertical electrodes under each anode are arranged symmetrically, which can ensure the flatness and uniformity of the first anode 90A and the second anode 90B. Not only can the light emitting performance of the two light emitting devices be substantially the same, but the left-right color deviation asymmetry can also be improved. In addition, defects such as screen-out watermark caused by the height difference of the anodes can be avoided, and the quality of the display substrate is improved.

[0330] In an exemplary embodiment, the orthographic projections of the main body of the third anode 90C and the main body of the fourth anode 90D onto the substrate at least partially overlap with the orthographic projection of a transverse line onto the substrate. This transverse line can be a second initial signal line 42 located in the third conductive layer. Thus, the number of transverse lines in the SD1 layer below the main bodies of the third anode 90C and the fourth anode 90D at multiple locations is substantially the same, ensuring the uniformity of the third anode 90C and the fourth anode 90D, and guaranteeing that the luminous performance of the two light-emitting devices is substantially the same.

[0331] In an exemplary embodiment, the orthographic projections of the main body of the third anode 90C and the main body of the fourth anode 90D onto the substrate at least partially overlap with the orthographic projections of the three vertical electrodes onto the substrate. The three vertical electrodes may be two fifth connecting electrodes 55 and a connecting electrode strip 58-1 located in the third conductive layer. The connecting electrode strip 58-1 may be located between the two fifth connecting electrodes 55. The orthographic projection of the connecting electrode strip 58-1 onto the substrate at least partially overlaps with the orthographic projection of the second center line O2 onto the substrate. The two fifth connecting electrodes 55 may be substantially symmetrically arranged relative to the connecting electrode strip 58-1. Alternatively, the three vertical electrodes may be two fifth connecting electrodes 55 and a dummy electrode strip 59-1 (a dummy connecting electrode 59) located in the third conductive layer. The dummy electrode strip 59-1 may be located between the two fifth connecting electrodes 55. The orthographic projection of the dummy electrode strip 59-1 onto the substrate at least partially overlaps with the orthographic projection of the second center line O2 onto the substrate. The two fifth connecting electrodes 55 may be substantially symmetrically arranged relative to the dummy electrode strip 59-1. In this way, the number of vertical electrodes on the SD1 layer below the main body of the third anode 90C and the main body of the fourth anode 90D at multiple locations is basically the same, and the vertical electrodes below each anode are symmetrically arranged. This can ensure the flatness and uniformity of the third anode 90C and the fourth anode 90D, which can not only ensure that the light-emitting performance of the two light-emitting devices is basically the same and improve the asymmetry of left and right color shift, but also avoid defects such as screen-off watermarks caused by the height difference of the anodes, thus improving the quality of the display substrate.

[0332] In an exemplary embodiment, the orthographic projection of the main body portion of the first anode 90A and the main body portion of the second anode 90B onto the substrate may include the orthographic projection of the data connection electrode 83 onto the substrate.

[0333] In an exemplary embodiment, the orthographic projection of the data connection electrode 83 on the substrate can be substantially symmetrically arranged with respect to the orthographic projection of the first center line O1 on the substrate, and the orthographic projection of the data connection electrode 83 on the substrate can be substantially symmetrically arranged with respect to the orthographic projection of the second center line O2 on the substrate.

[0334] In the example embodiment, the normal projection of the first connection sub-block 83-1, the second connection sub-block 83-2 and the connection sub-strip 83-3 in the data connection electrode 83 on the substrate at least partially overlaps with the normal projection of the second center line O2 on the substrate.

[0335] In the example embodiment, the normal projection of the first connection sub-block 83-1 and the second connection sub-block 83-2 in the data connection electrode 83 on the substrate can be arranged substantially symmetrically with respect to the normal projection of the first center line O1 on the substrate. For the twenty-fourth via hole for realizing the connection of the second connection line 82 with the first connection sub-block 83-1 and the twenty-fourth via hole for realizing the connection of the second connection line 82 with the second connection sub-block 83-2, the normal projection of the two twenty-fourth via holes on the substrate can be arranged substantially symmetrically with respect to the normal projection of the first center line O1 on the substrate.

[0336] In the example embodiment, the normal projection of the main body part of the third anode 90C on the substrate at least partially overlaps with the normal projection of the twenty-seventh via hole V27 (connection via hole) on the substrate, and the normal projection of the main body part of the fourth anode 90D on the substrate at least partially overlaps with the normal projection of the twenty-eighth via hole V28 (dummy via hole); or, the normal projection of the main body part of the third anode 90C on the substrate at least partially overlaps with the normal projection of the twenty-eighth via hole V28 (dummy via hole), and the normal projection of the main body part of the fourth anode 90D on the substrate at least partially overlaps with the normal projection of the twenty-seventh via hole V27 (connection via hole). The present disclosure can not only improve the uniformity of the third anode 90C and the fourth anode 90D by arranging the dummy via hole so that the first planar layer via hole (PLN via hole) is arranged below the main body part of the third anode 90C and the main body part of the fourth anode 90D at multiple positions, but also enable different regions to achieve the same display effect under transmitted and reflected light, realize shadow elimination, effectively avoid the occurrence of appearance defects of the display substrate and screen-off watermark, and improve the display quality and display performance.

[0337] In some other embodiments, the normal projection of the main body part of the third anode 90C on the substrate at least partially does not overlap with the normal projection of the twenty-seventh via hole V27 (connection via hole) on the substrate, and the normal projection of the main body part of the fourth anode 90D on the substrate at least partially does not overlap with the normal projection of the twenty-eighth via hole V28 (dummy via hole); or, the normal projection of the main body part of the third anode 90C on the substrate at least partially does not overlap with the normal projection of the twenty-eighth via hole V28 (dummy via hole), and the normal projection of the main body part of the fourth anode 90D on the substrate at least partially does not overlap with the normal projection of the twenty-seventh via hole V27 (connection via hole), which is not limited in the present disclosure.

[0338] In the example embodiment, the anode conductive layer can adopt a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or can adopt a multi-layer composite structure, such as ITO / Ag / ITO, etc.

[0339] In the example embodiment, the subsequent preparation process can include: first forming a pixel definition layer, the pixel definition layer being provided with a plurality of pixel openings, the plurality of pixel openings respectively exposing the first anode, the second anode, the third anode and the fourth anode. Then, an organic light-emitting layer is formed by using an evaporation or inkjet printing process, and then a cathode is formed on the organic light-emitting layer, and then a packaging structure layer is formed, the packaging structure layer can include a first packaging layer, a second packaging layer and a third packaging layer which are stacked, the first packaging layer and the third packaging layer can adopt inorganic materials, the second packaging layer can adopt an organic material, and the second packaging layer is arranged between the first packaging layer and the third packaging layer, so as to ensure that external water vapor cannot enter the light-emitting structure layer.

[0340] The example embodiment of the present disclosure provides a display substrate, by adopting pixel driving circuit mirror symmetry design and circuit node sharing, the first transistor T1 in adjacent unit columns is mirror arranged and shares the first electrode of the first transistor T1, the seventh transistor T7 in adjacent unit columns is mirror arranged and shares the first electrode of the seventh transistor T7, and the eighth transistor T8 in adjacent unit columns is mirror arranged and shares the first electrode of the eighth transistor T8, which can effectively reduce the layout space, reduce the number of vias and connection electrodes, reduce the occupied area of the pixel driving circuit, and is conducive to realizing high resolution.

[0341] The example embodiment of the present disclosure binds the data lead-out line of the binding area to the data signal line through the first connection line and the second connection line by arranging the first connection line and the second connection line in the display area, so that the fan-shaped diagonal line does not need to be arranged in the lead-out line area, the length of the lead-out line area is effectively reduced, the lower frame width is greatly reduced, the screen ratio is improved, and the full-screen display is facilitated.

[0342] The example embodiment of the present disclosure can effectively reduce the leakage of the first transistor T1 and the second transistor T2 by arranging the first transistor T1 and the second transistor T2 in the double-gate structure, and is conducive to meeting the needs of low-frequency display.

[0343] The first shielding electrode and the second shielding electrode are arranged, the first shielding electrode forms a coupling capacitor with the first active layer between the two gate electrodes of the first transistor T1, and is connected with the third initial signal line, the second shielding electrode forms a coupling capacitor with the second active layer between the two gate electrodes of the second transistor T2, and is connected with the first initial signal line, on the one hand, the node between the two gate electrodes of the first transistor T1 and the second transistor T2 can be shielded, the influence of data voltage jump on the first transistor T1 and the second transistor T2 is avoided, the normal work of the pixel driving circuit affected by the data voltage jump is reduced, and on the other hand, the leakage of the first transistor T1 and the second transistor T2 is further reduced by using the coupling capacitor, and the display effect is improved.

[0344] The third shielding electrode is arranged between the second region of the first active layer in the semiconductor layer and the first connection line in the third conductive layer, and is connected with the first initial signal line, the third shielding electrode can shield the first connection line, avoid the influence of data voltage jump in the first connection line on the first transistor T1 and the second transistor T2, reduce the normal work of the pixel driving circuit affected by the data voltage jump, and improve the display effect.

[0345] The fourth shielding electrode is arranged between the first node N1 and the data signal line, and is connected with the first initial signal line, the influence of the data signal line on the first node N1 can be avoided, the normal work of the pixel driving circuit affected by the data voltage jump is reduced, and the display effect is improved.

[0346] The first initial signal line extending along the first direction X and the first initial connection line extending along the second direction Y are arranged, and the first initial signal line and the first initial connection line are connected with each other, a mesh communication structure for transmitting the first initial signal is formed on the display substrate, not only the resistance of the first initial signal line can be effectively reduced, the voltage drop of the first initial signal is reduced, but also the uniformity of the first initial signal in the display substrate can be effectively improved, the display uniformity is effectively improved, and the display quality and display effect are improved.

[0347] The second initial signal line extending along the first direction X and the second initial connection line extending along the second direction Y are arranged, and the second initial signal line and the second initial connection line are connected with each other, a mesh communication structure for transmitting the second initial signal is formed on the display substrate, not only the resistance of the second initial signal line can be effectively reduced, the voltage drop of the second initial signal is reduced, but also the uniformity of the second initial signal in the display substrate can be effectively improved, the display uniformity is effectively improved, and the display quality and display effect are improved.

[0348] The third initial signal line and the third initial connection line are connected with each other, a mesh communication structure for transmitting the third initial signal is formed on the display substrate, the resistance of the third initial signal line can be effectively reduced, the voltage drop of the third initial signal can be reduced, the uniformity of the third initial signal in the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display quality and the display performance are improved.

[0349] The second connection line is arranged below the anodes of the red light emitting unit and the blue light emitting unit, and the initial connection line is arranged below the anodes of the first green light emitting unit and the second green light emitting unit, so that the light emitting performance of the plurality of light emitting devices is basically the same.

[0350] The third anode and the fourth anode are arranged, the orthographic projection of the main body part of the third anode and the fourth anode on the substrate at least partially overlaps the orthographic projection of the one horizontal line on the substrate, at least partially overlaps the orthographic projection of the three vertical electrodes on the substrate, and at least partially overlaps the orthographic projection of the three signal lines on the substrate, so that the metal lines below the third anode and the fourth anode are basically the same, and the metal lines below each anode are symmetrically arranged, the flatness and the uniformity of the third anode and the fourth anode are ensured, the light emitting performance of the two light emitting devices is basically the same, the left-right color deviation asymmetry is improved, and the screen-out watermark defect caused by the height difference of the anode is avoided, and the quality of the display substrate is improved.

[0351] The third anode and the fourth anode are arranged, the orthographic projection of the main body part of the third anode and the fourth anode on the substrate at least partially overlaps the orthographic projection of the one horizontal line on the substrate, at least partially overlaps the orthographic projection of the three vertical electrodes on the substrate, and at least partially overlaps the orthographic projection of the three signal lines on the substrate, so that the metal lines below the third anode and the fourth anode are basically the same, and the metal lines below each anode are symmetrically arranged, the flatness and the uniformity of the third anode and the fourth anode are ensured, the light emitting performance of the two light emitting devices is basically the same, the left-right color deviation asymmetry is improved, and the screen-out watermark defect caused by the height difference of the anode is avoided, and the quality of the display substrate is improved.

[0352] The third anode and the fourth anode are arranged, the orthographic projection of the main body part of the third anode and the fourth anode on the substrate at least partially overlaps the orthographic projection of the one horizontal line on the substrate, at least partially overlaps the orthographic projection of the three vertical electrodes on the substrate, and at least partially overlaps the orthographic projection of the three signal lines on the substrate, so that the metal lines below the third anode and the fourth anode are basically the same, and the metal lines below each anode are symmetrically arranged, the flatness and the uniformity of the third anode and the fourth anode are ensured, the light emitting performance of the two light emitting devices is basically the same, the left-right color deviation asymmetry is improved, and the screen-out watermark defect caused by the height difference of the anode is avoided, and the quality of the display substrate is improved.

[0353] The 8T1C pixel driving circuit structure and the 2SD FIP are fused through the above structure, which can not only improve the flicker of low-frequency display, but also reduce the lower border width and improve the screen ratio. Through the optimization of the pixel driving circuit layout, the up and down color deviation and the left and right color deviation can be improved, and the occupied area of the pixel driving circuit can be reduced, so as to improve the resolution and the transmittance.

[0354] The preparation process of the embodiment of the present disclosure can be well compatible with the existing preparation process, and the process is simple to implement, high in production efficiency, low in production cost and high in yield.

[0355] The foregoing structure and the preparation process thereof of the present disclosure are only exemplary descriptions, and in the exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or reduced according to actual needs.

[0356] In the exemplary embodiments, the display substrate of the present disclosure can be applied to a display device with a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), or quantum dot light-emitting diode display (QDLED), which is not limited herein.

[0357] The present disclosure also provides another display substrate. In the exemplary embodiments, the display substrate includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit and at least one initial signal line; the pixel driving circuit includes at least one initialization transistor, and the initial signal line is connected with the initialization transistor through a connection electrode; in at least one unit row, two initialization transistors in adjacent circuit units are connected with the connection electrode through the same via, or two connection electrodes in adjacent circuit units are connected with the initial signal line through the same via.

[0358] In the exemplary embodiments, the at least one initial signal line can include a first initial signal line, and the at least one initialization transistor can include a first transistor as a first initialization transistor. The first transistor includes at least a first active layer, and the first initial signal line is connected with a first region of the first active layer through a sixth connection electrode. Among them, the pixel driving circuits in adjacent circuit units share the first region of the first active layer, the pixel driving circuits in adjacent circuit units share the sixth connection electrode, and the sixth connection electrode is connected with the first regions of two first active layers in adjacent circuit units through the same via.

[0359] In an exemplary embodiment, the at least one initial signal line can include a second initial signal line, and the at least one initialization transistor can include a seventh transistor as a second initialization transistor. The seventh transistor includes at least a seventh active layer, and the second initial signal line is connected to a first region of the seventh active layer through a second initial connection block. The pixel driving circuit in an adjacent circuit unit shares the first region of the seventh active layer, and the pixel driving circuit in the adjacent circuit unit shares the second initial connection block, which is connected to the first regions of the seventh active layers in two adjacent circuit units through a same via.

[0360] In an exemplary embodiment, the at least one initial signal line can include a third initial signal line, and the at least one initialization transistor can include an eighth transistor as a third initialization transistor. The eighth transistor includes at least an eighth active layer, and the third initial signal line is connected to a first region of the eighth active layer through a seventh connection electrode. The seventh connection electrodes in adjacent circuit units are an integrated structure connected to each other, the pixel driving circuit in an adjacent circuit unit shares the seventh connection electrode, and the third initial signal line is connected to the seventh connection electrodes in two adjacent circuit units through a same via.

[0361] The present disclosure also provides a preparation method of a display substrate to manufacture the display substrate provided in the above embodiments. In an exemplary embodiment, the preparation method can include:

[0362] forming a driving structure layer on a substrate; the driving structure layer includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit including a pixel driving circuit, a first initial signal line, a second initial signal line, and a third initial signal line; the pixel driving circuit includes at least a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor, and an eighth transistor as a third initialization transistor, the first initial signal line being connected to a first electrode of the first transistor, the second initial signal line being connected to a first electrode of the seventh transistor, and the third initial signal line being connected to a first electrode of the eighth transistor; in at least one unit row, the pixel driving circuit in at least two adjacent circuit units shares the first electrode of the first transistor, the pixel driving circuit in at least two adjacent circuit units shares the first electrode of the seventh transistor, and the pixel driving circuit in at least two adjacent circuit units shares the first electrode of the eighth transistor;

[0363] forming a light-emitting structure layer on the driving structure layer.

[0364] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0365] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, the driving structure layer comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, a first initial signal line, a second initial signal line and a third initial signal line; the pixel driving circuit comprising at least a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor and an eighth transistor as a third initialization transistor, the first initial signal line being connected with a first electrode of the first transistor, the second initial signal line being connected with a first electrode of the seventh transistor, and the third initial signal line being connected with a first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share the first electrode of the eighth transistor. 2.The display substrate of claim 1, wherein, The first transistor comprises at least a first active layer, and the first initial signal line is connected with a first region of the first active layer through a sixth connection electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the sixth connection electrode. 3.The display substrate of claim 1, wherein, The seventh transistor comprises at least a seventh active layer, and the second initial signal line is connected with a first region of the seventh active layer through a second initial connection block; in at least one unit row, the pixel driving circuits in adjacent circuit units share the second initial connection block. 4.The display substrate of claim 1, wherein, The eighth transistor comprises at least an eighth active layer, and the third initial signal line is connected with a first region of the eighth active layer through a seventh connection electrode; in at least one unit row, the pixel driving circuits in adjacent circuit units share the seventh connection electrode. 5.The display substrate of claim 1, wherein, The first initial signal line, the second initial signal line and the third initial signal line extend along a first direction, and the driving structure layer further comprises a first initial connection line, a second initial connection line and a third initial connection line extending along a second direction, the first direction and the second direction intersecting; the first initial connection line is connected with the first initial signal line through a sixth connection electrode, forming a meshed communication structure for transmitting a first initial signal, or the second initial connection line is connected with the second initial signal line through an eighth connection electrode, forming a meshed communication structure for transmitting a second initial signal, or the third initial connection line is connected with the third initial signal line through a seventh connection electrode, forming a meshed communication structure for transmitting a third initial signal. 6.The display substrate of claim 5, wherein, The first initial connection line, the second initial connection line and the third initial connection line are respectively disposed between adjacent unit columns, and the first initial connection line, the second initial connection line, the third initial connection line and the second initial connection line are periodically arranged in the first direction. 7.The display substrate of claim 5, wherein, The light-emitting structure layer comprises at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units comprise at least a first anode, the blue light-emitting units comprise at least a second anode, the first green light-emitting units comprise at least a third anode, and the second green light-emitting units comprise at least a fourth anode, at least one of the first anode, the second anode, the third anode, and the fourth anode comprises a main body portion and a connecting portion connected to each other, a first end of the connecting portion is connected to the main body portion, and a second end of the connecting portion is connected to an anode connection electrode in the pixel driving circuit through an anode via hole; a normal projection of the main body portion of the third anode and the main body portion of the fourth anode on the substrate at least partially overlaps with a normal projection of the first initial connection line on the substrate, or a normal projection of the main body portion of the third anode and the main body portion of the fourth anode on the substrate at least partially overlaps with a normal projection of the second initial connection line on the substrate, or a normal projection of the main body portion of the third anode and the main body portion of the fourth anode on the substrate at least partially overlaps with a normal projection of the third initial connection line on the substrate. 8.The display substrate of claim 5, wherein, In a direction perpendicular to the substrate, the driving structure layer comprises at least a first conductive layer arranged on the substrate, a second conductive layer arranged on a side of the first conductive layer away from the substrate, a third conductive layer arranged on a side of the second conductive layer away from the substrate, and a fourth conductive layer arranged on a side of the third conductive layer away from the substrate, the first initial signal line, the second initial signal line, and the third initial signal line are arranged in at least one of the second conductive layer and the third conductive layer, and the first initial connection line, the second initial connection line, and the third initial connection line are arranged in the fourth conductive layer. 9.The display substrate of claim 8, wherein, The driving structure layer further comprises a first planar layer arranged on a side of the third conductive layer away from the substrate, and the fourth conductive layer is arranged on a side of the first planar layer away from the substrate; at least one circuit unit further comprises a connection via hole, and the third initial connection line is connected to the seventh connection electrode through the connection via hole; and at least another circuit unit further comprises a dummy via hole, and the first initial connection line and / or the second initial connection line are arranged at least partially in the dummy via hole. 10.The display substrate of claim 9, wherein, The light-emitting structure layer comprises at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units comprise at least a first anode, the blue light-emitting units comprise at least a second anode, the first green light-emitting units comprise at least a third anode, and the second green light-emitting units comprise at least a fourth anode, at least one of the first anode, the second anode, the third anode, and the fourth anode comprises a main body portion and a connecting portion connected to each other, a first end of the connecting portion is connected to the main body portion, and a second end of the connecting portion is connected to an anode connection electrode in the pixel driving circuit through an anode via hole; a normal projection of the main body portion of the third anode on the substrate at least partially overlaps a normal projection of the connecting via hole on the substrate, and a normal projection of the main body portion of the fourth anode on the substrate at least partially overlaps a normal projection of the dummy via hole on the substrate. Alternatively, a normal projection of the main body portion of the third anode on the substrate at least partially overlaps a normal projection of the dummy via hole on the substrate, and a normal projection of the main body portion of the fourth anode on the substrate at least partially overlaps a normal projection of the connecting via hole on the substrate. 11.The display substrate of claim 9, wherein, The light-emitting structure layer comprises at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units comprise at least a first anode, the blue light-emitting units comprise at least a second anode, the first green light-emitting units comprise at least a third anode, and the second green light-emitting units comprise at least a fourth anode, at least one of the first anode, the second anode, the third anode, and the fourth anode comprises a main body portion and a connecting portion connected to each other, a first end of the connecting portion is connected to the main body portion, and a second end of the connecting portion is connected to an anode connection electrode in the pixel driving circuit through an anode via hole; a normal projection of the main body portion of the third anode on the substrate at least partially does not overlap a normal projection of the connecting via hole on the substrate, and a normal projection of the main body portion of the fourth anode on the substrate at least partially does not overlap a normal projection of the dummy via hole on the substrate. Alternatively, a normal projection of the main body portion of the third anode on the substrate at least partially does not overlap a normal projection of the dummy via hole on the substrate, and a normal projection of the main body portion of the fourth anode on the substrate at least partially does not overlap a normal projection of the connecting via hole on the substrate. 12.The display substrate of claim 5, wherein, The eighth connection electrode includes a connection electrode strip and a connection electrode block, the connection electrode strip has a strip shape extending along the second direction, the connection electrode block has a block shape, a first end of the connection electrode strip is connected to the second initial signal line, a second end of the connection electrode strip extends away from the second initial signal line and is connected to the connection electrode block, and the second initial connection line is connected to the connection electrode block through a via hole; the at least one circuit unit further includes a dummy electrode strip, a first end of the dummy electrode strip is connected to the second initial signal line, and a second end of the dummy electrode strip extends away from the second initial signal line; the connection electrode strip and the dummy electrode strip are alternately arranged in the first direction. 13.The display substrate of claim 12, wherein, The at least one circuit unit further includes a dummy electrode block and a dummy via hole, the dummy electrode block has a block shape and is connected to the second end of the dummy electrode strip, and a projection of the dummy via hole on the substrate is located within a projection range of the dummy electrode block on the substrate; and the first initial connection line and / or the third initial connection line are at least partially arranged in the dummy via hole. 14.The display substrate of claim 13, wherein, The connection electrode block and the dummy electrode block are located on a straight line extending along the first direction. 15.The display substrate of claim 12, wherein, The light-emitting structure layer includes at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light, the red light-emitting units include at least a first anode, the blue light-emitting units include at least a second anode, the first green light-emitting units include at least a third anode, and the second green light-emitting units include at least a fourth anode, at least one of the first anode, the second anode, the third anode, and the fourth anode includes a main body portion and a connection portion connected to each other, a first end of the connection portion is connected to the main body portion, and a second end of the connection portion is connected to an anode connection electrode in the pixel driving circuit through an anode via hole; a projection of the main body portion of the third anode on the substrate at least partially overlaps with a projection of the connection electrode strip on the substrate, and a projection of the main body portion of the fourth anode on the substrate at least partially overlaps with a projection of the dummy electrode strip on the substrate. Alternatively, a projection of the main body portion of the third anode on the substrate at least partially overlaps with a projection of the dummy electrode strip on the substrate, and a projection of the main body portion of the fourth anode on the substrate at least partially overlaps with a projection of the connection electrode strip on the substrate. 16.The display substrate of claim 1, wherein, The pixel driving circuit further includes a second transistor as a compensation transistor and a third transistor as a driving transistor, a first electrode of the second transistor is connected to a second electrode of the first transistor and a gate electrode of the third transistor respectively, and a second electrode of the second transistor is connected to a second electrode of the third transistor; the first transistor and the second transistor have a double-gate structure. 17.The display substrate of claim 1, wherein, The driving structure layer further comprises a plurality of data signal lines extending along a second direction, a plurality of first connection lines extending along a first direction, and a plurality of second connection lines extending along the second direction, the first direction and the second direction intersecting; at least one data signal line is connected with the plurality of pixel driving circuits of one unit column, first ends of the plurality of first connection lines are connected with the plurality of data signal lines correspondingly, and second ends of the plurality of first connection lines are connected with the plurality of second connection lines correspondingly. 18.The display substrate of claim 17, wherein, The light-emitting structure layer comprises at least a plurality of red light-emitting units emitting red light, a plurality of blue light-emitting units emitting blue light, a plurality of first green light-emitting units emitting green light, and a plurality of second green light-emitting units emitting green light; the red light-emitting unit comprises at least a first anode, the blue light-emitting unit comprises at least a second anode, the first green light-emitting unit comprises at least a third anode, and the second green light-emitting unit comprises at least a fourth anode; at least one of the first anode, the second anode, the third anode, and the fourth anode comprises a main body portion and a connection portion connected with each other, a first end of the connection portion is connected with the main body portion, and a second end of the connection portion is connected with an anode connection electrode in the pixel driving circuit through an anode via hole; a normal projection of the main body portion of the first anode and a normal projection of the main body portion of the second anode on the substrate at least partially overlap with a normal projection of the second connection line on the substrate.

19. The display substrate of claim 18, wherein, The driving structure layer further comprises a data connection electrode, the second connection line is connected with the data connection electrode through a via hole; a normal projection of the data connection electrode on the substrate is located within a range of the normal projection of the main body portion of the first anode on the substrate, and / or a normal projection of the data connection electrode on the substrate is located within a range of the normal projection of the main body portion of the second anode on the substrate.

20. A display substrate comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit and at least one initial signal line; the pixel driving circuit comprising at least one initialization transistor, the initial signal line being connected with the initialization transistor through a connection electrode; in at least one unit row, two initialization transistors in adjacent circuit units are connected with the connection electrode through the same via hole, or two connection electrodes in adjacent circuit units are connected with the initial signal line through the same via hole.

21. A display device comprising the display substrate according to any one of claims 1 to 19.

22. A method for manufacturing a display substrate, comprising: forming a driving structure layer on a substrate; the driving structure layer comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, a first initial signal line, a second initial signal line, and a third initial signal line; The pixel driving circuit comprises at least a first transistor as a first initialization transistor, a seventh transistor as a second initialization transistor and an eighth transistor as a third initialization transistor, the first initialization signal line is connected with the first electrode of the first transistor, the second initialization signal line is connected with the first electrode of the seventh transistor, and the third initialization signal line is connected with the first electrode of the eighth transistor; in at least one unit row, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the first transistor, the pixel driving circuits in at least two adjacent circuit units share the first electrode of the seventh transistor, and the pixel driving circuits in at least two adjacent circuit units share the first electrode of the eighth transistor; A light-emitting structure layer is formed on the driving structure layer.

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