N-way doherty amplifier

Abstract

An aspect of the present disclosure relates to an N-way Doherty amplifier, wherein is an integer greater than three. An example of such an amplifier is a 4-way Doherty amplifier. A further aspect of the present disclosure relates to a base station for mobile telecommunications comprising such an N-way Doherty amplifier. According to the present disclosure, a novel DPA topology is provided in which the power amplifying devices are arranged in branches and wherein the order in which the peaking amplifiers switch on with increasing input power is defined by their position in the branch and the branch number.

Description

[0001] ^-WAY DOHERTY AMPLIFIER Field An aspect of the present disclosure relates to an ^-way Doherty amplifier, wherein ^ is an integer greater than three. An example of such an amplifier is a 4-way Doherty amplifier. A further aspect of the present disclosure relates to a base station for mobile telecommunications comprising such an ^-way Doherty amplifier. Background In modern wireless communication, the pursuit of higher data rates and expanded network capacity has prompted the adoption of spectral-efficient modulation techniques in wideband or multi-band scenarios. This leads to a strong increase in signal bandwidth and peak-to-average power ratio, posing challenges for the power amplifier, ‘PA’, which is required not only to exhibit optimum efficiency over a large power back-off range but also over a large RF bandwidth. Among the efficiency enhancement techniques, the Doherty power amplifier, ‘DPA’, is the most widely used in the base station market, since it can offer high power and high average efficiency at a relatively low circuit complexity. In a DPA, the main amplifier or carrier amplifier, wording that is used interchangeably throughout this description, is typically biased in class AB or class B and amplifies the input RF signal at substantially all power levels. The peak or peaking amplifiers, wording that is used interchangeably throughout this description, are typically biased in class C, and only amplify the RF input signal when the power level of this signal is sufficiently high. When a given peak or peaking amplifier amplifies the RF input signal depends on the biasing setting that is used for that amplifier. Hereinafter, changing from a situation in which a peak or peaking amplifier is not amplifying the RF input signal to a situation in which it is amplifying the RF input signal will be interchangeably referred to as switching on the peak or peaking amplifier or as activating the peak or peaking amplifier. The traditional symmetrical two-way DPA, using equally sized devices for the main and peaking amplifier, was originally introduced to enhance efficiency at 6 dB power back-off. Subsequently, the asymmetrical two-way DPA employing a peaking amplifier that is significantly larger in size than its main amplifier has gained popularity since it can offer high efficiency over an extended power back-off, typically up to 9 dB. However, this achievement comes at the cost of a notable efficiency decline in the transitional region between its two efficiency peaks. To overcome this drawback, ^-way DPA topologies have been proposed. They employ more than one peaking amplifier, activating them sequentially to maintain high efficiency throughout the intended power back-off region. In the prior art, two types of three-way DPA topologies are known, which are hereinafter referred to as the classical three-way DPA as described in the paper “A mixed-signal approach towards linear and efficient N-way Doherty amplifiers”, by W. C. Neo et al, IEEE Transactions on Microwave Theory and Techniques, vol.55, no.5, pp.866–878, 2007, and as the novel three-way DPA as described in US 2010315162A1. Both types offer improved efficiency over a large power backoff range (e.g. up to 12 dB). The classical three-way DPA necessitates the use of active devices with increasing peripheries for the subsequent peaking amplifiers and rather challenging driving profiles, e.g. deep saturation of the main amplifier, to achieve proper output power combining. As a result, the main amplifier benefits from a relatively low load modulation factor enhancing efficiency and bandwidth in power back-off but typically at the cost of linearity when considering practical implementations. In contrast, the novel three-way DPA is better suited for using identical active device peripheries while ensuring linear operation for all branch amplifiers. However, its main amplifier suffers from a high load modulation factor, impacting efficiency and bandwidth in power back-off. Four-way DPAs can in theory offer high efficiency at even larger power back-off range than three-way DPAs. However, in practice this comes at the expense of an increased design complexity. Four-way DPAs demand more accurate drive profiles for the main and peaking amplifiers, yielding often less-convincing results than theory originally suggested. Furthermore, they face challenges in achieving wideband performance. An object of the present disclosure is to provide design options for linear broadband ^-way Doherty amplifiers in which the abovementioned problems do not occur or to a lesser extent, and wherein ^ is an integer greater than three. According to the present disclosure this object is achieved using the ^-way Doherty amplifier as defined in claim 1 which comprises ^ parallel amplifier branches ^^^, each ^thamplifier branch ^^^comprising ^^nodes ^^^,^, ^^power generating devices ^^,^, and ^^impedance inverters ^^^^,^, wherein ^ is an index in a range [1, ^], and wherein for each value of ^,^ is an index in a range [1, ^^], wherein for ^ > 1 ^^ is an even integer equal to or greater than 2,wherein ^^is an integer equal to or greater than 2, and wherein: An output of each power generating device is connected to the node ^^^,^.Furthermore, for each value of index ^ and for each value of index ^ ≠ impedance inverter^^^^,^is arranged in between the node ^^^,^and the node ^^^,^^^. For each value of index ^ and for each value of index ^ = impedance inverter ^^^^,^ isarranged in between the node ^^^,^and a common combining node C that is electrically connected to an output of the ^-way Doherty amplifier. In addition, the power generating device ^^,^forms a carrier amplifier, and each power generating device ^^,^different from power generating device ^^,^forms a peaking amplifier. Each power generating device ^^,^is associated with a respective switching order ^^,^given by: wherein ^^ = 0. The switching orders ^^,^ describe the order in which the corresponding powergenerating devices ^^,^switch on when ramping up the power outputted by the ^-way Doherty amplifier starting with the power generating device ^^,^. The Applicant has found that ^-way Doherty amplifiers configured as described above offer superior wideband capability and allow the use of a relatively simple power combiner. The combining node can be connected to a load either directly or through one or more impedance matching stages, which are typically implemented using quarter wavelength transmission lines or lumped equivalents thereof. The power generating device associated with a switching order equal to can be configured to switch on when the power generating device associated with the switching orderequal to − 1 reaches voltage saturation, wherein is an integer in a range [2, ^]. Additionally,or alternatively, can be an even integer. An electrical length between each of the nodes ^^^,^ for which ^ = can equal or close to# times 180 degrees at an operational frequency of the ^-way Doherty amplifier, wherein n is an integer. In this manner, little to no impedance transformation occurs between the output of thepower generating devices and the common combining node.At least one of the impedance inverters ^^^^,^ for which ^ may comprise atransmission line of which an electrical length is equal or close to (2% + 1) times 90 degrees at an operational frequency of the ^-way Doherty amplifier, wherein % is an integer. Additionally, or alternatively, at least one of the impedance inverters ^^^^,^can be an equivalent impedance inverter that is formed using a lumped equivalent of a transmission line that has an electrical lengththat is equal or close to (2% + 1) times 90 degrees at an operational frequency of the ^-wayDoherty amplifier, wherein m is an integer. Such lumped equivalent circuits require less space than their distributed counterparts. At least one equivalent impedance inverter may further incorporate an output capacitance of at least one power generating device. Typically, the output capacitance of the amplifiers is compensated for, for example by arranging a shunt inductor in parallel such that the combination of the output capacitance and shunt inductor resonates at or close to the operating frequency. However, by incorporating the output capacitance, it is used as part of the equivalent impedance inverter. At least one equivalent impedance inverter may comprise a C-L-C or L-C-L lumped equivalent circuit. For example, an equivalent impedance inverter corresponding to impedance inverter ^^^^,^for which ^ may comprise a C-L-C lumped equivalent circuit that is formed using an outputcapacitance of the power generating device ^^,^, an output capacitance of the power generating device ^^,^^^, and a series inductor arranged in between the outputs of power generating device ^^,^and power generating device ^^,^^^. Furthermore, an equivalent impedance invertercorresponding to impedance inverter ^^^^,^ for which ^ = may comprise a C-L-C lumpedequivalent circuit that is formed using an output capacitance of the power generating devices a shunt capacitance connected at the combining node, and a series inductor arranged in between the output of the power generating device ^^,^and the combining node. The series inductors in these networks may comprise one or more bond-wires. In case of C-L-C equivalent networks, the ^-way Doherty amplifier may further comprise, for an equivalent impedance inverter corresponding to the impedance inverter ^^^^,^, a shunt inductor connected to the output of the power generating device ^^,^, and / or a shunt inductorconnected to the output of power generating device ^^,^^^ provided that ^ < for partiallycompensating the output capacitance of power generating device ^^,^or the output capacitance of power generating device ^^,^^^, respectively. These shunt inductors allow for partially compensating the output capacitances if these are too large for forming a C-L-C equivalent of a transmission line with a particular characteristic impedance. In other embodiments, where the output capacitances are too low, additional capacitors can be connected to the outputs of the amplifiers, thereby effectively increasing the output capacitance. Alternatively, an equivalent impedance inverter corresponding to impedance inverter^^^^,^ for which ^ ≠ may comprise a L-C-L lumped equivalent circuit that is formed using afirst shunt inductor connected to the output of the power generating device ^^,^, a second shunt inductor connected to the output of the power generating device ^^,^^^, and a series capacitor arranged in between the outputs of power generating device ^^,^and power generating device ^^,^^^. Additionally, or alternatively, an equivalent impedance inverter corresponding toimpedance inverter ^^^^,^ for which for which ^ = nay comprise a L-C-L lumped equivalentcircuit that is formed using a first shunt inductor connected to the output of the power generating device ^^,^, a second shunt inductor connected to the combining node, and a series capacitor arranged in between the output of the power generating device ^^,^and the combining node. When using L-C-L networks, the shunt inductors may be arranged in series with a DC blocking capacitor to prevent a DC path to ground. In the abovementioned embodiments, shunt elements such as capacitors or inductors, that are arranged in parallel can be combined into a single element. The ^-way Doherty amplifier can be configured for amplifying an input analog RF signal, wherein each power generating device ^^,^is separately biased to achieve the switching order with increasing power level of the input analog RF signal. The carrier amplifier may be biased in class AB or class B, and the peaking amplifiers may be biased in class C. The ^-way Doherty amplifier may further comprise a Doherty splitter for splitting the input analog RF signal into respective parts, wherein each part is provided to a respective power generating device ^^,^, wherein the impedance inverters ^^^^,^and the Doherty splitter are configured for ensuring that signals amplified by the power generating devices add up in-phase at the combining node. One or more power generating device ^^,^can be configured for transforming a digital control word into an analog signal emerging at its or their output(s). In this case, the ^-way Doherty amplifier may comprise one or more controllers corresponding to the one or more power generating devices each controller being configured for generating, for the corresponding power generating device ^^,^, a digital control word. In this case, the order by which the power generating devices are switched on with an increasing level of power outputted by the ^-way Doherty amplifier can be controlled by the one or more controllers. In these embodiments, each power generating device may comprise multiple transistor segments that are arranged in parallel and that can each be separately controlled using a respective bit of the digital control word that is provided to that power generating device. Each controller may comprise an input for receiving digital input data, a processing unit configured for generating the bits of the digital control word for the corresponding power generating device ^^,^based on the digital input data, and a modulation unit comprising a plurality of logical gates, wherein the modulation unit is configured to modulate the bits of the digital control word using one or more local oscillator or clock activation signals and the plurality of logical gates. At least some of the one or more controllers can be combined into a single controller. In the embodiments described above, at least some of the power generating devices have a different maximum saturated output power than others of the power generating devices. Additionally, or alternatively, each power generating device may comprise a gallium nitride-based field-effect transistor, a laterally diffused metal oxide semiconductor transistor, or metal-oxide- semiconductor transistor. According to a second aspect, the present disclosure provides a base station for mobile telecommunications comprising the ^-way Doherty amplifier as defined above. Next, the present disclosure will be described in more detail by referring to the appended drawings in which identical or similar components are referred to using identical reference signs and wherein: Fig.1A illustrates a general three-way DPA with lossless power combining network, and Fig.1B illustrates the drain efficiency and normalized output power vs. normalized input voltage; wherein ports P1-P4 denote the four ports of the power combining network; Fig.2 illustrates a comparison of two different three-way DPAs: (a) classical DPA (b) novel DPA in terms of current, voltage, impedance profiles and output power combining networks for k1 = 0.50, k2 = 0.25 and RL = 0.5Ω; Fig.3A illustrates a general four-way DPA with lossless power combining network, Fig.3B illustrates the drain efficiency and normalized output power vs. normalized input voltage; wherein ports P1-P5 denote the five ports of the power combining network; Fig.4 illustrates voltage and current profiles across six different four-way DPA scenarios for k3 = 0.178, k2 = 0.356, and k1 =0.712, with high efficiency points at 15dB, 9dB, 3dB, and 0dB power back-off; Fig.5 illustrates selected power combining networks (in dark grey) for: (a) classical DPA (b) 2×2 DPA (c) 3+1 DPA (d) novel DPA using solely λ / 4 transmission lines; wherein ports P1-P5 denote the five ports of the power combining network shown in Fig.3; Fig.6 illustrates a schematic of different four-way DPAs: (a) Classical (b) 2×2 (c) 3+1 (d) Novel. The symbol c indicates the power combining point, with Rc representing its impedance; Fig.7 illustrates the drain efficiency and output power versus frequency with the same combining point impedance Rc = Ropt at different power back-off levels across different DPA topologies: (a) Classical (b) 2×2 (c) 3+1 (d) Novel; wherein the legend specifies the power backoff levels as BO3 (15 dB), BO2 (9 dB), BO1 (3 dB), and BO0 (0 dB). For all DPA configurations, a binomial two-section impedance transformer was used to match the combining point impedance to a 50 Ohm load; Fig.8 illustrates the drain efficiency and output power versus frequency of the 2×2 four- way DPA as a function of combining point impedance (a) Rc = 1.5Ropt (b) Rc = 2.0Ropt (c) Rc = 2.5Ropt (d) Rc = 3.0Ropt at different power back-off, ‘PBO’, levels; wherein the legend specifies the power backoff levels as BO3 (15 dB), BO2 (9 dB), BO1 (3 dB), and BO0 (0 dB). For all DPA configurations, a binomial two-section impedance transformer was used to match the combining point impedance to a 50 Ohm load; Fig.9 illustrates an embodiment of an 8-way DPA in accordance with the present disclosure; Fig.10 illustrates a first implementation of a 4-way DPA in accordance with the present disclosure; Fig.11 illustrates a second implementation of a 4-way DPA in accordance with the present disclosure; Fig.12 illustrates a third implementation of a 4-way DPA in accordance with the present disclosure; Fig.13 illustrates a fourth implementation of a 4-way DPA in accordance with the present disclosure and Fig.14 illustrates a digital implementation of a power amplifying device in accordance with the present disclosure. Next, a general approach for pioneering three-way DPAs will be described. It extends the methodology proposed in the paper “A mixed-signal approach towards linear and efficient N-way Doherty amplifiers”, by W. C. Neo et al, IEEE Transactions on Microwave Theory and Techniques, vol.55, no.5, pp.866–878, 2007, by introducing linearity requirements into current profile determination to better manage the increased design freedom and large variety of power combiner topologies when addressing ^-way DPAs. In the subsequent theoretical analysis of three-way DPAs, the following assumptions are adopted for simplicity: • In each branch amplifier, the output stage transistor is modeled as an ideal voltage- controlled current source with zero knee voltage, with all higher harmonic components short-circuited to ensure ideal class-B operation. • The fundamental current and voltage at the output of each branch amplifier are in phase to ensure energy-efficient power transfer to the output combing network. • The phase of the main amplifier (Main), denoted as (), is set as a reference and assumed to be 0. The phases of the first peaking amplifier (Peak1) and second peaking amplifier (Peak2), represented by (*+and (*,, are defined relative to the main amplifier. Unitvectors, = .^ / 0 with ^ representing 1^ and 12, are used to handle the phase informationeffectively. • The applied design procedure normalizes all power amplifier branches to operate at 1 V input voltage, and 1 V drain supply voltage with the total output power normalized to 1 W. Next, the drain voltages 3^,^are related to the corresponding drain currents ^^,^of the Doherty branch amplifiers through the 4-parameters of the intermediate network, which represents the Doherty output network including the external load, for all desired high-efficiency points 5, ^^, ^2. In this notation, the first subscript ^ refers to %, 1^or 12, corresponding to the main and two peaking devices, respectively, while the second subscripts ^ refers to 5, ^^or ^2, when the DPA is delivering maximum power and when the DPA is in power back-off by a factor of 6^2, 622, respectively, as shown in Fig.1(b). The operational region is segmented into three intervals: Interval I below ^2, Interval II between ^2and ^^, and Interval III between ^^and 5. Since the intermediate network is reciprocal, a generic three-way DPA can be described by the following system of equations: To optimize the efficiency at 5, and ^2, the peaking devices remain off below their respective back-off points and are only active beyond them. In addition, it is essential to maximize the voltage amplitude with respect to the DC supply voltage for all output stages that are active. Consequently, the following definitions can be made: Equations (1) yield nine sub-equations, in which the specific voltages and currents are “fixed” using the efficiency requirements defined by Equations (2) and (3). Subsequently, the three remaining unknown voltages 3*,,7+, 3*,,7,and the six unknown 4-parameters 4^^, 4^2, 4^8, 422, 428, 488can be expressed in terms of the current variables ^),9, ^),7+, ^),7,, ^*+,9, ^*,,7+and phase variables -*+, -*,. The resulting 3*,,7+are given below. They will be utilized to calculate the output power of the DPA at the mid-interval points which will be introduced next. The maximum output power delivered by the DPA in the normalized scenario ^:; = 1,under the assumption of in-phase output stage current and voltage, e.g.3),9and ^),9for the main output stage, can be described as a function of current variables When the DPA operates at one of the back-off levels, the output power has a fixed ratio to the full power: The power relations at the three points 5, ^^and ^2alone are, however, insufficient to ensure that the output power changes linearly with the input power or with the square of the inputvoltage as depicted in Fig. 1(b), following the relation 1<=> ∝ 32^^ . In fact, it can be shown thatthere are multiple solutions that meet the interval boundary conditions at the points 5, ^^and ^2in terms of output power but do not provide the desired consistent linearity. These solutions exhibit discontinuous derivatives of 1<=>with respect to 3^^at high efficiency points in the provided nonlinear DPA examples. To ensure a consistent linear relationship between 1<=>and 3^2^ in across the entire input range while avoiding unnecessarily mathematical complexity, two extra equations describing power relations at the midpoint @^of Interval III and the midpoint @2of Interval II are introduced. At these midpoints, the output current and voltage of each branch amplifier are the average of their respective start and end values, assuming a linear variation in the branch amplifier’s output current with 3^^within the interval. Consequently: Substituting equations (4) and (5) into (9) and (10) eliminates 3*,,7+and 3*+,7,. This allows the power relation at @^and @2to be expressed exclusively in terms of the current variables, similarly to the expressions at the points 5, ^^and ^2. With the power relations at five points ^2, @2, ^^, @^, 5, the six unknown current variables need to be solved for. The presence of the phase-related unit vectors in the denominatorsnecessitates the fulfillment of the conditions -2 2*+ = −1 and -*, = 1 for the expression to be valid.Under these constraints, the solution for current variables can be simplified, with ^),9representing the remaining design freedom in the context of a three-way DPA. Clearly, there are two relevant options in selecting ^),9. Either the main current reaches itsmaximum value at ^^, i.e. ^),9 = ^),7+, or the main current reaches its maximum value at 5, i.e.^),9 = ^),7+ / 6^, leading to the two known current profiles, namely the classical and the novelthree-way DPA, as illustrated in Fig.2. According to the present disclosure, a new insight obtained in that by introducing the mid- interval power requirement, as imposed by equations (9) and (10), allows the selection of more promising ^-way DPA current-profile solutions. As such, nonlinear input-output transfers can be avoided, which would demand additional digital predistortion signal processing correction. This insight is essential when evaluating higher-order ^-way Doherty configurations that offer an extensive range of possible current profiles. Next, the previously proposed approach will be extended from three-way DPAs to four- way DPAs, while further refining its procedure to better handle the steep increase in design freedom and related DPA network options. Again, the resistive load is adsorbed into the combiner, reducing the five-port lossless power combining network into a lossy four-port intermediate network, as shown in Fig.3(a). Similar to the three-way study, the reciprocal property of the intermediate network is used, yielding the general four-way Doherty system of equations. In the voltage 3^,^and current ^^,^, now the first subscript ^ refers to % and 1^, 12, 18corresponding to the main and three peaking devices, while the second subscript ^ refers to 5, ^2, ^8when the DPA is delivering full power and when the DPA is in back-off by a factor of 6^2, 622, and 682, respectively. Furthermore, unit vectors-^ = with ^ denoting 1^, 12, 18 are introduced to handle their phase information relative to themain amplifier. Similar to the three-way DPA case, the following boundary conditions are enforced to ensure high efficiency at full power and the three back-off points. Equations (16) yields sixteen sub-equations, in which the specific voltages and currents are “fixed” using the efficiency requirements defined by Equations (17) and (18). Similar to the three- way DPA case, the six remaining unknown voltages and the ten unknown 4-parameters can be expressed in terms of the current variables and phase variables. The maximum output power delivered by a four-way DPA in the normalized scenario^:; = 1 under the assumption of in-phase current and voltage at the ports of the PA branches canbe represented as follows: When the DPA operates at power back-off levels, the following applies: Moreover, to ensure that the output power changes perfectly with the square of the normalized input voltage, as depicted in Fig.3(b), three extra equations can be enforced describing power relations at the midpoint of Interval IV, the midpoint @2of Interval III, and the midpoint @8of Interval II, respectively: The highlighted voltage variables in bold can be substituted with current variables and phase vectors. Hence, the power relation at @2, and @8can be expressed similarly to the points ^8, ^2, and 5 with only current variables and phase vectors utilized in the expressions. Solving Equations (16) - (25), the so far unknown current variables can be expressed for a set of specified back-off levels. Such a solution is valid when the phases satisfy the conditions-*2+ = −1, -*2, = −1, and -*2B = −1, enabling the following simplified representation: The next step is to determine the remaining variables ^),9, ^),7+, and ^*+,7+, which represent the design freedom in defining the overall current profiles. They can be selected for which input levels the main and the first peaking amplifier are supposed to reach their maximum currents. There are two logical options for the first peaking amplifier. It can achieve its maximum current either at ^^or 5. The main amplifier offers a broader range of options, as it can achieve its maximum current at three distinct points: ^2, ^^or 5. When these findings are combined, it works out that for a four-way DPA design there are six current profiles that meet the previously set boundary conditions for efficiency and linearity. Fig.4 presents the six current profiles and their respective voltage profiles for power back-off levels: 68 = 0.178 → −15 dB, 62 = 0.356 → −9 dB, and 6^ = 0.712 → −3 dB. Among the six scenarios, the four most viable combinations have been identified, while the remaining two suffer from nonmonotonic current profiles other than saturation, complicating their implementation and making them less attractive. Hence, the four remaining four-way DPA solutions will hereinafter be focused on. Next, the network synthesis of the power combining networks for the four previously identified four-way DPA current profiles will be discussed. First, appropriate phase relationships between the main and peaking devices should be selected to allow the 4-parameters of the four- port intermediate network, denoted as[ ]IJ, to be expressed uniquely in terms of the currents and voltages. Next, the K-parameters can be obtained through -to-K conversion, which paves the way for the conversion of the lossy four-port intermediate network into a lossless five-port power combining network. Only the fifth port, which is connected to the load as depicted in Fig.3(a), needs to be reintroduced, while the other K -parameters remain identical to those of the intermediate four-port network. Considering the reciprocity condition, this step introduces five new variables KL^, KL2, KL8, KLI, and KLL, which can be found by imposing the well-known lossless ^- port K-parameter conditions: Here, ^ represents the number of ports of the power combining network, excluding the load port. With a total of 10 unknowns, wherein the K-parameters are typically complex, and 10 equations, the remaining K-parameters that are related to the fifth port P5 (see Fig.3(a)) can be determined. Due to the complexity of Equations (33) and (34), numerical techniques are best employed to solve for the K-matrix of the power combining network. For this study, the load impedance is set according to: 0.5Ω and three back-off points 68, 62, and 6^at 0.178, 0.356, and 0.712, yielding high efficiency points at power back-off levels of 15 dB, 9 dB, and 3 dB, respectively, in addition to the full power level. Subsequently, the power combining network’s K-matrix is converted to its R-matrix, wherein the R-matrix is denoted as[R]LJ, while the corresponding -matrix is denoted as[ ]LJ. The R-matrix is preferred since it is more straightforward for network synthesis, but if it does not exist, the -matrix may serve as an alternative. The solution for the power combiningnetwork may not be unique due to the design freedom provided by S = ∠UL^. However, theoptimal phase of UL^can be established based on two conditions. First, all elements of [R]LJor [ ]LJmust be zero or purely imaginary. Second, to attain a simplified combiner network with minimal V / 4 transmission lines, it is crucial to maximize the number of zero elements in [R]LJor [ ]LJ. Once [R]LJor [[ ]LJis determined, the general four- way Doherty power combiner topology described in the paper “A Wideband Four-Way Doherty Bits-In RF-Out CMOS Transmitter”, by M. Beikmirza et al, IEEE Journal of Solid-State Circuits, vol.56, no.12, pp.3768–3783, 122021, is used for network synthesis. In this manner, four different topologies can be obtained, which will be described next. 1. Classical Four-way DPA This DPA design corresponds to the scenario in Fig. 4(a), where the main amplifier reaches its maximum current at ^2and peak1 amplifier reaches its maximum current at ^^. Assuming-*+ = −^, -*, = −1, -*B = ^, the [R]LJ matrix can be written as The resulting[R]LJmatrix shows purely imaginary off-diagonal elements, including (X^2, X2^), (X28, X82), (X8I, XI8), and (XIL, XLI), while all other parameters remain at zero. A zero X^^implies no mutual connection between port ^ and port ^ via the V / 4 transmission line, while a purely imaginary X^^suggests a mutual connection between port ^ and port ^ via theV / 4 transmission line, with its characteristic impedance given by Thus, thiscombiner network can be synthesized using exclusively V / 4 transmission lines as highlightedin Fig. 5(a). In this design example, ^ = 7.7 Ω, 2 = 2.0 Ω, 8 = 0.7 Ω, I = 0.5 Ω. The derivedpower combining network precisely corresponds to the classical four-way DPA, validating the present design methodology. 2) 2×2 Four-way DPA This DPA design corresponds to the scenario in Fig.4(b), where the main amplifier reaches its maximum current at ^2and peak1 amplifier reaches its maximum current at 5.Assuming -*+ = −^, -*, = 1, -*B = −^, the [R]LJ matrix can be written as The resulting [R]LJmatrix shows purely imaginary off-diagonal elements, including (X^2, X2^), (X2L, XL2), (X8I, XI8), and (XIL, XLI), while all other parameters remain at zero. Thus we can synthesize this combiner network using exclusively V / 4 transmission lines as highlightedin Fig. 5(b). In this design example, = 7.7 Ω, 2 = 1.4 Ω, 8 = 1.1 Ω, I = 0.8 Ω. Thisarchitecture will hereinafter be referred to as the 2×2 four-way DPA as it can be considered as two two-way Doherty in parallel. Also visible in Fig.4(b) is that the peak1 amplifier switches on at ^8when the main amplifier reaches voltage saturation, the peak2 amplifier switches on at ^2when the peak1 amplifier reaches voltage saturation, and the peak3 amplifier switches on at ^^when the peak2 amplifier reaches voltage saturation. 3) 3+1 Four-way DPA This DPA design corresponds to the scenario in Fig.4(e), where the main amplifier reaches its maximum current at 5 and peak1 amplifier reaches its maximum current at ^^. Assuming -*+=^, -*, = 1, -*B = −^, the [R]LJ matrix can be written as The resulting[R]LJmatrix shows purely imaginary off-diagonal elements, including (X^I, XI^), (X28, X82), (X8I, XI8), and (XIL, XLI), while all other parameters remain at zero. Thus, this combiner network can be synthesized using exclusively V / 4 transmission lines as highlighted in Fig.5(c). In this design example, ^ = 2.8 Ω, 2 = 2.6 Ω, 8 = 0.9 Ω, I = 0.5 Ω. Theabovementioned four-way DPA architecture has not been reported before. As such, it is referred to as a 3+1 four-way DPA as it can be considered as a novel three-way DPA extended with an extra peaking device. 4) Novel Four-way DPA This DPA design corresponds to the scenario in Fig. 4(f), where both the main and peak1 amplifiers achieve their maximum currents at 5. Since the [[R]LJmatrix of the power combiningnetwork does not exist, the [ ]LJ matrix is used instead. Assuming -*+ = ^, -*, = 1, -*B = ^, the[ ]LJmatrix can be written as: The resulting [ ]LJmatrix shows symmetric imaginary elements including (4^2,42^), (428, 482), (48I, 4I8), and (4IL, 4LI), with all other parameters being zero. Unlike X-parameters, the construction of the power combining network based on 4-parameters is less straightforward. It is noted that a V / 4 line connecting two ports results in a negative imaginary component (e.g.4^I), whereas a 3V / 4 line yields a positive imaginary component (e.g.4^2). This insight allows effectively reconstructing the power combining network using 4-parameters as highlighted in Fig.5(d). There is a dependent relationship between^,2,8,IandL. Once2is selected,the other impedance parameters can be uniquely determined. In this design example, ^ = 2.8 Ω,2 = 1.7 Ω, 8 = 0.6 Ω, I = 1.5 Ω, L = 0.9 Ω.The power combining network derived from its 4-matrix precisely matches the previously reported novel four-way DPA, further validating the present design methodology. Fig.6 gives the different four-way DPA topologies based on the power combining network depicted in Fig.5. In the classical (Fig.6(a)) and the 3+1 designs (Fig.6(c)), the combining point C is directly connected to the peak3 amplifier, thus fixing the combining point impedance RC. Conversely, the 2×2 (Fig.6(b)) and novel designs (Fig.6(d)) allow for a flexible choice of the combining point impedance ^\. Next, the abovementioned DPA theory is expanded by providing a generalized relationship for output combiner elements (before the combining point C), as outlined in Table I,with the normalized resistance ^ 2<*> = ^]\ / (2N)OP).

[0002] This greatly enhances design flexibility across different specifications, including power back-off levels, output power, and drain supply voltage, ultimately facilitating subsequent bandwidth analysis. Additionally, VSWR is introduced to indicate the amount of load modulation of the mainamplifier. Since 62 ≪ 1, the classical and 2×2 designs share the same lower VSWR, while the 3+1and novel designs have a higher, identical VSWR. So far, the operation principles of different four-way DPAs have been discussed at the center frequency. However, when the frequency deviates from the center frequency, both the efficiency and output power will degrade, which is undesirable. The frequency behavior of different four-way DPAs have been investigated to identify the optimal wideband design. The four-way DPA configurations under evaluation are depicted in Fig.6. LDMOS / GaN technologies optimized for a 28V supply voltage (Vdc) were focused on, which are interesting for massive multiple-input-multiple-output (mMIMO) systems. By choosing a center frequency of 1 GHz and a maximum TX output power level (Pmax) of 80 W, the designs are compatible with available commercial GaN devices. The previously chosen power backoff points: 68= 0.178 → −15 dB, 62= 0.356 → −9 dB, and 6^= 0.712 → −3 dB have been used. Moreover, the following assumptions have been applied for all four variations of the four-way DPA: 1) Ideal class-B terminations for all DPA output stages, regardless of the operating frequency; 2) Perfect phase tracking between main and peaking devices across frequency to match the delays in the output power combiner.; 3) After the combing point C, an impedance transformer is employed to match ^\to the 50Ω load. 4) As a last point, an extra bandwidth limitation is added. Consider the classical four-way DPA illustrated in Fig. 6(a), the combining point impedance is determined by ^; = ^<*> =^2]\ / (2N)OP) = 4.9_, yielding a transformation ratio of 50 / 4.9 = 10.2. A single-section quarter-wave transformer is too narrowband, necessitating the use of a high-order impedance transformer. Hence, a two-section binomial transformer is utilized for the following evaluation, where the four-way DPA wideband performance is evaluated in terms of drain efficiency and RF output power over the 0.7-1.3 GHz frequency range across various power back-off levels. In Fig.7, the simulated output power and efficiency are depicted across various DPAtopologies with the same combining load impedance ^; = ^<*>. The results reveal that theclassical and 2×2 designs, with a smaller load modulation factor (62 / 68 = 2.0), outperform thenovel and 3+1 designs, which have a larger load modulation factor (1 / 68 = 5.6). Furthermore,the 2×2 design exhibits a more consistent response versus frequency across diverse back-off levels relative to the classical design. Next, the 2 × 2 design is evaluated in more detail due to its superior wideband capability with a simple power combiner. Fig.8 presents a comparative study of the 2 × 2 design with combining point impedance ^;ranging from 1.5^<*>to 3.0^<*>. Notably, the 2 × 2 design with a larger combining point impedance shows comparable or even better wideband behavior compared to the classical design in Fig.7(a). However, when the combining point impedance exceeds 2.5^<*>, the efficiency at 15 dB PBO (BO3) starts to be limited. Another notable advantage of a larger combining point impedance in the 2 × 2 design, is the minimized impedance variation (δ). This occurs because as the combining point impedance increases, 2 andIincrease while^and8remain constant. Clearly, a smaller value of impedance variation helps easing the practical implementation. As discussed above, the 2x2 design offers superior performance compared to the other four-way DPA topologies. In the 2x2 design, a carrier amplifier and a first peak amplifier are arranged in a first branch, and a second and third peak amplifier are arranged in a second branch. During operation, and as a function of the input power, the peak amplifiers switch on with increasing input power in the order, first peak amplifier, second peak amplifier, and third peak amplifier. The Applicant has found that the 2x2 design can be generalized to an ^-way Doherty amplifier with while still maintaining substantially the same advantages as the 2x2 design. This generalization is based on the following assumptions: 1) The ^-way Doherty amplifier comprises ^ parallel amplifier branches ^^^; 2) each ^thamplifier branch ^^^comprises ^^nodes ^^^,^, ^^power generating devices ^^,^, and ^^impedance inverters ^^^^,^3) ^ is an index in a range [1, ^], and for each value of ^, ^ is an index in a range[1, ^^];4) for ^>1 ^^is an even integer equal to or greater than 2, wherein ^^is an integer equal to or greater than 2, and wherein: 5) an output of each power generating device ^^,^is connected to the node ^^^,^; 6) for each value of index ^ and for each value of index ^ ≠ ^^, impedance inverter^^^^,^is arranged in between the node ^^^,^and the node ^^^,^^^; 7) for each value of index ^ and for each value of index ^ = impedance inverter^^^^,^is arranged in between the node ^^^,^and a common combining node C that is electrically connected to an output of the ^-way Doherty amplifier; 8) the power generating device ^^,^forms a carrier amplifier, and each power generating device different from power generating device ^^,^forms a peaking amplifier; 9) each power generating device ^^,^is associated with a respective switching order ^^,^given by: wherein ^^ = 0;10) the switching orders ^^,^describe the order in which the corresponding power generating devices switch on when ramping up the power outputted by the ^-way Doherty amplifier starting with the power generating device ^^,^. In an embodiment, the power generating device associated with a switching order equal to is configured to switch on when the power generating device associated with the switching orderequal to − 1 reaches voltage saturation, wherein is an integer in a range [2, ^].Fig.9 presents a first embodiment of an eight-way Doherty in accordance with the new topology that was generalized from the 2 x 2 design. This embodiment has three branches ^^^, ^^2, ^^8. The number of power amplifying devices in these branches equals 4, 2, and 2, respectively. The output of each power amplifying device ^^,^is connected to a respective node ^^^,^. The signals from the different branches are collected at combining node C. Between each pair of power amplifying devices in a given branch, and between the last power amplifying device in a branch and combining node C, a respective impedance inverter ^^^^,^is arranged. Power amplifying devices ^^,^may each comprise a GaN-based field-effect transistor, or a Si-based laterally diffused metal-oxide-semiconductor, LDMOS, transistor. Other semiconductor technologies such bipolar or complementary metal-oxide-semiconductor, CMOS, technologies are not excluded. For analog operation, the main amplifier ^^,^is biased in class AB or class B and the other peaking amplifiers in class C. Combining node C is connected to an output of the DPA, either directly or through one or more impedance matching stages. The order in which the peaking amplifiers switch on with increasing input power is determined in accordance with: For the embodiment in figure 10, this means that the amplifiers in branch ^^^switch on starting from the left, then the amplifiers in branch ^^2, also starting from the left, and then the amplifiers in branch ^^8, also starting from the left. A peaking amplifier will switch on when the previous peaking amplifier has reached voltage saturation. In Fig.9, impedance inverters ^^^^,^can be realized using quarter wavelength transmission lines. In Fig.10, impedance inverters ^^^^,^are realized using C-L-C lumped equivalents of transmission lines. Fig.10 illustrates an example of a four-way DPA in accordance with the 2 x 2 design. The lumped equivalent circuits are based on C-L-C equivalent circuits, wherein the shunt capacitors are at least partially formed using the parasitic output capacitances of the power amplifying devices and wherein the series inductors are either bond-wires or lumped integrated inductors such as spiral inductors. In case the parasitic output capacitance is too low, extra capacitance can be connected to the output of the relevant power amplifying device. In case the parasitic output capacitance is too high, a shunt inductor can be connected to the output of the relevant power amplifying device for partially compensating the output capacitance. Such inductor is typically connected to ground through a DC blocking capacitor. In detail, a first impedance inverter is formed between ^^,^and ^^,2using output capacitance Cd1, part of the combination of output capacitance Cd2 and added capacitance Cadd1, and series inductor L1. A second impedance inverter is formed between ^^,2and combining node C using the remaining part of the combination of output capacitance Cd2 and added capacitance Cadd1, series inductor L2, and part of capacitance Ctot. A third impedance inverter is formed between ^2,^and ^2,2using output capacitance Cd3, part of the combination of output capacitance Cd4 and added capacitance Cadd2, and series inductor L3. A fourth impedance inverter is formed between ^2,2and combining node C using the remaining part of the combination of output capacitance Cd4 and added capacitance Cadd2, series inductor L4, and the remaining part of capacitance Ctot. In Fig.11, impedance inverters ^^^^,^are realized using L-C-L lumped equivalents of the transmission lines in Fig.9. Fig.11 illustrates an example of a four-way DPA in accordance with the 2 x 2 design. The lumped equivalent circuits are based on L-C-L equivalent circuits, wherein the shunt inductors are either bond-wires or lumped integrated inductors such as spiral inductors. In detail, a first impedance inverter is formed between ^^,^and ^^,2using shunt inductor L1, series capacitance C1, and part of shunt inductor L2. A second impedance inverter is formed between ^^,2and combining node C using the remaining part of shunt inductor L2, series capacitor C2, and part of shunt inductor Ltot. A third impedance inverter is formed between ^2,^and ^2,2using shunt inductor L3, series capacitance C3, and part of shunt inductor L4. A fourth impedance inverter is formed between ^2,2and combining node C using the remaining part of shunt inductor L4, series capacitor C4, and the remaining part of shunt inductor Ltot. It should be noted that for the determination of the shunt inductors L1-L4, the effect of the parasitic output capacitances Cd1-Cd4 should be taken into account. Furthermore, shunt inductors L1-L4, and optionally Ltot, are typically connected to ground through a DC blocking capacitor. Fig.12 illustrates an example of a four-way DPA in accordance with the 2 x 2 design. The lumped equivalent circuits are based on a combination of the C-L-C and L-C-L equivalent circuits shown in Fig.10 and Fig 11. In detail, a first impedance inverter is formed between ^^,^and ^^,2using output capacitance Cd1, output capacitance Cd2, and series inductor L1. A second impedance inverter is formed between ^^,2and combining node C using shunt inductor L2, series capacitor C2, and part of shunt inductor Ltot. A third impedance inverter is formed between ^2,^and ^2,2using output capacitance Cd3, output capacitance Cd4, and series inductor L3. A fourth impedance inverter is formed between ^2,2and combining node C using shunt inductor L4, series capacitor C4, and the remaining part of shunt inductor Ltot. Each shunt inductor L2, L4 should be designed such that the combination of the shunt inductance required for the L-C-L equivalent circuit and the shunt capacitance required for the C- L-C equivalent circuit corresponds to the combined reactance of Cd2, Cd4 and L2, L4, respectively. The DPAs of figures 9-12 can be fully integrated, in which case the power amplifying devices are realized on one or more semiconductor dies, and wherein the required inductors and capacitors are realized on the one or more semiconductor dies. In other embodiments, a hybrid approach is followed in which the power amplifying devices are realized on one or more semiconductor dies that are mounted on a printed circuit board, wherein optionally some or all inductors are arranged on the printed circuit board, either as SMD component or as transmission line, and wherein optionally some or all capacitors, other than the parasitic output capacitances, are arranged on the printed circuit board as SMD component. For example, Fig.13 illustrates a further embodiment of the four-way DPA in accordance with the 2 x 2 design. In this embodiment, a Silicon LDMOS die 100 comprising a main amplifier and three peaking amplifiers, is arranged on a printed circuit board 110. Each of the amplifiers comprises a bond pad 101 connected at its respective output. The output capacitance of the main amplifier and the output capacitance of the first peaking amplifier form, together with a series inductance realized using bond wires BW1, a C-L-C equivalent circuit for a quarter wavelength transmission line. Similarly, the output capacitance of the second peaking amplifier and the output capacitance of the third peaking amplifier form, together with a series inductance realized using bond wires BW3, a C-L-C equivalent circuit for a quarter wavelength transmission line. The first peaking amplifier is coupled, using bond wires BW2, to a first quarter wavelength transmission line 111A arranged on the printed circuit board 110. Similarly, the third peaking amplifier is coupled, using bond wires BW4, to a second quarter wavelength transmission line 111B arranged on the printed circuit board 110. Transmission lines 111A, 111B join at the combining node C. As discussed above in connection with figures 9-13, if the output capacitance of a power amplifying device is too large or small, it can be tuned by connecting a shunt inductor or shunt capacitor to the output of that amplifying device. The DPAs of figures 9-13 represent an analog solution. Fig.14 illustrates a digital solution for implementing one or more of the power generating devices in which each power generating device comprises multiple transistor segments T1-Tn that are arranged in parallel, that are optionally equal in size, and that can each be separately controlled using a respective bit b1-bn of a digital control word that is provided to the power generating device from a controller 10. In Fig. 14, an example of a polar controller 10 is given, in which all the segments T1-Tn use the same activation phase that is provided by a local oscillator LO or phase modulator / mapper. The number of activated segments T1-Tx (with x being an integer number between 0 and n) sets the RF output current / power of power generating device ^^,^. The desired current drive profiles, for example as given in Fig.4b., with different activation levels and slopes for power generating device ^^,^can be as such entirely controlled from the digital domain offering superior accuracy and performance. Logically, variations on how the controller activates the transistor segments are possible. E.g. when targeting the handling of wideband modulated signals, Cartesian or multiphase DTX schemes can be attractive. It should be noted that these later schemes make use of multiple activation phases or LO / clock signals. Also, other digital schemes for controlling the segments T1-Tn are possible in combination with the embodiments of the present disclosure. In addition to the pure analog and digital implementations of invention above, also configurations of the proposed invention are possible in which power generating devices ^^,^operate in the analog domain, but the optimum analog signals (^, ^) to drive power generatingdevices ^^,^are obtained using multiple digital-to-analog, ‘DAC’, converters. Such a mixed-signal solution can also provide accurate drive profiles for the drive power generating devices ^^,^to obtain their desired current profile, while avoiding the need for a segmented RF power device technology. In the above, embodiments of the present disclosure have been described in detail. However, the present disclosure is not limited to these embodiments. Rather, various modifications to these embodiments are possible without deviating from the scope of the present disclosure, which is defined by the appended claims and their equivalents.

Claims

CLAIMS 1. An ^-way Doherty amplifier comprising ^ parallel amplifier branches ^^^, each ^thamplifier branch ^^^comprising ^^nodes ^^^,^, ^^power generating devices ^^,^, and ^^impedance inverters ^^^^,^, wherein ^ is an index in a range [1, ^], and wherein for each value of ^,^ is an index in a range [1, ^^], wherein for ^ > 1 ^^ is an even integer equal to or greater than 2,wherein is an integer equal to or greater than 2, and wherein:wherein an output of each power generating device ^^,^is connected to the node ^^^,^; wherein for each value of index ^ and for each value of index ^ ≠ ^^, impedance inverter^^^^,^is arranged in between the node ^^^,^and the node ^^^,^^^; wherein for each value of index ^ and for each value of index ^ =impedance inverter^^^^,^is arranged in between the node ^^^,^and a common combining node C that is electrically connected to an output of the ^-way Doherty amplifier; wherein the power generating device ^^,^forms a carrier amplifier, and wherein each power generating device ^^,^different from power generating device ^^,^forms a peaking amplifier; wherein each power generating device ^^,^is associated with a respective switching order ^^,^given by:wherein ^^ = 0, the switching orders ^^,^ describing the order in which the corresponding powergenerating devices ^^,^switch on when ramping up the power outputted by the ^-way Doherty amplifier starting with the power generating device ^^,^.

2. The ^-way Doherty amplifier according to claim 1, wherein the power generating device associated with a switching order equal to is configured to switch on when the powergenerating device associated with the switching order equal to − 1 reaches voltage saturation,wherein is an integer in a range [2, ^].

3. The ^-way Doherty amplifier according to any of the previous claims, wherein anelectrical length between each of the nodes ^^^,^ for which ^ =is equal or close to # times 180degrees at an operational frequency of the ^-way Doherty amplifier, wherein n is an integer.

4. The ^-way Doherty amplifier according to any of the previous claims, wherein atleast one of the impedance inverters ^^^^,^ for which ^ ≠ ^^ comprises a transmission line of whichan electrical length is equal or close to (2% + 1) times 90 degrees at an operational frequency ofthe ^-way Doherty amplifier, wherein % is an integer.

5. The ^-way Doherty amplifier according to any of the previous claims, wherein at least one of the impedance inverters ^^^^,^is formed using a lumped equivalent of a transmissionline that has an electrical length that is equal or close to (2% + 1) times 90 degrees at anoperational frequency of the ^-way Doherty amplifier, wherein m is an integer.

6. The ^-way Doherty amplifier according to claim 5, wherein at least one equivalent impedance inverter incorporates an output capacitance of at least one power generating device.

7. The ^-way Doherty amplifier according to claim 5 or 6, wherein at least one equivalent impedance inverter comprises a C-L-C or L-C-L lumped equivalent circuit.

8. The ^-way Doherty amplifier according to claim 7, wherein an equivalentimpedance inverter corresponding to impedance inverter ^^^^,^ for which ^ ≠comprises a C-L-C lumped equivalent circuit that is formed using an output capacitance of the power generating device ^^,^, an output capacitance of the power generating device ^^,^^^, and a series inductor arranged in between the outputs of power generating device ^^,^and power generating device ^^,^^^.

9. The ^-way Doherty amplifier according to claim 7 or 8, wherein an equivalentimpedance inverter corresponding to impedance inverter ^^^^,^ for which ^ =comprises a C-L-C lumped equivalent circuit that is formed using an output capacitance of the power generating devices ^^,^, a shunt capacitance connected at the combining node, and a series inductor arranged in between the output of the power generating device ^^,^and the combining node C.

10. The ^-way Doherty amplifier according to any of the claims 7-9, wherein the series inductor comprises one or more bond-wires.

11. The ^-way Doherty amplifier according to any of the claims 7-10, further comprising, for an equivalent impedance inverter corresponding to the impedance inverter ^^^^,^, a shunt inductor connected to the output of the power generating device ^^,^, and / or a shunt inductorconnected to the output of power generating deviceprovided that ^ <for partiallycompensating the output capacitance of power generating device ^^,^or the output capacitance of power generating device ^^,^^^, respectively.

12. The ^-way Doherty amplifier according to claim 7, wherein an equivalentimpedance inverter corresponding to impedance inverter ^^^^,^ for which ^ ≠comprises a L-C-L lumped equivalent circuit that is formed using a first shunt inductor connected to the output of the power generating device ^^,^, a second shunt inductor connected to the output of the power generating device ^^,^^^, and a series capacitor arranged in between the outputs of power generating device ^^,^and power generating device ^^,^^^.

13. The ^-way Doherty amplifier according to claim 7 or 12, wherein an equivalentimpedance inverter corresponding to impedance inverter ^^^^,^ for which for which ^ =comprises a L-C-L lumped equivalent circuit that is formed using a first shunt inductor connected to the output of the power generating device ^^,^, a second shunt inductor connected to the combining node, and a series capacitor arranged in between the output of the power generating device ^^,^and the combining node C.

14. The ^-way Doherty amplifier according to any of the previous claims, wherein the ^-way Doherty amplifier is configured for amplifying an input analog RF signal, wherein each power generating device ^^,^is separately biased to achieve the switching order with increasing power level of the input analog RF signal.

15. The ^-way Doherty amplifier according to claim 14, further comprising a Doherty splitter for splitting the input analog RF signal into respective parts, wherein each part is provided to a respective power generating device ^^,^, wherein the impedance inverters ^^^^,^and the Doherty splitter are configured for ensuring that signals amplified by the power generating devices ^^,^add up in-phase at the combining node.

16. The ^-way Doherty amplifier according to any of the previous claims, wherein one or more power generating devicesare configured for transforming a digital control word into an analog signal emerging at its or their outputs, the ^-way Doherty amplifier comprising one or more controllers (10) corresponding to the one or more power generating devices ^^,^, each controller (10) being configured for generating, for the corresponding power generating device ^^,^, a digital control word.

17. The ^-way Doherty amplifier according to claim 16, wherein the order by which the one or more power generating devices ^^,^are switched on with an increasing level of power outputted by the ^-way Doherty amplifier is controlled by the one or more controllers (10).

18. The ^-way Doherty amplifier according to claim 16 or 17, wherein each power generating device ^^,^comprises multiple transistor segments (T1-Tn) that are arranged in parallel and that can each be separately controlled using a respective bit (b1-bn) of the digital control word that is provided to that power generating device ^^,^.

19. The ^-way Doherty amplifier according to any of the claims 16-18, wherein each controller (10) comprises an input for receiving digital input data (Din), a processing unit (12) configured for generating the bits (b1-bn) of the digital control word for the corresponding power generating devicebased on the digital input data (Din), and a modulation unit comprising a plurality of logical gates (11), wherein the modulation unit is configured to modulate the bits (b1- bn) of the digital control word using one or more local oscillator or clock activation signals and the plurality of logical gates (11).

20. The ^-way Doherty amplifier according to any of the previous claims 16-19, wherein at least some of the one or more controllers (10) are combined into a single controller.

21. The ^-way Doherty amplifier according to any of the previous claims, wherein at least some of the power generating devices have a different maximum saturated output power than others of the power generating devices.

22. The ^-way Doherty amplifier according to any of the previous claims, wherein each power generating device comprises a gallium nitride-based field-effect transistor, a laterally diffused metal oxide semiconductor transistor, or metal-oxide-semiconductor transistor.

23. A base station for mobile telecommunications comprising the ^-way Doherty amplifier as defined in any of the previous claims.

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