Method for fabricating semiconductor device

Abstract

Provided is a semiconductor device that allows for miniaturization and a high level of integration. In this semiconductor device, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer are laminated, in that order. The third insulating layer, the second conductive layer, and the second insulating layer have an opening reaching the first conductive layer. A semiconductor layer has a portion covering each of an upper surface of the first conductive layer, a lateral surface of the opening in the second insulating layer, a lateral surface of the opening in the second conductive layer, and a lateral surface of the opening in the third insulating layer. The semiconductor layer is processed using, as a mask, a first layer formed so as to fill in the opening. The height of the upper surface of the first layer is lower than the height of the upper surface of the third insulating layer.

Description

Method for manufacturing a semiconductor device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories (storage devices), etc. A CPU is an aggregate of semiconductor elements that have integrated circuits (including transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Integrated circuits (ICs) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, metal oxides have also attracted attention as other materials.

[0007] Furthermore, it is known that transistors using metal oxides have extremely low leakage current in an off state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the low leakage current characteristic of transistors using metal oxides. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored content for a long period of time by utilizing the low leakage current characteristic of transistors using metal oxides.

[0008] In recent years, with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using a metal oxide film and a second transistor using a metal oxide film to provide multiple overlapping memory cells. Patent Document 4 also discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using a metal oxide film. Non-Patent Document 2 also discloses a vertically structured transistor.

[0009] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0010] M. Oota et al. , “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53X. Duan et. al, “Novel Vertical Channel-All-Around (CAA) IGZO FETs for 2T0C DRAM with High Density beyond 4F2 by Monolithic Stacking”, IEDM Tech. Dig. , 2021, pp. 222-225 Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0011] An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with favorable electrical characteristics.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current.An object of one embodiment of the present invention is to provide a semiconductor device including a transistor with low parasitic capacitance.An object of one embodiment of the present invention is to provide a novel semiconductor device.An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device having the above characteristics.

[0012] An object of one embodiment of the present invention is to manufacture a semiconductor device with a high yield.An object of one embodiment of the present invention is to reduce the number of manufacturing steps of a semiconductor device.An object of one embodiment of the present invention is to reduce the manufacturing cost of a semiconductor device.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0014] One embodiment of the present invention includes forming a first conductive layer on a first insulating layer, forming a second insulating layer on the first insulating layer and the first conductive layer, forming a second conductive layer on the second insulating layer so as to have a portion overlapping with the first conductive layer, forming a third insulating layer on the second insulating layer and the second conductive layer, forming a first mask on the third insulating layer, forming an opening that reaches the first conductive layer in the third insulating layer, the second conductive layer, and the second insulating layer, and forming a first mask on a top surface of the first conductive layer, a side surface of the opening in the second insulating layer, and a side surface of the opening in the second conductive layer. a semiconductor layer covering a surface of the semiconductor layer and a side surface of an opening in the third insulating layer; a first layer formed on the semiconductor layer to fill the opening; a portion of the first layer removed so that the height of the top surface of the first layer is lower than the height of the top surface of the third insulating layer; the first layer used as a second mask; a portion of the semiconductor layer higher than the height of the top surface of the first layer removed; the first layer removed; a fourth insulating layer formed in the opening to cover the semiconductor layer; and a third conductive layer formed on the fourth insulating layer.

[0015] In the above aspect, when removing the semiconductor layer using the first layer as the second mask, it is preferable that the removal be performed so that the height of the upper end of the semiconductor layer is lower than the height of the upper surface of the third insulating layer and higher than the height of the upper surface of the second conductive layer.

[0016] Alternatively, one embodiment of the present invention includes forming a first conductive layer over a first insulating layer, forming a second insulating layer over the first insulating layer and the first conductive layer, forming a second conductive layer over the second insulating layer to have a portion overlapping with the first conductive layer, forming a sacrificial layer over the second conductive layer, forming a third insulating layer over the second insulating layer and the sacrificial layer, forming a first mask over the third insulating layer, forming an opening that reaches the first conductive layer in the third insulating layer, the sacrificial layer, the second conductive layer, and the second insulating layer, and removing the sacrificial layer to form a gap sandwiched between the second conductive layer and the third insulating layer from above and below. A method for manufacturing a semiconductor device includes forming a semiconductor layer to cover side surfaces of the opening in the edge layer, the opening in the second conductive layer, and the opening in the third insulating layer and to fill the gap; forming a first layer on the semiconductor layer to fill the opening; removing a portion of the first layer so that the height of the top surface of the first layer is lower than the height of the top surface of the third insulating layer; using the first layer as a second mask, removing a portion of the semiconductor layer that is higher than the height of the top surface of the first layer; removing the first layer; forming a fourth insulating layer to cover the semiconductor layer in the opening; and forming a third conductive layer on the fourth insulating layer.

[0017] In the above aspect, when removing the semiconductor layer using the first layer as the second mask, it is preferable that the removal be performed so that the height of the upper end of the semiconductor layer within the opening is lower than the height of the upper surface of the third insulating layer and higher than the height of the upper surface of the portion of the semiconductor layer located on the second conductive layer.

[0018] Alternatively, one embodiment of the present invention includes forming a first conductive layer over a first insulating layer, forming a second insulating layer over the first insulating layer and the first conductive layer, forming a second conductive layer over the second insulating layer to have a portion overlapping with the first conductive layer, forming a third insulating layer over the second insulating layer and the second conductive layer, forming a third conductive layer over the third insulating layer, forming an opening that reaches the first conductive layer in the third conductive layer, the third insulating layer, the second conductive layer, and the second insulating layer, forming a semiconductor layer to cover a top surface of the first conductive layer, a side surface of the opening in the second insulating layer, a side surface of the opening in the second conductive layer, and a side surface of the opening in the third insulating layer, and forming a semiconductor layer between a first portion facing the side surface of the opening in the second insulating layer and the semiconductor layer. a fourth insulating layer having a second portion facing a side surface of the opening of the second conductive layer, a third portion facing a side surface of the opening of the third insulating layer with a semiconductor layer sandwiched therebetween, and a fourth portion facing a top surface of the first conductive layer with the semiconductor layer sandwiched therebetween; a part of the fourth insulating layer is removed so that the height of the top surface of the third portion of the fourth insulating layer is lower than the height of the top surface of the third insulating layer; using the fourth insulating layer as a mask, a portion of the semiconductor layer that is higher than the height of an upper end of the third portion of the fourth insulating layer is removed; the fourth insulating layer is removed; a fifth insulating layer is formed in the opening so as to cover the semiconductor layer; a fourth conductive layer is formed on the fifth insulating layer; and the third conductive layer is removed.

[0019] In the above aspect, it is preferable that in removing a portion of the fourth insulating layer, the fourth portion of the fourth insulating layer is removed, and in removing the semiconductor layer using the fourth insulating layer as a mask, a second opening reaching the first conductive layer is formed in a portion covering the upper surface of the first conductive layer of the semiconductor layer, and the fifth insulating layer and the fourth conductive layer are formed so as to have portions located within the second opening.

[0020] In the above aspect, when removing the semiconductor layer using the fourth insulating layer as a mask, it is preferable that the semiconductor layer is removed so that the height of the upper end of the semiconductor layer is lower than the height of the upper surface of the third insulating layer and higher than the height of the upper surface of the second conductive layer.

[0021] In any one of the above aspects, it is preferable that the first layer be a layer containing carbon formed by spin coating.

[0022] In addition, in any one of the above aspects, it is preferable that the formation of the opening in the third insulating layer is carried out using a first mask, and that the first mask is removed before the formation of the opening in the second insulating layer.

[0023] In any one of the above aspects, the semiconductor layer preferably contains a metal oxide.

[0024] In any one of the above aspects, the second conductive layer preferably contains a metal oxide having electrical conductivity.

[0025] According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with low parasitic capacitance can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a manufacturing method of a semiconductor device having the above characteristics can be provided.

[0026] According to one embodiment of the present invention, a semiconductor device can be manufactured with a high yield. According to one embodiment of the present invention, the number of manufacturing steps of a semiconductor device can be reduced. According to one embodiment of the present invention, the manufacturing cost of a semiconductor device can be reduced.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIG. 1A is a plan view illustrating an example of a semiconductor device. FIG. 1B is a cross-sectional view illustrating an example of a semiconductor device. FIG. 1C is a perspective view illustrating an example of a semiconductor device. FIGS. 2A and 2B are cross-sectional views illustrating an example of a semiconductor device. FIGS. 3A, 3B, 3C, and 3D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views illustrating an example of a semiconductor device. FIG. 4C is a plan view illustrating an example of a semiconductor device. FIG. 5A is a plan view illustrating an example of a semiconductor device. FIGS. 5B and 5C are cross-sectional views illustrating an example of a semiconductor device. FIGS. 6A, 6B, 6C, and 6D are cross-sectional views illustrating an example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 8A and 8B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 9A, 9B, and 9C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 10A, 10B, and 10C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11A and 11B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. 12A, 12B, and 12C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13A and 13B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 14A is a plan view illustrating an example of a memory device. FIG. 14B is a cross-sectional view illustrating an example of a memory device. FIG. 15A is a plan view illustrating an example of a memory device. FIGS. 15B and 15C are cross-sectional views illustrating an example of a memory device. FIG. 16 is a cross-sectional view illustrating an example of a memory device. FIG. 17 is a cross-sectional view illustrating an example of a memory device. FIG. 18A is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 18B and 18C are perspective views illustrating a configuration example of a semiconductor device. FIGS. 19A, 19B, 19C, 19D, 19E, 19F, 19G, and 19H are diagrams illustrating an example of a circuit configuration of a memory cell. FIG. 20 is a diagram illustrating an example of a circuit configuration of a memory cell. FIG. 21A is a block diagram illustrating a CPU. FIG. 21B is a perspective view of a semiconductor device. FIG. 22 is a conceptual diagram illustrating layers of a memory device. 23A and 23B show examples of the configuration of electronic components, and Fig. 24A, Fig. 24B, and Fig. 24C show examples of mainframe computers.Fig. 24D is a diagram showing an example of space equipment. Fig. 24E is a diagram showing an example of a storage system applicable to a data center. Figs. 25A and 25B are diagrams explaining the carrier concentration dependence of Hall mobility. Fig. 25C is a cross-sectional view explaining an indium oxide film.

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or stacking order). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0033] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0034] In this specification and the like, a transistor using a metal oxide for a semiconductor layer and a transistor having a metal oxide for a channel formation region may be referred to as an OS (oxide semiconductor) transistor. A transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0035] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0036] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0037] Note that impurities in a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen deficiency (V) in the metal oxide. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0038] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0039] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0040] In this specification, the term "content" refers to the proportion of a component contained in a film. For example, if a metal oxide layer contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide layer is A, then the number of atoms of each of metal elements X, Y, and Z is A. Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) The content of the metal element X in the metal oxide layer can be expressed as the content not taking into account oxygen, impurities, etc.

[0041] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0042] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0043] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0044] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0045] Specific examples of "indirect connection" are given below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming that the circuit is operating, it is assumed that there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where there is a time when one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that there is at least one time when each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow, assuming that the circuit is operating. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0046] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0047] Another example of a case in which it cannot be said that "A and B are indirectly connected" is when there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. For example, a path from A to B may have multiple transistors connected via their sources and drains, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." Note that if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply, GND, or the like, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and C are indirectly connected" or "B and C are indirectly connected."

[0048] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0049] Next, specific examples of "direct connection" are shown. An example of "A and B are directly connected" is when A and B are connected without any circuit element between them. Note that when A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Note that even when A (or B) is connected to a constant potential V via the source and drain of a transistor, it can still be said that "A and B are directly connected." Note that because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, and it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0050] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0051] In this specification and the like, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the leakage current between the source and the gate when the voltage V ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0052] In this specification, "normally on" refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, and "normally off" refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0053] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0054] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0055] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0056] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0057] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and there may be no distinction between the forward direction and the reverse direction unless explicitly stated. The same applies to the "Y direction" and the "Z direction." Furthermore, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other, i.e., vertical directions.

[0058] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described.

[0059] A semiconductor device according to one embodiment of the present invention includes a transistor and a first insulating layer. The transistor according to one embodiment of the present invention includes a semiconductor layer, a first conductive layer, and a second conductive layer. The first insulating layer is located on the first conductive layer, and the second conductive layer is located on the first insulating layer. The first conductive layer can function as one of a source electrode and a drain electrode, and the second conductive layer can function as the other of the source electrode and the drain electrode. In the transistor according to one embodiment of the present invention, the source electrode and the drain electrode are located at different heights (e.g., heights perpendicular to a substrate surface or an insulating plane on which the transistor is provided), and a current flows in the height direction through the semiconductor layer. In other words, the channel length direction can be said to have a component in the height direction (vertical direction). Therefore, the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0060] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided so as to overlap with each other; therefore, the area occupied by the transistor can be significantly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0061] Furthermore, the channel length of the transistor of one embodiment of the present invention can be controlled by the thickness of an insulating layer provided between a source electrode and a drain electrode, etc. Therefore, a transistor with an extremely short channel length, which is difficult to achieve with a planar transistor, can be realized. Therefore, a transistor with a small occupation area and large on-state current can be realized.

[0062] The semiconductor layer of the transistor of one embodiment of the present invention can contain a metal oxide. A transistor having a metal oxide in a channel formation region has a low off-state current. Therefore, when used in a memory device, for example, the transistor can retain stored data for a long period of time. That is, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced. By using the transistor of one embodiment of the present invention in a memory device, the memory device can be highly integrated and has low power consumption.

[0063] 1A illustrates a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0064] A semiconductor device of one embodiment of the present invention includes an insulating layer 210, a transistor 200 over the insulating layer 210, a conductive layer 265, an insulating layer 280, and an insulating layer 281. In the structure shown in FIG. 1A , the semiconductor device includes an insulating layer 278 over the transistor 200.

[0065] The transistor 200 includes a conductive layer 220, a conductive layer 240, an oxide semiconductor layer 230, an insulating layer 250, and a conductive layer 260. The conductive layer 265 is located over the conductive layer 260. The conductive layer 265 is provided on and in contact with the conductive layer 260.

[0066] The conductive layer 220 is located on the insulating layer 210, the insulating layer 280 is located on the conductive layer 220, the conductive layer 240 is located on the insulating layer 280, and the insulating layer 281 is located on the conductive layer 240 and the insulating layer 280. The conductive layer 240 has a portion overlapping with the conductive layer 220, with the insulating layer 280 sandwiched therebetween.

[0067] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion is preferably used for the conductive layer 220 and the conductive layer 240. Examples of the conductive material include a conductive material containing oxygen and a conductive material containing nitrogen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0068] The conductive layer 220 and the conductive layer 240 can each function as wirings of the semiconductor device. The use of a highly conductive material for the wirings is preferable because it can increase the speed of circuit operation of the semiconductor device. Examples of highly conductive materials include metals and metal alloys.

[0069] The conductive layer 220 is a conductive layer in contact with the insulating layer 210. When an oxide is used for the insulating layer 210, it is preferable to use one or both of a conductive material containing nitrogen and a conductive material containing oxygen for the conductive layer 220, because conductivity can be maintained.

[0070] FIG. 1A shows an example in which the conductive layer 220 has a stacked structure of a conductive layer 220a, a conductive layer 220b on the conductive layer 220a, and a conductive layer 220c on the conductive layer 220b, and the conductive layer 240 has a stacked structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a.

[0071] For example, one or both of a conductive material containing oxygen and a conductive material containing nitrogen can be used for the conductive layer 220c and the conductive layer 240b, which are layers in contact with the oxide semiconductor layer 230. For example, a material with high conductivity can be used for the conductive layer 220b and the conductive layer 240a. For example, one or both of a conductive material containing nitrogen and a conductive material containing oxygen can be used for the conductive layer 220a, which is a layer in contact with the insulating layer 210.

[0072] Materials applicable to the laminated structures of the conductive layer 220 and the conductive layer 240 will be described in detail below.

[0073] Since the insulating layer 280 functions as an interlayer film, it is preferable to use a material with a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0074] An insulating layer having a barrier property against impurities is preferably used as the insulating layer 280. The concentration of impurities such as water and hydrogen in the insulating layer is preferably reduced, which can prevent impurities from entering the channel formation region of the oxide semiconductor layer 230.

[0075] FIG. 1A shows an example in which the insulating layer 280 has a stacked structure of an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b.

[0076] The insulating layer 280b can be made of a material with a low dielectric constant, and the insulating layers 280a and 280c can be made of a barrier insulating layer against impurities.

[0077] Materials applicable to each layer of the laminated structure of the insulating layer 280 will be described in detail below.

[0078] The conductive layer 260 can function as wiring such as a word line. By using a highly conductive material for the conductive layer 260, the wiring resistance can be reduced. Furthermore, by using a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion for the conductive layer 260, oxidation of the conductive layer 260 due to oxygen diffusion from surrounding layers can be suppressed. Furthermore, by extending the conductive layer 265 on the conductive layer 260, it can be used as wiring such as a word line.

[0079] 1A shows an example in which the conductive layer 260 has a stacked structure of a conductive layer 260a and a conductive layer 260b over the conductive layer 260a. Materials that can be used for each layer of the stacked structure of the conductive layer 260 will be described in detail later.

[0080] The conductive layer 260a can be formed using, for example, a conductive material containing nitrogen or a conductive material containing oxygen, and the conductive layer 260b can be formed using, for example, a material with high conductivity.

[0081] An opening 290 reaching the conductive layer 220 is provided in the insulating layer 281, the conductive layer 240, and the insulating layer 280. At this time, the opening provided in the insulating layer 280 is referred to as an opening 290a, the opening provided in the conductive layer 240 is referred to as an opening 290b, and the opening provided in the insulating layer 281 is referred to as an opening 290c.

[0082] By providing openings in the conductive layer 240, the insulating layer 280, and the insulating layer 281 using the same mask, the side surface of the insulating layer 280 on the opening 290a side, the side surface of the conductive layer 240 on the opening 290b side, and the side surface of the insulating layer 281 on the opening 290c side can be aligned. Note that after processing an upper layer film of the processing target film using a mask such as a resist mask, the processing target film may be performed using the processed upper layer film as a mask. Specifically, for example, after forming the opening 290b in the conductive layer 240 using a mask such as a resist mask, the opening 290a may be formed in the insulating layer 280 using the conductive layer 240 as a mask.

[0083] The oxide semiconductor layer 230 has a portion located within the opening 290. More specifically, the oxide semiconductor layer 230 has a portion along the sidewall of the opening 290. The oxide semiconductor layer 230 has a portion on the conductive layer 220, a portion along the side surface of the opening 290a in the insulating layer 280, a portion along the side surface of the opening 290b in the conductive layer 240, and a portion along the side surface of the opening 290c in the insulating layer 281.

[0084] The insulating layer 250 and the conductive layer 260 each have a portion located within the opening 290 .

[0085] The conductive layer 220 can function as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 240 can function as the other of the source electrode and the drain electrode of the transistor 200. The conductive layer 260 can function as a gate electrode of the transistor 200. The insulating layer 250 can function as a gate insulating layer of the transistor 200.

[0086] The oxide semiconductor layer 230 has a portion facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween. The conductive layer 260 also has a portion facing the side surface of the insulating layer 280 on the opening 290 side, with the oxide semiconductor layer 230 and the insulating layer 250 sandwiched therebetween. At least part of this portion functions as a channel formation region of the transistor 200. A region of the oxide semiconductor layer 230 near the conductive layer 220 functions as one of the source region and the drain region, and a region of the oxide semiconductor layer 230 near the conductive layer 240 functions as the other of the source region and the drain region. That is, the channel formation region is sandwiched between the source region and the drain region.

[0087] The transistor 200 has a structure in which one of the source electrode and the drain electrode (the conductive layer 220 here) is located below and the other of the source electrode and the drain electrode (the conductive layer 240 here) is located above, and thus current flows vertically. That is, a channel is formed in the oxide semiconductor layer 230 in a region provided along the side surface of the opening 290.

[0088] In the oxide semiconductor layer 230, for example, at least a part of a region in contact with the conductive layer 220 functions as one of a source region and a drain region of the transistor, at least a part of a region in contact with the conductive layer 240 functions as the other of the source region and the drain region of the transistor, and at least a part of a region not in contact with the conductive layer 220 or the conductive layer 240 functions as a channel formation region of the transistor.

[0089] The semiconductor device of one embodiment of the present invention can achieve excellent transistor characteristics even when applied to a memory device having a memory cell array with high element density, a display device having a high-definition display portion, or the like.

[0090] In the transistor 200, a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are separately provided on the XY plane. Therefore, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a display device, the resolution of the display portion can be improved.

[0091] In this specification, a planar transistor refers to a transistor in which the source electrode and the drain electrode are located at the same height or approximately the same height relative to a reference plane, and the current flowing through the semiconductor has a lateral component. Here, the reference plane can be, for example, the substrate surface. Here, the lateral direction refers, for example, to a direction parallel to the substrate surface. In this specification, a VFET refers to a transistor in which the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor has a vertical component. Since a VFET can have two or more of the source electrode, semiconductor, and drain electrode stacked, it can occupy a significantly smaller area than a planar transistor.

[0092] 1A and the like, the top surface of the insulating layer 210 can be approximately parallel to the substrate surface, and the top surface of the conductive layer 220 can be approximately parallel to the substrate surface.

[0093] By providing the insulating layer 281 on the conductive layer 240, the conductive layer 240 and a conductive layer provided above the conductive layer 240, for example, the conductive layer 265 in this case, can be spaced apart by at least the thickness of the insulating layer 281 on the conductive layer 240. The conductive layer 265 can function as a wiring connected to the conductive layer 260. The distance between the conductive layer 240 and the conductive layer 265 can reduce parasitic capacitance generated between the two conductive layers. Furthermore, the leakage current between the conductive layer 240 and the conductive layer 265 can be reduced. Note that the insulating layer 281 preferably has a thickness sufficient to sufficiently reduce the parasitic capacitance generated between the conductive layer 240 and the conductive layer 265, and the equivalent oxide thickness (EOT) of the insulating layer 281 is preferably at least thicker than the equivalent oxide thickness of the insulating layer 250. In this specification, the equivalent oxide thickness refers to a value obtained by converting a physical film thickness into an electrical film thickness equivalent to silicon oxide. The thickness of the insulating layer 281 can be determined by referring to the thickness of the insulating layer 280, for example.

[0094] The oxide semiconductor layer 230 preferably contains a metal oxide (also referred to as an oxide semiconductor). The oxide semiconductor layer 230 contains a metal oxide, which can significantly reduce the off-state current of the transistor 200. A transistor including the oxide semiconductor layer 230 in a channel formation region may be referred to as an OS transistor hereinafter.

[0095] When oxygen vacancies and impurities exist in a channel formation region of an oxide semiconductor, the electrical characteristics of an OS transistor are likely to fluctuate, and the reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to be normally on. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0096] Oxygen is supplied to the oxide semiconductor layer 230 from each layer included in the transistor 200 (e.g., insulating layers such as the insulating layer 250) and each layer disposed around the transistor 200 (e.g., insulating layers such as the insulating layer 280), thereby reducing oxygen vacancies in the oxide semiconductor layer 230. Consider a case where multiple transistors are arranged in a certain region of a semiconductor device. In this case, when the ratio of the volume of each layer that supplies oxygen to the volume occupied by the transistor 200 decreases, the amount of oxygen supplied per transistor 200 decreases. As the integration density of a circuit increases, the transistors 200 are arranged more densely, and therefore the amount of oxygen supplied per transistor decreases. Therefore, in a highly integrated circuit, there is a concern that the extraction of oxygen from the oxide semiconductor layer 230 by the conductive layer 240 will have a more significant effect on the characteristics of the transistor 200. Oxygen is supplied to the oxide semiconductor layer 230 from each layer disposed around the transistor 200, thereby stabilizing the transistor characteristics even in a highly integrated circuit.

[0097] 1B is a cross section taken along dashed dotted line A1-A2 in FIG. 1A and perpendicular to the cross section in FIG. 1A. FIG. 1B can also be expressed as a plan view including an opening 290a in an insulating layer 280. FIG. 1C is a perspective view showing an example of the configuration of the transistor 200 shown in FIGS. 1A and 1B. Note that the configuration of the transistor 200 shown in FIGS. 1A and 1B is not limited to that shown in FIG. 1C.

[0098] As shown in FIG. 1B , the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. Therefore, the side surface of the conductive layer 260 provided at the center faces the side surface of the oxide semiconductor layer 230 with the insulating layer 250 interposed therebetween. That is, in a plan view, the entire periphery of the oxide semiconductor layer 230 becomes a channel formation region. In this case, for example, the channel width of the transistor 200 is determined by the periphery of the oxide semiconductor layer 230 on the conductive layer 260 side. That is, the channel width of the transistor 200 can be determined by the width of the opening 290 (or the diameter when the opening 290 is circular in a plan view). In FIG. 1B , the channel width W of the transistor 200 is shown.

[0099] Increasing the width D of the opening 290 increases the channel width per unit area, thereby increasing the on-state current. On the other hand, the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view, is roughly determined by the width of the opening 290. Reducing the width D of the opening 290 reduces the area occupied by the transistor 200, thereby enabling a semiconductor device to be highly integrated.

[0100] The width D of the opening 290 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the conductive layer 240 on the opening 290b side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 290b in the conductive layer 240 is used as the width D of the opening 290b. Alternatively, the width of the opening 290b at the highest position in the conductive layer 240, the width of the opening 290b at the lowest position, the width of the opening 290b at the midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 290b in the conductive layer 240, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the insulating layer 280 on the opening 290a side can be used as the width D. Furthermore, the width of the opening 290a at the highest position in the insulating layer 280, the width of the opening 290a at the lowest position, the width of the opening 290a at the midpoint between these, or the average value of these three widths may be used as the width D.

[0101] When the opening 290 is formed using photolithography, the width D of the opening 290 is limited by the exposure limit of photolithography. The width D of the opening 290 is, for example, preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, and more preferably 20 nm to 100 nm. It is also preferably 5 nm to 60 nm, more preferably 10 nm to 60 nm, and more preferably 20 nm to 60 nm. It is also preferably 5 nm to 50 nm, more preferably 10 nm to 50 nm, and more preferably 20 nm to 50 nm. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x π".

[0102] The channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 1A , the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. The channel length L can be considered to be the distance between the end of the region where the oxide semiconductor layer 230 and the conductive layer 220 face each other and the end of the region where the oxide semiconductor layer 230 and the conductive layer 240 face each other in a cross-sectional view. In this case, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 290 side in a cross-sectional view.

[0103] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length of the transistor 200 can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor 200 can be made extremely small, equal to or less than the exposure limit of photolithography. This increases the on-state current of the transistor 200, thereby improving frequency characteristics. The channel length of the transistor 200 is preferably, for example, 0.1 nm to 60 nm, 0.1 nm to 50 nm, 0.1 nm to 40 nm, 0.1 nm to 30 nm, 0.1 nm to 20 nm, or 0.1 nm to 10 nm. Alternatively, for example, the channel length is preferably 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, or 1 nm to 10 nm. Alternatively, for example, 5 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm is preferable.

[0104] Note that the channel length of the transistor 200 corresponds to the thickness of the insulating layer 280 over the conductive layer 220 and does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. By setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in a step of forming the insulating layer 280, a step of forming the opening 290 in the insulating layer 280, and the like.

[0105] The channel length L of the transistor 200 is preferably at least shorter than the channel width W of the transistor 200. The channel length L of the transistor 200 is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width W of the transistor 200. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0106] As described above, by forming the opening 290 so as to have a circular shape in a plan view, the oxide semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are provided concentrically. Because a circle has no corners, it is easy to apply a gate electric field from the conductive layer 260 uniformly and the gate electric field is less likely to concentrate locally.

[0107] Although the present embodiment illustrates an example in which the opening 290 is circular in plan view, the present invention is not limited thereto. In plan view, the opening 290 may be, for example, a circle, an approximately circular shape such as an oval, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygonal shape with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1B and other figures, the opening 290 is preferably circular in plan view. By using a circular shape, the processing precision during the formation of the opening can be improved, allowing for the formation of openings of minute sizes. In this specification and other figures, the term "circular" is not limited to a perfect circle.

[0108] 1C and other drawings, the conductive layer 260 has a columnar shape. The oxide semiconductor layer 230 has a portion facing a side surface of the conductive layer 260 with the insulating layer 250 sandwiched therebetween.

[0109] A region of the oxide semiconductor layer 230 that is located within the opening 290c and covers the side surface of the opening 290c does not contribute to a channel formation region and overlaps with the conductive layer 260 with the insulating layer 250, which is thinner than the insulating layer 281, sandwiched therebetween, which might generate significant parasitic capacitance between the oxide semiconductor layer 230 and the conductive layer 260. Therefore, in the semiconductor device of one embodiment of the present invention, it is preferable to reduce the area where the oxide semiconductor layer 230 and the conductive layer 260 overlap within the opening 290c.

[0110] In the opening 290c, the upper end of the oxide semiconductor layer 230 is preferably lower than the upper end of the conductive layer 260. This can reduce the area where the oxide semiconductor layer 230 overlaps with the conductive layer 260 with the insulating layer 250 sandwiched therebetween, thereby reducing parasitic capacitance that causes a delay in the operating speed of the semiconductor device.

[0111] If the difference in height between the upper surface of the upper surface of the conductive layer 240 and the upper surface of the conductive layer 260 within 290c is H1, and the difference in height between the upper surface of the conductive layer 240 and the upper end of the oxide semiconductor layer 230 within the opening 290c is H2, then H2 is preferably, for example, 1 / 2 or less of H1, and more preferably 1 / 3 or less of H1.

[0112] <Angle of Side Surface of Opening> Fig. 2A is an enlarged view of a region including insulating layer 280 and insulating layer 281 in Fig. 1A. In Fig. 2A, the hatching patterns of conductive layer 220c, conductive layer 240a, and conductive layer 240b are omitted.

[0113] By making the side surface of the opening 290c in the insulating layer 281, the side surface of the opening 290b in the conductive layer 240, and the side surface of the opening 290a in the insulating layer 280 perpendicular to the reference plane, the integration density of the transistor 200 can be increased, which is preferable. Here, the reference plane is, for example, the top surface of the conductive layer 220. The top surface of the insulating layer 210, the substrate surface, or the like can also be used as the reference plane. Alternatively, by making the top end and its vicinity tapered with a small inclination angle and making the lower end thereof tapered with a larger inclination angle, the opening can be shaped like a mortar, which improves coverage with the oxide semiconductor layer 230, the insulating layer 250, the conductive layer 260, and the like.

[0114] The inclinations of the side surface of the insulating layer 280 on the opening 290a side and the side surface of the conductive layer 240 on the opening 290b side are defined as angles d_1 and d_4, respectively. Each angle is an angle formed with a plane that serves as a reference plane in a cross-sectional view, for example. The reference plane may be, for example, the top surface of the conductive layer 220. Alternatively, the top surface of the insulating layer 210 may be used as the reference plane. Alternatively, the substrate surface may be used as the reference plane.

[0115] Preferably, angle d_1 and angle d_4 are each 45 degrees or greater and less than 90 degrees. Specifically, if the angle is 80 degrees or greater and less than 90 degrees, as described above, miniaturization or high integration of the semiconductor device can be achieved, which is preferable. Furthermore, if the angle is 45 degrees or greater or 50 degrees or greater and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed in opening 290 is improved, which is preferable.

[0116] The angle of the side surface of the opening 290c of the insulating layer 281 is preferably, for example, 45 degrees or more and less than 90 degrees. Specifically, if the angle is 80 degrees or more and less than 90 degrees, as described above, miniaturization or high integration of the semiconductor device can be achieved, which is preferable. Furthermore, if the angle is 45 degrees or more or 50 degrees or more and less than 80 degrees, 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less, the coverage of the film formed in the opening 290 is improved, which is preferable.

[0117] The angle of the side surface of the opening 290c is, for example, the angle formed with a plane serving as a reference plane in a cross-sectional view. The reference plane may be, for example, the top surface of the conductive layer 220. Alternatively, the top surface of the insulating layer 210 may be used as the reference plane. Alternatively, the substrate surface may be used as the reference plane.

[0118] 2A shows an example in which the angle d_6 of the side surface of the insulating layer 281 at and near the upper end of the opening 290c is smaller than the angle d_5 of the side surface below the upper end. The side surface of the opening 290c of the insulating layer 281 may have a tapered shape as it approaches the upper end. By making the angle d_6 smaller than the angle d_5, it is possible to improve the coverage of the insulating layer 250, the conductive layer 260, etc. on the side surface of the opening 290c.

[0119] 2B , the angle of the side surface of the upper end and its vicinity of the opening 290c may be approximately vertical instead of tapered. By making the angle approximately vertical, the diameter of the opening 290c can be reduced. This may result in a smaller area occupied by the transistor.

[0120] 6A is a modified example of FIG. 1A , in which angle d_4 differs between conductive layer 240a and conductive layer 240b. The inclination of the side surface of conductive layer 240a facing opening 290b is angle d_4a, and the inclination of the side surface of conductive layer 240b facing opening 290b is angle d_4b. FIG. 6B is an enlarged view of a region including conductive layer 240 in FIG. 6A .

[0121] 6A , the angle d_4a is smaller than the angle d_4b. The angle d_4a is, for example, less than 70°, less than 60°, less than 50°, or less than 40°. By making the angle d_4a smaller than the angle d_4b, for example, the coverage of the conductive layer 240a and the conductive layer 240b with the oxide semiconductor layer 230 and the insulating layer 250 and the conductive layer 260 thereover can be improved.

[0122] 6C is a modified example of Fig. 1A, showing an example in which conductive layer 240b is recessed by etching or the like during the formation of opening 290, so that the side surface of conductive layer 240b on the opening 290b side is positioned more outward from the center of the opening than the side surface of insulating layer 281 on the opening 290c side (or the side surface of conductive layer 240a on the opening 290b side). Fig. 6D is an enlarged view of a region including conductive layer 240 in Fig. 6C.

[0123] 6D , the side surface of the conductive layer 240b on the opening 290b side is positioned outward by a width H7 from the side surface of the insulating layer 281 on the opening 290c side (or the side surface of the conductive layer 240a on the opening 290b side). The width H7 is preferably, for example, 0.5 times or more the film thickness of the oxide semiconductor layer 230 covering the side surface of the insulating layer 280.

[0124] Although FIGS. 6C and 6D show an example in which the angle d_4a is smaller than the angle d_4b, the present invention is not limited to this.

[0125] 3A is a modified example of the configuration of the semiconductor device shown in FIG. 1A , and differs mainly in that the oxide semiconductor layer 230 has a portion on the conductive layer 240. Also, FIG. 3B is an enlarged view of a region including the conductive layer 240 in FIG. 3A .

[0126] 3A and 3B , the oxide semiconductor layer 230 has a portion on the conductive layer 220, a portion along the side surface of the opening 290 a in the insulating layer 280, a portion along the side surface of the opening 290 b in the conductive layer 240, a portion located on the conductive layer 240 (shown as portion 279 in FIG. 3B ), and a portion along the side surface of the opening 290 c in the insulating layer 281. The portion 279 is sandwiched between the conductive layer 240 and the insulating layer 281 from above and below.

[0127] 3A and 3B , the oxide semiconductor layer 230 has a portion facing the side surface of the conductive layer 260 with the insulating layer 250 sandwiched therebetween, and a portion (portion 279) located on the conductive layer 240 and surrounding the conductive layer 260 with the insulating layer 250 sandwiched therebetween. The portion 279 can be formed by forming a void sandwiched between the conductive layer 240 and the insulating layer 281 and then filling the void with a semiconductor layer. The void can be formed, for example, by patterning a sacrificial layer stacked on the conductive layer 240 together with the conductive layer 240, and then removing the sacrificial layer under conditions that allow selective etching (e.g., wet etching) after forming the opening 290. The oxide semiconductor layer 230 having the portion 279 can be configured so that the oxide semiconductor layer 230 is in contact with the top surface of the conductive layer 240b in addition to the side surface of the conductive layer 240b. This allows for a larger contact area between the oxide semiconductor layer 230 and the conductive layer 240b. Therefore, the contact resistance between the oxide semiconductor layer 230 and the conductive layer 240 can be reduced.

[0128] In the opening 290c, the upper end of the oxide semiconductor layer 230 is preferably lower than the upper end of the conductive layer 260. This makes it possible to reduce the area where the oxide semiconductor layer 230 overlaps with the conductive layer 260, with the insulating layer 250 sandwiched therebetween, and to reduce parasitic capacitance that causes a delay in the operating speed of the semiconductor device. On the other hand, if the height of the upper end of the oxide semiconductor layer 230 in the opening 290c is lower than the height of the upper surface of the oxide semiconductor layer 230 located on the conductive layer 240, the oxide semiconductor layer 230 will be discontinuous between the opening 290c and on the conductive layer 240, which may hinder conduction between the oxide semiconductor layer 230 and the conductive layer 240 or increase contact resistance between the oxide semiconductor layer 230 and the conductive layer 240.

[0129] Therefore, it is preferable that the height of the upper end of the oxide semiconductor layer 230 in the opening 290c is higher than the upper surface of a portion of the oxide semiconductor layer 230 located on the conductive layer 240 and lower than the height of the upper surface of the periphery of the insulating layer 281. This can improve the reliability and operating speed of the semiconductor device.

[0130] If the difference in height between the upper surface of the oxide semiconductor layer 230 covering the upper surface of the conductive layer 240 and the upper surface of the conductive layer 260 within the opening 290c is defined as H1', ​​and the difference in height between the upper surface of the oxide semiconductor layer 230 covering the upper surface of the conductive layer 240 and the upper end of the oxide semiconductor layer 230 within the opening 290c is defined as H2', then H1' is preferably, for example, ½ or less of H2', and more preferably ⅓ or less of H2'.

[0131] 3A and 3B , the side surface of the portion 279 of the oxide semiconductor layer 230 is aligned with the side surface of the conductive layer 240 opposite to the opening 290b. When the same mask is used to process the sacrificial layer used to form the void into which the portion 279 of the oxide semiconductor layer 230 is embedded and the conductive layer 240, a configuration in which the side surfaces are aligned can be achieved.

[0132] On the other hand, when processing the sacrificial layer and the conductive layer 240, different masks can be used, so that the side surface of portion 279 of the oxide semiconductor layer 230 does not coincide with the side surface of the conductive layer 240.

[0133] In portion 279, oxide semiconductor layer 230 is formed so as to cover the upper surface of conductive layer 240b, the side surface of insulating layer 281, and the lower surface of insulating layer 281. At this time, as shown in Figures 3C and 3D , a void 273 surrounded by oxide semiconductor layer 230 may be formed in portion 279. Figure 3C shows that, in void 273 surrounded by oxide semiconductor layer 230, the void is blocked by oxide semiconductor layer 230 on the side closer to insulating layer 250, while Figure 3D shows that void 273 is not blocked by oxide semiconductor layer 230, and insulating layer 250 is disposed to cover the void. In Figure 3D , void 273 is surrounded by oxide semiconductor layer 230 and insulating layer 250.

[0134] 4A is a modified example of the configuration of the semiconductor device shown in FIG. 1A , and is mainly different in that the oxide semiconductor layer 230 has an opening 289 and that the insulating layer 250 and the conductive layer 260 are also provided in the opening 289. FIG. 4B is an enlarged view of a region including the conductive layer 220 in FIG. 4A .

[0135] As shown in FIGS. 4A and 4B , the oxide semiconductor layer 230 has an opening 289 in a portion covering the conductive layer 220. In a region overlapping with the opening 289, the upper surface of the conductive layer 220 has a recess. The insulating layer 250 is provided to cover the recess. The insulating layer 250 and the conductive layer 260 have a portion within the opening 289 of the oxide semiconductor layer 230 and a portion within the recess of the conductive layer 220 that overlaps with the opening 289. This reduces the distance between the bottom end of the conductive layer 260 and the conductive layer 220, allowing a gate electric field to be applied up to the vicinity of the conductive layer 220. In addition, in FIGS. 4A and 4B , the conductive layer 260 and the conductive layer 220 have portions that face each other with the oxide semiconductor layer 230 and the insulating layer 250 sandwiched therebetween. This allows a structure in which one of the source region and the drain region of the semiconductor layer overlaps with the gate electrode.

[0136] Fig. 4C shows an example of a cross section including the dashed dotted line A3-A4 shown in Fig. 4B. The cross section shown in Fig. 4C is perpendicular to the cross section shown in Fig. 4B. Fig. 4C can also be expressed as a plan view including the opening 289 of the oxide semiconductor layer 230.

[0137] Although the present embodiment illustrates an example in which the opening 289 is circular in plan view, the present invention is not limited to this. In plan view, the opening 289 may be, for example, a circle, an approximately circle such as an oval, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or any of these polygons with rounded corners. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0138] 1A to 4C , the conductive layer 220, the conductive layer 240, and the conductive layer 265 can each be extended to function as wiring. As an example, FIGS. 5A to 5C show an example in which, in the configuration shown in FIG. 1A , the conductive layer 220 and the conductive layer 240 extend in a first direction (the X direction shown in the figure), and the conductive layer 265 extends in a second direction (the Y direction shown in the figure). Note that the direction in which the conductive layers extend is not limited to this. Alternatively, a configuration in which only a portion of the conductive layer 220, the conductive layer 240, and the conductive layer 265 extends may also be used. For example, the conductive layer 265 and one or more of the conductive layer 240 and the conductive layer 220 are provided so as to intersect with each other.

[0139] 5A to 5C illustrate a configuration example of a semiconductor device according to one embodiment of the present invention. FIG. 5A is a plan view illustrating the example of the semiconductor device. FIG. 5B is a cross-sectional view corresponding to the dashed-dotted line C1-C2 illustrated in FIG. 5A, and FIG. 5C is a cross-sectional view corresponding to the dashed-dotted line C3-C4 illustrated in FIG. 5A. Note that some elements are omitted in FIG. 1A for clarity. Some elements may also be omitted in the subsequent plan views.

[0140] In Figures 5A to 5C, the conductive layer 265 extends in the Y direction.

[0141] By crossing the conductive layer 265 and the conductive layer 240, the overlapping area between the conductive layer 265 and the conductive layer 240 can be reduced, and the parasitic capacitance between the two conductive layers can be reduced. Furthermore, by crossing the conductive layer 265 and the conductive layer 240, for example, a configuration can be achieved in which a plurality of transistors 200 are arranged in a matrix and a signal is applied to a transistor 200 corresponding to the crossed wiring. In the configurations shown in Figures 5A to 5C, the conductive layer 240 extends in the X direction.

[0142] In the configuration shown in FIGS. 5A to 5C, the conductive layer 220 extends in the X direction.

[0143] In FIG. 5B, the side surfaces of the opening 290a in the insulating layer 280, the side surfaces of the opening 290b in the conductive layer 240, and the side surfaces of the opening 290c in the insulating layer 281 can be aligned in the Y direction.

[0144] In addition, in FIG. 5C, the side surfaces of the opening 290a in the insulating layer 280, the side surfaces of the opening 290b in the conductive layer 240, and the side surfaces of the opening 290c in the insulating layer 281 can be aligned in the X direction.

[0145] <Example 1 of Manufacturing Method of Semiconductor Device> Thin films (insulating films, semiconductor films, conductive films, and the like) constituting a semiconductor device can be formed by a sputtering method, a CVD method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0146] Sputtering methods include RF sputtering, which uses a high-frequency power source as the sputtering power source; DC sputtering, which uses a direct current power source; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF-superimposed DC sputtering, which superimposes RF and DC, is also available. RF sputtering is preferred for film formation using insulating targets. DC sputtering is primarily used when forming films using conductive targets. DC sputtering can also form insulating films by reactive sputtering, in addition to forming conductive films. Pulsed DC sputtering is primarily used when forming films of compounds such as oxides, nitrides, and carbides using reactive sputtering. RF-superimposed DC sputtering allows for control of ion energy and target potential during film formation. Therefore, compared to RF sputtering, damage caused by film formation is reduced. High-quality films can also be obtained.

[0147] Examples of sputtering methods that can be used include ionization sputtering and long-throw sputtering. Ionization sputtering is a method in which sputtering particles generated from a target are ionized by RF or the like, and anisotropic film formation is achieved by self-bias or the like. In addition, long-throw sputtering can form anisotropic films by increasing the distance between the sputtering target and the substrate.

[0148] CVD methods can be classified into PECVD, thermal CVD (TCVD) using heat, photo CVD (Photo CVD) using light, etc. They can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD) depending on the source gas used.

[0149] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0150] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD (Plasma Enhanced ALD) method in which a plasma-excited reactant is used, or the like can be used.

[0151] Furthermore, the ALD method can deposit atoms layer by layer, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. The PEALD (Plasma Enhanced ALD) method may be preferable because it utilizes plasma, allowing film formation at lower temperatures. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. The amount of impurities can be quantified using XPS.

[0152] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of a workpiece. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0153] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0154] Furthermore, in the ALD method, when different types of precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor.

[0155] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0156] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0157] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0158] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0159] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0160] As an etching gas for the dry etching process, for example, a gas containing halogen can be used.

[0161] The halogen-containing gas may be, for example, an etching gas containing one or more of fluorine, chlorine, and bromine, such as a fluorocarbon gas, a hydrofluorocarbon gas, or SF ６ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr ３ The fluorocarbon gas may be a single gas or a mixture of two or more gases. ｘ F ｙ A gas represented by (y≦2x+2) can be used. An example of a fluorocarbon gas that satisfies y=2x+2 is CF.４ , C ２ F ６ , C ３ F ８ , C ４ F １０ , C ５ F １２ Examples of fluorocarbon gases that satisfy the condition y<2x+2 include saturated fluorocarbon compounds such as C ２ F ４ , C ２ F ２ , C ３ F ７ , C ３ F ４ , C ４ F ８ , C ４ F ６ , C ４ F ４ , C ４ F ２ , C ５ F １０ , C ５ F ８ , C ５ F ６ , C ５ F ４ Examples of hydrofluorocarbon gases include unsaturated fluorocarbon compounds such as CHF ３ Gas, CH ２ F ２ Gas, etc.

[0162] When a gas containing halogen is used as an etching gas, oxygen (O ２ ) gas, carbon dioxide, nitrogen (N ２ ) gas, helium gas, argon gas, hydrogen gas, hydrocarbon gas, or the like can be added as appropriate.

[0163] Alternatively, a gas containing no halogen gas but containing hydrocarbon gas or hydrogen gas can be used as the etching gas.

[0164] Examples of hydrocarbon gases include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H１０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ ) can be used.

[0165] When a hydrocarbon gas is used as the etching gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like may be added as appropriate.

[0166] Furthermore, a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes can be used as the dry etching apparatus. The capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, it may be configured to apply multiple different high-frequency voltages to one of the parallel-plate electrodes. Alternatively, it may be configured to apply a high-frequency voltage of the same frequency to each of the parallel-plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of different frequencies to each of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus can be used. The etching apparatus can be appropriately configured depending on the object to be etched.

[0167] As an example of a method for manufacturing a semiconductor device of one embodiment of the present invention, an example of a method for manufacturing the semiconductor device illustrated in FIG. 1A will be described with reference to FIGS. 7A to 9C.

[0168] First, an insulating layer 210 is formed over a substrate. As the insulating layer 210, an oxide insulating film, a nitride insulating film, an oxynitride insulating film, a nitride oxide insulating film, or the like can be used. For the insulating layer 210, a material having high etching resistance (low etching rate) under the etching conditions in the step of forming the conductive layer 220 is preferably used. Furthermore, for the insulating layer 210, an insulating layer having a barrier property against impurities is preferably used.

[0169] Next, the conductive layer 220 is formed over the insulating layer 210. After that, the insulating layer 280 is formed over the insulating layer 210 and the conductive layer 220. After the insulating layer 280 is formed, a top surface thereof may be planarized by planarization treatment.

[0170] Here, a stack of tantalum nitride (conductive layer 220a), tungsten (conductive layer 220b), and indium tin oxide (conductive layer 220c) is used as the conductive layer 220. Alternatively, indium tin oxide containing silicon may be used as the conductive layer 220c.

[0171] Here, the insulating layer 280 is formed by stacking silicon nitride (insulating layer 280a), silicon oxide (insulating layer 280b), and silicon nitride (insulating layer 280c).

[0172] Next, the conductive layer 240 is formed over the insulating layer 280. The conductive layer 240 has a stacked structure of a conductive layer 240a and a conductive layer 240b over the conductive layer 240a. After that, the insulating layer 281 is formed. Here, the conductive layer 240 is provided over the insulating layer 280 so as to have a portion overlapping with the conductive layer 220.

[0173] Here, tungsten is used as the conductive layer 240a, indium tin oxide containing silicon is used as the conductive layer 240b, and silicon oxide is used as the insulating layer 281.

[0174] Next, a mask 275 is formed on the insulating layer 281 (FIG. 7A). For example, a layered structure of SOC (Spin On Carbon), SOG (Spin On Glass) on the SOC, and resist on the SOG can be used as the mask 275. The SOC and SOG can each be formed using a coating method such as spin coating.

[0175] The SOC is a layer containing carbon. A compound containing carbon, such as a polymer containing carbon, can be used as the SOC. For example, an organic resin layer with a carbon content of 80% by weight or more can be used as the SOC. The SOC can be formed, for example, by applying a polymer containing an aromatic ring or a fused aromatic ring in its main chain. The polymer contains, for example, a hydroxyl group, a carboxyl group, or a substituted or unsubstituted aryl group in its side chain. The SOC can be formed, for example, by applying the SOC to the insulating layer 281 by spin coating, followed by heating to volatilize the solvent. Heating can be performed, for example, at 250° C. or less for 10 minutes or less.

[0176] As the SOG, for example, a polymer containing silicon and oxygen is preferably used, and a polymer containing silicon, oxygen, and carbon is more preferably used. As the SOG, for example, a layer containing polysiloxane can be used.

[0177] First, a resist is processed into a desired shape using lithography, and then the SOG is processed using the resist as a mask. Next, the SOC is processed using the SOG as a mask. It is preferable that the resist is removed during the SOC processing.

[0178] Next, etching treatment (referred to as a first etching treatment) is performed. Specifically, openings are formed in the insulating layer 281, the conductive layer 240, and the insulating layer 280 in this order. Details are described below.

[0179] An opening 290c is formed in the insulating layer 281 using the mask 275. Then, an opening 290b is formed in the conductive layer 240 using the mask 275.

[0180] In the first etching process, the mask 275 may gradually recede, widening the opening diameter. In such a case, for example, the opening diameter at the upper end of the insulating layer 281 and in the vicinity thereof may widen, causing the side surface of the insulating layer 281 to have a tapered shape.

[0181] Note that the thickness of the SOG may be reduced when the opening 290b is formed in the conductive layer 240 using the mask 275. Therefore, after the opening 290b is formed in the conductive layer 240, the mask 274 has, for example, a stacked structure of an SOC layer and an SOG layer of the SOC layer, and the thickness of the SOG layer is reduced compared to before the opening 290b is formed.

[0182] Next, an opening 290a is formed in the insulating layer 280 using the mask 275 and the conductive layer 240b as a mask (FIG. 7B).

[0183] Anisotropic etching conditions are preferably used to form the insulating layer 281, the conductive layer 240, and the opening 290 in the insulating layer 280. Dry etching allows anisotropic etching, and therefore has a high aspect ratio, and the sidewall of the opening can be perpendicular or at an angle close to perpendicular to the surface to be formed, for example, the top surface of the conductive layer 220 in this case.

[0184] When the insulating layer 281 and the insulating layer 280 are made of the above-mentioned materials, the gas used for dry etching the insulating layer 281 and the insulating layer 280 is, for example, CH ２ F ２ , CHF3, O ２ , C.F. ４ A mixed gas of Ar and Ar can be used.

[0185] When the conductive layer 240b is made of the above-mentioned material, the gas used for dry etching the conductive layer 240b is, for example, CH ４ A mixed gas of Ar and Ar can be used.

[0186] When the conductive layer 240a is made of the above-mentioned material, the gas used for dry etching the conductive layer 240a is, for example, CF ４ , Cl ２ , and O ２ A mixed gas of the above can be used.

[0187] After the opening 290a is formed, cleaning with dilute hydrofluoric acid may be performed to remove by-products that may be formed on the side surfaces of the opening 290a.

[0188] By the above process, openings can be formed in the insulating layer 281, the conductive layer 240, and the insulating layer 280 in this order.

[0189] Subsequently, if the mask 275 remains, the mask 275 is removed (FIG. 7B).

[0190] Note that when forming the opening 290a in the insulating layer 280 using the mask 275, removing the SOG at the same time simplifies the process of removing the mask 275 after the formation of the opening 290a, which is preferable. In such a case, since only the SOC needs to be removed in the process of removing the mask 275, damage to the insulating layer 281, the conductive layer 240, the insulating layer 280, and the exposed upper surface of the conductive layer 220 in the process of removing the mask 275 is likely to be reduced. By configuring the insulating layer 280 to contain silicon oxide, silicon oxynitride, or the like, and using a polymer containing silicon and oxygen as the SOG, the insulating layer 280 and the mask 275 can be removed simultaneously.

[0191] Next, an oxide semiconductor layer 230 is formed to cover the top surface of the conductive layer 220, the side surfaces of the opening 290a in the insulating layer 280, the side surfaces of the opening 290b in the conductive layer 240, the side surfaces of the opening 290c in the insulating layer 281, and the top surface of the insulating layer 281. Subsequently, a sacrificial layer 277 is formed on the oxide semiconductor layer 230 ( FIG. 8A ). The sacrificial layer 277 is provided to fill the opening 290.

[0192] The sacrificial layer 277 may be an SOC.

[0193] Next, an etching process (referred to as a second etching process) is performed. Specifically, the sacrificial layer 277 is processed so that its upper surface is positioned at a predetermined height, in this case, between the height of the upper surface of the insulating layer 281 and the height of the upper surface of the conductive layer 240 ( FIG. 8B ). The process performed here is a process of removing portions of the sacrificial layer 277 that are higher than the predetermined height. This process can be expressed as an etch-back process, a half-etching process, or the like. The etch-back process is, for example, a process of etching the upper surface substantially uniformly. The half-etching process refers to, for example, etching such that the height of the upper surface of the sacrificial layer 277 (e.g., the height relative to the upper surface of the conductive layer 220) is lowered without removing the sacrificial layer 277. Dry etching can be used to etch the sacrificial layer 277 here.

[0194] Next, an etching process (referred to as a third etching process) is performed. Specifically, the portion of the oxide semiconductor layer 230 that is not covered by the sacrificial layer 277 is removed ( FIG. 9A ). Either dry etching or wet etching may be used for etching the oxide semiconductor layer 230. When the etching process is performed, the exposed area of ​​the sacrificial layer 277 on the insulating layer 281 is removed, and the exposed area of ​​the sacrificial layer 277 is reduced. The reduction in the area changes the emission intensity of the plasma during etching. The etching status of the sacrificial layer 277 can be monitored by utilizing this change in intensity. For example, by maintaining a constant etching process time after a change in intensity is observed, the etching can be reproducible and the etching process can be stabilized.

[0195] For example, isotropic etching conditions can be used for etching the oxide semiconductor layer 230. By using isotropic etching conditions, the portion of the oxide semiconductor layer 230 that covers the top surface and the portion that covers the side surface of the insulating layer 281 can be removed at approximately the same etching rate, and film residue in the region that covers the side surface of the insulating layer 281 can be suppressed.

[0196] Alternatively, anisotropic etching conditions may be used for etching the oxide semiconductor layer 230. Alternatively, isotropic etching conditions and anisotropic etching conditions may be used in combination.

[0197] The etching conditions for the oxide semiconductor layer 230 can be appropriately selected from dry etching and wet etching.

[0198] When wet etching is used, for example, dilute hydrofluoric acid can be used as the wet etching chemical. Alternatively, for example, a solution containing acid can be used. For example, a solution containing oxalic acid can be used. Alternatively, a solution containing hydrochloric acid and sulfuric acid can be used.

[0199] Alternatively, dry etching and wet etching may be combined. For example, after a portion of the oxide semiconductor layer 230 over the insulating layer 281 is removed by dry etching, a portion of the insulating layer 281 along the side surface of the opening 290c can be removed by wet etching.

[0200] The oxide semiconductor layer 230 is provided along the sidewall of the opening 290 and the upper surface of the conductive layer 220, which is the bottom of the opening 290, and has a recess that reflects the shape of the opening 290. The sacrificial layer 277 is provided to fill the recess in the oxide semiconductor layer 230, and the portion of the oxide semiconductor layer 230 that is covered with the sacrificial layer 277 is protected by etching and is not removed. Therefore, as shown in FIG. 9A , the portion of the oxide semiconductor layer 230 above the portion where the sacrificial layer 277 is buried is removed.

[0201] However, as shown in FIG. 9A , the upper surface of the portion of the oxide semiconductor layer 230 that is provided along the opening 290c is not covered with the sacrificial layer 277, and therefore, the height may be slightly lower than the height of the upper end of the sacrificial layer 277, particularly when isotropic etching is used.

[0202] In this manner, the sacrificial layer 277 can function as a protective film or a mask in processing the oxide semiconductor layer 230. The height of the upper end of the oxide semiconductor layer 230 in the opening 290c depends on the height of the upper surface of the sacrificial layer 277.

[0203] As the height of the upper end of the oxide semiconductor layer 230 in the opening 290c increases, the area overlapping with the conductive layer 260 via the insulating layer 250 increases. A larger overlapping area increases parasitic capacitance, which may result in a decrease in the operating speed of the semiconductor device. On the other hand, if the height of the upper end of the oxide semiconductor layer 230 in the opening 290c is lower than the height of the upper surface of the oxide semiconductor layer 230 located on the conductive layer 240b, the oxide semiconductor layer 230 may be discontinuous between the opening 290c and the conductive layer 240b, which may impair electrical continuity between the oxide semiconductor layer 230 and the conductive layer 240 or increase contact resistance between the oxide semiconductor layer 230 and the conductive layer 240. Therefore, it is preferable that the height of the upper end of the oxide semiconductor layer 230 in the opening 290c be higher than the upper surface of the conductive layer 240b and lower than the height of the upper surface of the outer periphery of the opening 290c in the insulating layer 281. This improves the reliability and operating speed of the semiconductor device.

[0204] Next, an etching process (referred to as a fourth etching process) is performed. Specifically, the sacrificial layer 277 is removed (FIG. 9B). When an SOC is used as the sacrificial layer 277, the sacrificial layer 277 can be removed by, for example, an ashing process using oxygen plasma.

[0205] Next, an insulating layer 250 and a conductive layer 260 are formed in this order so as to cover the oxide semiconductor layer 230 in the opening 290, the side surface of the opening 290c of the insulating layer 281, and the top surface of the insulating layer 281 ( FIG. 9C ). Thereafter, the conductive layer 260 on the insulating layer 281 is removed by planarization treatment or the like. Note that although the conductive layer 260 is provided so as to fill the opening 290 in FIG. 9C , the conductive layer 260 may be provided along the side surface of the opening 290 and have a recess that reflects the shape of the opening 290.

[0206] Subsequently, a conductive layer 265 and an insulating layer 278 are formed in this order, thereby fabricating the structure shown in Fig. 1A. Here, in the structure example shown in Fig. 1A, the insulating layer 250 on the insulating layer 281 is removed, but the insulating layer 250 may remain on the insulating layer 281.

[0207] 10A to 11B , an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that detailed description of the method common to the above-described manufacturing methods may be omitted.

[0208] First, an insulating layer 210 is formed on a substrate. Next, a conductive layer 220 is formed on the insulating layer 210. Next, an insulating layer 280 is formed on the insulating layer 210 and the conductive layer 220.

[0209] Next, a laminated structure of a conductive layer 240a, a conductive layer 240b on the conductive layer 240a, and a sacrificial layer 276 on the conductive layer 240b is formed on the insulating layer 280. Subsequently, an insulating layer 281 is formed on the insulating layer 280 and the sacrificial layer 276 (FIG. 10A).

[0210] The sacrificial layer 276 is provided in a region where the oxide semiconductor layer 230 will be formed later. Therefore, the thickness of the sacrificial layer 276 determines the thickness of the oxide semiconductor layer 230 that will be formed later.

[0211] The sacrificial layer 276 is preferably made of a material that can be etched with a wet etching solution. Wet etching allows etching with a high selectivity, and when etching the sacrificial layer 276, the etching selectivity with respect to the conductive layer 220, the conductive layer 240, etc. is high. Here, a high etching selectivity means that the etching rate of the conductive layer 220, the conductive layer 240, etc. is lower than the etching rate of the sacrificial layer 276, and etching of the conductive layer 220, the conductive layer 240 can be suitably suppressed.

[0212] The sacrificial layer 276 may be any of the insulating layers listed above. Alternatively, the sacrificial layer 276 may be any of the metal oxides listed above. Alternatively, the sacrificial layer 276 may be a metal film or an alloy film. Alternatively, the sacrificial layer 276 may be made of a combination of two or more materials selected from these materials.

[0213] For example, the sacrificial layer 276 can be aluminum oxide.

[0214] Next, an etching process (referred to as a first etching process) is performed. Specifically, a mask is formed over the insulating layer 281, and openings are formed in the insulating layer 281, the sacrificial layer 276, and the conductive layer 240 in this order, and then an opening 290a is formed in the insulating layer 280 (FIG. 10B).

[0215] Next, an etching process (referred to as a second etching process) is performed. Specifically, the sacrificial layer 276 is removed to form a region 288. The region 288 is, for example, a void (FIG. 10C). Here, by removing the sacrificial layer 276, the upper surface of the conductive layer 240b and the lower surface of the insulating layer 281 are exposed.

[0216] The sacrificial layer 276 can be etched by, for example, wet etching. In addition, as a chemical solution for wet etching the sacrificial layer 276, a chemical solution using a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixture of these can be used.

[0217] Next, the oxide semiconductor layer 230 is formed to fill the region 288. The oxide semiconductor layer 230 is also formed to cover the top surface of the conductive layer 220, the side surface of the insulating layer 280 on the opening 290a side, the side surface of the conductive layer 240 on the opening 290b side, the side surface of the insulating layer 281 on the opening 290c side, and the top surface of the insulating layer 281 ( FIG. 11A ).

[0218] Next, an etching process (referred to as a third etching process) is performed. Specifically, a sacrificial layer 277 is formed in the opening 290, and the sacrificial layer 277 is processed by etch-back so that the height of the upper surface of the sacrificial layer 277 is lower than the height of the upper surface of the insulating layer 281.

[0219] Next, an etching process (referred to as a fourth etching process) is performed. Specifically, a part of the oxide semiconductor layer 230 is removed using the sacrificial layer 277 as a mask ( FIG. 11B ). Here, the etching process is preferably performed so that the height of the upper end of the oxide semiconductor layer 230 in the opening 290 c is higher than the upper surface of a portion of the oxide semiconductor layer 230 located on the conductive layer 240 b and lower than the height of the upper surface of the insulating layer 281 around the opening 290 c.

[0220] Next, an etching process (referred to as a fifth etching process) is performed. Specifically, the sacrificial layer 277 is removed.

[0221] Subsequently, an insulating layer 250, a conductive layer 260, a conductive layer 265, and an insulating layer 278 are formed in this order, thereby completing the semiconductor device shown in FIG. 3A.

[0222] 12A to 13B , an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Note that detailed description of the method common to the above-described manufacturing methods may be omitted.

[0223] First, an insulating layer 210 is formed on a substrate. Next, a conductive layer 220 is formed on the insulating layer 210. Next, an insulating layer 280 is formed on the insulating layer 210 and the conductive layer 220.

[0224] Next, a stacked structure of a conductive layer 240a, a conductive layer 240b on the conductive layer 240a, and a sacrificial layer 276 on the conductive layer 240b is formed on the insulating layer 280. Subsequently, an insulating layer 281 is formed on the insulating layer 280 and the sacrificial layer 276.

[0225] Next, a layer 262 is formed on the insulating layer 281 .

[0226] Next, a mask is provided on the layer 262. Subsequently, openings are provided in the layer 262 using the mask.

[0227] The layer 262 can function as a hard mask. Since the shape of the mask is less likely to change during the etching process, a change in the opening width due to the recession of the mask can be suppressed. Therefore, the sidewalls of the opening, particularly the upper end of the opening and the sidewalls in the vicinity thereof, can be made vertical or approximately vertical. For example, a metal layer can be used as the layer 262. Here, tungsten is used as an example.

[0228] Next, etching treatment (referred to as a first etching treatment) is performed. Specifically, openings 290c, 290b, and 290a are formed in the insulating layer 281, the conductive layer 240, and the insulating layer 280 in this order (FIG. 12A).

[0229] The insulating layer 281, the conductive layer 240, and the insulating layer 280 can be etched using the layer 262 as a mask.

[0230] Next, an oxide semiconductor layer 230 is formed to cover the top surface of the conductive layer 220, the side surface of the insulating layer 280 on the opening 290a side, the side surface of the conductive layer 240 on the opening 290b side, the side surface of the opening 290c of the insulating layer 281, the side surface of the opening of the layer 262, and the top surface of the layer 262. Subsequently, an insulating layer 263 is formed over the oxide semiconductor layer 230 ( FIG. 12B ).

[0231] The insulating layer 263 may be made of, for example, the inorganic insulating film described above, such as silicon nitride or silicon oxide.

[0232] Next, an etching process (referred to as a second etching process) is performed. Specifically, anisotropic etching is used to remove a portion of the insulating layer 281 located above the upper surface of the insulating layer 281, leaving only a portion facing the side surface of the opening 290 ( FIG. 12C ). This etching process causes the insulating layer 281 to face the side surface of the opening 290 with the oxide semiconductor layer 230 sandwiched therebetween. The insulating layer 263 shown in FIG. 12C can be expressed as a sidewall (or a sidewall insulating layer or a sidewall protective layer). The sidewall can function as a mask for subsequent etching of the oxide semiconductor layer 230. By making the height of the upper end of the sidewall lower than the upper surface of the insulating layer 281, the oxide semiconductor layer 230 can be processed so that the height of the upper end of the oxide semiconductor layer 230 is lower than the upper surface of the insulating layer 281. Note that, as shown in FIG. 12C , during the etching process of the insulating layer 263, a portion of the oxide semiconductor layer 230 located above the upper surface of the insulating layer 281 may be removed.

[0233] The layer 262 can function as a protective film for the insulating layer 281 when opening the insulating layer 263. Alternatively, when a material that has a high etching selectivity with respect to the insulating layer 281 is used for the insulating layer 263, the layer 262 may be removed before the formation of the insulating layer 263 in Fig. 12B. Specifically, the phrase "high etching selectivity" here means that the etching rate of the insulating layer 281 is sufficiently low under the conditions used for etching the insulating layer 263, for example.

[0234] Next, etching treatment (referred to as a third etching treatment) is performed. Specifically, a portion of the oxide semiconductor layer 230 that is not covered with the insulating layer 263 is removed ( FIG. 13A ). By this etching treatment, the oxide semiconductor layer 230 can be processed so that the height of the upper end thereof is lower than the top surface of the insulating layer 281. Furthermore, by this etching treatment, the oxide semiconductor layer 230 is preferably processed so that the height of the upper end thereof is higher than the top surface of the conductive layer 240b. For etching the oxide semiconductor layer 230, either dry etching or wet etching may be used. Alternatively, dry etching and wet etching may be combined. Here, the insulating layer 263 is formed so as to cover the side surfaces of the openings but not the bottom surfaces. Therefore, a portion of the oxide semiconductor layer 230 that covers the bottoms of the openings (here, a portion that covers the top surface of the conductive layer 220) is removed. As a result, an opening 289 that overlaps with the conductive layer 220 is formed in the oxide semiconductor layer 230. Furthermore, a recess is formed in the upper surface of the conductive layer 220 in a region overlapping with the opening 289 .

[0235] Subsequently, etching treatment (referred to as a fourth etching treatment) is performed. Specifically, the insulating layer 263 is removed. Either dry etching or wet etching may be used for the etching. Alternatively, dry etching and wet etching may be used in combination.

[0236] Next, an insulating layer 250 and a conductive layer 260 are formed ( FIG. 13B ), and the conductive layer 260 and the like on the insulating layer are removed by planarization treatment or the like. Next, a conductive layer 265 and an insulating layer 278 are formed in this order, and the semiconductor device shown in FIG. 4A can be manufactured. Note that the insulating layer 250 and the conductive layer 260 are also formed in an opening 289 in the oxide semiconductor layer 230 and in a recessed portion of the conductive layer 220 that overlaps with the opening 289.

[0237] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0238] [Oxide Semiconductor Layer 230] As described above, the oxide semiconductor layer 230 has a channel formation region. The oxide semiconductor layer 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region. The oxide semiconductor layer 230 may have a stacked structure of two or more layers.

[0239] The crystallinity of a semiconductor material used for the oxide semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because deterioration of transistor characteristics can be suppressed.

[0240] An OS transistor has an oxygen vacancy (V Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H) and generate electrons that serve as carriers. Therefore, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to be normally on. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration in the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0241] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0242] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for an oxide semiconductor layer, the off-state current of a transistor can be reduced. Because the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0243] For example, indium oxide can be used as a metal oxide for the semiconductor layer of an OS transistor.

[0244] Examples of the metal oxide that can be used for the semiconductor layer of an OS transistor include oxides containing one or more elements selected from In, Sn, Zn, Ga, Al, and Ti. In these oxides, the content of each of the elements selected from In, Sn, Zn, Ga, Al, and Ti is preferably 1 atomic % or more, for example.

[0245] Examples of the metal oxide include, in addition to the above-mentioned indium oxide, zinc oxide, tin oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as "GZO"), aluminum zinc oxide (Al-Zn oxide, also referred to as "AZO"), indium Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "IAZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0246] Specifically, the composition of the In-Zn oxide can be In:Zn=1:1 (atomic ratio) or a composition close thereto, In:Zn=2:1 (atomic ratio) or a composition close thereto, or In:Zn=4:1 (atomic ratio) or a composition close thereto, where the term "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0247] Specifically, the composition of the In-M-Zn oxide may be a metal oxide having an In:M:Zn=1:1:1 [atomic ratio] or a composition thereabout, an In:M:Zn=1:1:1.2 [atomic ratio] or a composition thereabout, an In:M:Zn=1:1:0.5 [atomic ratio] or a composition thereabout, an In:M:Zn=1:1:2 [atomic ratio] or a composition thereabout, an In:M:Zn=4:2:3 [atomic ratio] or a composition thereabout, an In:M:Zn=1:3:2 [atomic ratio] or a composition thereabout, or an In:M:Zn=1:3:4 [atomic ratio] or a composition thereabout. Alternatively, examples of a composition containing a trace amount of element M include a composition in which In:M:Zn=4:0.1:1 (atomic ratio) or a composition in the vicinity thereof, a composition in which In:M:Zn=2:0.1:1 (atomic ratio) or a composition in the vicinity thereof, or a composition in which In:M:Zn=1:0.1:1 (atomic ratio) or a composition in the vicinity thereof. Examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0248] Examples of the crystalline structure of metal oxides that function as semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline line (CAAC), nanocrystalline line (nc), cloud-aligned composite (CAC), single crystal, and polycrystalline.

[0249] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0250] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0251] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0252] For example, the oxide semiconductor layer of one embodiment of the present invention includes a crystalline metal oxide. Examples of the structure of the crystalline metal oxide include a CAAC structure, a polycrystalline (poly-crystalline) structure, and an nc structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0253] Note that the semiconductor device of this embodiment may also be applied to a transistor using another semiconductor material for a channel formation region, such as a semiconductor made of a single element or a compound semiconductor.

[0254] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0255] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned metal oxides are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0256] Indium oxide that can be used for the oxide semiconductor layer of one embodiment of the present invention will be described below.

[0257] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0258] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide and zinc oxide.

[0259] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 25A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 25B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0260] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 25B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 25A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 25A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 25A.

[0261] 25A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0262] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0263] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0264] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0265] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 25A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0266] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0267] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0268] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0269] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0270] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0271] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0272] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0273] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0274] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0275] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 25C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0276] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0277] Furthermore, as shown in FIG. 25C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0278] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0279] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0280]

[0281] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0282] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0283] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0284] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0285] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0286] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 210, insulating layer 250, insulating layer 280, insulating layer 281, insulating layer 278, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. Furthermore, an organic insulating film may be used for the insulating layer of the semiconductor device.

[0287] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. Furthermore, the equivalent oxide thickness (EOT) of the gate insulating layer can be reduced. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wirings. Therefore, materials can be selected depending on the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0288] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0289] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other examples of inorganic insulating materials with a low relative dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0290] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of a semiconductor device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 atoms can be set appropriately; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms may be set to 1:1 or close to 1:1. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to 1:1. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0291] Furthermore, examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of element M1 to the number of atoms of element M2 to the number of atoms of element M3 can be set as appropriate.

[0292] Furthermore, materials that can have ferroelectricity include SrTaO ２ N, BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Examples include:

[0293] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0294] Furthermore, as a material that can have ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used.

[0295] Metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can have ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved.

[0296] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0297] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals having an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0298] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0299] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; nitrides such as aluminum nitride and silicon nitride; or nitride oxides such as silicon nitride oxide.

[0300] Specifically, examples of materials for the insulating layer that function to suppress the permeation of impurities such as water and hydrogen, and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Also included are nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, and silicon nitride. Also included are nitride oxides such as silicon nitride oxide.

[0301] An insulating layer, such as a gate insulating layer, that is in contact with an oxide semiconductor layer or that is provided near the oxide semiconductor layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen). For example, when an insulating layer having a region containing excess oxygen is in contact with an oxide semiconductor layer or is located near the oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced. Examples of materials for an insulating layer that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0302] An insulating layer provided in contact with or near the oxide semiconductor layer is preferably a barrier insulating layer against hydrogen, which can suppress diffusion of hydrogen into the oxide semiconductor layer.

[0303] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and silicon (hafnium silicate), etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium.

[0304] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced. For example, an amorphous structure may be realized by adding silicon to the metal oxide. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate).

[0305] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0306] The insulating layer may partially include either or both of a crystalline region and a grain boundary.

[0307] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0308] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are also referred to as a property that makes it difficult for a corresponding substance to diffuse (a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. −Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0309] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0310] Examples of materials for the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0311] Since the insulating layer 210 functions as an interlayer film, it is preferable to use the above-mentioned material having a low relative dielectric constant. By using a material having a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced.

[0312] A barrier insulating layer against hydrogen is preferably used for the insulating layer 210. When the insulating layer 210 provided below the oxide semiconductor layer 230 has a barrier property against hydrogen, diffusion of hydrogen from below the transistor 200 to the oxide semiconductor layer 230 can be suppressed. For example, a silicon nitride film is preferably used as the insulating layer 210.

[0313] An insulating layer having a function of capturing or fixing hydrogen is preferably used as the insulating layer 210. When the insulating layer 210 has a function of capturing or fixing hydrogen, hydrogen in the oxide semiconductor layer 230 diffuses into the insulating layer 210 through the conductive layer 220, and the hydrogen can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced.

[0314] The concentration of impurities such as water and hydrogen in the insulating layer 210 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0315] The insulating layer 210 can have a stacked structure of two or more layers. For example, the insulating layer 210 can have a two-layer structure of a first insulating layer and a second insulating layer on the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0316] Since the insulating layer 280 functions as an interlayer film, it is preferable to use the above-mentioned material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0317] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor layer 230.

[0318] For example, an insulating layer having a region containing excess oxygen can be formed by sputtering in an oxygen-containing atmosphere. Furthermore, by using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 280 can be reduced. By depositing at least some of the layers constituting the insulating layer 280 by sputtering, oxygen can be supplied from the insulating layer 280 to the channel formation region of the oxide semiconductor layer 230, thereby reducing oxygen vacancies and V. Ｏ H can be reduced.

[0319] Note that the thickness of the insulating layer 280 on the conductive layer 220 affects the channel length of the transistor 200 , and therefore the thickness of the insulating layer 280 is set appropriately in accordance with the design value of the channel length of the transistor 200 .

[0320] The insulating layer 280b may be made of a material having a low dielectric constant, and the insulating layers 280a and 280c may be made of a barrier insulating layer against oxygen. This configuration can prevent the conductive layers 220 and 240 from being oxidized and from becoming highly resistive.

[0321] For example, it is preferable to use a silicon nitride film or an aluminum oxide film as the insulating layer 280a and the insulating layer 280c, and a silicon oxide film as the insulating layer 280b. Note that each of the insulating layer 280a and the insulating layer 280c may have a stacked structure of two or more layers.

[0322] The insulating layer 281 preferably contains a material with a low relative dielectric constant. The insulating layer 281 may be made of any material, structure, or the like that can be used for the insulating layer 280.

[0323] Alternatively, the insulating layer 281 may have a laminated structure of a material with a low relative dielectric constant and a material having a barrier property against hydrogen.

[0324] When the insulating layer 281 has a barrier property against hydrogen, diffusion of hydrogen from above the transistor 200 to the oxide semiconductor layer 230 can be suppressed.

[0325] The insulating layer 278 preferably contains a material with a low relative dielectric constant. The insulating layer 278 may be made of any material, structure, or the like that can be used for the insulating layer 280.

[0326] A barrier insulating layer against hydrogen is preferably used for the insulating layer 250. When the insulating layer 250 provided over the oxide semiconductor layer 230 has a barrier property against hydrogen, hydrogen contained in the conductive layer 260 can be prevented from diffusing into the oxide semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0327] Furthermore, since the insulating layer 250 is in contact with the oxide semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the oxide semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0328] An insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. In this way, oxygen can be supplied from the insulating layer 250 to the oxide semiconductor layer 230, and oxygen vacancies in the oxide semiconductor layer 230 can be reduced. A silicon oxide film, a silicon oxynitride film, or the like is suitable for the insulating layer 250 because it has a structure that is stable against heat.

[0329] The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed using two or more types of films. By using two or more types of films as the insulating layer 250, the insulating layer 250 can have multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the oxide semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the oxide semiconductor layer 230.

[0330] For example, the insulating layer 250 can have a two-layer structure including a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the oxide semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the oxide semiconductor layer 230 can be reduced and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0331] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the oxide semiconductor layer 230 can be reduced, and diffusion of hydrogen into the oxide semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be provided.

[0332] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the oxide semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including the third insulating layer, the first insulating layer on the third insulating layer, and the second insulating layer on the first insulating layer.

[0333] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having a barrier property against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the oxide semiconductor layer 230, oxygen can be supplied to the oxide semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the oxide semiconductor layer 230 can be suppressed.

[0334] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the oxide semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including the fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0335] An insulating layer having a barrier property against oxygen is preferably used as the fourth insulating layer. Note that the first to third insulating layers can have the same structure as the layers used in the above-described three-layer structure. The fourth insulating layer is a layer in contact with the oxide semiconductor layer 230 and the conductive layer 240. The fourth insulating layer having a barrier property against oxygen can prevent oxygen from being released from the oxide semiconductor layer 230. Furthermore, the side surfaces of the conductive layer 240 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in on-state current or a decrease in field-effect mobility of the transistor 200.

[0336] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the oxide semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the oxide semiconductor layer 230 side.

[0337] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0338] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0339] Typically, the thicknesses of the fourth insulating layer, the third insulating layer, the first insulating layer, and the second insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0340] Note that the insulating layer 250 having a four-layer structure may not include the second insulating layer. For example, an insulating layer having a barrier property against oxygen can be used as the fourth insulating layer, an insulating layer containing a material with a low dielectric constant can be used as the third insulating layer, and an insulating layer having a function of capturing or fixing hydrogen can be used as the first insulating layer. Specifically, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the oxide semiconductor layer 230 side can be used.

[0341] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, it is possible to increase productivity by successively forming two or more types of films, for example, two or more types of insulating films, using the ALD process.

[0342] [Conductive Layer] For the conductive layers (conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from tungsten, copper, aluminum, chromium, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. Alternatively, nitrides of alloys containing the above-mentioned metal elements or oxides of such alloys may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0343] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (In—Si—Sn oxide, also referred to as ITSO), indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0344] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0345] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0346] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0347] The conductive layer 220 and the conductive layer 240 are conductive layers in contact with the oxide semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 220 and the conductive layer 240.

[0348] By using a conductive material containing oxygen for the conductive layer 220, the conductive layer 220 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240, the conductive layer 240 can maintain its conductivity even if it absorbs oxygen. Furthermore, even when an insulating layer containing oxygen, such as hafnium oxide, is used for the insulating layer 210, the conductive layer 220 is preferably able to maintain its conductivity.

[0349] The conductive layers 220 and 240 can each function as wirings of the semiconductor device. Using a highly conductive material for the wirings is preferable because it can increase the speed of circuit operation of the semiconductor device.

[0350] When the conductive layer 220 and the conductive layer 240 each have a stacked structure, by using a conductive material containing oxygen for a layer in the stacked structure that has the largest contact area with the oxide semiconductor layer 230, it is possible to reduce the contact resistance between the conductive layer 220 and the oxide semiconductor layer 230 and between the conductive layer 240 and the oxide semiconductor layer 230. Furthermore, by using a material with high conductivity in combination with the above layers, it is possible to obtain a conductive layer with low contact resistance with the semiconductor layer and high conductivity.

[0351] The conductive layer 220c and the conductive layer 240b described above can be, for example, a conductive material containing oxygen, a conductive material containing nitrogen, a material containing a metal element such as titanium, tantalum, or ruthenium, etc. The conductive layer 220c and the conductive layer 240b can be, for example, a metal oxide, a metal nitride, etc.

[0352] Specific examples of metal oxides suitable for the conductive layer include indium tin oxide, indium tin oxide containing silicon, and In—Zn oxide.

[0353] For example, the conductive layers 220a, 220b, and 240a described above can be made of any of the metal elements listed above, alloys containing the metal elements listed above, or alloys combining the metal elements listed above. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, and the like can also be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide can also be used.

[0354] Examples of suitable metal elements or alloys containing metal elements for the conductive layer include tungsten, copper, aluminum, and alloys containing aluminum. Additionally, ruthenium, titanium nitride, tantalum nitride, and the like can be used.

[0355] Furthermore, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion can be used for the conductive layer 220a, and a material with high conductivity can be used for the conductive layer 220b. Specifically, titanium nitride can be used for the conductive layer 220a, and tungsten can be used for the conductive layer 220b. In this case, the titanium nitride film is in contact with the insulating layer 210. By using a material that is resistant to oxidation for the conductive layer 220a, when an oxide insulating layer is used for the insulating layer 210, excessive oxidation of the conductive layer 220 by the insulating layer 210 can be suppressed. Furthermore, by using a metal material (here, tungsten) that has higher conductivity than an oxide conductor and titanium nitride for the conductive layer 220a, the conductivity of the conductive layer 220 can be increased.

[0356] The conductive layer 260 has a region that functions as a gate wiring. The conductive layer 260 is preferably made of a highly conductive material such as tungsten. Furthermore, the conductive layer 260 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0357] The conductive layer 260 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the above-mentioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and indium tin oxide containing silicon may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0358] The conductive layer 260a described above is preferably formed under conditions that provide high coverage. The conductive layer 260a may be formed using a film that has barrier properties against oxygen, hydrogen, and the like. The conductive layer 260b described above is preferably formed using a material with high conductivity.

[0359] Specifically, for example, it is preferable to use a titanium nitride film as the conductive layer 260a and a tungsten film as the conductive layer 260b. Alternatively, it is preferable to use a tantalum nitride film as the conductive layer 260a and a copper film as the conductive layer 260b. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0360] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0361] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0362] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0363] Embodiment 2 In this embodiment, a memory device will be described. A semiconductor device according to one embodiment of the present invention can be applied to a memory device.

[0364] <Structure Example 1 of Memory Device> A structure of a memory device including a transistor and a capacitor will be described with reference to FIGS. 14A and 14B.

[0365] Fig. 14A is a plan view showing an example in which four memory cells 150 are arranged in two rows in the Y direction and two columns in the X direction. Fig. 14B is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 14A.

[0366] Each memory cell 150 has a capacitor element 100 and a transistor 200 on the capacitor element.

[0367] The memory device shown in Figures 14A and 14B has an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a plurality of memory cells 150 on the conductive layer 110, an insulating layer 180 on the conductive layer 110, an insulating layer 280, an insulating layer 281, and a conductive layer 265 on the memory cells 150.

[0368] The conductive layer 110 functions as a wiring and is shared by a plurality of memory cells 150 .

[0369] The memory cell 150 includes a capacitor 100 over a conductive layer 110 and a transistor 200 over the capacitor 100 .

[0370] The capacitor 100 includes a conductive layer 115 on the conductive layer 110, an insulating layer 130 on the conductive layer 115, and a conductive layer 120 on the insulating layer 130. The conductive layer 120 functions as one of a pair of electrodes (sometimes referred to as an upper electrode), the conductive layer 115 functions as the other of the pair of electrodes (sometimes referred to as a lower electrode), and the insulating layer 130 functions as a dielectric. In other words, the capacitor 100 constitutes a metal-insulator-metal (MIM) capacitor.

[0371] As shown in FIG. 14B , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. At least a portion of the conductive layer 115 is disposed in the opening 190. The conductive layer 115 has a region in contact with the upper surface of the conductive layer 110 in the opening 190, a region in contact with the side surface of the insulating layer 180 in the opening 190, and a region in contact with at least a portion of the upper surface of the insulating layer 180. The insulating layer 130 is disposed so that at least a portion of it is located in the opening 190. The conductive layer 120 is disposed so that at least a portion of it is located in the opening 190. As shown in FIG. 14B , the conductive layer 120 is preferably disposed so as to fill the opening 190. The films disposed inside the opening 190 are preferably formed using a method with high coverage, such as an ALD method. This improves the coverage of the films. For example, the conductive layer 115, the insulating layer 130, and the conductive layer 120 are preferably formed by an ALD method, a metal CVD method, or the like.

[0372] The capacitor 100 has a configuration in which the upper electrode and the lower electrode face each other across a dielectric not only on the bottom surface but also on the side surface of the opening 190, allowing for a larger capacitance per unit area. Therefore, the deeper the opening 190, the larger the capacitance of the capacitor 100 can be. Increasing the capacitance per unit area of ​​the capacitor 100 in this way can stabilize the read operation of the memory device. Furthermore, it is possible to promote higher integration of memory devices.

[0373] 14B shows an example in which the sidewall of the opening 190 is perpendicular to the upper surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With such a configuration, a memory device can be highly integrated.

[0374] A conductive layer 115 and an insulating layer 130 are stacked along the sidewall of the opening 190 and the upper surface of the conductive layer 110. A conductive layer 120 is provided on the insulating layer 130 so as to fill the opening 190. The capacitor element 100 having such a configuration may be called a trench capacitor or a trench capacitor.

[0375] An insulating layer 280 and an insulating layer 281 are disposed on the capacitor element 100 .

[0376] The structure of the transistor 200 described in Embodiment 1 can be applied to the transistor 200. Note that in FIG. 14B , the conductive layer 120 is used instead of the conductive layer 220 of the transistor 200 described in Embodiment 1. Note that the conductive layer 220 can be formed over the conductive layer 120 without omitting the conductive layer 220.

[0377] The transistor 200 can be described in Embodiment 1; therefore, detailed description thereof will be omitted.

[0378] As shown in FIGS. 14A and 14B , the transistor 200 is provided so as to overlap with the capacitor 100. An opening 290 in which part of the structure of the transistor 200 is provided overlaps with an opening 190 in which part of the structure of the capacitor 100 is provided. In particular, the conductive layer 120 functions as one of the source electrode and drain electrode of the transistor 200 and as the upper electrode of the capacitor 100. Therefore, the transistor 200 and the capacitor 100 share part of their structures. With this structure, the transistor 200 and the capacitor 100 can be provided without significantly increasing the occupied area in a plan view. This reduces the occupied area of ​​the memory cell 150, thereby enabling the memory cells 150 to be arranged at a high density and increasing the storage capacity of the memory device. In other words, the memory device can be highly integrated.

[0379] Furthermore, by providing the transistor 200 above the capacitor 100, the transistor 200 is not affected by heat treatment during manufacturing of the capacitor 100. Therefore, in the transistor 200, deterioration of electrical characteristics such as a change in threshold voltage and an increase in parasitic resistance, as well as an increase in variation in electrical characteristics due to the deterioration of the electrical characteristics, can be suppressed.

[0380] [Insulating Layer 130] It is preferable to use a material with a high relative dielectric constant (high-k) as the insulating layer 130. By using a material with a high relative dielectric constant as the insulating layer 130, the insulating layer 130 can be made thick enough to suppress leakage current, and the capacitance of the capacitive element 100 can be sufficiently ensured.

[0381] Furthermore, the insulating layer 130 is preferably formed by stacking insulating layers made of a material with a high dielectric constant, and preferably by using a stack structure of a material with a high dielectric constant and a material with a higher dielectric strength than the material with a high dielectric constant. For example, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, and zirconium oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating layer 130 can be formed by stacking hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By stacking insulating layers with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0382] Furthermore, a material that can have ferroelectricity may be used as the insulating layer 130. For details of the material with a high relative dielectric constant and the material that can have ferroelectricity, see the description of the first embodiment.

[0383] Metal oxides containing one or both of hafnium and zirconium can have ferroelectricity even when the thickness is as thin as a few nanometers, and are therefore preferable as the insulating layer 130. The film thickness of the insulating layer 130 is preferably 100 nm or less, more preferably 50 nm or less, even more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). Furthermore, for example, the film thickness is preferably 8 nm to 12 nm. By using a ferroelectric layer that can be thinned, the capacitor element 100 can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device.

[0384] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as the insulating layer 130. For example, when the area (occupied area) of the ferroelectric layer in a plan view is 100 μm ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor element 100 can be reduced.

[0385] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitor element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitor element 100, the memory device described in this embodiment functions as a ferroelectric memory.

[0386] [Conductive Layer 110, Conductive Layer 115, and Conductive Layer 120] The conductive layer 110, the conductive layer 115, and the conductive layer 120 can be formed using the material and the formation method of the conductive layer described in the above embodiment as appropriate.

[0387] <Configuration Example 2 of Memory Device> The configuration of a memory device including a transistor and a capacitor will be described with reference to Figures 15A to 15C. Figure 15A is a plan view of a memory device including a transistor 200, a transistor 200(2), and a capacitor 100. Figure 15B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in Figure 15A. Figure 15C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 shown in Figure 15A.

[0388] 15A to 15C includes an insulating layer 140 over a substrate (not shown) and a memory cell 151 over the insulating layer 140. The memory cell 151 includes a transistor 200 over the insulating layer 140, a capacitor 100b over the transistor 200, and a transistor 200 over the capacitor 100b. The two transistors 200 included in the memory cell 151 are stacked vertically with the capacitor 100b sandwiched between them. The transistor 200 located on the lower side is referred to as transistor 200(2). In FIGS. 15B and 15C, the conductive layer 220 and the conductive layer 240 included in the transistor 200(2) are referred to as conductive layer 220(2) and conductive layer 240(2), respectively.

[0389] The capacitor 100 b includes a conductive layer 120 , a conductive layer 115 , and an insulating layer 130 .

[0390] An insulating layer 180 is provided over the transistor 200(2). An insulating layer 130 is provided over the insulating layer 280.

[0391] The conductive layer 120 has a portion that is provided so as to be embedded in the insulating layer 180. The insulating layer 130 has a portion that is sandwiched between the conductive layer 115 and the conductive layer 120. In the capacitor 100b, the conductive layer 120 has a columnar shape, and the insulating layer 130 is provided so as to surround the conductive layer 120. The conductive layer 115 is provided so as to surround the conductive layer 120 with the insulating layer 130 sandwiched therebetween.

[0392] The conductive layer 260 of the transistor 200(2) and the conductive layer 220 of the transistor 200 are connected to each other through the conductive layer 120. The conductive layer 120 is preferably provided in contact with the top surface of the conductive layer 260 of the transistor 200(2). The conductive layer 220 of the transistor 200 is preferably provided in contact with the top surface of the conductive layer 120.

[0393] <Configuration Example 3 of Memory Device> FIG. 16 shows an example in which a plurality of memory cells are stacked in n layers (n is an integer of 3 or more) in the Z direction.

[0394] 16 has n memory layers 160. Specifically, memory layer 160[2] is provided on memory layer 160[1], and (n-2) memory layers are further provided on memory layer 160[2], with memory layer 160[n] provided on the topmost layer. The number of memory cells included in one memory layer 160 is not particularly limited, and one memory layer 160 may have two or more memory cells.

[0395] The memory layer 160 includes a plurality of memory cells 150. In FIG. 16, an insulating layer 286 is provided over the transistor 200, the insulating layer 281, and the conductive layer 265 included in the memory cell 150.

[0396] On the insulating layer 286, an upper memory layer 160 is further provided.

[0397] 16, two memory cells are connected to common wiring (conductive layer 245, conductive layer 246, conductive layer 247, conductive layer 248, etc.). The conductive layer 245, conductive layer 246, conductive layer 247, and conductive layer 248 are connected to, for example, a sense amplifier (not shown) provided below the n-layer memory layer 160.

[0398] 16, by stacking a plurality of memory cells, it is possible to integrate and arrange the cells without increasing the area occupied by the memory cell array, that is, it is possible to configure a 3D memory cell array.

[0399] 17 shows a cross-sectional structure example of a memory device. In the structure example shown in FIG. 17, a layer 168 including a transistor 200 and a memory layer 160 are stacked in this order over a layer 169 including a transistor 300.

[0400] Peripheral circuitry such as sense amplifiers may be provided in layer 169. Transistor 300 is, for example, a Si transistor.

[0401] 17 shows an example in which the transistor 300 included in the layer 169 is connected to the memory cell 150 included in the memory layer 160. The connection example shown in FIG. 17 can be applied to the case in which the transistor 300 is one of the transistors included in a sense amplifier.

[0402] 17 , by providing a layer 169 so as to overlap the memory cell 150, it is possible to shorten the wiring connecting the memory cell 150 and the layer 169. For example, it is possible to shorten the bit line connected to the sense amplifier, which reduces the bit line capacitance and enables high-speed operation of the memory device.

[0403] The transistor included in the layer 168 can be used as, for example, a transistor that forms a peripheral circuit.

[0404] The transistor included in the layer 168 can be used in combination with, for example, the transistor included in the layer 169. A CMOS circuit can be configured by combining the transistor 300 in the layer 169 as a p-channel transistor and the transistor included in the layer 168 as an n-channel transistor.

[0405] 17 can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, the transistor 300 corresponds to a transistor included in a sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to a memory cell 950.

[0406] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The semiconductor region 313, its neighboring regions, and the low-resistance regions 314a and 314b each preferably contain a silicon-based semiconductor, specifically, single-crystal silicon. Alternatively, each of the aforementioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. A configuration using silicon whose effective mass is controlled by applying stress to the crystal lattice to change the lattice spacing may also be used. Alternatively, the transistor 200 may be a high electron mobility transistor (HEMT) using, for example, gallium arsenide and aluminum gallium arsenide.

[0407] Here, in the transistor 300 shown in FIG. 17 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0408] Note that the transistor 300 illustrated in FIG. 17 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0409] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0410] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0411] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0412] A wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, in FIG. 17 , an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0413] The insulating layer 352, the insulating layer 354, and the like, which function as interlayer films, can be formed using the above-described insulating layer that can be used in a semiconductor device or a memory device.

[0414] For conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, a conductive material applicable to the conductive layer 240 can be used. A high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, is preferably used, and tungsten is preferably used. Alternatively, a low-resistance conductive material, such as aluminum or copper, is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0415] The conductive layer 240 of the transistor 200 in the memory layer 160 is connected to the low-resistance region 314b functioning as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 642, the conductive layer 644, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, the conductive layer 328, and a conductive layer provided to be embedded in the insulating layer of the layer 168.

[0416] 17 , the conductive layer 240 is located below the oxide semiconductor layer 230, and therefore, the conductive layer 240 can be easily provided so as to be in contact with the top surface of the conductive layer 643.

[0417] The conductive layer 642 is provided over the insulating layer 130 and is embedded in the insulating layer 641. The conductive layer 642 can be manufactured using the same material and process as the conductive layer 120. The conductive layer 644 is embedded in the insulating layer 180 and the insulating layer 130. The conductive layer 645 can be manufactured using the same material and process as the conductive layer 110. The conductive layer 646 is embedded in the insulating layer 648. The insulating layer 648 insulates the transistor 300 from the layer 168. An insulating layer 647 is provided over the layer 168. The conductive layer 645 is embedded in the insulating layer 647. The insulating layer 647 insulates the transistor 200 of the layer 168 from the conductive layer 110.

[0418] As described above, the memory device of this embodiment has a transistor with reduced parasitic capacitance, and therefore the operating speed can be increased. In addition, the memory device of this embodiment has a capacitor and a transistor stacked on top of each other, and therefore the area occupied by the memory cell in a plan view can be reduced, and a memory device with high integration can be realized.

[0419] <Application to Circuit Diagrams> The memory device described in this embodiment can be applied to circuit diagrams described in later embodiments, for example, the circuit diagrams shown in FIGS.

[0420] The memory device described in this embodiment can be applied to, for example, the circuit diagram shown in FIG. 19A . The memory cell 951 includes a transistor M1 and a capacitor CA. Here, by using the transistor 200 as the transistor M1 and the capacitor 100 as the capacitor CA, the configuration of the memory cell 150 shown in FIGS. 14A and 14B can be applied to FIG. 19A .

[0421] Here, the wiring BIL corresponds to the conductive layer 240, the wiring WOL corresponds to the conductive layer 260, and the wiring CAL corresponds to the conductive layer 110. The wiring BIL functions as a bit line, and the wiring WOL functions as a word line.

[0422] Here, in the transistor of one embodiment of the present invention, an insulating layer 281 is provided between the conductive layer 240 and the conductive layer 260 which function as a bit line, and an insulating layer 280 is provided between the conductive layer 220. Therefore, the wiring capacitance between the conductive layer 240 and the conductive layer 260 and the wiring capacitance between the conductive layer 240 and the conductive layer 220 can be reduced. That is, in the memory device of one embodiment of the present invention, the parasitic capacitance of the bit line can be made extremely small.

[0423] Furthermore, when a low potential signal is applied to the gate of the transistor, carriers are not induced in the semiconductor layer, and it can be said that parasitic capacitance generated between the conductive layer 260 functioning as a word line and the oxide semiconductor layer 230 is extremely small. Furthermore, when a high potential signal is applied to the gate, carriers are induced in the semiconductor layer, and significant parasitic capacitance can be generated between the conductive layer 260 and the oxide semiconductor layer 230. However, since the influence of parasitic capacitance on the word line is smaller than that on the bit line in the operation of the memory device, the memory device of one embodiment of the present invention can achieve sufficiently high operating speed by extremely reducing the parasitic capacitance of the bit line.

[0424] 19C and 19D . The memory cell 953 and the memory cell 954 each include a transistor M2, a transistor M3, and a capacitor CB. Here, by using the transistor 200 as the transistor M2, the transistor 200(2) as the transistor M3, and the capacitor CB as the capacitor CB, the configuration of the memory cell 151 shown in FIGS. 15A to 15C can be applied to FIGS. 19C and 19D .

[0425] 19C , the wiring WBL corresponds to the conductive layer 240 of the transistor 200, the wiring WOL corresponds to the conductive layer 260 of the transistor 200, the wiring CAL corresponds to the conductive layer 115, and the wiring RBL and the wiring SL correspond to one of the conductive layers 240 and 220 of the transistor 200(2), respectively. The conductive layers 240 and 220 of the transistor 200(2) are referred to as the conductive layer 240(2) and the conductive layer 220(2), respectively, in FIGS. 15B and 15C . The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL and the wiring CAL function as word lines.

[0426] In the memory device of one embodiment of the present invention, the conductive layer 240 of the transistor 200, which functions as a write bit line, has the insulating layer 281 between it and a wiring above it and the insulating layer 280 between it and a wiring below it, so that parasitic capacitance can be made extremely small. Similarly, the conductive layer 240(2) of the transistor 200(2), which functions as a read bit line, can also have extremely small parasitic capacitance.

[0427] Furthermore, the conductive layer 240 of the transistor 200 can be connected to one of the conductive layer 240 and the conductive layer 220 of the transistor 200(2) and at least one of them can be used as a wiring BIL, thereby applying the circuit diagram shown in FIG. 19D.

[0428] The circuit diagrams shown in FIGS. 19A to 19H and FIG. 20 will be described in detail later.

[0429] This embodiment mode can be combined with other embodiment modes as appropriate.

[0430] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0431] Fig. 18A is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 18A has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 18A shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0432] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 18B, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 18C, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0433] The memory cell 950 can be any of the memory devices described in Embodiment 2 (such as the memory cell 150 ).

[0434] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0435] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0436] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0437] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0438] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0439] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0440] Each circuit included in the peripheral circuit 911 can have a function of generating or outputting a fixed potential, a variable potential (for example, a pulse voltage, a pulse signal, a clock signal, or the like).

[0441] The peripheral circuits may use Si transistors or the like.

[0442] An example of the structure of a Si transistor will be described below. An element isolation layer, a semiconductor region, a low-resistance region functioning as a source region or a drain region, and the like can be provided on a single-crystal silicon substrate or an SOI substrate having single-crystal silicon. Furthermore, a gate insulating layer, a gate electrode, and the like can be provided in a region overlapping with the semiconductor layer.

[0443] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0444] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0445] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 18A, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0446] Here, V ＤＤ For example, 0.8 V can be used as V. ＨＭ For example, 1.8 V, 2.5 V, 3.3 V, etc. can be used.

[0447] When the difference between the high power supply potential and the low power supply potential applied to the word line is 3.3 V, for example, the high power supply potential can be 3.3 V and the low power supply potential can be 0 V (e.g., ground potential). Alternatively, the high power supply potential can be 2.5 V and the low power supply potential can be −0.8 V. Alternatively, the high power supply potential can be 1.8 V and the low power supply potential can be −1.5 V.

[0448] Also, in the column driver 924, V ＤＤFor example, when data is written to the memory cell 950, a higher potential (for example, 1.8 V, 2.5 V, or 3.3 V) can be used. For example, when data is written to the memory cell 950, the write speed can be improved by using a higher potential. ＤＤ For example, V ＨＭ can be used for the column driver 924. Alternatively, V ＤＤ and V ＨＭ A different high power supply potential may be used.

[0449] 19A to 19H, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0450] 19A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0451] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0452] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0453] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0454] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0455] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 19B may be used. The memory cell 952 is an example in which the memory cell 952 does not include the capacitor CA and the wiring CAL. The first terminal of the transistor M1 is in a floating state.

[0456] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0457] Note that an OS transistor is preferably used as the transistor M1. An OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0458] 19C shows an example circuit configuration of a gain cell memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and elsewhere, a memory device having a gain cell memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0459] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0460] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL and the wiring CAL function as word lines. The wiring WOL may be called a write word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.

[0461] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. At this time, a high-level potential is also applied to the wiring CAL. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and this potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential between the first and second terminals of the capacitor CB. Then, by applying a low-level potential to the wiring CAL, the gate potential of the transistor M3 decreases due to capacitive coupling of the capacitor CB, turning off the transistor M3.

[0462] Data is read by applying a high-level potential to the wiring CAL and a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0463] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 19D . The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured such that the write bit line and the read bit line operate as a single wiring BIL.

[0464] 19E is an example in which the capacitor element CB and the wiring CAL in the memory cell 953 are omitted. Also, the memory cell 956 in Fig. 19F is an example in which the capacitor element CB and the wiring CAL in the memory cell 954 are omitted. With such a configuration, the integration degree of the memory cells can be increased.

[0465] Note that at least the transistor M2 is preferably an OS transistor, and in particular, the transistors M2 and M3 are preferably OS transistors.

[0466] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0467] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, each of which uses an OS transistor as the transistor M2, are one embodiment of an NOSRAM.

[0468] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0469] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0470] 19G shows a gain cell type memory cell 957 having three transistors and one capacitor element. The memory cell 957 has transistors M4 to M6 and a capacitor element CC.

[0471] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0472] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0473] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0474] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0475] Note that at least the transistor M4 is preferably an OS transistor.

[0476] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0477] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0478] A memory cell 957b shown in FIG. 19H includes transistors M4 to M6 and does not include a capacitor CC.

[0479] A first terminal of the transistor M4 is connected to the gate of the transistor M5 and the node N, a second terminal of the transistor M4 is connected to the wiring WBL, and a gate of the transistor M4 is connected to the wiring WOL. A first terminal of the transistor M5 is connected to the wiring SL. A second terminal of the transistor M5 is connected to the first terminal of the transistor M6. A second terminal of the transistor M6 is connected to the wiring RBL, and a gate of the transistor M6 is connected to the wiring RWL.

[0480] To write data, a high-level potential is applied to the wiring WOL to turn on the transistor M4, thereby bringing the wiring WBL and the node N into electrical continuity, and charge is accumulated in the node N. After that, a low-level potential is applied to the wiring WOL to turn off the transistor M4, thereby maintaining the potential of the node N. Note that a constant potential (GND (ground potential) or low potential)) is always applied to the wiring SL.

[0481] To read data, the wiring RBL is precharged to a predetermined potential. The potential of the wiring SL is maintained constant. Furthermore, the potential of the wiring RWL is set to a high potential, and the transistor M6 is turned on, thereby bringing the wiring RWL and the second terminal of the transistor M5 into electrical continuity.

[0482] At this time, a high potential is applied to the second terminal of the transistor M5, and GND or a low potential is applied to the first terminal thereof. A potential having a magnitude corresponding to the data written to the node N is applied to the gate of the transistor M5. In other words, the type of data determines whether the transistor M5 is in an on state or an off state.

[0483] Here, when the data stored in the memory cell is "0", the difference between the gate potential and the source potential of transistor M5 is assumed to be lower than the threshold voltage of transistor M5. Also, when the data stored in the memory cell is "1", the difference between the gate potential and the source potential of transistor M5 is assumed to be higher than the threshold voltage of transistor M5. In this case, if the data stored in the memory cell is "0", transistor M5 is turned off (transistor M6 is turned on), and therefore no current flows from wiring RBL to wiring SL. On the other hand, if the data stored in the memory cell is "1", both transistors M5 and M6 are turned on, and therefore current flows from wiring RBL to wiring SL. The data stored in the memory cell can be read from the current flowing through wiring RBL or the potential of wiring RBL.

[0484] 20 shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 20 is a memory cell of an SRAM capable of backing up data.

[0485] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0486] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0487] A second terminal of the transistor MS1 is connected to the wiring VDL. A second terminal of the transistor MS2 is connected to the wiring VDL. A second terminal of the transistor MS3 is connected to the wiring GNDL. A second terminal of the transistor MS4 is connected to the wiring GNDL.

[0488] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0489] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0490] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the on / off states of the transistors M9 and M10.

[0491] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0492] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is on, a potential corresponding to information to be written is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0493] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 to MS4, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is on, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are on, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Then, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0494] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of the wiring BIL or BILB.

[0495] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, which reduces the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated.

[0496] Note that Si transistors may be used as the transistors MS1 to MS4.

[0497] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0498] 21A shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 21A can be applied to, for example, a CPU (Central Processing Unit). The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0499] The arithmetic device 960 shown in FIG. 21A has an ALU 991 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, a register 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. The substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 999 and the cache interface 989 may also be provided on separate chips.

[0500] The cache 999 is connected to a main memory provided on a separate chip via a cache interface 989. The cache interface 989 has a function of supplying part of the data held in the main memory to the cache 999. The cache interface 989 also has a function of outputting part of the data held in the cache 999 to the ALU 991, register 996, etc. via the bus interface 998.

[0501] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 989 may have a function of supplying data held in the memory array 920 to the cache 999. In this case, it is preferable that a drive circuit 910 be included as part of the cache interface 989.

[0502] It is also possible to use only the memory array 920 as a cache without providing the cache 999 .

[0503] The arithmetic device 960 shown in FIG. 21A is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 21A as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration with 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0504] An instruction input to the arithmetic unit 960 via the bus interface 998 is input to the instruction decoder 993, decoded, and then input to the ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995.

[0505] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on the decoded instructions. Specifically, the ALU controller 992 generates signals for controlling the operation of the ALU 991. Furthermore, the interrupt controller 994 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 997 generates addresses for registers 996 and reads and writes data from and to the registers 996 depending on the state of the arithmetic unit 960.

[0506] Furthermore, the timing controller 995 generates signals that control the timing of the operations of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0507] 21A, the register controller 997 selects the holding operation of the register 996 in accordance with an instruction from the ALU 991. That is, it selects whether the memory cells of the register 996 will hold data using flip-flops or using capacitors. If holding data using flip-flops is selected, a power supply potential is supplied to the memory cells in the register 996. If holding data using capacitors is selected, the data is rewritten to the capacitors, and the supply of power supply potential to the memory cells in the register 996 can be stopped.

[0508] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Figure 21B shows a perspective view of a semiconductor device 970A. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 21B.

[0509] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0510] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0511] Here, the arithmetic unit 960 does not have a cache 999, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0512] When the cache 999 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0513] The arithmetic unit is also provided with a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3. The driving circuit 910L1 is connected to a memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to a memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to a memory array 920L3 via a connection electrode 940L3.

[0514] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0515] When the memory array 920L1 is used as a cache, the drive circuit 910L1 may function as part of the cache interface 989, or may be configured so that the drive circuit 910L1 is connected to the cache interface 989. Similarly, the drive circuits 910L2 and 910L3 may also function as part of the cache interface 989, or may be configured so that they are connected thereto.

[0516] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0517] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0518] Alternatively, a layer 930 having one memory array 920 may be provided over the computing device 960 .

[0519] Furthermore, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. For example, three areas can be used as an L1 cache, an L2 cache, and an L3 cache. The size of each area can be changed depending on the situation. This can improve the efficiency of calculation processing and increase the processing speed.

[0520] Alternatively, memory arrays corresponding to each region may be stacked. For example, multiple memory arrays may be stacked in the same manner as the arithmetic unit 960, with the memory array physically closest to the arithmetic unit 960 being used as a higher-level cache and the memory array farthest from the arithmetic unit 960 being used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0521] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 22 shows a conceptual diagram illustrating the hierarchy of memory devices used in semiconductor devices. In Figure 22, the conceptual diagram illustrating the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0522] In FIG. 22 , from the top layer of the triangle, there are shown memories integrated as registers into arithmetic processing units such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), and an NPU (Neural Processing Unit), cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs (Dynamic Random Access Memory), and storage memories such as 3D NANDs and hard disks (also called HDDs: Hard Disk Drives).

[0523] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0524] Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

[0525] The memory device of one embodiment of the present invention can be used as a DRAM.

[0526] 22 illustrates only up to the L3 cache, but the cache memory is not limited to this. For example, the storage device of one embodiment of the present invention can be used as a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of the cache.

[0527] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0528] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0529] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0530] The storage device of one embodiment of the present invention can be used for the Target2 region and the Target1 region shown in Figure 22. In particular, the storage device can be suitably used for the Target1 region.

[0531] A memory device (OS memory) including an oxide semiconductor according to one embodiment of the present invention can retain data for a long time and has a high operating speed. Therefore, when used as a DRAM, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0532] Furthermore, a memory device including an oxide semiconductor according to one embodiment of the present invention has high operating speed and can be suitably used as a DRAM.

[0533] As indicated by the diagonal hatching in FIG. 22, Target1 includes a boundary area (Target1_1) between the DRAM and 3D NAND, and a boundary area (Target1_2) between the DRAM and cache (L1, L2, L3).

[0534] Furthermore, the memory device of one embodiment of the present invention can hold data for a long time, and therefore can be suitably used for Target1_1, which is an area where rewriting is relatively infrequent.

[0535] Furthermore, the memory device of one embodiment of the present invention has high operating speed and can therefore be suitably used for Target1_2, which is rewritten more frequently among Target1.

[0536] This embodiment mode can be combined with other embodiment modes as appropriate.

[0537] Embodiment 4 In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described.

[0538] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0539] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0540] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0541] [Electronic Component] FIG. 23A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 23A has semiconductor device 710 inside mold 711. FIG. 23A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0542] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0543] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0544] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0545] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0546] 23B shows a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on the interposer 731.

[0547] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0548] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0549] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0550] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0551] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0552] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0553] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the semiconductor device 710 and the height of the semiconductor device 735.

[0554] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 23B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0555] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0556] 24A shows a perspective view of a mainframe computer 5600. The mainframe computer 5600 shown in Fig. 24A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe computer 5600 may also be called a supercomputer.

[0557] The computer 5620 can have the configuration shown in the perspective view in Fig. 24B, for example. In Fig. 24B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0558] PC card 5621 shown in Figure 24C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 24C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referred to.

[0559] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0560] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0561] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0562] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0563] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0564] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0565] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0566] A semiconductor device according to one embodiment of the present invention includes an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and can be suitably used in an environment where radiation may be incident. For example, the OS transistor can be suitably used in outer space. Specifically, the OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, but the outer space described in this specification may include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0567] Fig. 24D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 24D illustrates a planet 6804 in space.

[0568] 24D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0569] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0570] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0571] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0572] The control device 6807 has a function of controlling the satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used for the control device 6807. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.

[0573] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0574] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0575] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0576] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0577] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0578] Furthermore, the semiconductor device of one embodiment of the present invention consumes less power, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0579] Fig. 24E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 24E has a plurality of servers 7001sb as hosts 7001. It also has a plurality of storage devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.

[0580] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0581] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0582] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0583] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing can be reduced and power consumption can be reduced.

[0584] Note that the semiconductor device of one embodiment of the present invention can reduce power consumption by applying it to any one or more of electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0585] Note that the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0586] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0587] ADDR: signal, BIL: wiring, BILB: wiring, BRL: wiring, BW: signal, CA: capacitance element, CAL: wiring, CB: capacitance element, CC: capacitance element, CE: signal, CLK: signal, GNDL: wiring, GW: signal, M10: transistor, RBL: wiring, RDA: signal, RWL: wiring, SL: wiring, TrP: transistor, TrQ: transistor, VDL: wiring, WAKE: signal, WBL: wiring, WDA: signal, WOL: wiring, 100: capacitance element, 100b: capacitance element, 110: conductive layer, 115: conductive layer, 120: conductive layer, 130: insulating layer, 140: insulating layer, 150: memory cell, 151: memory cell, 160: memory layer, 168: layer, 169: layer, 180: insulating layer, 190: opening, 200: transistor, 210: insulating layer, 220: conductive layer, 220a: conductive layer, 220b: conductive layer, 220c: conductive layer, 230: oxide semiconductor layer, 240: conductive layer, 240a: conductive layer, 240b: conductive layer, 245: conductive layer, 246: conductive layer, 247: conductive layer, 248: conductive layer, 250: insulating layer, 260: conductive layer, 260a: conductive layer, 260b: conductive layer, 262: layer, 263: insulating layer, 265: conductive layer, 274: mask, 275: Mask, 276: sacrificial layer, 277: sacrificial layer, 278: insulating layer, 279: portion, 280: insulating layer, 280a: insulating layer, 280b: insulating layer, 280c: insulating layer, 281: insulating layer, 286: insulating layer, 288: region, 289: opening, 290: opening, 290a: opening, 290b: opening, 290c: opening, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer , 350: insulating layer, 352: insulating layer, 354: insulating layer, 356: conductive layer, 641: insulating layer, 642: conductive layer, 643: conductive layer, 644: conductive layer, 645: conductive layer, 646: conductive layer, 647: insulating layer, 648: insulating layer, 700: electronic component, 702: printed circuit board, 704: mounting board, 710: semiconductor device, 711: mold, 712: land, 713: electrode pad, 714: wire, 715: drive circuit layer, 716: memory layer, 730: electronic component, 731: interposer, 732: package substrate, 733: electrode, 735: semiconductor device, 900: semiconductor device,910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 957b: memory cell, 958: memory cell, 960: arithmetic unit, 970A: semiconductor device, 989: cache interface, 990: substrate, 991: ALU, 992: ALU controller, 993: instruction decoder, 994: interrupt controller, 995: timing ing controller, 996: register, 997: register controller, 998: bus interface, 999: cache, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 56 30: motherboard, 5631: slot, 6800: satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network, 7010: storage system,

Claims

forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first insulating layer and the first conductive layer; forming a second conductive layer on the second insulating layer so as to have a portion overlapping with the first conductive layer; forming a third insulating layer on the second insulating layer and the second conductive layer; forming a first mask on the third insulating layer; forming an opening in the third insulating layer, the second conductive layer, and the second insulating layer, the opening reaching the first conductive layer; forming a semiconductor layer so as to cover an upper surface of the first conductive layer, a side surface of the opening of the second insulating layer, a side surface of the opening of the second conductive layer, and a side surface of the opening of the third insulating layer; forming a first layer on the semiconductor layer so as to fill the opening; removing a portion of the first layer so that the height of the upper surface of the first layer is lower than the height of the upper surface of the third insulating layer; using the first layer as a second mask to remove a portion of the semiconductor layer that is higher than the height of an upper surface of the first layer; removing the first layer; forming a fourth insulating layer in the opening so as to cover the semiconductor layer; forming a third conductive layer over the fourth insulating layer; 　 In claim 1, a method for manufacturing a semiconductor device, wherein, when removing the semiconductor layer using the first layer as the second mask, the removal is performed so that the height of an upper end of the semiconductor layer is lower than the height of an upper surface of the third insulating layer and higher than the height of an upper surface of the second conductive layer. 　 forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first insulating layer and the first conductive layer; forming a second conductive layer on the second insulating layer so as to have a portion overlapping with the first conductive layer; forming a sacrificial layer on the second conductive layer; forming a third insulating layer on the second insulating layer and the sacrificial layer; forming a first mask on the third insulating layer; forming an opening in the third insulating layer, the sacrificial layer, the second conductive layer, and the second insulating layer, the opening reaching the first conductive layer; removing the sacrificial layer to form a gap sandwiched between the second conductive layer and the third insulating layer; forming a semiconductor layer to cover an upper surface of the first conductive layer, a side surface of the opening of the second insulating layer, a side surface of the opening of the second conductive layer, and a side surface of the opening of the third insulating layer, and to fill the gap; forming a first layer on the semiconductor layer so as to fill the opening; removing a portion of the first layer so that the height of the upper surface of the first layer is lower than the height of the upper surface of the third insulating layer; using the first layer as a second mask to remove a portion of the semiconductor layer that is higher than the height of an upper surface of the first layer; removing the first layer; forming a fourth insulating layer in the opening so as to cover the semiconductor layer; forming a third conductive layer over the fourth insulating layer; 　 In claim 3, a method for manufacturing a semiconductor device, wherein, when removing the semiconductor layer using the first layer as the second mask, the removal is performed so that the height of an upper end of the semiconductor layer in the opening is lower than the height of an upper surface of the third insulating layer and higher than the height of an upper surface of a portion of the semiconductor layer located on the second conductive layer. 　 forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first insulating layer and the first conductive layer; forming a second conductive layer on the second insulating layer so as to have a portion overlapping with the first conductive layer; forming a third insulating layer on the second insulating layer and the second conductive layer; forming a third conductive layer on the third insulating layer; forming an opening in the third conductive layer, the third insulating layer, the second conductive layer, and the second insulating layer, the opening reaching the first conductive layer; forming a semiconductor layer so as to cover an upper surface of the first conductive layer, a side surface of the opening of the second insulating layer, a side surface of the opening of the second conductive layer, and a side surface of the opening of the third insulating layer; forming a fourth insulating layer to have a first portion facing a side surface of the opening of the second insulating layer with the semiconductor layer therebetween, a second portion facing a side surface of the opening of the second conductive layer with the semiconductor layer therebetween, a third portion facing a side surface of the opening of the third insulating layer with the semiconductor layer therebetween, and a fourth portion facing an upper surface of the first conductive layer with the semiconductor layer therebetween; removing a portion of the fourth insulating layer so that a height of an upper surface of the third portion of the fourth insulating layer is lower than a height of an upper surface of the third insulating layer; using the fourth insulating layer as a mask, removing a portion of the semiconductor layer that is higher than the height of an upper end of the third portion of the fourth insulating layer; removing the fourth insulating layer; forming a fifth insulating layer in the opening so as to cover the semiconductor layer; forming a fourth conductive layer on the fifth insulating layer; The method for manufacturing a semiconductor device further comprises removing the third conductive layer. 　 In claim 5, removing the portion of the fourth insulating layer includes removing the fourth portion of the fourth insulating layer; In the removal of the semiconductor layer using the fourth insulating layer as the mask, a second opening reaching the first conductive layer is formed in a portion of the semiconductor layer covering an upper surface of the first conductive layer; The method for manufacturing a semiconductor device, wherein the fifth insulating layer and the fourth conductive layer are formed to have portions located within the second opening. 　 In claim 5, a method for manufacturing a semiconductor device, wherein the removal of the semiconductor layer using the fourth insulating layer as the mask is performed so that the height of an upper end of the semiconductor layer is lower than the height of an upper surface of the third insulating layer and higher than the height of an upper surface of the second conductive layer. 　 In any one of claims 1 to 4, A method for manufacturing a semiconductor device, wherein a layer containing carbon is formed by spin coating as the first layer. 　 In any one of claims 1 to 4, forming the opening in the third insulating layer using the first mask; The method for manufacturing a semiconductor device, wherein the first mask is removed before the opening is formed in the second insulating layer. 　 In any one of claims 1 to 7, The method for manufacturing a semiconductor device, wherein the semiconductor layer contains a metal oxide. 　 In any one of claims 1 to 7, The method for manufacturing a semiconductor device, wherein the second conductive layer contains a metal oxide having conductivity.

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