Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device having a high operating speed. This semiconductor device comprises: a semiconductor layer; a first conductive layer and a second conductive layer spaced apart from each other on the semiconductor layer; a first insulating layer disposed on the first conductive layer and the second conductive layer and having a first opening; a second insulating layer having a second opening and disposed in contact with a part of the upper surface of the first conductive layer and a part of the upper surface of the second conductive layer at a position overlapping the first opening; a third insulating layer in contact with a side surface of the first conductive layer in the second opening; a fourth insulating layer in contact with a side surface of the second conductive layer in the second opening; a fifth insulating layer disposed in the first opening and in contact with a part of the upper surface of the semiconductor layer, a side surface of the third insulating layer, a side surface of the fourth insulating layer, and a part of the upper surface of the second insulating layer; and a third conductive layer disposed on the fifth insulating layer in the first opening and having a region overlapping the semiconductor layer via the fifth insulating layer.

Description

Semiconductor device and method for manufacturing the semiconductor device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, the development of semiconductor devices has progressed, and large scale integration (LSI), central processing units (CPU), memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (including at least transistors and capacitors) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] JP 2012-257187 A JP 2011-151383 A

[0009] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with high field-effect mobility. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device in which variation in electrical characteristics of transistors is small. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0012] One embodiment of the present invention includes a semiconductor layer on a substrate, a first conductive layer and a second conductive layer spaced apart from each other on the semiconductor layer, a first insulating layer disposed on the first conductive layer and the second conductive layer and having a first opening, a second insulating layer disposed in contact with a part of an upper surface of the first conductive layer and a part of an upper surface of the second conductive layer at a position overlapping with the first opening, and having a second opening overlapping with the first opening, and a side surface of the first conductive layer and a part of an upper surface of the semiconductor layer at the second opening. a third insulating layer in contact with the semiconductor layer; a fourth insulating layer in contact with a side surface of the second conductive layer and another portion of the top surface of the semiconductor layer in the second opening; a fifth insulating layer disposed in the first opening and in contact with another portion of the top surface of the semiconductor layer, the side surface of the third insulating layer, the side surface of the fourth insulating layer, and a portion of the top surface of the second insulating layer; and a third conductive layer disposed on the fifth insulating layer in the first opening and having a region overlapping with the semiconductor layer via the fifth insulating layer. The third insulating layer has a lower dielectric constant than the second insulating layer. The portion of the top surface of the semiconductor layer can be referred to as a first region or first portion of the semiconductor layer, the other portion of the top surface of the semiconductor layer can be referred to as a second region or second portion of the semiconductor layer, and the other portion of the top surface of the semiconductor layer can be referred to as a third region or third portion of the semiconductor layer.

[0013] In the above semiconductor device, it is preferable that the second insulating layer contains silicon and nitrogen, and that the third insulating layer and the fourth insulating layer each contain silicon and oxygen.

[0014] In the semiconductor device, it is preferable that the second insulating layer contains aluminum and oxygen, and the third insulating layer and the fourth insulating layer each contain silicon and nitrogen.

[0015] In the semiconductor device, it is preferable that a side surface of the second insulating layer in the second opening be aligned or substantially aligned with a side surface of the first conductive layer facing the second conductive layer.

[0016] In the above semiconductor device, the semiconductor layer preferably contains indium and oxygen, and the first conductive layer and the second conductive layer preferably contain indium, tin, and oxygen.

[0017] One embodiment of the present invention includes forming an island-shaped structure including a semiconductor layer and a first conductive layer over the semiconductor layer over a substrate, forming a first insulating layer to cover the island-shaped structure, forming a first opening in the first insulating layer that reaches the first conductive layer, forming a second insulating layer to cover the first conductive layer and the first insulating layer, forming a second opening in the second insulating layer that overlaps with a part of the first opening, removing a part of the first conductive layer that overlaps with the second opening to expose a top surface of the semiconductor layer, and removing the second conductive layer and the third conductive layer from the first conductive layer. A method for manufacturing a semiconductor device includes forming a conductive layer, forming a third insulating layer over the second insulating layer and the semiconductor layer, performing anisotropic etching to form a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer from the third insulating layer, forming a seventh insulating layer over the semiconductor layer, the second insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer, forming a fourth conductive layer on the seventh insulating layer, and exposing the top surface of the first insulating layer by chemical mechanical polishing, thereby leaving the seventh insulating layer and the fourth conductive layer in the first opening.

[0018] According to one embodiment of the present invention, a semiconductor device with high field-effect mobility can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in the electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0019] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0020] FIGS. 1A, 1B, 1C, and 1D are diagrams illustrating structural examples of semiconductor devices. FIGS. 2A, 2B, and 2C are diagrams illustrating structural examples of semiconductor devices. FIGS. 3A, 3B, and 3C are diagrams illustrating structural examples of semiconductor devices. FIGS. 4A, 4B, 4C, and 4D are diagrams illustrating structural examples of semiconductor devices. FIG. 5 is a diagram illustrating a structural example of a semiconductor device. FIGS. 6A, 6B, 6C, and 6D are diagrams illustrating structural examples of semiconductor devices. FIG. 7 is a diagram illustrating a structural example of a semiconductor device. FIGS. 8A, 8B, 8C, and 8D are diagrams illustrating structural examples of semiconductor devices. FIG. 9 is a diagram illustrating a structural example of a semiconductor device. FIGS. 10A and 10B are diagrams illustrating structural examples of semiconductor devices. FIGS. 11A, 11B, and 11C are diagrams illustrating structural examples of semiconductor devices. FIGS. 12A, 12B, 12C, and 12D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13A, 13B, 13C, and 13D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14A, 14B, 14C, and 14D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15A, 15B, 15C, and 15D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16A, 16B, 16C, and 16D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17A, 17B, 17C, and 17D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 18A, 18B, 18C, and 18D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 19A, 19B, 19C, and 19D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 20A, 20B, 20C, and 20D are diagrams illustrating an example of a method for manufacturing a semiconductor device. 21A, 21B, 21C, and 21D are diagrams illustrating an example of a method for manufacturing a semiconductor device. 22A, 22B, 22C, and 22D are diagrams illustrating an example of a method for manufacturing a semiconductor device. 23A and 23B are diagrams illustrating carrier concentration dependence of Hall mobility. 23C is a cross-sectional view illustrating an indium oxide film. 24 is a block diagram illustrating an example of a configuration of a semiconductor device. 25A, 25B, 25C, 25D, 25E, 25F, and 25G are diagrams illustrating an example of a circuit configuration of a memory cell.FIG. 26 is a cross-sectional view showing an example of a semiconductor device. FIGS. 27A and 27B are perspective views illustrating a configuration example of a semiconductor device. FIG. 28 is a cross-sectional view showing an example of a semiconductor device. FIG. 29 is a block diagram illustrating a CPU. FIGS. 30A and 30B are perspective views of a semiconductor device. FIGS. 31A and 31B are perspective views of a semiconductor device. FIG. 32 is a conceptual diagram illustrating the hierarchy of a memory device. FIGS. 33A and 33B are diagrams illustrating an example of electronic components. FIGS. 34A, 34B, and 34C are diagrams illustrating an example of a mainframe computer. FIG. 34D is a diagram illustrating an example of space equipment. FIG. 34E is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 35A1, 35A2, 35B1, 35B2, 35C1, and 35C2 are cross-sectional views of transistors according to the examples. FIG. 36 shows calculation results for the cutoff frequencies of the transistors. 37A1, 37A2, 37B1, 37B2, 37C1, and 37C2 are cross-sectional views of transistors according to examples. Fig. 38 shows the calculation results of the cutoff frequencies of the transistors.

[0021] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0022] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0023] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0024] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (for example, the order of processes or the order of stacking). Furthermore, the ordinal numbers assigned to components in one part of this specification may not match the ordinal numbers assigned to the same components in other parts of this specification or in the claims.

[0025] The terms "film" and "layer" can be interchanged in some cases or depending on the situation. For example, the term "conductive layer" can be interchanged with the term "conductive film." The term "insulating film" can be interchanged with the term "insulating layer." The term "semiconductor film" can be interchanged with the term "semiconductor layer." The term "conductor" can be interchanged with the term "conductive layer" or the term "conductive film" in some cases or depending on the situation. The term "insulator" can be interchanged with the term "insulating layer" or the term "insulating film" in some cases or depending on the situation. The term "semiconductor" can be interchanged with the term "semiconductor layer" or the term "semiconductor film" in some cases or depending on the situation.

[0026] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0027] The openings include, for example, grooves, slits, etc. Furthermore, the area in which the openings are formed may be referred to as an opening portion.

[0028] Although the drawings used in this embodiment show the case where the sidewall of the opening (the side surface of the structure in the opening) is perpendicular or approximately perpendicular to the substrate surface or the surface on which the structure is formed, it may have a tapered shape.

[0029] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, the angle between the inclined side surface and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily need to be completely flat, but may be substantially planar with a slight curvature or a substantially planar with a slight unevenness.

[0030] In this specification, "having the same or substantially the same height" refers to a configuration in which the heights from a reference surface (e.g., a flat surface such as a substrate surface) are the same or substantially the same in cross-sectional view. For example, in the case of having two layers (here, layer A and layer B) with different heights relative to the reference surface, the difference in height between the top surface of layer A and the top surface of layer B is 10 nm or less, and this is also referred to as "having the same or substantially the same height."

[0031] In this specification, the phrase "side edges that coincide or substantially coincide" refers to a state in which at least a portion of the contours of the stacked layers overlap in a planar view. For example, in the case of two stacked layers (here, Layer A and Layer B), the phrase "side edges that coincide or substantially coincide" also refers to a state in which the shortest distance from the side edge of Layer A to the side edge of Layer B in a planar view is 10 nm or less.

[0032] Embodiment 1 In this embodiment, a semiconductor device including an oxide semiconductor and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1A to 22D.

[0033] <Configuration Example of Semiconductor Device> A configuration example of a semiconductor device will be described with reference to FIGS. 1A to 3C. FIGS. 1A to 1D are plan views or cross-sectional views of a semiconductor device including a transistor 200. FIG. 1A is a plan view of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed dotted line A1-A2 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed dotted line A3-A4 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed dotted line A5-A6 in FIG. 1A and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted in the plan view of FIG. 1A for clarity. Some elements may also be omitted in the subsequent plan views. FIGS. 2A and 2B show enlarged cross-sectional views of the transistor 200 in the channel length direction.

[0034] The transistor 200 includes a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a semiconductor layer 230 on the insulating layer 224, conductive layers 242a and 242b spaced apart from each other on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0035] In the transistor 200, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating layer (which can also be referred to as an upper gate insulating layer or a top gate insulating layer). The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode), and the insulating layers 224, 222, and 221 each function as a second gate insulating layer (which can also be referred to as a lower gate insulating layer or a bottom gate insulating layer). The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0036] The semiconductor layer 230 has a channel formation region and a source region and a drain region sandwiching the channel formation region in the transistor 200. At least a part of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0037] A metal oxide functioning as a semiconductor (hereinafter also referred to as an oxide semiconductor) can be used for the semiconductor layer 230. In this case, the transistor 200 can be said to be an OS transistor.

[0038] For example, an oxide containing indium is preferably used for the semiconductor layer 230, and indium oxide (also referred to as indium oxide) is particularly preferably used. The band gap of an oxide containing indium is 2.0 eV or more, or 2.5 eV or more. By using a metal oxide having a wider band gap than silicon for the semiconductor layer 230, the off-state current of the transistor 200 can be reduced. Because the off-state current of an OS transistor is small, the power consumption of the semiconductor device can be sufficiently reduced. Furthermore, because the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0039] For indium oxide that can be used for the semiconductor layer 230, refer to the description in Embodiment 2. Here, detailed description is omitted.

[0040] An OS transistor has an oxygen vacancy (V Ｏ If there are impurities and oxygen vacancies, the electrical characteristics may be easily changed and reliability may be reduced. ＯH) may generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region of the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0041] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance compared to a channel formation region, and the source and drain regions of the OS transistor preferably have a high carrier concentration and low resistance due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0042] 1C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the semiconductor layer 230 and the top surface of the semiconductor layer 230. That is, the end of the side surface and the end of the top surface may be curved. By adopting such a shape, it is possible to suppress the concentration of an electric field between the side surface and the top surface, thereby suppressing fluctuations in the transistor characteristics.

[0043] FIG. 1B and other figures show an example in which the semiconductor layer 230 has a single-layer structure. The semiconductor layer 230 can have a stacked structure of two or more layers. FIG. 2B shows a configuration in which the semiconductor layer 230 has a two-layer structure including a semiconductor layer 230_1 and a semiconductor layer 230_2 on the semiconductor layer 230_1. Indium oxide can be used for the semiconductor layer 230_2, and a metal oxide other than indium oxide, as described in the "Semiconductor Layer" section below, can be used for the semiconductor layer 230_1. Specifically, a metal oxide containing indium, gallium, and zinc can be used for the semiconductor layer 230_1. By providing the semiconductor layer 230_1 below the semiconductor layer 230_2, diffusion of impurities from a structure formed below the semiconductor layer 230_1 to the semiconductor layer 230_2 can be suppressed. Furthermore, the semiconductor layer 230_1 can be used as a seed or nucleus to enhance the crystallinity of the semiconductor layer 230_2.

[0044] An insulating layer 275 is provided over the conductive layer 242a and the conductive layer 242b, and an insulating layer 280 is provided over the insulating layer 275. The top surface of the insulating layer 280 may be planarized. An opening 289 reaching the insulating layer 222 and the semiconductor layer 230 is formed in the insulating layer 280 and the insulating layer 275. The opening 289 has a portion overlapping with a part of the conductive layer 242a and a portion overlapping with a part of the conductive layer 242b. In other words, a part of the conductive layer 242a and a part of the conductive layer 242b are formed to protrude into the opening 289.

[0045] The sidewall of the opening 289 may be perpendicular or approximately perpendicular to the upper surface of the insulating layer 222, or may have a tapered shape. By making the sidewall of the opening 289 tapered, the coverage of the insulating layer 250 and the like provided in the opening 289 can be improved, and defects such as voids can be reduced.

[0046] An insulating layer 255 is provided in contact with the side wall of the opening 289. As shown in FIG. 2A , an opening 290 is formed in the insulating layer 255 at a position overlapping the opening 289, and the opening 290 overlaps the region between the conductive layer 242a and the conductive layer 242b. The insulating layer 255 is in contact with the side surface of the insulating layer 280, the side surface of the insulating layer 275, and the top surface of the insulating layer 222 at the opening 289. The insulating layer 255 is in contact with a portion of the top surface of the conductive layer 242a and a portion of the top surface of the conductive layer 242b at the positions overlapping the opening 289. In a plan view, the side surfaces of the conductive layer 242a and the conductive layer 242b are aligned or approximately aligned with the side surfaces of the insulating layer 255 at the positions overlapping the opening 289.

[0047] Insulating layers 256a and 256b are provided at positions overlapping with the opening 290, and an insulating layer 256c is provided in the opening 289. In the opening 290, the insulating layer 256a is in contact with the side surface of the insulating layer 255 facing the conductive layer 242a, the side surface of the conductive layer 242a, and part of the top surface of the semiconductor layer 230, and the insulating layer 256b is in contact with the side surface of the insulating layer 255 facing the conductive layer 242b, the side surface of the conductive layer 242b, and another part of the top surface of the semiconductor layer 230. In the opening 289, the insulating layer 256c is in contact with the side surface of the insulating layer 255 and part of the top surface of the insulating layer 255. Note that the insulating layers 256a, 256b, and 256c may be collectively referred to as insulating layers 256.

[0048] The insulating layer 250 and the conductive layer 260 are disposed in the openings 289 and 290. In the openings 289 and 290, the insulating layer 250 contacts the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface of the semiconductor layer 230, another portion of the top surface of the semiconductor layer 230, the side surface of the insulating layer 256a, the side surface of the insulating layer 256b, another portion of the top surface of the insulating layer 255, and the side surface of the insulating layer 256c. The conductive layer 260 covers the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface of the semiconductor layer 230, and the top surface of the semiconductor layer 230 via the insulating layer 250. The height of the top surface of the conductive layer 260 is equal to or approximately equal to the height of the top end of the insulating layer 250, the height of the top end of the insulating layer 255, the height of the top end of the insulating layer 256c, and the height of the top surface of the insulating layer 280, respectively.

[0049] Note that a portion of the top surface of the semiconductor layer 230 in the opening 290 can be referred to as a first region or a first portion, another portion of the top surface of the semiconductor layer 230 in the opening 290 can be referred to as a second region or a second portion, and another portion of the top surface of the semiconductor layer 230 in the opening 290 can be referred to as a third region or a third portion. In this case, the portion of the semiconductor layer 230 overlapping with the opening 290 has the third portion, and the first portion and the second portion provided to sandwich the third portion. The first portion is in contact with the insulating layer 256a, the second portion is in contact with the insulating layer 256b, and the third portion is in contact with the insulating layer 250.

[0050] The insulating layer 250 can be made of an insulating material described in the section [Insulating Layer] below.

[0051] FIG. 1B and other figures show an example in which the insulating layer 250 has a single-layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 into two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0052] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value) can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.

[0053] The insulating layer 250 can have, for example, a four-layer structure in which an aluminum oxide film, a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the aluminum oxide film, the hafnium oxide film, the silicon oxide film, and the silicon nitride film are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. The insulating layer 250 can have, for example, a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the aluminum oxide film, the silicon oxide film, the hafnium oxide film, and the silicon nitride film are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With this structure, excess oxygen in the semiconductor layer 230 can be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

[0054] In addition, in forming the insulating layer 250 having a stacked structure of multiple insulating films, it is preferable to use an atomic layer deposition (ALD) process two or more times. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0055] 1A and 1C, the conductive layer 260 is preferably provided so as to extend in the channel width direction. With this configuration, when a plurality of transistors are provided, the conductive layer 260 functions as wiring.

[0056] The conductive layer 260 can be formed using a conductive material described in the section "Conductive Layer" below. The conductive layer 260 is preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 260 may have a stacked structure. For example, the conductive layer 260 can have a stacked structure of a titanium nitride film and a tungsten film over the titanium nitride film.

[0057] As shown in FIG. 2A , in a cross-sectional view of the transistor 200 in the channel length direction, the shortest distance between the side surfaces of the insulating layer 280 in the opening 289 is defined as distance L1. Distance L1 can also be considered the width of the opening 289. Distance L2 can also be considered the shortest distance between the conductive layer 242a and the conductive layer 242b. In the configuration shown in FIG. 2A , distance L2 can also be considered the width of the opening 290. Furthermore, since the conductive layer 242a and the conductive layer 242b function as a source electrode and a drain electrode, respectively, distance L2 can also be considered the channel length of the transistor 200. Distance L2 is smaller than distance L1. This configuration can further shorten the distance between the source and drain, thereby shortening the channel length accordingly. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, miniaturization of the semiconductor device can provide a semiconductor device with improved operating speed.

[0058] 2A , the width of the conductive layer 260 located between the conductive layer 242a and the conductive layer 242b is a distance L3. The distance L3 can also be referred to as the gate length of the transistor 200. When the opening 290 is formed by photolithography, the width of the opening 290 is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in the transistor included in the semiconductor device of one embodiment of the present invention, by providing the insulating layers 256a and 256b in the opening 290, an extremely miniaturized transistor (a transistor with a short gate length) can be manufactured. For example, the transistor 200 can be manufactured with a gate length of 1 nm to 30 nm, 2 nm to 15 nm, 3 nm to 15 nm, or 5 nm to 15 nm.

[0059] It is preferable that the insulating layer 255 and the insulating layer 256 have a large difference in etching rate when the insulating layer 256 is etched. The etching rate of the insulating layer 256 is preferably higher than the etching rate of the insulating layer 255. Therefore, it is preferable that the insulating layer 255 and the insulating layer 256 be made of materials that differ in at least one of film formation conditions, constituent elements, composition, and crystallinity.

[0060] As an example of a combination of the insulating layer 255 and the insulating layer 256, it is preferable to use aluminum oxide or hafnium oxide for one of the insulating layer 255 and the insulating layer 256, and silicon nitride for the other of the insulating layer 255 and the insulating layer 256. As another example of a combination of the insulating layer 255 and the insulating layer 256, it is preferable to use silicon oxide for one of the insulating layer 255 and the insulating layer 256, and silicon nitride for the other of the insulating layer 255 and the insulating layer 256.

[0061] An insulating layer 256a is disposed between the conductive layer 242a and a portion of the conductive layer 260 located between the conductive layer 242a and the conductive layer 242b. Similarly, an insulating layer 256b is disposed between the conductive layer 242b and the portion. Therefore, by using a material having a lower dielectric constant than the insulating layer 255 as the insulating layer 256, the parasitic capacitance between the gate electrode and the source electrode and the parasitic capacitance between the gate electrode and the drain electrode can be reduced. Therefore, a transistor with high frequency characteristics can be obtained, and the semiconductor device can operate at high speed. For example, aluminum oxide or hafnium oxide can be used as the insulating layer 255, and silicon nitride can be used as the insulating layer 256. Alternatively, for example, silicon nitride can be used as the insulating layer 255, and silicon oxide can be used as the insulating layer 256.

[0062] For example, silicon nitride can be used for the insulating layer 255, and aluminum oxide or hafnium oxide can be used for the insulating layer 256. Silicon nitride has a barrier property against hydrogen and can therefore prevent excessive diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230. Hafnium oxide has a function of capturing or fixing hydrogen, and therefore can cause the insulating layer 256, which is provided inside the insulating layer 255, to capture or fix hydrogen contained in the insulating layer 250 or the like. This can reduce excess hydrogen in the semiconductor layer 230 and its vicinity. Aluminum oxide has a barrier property against oxygen and can therefore control the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230 through the insulating layer 250. By adjusting the thickness of the insulating layer 255, a suitable amount of oxygen can be supplied to the insulating layer 280. Therefore, a highly reliable transistor 200 can be realized.

[0063] Note that the insulating layers 255 and 256 may use materials with a small difference in etching rate. For example, this may be the case when the parasitic capacitance between the gate electrode and the source electrode and the parasitic capacitance between the gate electrode and the source electrode are small, and the gate length is shortened. In this case, the insulating layers 255 and 256 may use materials with the same film formation conditions, constituent elements, composition, and / or crystallinity. By using materials with a small difference in etching rate between the insulating layers 255 and 256, the width of the opening 290 becomes larger than the distance L2. Furthermore, a portion of the upper surface of the portion of the conductive layer 242a protruding into the opening 289 contacts the insulating layer 250 (see FIG. 2C ).

[0064] An insulating layer 216 is provided in contact with a lower surface of the insulating layer 221. The upper surface of the insulating layer 216 may be planarized. The insulating layer 216 functions as an interlayer film.

[0065] The conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. The conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. As shown in FIGS. 1A and 1C , the conductive layer 205 is preferably provided so as to extend in the channel width direction. With this structure, when a plurality of transistors are provided, the conductive layer 205 functions as a wiring.

[0066] The threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V, compared to when no negative potential is applied.

[0067] The conductive layer 205 can be formed using a conductive material described in the section "Conductive Layer" below. The conductive layer 205 is preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layer 205 may have a stacked structure. For example, the conductive layer 205 can have a stacked structure of a titanium nitride film in contact with the sidewall of the opening in the insulating layer 216 and a tungsten film on the titanium nitride film.

[0068] The insulating layer 224 is preferably made of an insulating material that releases oxygen when heat is applied. When heat is applied during the manufacturing process of the semiconductor device, the insulating layer 224 releases oxygen, and the oxygen can be supplied to the semiconductor layer 230. By supplying oxygen to the semiconductor layer 230, particularly to the channel formation region, oxygen vacancies or V Ｏ H can be reduced. Therefore, a transistor with good electrical characteristics and high reliability can be obtained. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0069] Similarly to the semiconductor layer 230, the insulating layer 224 is preferably processed into an island shape. Thus, when a plurality of transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. This allows the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 to be approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed. Furthermore, by processing the insulating layer 224 into an island shape, at least a portion of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see FIG. 1C ). This allows the conductive layer 260 to be provided facing the upper surface and side surfaces of the semiconductor layer 230, allowing the electric field of the conductive layer 260 to act on the upper surface and side surfaces of the semiconductor layer 230.

[0070] However, the insulating layer 224 does not necessarily have to be processed into an island shape. For example, the insulating layer 224 can have a convex portion at a position overlapping with the semiconductor layer 230. In this case, the thickness of the insulating layer 224 in a region not overlapping with the semiconductor layer 230 is thinner than the thickness of the region overlapping with the semiconductor layer 230. When multiple transistors are provided on the same substrate, forming the insulating layer 224 in this manner allows the semiconductor layer 230 of each transistor to be formed on the same insulating layer 224. This reduces variation in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variation in the electrical characteristics of each transistor can be reduced. Note that the insulating layer 224 having a convex portion may have an opening in a region that does not overlap with the semiconductor layer 230 and overlaps with the insulating layer 250, or may not have such an opening.

[0071] The conductive layers 242a and 242b can be formed using the conductive materials described in the section "Conductive Layer" below. In particular, it is preferable to use a conductive material that is resistant to oxidation, a material that maintains its conductivity even when absorbing oxygen, or a conductive material that has a function of suppressing oxygen diffusion for the conductive layers 242a and 242b. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen (also referred to as an oxide conductor). This can suppress a decrease in the conductivity of the conductive layers 242a and 242b.

[0072] It is particularly preferable to use an oxide conductor for the conductive layer 242a and the conductive layer 242b. For example, it is particularly preferable to use indium tin oxide (In-Sn oxide, also referred to as ITO), ITO containing silicon (In-Sn-Si oxide, also referred to as ITSO), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium titanium oxide (In-Ti oxide), or the like. These materials are preferable because they are materials that can easily maintain conductivity even after absorbing oxygen, compared to materials composed of metal elements (also referred to as metal materials). Furthermore, these materials are preferable because they can reduce the contact resistance between the conductive layer 242a and the semiconductor layer 230 and the contact resistance between the conductive layer 242b and the semiconductor layer 230.

[0073] Furthermore, when an oxide conductor is used for the conductive layers 242a and 242b, the conductive layer 242a may function as one of the source and drain regions, and the conductive layer 242b may function as the other of the source and drain regions. This allows the semiconductor layer 230 to be i-type (intrinsic) or substantially i-type. In other words, it is not necessary to separately form an i-type (intrinsic) or substantially i-type region and a low-resistance n-type region in the semiconductor layer 230. Therefore, even when the distance between the conductive layer 242a and the conductive layer 242b is short, a channel formation region can be provided, and a transistor exhibiting favorable electrical characteristics can be obtained. Therefore, miniaturization or high integration of a semiconductor device can be achieved.

[0074] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. In this case, the above-described conductive material may be used for the first conductive layer in contact with the semiconductor layer 230, and a conductive material with higher conductivity may be used for the second conductive layer provided over the first conductive layer. For example, ITO or ITSO may be used for the first conductive layer, and tungsten may be used for the second conductive layer. This can increase the conductivity of the conductive layers 242a and 242b.

[0075] The insulating layer 280 is preferably made of an insulating material that releases oxygen when heat is applied. When heat is applied during the manufacturing process of the semiconductor device, the insulating layer 280 releases oxygen, and the oxygen can be supplied to the semiconductor layer 230 through the insulating layer 250. By supplying oxygen to the semiconductor layer 230, particularly to the channel formation region, oxygen vacancies or V Ｏ H can be reduced. Therefore, a highly reliable transistor can be obtained that exhibits favorable electrical characteristics.

[0076] Since the insulating layer 280 functions as an interlayer film, it is preferable to use a material with a low dielectric constant. By using a material with a low dielectric constant for the interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. In addition, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulating layer 280. This makes it possible to suppress the intrusion of impurities such as hydrogen or water into the channel formation region of the semiconductor layer 230. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 280.

[0077] An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the top end of the insulating layer 250, the top end of the insulating layer 255, the top end of the insulating layer 256c, and the top surface of the conductive layer 260, an insulating layer 283 is provided over the insulating layer 282, and an insulating layer 285 is provided over the insulating layer 283. In addition, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0078] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0079] An insulator having a function of suppressing diffusion of hydrogen is preferably used for the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283. For example, silicon nitride, which has a higher hydrogen barrier property, may be used for the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283.

[0080] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide can be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high dielectric constant (high-k) material, is preferably used for the insulating layer 222, which functions as the second gate insulating layer.

[0081] By providing the insulating layer 212 having a function of suppressing hydrogen diffusion under the transistor 200, it is possible to suppress diffusion of hydrogen from layers below the transistor 200. Furthermore, by providing the insulating layer 214 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This makes it possible to reduce excess hydrogen in the semiconductor layer 230 and its vicinity.

[0082] Furthermore, by providing the insulating layer 221 having a function of suppressing hydrogen diffusion under the semiconductor layer 230, it is possible to suppress diffusion of hydrogen from a layer below the semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. This makes it possible to reduce excess hydrogen in the semiconductor layer 230 and its vicinity.

[0083] Furthermore, by providing an insulating layer 275 having the function of suppressing the diffusion of hydrogen so as to cover the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc.

[0084] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200, it is possible to suppress diffusion of hydrogen from above the transistor 200. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. This makes it possible to reduce excess hydrogen in the semiconductor layer 230 and its vicinity.

[0085] In this manner, by using a structure in which the top and bottom of the transistor 200 are surrounded by barrier insulating layers against hydrogen, diffusion of hydrogen into the oxide semiconductor is suppressed, and the V Ｏ H can be reduced. As a result, the electrical characteristics and reliability of the transistor 200 can be improved.

[0086] Note that when the hydrogen concentration in the insulating layer 280 is low, a structure without the insulating layer 275 can be used (see FIG. 3A ). In this structure, the insulating layer 280 is in contact with the conductive layers 242a and 242b. Note that by using an oxide conductor for the conductive layers 242a and 242b, the conductive layers 242a and 242b can be in contact with the insulating layer 280 containing oxygen and maintain conductivity even when they absorb oxygen.

[0087] The insulating layer 282 is preferably formed by a sputtering method in an atmosphere containing oxygen gas, whereby oxygen can be added to the insulating layer 280.

[0088] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower dielectric constant than the insulating layer 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0089] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, which will be described later in the section [Insulating Layer]. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing excess oxygen.

[0090] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layer 240a is provided in the openings. Openings reaching the conductive layer 242b are also formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layer 240b is provided in the openings. The heights of the upper surfaces of the conductive layers 240a and 240b are the same or substantially the same as the height of the upper surface of the insulating layer 285. The lower portion of the conductive layer 240a may be formed so as to be embedded in the conductive layer 242a. Similarly, the lower portion of the conductive layer 240b may be formed so as to be embedded in the conductive layer 242b.

[0091] The conductive layer 240a and the conductive layer 240b function as vias that connect a wiring or the like provided over the transistor 200 to the source or drain of the transistor 200. The conductive layer 240a and the conductive layer 240b can be formed using a conductive material described in the below-described [Conductive Layer] section. The conductive layer 240a and the conductive layer 240b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example. The conductive layer 240a and the conductive layer 240b may have a stacked structure. For example, a stacked structure of a titanium nitride film and a tungsten film over the titanium nitride film can be used.

[0092] An insulating layer can be provided between the sidewall of the opening of the insulating layer 280 or the like and the conductive layer 240a. A barrier insulating layer applicable to the insulating layer 275 or the like can be used as the insulating layer. For example, silicon nitride can be used as the insulating layer. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 or the like from being mixed into the semiconductor layer 230 through the conductive layer 240a. Furthermore, it can prevent oxygen contained in the insulating layer 280 from being absorbed by the conductive layer 240a. Note that the insulating layer can be provided between the sidewall of the opening of the insulating layer 280 or the like and the conductive layer 240b.

[0093] The insulating layer may have a stacked structure. In this case, it is preferable that a first insulating layer in contact with the side wall of the opening of the insulating layer 280 or the like and a second insulating layer on the inner side thereof are formed by combining a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0094] Although FIG. 1B shows a configuration in which the insulating layer 255 is provided only in the opening 289, the present invention is not limited to this. The insulating layer 255 may have a portion located outside the opening 289. In FIG. 3B, the insulating layer 255 contacts the upper surface of the insulating layer 280 outside the opening 289. Furthermore, the insulating layer 255 is located between the insulating layer 280 and the insulating layer 282 outside the opening 289. With this configuration, oxygen is added to the insulating layer 280 through the insulating layer 255, so the amount of oxygen added to the insulating layer 280 can be controlled. By adjusting the film thickness of the insulating layer 255, a suitable amount of oxygen can be supplied to the insulating layer 280.

[0095] FIG. 1B illustrates a configuration in which the top surface of the semiconductor layer 230 is flat. Note that, as shown in FIG. 3C , a recess may be formed in a portion of the semiconductor layer 230 that overlaps with the opening 290. In this case, the insulating layer 256a contacts a sidewall and a portion of the bottom of the recess, the insulating layer 256b contacts another sidewall and another portion of the bottom of the recess, and the insulating layer 250 contacts another portion of the bottom of the recess. The recess in the semiconductor layer 230 allows the channel length to be effectively longer than the channel length in a planar view of the transistor. This allows the effective channel length (also referred to as the effective channel length) to be longer while maintaining a short distance between the source and drain. Therefore, the short channel effect can be reduced, and a semiconductor device with excellent electrical characteristics can be provided. Furthermore, a semiconductor device that allows miniaturization or high integration can be provided.

[0096] 1A to 1D show a cross-sectional view of the transistor 200 in which the insulating layer 255 has a portion that extends along the sidewall of the opening 289 and a portion that extends along the top surface of the conductive layer 242a, in other words, a configuration in which the insulating layer 255 has an L-shape. However, the present invention is not limited to this. For example, the insulating layer 255 may be configured to extend along the sidewall of the opening 289, in other words, the insulating layer 255 may be formed in a sidewall shape in contact with the sidewall of the opening 289.

[0097] Modifications of the semiconductor device described in <Configuration Example of Semiconductor Device> will be described with reference to Figures 4A to 5. Figure 4A is a plan view of a semiconductor device including a transistor 200, and corresponds to the plan view shown in Figure 1A. Figures 4B to 4D are cross-sectional views of the semiconductor device, and correspond to the cross-sectional views shown in Figures 1B to 1D, respectively. Figure 5 is an enlarged cross-sectional view of the transistor 200 in the channel length direction, and corresponds to the enlarged cross-sectional view shown in Figure 4B.

[0098] 4A to 4D is different from the transistor 200 shown in FIGS. 1A to 1D mainly in that the insulating layer 255 has a sidewall shape. Hereinafter, differences from the above-described <Configuration Example of Semiconductor Device> will be mainly described, and overlapping parts will be referred to and may not be described again.

[0099] In the transistor 200 shown in FIGS. 4A to 4D , the side surface of the insulating layer 255 facing the conductive layer 260 is aligned or substantially aligned with the side surface of the conductive layer 242a facing the conductive layer 260 in a plan view or a cross-sectional view. The side surface of the conductive layer 242b facing the conductive layer 260 is also aligned or substantially aligned with the side surface of the conductive layer 242a facing the conductive layer 260. The sidewall-shaped insulating layer 255 can be formed over the conductive layers that will become the conductive layers 242a and 242b by anisotropic etching. Furthermore, the conductive layers 242a and 242b can be formed by dividing the conductive layers using the insulating layer 255 as a mask. That is, the insulating layer 255 that functions as a mask can be formed in a self-aligned manner. This can reduce the number of masks and steps in the manufacturing process of the semiconductor device. Therefore, productivity of the semiconductor device can be improved. Note that the structures shown in FIGS. 4A to 4D also enable the source-drain distance to be shortened, thereby shortening the channel length. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, it is possible to provide a semiconductor device with improved operating speed.

[0100] 1A to 1D, by forming the insulating layer 255 in an L-shape, the width of the upper portion of the conductive layer 260 can be made larger than the distance L2. This can reduce the wiring resistance of the conductive layer 260. Therefore, the power consumption of the semiconductor device can be reduced.

[0101] 4A to 4D , the insulating layer 256 is provided as a continuous layer. For example, the insulating layer 256 is in contact with the side surfaces of the insulating layer 255, the side surfaces of the conductive layers 242 a and 242 b, and part of the top surface of the semiconductor layer 230.

[0102] 1A to 1D show a configuration in which the insulating layer 256 is provided, but the present invention is not limited to this. For example, a configuration in which the insulating layer 256 is not provided may be used.

[0103] Modifications of the semiconductor device described in <Configuration Example of Semiconductor Device> will be described with reference to Figures 6A to 7. Figure 6A is a plan view of a semiconductor device including a transistor 200, and corresponds to the plan view shown in Figure 1A. Figures 6B to 6D are cross-sectional views of the semiconductor device, and correspond to the cross-sectional views shown in Figures 1B to 1D, respectively. Figure 7 is an enlarged cross-sectional view of the transistor 200 in the channel length direction, and corresponds to the enlarged cross-sectional view shown in Figure 6B.

[0104] 6A to 6D differs from the transistor 200 shown in FIGS. 1A to 1D mainly in that the transistor 200 does not include the insulating layers 256a to 256c. Hereinafter, differences from the above-described <Structural Example of Semiconductor Device> will be mainly described, and overlapping portions will be referred to and may not be described again.

[0105] In the transistor 200 shown in FIGS. 6A to 6D , the insulating layer 250 is in contact with the side surface and top surface of the insulating layer 255 in the opening 289. Furthermore, the insulating layer 250 is in contact with the side surface of the insulating layer 255, the side surface of the conductive layer 242a, and the side surface of the conductive layer 242b in the opening 290. With this structure, the distance L3 can be sufficiently secured compared to the case where the insulating layer 256 is provided, and a decrease in the conductivity of the conductive layer 260 can be prevented. Furthermore, the number of steps involved in manufacturing the transistor can be reduced, thereby increasing the productivity of the semiconductor device. Furthermore, by not providing the insulating layer 256, the region where the semiconductor layer 230 and the conductive layer 260 do not overlap with each other via the insulating layer 250 (also referred to as the Loff region) can be narrowed. Therefore, the frequency characteristics of the transistor 200 can be improved, and the operating speed of the semiconductor device can be increased.

[0106] 4A to 4D show a configuration in which the insulating layer 256 is provided, but the present invention is not limited to this. For example, a configuration in which the insulating layer 256 is not provided may be used.

[0107] Modifications of the semiconductor device described in <Modification 1> will be described with reference to Figures 8A to 9. Figure 8A is a plan view of a semiconductor device including a transistor 200, and corresponds to the plan view shown in Figure 4A. Figures 8B to 8D are cross-sectional views of the semiconductor device, and correspond to the cross-sectional views shown in Figures 4B to 4D, respectively. Figure 9 is an enlarged cross-sectional view of the transistor 200 in the channel length direction, and corresponds to the enlarged cross-sectional view shown in Figure 8B.

[0108] 8A to 8D differs from the transistor 200 shown in Figures 4A to 4D mainly in that it does not have an insulating layer 256. Hereinafter, differences from the above-described <Configuration Example of Semiconductor Device> and <Modification 1> will be mainly described, and overlapping parts will be referred to and may not be described again.

[0109] 8A to 8D , the insulating layer 250 is in contact with the side surface of the insulating layer 255, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, and the top surface of the semiconductor layer 230 in the opening 289. With this structure, the distance L3 can be sufficiently secured compared to the case where the insulating layer 256 is provided (see FIGS. 4A to 4D ), and a decrease in the conductivity of the conductive layer 260 can be prevented. Furthermore, the number of steps involved in manufacturing the transistor can be reduced, thereby improving the productivity of the semiconductor device.

[0110] <Modification 4> As described above, the conductive layer 242a and the conductive layer 242b may each have a stacked structure. Of the configurations shown in FIG. 2A , FIG. 10A shows a semiconductor device in which the conductive layer 242a and the conductive layer 242b each have a two-layer structure. In FIG. 10A , the conductive layer 242a has a two-layer structure including a conductive layer 242a1 in contact with the semiconductor layer 230 and a conductive layer 242a2 on the conductive layer 242a1, and the conductive layer 242b has a two-layer structure including a conductive layer 242b1 in contact with the semiconductor layer 230 and a conductive layer 242b2 on the conductive layer 242b1. The conductive layer 242a1 and the conductive layer 242b1 correspond to the first conductive layer in contact with the semiconductor layer 230 described above, and may be made of, for example, ITO or ITSO. The conductive layer 242a2 and the conductive layer 242b2 correspond to the second conductive layer provided on the first conductive layer described above, and may be made of, for example, tungsten.

[0111] The insulating layer 255 is in contact with a part of the upper surface of the conductive layer 242a2 and a part of the upper surface of the conductive layer 242b2 at positions overlapping with the opening 289. In a plan view, at positions overlapping with the opening 289, the side surfaces of the conductive layer 242a1 and the conductive layer 242a2 are aligned or substantially aligned with the side surfaces of the insulating layer 255, respectively, and the side surfaces of the conductive layer 242b1 and the conductive layer 242b2 are aligned or substantially aligned with other side surfaces of the insulating layer 255, respectively.

[0112] Although FIG. 10A shows a structure in which the conductive layers 242a1 and 242a2 are in contact with the insulating layer 256a, and the conductive layers 242b1 and 242b2 are in contact with the insulating layer 256b, the present invention is not limited to this.

[0113] A modification of the semiconductor device shown in Fig. 10A will be described with reference to Fig. 10B, which is an enlarged cross-sectional view of a transistor in the channel length direction.

[0114] The semiconductor device shown in FIG. 10B differs from the semiconductor device shown in FIG. 10A mainly in that the side surfaces of the conductive layers 242a2 and 242b2 are in contact with the insulating layer 255.

[0115] 10B , the insulating layer 255 is in contact with the side surface of the conductive layer 242a2, part of the top surface of the conductive layer 242a1, the side surface of the conductive layer 242b2, and part of the top surface of the conductive layer 242b1 at positions overlapping with the opening 289. In a plan view, at positions overlapping with the opening 289, the side surfaces of the conductive layer 242a2 and the conductive layer 242b2 are aligned or approximately aligned with the side surfaces of the insulating layer 255.

[0116] In the opening 290, the insulating layer 256a contacts the side surface of the insulating layer 255 facing the conductive layer 242a1, the side surface of the conductive layer 242a1, and a part of the top surface of the semiconductor layer 230, and the insulating layer 256b contacts the side surface of the insulating layer 255 facing the conductive layer 242b1, the side surface of the conductive layer 242b1, and another part of the top surface of the semiconductor layer 230.

[0117] 10B , the conductive layer 242a2 is in contact with the insulating layer 255 but not with the insulating layer 256a. Similarly, the conductive layer 242b2 is in contact with the insulating layer 255 but not with the insulating layer 256b. With this structure, when an insulating material containing oxygen is used for the insulating layers 256a and 256b, the conductive layers 242a2 and 242b2 can be prevented from being excessively oxidized.

[0118] 10B, the distance L1 can be considered the shortest distance between the conductive layer 242a2 and the conductive layer 242b2, and the distance L2 can be considered the shortest distance between the conductive layer 242a1 and the conductive layer 242b1.

[0119] The above configuration can also be applied to the semiconductor device shown in Fig. 5, the semiconductor device shown in Fig. 7, and the semiconductor device shown in Fig. 9. Fig. 11A shows an example in which the above configuration is applied to the semiconductor device shown in Fig. 5, Fig. 11B shows an example in which the above configuration is applied to the semiconductor device shown in Fig. 7, and Fig. 11C shows an example in which the above configuration is applied to the semiconductor device shown in Fig. 9.

[0120] <Materials for Constituting Semiconductor Device> Materials that can be used for the semiconductor device will be described below. Each layer constituting the semiconductor device may have a single layer structure or a multilayer structure.

[0121] [Semiconductor Layer] As a metal oxide that can be used for the semiconductor layer 230, a metal oxide other than indium oxide can also be used. The metal oxide preferably contains at least one of indium and zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc. Note that the element M is a metal element or a metalloid element that has a high bond energy with oxygen, for example, a metal element or a metalloid element that has a higher bond energy with oxygen than indium.

[0122] Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, antimony, etc. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.

[0123] For example, metal oxides that can be used for the semiconductor layer 230 include zinc oxide (Zn oxide), In—Zn oxide, ITO, In—Ti oxide, indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also written as “GZO”), aluminum zinc oxide (Al—Zn oxide, also written as “AZO”), indium aluminum zinc oxide (In Indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), indium gallium zinc oxide (In—Ga—Zn oxide), indium tin zinc oxide (In—Ga—Sn—Zn oxide), indium gallium tin zinc oxide (In—Ga—Sn—Zn oxide), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide), indium gallium aluminum zinc oxide (In—Ga—Al—Zn oxide), or the like can be used. Alternatively, ITSO, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like can be used. Depending on the film formation conditions, composition, crystallinity, heat treatment after formation, and the like, these oxides may be used as oxygen-containing insulating materials (also called oxide insulators) or oxide conductors.

[0124] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of the metal elements among the main component elements contained in the metal oxide that functions as a semiconductor, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0125] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of metal elements among the main component elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0126] By increasing the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased. Typically, by using single-crystal or polycrystalline indium oxide for the semiconductor layer, the field-effect mobility of the transistor can be significantly increased. Furthermore, a transistor using single-crystal or polycrystalline indium oxide for the semiconductor layer can achieve good frequency characteristics.

[0127] A semiconductor material other than a metal oxide may be used as the semiconductor layer 230. Examples of the semiconductor material include a semiconductor made of a single element and a compound semiconductor.

[0128] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0129] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0130] Furthermore, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as a material that can be used for the semiconductor layer 230. Specifically, molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0131] The crystallinity of the semiconductor material used for the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a single crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0132] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 221, insulating layer 222, insulating layer 224, insulating layer 250, insulating layer 275, insulating layer 280, insulating layer 282, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a semiconductor device may be an organic insulating film.

[0133] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer allows for lower voltages during transistor operation while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. Meanwhile, using a material with a low dielectric constant for the insulating layer that functions as an interlayer film can reduce the parasitic capacitance that occurs between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0134] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0135] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low relative dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0136] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. As the material capable of exhibiting ferroelectricity, an oxide containing one or both of hafnium and zirconium is preferably used. Examples of such oxides include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Furthermore, as the material capable of exhibiting ferroelectricity, a material obtained by adding an element J1 (here, the element J1 is one or more selected from the other of hafnium and zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to a metal oxide containing one of hafnium and zirconium may be used.

[0137] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0138] Furthermore, examples of materials that may have ferroelectricity include metal nitrides containing nitrogen and at least one of element M1 and element M2. Here, element M1 is one or more selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. Furthermore, examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.

[0139] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ Furthermore, examples of materials that can have ferroelectricity include lead titanate (PbTiO ＸPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0140] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0141] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound of a plurality of materials selected from the materials listed above can be used. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of exhibiting ferroelectricity.

[0142] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0143] The ferroelectric layer preferably contains crystals having an orthorhombic crystal structure, since this allows ferroelectricity to be exhibited. The crystal structure of the crystals contained in the ferroelectric layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The ferroelectric layer may also have an amorphous structure. In this case, the ferroelectric layer may have a composite structure having an amorphous structure and a crystalline structure.

[0144] A metal oxide containing one or both of hafnium and zirconium is also an insulating material that has a function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing one or both of hafnium and zirconium for at least a part of a gate insulating layer, hydrogen contained in the oxide semiconductor layer can be captured or fixed, and excess hydrogen in the oxide semiconductor layer can be reduced. Furthermore, a transistor including the gate insulating layer can function as a ferroelectric field effect transistor (FeFET).

[0145] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0146] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0147] An insulating layer such as a gate insulating layer that is in contact with or near an oxide semiconductor layer preferably has a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with or near an oxide semiconductor layer, oxygen vacancies in the oxide semiconductor layer can be reduced.

[0148] An insulating layer provided in contact with or near an oxide semiconductor layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, diffusion of hydrogen into the oxide semiconductor layer can be suppressed. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0149] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, and examples thereof include oxides containing hafnium and zirconium.

[0150] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0151] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0152] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0153] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule or OH − . Furthermore, unless otherwise specified, impurities when described as a corresponding substance refer to impurities in a channel formation region or a semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0154] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), silicon nitride, and silicon nitride oxide.

[0155] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for oxygen barrier insulating layers include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0156] [Conductive Layer] The conductive layers (conductive layer 205, conductive layer 240a, conductive layer 240b, conductive layer 242a, conductive layer 242b, conductive layer 260, etc.) included in the semiconductor device preferably contain a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0157] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, In—Ti oxide, ITO, indium tin oxide containing titanium oxide, ITSO, In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0158] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0159] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0160] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0161] The above is a description of materials that can be used in semiconductor devices.

[0162] 12A to 22D , an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Here, the case of manufacturing the semiconductor device illustrated in FIGS. 1A to 1D will be described as an example. Note that with regard to the materials and formation methods of each component, descriptions of parts similar to those described above may be omitted.

[0163] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0164] RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used for film formation using a conductive target. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used for forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0165] CVD methods can be further classified into plasma-enhanced CVD (PECVD), which utilizes plasma, thermal CVD (TCVD), which utilizes heat, and photo-CVD (photo-CVD), which utilizes light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0166] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0167] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0168] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, a film formed by the ALD method may contain more elements such as carbon or chlorine than a film formed by other film formation methods. The amounts of these elements can be quantified using X-ray photoelectron spectroscopy (XPS) or secondary ion mass spectrometry (SIMS). Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method. However, because the method employs a high substrate temperature during film formation and / or performs an impurity removal treatment, the amounts of carbon and chlorine contained in the film may be smaller than those in a film formed by the ALD method without these treatments.

[0169] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0170] The CVD and ALD methods differ from sputtering, in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which has a faster film formation rate.

[0171] Furthermore, the CVD method allows deposition of a film with any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0172] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0173] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0174] In photolithography, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0175] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0176] 12 to 22A are plan views. Also, each of FIGS. 12 to 22B is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A1-A2 in each of FIGS. 12A to 22B, and is also a cross-sectional view in the channel length direction of the transistor 200. Also, each of FIGS. 12A to 22C is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A3-A4 in each of FIGS. 12A to 22D is a cross-sectional view corresponding to the portion indicated by the dashed dotted line A5-A6 in each of FIGS. 12A to 22D.

[0177] First, a substrate (not shown) is prepared, an insulating layer 212 is formed on the substrate, and an insulating layer 214 is formed on the insulating layer 212 (see FIGS. 12A to 12D ). In this embodiment, a silicon nitride film is formed as the insulating layer 212 by a sputtering method, and an aluminum oxide film is formed as the insulating layer 214 by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the film formation gas, the hydrogen concentrations in the insulating layers 212 and 214 can be reduced.

[0178] Furthermore, it is preferable to perform heat treatment to reduce water and hydrogen adsorbed to the substrate (including the circuit elements and interlayer films formed over the substrate) before forming the insulating layer 212. In this embodiment mode, the temperature of the heat treatment is 400° C.

[0179] Subsequently, the insulating layer 216 is formed over the insulating layer 214. In this embodiment, a silicon oxide film is formed by a sputtering method as the insulating layer 216. By using the sputtering method, which does not require the use of molecules containing hydrogen in a deposition gas, the hydrogen concentration in the insulating layer 216 can be reduced.

[0180] The insulating layers 212, 214, and 216 are preferably successively formed without exposure to the air. For example, a multi-chamber film formation apparatus may be used. This allows the insulating layers 212, 214, and 216 to be formed with reduced hydrogen content and further reduces hydrogen contamination between film formation steps.

[0181] Next, an opening reaching the insulating layer 214 is formed in the insulating layer 216. The opening is formed in a region where the conductive layer 205 is to be formed. Although wet etching may be used to form the opening, dry etching is preferable for fine processing. For the insulating layer 214, an insulator that functions as an etching stopper film when the insulating layer 216 is etched is preferably selected. For example, when silicon oxide or silicon oxynitride is used for the insulating layer 216, silicon nitride, aluminum oxide, hafnium oxide, or the like may be used for the insulating layer 214.

[0182] After the opening is formed, a conductive film to be the conductive layer 205 is formed, and then a chemical mechanical polishing (CMP) process is performed to remove part of the conductive film until the insulating layer 216 is exposed. This allows the conductive layer 205 to be embedded in the insulating layer 216 to be formed (see FIGS. 12A to 12D ). In this embodiment, the conductive film is a stacked film of a titanium nitride film formed by a CVD method and a tungsten film formed on the titanium nitride film by a CVD method.

[0183] Subsequently, an insulating layer 221 is formed over the insulating layer 216 and the conductive layer 205, and an insulating layer 222 is further formed over the insulating layer 221 (see FIGS. 13A to 13D ). In this embodiment, a silicon nitride film is formed as the insulating layer 221 by a PEALD method, and a hafnium oxide film is formed as the insulating layer 222 by a thermal ALD method.

[0184] Subsequently, an insulating layer 224 is formed over the insulating layer 222 (see FIGS. 13A to 13D ). In this embodiment, a silicon oxide film is formed as the insulating layer 224 by a sputtering method. By using a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration in the insulating layer 224 can be reduced. Since the insulating layer 224 will be in contact with the semiconductor layer 230 in a later step, it is preferable that the hydrogen concentration be reduced in this manner.

[0185] Next, a semiconductor layer 230 is formed over the insulating layer 224 (see FIGS. 13A to 13D). In this embodiment, an indium oxide film is formed as the semiconductor layer 230 by a sputtering method or an ALD method.

[0186] Subsequently, heat treatment is preferably performed. For example, the heat treatment can be performed at 450° C. for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. The heat treatment can improve the crystallinity of the semiconductor layer 230. As a result, the on-state current, S value, field-effect mobility, frequency characteristics, and the like of the transistor 200 can be improved, and a semiconductor device with favorable electrical characteristics can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0187] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0188] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the semiconductor layer 230 and the like as much as possible. Note that highly purified gas can also be used for the heat treatment before this step and the heat treatment after this step.

[0189] Furthermore, the heat treatment including oxygen gas as described above can reduce impurities such as carbon, water, and hydrogen in the semiconductor layer 230. Reducing the impurities in the film in this way can improve the crystallinity of the semiconductor layer 230, resulting in a denser and more compact structure. This increases the crystalline region in the semiconductor layer 230, reducing in-plane variations in the crystalline region in the semiconductor layer 230. This can reduce in-plane variations in the electrical characteristics of the transistor.

[0190] Furthermore, by performing heat treatment, oxygen can be supplied to the semiconductor layer 230, and oxygen vacancies in the semiconductor layer 230 can be reduced. This can improve the reliability of the transistor 200.

[0191] Furthermore, by performing heat treatment, hydrogen in the insulating layer 216, the insulating layer 224, and the semiconductor layer 230 moves to the insulating layer 222 and is absorbed into the insulating layer 222. In other words, hydrogen in the insulating layer 216, the insulating layer 224, and the semiconductor layer 230 diffuses into the insulating layer 222. Therefore, the hydrogen concentration in the insulating layer 222 increases, but the hydrogen concentrations in the insulating layer 216, the insulating layer 224, and the semiconductor layer 230 decrease. Note that by providing the insulating layer 221 in contact with the lower surface of the insulating layer 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulating layer 221 during the heat treatment.

[0192] Next, a conductive layer 242f to be the conductive layer 242a and the conductive layer 242b is formed over the semiconductor layer 230 (see FIGS. 13A to 13D ). In this embodiment, ITO or ITSO is formed as the conductive layer 242f by a sputtering method or an ALD method. Note that heat treatment may be performed before the formation of the conductive layer 242f. The heat treatment may be performed under reduced pressure, and the conductive layer 242f may be formed successively without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the semiconductor layer 230 can be removed and excess hydrogen in the semiconductor layer 230 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0193] Next, the insulating layer 224, the semiconductor layer 230, and the conductive layer 242f are processed into island shapes by lithography (see FIGS. 14A to 14D). Dry etching or wet etching can be used for this processing. Dry etching is suitable for fine processing. The insulating layer 224, the semiconductor layer 230, and the conductive layer 242f may be processed under different conditions.

[0194] Here, it is preferable to process the insulating layer 224, the semiconductor layer 230, and the conductive layer 242f collectively into an island shape. At this time, it is preferable that the side edge of the conductive layer 242f coincides or substantially coincides with the side edge of the semiconductor layer 230. Furthermore, it is preferable that the side edge of the insulating layer 224 coincides or substantially coincides with the side edge of the semiconductor layer 230. With such a structure, the number of steps involved in manufacturing a transistor can be reduced, and the productivity of the semiconductor device can be increased.

[0195] Furthermore, the insulating layer 222 is exposed in a region that does not overlap with the insulating layer 224, the semiconductor layer 230, or the conductive layer 242f. However, this is not limiting, and a structure in which the insulating layer 224 remains on the insulating layer 222 in a region that does not overlap with the semiconductor layer 230 may also be used.

[0196] 14B to 14D , the side surfaces of the insulating layer 224, the semiconductor layer 230, and the conductive layer 242f may be tapered. The taper angle of the side surfaces of the insulating layer 224, the semiconductor layer 230, and the conductive layer 242f may be, for example, 60° or more and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulating layer 275 and the like can be improved in subsequent steps, and defects such as voids can be reduced.

[0197] Furthermore, without being limited to the above, the side surfaces of the insulating layer 224, the semiconductor layer 230, and the conductive layer 242f may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222. With such a structure, it is possible to reduce the area and increase the density when providing a plurality of transistors.

[0198] In lithography, a photoresist is first exposed through a mask. The exposed area is then removed or left using a developer to form a resist mask. Next, a conductive layer, a semiconductor layer, an insulating layer, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the photoresist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique may also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Alternatively, an electron beam or an ion beam may be used instead of the light described above. When an electron beam or an ion beam is used, a mask may not be required.

[0199] The resist mask that is no longer needed after processing can be removed by performing a dry etching treatment such as ashing using oxygen plasma (hereinafter, sometimes referred to as oxygen plasma treatment), a wet etching treatment, a dry etching treatment followed by a wet etching treatment, or a wet etching treatment followed by a dry etching treatment.

[0200] Furthermore, a hard mask made of an insulating layer or a conductive layer may be used under the resist mask. When using a hard mask, an insulating or conductive film serving as the hard mask is formed on the conductive layer 242f, a resist mask is formed thereon, and the hard mask is etched to a desired shape. For example, tungsten may be used as the hard mask. Etching of the conductive layer 242f and the like may be performed after removing the resist mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the insulating layer 275 and the like. On the other hand, if the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0201] Alternatively, a spin-on-carbon (SOC) film and a spin-on-glass (SOG) film may be formed between the workpiece and the resist mask. Using the SOC film and the SOG film as a mask can improve adhesion with the resist mask and improve the durability of the mask pattern. For example, a lithography method can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0202] As the etching gas for the dry etching process, an etching gas containing halogen can be used, and specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas may contain C ４ F ６ Gas, C ５ F ６ Gas, C ４ F ８ Gas, CF ４ Gas, SF ６ Gas, CHF ３ Gas, CH ２ F ２ Gas, Cl ２ Gas, BCl ３ Gas, SiCl ４ gas, or BBr ３Gases such as fluorine-containing gases can be used alone or in combination of two or more gases. Oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the above-mentioned etching gas as appropriate. Depending on the object to be dry-etched, gases containing hydrocarbon gas or hydrogen gas but not containing halogen gas can be used as the etching gas. Examples of hydrocarbons used in the etching gas include methane (CH ４ ), ethane (C ２ H ６ ), propane (C ３ H ８ ), butane (C ４ H １０ ), ethylene (C ２ H ４ ), propylene (C ３ H ６ ), acetylene (C ２ H ２ ), and propyne (C ３ H ４ The etching conditions can be appropriately set depending on the target to be etched.

[0203] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel-plate electrodes. A capacitively coupled plasma etching apparatus having parallel-plate electrodes may be configured to apply a high-frequency voltage to one of the parallel-plate electrodes. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to the parallel-plate electrodes. Such a CCP etching apparatus is called a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. In the DF-CCP etching apparatus, a high-frequency voltage of a different frequency may be applied to each of the parallel-plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel-plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. The dry etching apparatus having a high-density plasma source can be, for example, an inductively coupled plasma (ICP) etching apparatus. The etching apparatus can be appropriately configured according to the object to be etched. In the above-mentioned dry etching apparatus, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, thereby enabling highly anisotropic etching.

[0204] Subsequently, an insulating layer 275 is formed to cover the insulating layer 224, the semiconductor layer 230, and the conductive layer 242f, and an insulating layer 280 is further formed over the insulating layer 275 (see FIGS. 15A to 15D). Note that after the insulating layer 280 is formed, it is preferable to perform CMP treatment to planarize the top surface of the insulating layer 280.

[0205] Next, the insulating layer 275 and the insulating layer 280 are processed by lithography to form an opening 289 that reaches the conductive layer 242f and the insulating layer 222 (see FIGS. 16A to 16D ). The opening 289 overlaps with the semiconductor layer 230 and the conductive layer 205. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening 289 is L1.

[0206] The lithography method can be any of the above methods as appropriate. In order to finely process the opening 289, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0207] Note that when the conductive layer 242f has a two-layer structure including a first conductive layer that will become the conductive layers 242a1 and 242b1 and a second conductive layer that will become the conductive layers 242a2 and 242b2, the portion of the second conductive layer that overlaps with the opening 289 is removed during or after the formation of the opening 289. This separates the second conductive layer, forming the conductive layers 242a2 and 242b2. By performing the subsequent steps, the semiconductor device shown in FIG. 10B can be manufactured.

[0208] Subsequently, an insulating layer 255 is formed to cover the insulating layer 280, the conductive layer 242f, and the insulating layer 222 (see FIGS. 17A to 17D ). The insulating layer 255 is preferably formed along the opening 289 and therefore has good coverage. For example, the insulating layer 255 is preferably formed using an aluminum oxide film, a hafnium oxide film, or a silicon nitride film by an ALD method.

[0209] Next, the conductive layer 242f and the insulating layer 255 are processed using lithography at the opening 289 to form an opening that reaches the semiconductor layer 230 (see FIGS. 18A to 18D ). Here, an opening 290 is formed in the insulating layer 255. The conductive layer 242f is also divided to form the conductive layers 242a and 242b. In a cross-sectional view of the transistor 200 in the channel length direction, the width of the opening is L2, which corresponds to the distance L2 between the conductive layers 242a and 242b. Because the opening is formed in the opening 289, the distance L2 is shorter than the distance L1.

[0210] The lithography method can be any of the above methods as appropriate. In order to finely process the opening 289, it is preferable to use a lithography method using short wavelength light such as EUV light or an electron beam.

[0211] In this manner, the conductive layer 242 a and the conductive layer 242 b can be formed with a distance L2 between them. With this structure, the distance between the source and drain of the transistor 200 can be shortened, thereby improving the frequency characteristics of the transistor 200 and the operating speed of the semiconductor device.

[0212] In the above processing, the thickness of the region overlapping with the opening of the semiconductor layer 230 may be thinned. By performing the subsequent steps, the semiconductor device shown in FIG.

[0213] In the above process, the insulating layer 255 can be processed by anisotropic etching instead of lithography, thereby forming a sidewall-shaped insulating layer 255 as shown in Figures 4A to 4D. Furthermore, the conductive layer can be divided using the insulating layer 255 as a mask to form conductive layers 242a and 242b. Furthermore, by performing the following steps, the semiconductor device shown in Figures 4A to 4D can be manufactured.

[0214] The above processing may cause impurities to adhere to the top and side surfaces of the semiconductor layer 230 or to diffuse into the semiconductor layer 230. A process for removing such impurities may be performed. Furthermore, the above processing may cause damaged regions to be formed on the surface of the semiconductor layer 230. Such damaged regions may be removed. Examples of such impurities include those derived from components contained in the insulating layer 280, the insulating layer 275, the insulating layer 255, the conductive layer 242a, and the conductive layer 242b, components contained in the components of the device used to form the opening 289 or the opening 290, and components contained in the gas or liquid used in etching. Examples of such impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

[0215] It is preferable to perform a cleaning treatment to remove impurities and the like attached to the surface of the semiconductor layer 230. Cleaning methods include wet cleaning using a cleaning solution or the like (also called wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment, and the above cleaning methods may be combined as appropriate. Note that the cleaning treatment may deepen the grooves in some cases.

[0216] Wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0217] In this specification and the like, an aqueous solution obtained by diluting hydrofluoric acid with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution obtained by diluting ammonia water with pure water may be referred to as diluted ammonia water. The concentration, temperature, etc. of the aqueous solution are adjusted appropriately depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0218] Note that ultrasonic cleaning preferably uses a frequency of 200 kHz or more, and more preferably a frequency of 900 kHz or more, because use of such a frequency can reduce damage to the semiconductor layer 230 and the like.

[0219] The cleaning process may be repeated multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0220] It is preferable to perform heat treatment after the above processing or cleaning. The temperature of the heat treatment is preferably 100°C or higher, 250°C or higher, or 350°C or higher, and 650°C or lower, 600°C or lower, 550°C or lower, or 400°C or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. The heat treatment is preferably performed in an atmosphere containing oxygen, for example, at a temperature of 350°C for 1 hour with a flow ratio of nitrogen gas to oxygen gas of 4:1. This allows oxygen to be supplied to the semiconductor layer 230, thereby reducing oxygen vacancies. Furthermore, such heat treatment can improve the crystallinity of the semiconductor layer 230. Furthermore, the supplied oxygen reacts with hydrogen remaining in the semiconductor layer 230, converting the hydrogen into H ２ As a result, hydrogen remaining in the semiconductor layer 230 is recombined with the oxygen vacancies to form V Ｏ The formation of H can be suppressed. This improves the electrical characteristics of the transistor and increases its reliability. Furthermore, it is possible to suppress variations in the electrical characteristics of multiple transistors formed on the same substrate. The heat treatment may be performed under reduced pressure. Alternatively, after heat treatment in an oxygen atmosphere, heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0221] When heat treatment is performed with the conductive layer 242a and the conductive layer 242b in contact with the semiconductor layer 230, the sheet resistance may decrease in the region of the semiconductor layer 230 that overlaps with the conductive layer 242a and the region of the semiconductor layer 230 that overlaps with the conductive layer 242b. Also, the carrier concentration may increase. Therefore, the resistance of the region of the semiconductor layer 230 that overlaps with the conductive layer 242a and the region of the semiconductor layer 230 that overlaps with the conductive layer 242b can be reduced in a self-aligned manner.

[0222] Subsequently, an insulating layer 256 is formed to cover the insulating layer 280, the insulating layer 255, and the semiconductor layer 230 (see FIGS. 19A to 19D ). The insulating layer 256 is preferably formed along the openings 289 and 290 and therefore has good coverage. For example, the insulating layer 256 is preferably formed of a silicon nitride film by a PEALD method.

[0223] Subsequently, a portion of the insulating layer 256 is removed by anisotropic etching. As described above, by using a material for the insulating layer 256 that has a significantly different etching rate from the insulating layer 255, the insulating layer 256a can be formed in contact with a part of the sidewall of the opening 290 and the side surface of the conductive layer 242a, the insulating layer 256b can be formed in contact with another part of the sidewall of the opening 290 and the side surface of the conductive layer 242b, and the sidewall-shaped insulating layer 256c can be formed in contact with the side surface of the insulating layer 255 (see FIGS. 20A to 20D ). The insulating layers 256a to 256c are obtained by processing the insulating layer 256 and therefore contain the same material.

[0224] Note that the side surfaces of the semiconductor layer 230 are preferably tapered. For example, the taper angle of the semiconductor layer 230 is preferably smaller than the taper angle of the sidewall of the opening 289. Furthermore, the taper angle is preferably smaller than the taper angle of the side surfaces of the conductive layers 242a and 242b facing each other. This allows a structure in which the insulating layer 256 is not provided on the side surfaces of the semiconductor layer 230. Therefore, the distance between the semiconductor layer 230 and the conductive layer 260 can be kept constant in the opening 289. Therefore, the electric field of the conductive layer 260 can be easily applied to the entire channel formation region of the semiconductor layer 230. Therefore, the on-state current of the transistor 200 can be increased, and the frequency characteristics can be improved.

[0225] In a cross-sectional view in the channel length direction, the insulating layer 256a is formed in contact with the side surface of the conductive layer 242a at a position overlapping with the opening 290, and the insulating layer 256b is formed in contact with the side surface of the conductive layer 242a at a position overlapping with the opening 290. Therefore, the shortest distance between the insulating layer 256a and the insulating layer 256b is shorter than the distance L2. Here, the difference between the shortest distance between the insulating layer 256a and the insulating layer 256b and the distance L2 is equal to or approximately equal to the sum of the film thicknesses of the insulating layer 256a and the insulating layer 256b (see FIG. 2A ).

[0226] For anisotropic etching, it is preferable to use a dry etching method. The above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. For example, when silicon nitride is used for the insulating layer 256, the dry etching is performed in an ICP etching apparatus using CHF ３ and O ２ The etching process can be carried out using the above as an etching gas.

[0227] Note that the semiconductor device illustrated in FIGS. 6A to 6D can be manufactured by performing the subsequent steps without forming the insulating layers 256a to 256c.

[0228] Subsequently, the insulating layer 250 is formed to cover the insulating layer 280, the insulating layer 255, the insulating layers 256a to 256c, and the semiconductor layer 230 (see FIGS. 21A to 21D).

[0229] Next, it is preferable to perform microwave treatment in an oxygen-containing atmosphere. Here, microwave treatment refers to treatment using, for example, a device having a power source that generates high-density plasma using microwaves. In addition, in this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0230] In the microwave treatment, it is preferable to use a microwave treatment device having a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Furthermore, the output of the microwave power supply of the microwave treatment device is preferably 1000 W to 10,000 W, preferably 2000 W to 5,000 W. Furthermore, the microwave treatment device may have a power supply that applies RF to the substrate side. Furthermore, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the film.

[0231] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 to 1000 Pa, and more preferably from 300 to 700 Pa. The treatment temperature is preferably from room temperature (25°C) to 750°C, more preferably from 300 to 500°C, and even more preferably from 400 to 450°C.

[0232] Alternatively, after the microwave treatment or plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0233] The microwave treatment can be carried out using, for example, oxygen gas and argon gas. Here, the oxygen flow rate ratio (O ２ / (O ２ +Ar)) is preferably greater than 0% and less than 100%, more preferably greater than 0% and 50% or less, even more preferably 10% or more and 40% or less, and still more preferably 10% or more and 30% or less.

[0234] When the insulating layer 250 has a stacked structure, the microwave treatment is not necessarily performed after the formation of the insulating layer 250. For example, when two or more layers are stacked as the insulating layer 250, the microwave treatment may be performed before the formation of a layer in contact with the conductive layer 260, or after the formation of a layer in contact with the semiconductor layer 230, or after the formation of a layer provided between them. The microwave treatment may be performed multiple times (at least two times or more).

[0235] Subsequently, a conductive layer 260 is formed over the insulating layer 250 (see FIGS. 21A to 21D). In this embodiment, the conductive layer 260 is a stacked film including a titanium nitride film formed by an ALD method and a tungsten film formed over the titanium nitride film by a CVD method.

[0236] Subsequently, the insulating layer 255, the insulating layer 250, and the conductive layer 260 are polished by CMP treatment until the insulating layer 280 is exposed. That is, the portions of the insulating layer 255, the insulating layer 250, and the conductive layer 260 exposed from the opening 289 are removed. As a result, the insulating layer 255, the insulating layer 250, and the conductive layer 260 can be formed in the opening 289 (see FIGS. 22A to 22D ).

[0237] Subsequently, an insulating layer 282 is formed over the insulating layer 250, the insulating layer 255, the insulating layer 256c, the conductive layer 260, and the insulating layer 280, an insulating layer 283 is formed over the insulating layer 282, and an insulating layer 285 is formed over the insulating layer 283. In this embodiment, an aluminum oxide film is formed as the insulating layer 282 by a sputtering method, a silicon nitride film is formed as the insulating layer 283 by a sputtering method, and a silicon oxide film is formed as the insulating layer 285 by a sputtering method.

[0238] Next, a first opening reaching the conductive layer 242a and a second opening reaching the conductive layer 242b are formed in the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285. The first opening and the second opening may be formed by lithography. The first opening and the second opening are preferably formed by processing the workpiece using a dry etching method. Since the dry etching method allows anisotropic etching, it is suitable for forming openings with a high aspect ratio. When performing anisotropic etching, reactive ion etching, for example, is preferably performed. The shape of the opening in top view can be a circle, a substantially circular shape such as an ellipse, a polygonal shape such as a rectangle, or a polygonal shape with rounded corners such as a rectangle.

[0239] Subsequently, after the first opening and the second opening are formed, heat treatment is preferably performed. The temperature of the heat treatment is 100° C. or higher and 600° C. or lower, preferably 250° C. or higher and 550° C. or lower, more preferably 350° C. or higher and 450° C. or lower. Note that the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. Furthermore, since the heat treatment is performed in a state in which the conductive layers 242a and 242b are exposed, the heat treatment is preferably performed in an atmosphere that does not contain an oxidizing gas or oxygen gas. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at 400° C. for 1 hour. Note that the heat treatment may be performed under reduced pressure. By the heat treatment, oxygen contained in the insulating layer 280 can be supplied to the semiconductor layer 230 through the insulating layer 250. This can reduce oxygen vacancies in the channel formation region of the semiconductor layer 230.

[0240] Here, because the side surfaces of the insulating layer 280 are exposed in the first opening and the second opening, the heat treatment can outwardly diffuse oxygen contained in the insulating layer 280, thereby controlling the amount of oxygen contained in the insulating layer 280. Meanwhile, because the insulating layers 282 and 283, which have barrier properties against oxygen, are provided on the insulating layer 280, oxygen does not outwardly diffuse from the upper surface of the insulating layer 280. This can prevent excessive oxygen from outwardly diffusing from the insulating layer 280 and forming oxygen vacancies in the insulating layer 280. Furthermore, the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b are covered with the insulating layer 275. This can prevent excessive oxygen from diffusing directly from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b during the heat treatment.

[0241] Furthermore, by performing the heat treatment, hydrogen contained in the insulating layer 280, the insulating layer 250, and the semiconductor layer 230 diffuses into the insulating layer 282. Therefore, the hydrogen concentration in the insulating layer 282 increases, but the hydrogen concentrations in the insulating layer 280, the insulating layer 250, and the semiconductor layer 230 decrease. Note that by providing the insulating layer 283 in contact with the top surface of the insulating layer 282, impurities such as moisture or hydrogen can be prevented from entering from above the insulating layer 283 during the heat treatment.

[0242] Next, a conductive film that becomes the conductive layer 240a and the conductive layer 240b is formed along the shapes of the first opening and the second opening. The conductive film can be, for example, a stack of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. Then, CMP treatment is performed to remove part of the conductive film and expose the top surface of the insulating layer 285. As a result, the conductive film remains inside the first opening and the second opening, thereby forming the conductive layer 240a and the conductive layer 240b with flat top surfaces (see FIGS. 1A to 1D ). Note that the CMP treatment may remove part of the top surface of the insulating layer 285.

[0243] In this manner, the semiconductor device shown in FIGS. 1A to 1D can be manufactured.

[0244] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0245] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0246] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0247] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0248] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 23A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 23B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0249] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 23B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 23A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 23A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 23A.

[0250] 23A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0251] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0252] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0253] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0254] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 23A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0255] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0256] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 23B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 23A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor including indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor including indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor including indium oxide can be normally-off and achieve high field-effect mobility.

[0257] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0258] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0259] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0260] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0261] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0262] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0263] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0264] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0265] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0266] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0267] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0268] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0269]

[0270] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the base of the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition of the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0271] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0272] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less. ３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0273] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0274] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0275] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 23C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0276] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0277] Furthermore, as shown in FIG. 23C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0278] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0279] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0280]

[0281] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0282] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0283] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0284] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the YSZ crystal can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0285] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0286] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0287] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0288] Fig. 24 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 24 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 24 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0289] The transistor 200 described in Embodiment 1 can be applied to the memory cell 950. By using the transistor described in Embodiment 1, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0290] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0291] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0292] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0293] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0294] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0295] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0296] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0297] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0298] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ The signal PON1 controls the on / off of the PSW 931, and the signal PON2 controls the on / off of the PSW 932. In FIG. 24, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0299] 25A to 25G, examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0300] 25A shows an example of a circuit configuration of a memory cell of a dynamic random access memory (DRAM). In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0301] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0302] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0303] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0304] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and bringing the wiring BIL and the first terminal of the capacitor CA into a conductive state (a state in which current can flow).

[0305] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 25B may be used. The memory cell 952 is an example of a memory cell that does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0306] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0307] Note that an OS transistor is preferably used as the transistor M1. Use of an OS transistor can improve the operation speed of the memory device. Furthermore, an OS transistor has a characteristic of having an extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made extremely small. That is, since written data can be held by the transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cell 951 and the memory cell 952.

[0308] An example of the structure of a DOSRAM will now be described with reference to Fig. 26. In Fig. 26, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X and Y directions.

[0309] As shown in FIG. 26 , the memory cell 951 includes a transistor M1 and a capacitor CA. An insulating layer 284 is provided over the transistor M1. The insulating material described in the “Insulating Layer” section of Embodiment 1 can be used for the insulating layer 284. The insulating layer 284 can be formed using an insulator that can be used for the insulating layer 216. The transistor M1 has a similar structure to the transistor 200 described in Embodiment 1, and the same components are denoted by the same reference numerals. For details of the transistor 200, refer to Embodiment 1. A conductive layer 240 is provided in contact with one of the source electrode and drain electrode (conductive layer 242b) of the transistor M1. The conductive layer 240 extends in the Z direction and functions as a wiring BIL. The conductive layer 260 of the transistor M1 extends in the X direction and functions as a wiring WOL.

[0310] The capacitor CA includes a conductive layer 453 over the conductive layer 242 a, an insulating layer 454 over the conductive layer 453 , and a conductive layer 460 over the insulating layer 454 .

[0311] At least a portion of the conductive layer 453, the insulating layer 454, and the conductive layer 460 is disposed in openings provided in the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285, respectively. The upper end of the conductive layer 453 coincides or substantially coincides with the upper surface of the insulating layer 285. The end of the insulating layer 454 and the end of the conductive layer 460 are each located on the insulating layer 285. The insulating layer 454 is provided so as to cover the end of the conductive layer 453. This allows the conductive layer 453 and the conductive layer 460 to be electrically insulated from each other.

[0312] The deeper the depth of the openings provided in the insulating layers 275, 280, 282, 283, and 285 (i.e., the thicker the film thickness of one or more of the insulating layers 275, 280, 282, 283, and 285), the larger the capacitance of the capacitor CA. Increasing the capacitance per unit area of ​​the capacitor CA allows for miniaturization or high integration of memory devices. For example, the capacitance of the capacitor CA can be set by adjusting the film thickness of the insulating layer 285. Specifically, the film thickness of the insulating layer 285 can be set in the range of 50 nm to 250 nm, and the depth of the openings can be set to approximately 150 nm to 350 nm. Forming the capacitor CA within such a range allows the capacitor CA to have sufficient capacitance, and prevents the height of one layer from becoming excessively high in a semiconductor device in which multiple memory cell layers are stacked. Note that the capacitance of the capacitor provided in each memory cell may be different in each of the layers of the memory cells by, for example, varying the thickness of the insulating layer 285 provided in each memory cell layer.

[0313] In the capacitor CA, the conductive layer 453 functions as one electrode (lower electrode), the insulating layer 454 functions as a dielectric, and the conductive layer 460 functions as the other electrode (upper electrode). The upper part of the conductive layer 460 can be extended to function as a wiring CAL. The capacitor CA forms a MIM (Metal-Insulator-Metal) capacitor.

[0314] The conductive layer 242a provided over the semiconductor layer 230 functions as an electrode electrically connected to the lower electrode of the capacitor CA.

[0315] The conductive layer 453 and the conductive layer 460 can be formed using a conductor applicable to the conductive layer 205 or the conductive layer 260, respectively. The conductive layer 453 and the conductive layer 460 are preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method. For example, the conductive layer 453 can be a titanium nitride film or a tantalum nitride film formed by an ALD method or a CVD method.

[0316] The top surface of the conductive layer 242a is in contact with the bottom surface of the conductive layer 453. Here, by using a conductive material with good conductivity for the conductive layer 242a, contact resistance between the conductive layer 453 and the conductive layer 242a can be reduced.

[0317] Alternatively, the conductive layer 460 can be formed using a stacked film of a titanium nitride film formed by an ALD method or a CVD method and a tungsten film formed by a CVD method over the titanium nitride film. Note that if the adhesion of the tungsten film to the insulating layer 454 is sufficiently high, the conductive layer 460 may have a single-layer structure of a tungsten film formed by a CVD method.

[0318] The high-k material described in the above embodiment is preferably used for the insulating layer 454 of the capacitor CA. By using the high-k material, the insulating layer 454 can be thick enough to suppress leakage current and ensure sufficient capacitance of the capacitor CA. In addition, the insulating layer 454 is preferably formed by a film formation method with good coverage, such as an ALD method or a CVD method.

[0319] In addition, it is preferable to use a stack of insulating layers made of the above materials, and it is preferable to use a stack structure of a high-k material and a material having a higher dielectric strength than the high-k material. For example, the insulating layer 454 can be an insulating film stacked in this order: a zirconium oxide film, an aluminum oxide film, and a zirconium oxide film. Alternatively, it can be an insulating film stacked in this order: a zirconium oxide film, an aluminum oxide film, a zirconium oxide film, and an aluminum oxide film. Alternatively, it can be an insulating film stacked in this order: a hafnium zirconium oxide film, an aluminum oxide film, a hafnium zirconium oxide film, and an aluminum oxide film. By stacking an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength can be improved, and electrostatic breakdown of the capacitor element CA can be suppressed.

[0320] Further, the insulating layer 454 may be formed using the material that can have ferroelectricity described in the [Insulating Layer] section of Embodiment Mode 1.

[0321] A ferroelectric material is an insulator that generates polarization internally when an external electric field is applied, and the polarization remains even when the electric field is removed. Therefore, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes called a Ferroelectric Random Access Memory (FeRAM), a ferroelectric memory, or the like. For example, a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element CA, the memory device described in this embodiment functions as a ferroelectric memory.

[0322] Note that the sidewall of the opening where the capacitor element CA is disposed may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222, or may be tapered. By tapering the sidewall of the opening, coverage by the conductive layer 453 or the like provided in the opening can be improved, and defects such as voids can be reduced.

[0323] Furthermore, the conductive layer 242b provided on the semiconductor layer 230 functions as wiring that connects to the conductive layer 240. For example, in Fig. 26, the upper surface and side end portions of the conductive layer 242b are connected to the conductive layer 240 that extends in the Z direction.

[0324] By having the conductive layer 240 directly contact at least one of the upper surface and side end of the conductive layer 242b, there is no need to provide a separate connection electrode, thereby reducing the area occupied by the memory array. Furthermore, the integration density of memory cells is improved, allowing the storage capacity of the storage device to be increased. It is preferable that the conductive layer 240 contact a portion of the upper surface and side end of the conductive layer 242b. By having the conductive layer 240 contact multiple surfaces of the conductive layer 242b, the contact resistance between the conductive layer 240 and the conductive layer 242b can be reduced.

[0325] The conductive layer 240 is provided in openings formed in the insulating layer 212, the insulating layer 214, the insulating layer 216, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, the insulating layer 285, and the insulating layer 284.

[0326] 26 , an insulating layer 241 is preferably provided in contact with the side surface of the conductive layer 240. Specifically, the insulating layer 241 is provided in contact with the inner walls of the openings of the insulating layer 212, the insulating layer 214, the insulating layer 216, the insulating layer 221, the insulating layer 222, the insulating layer 224, the insulating layer 275, the insulating layer 280, the insulating layer 282, the insulating layer 283, the insulating layer 285, and the insulating layer 284. The insulating layer 241 is also formed on the side surface of the semiconductor layer 230, which is formed to protrude inward of the opening. Here, at least a portion of the conductive layer 242b is exposed from the insulating layer 241 and is in contact with the conductive layer 240. That is, the conductive layer 240 is provided so as to fill the openings via the insulating layer 241.

[0327] 26 , the uppermost portion of the insulating layer 241 formed below the conductive layer 242b is preferably located below the upper surface of the conductive layer 242b. This structure allows the conductive layer 240 to be in contact with at least a portion of the side edge of the conductive layer 242b. The insulating layer 241 formed below the conductive layer 242b preferably has a region in contact with the side surface of the semiconductor layer 230. This structure can prevent impurities such as water and hydrogen contained in the insulating layer 280 from being mixed into the semiconductor layer 230 through the conductive layer 240.

[0328] Furthermore, in the opening where the conductive layer 240 and the insulating layer 241 are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the top surface of the insulating layer 222, or may have a tapered shape. By making the sidewall tapered, coverage of the insulating layer 241 or the like provided in the opening is improved.

[0329] 25C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0330] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0331] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0332] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0333] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0334] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 25D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0335] 25E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 25F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0336] Note that it is preferable to use an OS transistor for at least the transistor M2. In particular, it is preferable to use OS transistors for the transistors M2 and M3. By using an OS transistor as the transistor M2, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely small, multilevel data or analog data can be held in the memory cells 953 to 956.

[0337] The memory cells 953 to 956 in which an OS transistor is used as the transistor M2 are one embodiment of NOSRAM.

[0338] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0339] 25G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0340] The first terminal of transistor M4 is connected to the first terminal of capacitor CC, the second terminal of transistor M4 is connected to wiring BIL, and the gate of transistor M4 is connected to wiring WOL. The second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. The second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of capacitor CC. The second terminal of transistor M6 is connected to wiring BIL, and the gate of transistor M6 is connected to wiring RWL.

[0341] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0342] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and establishing electrical continuity between the wiring BIL and the first terminal of the capacitor CC. Specifically, when the transistor M4 is on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0343] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0344] Note that at least the transistor M4 is preferably an OS transistor.

[0345] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0346] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 27A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 27B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0347] Here, a configuration example of a semiconductor device 900 in which memory arrays 920 are stacked in multiple layers will be described with reference to FIG.

[0348] 28 includes a driver circuit 910, which is a layer including a transistor 310 and the like, and memory arrays 920[1] to 920[m] over the driver circuit 910. Here, the layer provided in the first layer (bottom) is referred to as memory array 920[1], the layer provided in the second layer is referred to as memory array 920[2], and the layer provided in the m-th layer (top) is referred to as memory array 920[m]. In other words, the memory device of one embodiment of the present invention may have a structure in which a plurality of layers including memory cells are stacked.

[0349] 28 illustrates a transistor 310 included in a driver circuit 910. The transistor 310 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 including part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. An element isolation layer 318 is preferably provided between adjacent transistors 310. The transistor 310 may be either a p-channel transistor or an n-channel transistor. The substrate 311 may be, for example, a single crystal silicon substrate.

[0350] Here, in the transistor 310, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a FIN-type transistor because it utilizes the convex portions of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portions and functions as a mask for forming the convex portions may be provided. Here, the case where the convex portions are formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0351] Note that the transistor 310 illustrated in FIG. 28 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.

[0352] Between each structure, a wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer having the function of a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0353] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 310. A conductive layer 328 or the like is embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 or the like is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0354] The insulating layer serving as an interlayer film may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by CMP treatment to improve the planarity.

[0355] Insulators that can be used as the interlayer film include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0356] For example, by using a material with a low dielectric constant for the insulating layer that functions as an interlayer film, the parasitic capacitance that occurs between wirings can be reduced. Therefore, it is preferable to select a material depending on the function of the insulating layer.

[0357] An insulating layer 208 is provided over the driver circuit 910, and a conductive layer 207 is provided in an opening formed in the insulating layer 208. Further, an insulating layer 210 is provided over the insulating layer 208, and a conductive layer 209 is provided in an opening formed in the insulating layer 210. Further, an insulating layer 212 is provided over the insulating layer 210, and an insulating layer 214 is provided over the insulating layer 212. Part of the conductive layer 240 provided in the memory array 920[1] is buried in the openings formed in the insulating layer 212 and the insulating layer 214. Here, the insulating layer 208 and the insulating layer 210 can be formed using the insulating material described in [Insulating Layer] in Embodiment 1. Furthermore, the insulating layer 208 and the insulating layer 210 can be formed using an insulator applicable to the insulating layer 216.

[0358] The conductive layer 207 functions as a wiring electrically connected to the driver circuit 910. The top surface of the conductive layer 207 is in contact with the bottom surface of the conductive layer 209. The top surface of the conductive layer 209 is in contact with the bottom surface of the conductive layer 240 provided in the memory array 920[1]. With this structure, the conductive layer 240 corresponding to the wiring BIL can be electrically connected to the driver circuit 910.

[0359] Each of the memory arrays 920[1] to 920[m] includes a plurality of memory cells 951. The conductive layer 240 of each memory cell 951 is electrically connected to the conductive layer 240 in the upper layer and the conductive layer 240 in the lower layer.

[0360] 28, the conductive layer 240 is shared by adjacent memory cells 951. In addition, in the adjacent memory cells 951, the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductive layer 240.

[0361] In the above-described memory array 920, the memory arrays 920[1] to 920[m] can be stacked. The memory arrays 920[1] to 920[m] included in the memory array 920 can be arranged in the vertical direction of the substrate surface on which the driver circuit 910 is provided, thereby improving the memory density of the memory cells 951. Furthermore, the memory array 920 can be manufactured by repeatedly using the same manufacturing process in the vertical direction. The semiconductor device 900 can reduce the manufacturing cost of the memory array 920.

[0362] Next, an example of a processing unit that can include a semiconductor device such as the memory device will be described.

[0363] 29 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 29 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0364] The arithmetic device 960 shown in FIG. 29 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

[0365] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0366] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0367] It is also possible to use only the memory array 920 as a cache without providing the cache 969 .

[0368] The arithmetic device 960 shown in FIG. 29 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 29 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle via its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, or 64 bits.

[0369] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0370] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0371] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0372] 29 , a register controller 967 selects a holding operation in a register 966 in accordance with an instruction from an ALU 962. That is, the register controller 967 selects whether data is to be held by a flip-flop or by a capacitor in the memory cell of the register 966. If holding data by a flip-flop is selected, a power supply potential is supplied to the memory cell in the register 966. If holding data in a capacitor is selected, data is rewritten to the capacitor, and the supply of power supply potential to the memory cell in the register 966 can be stopped.

[0373] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 30A and 30B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 30B.

[0374] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0375] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also called monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (such as Cu-Cu bonding) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0376] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0377] When the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0378] 30B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0379] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0380] When the memory array 920L1 is used as a cache, the driver 910L1 may function as part of the cache interface 969i, or may be configured to be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or may be configured to be connected thereto.

[0381] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0382] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0383] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 31A shows a perspective view of a semiconductor device 970B.

[0384] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 31A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0385] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0386] Also, multiple memory arrays may be stacked. Figure 31B shows a perspective view of a semiconductor device 970C.

[0387] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0388] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0389] Embodiment 4 In this embodiment, an example of the applicability of a semiconductor device of one embodiment of the present invention will be described with reference to FIG. 32 . A transistor including an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor are used in a memory device of one embodiment of the present invention. Since the off-state current of an OS transistor is extremely small, a memory device including an OS transistor has excellent storage characteristics and can function as a nonvolatile memory.

[0390] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 32 shows a conceptual diagram explaining the hierarchy of memory devices used in semiconductor devices. In Figure 32, the conceptual diagram explaining the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0391] In FIG. 32 , from the top layer of the triangle, there are shown memories integrated as registers in the CPU, GPU, and NPU arithmetic processing units, cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs, and storage memories such as 3D NANDs and hard disks (also called HDDs: hard disk drives).

[0392] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0393] Cache memory has the function of duplicating and storing a portion of the data stored in DRAM. By duplicating frequently used data and storing it in cache memory, the speed of accessing the data can be increased. The storage capacity required for cache memory is smaller than that of DRAM, but it is required to have a faster operating speed than DRAM. In addition, data rewritten in cache memory is duplicated and supplied to DRAM.

[0394] The memory device of one embodiment of the present invention can be used as a DRAM.

[0395] 32 illustrates only up to the L3 cache as a cache memory, but the present invention is not limited to this. For example, the storage device of one embodiment of the present invention can be used as a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of the cache.

[0396] The DRAM has the function of holding programs, data, etc. read from the 3D NAND.

[0397] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0398] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) can be used.

[0399] The memory device of one embodiment of the present invention can be monolithically structured with peripheral circuits by using OS transistors. Furthermore, the use of OS transistors allows monolithic stacking with peripheral circuits. Therefore, this has advantages in terms of data access with peripheral circuits. Furthermore, the degree of integration can be increased by stacking with peripheral circuits. Furthermore, the use of OS transistors enables the memory device of one embodiment of the present invention to retain data for a long period of time. Therefore, when used as a DRAM, the frequency of refresh can be reduced.

[0400] Furthermore, the storage device of one embodiment of the present invention can reduce leakage current by using an OS transistor. Therefore, for example, data can be sufficiently stored even if the capacitance value of a capacitor is small. Therefore, for example, by using the storage device of one embodiment of the present invention as a DRAM, the operation speed of the DRAM, for example, the speed of rewriting, can be increased in some cases.

[0401] Furthermore, since the memory device of one embodiment of the present invention includes a capacitor including a ferroelectric material, data can be retained for a long time. Therefore, when the memory device is used as a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

[0402] The storage device of one embodiment of the present invention can be used for the Target2 region and the Target1 region shown in Figure 32. In particular, the storage device can be suitably used for the Target1 region.

[0403] 32, Target1 includes a boundary area (Target1_1) between the DRAM and 3D NAND, and a boundary area (Target1_2) between the DRAM and cache (L1, L2, L3). Examples of Target1_2 include the LLC and FLC mentioned above.

[0404] By replacing the storage device of one embodiment of the present invention with a DRAM, power consumption can be reduced. With this configuration, power consumption can be reduced to half or less, preferably one-tenth or less, more preferably one-hundredth or less, and further preferably one-thousandth or less, compared to a configuration using a DRAM. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target 1.

[0405] Furthermore, the storage device of one embodiment of the present invention can retain data for a long time and has advantages in terms of data access. Therefore, the storage device of one embodiment of the present invention can be suitably used for Target1_1, which is a region of Target1 that is rewritten relatively infrequently. By applying the storage device of one embodiment of the present invention to Target1_1, the reliability of the storage device can be improved. Furthermore, the integration degree of the storage device can be increased. Furthermore, the power consumption of the storage device can be reduced.

[0406] Furthermore, the storage device of one embodiment of the present invention has high operating speed and is advantageous in terms of data access, and therefore can be suitably used for Target1_2, which is rewritten more frequently than Target1. By applying the storage device of one embodiment of the present invention to Target1_2, the calculation efficiency of the storage device can be improved and power consumption can be reduced.

[0407] Another means for reducing power consumption is a configuration in which a storage device such as a DRAM or an FeRAM (including the semiconductor device of one embodiment of the present invention) is stacked on an arithmetic processing device such as a CPU, a GPU, or an NPU. A configuration in which an arithmetic processing device and a storage device are stacked is called a monolithic stack. By configuring the arithmetic processing device and the storage device as a monolithic stack, for example, the power consumption required for data access between the arithmetic processing device and the storage device can be significantly reduced. Therefore, by deploying information processing devices including supercomputers (also called high performance computers (HPCs)), computers, servers, and the like to which such a configuration is applied throughout the world, global warming can be suppressed.

[0408] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0409] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0410] Embodiment 5 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 33A to 34E.

[0411] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0412] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0413] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0414] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0415] [Electronic Component] FIG. 33A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 33A has a semiconductor device 981 inside a mold 984. FIG. 33A omits some parts in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.

[0416] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0417] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0418] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0419] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0420] 33B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0421] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0422] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0423] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0424] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0425] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0426] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array.

[0427] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0428] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 33B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0429] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0430] [Mainframe] Next, Fig. 34A shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 34A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0431] The computer 5620 can have the configuration shown in the perspective view in Fig. 34B, for example. In Fig. 34B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0432] PC card 5621 shown in Figure 34C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 34C illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, the following descriptions of semiconductor devices 5626, 5627, and 5628 can be referenced.

[0433] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0434] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0435] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0436] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0437] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0438] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0439] [Space Equipment] The semiconductor device according to one embodiment of the present invention is suitable for space equipment.

[0440] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, an OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in an environment where radiation may be incident. For example, an OS transistor is suitable for use in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0441] Fig. 34D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 34D illustrates a planet 6804 in space.

[0442] 34D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0443] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0444] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0445] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0446] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0447] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0448] Although an artificial satellite is given as an example of space equipment in this embodiment, the invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention is suitable for space equipment such as a spaceship, a space capsule, and a space probe.

[0449] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0450] [Data Center] The semiconductor device according to one embodiment of the present invention is suitable for a storage system applied to, for example, a data center. Data centers are required to perform long-term management of data, such as ensuring the immutability of data. Managing long-term data requires larger buildings, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply for maintaining the data, or ensuring cooling equipment required for maintaining the data.

[0451] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0452] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0453] Fig. 34E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 34E has multiple servers 7001sb as hosts 7001. It also has multiple storage devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.

[0454] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0455] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0456] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0457] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0458] Note that the semiconductor device of one embodiment of the present invention can reduce power consumption by applying it to any one or more of electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0459] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0460] In this example, a transistor according to one embodiment of the present invention was examined by device simulation using "Sentaurus Device" manufactured by Synopsys, Inc.

[0461] The transistors (transistors A, B, and C) assumed in the simulation are shown in Figures 35A1 to 35C2. Figures 35A1, 35B1, and 35C1 show cross-sectional views of transistors A, B, and C in the channel length direction (L direction), respectively, and Figures 35A2, 35B2, and 35C2 show cross-sectional views of transistors A, B, and C in the channel width direction (W direction), respectively. Transistors A to C are dual-gate transistors having gate electrodes on the top and bottom, but Figures 35A1 to 35C2 omit the bottom gate electrode (sometimes referred to as BGE) and bottom gate insulating layer (sometimes referred to as BGI).

[0462] In transistors A to C, the source and drain electrodes were assumed to be indium tin oxide (ITO) films with a thickness of 20 nm. The shortest distance between the source and drain electrodes was defined as L, the length of the top gate electrode (TGE) sandwiched between the source and drain electrodes in the channel length direction was defined as Lg, and the length of the semiconductor layer in the channel width direction was defined as W. The semiconductor layer was assumed to have a two-layer structure consisting of a 10-nm-thick indium gallium zinc oxide (IGZO) film and a 5-nm-thick indium oxide (InOx) film. The top gate insulating layer (TGI) was assumed to have a four-layer structure consisting of, from the semiconductor layer side, a 1-nm-thick hafnium oxide (HfOx) film, a 2-nm-thick silicon oxide (SiOx) film, a 2-nm-thick HfOx film, and a 1-nm-thick silicon nitride (SiNx) film. The BGI was assumed to have a three-layer structure consisting of a 20 nm thick SiOx film below the semiconductor layer, a 15 nm thick HfOx film below the SiOx film, and a 5 nm thick SiNx film below the HfOx film.

[0463] Transistor A corresponds to transistor 200 shown in FIG. 2B and includes an L-shaped first insulating layer (sometimes referred to as SW1) and a sidewall-shaped second insulating layer (sometimes referred to as SW2). The length of the portion where SW1 contacts the top surface of the source electrode or drain electrode was set to 10 nm. SW1 was assumed to be a SiNx film with a thickness of 5 nm, and SW2 was assumed to be a SiOx film with a thickness of 2 nm. SW1 and SW2 correspond to insulating layer 255 and insulating layer 256, respectively, described in Embodiment 1.

[0464] 7, and includes SW1. The length of the portion where SW1 contacts the top surface of the source electrode or drain electrode is 10 nm. SW1 is assumed to be a SiNx film with a thickness of 5 nm.

[0465] The transistor C differs from the transistors A and B in that it does not have the above-mentioned SW1 and SW2.

[0466] The lengths of L, Lg, and W of each of the transistors A to C are shown in Table 3, and other various parameters are shown in Table 4. Note that "S / D metal" in Table 4 refers to a conductive layer functioning as a source electrode or a drain electrode described in Example 2.

[0467]

[0468]

[0469] Simulations were performed on transistors A to C using the conditions shown in Tables 3 and 4. The calculation results for the cutoff frequency (fT) of each transistor are shown in FIG. 36. In FIG. 36, the horizontal axis represents the L [nm] of the transistor, and the vertical axis represents fT [GHz]. The triangular plots represent the results for transistor A, the circular plots represent the results for transistor B, and the square plots represent the results for transistor C. The larger the fT, the faster the operating speed of the transistor, which is preferable.

[0470] The results in FIG. 36 show that the operating speed is faster in the order of transistor A and transistor B. Transistor A, by including SW2, can reduce the parasitic capacitance between ITO and TGE, and can improve its operating speed compared to transistor B. Furthermore, by including SW2, transistor A can reduce Lg compared to transistor B. Therefore, transistor A can reduce the gate capacitance and improve its operating speed compared to transistor B.

[0471] According to one embodiment of the present invention, a transistor with high operating speed can be provided.

[0472] In this example, a transistor according to one embodiment of the present invention was examined by device simulation.

[0473] The transistors assumed in the simulation (transistors D, E, and F) are shown in Figures 37A1 to 37C2. Figures 37A1, 37B1, and 37C1 show cross-sectional views of transistors D, E, and F in the channel length direction (L direction), respectively, and Figures 37A2, 37B2, and 37C2 show cross-sectional views of transistors D, E, and F in the channel width direction (W direction), respectively. Transistors D to F are dual-gate transistors having gate electrodes on the top and bottom, but BGE and BGI are omitted in Figures 37A1 to 37C2.

[0474] Transistor D differs from transistor A of Example 1 in that it has a conductive layer (sometimes referred to as S / D metal) functioning as a source electrode or a drain electrode on ITO. The other configurations are the same as those of transistor A. Transistor D corresponds to the transistor shown in FIG. 10B.

[0475] Transistor E differs from transistor B of Example 1 in that it has source / drain metal on ITO. The other configurations are the same as those of transistor B. Transistor E corresponds to the transistor shown in FIG. 11B.

[0476] The transistor F differs from the transistor C of Example 1 in that it has source / drain metal on ITO. The other configurations are the same as those of the transistor C.

[0477] The S / D metal provided in the transistors D to F has the effect of reducing the wiring resistance of the source electrode or the drain electrode. On the other hand, a parasitic capacitance is formed between the S / D metal and the TGE, which may cause a decrease in operating speed.

[0478] The lengths of L, Lg, and W of transistor D can refer to the lengths of L, Lg, and W of transistor A shown in Table 3, the lengths of L, Lg, and W of transistor E can refer to the lengths of L, Lg, and W of transistor B shown in Table 3, and the lengths of L, Lg, and W of transistor F can refer to the lengths of L, Lg, and W of transistor C shown in Table 3. Table 4 can be referenced for other various parameters.

[0479] Simulations were performed on transistors D to F using the conditions shown in Tables 3 and 4. The calculation results for fT of each transistor are shown in FIG. 38. In FIG. 38, the horizontal axis represents the L [nm] of the transistor, and the vertical axis represents fT [GHz]. The triangular plots represent the results for transistor D, the circular plots represent the results for transistor E, and the square plots represent the results for transistor F.

[0480] The results in FIG. 38 show that the operating speed is faster in the order of transistors D, E, and F. Transistors D and E have SW1, which reduces the parasitic capacitance between the S / D metal and the TGE, allowing them to operate at a higher speed than transistor F. Furthermore, transistor D has SW2, which reduces the parasitic capacitance between the ITO and the TGE, allowing them to operate at a higher speed than transistors E and F. Furthermore, transistor D has SW2, which allows it to have a smaller Lg than transistors E and F. Therefore, transistor D can reduce the gate capacitance and operate at a higher speed than transistors E and F.

[0481] According to one embodiment of the present invention, a transistor with high operating speed can be provided.

[0482] 200: transistor, 205: conductive layer, 207: conductive layer, 208: insulating layer, 209: conductive layer, 210: insulating layer, 212: insulating layer, 214: insulating layer, 216: insulating layer, 221: insulating layer, 222: insulating layer, 224: insulating layer, 230: semiconductor layer, 230_1: semiconductor layer, 230_2: semiconductor layer, 240: conductive layer, 240a: conductive layer, 240b: conductive layer, 241: insulating layer, 242a: conductive layer, 242a1: conductive layer, 242a2: conductive layer, 242b: conductive layer, 242b1: conductive layer, 242b2: conductive layer, 242f: conductive layer, 250: insulating layer, 255: insulating layer, 25 6: insulating layer, 256a: insulating layer, 256b: insulating layer, 256c: insulating layer, 260: conductive layer, 275: insulating layer, 280: insulating layer, 282: insulating layer, 283: insulating layer, 284: insulating layer, 285: insulating layer, 289: opening, 290: opening, 310: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating layer, 316: conductive layer, 318: element isolation layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 453: conductive layer, 454: insulating layer, 460: Conductive layer, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920[1]: memory array, 920[2]: memory array, 920[m]: memory array, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 960: arithmetic unit, 961: substrate, 962: ALU, 962c: ALU controller, 963: instruction decoder, 964: interrupt controller, 965: timing controller, 966: register, 967: register controller, 968: bus interface, 969: cache, 969i: cache interface, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 980: electronic component, 981: semiconductor device,982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 991: interposer, 992: package board, 993: electrode, 994: semiconductor device, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5 627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network, 7010: storage system,

Claims

1. A semiconductor layer on a substrate; a first conductive layer and a second conductive layer spaced apart from each other on the semiconductor layer; a first insulating layer disposed on the first conductive layer and the second conductive layer and having a first opening; a second insulating layer disposed in contact with a portion of an upper surface of the first conductive layer and a portion of an upper surface of the second conductive layer at a position overlapping the first opening, and having a second opening overlapping the first opening; a third insulating layer in contact with a side surface of the first conductive layer and a portion of the upper surface of the semiconductor layer at the second opening; a fourth insulating layer in contact with a side surface of the second conductive layer and another portion of the upper surface of the semiconductor layer at the second opening; and a fifth insulating layer disposed in the first opening and in contact with another portion of the upper surface of the semiconductor layer, a side surface of the third insulating layer, a side surface of the fourth insulating layer, and a portion of the upper surface of the second insulating layer. a third conductive layer disposed on the fifth insulating layer in the first opening and having a region overlapping with the semiconductor layer via the fifth insulating layer, wherein the third insulating layer has a lower dielectric constant than the second insulating layer.

2. A semiconductor device according to claim 1, wherein the second insulating layer contains silicon and nitrogen, and the third insulating layer and the fourth insulating layer each contain silicon and oxygen.

3. A semiconductor device according to claim 1, wherein the second insulating layer contains aluminum and oxygen, and the third insulating layer and the fourth insulating layer each contain silicon and nitrogen.

4. A semiconductor device according to claim 1, wherein the side surface of the second insulating layer in the second opening is aligned or substantially aligned with the side surface of the first conductive layer facing the second conductive layer.

5. A semiconductor device according to any one of claims 1 to 4, wherein the semiconductor layer contains indium and oxygen, and the first conductive layer and the second conductive layer contain indium, tin, and oxygen.

6. Forming an island-shaped structure on a substrate, the island-shaped structure including a semiconductor layer and a first conductive layer on the semiconductor layer; forming a first insulating layer covering the island-shaped structure; forming a first opening in the first insulating layer that reaches the first conductive layer; forming a second insulating layer covering the first conductive layer and the first insulating layer; forming a second opening in the second insulating layer that overlaps with a part of the first opening; removing the part of the first conductive layer that overlaps with the second opening to expose the top surface of the semiconductor layer, and forming a second conductive layer and a third conductive layer from the first conductive layer; forming a third insulating layer covering the second insulating layer and the semiconductor layer; and forming a fourth insulating layer, a fifth insulating layer, and a sixth insulating layer from the third insulating layer by anisotropic etching. a fourth conductive layer is formed on the seventh insulating layer; and a top surface of the first insulating layer is exposed by chemical mechanical polishing, thereby leaving the seventh insulating layer and the fourth conductive layer in the first opening.

Images