Hetero-junction bipolar transistor

Abstract

This HBT comprises a collector layer (103) composed of a compound semiconductor formed on a substrate (101), a base layer (104) composed of a compound semiconductor formed on the collector layer (103), and an emitter layer (105) that is formed on the base layer (104) and is composed of a compound semiconductor different from that of the base layer (104). The HBT also comprises a collector electrode (111) electrically connected to the collector layer (103), a base electrode (112) formed on the base layer (104) around the emitter layer (105), and an emitter electrode (113) formed on an emitter cap layer (106). The HBT furthermore comprises an electric field application electrode (114) for applying an electric field to the collector layer (103).

Description

heterojunction bipolar transistor

[0001] The present invention relates to a heterojunction bipolar transistor.

[0002] Heterojunction bipolar transistors (HBTs) using indium phosphide (InP)-based materials are excellent in terms of speed and power output, and are particularly suitable for large-capacity optical communication front-end ICs and ICs for beyond 5G wireless communications, which require ultra-high frequency operation. To enhance the competitiveness of this type of transistor, it is necessary to continuously improve the operating speed of HBTs.

[0003] In particular, to improve the maximum oscillation frequency, which is a required high-frequency characteristic index for the above-mentioned applications, it is effective to reduce the intrinsic collector capacitance, the parasitic collector capacitance, and the base resistance. To reduce these, efforts are being made to reduce the emitter width and the width of the base-collector columnar portion.

[0004] However, with existing technology, the width of the base-collector columnar portion has been reduced to a level approaching its limit, making it difficult to reduce the collector capacitance and improve high-frequency characteristics simply by miniaturization.

[0005] For example, a technology has been proposed in which the base electrode is positioned as close as possible to the emitter layer, sandwiching the emitter layer between them, so as to surround the outer periphery of the emitter in order to reduce base resistance (Non-Patent Document 1). In this HBT structure, a significant undercut is created during the etching process in the process of forming the base and collector layers directly below the base electrode, so that the width of the columnar structure (mesa structure) of the base and collector is wider than the width of the emitter layer and is minimized while still ensuring an area in contact with the base electrode, thereby reducing the collector parasitic capacitance and achieving high high-frequency characteristics.

[0006] AM Arabhavi et al., “THz InP / GaAsSb DHBTs with Record favg=800 GHz: Characterization to 330 GHz,” Proc. 2023 IEEE Electron Device Meeting (IEDM), San Francisco, Dec. 2023. Doi: 10.1109 / IEDM45741.2023.10413850.

[0007] However, in the conventional HBT structure described above, the contact width between the base electrode and base layer is only about 40 nm, making it structurally difficult to further reduce the base-collector mesa width by etching. Even if it were possible to reduce it, the contact area between the base layer and base electrode would be reduced, increasing the contact resistance of the base electrode and offsetting the reduction in collector parasitic capacitance, or in some cases, potentially degrading high-frequency characteristics. Thus, it is not easy to further reduce collector parasitic capacitance and improve high-frequency characteristics by simply reducing the base-collector mesa width.

[0008] The present invention has been made to solve the above problems, and has as its object to improve high frequency characteristics by reducing the collector parasitic capacitance without reducing the width of the base and collector.

[0009] A heterojunction bipolar transistor according to the present invention includes a collector layer made of a compound semiconductor formed on a substrate, a base layer made of a compound semiconductor formed on the collector layer, an emitter layer formed on the base layer and made of a compound semiconductor different from that of the base layer, an emitter cap layer made of a compound semiconductor formed on the emitter layer, a collector electrode connected to the collector layer, a base electrode formed on the base layer around the emitter layer, an emitter electrode formed on the emitter cap layer, and an electric field application electrode that applies an electric field to the collector layer.

[0010] As described above, according to the present invention, since an electric field applying electrode for applying an electric field to the collector layer is provided, the collector parasitic capacitance can be reduced and high frequency characteristics can be improved without reducing the widths of the base and collector.

[0011] FIG. 1A is a cross-sectional view showing a configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 1B is a cross-sectional view showing a configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2A is a cross-sectional view showing a state of a heterojunction bipolar transistor in an intermediate step for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2B is a cross-sectional view showing a state of a heterojunction bipolar transistor in an intermediate step for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2C is a cross-sectional view showing a state of a heterojunction bipolar transistor in an intermediate step for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2D is a cross-sectional view showing a state of a heterojunction bipolar transistor in an intermediate step for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2E is a cross-sectional view showing a state of a heterojunction bipolar transistor in an intermediate step for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2F is a cross-sectional view showing a state of a heterojunction bipolar transistor in an intermediate step for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2G is a cross-sectional view showing a state of a heterojunction bipolar transistor in an intermediate step for explaining a manufacturing method of a heterojunction bipolar transistor according to an embodiment of the present invention. 2H, 2I, and 2J are cross-sectional views showing the state of a heterojunction bipolar transistor in an intermediate step for explaining a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention.

[0012] Hereinafter, a heterojunction bipolar transistor (HBT) according to an embodiment of the present invention will be described with reference to FIGS. 1A and 1B.

[0013] This HBT first includes a collector layer 103 made of a compound semiconductor formed on a substrate 101, a base layer 104 made of a compound semiconductor formed on the collector layer 103, and an emitter layer 105 formed on the base layer 104 and made of a compound semiconductor different from that of the base layer 104. Fig. 1A shows a cross section taken along a plane perpendicular to a first direction, and Fig. 1B shows a cross section taken along a plane perpendicular to a second direction.

[0014] The HBT also includes an emitter cap layer 106 made of a compound semiconductor formed on the emitter layer 105. In this embodiment, the collector layer 103 is formed on a sub-collector layer 102 formed on the substrate 101.

[0015] The collector layer 103 and the base layer 104 have the same area, and their laminated structure forms a first columnar section that is rectangular in plan view when viewed from the normal direction to the plane of the substrate 101. The emitter layer 105 and the emitter cap layer 106 have the same area, and their laminated structure forms a second columnar section that is rectangular in plan view when viewed from the normal direction to the plane of the substrate 101. The second columnar section has a smaller area in plan view than the first columnar section. The first columnar section has a rectangular (planar shape) shape in which the length in a first direction is longer than the length in a second direction perpendicular to the first direction when viewed from the normal direction to the plane of the substrate 101.

[0016] The substrate 101 may be made of, for example, InP doped with Fe to give it high resistance. The subcollector layer 102 may be made of, for example, InGaAs doped with a high concentration of n-type impurities. The subcollector layer 102 may have a two-layer structure consisting of a layer made of InP on the substrate 101 side and a layer made of InGaAs formed on top of the layer made of InP.

[0017] The collector layer 103 may be made of, for example, InP doped with n-type impurities. The base layer 104 may be made of GaAsSb doped with a high concentration of p-type impurities. The emitter layer 105 may be made of InP doped with a low concentration of n-type impurities. The emitter cap layer 106 may be made of InGaAs doped with a high concentration of n-type impurities.

[0018] The HBT also includes a collector electrode 111 electrically connected to the collector layer 103, a base electrode 112 formed on the base layer 104 around the emitter layer 105, and an emitter electrode 113 formed on the emitter cap layer 106.

[0019] The collector electrode 111 is formed on the sub-collector layer 102 around the collector layer 103 and is electrically connected to the collector layer 103 via the sub-collector layer 102. The base electrode 112 is formed on the base layer 104, surrounding the outer periphery of the emitter layer 105 to reduce base resistance. The base electrode 112 also has a base pad electrode 112a in a region above the first columnar portion extending in the first direction. The base pad electrode 112a is formed wider in the first direction in plan view than the other regions of the base electrode 112 for connection to upper-layer wiring, and functions as a pad portion.

[0020] The HBT according to the embodiment further includes an electric field application electrode 114 that applies an electric field to the collector layer 103. The electric field application electrode 114 is disposed on a side of the collector layer 103. For example, the electric field application electrode 114 can be disposed on the side of the collector layer 103 so as to surround the periphery of the collector layer 103. For example, a collector insulating layer 122 can be formed so as to surround the side of the collector layer 103, and the electric field application electrode 114 can be formed around the periphery of the collector layer 103 via the collector insulating layer 122. The electric field application electrode 114 can also include an electrode pad 114a in a region on the sub-collector layer 102 extending in the first direction. The electric field application electrode 114 can be made of, for example, Pt and Pd. The collector insulating layer 122 can be made of, for example, SiN and Al2O3.

[0021] In this embodiment, an inner insulating layer 121 is provided, which is formed to cover the side surfaces of the base layer 104, the emitter layer 105, and the emitter cap layer 106 and to cover the base electrode 112. A collector insulating layer 122 is formed to cover the side surfaces of the collector layer 103 and the inner insulating layer 121. The inner insulating layer 121 can be formed so that its outer diameter is slightly wider than that of the first columnar section (collector layer 103, base layer 104). The electric field application electrode 114 is formed around the collector layer 103, the base layer 104, the emitter layer 105, and the emitter cap layer 106, with the inner insulating layer 121 and the collector insulating layer 122 interposed therebetween. The inner insulating layer 121 can be made of, for example, benzocyclobutene (BCB), a type of organic resin.

[0022] Applying a voltage (mainly a negative bias) to the electric field application electrode 114 can promote depletion of the side surfaces of the collector layer 103, thereby reducing the collector capacitance. Furthermore, lateral diffusion of electrons injected from the base layer 104 as they travel through the collector layer 103 can be suppressed, thereby shortening the collector transit time. This means that high-frequency characteristics can be improved. By constructing the electric field application electrode 114 from a material with a high work function, such as Pt or Pd, the potential of the side surfaces of the collector layer 103 in a thermal equilibrium state can be increased, thereby promoting depletion of the collector layer 103 at a lower voltage.

[0023] The above-described effect is particularly remarkable under bias conditions where the collector voltage is low, causing insufficient depletion of the collector layer 103. In other words, the bias range of the collector voltage that allows high-speed operation of the transistor can be expanded to the low bias side, improving the degree of freedom in circuit design.

[0024] By applying a voltage to the electric field application electrode 114 described above, the surface potential of the collector layer 103 can be stabilized and the surface leakage current can be reduced, thereby suppressing a decrease in breakdown voltage, particularly in miniaturized HBTs, which are greatly affected by the surface leakage current of the collector layer 103.

[0025] In this example, the electric field application electrode 114 is formed in the thickness direction, from the collector layer 103 to the base layer 104, the emitter layer 105, and the emitter cap layer 106, but in this region, the inner insulating layer 121 is formed thick in a direction parallel to the plane of the substrate 101. Therefore, the above-mentioned action caused by the application of a voltage to the electric field application electrode 114 can be made to have almost no effect on the base layer 104, the emitter layer 105, and the emitter cap layer 106. In the above-mentioned configuration, the inner insulating layer 121 is provided, the collector insulating layer 122 is formed on the outside of this, and the electric field application electrode 114 is formed from the collector layer 103 to the emitter cap layer 106, and this configuration is easy to manufacture.

[0026] Next, a method for manufacturing a heterojunction bipolar transistor according to the embodiment will be described with reference to FIGS. 2A to 2G.

[0027] First, as shown in FIG. 2A, a sub-collector forming layer 202, a collector forming layer 203, a base forming layer 204, an emitter forming layer 205, and an emitter cap forming layer 206 are laminated in this order on a substrate 101.

[0028] For example, first, the subcollector-forming layer 202 is formed by sequentially growing crystals (epitaxial growth) of InP and InGaAs doped with a high concentration of n-type impurities. Next, the collector-forming layer 203 is formed by growing crystals of InP doped with n-type impurities. Next, the base-forming layer 204 is formed by growing crystals of GaAsSb doped with a high concentration of p-type impurities. Next, the emitter-forming layer 205 is formed by growing crystals of InP doped with a low concentration of n-type impurities. Next, the emitter cap-forming layer 206 is formed by growing crystals of InGaAs doped with a high concentration of n-type impurities.

[0029] The thickness, doping concentration, and composition of each of the above-mentioned layers are set to optimal values ​​to obtain the desired electrical performance. Each of the above-mentioned layers can be formed by well-known methods such as metal organic chemical vapor deposition and molecular beam epitaxy.

[0030] 2B and 2C, the emitter electrode 113, the emitter cap layer 106, the emitter layer 105, the base electrode 112, the base pad electrode 112a, and the base layer 104 are formed, respectively. These can be formed by well-known methods for manufacturing semiconductor devices.

[0031] For example, each electrode can be formed by forming a lift-off mask having openings at the positions where each electrode is to be formed, then depositing metal to be used as the electrode material, and then removing the lift-off mask (lift-off). Alternatively, the emitter cap layer 106 and the emitter layer 105 can be formed by dry-etching or wet-etching the emitter cap-forming layer 206 and the emitter-forming layer 205 using a predetermined resist pattern formed by lithography as a mask. Similarly, the base layer 104 can be formed by dry-etching or wet-etching the base-forming layer 204 using a predetermined resist pattern formed by lithography as a mask.

[0032] The effects of the heterojunction bipolar transistor according to the above-described embodiment are exerted regardless of the widths of the base layer 104 and the collector layer 103 formed in a later process. However, to obtain a greater effect, i.e., a higher operating speed, it is desirable to reduce the widths of the base layer 104 and the collector layer 103 (first columnar portion) as much as possible.

[0033] 2D , an insulating film 207 is formed on the collector-forming layer 203, covering the base layer 104, the emitter layer 105, the emitter cap layer 106, the base electrode 112 (base pad electrode 112 a), and the emitter electrode 113. For example, the insulating film 207 can be formed by spin-coating BCB and curing it by heat treatment.

[0034] BCB can form a relatively good interface with the base layer 104. In addition, the BCB coating film flows during the heat treatment process, flattening the steps caused by the base layer 104, emitter layer 105, emitter cap layer 106, base electrode 112 (base pad electrode 112a), and emitter electrode 113, allowing the insulating film 207 to be formed with a flat surface. This makes it relatively easy to form the inner insulating layer 121 in a later process.

[0035] Next, the insulating film 207 is processed to form the inner insulating layer 121, as shown in Fig. 2E. First, the insulating film 207, which has been formed with a flat surface, is etched back to expose the upper part of the emitter electrode 113 from the surface of the insulating film 207.

[0036] Next, a mask pattern having an area somewhat larger than that of the base layer 104 is formed on the emitter electrode 113, the emitter cap layer 106, the emitter layer 105, the base electrode 112 (base pad electrode 112a), and the base layer 104. The mask pattern is formed so that the base layer 104 is positioned inside the outer periphery of this mask pattern. By etching the insulating film 207 using the mask pattern formed in this way as a mask, the inner insulating layer 121 can be formed as shown in FIG. 2E.

[0037] Next, the collector-forming layer 203 is processed to form the collector layer 103, as shown in FIG. 2F . For example, the collector-forming layer 203 can be etched using a predetermined resist pattern to form the collector layer 103. For example, the collector-forming layer 203 made of InP can be processed by wet etching using a hydrochloric acid-based etchant. Alternatively, the collector-forming layer 203 can be etched using the inner insulating layer 121 as a mask to form the collector layer 103. The collector-forming layer 203 is etched to form an undercut, and the area of ​​the collector layer 103 is processed to be equal to the area of ​​the base layer 104.

[0038] Here, the inner insulating layer 121 made of BCB does not have a particularly strong adhesion to the layer made of InP. Therefore, in the above-described wet etching, the etchant is more likely to enter the interface between the lower surface of the inner insulating layer 121 and the collector-forming layer 203 than the outer peripheral edge of the inner insulating layer 121. As a result, undercuts in the collector-forming layer 203 are formed evenly from the interface to the center of the side surface. As a result, the side surface of the collector layer 103 can be formed to be approximately flat in cross section.

[0039] Next, as shown in FIG. 2G , an insulating film 208 is formed to cover the side surfaces of the collector layer 103, the side surfaces of the inner insulating layer 121, the surface of the emitter electrode 113 protruding from the upper surface of the inner insulating layer 121, and the surface of the collector-forming layer 203. The insulating film 208 can be formed to conform to the surfaces of the above-mentioned components. The insulating film 208 can be made of a material such as SiN or Al2O3, which can form a relatively good interface with InP-based materials, e.g., does not form interface states. Furthermore, these materials have a high dielectric constant and can form a dense, thinner insulating layer. For example, the insulating film 208 can be formed by depositing these materials using CVD or atomic layer deposition.

[0040] The insulating film 208 is a film for forming the collector insulating layer 122, and its thickness affects the efficiency of modulation of the lateral potential of the collector layer 103 by the electric field application electrode 114. Therefore, it is desirable to form the insulating film 208 as thin as possible, as long as the insulation required for the design is obtained. For example, it is desirable that the insulating film 208 have a thickness that is typically ¼ of the thickness of the collector layer 103, that is, approximately 10 nm to 50 nm.

[0041] Next, as shown in FIG. 2H , electric field-applying electrode-forming layer 209 is formed to cover the outer surface of insulating film 208. The electric field-applying electrode-forming layer 209 can be formed by depositing a metal for use as electric field-applying electrode 114, for example, by sputtering. Electric field-applying electrode-forming layer 209 can be made of a metal such as Pt or Pd that has a high work function and minimally functions as electric field-applying electrode 114. By using this metal, the potential on the side surface of collector layer 103 made of InP in a thermal equilibrium state can be increased, and depletion of collector layer 103 can be promoted at a lower voltage.

[0042] It should be noted that Pt and Pd are materials that are difficult to process, and the electric field applying electrode 114 only applies a constant voltage, and in principle no current flows except when a voltage is applied. For these reasons, the electric field applying electrode forming layer 209 can be made thin, for example, to a thickness of about 10 nm to 20 nm.

[0043] Next, the electric field-applying electrode-forming layer 209 and insulating film 208 around the collector layer 103 are etched away to form the collector insulating layer 122 and electric field-applying electrode 114, as shown in FIGS. 2I and 2J. The upper surface of the sub-collector-forming layer 202 around the collector layer 103 is also exposed. For example, a mask pattern is formed to cover the collector insulating layer 122 and the portions to become the electric field-applying electrode 114, and the electric field-applying electrode-forming layer 209 made of Pt or Pd is etched by ion milling using argon, for example. When the electric field-applying electrode-forming layer 209 is made of another metal, the electric field-applying electrode 114 can be formed by dry etching using an appropriate etching gas.

[0044] Furthermore, using the above-described mask pattern as a mask, the insulating film 208 is etched by dry etching using a fluorine-based gas, thereby forming the collector insulating layer 122. Note that in the above-described patterning, some of the electric field-applying electrode-forming layer 209 and the insulating film 208 remain on the side surfaces of the emitter electrode 113, but this does not affect the operation of the HBT or the operation and effects of the electric field-applying electrode 114.

[0045] After forming the collector insulating layer 122 and the electric field application electrode 114 as described above, the collector electrode 111 is formed on the sub-collector forming layer 202, and the sub-collector forming layer 202 is patterned to form the sub-collector layer 102, thereby obtaining the HBT shown in FIGS. 1A and 1B.

[0046] As described above, according to the embodiment of the present invention, an electric field application electrode that applies an electric field to the collector layer is provided, so that the collector parasitic capacitance can be reduced and high frequency characteristics can be improved without reducing the widths of the base and collector.

[0047] While the above description has been given using an npn-type InP / GaAsSb-based HBT on an InP substrate, which is a promising example for realizing ultra-high-speed integrated circuits, the present invention is not limited to this configuration. For example, the present invention is also effective for an InP / InGaAs HBT or an InP-based HBT formed on a heat dissipation substrate made of SiC. The present invention is not limited to the above-described embodiments, and it is clear that many modifications and combinations can be made by those skilled in the art within the technical spirit of the present invention.

[0048] 101...substrate, 102...sub-collector layer, 103...collector layer, 104...base layer, 105...emitter cap layer, 106...emitter cap layer, 111...collector electrode, 112...base electrode, 112a...base pad electrode, 113...emitter electrode, 114...electric field application electrode, 114a...electrode pad, 121...inner insulating layer, 122...collector insulating layer.

Claims

1. A heterojunction bipolar transistor comprising: a collector layer made of a compound semiconductor formed on a substrate; a base layer made of a compound semiconductor formed on the collector layer; an emitter layer formed on the base layer and made of a compound semiconductor different from that of the base layer; an emitter cap layer made of a compound semiconductor formed on the emitter layer; a collector electrode connected to the collector layer; a base electrode formed on the base layer around the emitter layer; an emitter electrode formed on the emitter cap layer; and an electric field application electrode that applies an electric field to the collector layer.

2. A heterojunction bipolar transistor according to claim 1, wherein said electric field application electrode is disposed on a side of said collector layer.

3. A heterojunction bipolar transistor according to claim 2, wherein the electric field application electrode is disposed so as to surround the periphery of the collector layer.

4. A heterojunction bipolar transistor according to claim 2 or 3, further comprising a collector insulating layer formed so as to surround the side surfaces of the collector layer, and the electric field application electrode is formed around the collector layer via the collector insulating layer.

5. A heterojunction bipolar transistor according to claim 4, further comprising an inner insulating layer formed to cover the side surfaces of the base layer, the emitter layer, and the emitter cap layer and to cover the base electrode, the collector insulating layer being formed to cover the side surfaces of the collector layer and the inner insulating layer, and the electric field application electrode being formed around the collector layer, the base layer, the emitter layer, and the emitter cap layer via the inner insulating layer and the collector insulating layer.

6. A heterojunction bipolar transistor according to claim 5, wherein the outer diameter of said inner insulating layer is formed to be wider than the collector layer and the base layer.

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