Semiconductor memory device

Abstract

Provided is a layout structure that suppresses, for a mask read only memory (ROM), a reduction in the operating speed without an increase in the area. In a semiconductor menory device, a memory cell (M00) is provided with a nanosheet field effect transistor (FET) in which the gate is connected to a word line (41) and the drain is connected to a bit line (21), and stores data depending on the presence or absence of a connection between the source of the nanosheet FET and ground power supply wiring (11). The surface of a nanosheet (32a) on a nanosheet (36a) side in the X direction is exposed from the gate wiring (41). The bit line (21) is formed in a wiring layer on the front surface side of the nanosheet FET, and the ground power supply wiring (11) is formed in a wiring layer on the back surface side of the nanosheet FET.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device, and more particularly to a layout structure of a mask ROM (Read Only Memory).

[0002] A mask ROM includes an array of memory cells, each of which is programmed and manufactured to have a fixed data state. The transistors that make up the memory cells are provided between a bit line and VSS, and the word line is connected to the gate. Bit data "1" or "0" is stored depending on whether the source or drain is connected to the bit line or VSS. The presence or absence of a connection is achieved, for example, by the presence or absence of a contact or via.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved increased integration density, reduced operating voltage, and improved operating speed through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, three-dimensional transistors, such as finFETs (field-effect transistors) and nanosheet FETs, which change the transistor structure from the conventional planar type to a three-dimensional type, have been actively researched.

[0004] Patent Document 1 discloses a layout structure of a ROM memory cell using a fork sheet FET in which the gate electrode is forked.

[0005] International Publication No. 2021 / 125138

[0006] In the mask ROM described in Patent Document 1, the power supply wiring is provided in the same layer as the bit lines, so the wiring width of the bit lines cannot be increased. This increases the wiring resistance, reducing the operating speed. Furthermore, the wiring width of the power supply wiring cannot be increased. This increases the wiring resistance, reducing the operating speed and stability. Furthermore, the closer the distance between the bit lines and the power supply wiring, the larger the parasitic capacitance, reducing the operating speed.

[0007] The present disclosure provides a layout structure for a mask ROM that suppresses a decrease in operating speed without increasing the area.

[0008] In a first aspect of the present disclosure, a semiconductor memory device includes first and second ROM (Read Only Memory) memory cells adjacent to each other in a first direction, a word line extending in the first direction, first and second bit lines extending in a second direction perpendicular to the first direction, and first and second ground power supply wirings extending in the second direction, and the first ROM memory cell includes a first nanosheet as a channel region, a gate connected to the word line, and a drain connected to the first bit line. the second ROM memory cell includes a second nanosheet FET having a second nanosheet as a channel region, a gate connected to the word line, and a drain connected to the second bit line, and stores data depending on whether or not the source of the second nanosheet FET is electrically connected to the second ground power supply wiring; the word line includes a first gate wiring surrounding the periphery of the first nanosheet in the first direction and a third direction perpendicular to the first and second directions, and a second gate wiring surrounding the periphery of the second nanosheet in the first direction and the third direction; The first and second nanosheets face each other in the first direction, and the surface of the first nanosheet facing the second nanosheet in the first direction is exposed from the first gate wiring, and the surface of the second nanosheet facing the first nanosheet in the first direction is exposed from the second gate wiring, the first and second bit lines are formed in a first wiring layer on the front side of the first and second nanosheet FETs and overlap with the first and second nanosheet FETs, respectively, in a planar view, and the first and second ground power wirings are formed in a second wiring layer on the back side of the first and second nanosheet FETs and overlap with the first and second nanosheet FETs, respectively, in a planar view.

[0009] According to this aspect, the semiconductor memory device includes first and second ROM memory cells adjacent to each other in a first direction. The first ROM memory cell includes a first nanosheet FET having a first nanosheet as a channel region, and the second ROM memory cell includes a second nanosheet FET having a second nanosheet as a channel region. The first and second nanosheets face each other in the first direction, and the surface of the first nanosheet facing the second nanosheet in the first direction is exposed from the first gate wiring, while the surface of the second nanosheet facing the first nanosheet in the first direction is exposed from the second gate wiring. In other words, the first and second nanosheet FETs are fork-sheet FETs. The first and second bit lines are formed in a first wiring layer on the front side of the first and second nanosheet FETs, and the first and second ground power supply wirings are formed in a second wiring layer on the back side of the first and second nanosheet FETs. This allows the wiring width of the first and second bit lines to be increased, thereby improving operating speed. Furthermore, since the width of the first and second ground power supply wirings can be increased, the operating speed and stability can be improved.Furthermore, since the parasitic capacitance between the bit lines and the power supply wirings can be reduced, the operating speed can be improved.

[0010] In a second aspect of the present disclosure, a semiconductor memory device includes first and second ROM (Read Only Memory) memory cells adjacent to each other in a first direction, a word line extending in the first direction, first and second bit lines extending in a second direction perpendicular to the first direction, and first and second ground power supply wirings extending in the second direction, and the first ROM memory cell includes a first nanosheet as a channel region, a gate connected to the word line, and a drain connected to the first bit line. the second ROM memory cell includes a second nanosheet FET having a second nanosheet as a channel region, a gate connected to the word line, and a drain connected to the second bit line, and stores data depending on whether or not the source of the second nanosheet FET is electrically connected to the second ground power supply wiring; the word line includes a first gate wiring surrounding the periphery of the first nanosheet in the first direction and a third direction perpendicular to the first and second directions, and a second gate wiring surrounding the periphery of the second nanosheet in the first direction and the third direction; The first and second nanosheets face each other in the first direction, and the surface of the first nanosheet facing the second nanosheet in the first direction is exposed from the first gate wiring, and the surface of the second nanosheet facing the first nanosheet in the first direction is exposed from the second gate wiring, the first and second ground power wirings are formed in a first wiring layer on the front side of the first and second nanosheet FETs and overlap with the first and second nanosheet FETs, respectively, in a planar view, and the first and second bit lines are formed in a second wiring layer on the back side of the first and second nanosheet FETs and overlap with the first and second nanosheet FETs, respectively, in a planar view.

[0011] According to this aspect, the semiconductor memory device includes first and second ROM memory cells adjacent to each other in a first direction. The first ROM memory cell includes a first nanosheet FET having a first nanosheet as a channel region, and the second ROM memory cell includes a second nanosheet FET having a second nanosheet as a channel region. The first and second nanosheets face each other in the first direction, and the surface of the first nanosheet facing the second nanosheet in the first direction is exposed from the first gate wiring, while the surface of the second nanosheet facing the first nanosheet in the first direction is exposed from the second gate wiring. In other words, the first and second nanosheet FETs are fork-sheet FETs. The first and second ground power supply wirings are formed in a first wiring layer on the front side of the first and second nanosheet FETs, and the first and second bit lines are formed in a second wiring layer on the back side of the first and second nanosheet FETs. This allows the wiring width of the first and second bit lines to be increased, thereby improving operating speed. Furthermore, since the width of the first and second ground power supply wirings can be increased, the operating speed and stability can be improved.Furthermore, since the parasitic capacitance between the bit lines and the power supply wirings can be reduced, the operating speed can be improved.

[0012] In a third aspect of the present disclosure, a semiconductor memory device includes first and second ROM (Read Only Memory) memory cells adjacent to each other in a first direction, a word line extending in the first direction, first and second bit lines extending in a second direction perpendicular to the first direction, and first and second ground power wirings extending in the second direction, and the first ROM memory cell has a first nanosheet as a channel region, and is a first nanosheet FET (Field Effect Transistor) having a gate connected to the word line, a source connected to the first bit line or the first ground power wiring, and a drain connected to the first bit line or the first ground power wiring.The second ROM memory cell includes a second nanosheet FET having a second nanosheet as a channel region, a gate connected to the word line, a source connected to the second bit line or the second ground power wiring, and a drain connected to the second bit line or the second ground power wiring, and stores data depending on whether the source and drain of the second nanosheet FET are connected to the same line or different lines of the second bit line and the second ground power wiring, and the second ROM memory cell includes a second nanosheet FET having a second nanosheet as a channel region, a gate connected to the word line, a source connected to the second bit line or the second ground power wiring, and a drain connected to the second bit line or the second ground power wiring, and stores data depending on whether the source and drain of the second nanosheet FET are connected to the same line or different lines of the second bit line and the second ground power wiring, and the word line includes a first gate wiring surrounding the periphery of the first nanosheet in the first direction and a third direction perpendicular to the first and second directions, and a second nanosheet FET having a gate connected to the second nanosheet in the first direction and a third direction perpendicular to the first and second directions. and a second gate wiring surrounding the outer periphery in the third direction, the first and second nanosheets facing each other in the first direction, the surface of the first nanosheet facing the second nanosheet in the first direction being exposed from the first gate wiring, the surface of the second nanosheet facing the first nanosheet in the first direction being exposed from the second gate wiring, the first and second bit lines being formed in either a first wiring layer on the front side of the first and second nanosheet FETs or a second wiring layer on the back side of the first and second nanosheet FETs, and overlapping with the first and second nanosheet FETs, respectively, in a planar view, and the first and second ground power wirings being formed in the other of the first wiring layer or the second wiring layer, and overlapping with the first and second nanosheet FETs, respectively, in a planar view.

[0013] According to this aspect, the semiconductor memory device includes first and second ROM memory cells adjacent to each other in a first direction. The first ROM memory cell includes a first nanosheet FET having a first nanosheet as a channel region, and the second ROM memory cell includes a second nanosheet FET having a second nanosheet as a channel region. The first and second nanosheets face each other in the first direction, and the surface of the first nanosheet facing the second nanosheet in the first direction is exposed from the first gate wiring, while the surface of the second nanosheet facing the first nanosheet in the first direction is exposed from the second gate wiring. In other words, the first and second nanosheet FETs are fork-sheet FETs. The first and second bit lines are formed in either a first wiring layer on the front side of the first and second nanosheet FETs or a second wiring layer on the back side of the first and second nanosheet FETs, and the first and second ground power supply wirings are formed in the other of the first wiring layer or the second wiring layer. Therefore, the wiring width of the first and second bit lines can be increased, thereby improving the operating speed. Also, the wiring width of the first and second ground power supply wiring can be increased, thereby improving the operating speed and operational stability. Furthermore, the parasitic capacitance of the bit lines and power supply wiring can be suppressed, thereby improving the operating speed.

[0014] According to the present disclosure, it is possible to provide a layout structure for a mask ROM that suppresses a decrease in operating speed without increasing the area.

[0015] 2A to 2C are cross-sectional views of the layout structure of FIG. 2. A plan view showing an example of the layout structure of a semiconductor memory device according to a first modification of the first embodiment. A plan view showing an example of the layout structure of a semiconductor memory device according to a second modification of the first embodiment. A plan view showing an example of the layout structure of a semiconductor memory device according to a third modification of the first embodiment. A plan view showing an example of the layout structure of a semiconductor memory device according to a fourth modification of the first embodiment. A circuit diagram showing the configuration of a contact-type mask ROM as an example of a semiconductor memory device according to a second embodiment. A plan view showing an example of the layout structure of a semiconductor memory device according to a first modification of the second embodiment.

[0016] Hereinafter, embodiments will be described with reference to the drawings. In this specification, "VDD" and "VSS" refer to power supply voltages or the power supply itself. In addition, in this specification, the source and drain regions of a transistor are referred to as the "nodes" of the transistor as appropriate. In other words, one node of a transistor refers to the source or drain of the transistor, and both nodes of a transistor refer to the source and drain of the transistor.

[0017] 1 is a circuit diagram showing the configuration of a contact-type mask ROM as an example of a semiconductor memory device. In the mask ROM shown in FIG. 1, whether the source of a memory cell transistor is connected to a ground line VSS via a contact or not corresponds to "0" or "1" in the stored data.

[0018] In FIG. 1, the mask ROM includes a memory cell array 3 , a column decoder 2 , and a sense amplifier 18 .

[0019] The memory cell array 3 is configured by arranging memory cells Mij (i = 0 to m, j = 0 to n) of N-type MOS transistors in a matrix. The gates of the memory cells Mij are connected to word lines WLi in common in the row direction, and the drains are connected to bit lines BLj in common in the column direction. The source of the memory cell Mij is connected to the ground potential VSS when the stored data is set to "0", and is not connected to the ground potential VSS when the stored data is set to "1".

[0020] The column decoder 2 is composed of N-type MOS transistors Cj, whose drains are all connected in common, whose gates are connected to respective column selection signal lines CLj, and whose sources are connected to respective bit lines BLj.

[0021] The sense amplifier 18 includes a precharge P-type MOS transistor 5, an inverter 8 that determines the output data of the memory cell Mij, and an inverter 9 that buffers the output signal of the inverter 8. A precharge signal NPR is input to the gate of the P-type MOS transistor 5, a power supply voltage VDD is supplied to the source, and the drain is connected to the common drain of the N-type MOS transistor Cj. The inverter 8 receives a signal SIN from the common drain of the N-type MOS transistor Cj and determines the output data of the memory cell Mij. The inverter 9 receives an output signal SOUT from the inverter 8 and outputs the stored data of the memory cell Mij.

[0022] The operation of the mask ROM of FIG. 1 will be described by taking as an example the case where data is read from memory cell M00.

[0023] First, among the column selection signal lines CLj, CL0 is set to high level and the other CL1 to CLn are set to low level. As a result, among the transistors constituting the column decoder 2, C0 is turned on and the other C1 to Cn are turned off. Also, the word line WL0 is transitioned from low level, which indicates a non-selected state, to high level, which indicates a selected state.

[0024] Next, the precharge signal NPR is changed from high level to low level, and the precharge P-type MOS transistor 5 is turned on.

[0025] Here, when the source of memory cell M00 is connected to ground potential VSS, the current capability of memory cell M00 is greater than that of precharge P-type MOS transistor 5, and therefore input signal SIN of inverter 8 has a voltage lower than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 is held at a high level, and output signal OUT of inverter 9 is held at a low level.

[0026] On the other hand, when the source of memory cell M00 is not connected to the ground potential VSS, bit line BL0 is charged by precharge P-type MOS transistor 5, and input signal SIN of inverter 8 becomes a voltage higher than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 becomes low level, and output signal OUT of inverter 9 becomes high level.

[0027] That is, when the source of the memory cell is connected to VSS, a low level is output (storage data "0"), and when the source of the memory cell is not connected to VSS, a high level is output (storage data "1").

[0028] In addition, the mask ROM of the present disclosure may store the value of each memory cell by connecting / disconnecting the memory cell to VSS, or by connecting / disconnecting the memory cell to a bit line.

[0029] 2 and 3 are diagrams showing an example of the layout structure of the mask ROM according to the first embodiment, with Fig. 2 being a plan view of the memory cell array and Figs. 3(a) to 3(c) being cross-sectional views in the horizontal direction in a plan view of the memory cell array of Fig. 2. Fig. 3(a) is a cross-section along line X1-X1', Fig. 3(b) is a cross-section along line X2-X2', and Fig. 3(c) is a cross-section along line X3-X3'.

[0030] 2 and other plan views, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). Note that the X direction is the direction in which the gate wiring and word lines extend, and the Y direction is the channel direction and the direction in which the bit lines extend.

[0031] In each drawing of the first embodiment, the letter "D" is attached to the contact that determines the stored value of the memory cell.

[0032] FIG. 2 corresponds to a layout for (4×2) bits. Dashed lines indicate the frame of a memory cell for one bit. That is, FIG. 2 shows a configuration in which four memory cells are arranged in the X direction and two in the Y direction. In the Y direction, the memory cells are arranged in an inverted manner in every other column. In FIG. 2, the two memory cells from the left in the bottom row of the drawing correspond to memory cells M00 and M01 in the circuit diagram of FIG. 1, and the two memory cells from the left in the top row of the drawing correspond to memory cells M10 and M11 in the circuit diagram of FIG. 1. The structure of the memory cells will be explained below mainly using memory cells M00 and M01 as an example.

[0033] 2 and 3, power supply wirings 11, 12, 13, and 14 extending in the Y direction are formed in the BM0 wiring layer. The BM0 wiring layer is a wiring layer provided on the back side of the transistors in the semiconductor chip. The power supply wirings 11, 12, 13, and 14 supply VSS.

[0034] In the M1 wiring layer, bit lines 21, 22, 23, and 24 extending in the Y direction are formed. The M1 wiring layer is a wiring layer located above the transistors in the semiconductor chip, i.e., on the surface side of the transistors. The bit lines 21, 22, 23, and 24 correspond to bit lines BL0, BL1, BL2, and BL3, respectively. The power supply wirings 11, 12, 13, and 14 and the bit lines 21, 22, 23, and 24 overlap each other in a plan view.

[0035] Here, in a semiconductor chip, the back side of a transistor refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the transistor are stacked, and the side on which local wiring, metal wiring, etc. connected to the transistor are stacked is called the front side of the transistor.

[0036] In the BM0 wiring layer, the power supply wirings 11, 12, 13, and 14 are arranged at equal intervals. However, the arrangement of the power supply wirings 11, 12, 13, and 14 does not have to be at equal intervals. Furthermore, the power supply wirings 11, 12, 13, and 14 are formed for each bit string, but for example, the power supply wirings may be formed integrally for multiple bit strings.

[0037] Furthermore, in the M1 wiring layer, the bit lines 21, 22, 23, and 24 are arranged at equal intervals. This makes it possible to suppress performance variations because the load capacitance due to the inter-wiring capacitance is the same for all of the bit lines 21, 22, 23, and 24. However, the bit lines 21, 22, 23, and 24 do not have to be arranged at equal intervals.

[0038] An active region 31 that constitutes the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 11 and below the bit line 21. The active region 31 overlaps the power supply wiring 11 and the bit line 21 in a planar view. The active region 31 includes nanosheets 32a and 32b that become the channel of the N-type nanosheet FET. The active region 31 also includes portions 33a, 33b, and 33c that become the source or drain of the N-type nanosheet FET.

[0039] An active region 35 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 12 and below the bit line 22. The active region 35 overlaps the power supply wiring 12 and the bit line 22 in a planar view. The active region 35 includes nanosheets 36a and 36b that become the channel of the N-type nanosheet FET. The active region 35 also includes portions 37a, 37b, and 37c that become the source or drain of the N-type nanosheet FET.

[0040] Gate wirings 41 and 42 are formed extending in the X direction. The gate wiring 41 surrounds the outer periphery of the nanosheet 32a in the X direction and the Z direction via a gate insulating film (not shown). The gate wiring 41 serves as the gate of the memory cell M00. The gate wiring 42 surrounds the outer periphery of the nanosheet 36a in the X direction and the Z direction via a gate insulating film (not shown). The gate wiring 42 serves as the gate of the memory cell M01.

[0041] The surface of nanosheet 32a facing nanosheet 36a in the X direction is not covered by gate wiring 41 and is exposed from gate wiring 41. The surface of nanosheet 36a facing nanosheet 32a in the X direction is not covered by gate wiring 42 and is exposed from gate wiring 42. That is, memory cells M00 and M01 include fork-sheet FETs. This reduces the space required between nanosheet 32a and nanosheet 36a, allowing the distance d1 between nanosheet 32a and nanosheet 36a to be reduced (d1<d2). This allows for a smaller semiconductor memory device.

[0042] The gate wiring 41 and the gate wiring 42 are connected by a bridge portion 43 formed between the gate wiring 41 and the gate wiring 42. The bridge portion 43 is an example of a gate connection portion. The gate wirings 41 and 42 are connected to other gate wirings aligned in a row in the X direction to form a word line WL0. Similarly, the word line WL1 also includes other gate wirings aligned in a row in the X direction.

[0043] Dummy gate wirings 44a and 44b are formed to extend in the X direction. The dummy gate wirings 44a and 44b supply VSS.

[0044] Local interconnects 51 and 52 are formed extending in the X direction. In FIG. 2 and other drawings, the local interconnect is denoted as LI. The local interconnect 51 is connected to a portion 33b of the active region 31 that serves as a common drain for the nanosheet FETs provided in the memory cells M00 and M10. The local interconnect 52 is connected to a portion 37b of the active region 35 that serves as a common drain for the nanosheet FETs provided in the memory cells M01 and M11.

[0045] The local wiring 51 is connected to the bit line 21 via a contact 61. The local wiring 52 is connected to the bit line 22 via a contact 62.

[0046] The presence or absence of contacts 71, 72, 73, and 74 determines the stored value of the memory cell. When formed, contact 71 connects portion 33a of active region 31 to power supply wiring 11. When formed, contact 72 connects portion 33c of active region 31 to power supply wiring 11. When formed, contact 73 connects portion 37a of active region 35 to power supply wiring 12. When formed, contact 74 connects portion 37c of active region 35 to power supply wiring 12.

[0047] 2 and 3, in the BM0 wiring layer, the power supply wirings 11, 12, 13, and 14 are arranged so as to overlap with the nanosheet FET in a planar view. This allows the wiring width of the power supply wirings 11, 12, 13, and 14 to be increased, thereby reducing their wiring resistance and improving the operating speed and stability of the mask ROM. Furthermore, this also prevents the area of ​​the mask ROM from increasing.

[0048] Furthermore, since only the bit lines 21, 22, 23, and 24 are formed in the M1 wiring layer, the wiring width can be increased, and the load capacitance of the bit lines can be reduced, thereby improving the operating speed of the mask ROM.

[0049] Furthermore, in the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this embodiment, the contacts 71, 72, 73, and 74 for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time for changing the memory value of the memory cell.

[0050] That is, in the method for manufacturing a semiconductor memory device according to the present disclosure, for example, a step of forming word lines, bit lines, and a plurality of nanosheet FETs on a semiconductor substrate is performed, and after this step, contacts for connecting the sources of the nanosheet FETs to ground power wiring are formed on the back side of the plurality of nanosheet FETs according to the data to be stored, and then ground power wiring is formed on the wiring layer on the back side.

[0051] As described above, according to this embodiment, memory cells M00 and M01 are adjacent in the X direction. Memory cell M00 includes a nanosheet FET having nanosheet 32a as a channel region, and memory cell M01 includes a nanosheet FET having nanosheet 36a as a channel region. Nanosheets 32a and 36a face each other in the X direction, and the surface of nanosheet 32a facing nanosheet 36a in the X direction is exposed from gate wiring 41, while the surface of nanosheet 36a facing nanosheet 32a in the X direction is exposed from gate wiring 42. That is, memory cells M00 and M01 include fork-sheet FETs. Bit lines 21 and 22 are formed in the M1 wiring layer, and power supply wirings 11 and 12 are formed in the BM0 wiring layer. Therefore, the wiring width of bit lines 21 and 22 can be increased, thereby improving the operating speed of the mask ROM. Furthermore, the wiring width of power supply wirings 11 and 12 can be increased, thereby improving the operating speed and operational stability of the mask ROM. Furthermore, the parasitic capacitance of the bit lines 21 and 22 and the power supply lines 11 and 12 can be reduced, thereby improving the operating speed.

[0052] <Modification 1> Fig. 4 is a plan view showing the layout structure of a mask ROM according to Modification 1 of the first embodiment. In this modification, wirings 25a, 25b, 25c, 25d, and 25e extending in the Y direction are provided in the M1 wiring layer. The wirings 25a, 25b, 25c, 25d, and 25e supply VSS. The other configurations are the same as those in Fig. 2.

[0053] The wirings 25a, 25b, 25c, 25d, and 25e function as shield wiring between the bit lines, suppressing crosstalk noise between the bit lines. This improves the stability of the operation of the mask ROM. Furthermore, by connecting the power supply wiring in the BM0 wiring layer and the wiring that supplies VSS in the M1 wiring layer outside the memory cell array, the power supply can be strengthened, thereby improving the operating speed and stability of the mask ROM.

[0054] In FIG. 4, the wirings 25a, 25b, 25c, 25d, and 25e are arranged at the boundaries of the ROM memory cells, but the positions where they are arranged are not limited to this.

[0055] 5 is a plan view showing the layout structure of a mask ROM according to a second modification of the first embodiment. This modification corresponds to the first embodiment in which the wiring layers of the bit lines and the VSS power supply wiring are interchanged. That is, in this modification, the bit lines are arranged in the BM0 wiring layer, and the VSS power supply wiring is arranged in the M1 wiring layer.

[0056] 5, bit lines 15, 16, 17, and 18 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 15, 16, 17, and 18 correspond to bit lines BL0, BL1, BL2, and BL3, respectively. Furthermore, power supply lines 25, 26, 27, and 28 extending in the Y direction are formed in the M1 wiring layer. The power supply lines 25, 26, 27, and 28 supply VSS. The bit lines 15, 16, 17, and 18 overlap with the power supply lines 25, 26, 27, and 28 in a plan view.

[0057] The active region 31 overlaps with the bit line 15 and the power supply wiring 25 in plan view. A portion 33b of the active region 31 is connected to the bit line 15 via a contact 63. The active region 35 overlaps with the bit line 16 and the power supply wiring 26 in plan view. A portion 37b of the active region 35 overlaps with the bit line 16 via a contact 64 in plan view.

[0058] Local interconnections 53, 54, 55, and 56 are formed extending in the X direction. The local interconnections 53 and 54 are connected to portions 33a and 33c, respectively, of the active region 31. The local interconnections 55 and 56 are connected to portions 37a and 37c, respectively, of the active region 35.

[0059] The presence or absence of contacts 75, 76, 77, and 78 determines the stored value of the memory cell. When formed, contact 75 connects local interconnect 53 to power supply interconnect 25. When formed, contact 76 connects local interconnect 54 to power supply interconnect 25. When formed, contact 77 connects local interconnect 55 to power supply interconnect 26. When formed, contact 78 connects local interconnect 56 to power supply interconnect 26.

[0060] 5, in the BM0 wiring layer, the bit lines 15, 16, 17, and 18 are arranged so as to overlap with the nanosheet FETs in a planar view. This allows the wiring width of the bit lines 15, 16, 17, and 18 to be increased, thereby reducing their wiring resistance and improving the operating speed and stability of the mask ROM. Furthermore, this also prevents the area of ​​the mask ROM from increasing.

[0061] That is, in this modification, the power supply wirings 25 and 26 are formed in the M1 wiring layer, and the bit lines 15 and 16 are formed in the BM0 wiring layer. Therefore, the wiring width of the bit lines 15 and 16 can be increased, thereby improving the operating speed of the mask ROM. Also, the wiring width of the power supply wirings 25 and 26 can be increased, thereby improving the operating speed and operational stability of the mask ROM. Furthermore, the parasitic capacitance of the bit lines 15 and 16 and the power supply wirings 25 and 26 can be suppressed, thereby improving the operating speed.

[0062] Furthermore, in this modification, similar to the above-described modification 1, power supply wiring for supplying VSS may be arranged between the bit lines in the BM0 wiring layer. The arranged power supply wiring functions as shield wiring between the bit lines and suppresses crosstalk noise between the bit lines. This improves the stability of the operation of the ROM memory cells.

[0063] <Modification 3> FIG. 6 is a plan view showing an example of the layout structure of a mask ROM according to Modification 3 of the first embodiment. In this modification, the transistor of each memory cell is composed of two nanosheet FETs arranged adjacent to each other in the Y direction and sharing a source. Similar to FIG. 2, FIG. 6 shows a configuration in which four memory cells are arranged in the X direction and two in the Y direction. In FIG. 6, the two memory cells from the left in the bottom row of the drawing correspond to memory cells M00 and M01 in the circuit diagram of FIG. 1, respectively, and the two memory cells from the left in the top row of the drawing correspond to memory cells M10 and M11 in the circuit diagram of FIG. 1, respectively. Hereinafter, the structure of the memory cells will be described mainly using memory cells M00 and M01 as an example.

[0064] 6, power supply wirings 111, 112, 113, and 114 extending in the Y direction are formed in the BM0 wiring layer. The power supply wirings 111, 112, 113, and 114 supply VSS. Bit lines 121, 122, 123, and 124 extending in the Y direction are formed in the M1 wiring layer. The bit lines 121, 122, 123, and 124 correspond to bit lines BL0, BL1, BL2, and BL3, respectively. The power supply wirings 111, 112, 113, and 114 overlap with the bit lines 121, 122, 123, and 124 in a plan view.

[0065] In the BM0 wiring layer, the power supply wirings 111, 112, 113, and 114 are arranged at equal intervals. However, the arrangement of the power supply wirings 111, 112, 113, and 114 does not have to be at equal intervals. Also, although the power supply wirings 111, 112, 113, and 114 are formed for each bit string, for example, the power supply wirings may be formed integrally for multiple bit strings.

[0066] Furthermore, in the M1 wiring layer, the bit lines 121, 122, 123, and 124 are arranged at equal intervals. This makes it possible to suppress performance variations because the load capacitance due to the inter-wiring capacitance is the same for all of the bit lines 121, 122, 123, and 124. However, the bit lines 121, 122, 123, and 124 do not have to be arranged at equal intervals.

[0067] An active region 131 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 111 and below the bit line 121. The active region 131 overlaps the power supply wiring 111 and the bit line 121 in a planar view. The active region 131 includes nanosheets 132a, 132b, 132c, and 132d that become the channel of the N-type nanosheet FET. The active region 131 also includes portions 133a, 133b, 133c, 133d, and 133e that become the source or drain of the N-type nanosheet FET.

[0068] An active region 135 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 112 and below the bit line 122. The active region 135 overlaps the power supply wiring 112 and the bit line 122 in a planar view. The active region 135 includes nanosheets 136a, 136b, 136c, and 136d that become the channel of the N-type nanosheet FET. The active region 135 also includes portions 137a, 137b, 137c, 137d, and 137e that become the source or drain of the N-type nanosheet FET.

[0069] Gate wirings 141, 142, 143, and 144 are formed extending in the X direction. Gate wiring 141 surrounds the outer peripheries of nanosheet 132a in the X and Z directions via a gate insulating film (not shown). Gate wiring 142 surrounds the outer peripheries of nanosheet 136a in the X and Z directions via a gate insulating film (not shown). Gate wiring 143 surrounds the outer peripheries of nanosheet 132b in the X and Z directions via a gate insulating film (not shown). Gate wiring 144 surrounds the outer peripheries of nanosheet 136b in the X and Z directions via a gate insulating film (not shown). Gate wirings 141 and 143 serve as gates for memory cell M00. Gate wirings 142 and 144 serve as gates for memory cell M01.

[0070] The surface of nanosheet 132a facing nanosheet 136a in the X direction is not covered by gate wiring 141 and is exposed from gate wiring 141. The surface of nanosheet 136a facing nanosheet 132a in the X direction is not covered by gate wiring 142 and is exposed from gate wiring 142. The surface of nanosheet 132b facing nanosheet 136b in the X direction is not covered by gate wiring 143 and is exposed from gate wiring 143. The surface of nanosheet 136b facing nanosheet 132b in the X direction is not covered by gate wiring 144 and is exposed from gate wiring 144. That is, memory cells M00 and M01 include fork-sheet FETs. This reduces the space required between the nanosheets 132a, 132b and the nanosheets 136a, 136b, and therefore the distance d1 between the nanosheets 132a, 132b and the nanosheets 136a, 136b can be reduced (d1<d2), thereby realizing a reduction in the area of ​​the semiconductor memory device.

[0071] The gate wiring 141 and the gate wiring 142 are connected by a bridge portion 145 formed between the gate wiring 141 and the gate wiring 142. The bridge portion 145 is an example of a gate connection portion. The gate wirings 141 and 142 are connected to other gate wirings aligned in a row in the X direction to form the word line WL0. The gate wirings 143 and 144 are connected by a bridge portion 146 formed between the gate wirings 143 and 144. The bridge portion 146 is an example of a gate connection portion. The gate wirings 143 and 144 are connected to other gate wirings aligned in a row in the X direction to form the word line WL0. Similarly, the word line WL1 also includes other gate wirings aligned in a row in the X direction.

[0072] Local interconnections 151, 152, 153, 154, 155, and 156 are formed extending in the X direction. The local interconnection 151 is connected to a portion 133a of the active region 131. The local interconnection 152 is connected to a portion 133c of the active region 131. The local interconnection 153 is connected to a portion 133e of the active region 131. The local interconnection 154 is connected to a portion 137a of the active region 135. The local interconnection 155 is connected to a portion 137c of the active region 135. The local interconnection 156 is connected to a portion 137e of the active region 135.

[0073] The local interconnects 151, 152, and 153 are connected to the bit line 121 via contacts. The local interconnects 154, 155, and 156 are connected to the bit line 122 via contacts.

[0074] The presence or absence of contacts 171, 172, 173, and 174 determines the stored value of a memory cell. When formed, contact 171 connects portion 133b of active region 131 to power supply wiring 111. When formed, contact 172 connects portion 133d of active region 131 to power supply wiring 111. When formed, contact 173 connects portion 137b of active region 135 to power supply wiring 112. When formed, contact 174 connects portion 137d of active region 135 to power supply wiring 112.

[0075] 6, in the BM0 wiring layer, the power supply wirings 111, 112, 113, and 114 are arranged so as to overlap with the nanosheet FETs in a planar view. Therefore, the wiring width of the power supply wirings 111, 112, 113, and 114 can be increased, thereby reducing their wiring resistance, thereby improving the operating speed and stability of the mask ROM. Furthermore, an increase in the area of ​​the mask ROM can be suppressed.

[0076] Furthermore, in the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this modification, the contacts 171, 172, 173, and 174 for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time required to change the memory value of the memory cell.

[0077] In the configuration example of FIG. 6 , the M1 wiring layer is provided with wirings 125a, 125b, 125c, 125d, and 125e extending in the Y direction. The wirings 125a, 125b, 125c, 125d, and 125e supply VSS. The wirings 125a, 125b, 125c, 125d, and 125e function as shield wiring between bit lines and suppress crosstalk noise between the bit lines. This improves the stability of the operation of the ROM memory cells. Note that the wirings 125a, 125b, 125c, 125d, and 125e do not necessarily have to be provided.

[0078] 7 is a plan view showing the layout structure of a mask ROM according to Modification 4 of the first embodiment. This modification corresponds to Modification 3, in which the wiring layers of the bit lines and the VSS power supply wiring are swapped. That is, in this modification, the bit lines are arranged in the BM0 wiring layer, and the VSS power supply wiring is arranged in the M1 wiring layer.

[0079] 7, bit lines 115, 116, 117, and 118 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 115, 116, 117, and 118 correspond to bit lines BL0, BL1, BL2, and BL3, respectively. Furthermore, power supply lines 125, 126, 127, and 128 extending in the Y direction are formed in the M1 wiring layer. The power supply lines 125, 126, 127, and 128 supply VSS. The bit lines 115, 116, 117, and 118 overlap with the power supply lines 125, 126, 127, and 128 in a plan view.

[0080] The active region 131 overlaps the bit line 115 and the power supply wiring 125 in a planar view. Portions 133a, 133c, and 133e of the active region 131 are connected to the bit line 115 via contacts. The active region 135 overlaps the bit line 116 and the power supply wiring 126 in a planar view. Portions 137a, 137c, and 137e of the active region 135 overlap the bit line 116 via contacts in a planar view.

[0081] Local interconnections 157, 158, 159, and 160 are formed extending in the X direction. The local interconnections 157 and 158 are connected to portions 133b and 133d, respectively, of the active region 131. The local interconnections 159 and 160 are connected to portions 137b and 137d, respectively, of the active region 135.

[0082] The presence or absence of contacts 175, 176, 177, and 178 determines the stored value of a memory cell. When formed, contact 175 connects local interconnect 157 to power supply interconnect 125. When formed, contact 176 connects local interconnect 158 ​​to power supply interconnect 125. When formed, contact 177 connects local interconnect 159 to power supply interconnect 126. When formed, contact 178 connects local interconnect 160 to power supply interconnect 126.

[0083] 7, in the BM0 wiring layer, the bit lines 115, 116, 117, and 118 are arranged so as to overlap with the nanosheet FET in a planar view. Therefore, the wiring width of the bit lines 115, 116, 117, and 118 can be increased, thereby reducing their wiring resistance, thereby improving the operating speed and stability of the mask ROM. Furthermore, an increase in the area of ​​the mask ROM can be suppressed.

[0084] 7, the BM0 wiring layer is provided with wirings 115a, 115b, 115c, 115d, and 115e extending in the Y direction. The wirings 115a, 115b, 115c, 115d, and 115e supply VSS. The wirings 115a, 115b, 115c, 115, and 115e function as shield wirings between bit lines and suppress crosstalk noise between the bit lines. This improves the stability of the operation of the ROM memory cells. Note that the wirings 115a, 115b, 115c, 115d, and 115e do not necessarily have to be provided.

[0085] Second Embodiment Fig. 8 is a circuit diagram showing the configuration of a mask ROM as an example of a semiconductor memory device. In the mask ROM of Fig. 8, whether the source and drain of a memory cell transistor are connected to the same line or different lines out of a bit line and a ground power supply line corresponds to "1" or "0" of stored data.

[0086] 8, the mask ROM includes a memory cell array 3A, a column decoder 2, and a sense amplifier 18.

[0087] The memory cell array 3A is configured by arranging memory cells Mij (i = 0 to m, j = 0 to n) of N-type MOS transistors in a matrix. The gates of the memory cells Mij are connected to word lines WLi in common in the row direction. The source and drain of the memory cell Mij are connected to bit lines BLj or to a ground power supply wiring VSS. When the data stored in the memory cell Mij is set to "0", one of the source and drain is connected to the bit line BLj and the other is connected to the ground power supply wiring VSS. On the other hand, when the data stored in the memory cell Mij is set to "1", both the source and drain are connected to the bit line BLj or the ground power supply wiring VSS.

[0088] The column decoder 2 is composed of N-type MOS transistors Cj, whose drains are all connected in common, whose gates are connected to respective column selection signal lines CLj, and whose sources are connected to respective bit lines BLj.

[0089] The sense amplifier 18 includes a precharge P-type MOS transistor 5, an inverter 8 that determines the output data of the memory cell Mij, and an inverter 9 that buffers the output signal of the inverter 8. A precharge signal NPR is input to the gate of the P-type MOS transistor 5, a power supply voltage VDD is supplied to the source, and the drain is connected to the common drain of the N-type MOS transistor Cj. The inverter 8 receives a signal SIN from the common drain of the N-type MOS transistor Cj and determines the output data of the memory cell Mij. The inverter 9 receives an output signal SOUT from the inverter 8 and outputs the stored data of the memory cell Mij.

[0090] The operation of the mask ROM shown in Fig. 8 will be described below, taking as an example the case where data is read from memory cells M00 and M10.

[0091] First, among the column selection signal lines CLj, CL0 is set to high level and the other CL1 to CLn are set to low level. As a result, among the transistors constituting the column decoder 2, C0 is turned on and the other C1 to Cn are turned off. Also, the word line WL0 is transitioned from low level, which indicates a non-selected state, to high level, which indicates a selected state.

[0092] Next, the precharge signal NPR is changed from high level to low level, and the precharge P-type MOS transistor is turned on.

[0093] One of the source and drain of memory cell M00 is connected to bit line BL0, and the other is connected to ground power supply wiring VSS. Therefore, current flows from bit line BL0 to ground power supply wiring VSS via memory cell M00, and input signal SIN of inverter 8 becomes a voltage lower than the switching level of inverter 8. Therefore, output signal SOUT of inverter 8 remains high, and output signal OUT of inverter 9 remains low.

[0094] When data in the memory cell M10 is to be read, the word line WL1 is transitioned from a low level indicating a non-selected state to a high level indicating a selected state.

[0095] Both the source and drain of memory cell M10 are connected to bit line BL0. Therefore, no current flows through bit line BL0, and input signal SIN of inverter 8 becomes a voltage higher than the switching level of inverter 8. As a result, output signal SOUT of inverter 8 becomes low level, and output signal OUT of inverter 9 becomes high level.

[0096] That is, when one of the source and drain of the memory cell is connected to a bit line and the other is connected to a ground power supply wiring, a low level is output (storage data "0"), and when both the source and drain of the memory cell are connected to a bit line or a ground power supply wiring, a high level is output (storage data "1").

[0097] FIG. 9 is a diagram showing an example of the layout structure of a mask ROM according to the second embodiment, and is a plan view of a memory cell array. FIG. 9 corresponds to a layout for (4×4) bits. Dashed lines indicate the frame of a memory cell for one bit. That is, FIG. 9 shows a configuration in which four memory cells are arranged in the X direction and four in the Y direction. For example, the two memory cells from the left in the bottom row of the drawing correspond to memory cells M00 and M01 in the circuit diagram of FIG. 8, and the two memory cells from the left in the row above correspond to memory cells M10 and M11 in the circuit diagram of FIG. 8.

[0098] In the configuration of Figure 9, each memory cell is composed of one nanosheet FET. Note that the memory cell may have two or more nanosheet FETs. Furthermore, the cross-sectional structure is the same as that of the first embodiment and can be easily inferred from the cross-sectional view of Figure 3, etc., so the cross-sectional view is omitted here.

[0099] 9 , power supply wirings 211, 212, 213, and 214 extending in the Y direction are formed in the BM0 wiring layer. The power supply wirings 211, 212, 213, and 214 supply VSS. Bit lines 221, 222, 223, and 224 extending in the Y direction are formed in the M1 wiring layer. The bit lines 221, 222, 223, and 224 correspond to bit lines BL0, BL1, BL2, and BL3, respectively. The power supply wirings 211, 212, 213, and 214 overlap with the bit lines 221, 222, 223, and 224 in a plan view.

[0100] An active region 231 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 211 and below the bit line 221. The active region 231 overlaps the power supply wiring 211 and the bit line 221 in a planar view. The active region 231 includes nanosheets 232a, 232b, 232c, and 232d that become the channel of the N-type nanosheet FET. The active region 231 also includes portions 233a, 233b, 233c, 233d, and 233e that become the source or drain of the N-type nanosheet FET.

[0101] An active region 235 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 212 and below the bit line 222. The active region 235 overlaps the power supply wiring 212 and the bit line 222 in a planar view. The active region 235 includes nanosheets 236a, 236b, 236c, and 236d that become the channel of the N-type nanosheet FET. The active region 235 also includes portions 237a, 237b, 237c, 237d, and 237e that become the source or drain of the N-type nanosheet FET.

[0102] Gate wirings 241, 242, 243, and 244 are formed extending in the X direction. Gate wiring 241 surrounds the outer peripheries of nanosheet 232a in the X and Z directions via a gate insulating film (not shown). Gate wiring 242 surrounds the outer peripheries of nanosheet 236a in the X and Z directions via a gate insulating film (not shown). Gate wiring 243 surrounds the outer peripheries of nanosheet 232b in the X and Z directions via a gate insulating film (not shown). Gate wiring 244 surrounds the outer peripheries of nanosheet 236b in the X and Z directions via a gate insulating film (not shown).

[0103] The surface of nanosheet 232a facing nanosheet 236a in the X direction is not covered by gate wiring 241 and is exposed from gate wiring 241. The surface of nanosheet 236a facing nanosheet 232a in the X direction is not covered by gate wiring 242 and is exposed from gate wiring 242. The surface of nanosheet 232b facing nanosheet 236b in the X direction is not covered by gate wiring 243 and is exposed from gate wiring 243. The surface of nanosheet 236b facing nanosheet 232b in the X direction is not covered by gate wiring 244 and is exposed from gate wiring 244. That is, memory cells M00, M01, M10, and M11 include fork-sheet FETs. This reduces the space required between nanosheets 232a, 232b and nanosheets 236a, 236b, and therefore the distance d1 between nanosheets 232a, 232b and nanosheets 236a, 236b can be reduced (d1<d2), thereby realizing a reduction in the area of ​​the semiconductor memory device.

[0104] The gate wiring 241 and the gate wiring 242 are connected by a bridge portion 245 formed between the gate wiring 241 and the gate wiring 242. The bridge portion 245 is an example of a gate connection portion. The gate wirings 241 and 242 are connected to other gate wirings aligned in a row in the X direction to form the word line WL0. The gate wirings 243 and 244 are connected by a bridge portion 246 formed between the gate wirings 243 and 244. The bridge portion 246 is an example of a gate connection portion. The gate wirings 243 and 244 are connected to other gate wirings aligned in a row in the X direction to form the word line WL1. Similarly, the word lines WL2 and WL3 also include other gate wirings aligned in a row in the X direction.

[0105] Local wirings 251a, 251b, 251c, 251d, 251e, 252a, 252b, 252c, 252d, and 252e are formed extending in the X direction. The local wirings 251a, 251b, 251c, 251d, and 251e are connected to portions 233a, 233b, 233c, 233d, and 233e, respectively, of the active region 231. The local wirings 252a, 252b, 252c, 252d, and 252e are connected to portions 237a, 237b, 237c, 237d, and 237e, respectively, of the active region 235.

[0106] Contacts 261, 262, 263, 264, and 265 connect the VSS power supply wiring in the BM0 wiring layer to the active region. Contacts 271, 272, 273, 274, and 275 connect the local wiring to the bit lines in the M1 wiring layer. Contacts 261, 262, 263, 264, and 265 and contacts 271, 272, 273, 274, and 275 determine the memory value of the memory cell. That is, each memory cell stores data "1" when both nodes are connected to the VSS power supply wiring via contacts or when both nodes are connected to the bit lines via contacts. On the other hand, each memory cell stores data "0" when one node is connected to the VSS power supply wiring via contacts and the other node is connected to the bit line via contacts.

[0107] 9 , memory cell M00 has one node connected to VSS power supply line 211 in the BM0 wiring layer via contact 261, and the other node connected to bit line 221 in the M1 wiring layer via contact 271, and therefore stores data "0." Memory cell M10 has both nodes connected to bit line 221 in the M1 wiring layer via contacts 271 and 272, and therefore stores data "1." Memory cell M01 has one node connected to bit line 222 in the M1 wiring layer via contact 273, and the other node connected to VSS power supply line 212 in the BM0 wiring layer via contact 264, and therefore stores data "0." Memory cell M11 has one node connected to VSS power supply line 212 in the BM0 wiring layer via contact 264, and therefore stores data "0."

[0108] 9, in the BM0 wiring layer, the power supply wirings 211, 212, 213, and 214 are arranged so as to overlap with the nanosheet FETs in a planar view. Therefore, the wiring width of the power supply wirings 211, 212, 213, and 214 can be increased, thereby reducing the wiring resistance and improving the operating speed and stability of the mask ROM. Furthermore, an increase in the area of ​​the mask ROM can be suppressed.

[0109] 9, the M1 wiring layer is provided with wirings 229a, 229b, 229c, 229d, and 229e extending in the Y direction. The wirings 229a, 229b, 229c, 229d, and 229e supply VSS. The wirings 229a, 229b, 229c, 229d, and 229e function as shield wirings between bit lines and suppress crosstalk noise between the bit lines. This improves the stability of mask ROM operation. Note that the wirings 229a, 229b, 229c, 229d, and 229e do not necessarily have to be provided.

[0110] As described above, according to this embodiment, memory cells M00 and M01 are adjacent to each other in the X direction. Memory cell M00 includes a nanosheet FET having nanosheet 232a as a channel region, and memory cell M01 includes a nanosheet FET having nanosheet 236a as a channel region. Nanosheets 232a and 236a face each other in the X direction, and the surface of nanosheet 232a facing nanosheet 236a in the X direction is exposed from gate wiring 241, while the surface of nanosheet 236a facing nanosheet 232a in the X direction is exposed from gate wiring 242. That is, memory cells M00 and M01 include fork-sheet FETs. Bit lines 221 and 222 are formed in the M1 wiring layer, and power supply wiring 211 and 212 are formed in the BM0 wiring layer. Therefore, the wiring width of bit lines 221 and 222 can be increased, thereby improving the operating speed of the mask ROM. In addition, the width of the power supply wirings 211 and 212 can be increased, thereby improving the operating speed and stability of the mask ROM. Furthermore, the parasitic capacitance between the bit lines 221 and 222 and the power supply wirings 211 and 212 can be reduced, thereby improving the operating speed.

[0111] 10 is a plan view showing the layout structure of a mask ROM according to a first modification of the second embodiment. This modification corresponds to the second embodiment in which the wiring layers of the bit lines and the VSS power supply wiring are interchanged. That is, in this modification, the bit lines are arranged in the BM0 wiring layer, and the VSS power supply wiring is arranged in the M1 wiring layer.

[0112] 10 , bit lines 215, 216, 217, and 218 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 215, 216, 217, and 218 correspond to bit lines BL0, BL1, BL2, and BL3, respectively. Furthermore, power supply lines 225, 226, 227, and 228 extending in the Y direction are formed in the M1 wiring layer. The power supply lines 225, 226, 227, and 228 supply VSS. The bit lines 215, 216, 217, and 218 overlap with the power supply lines 225, 226, 227, and 228 in a plan view.

[0113] The active region 231 overlaps with the bit line 215 and the power supply wiring 225 in a planar view. The active region 235 overlaps with the bit line 216 and the power supply wiring 226 in a planar view. The local wirings 251a, 251b, 251c, 251d, and 251e are connected to portions 233a, 233b, 233c, 233d, and 233e of the active region 231, respectively. The local wirings 252a, 252b, 252c, 252d, and 252e are connected to portions 237a, 237b, 237c, 237d, and 237e of the active region 235, respectively.

[0114] Contacts 281, 282, 283, 284, and 285 connect bit lines in the BM0 wiring layer to the active regions. Contacts 291, 292, 293, 294, and 295 connect local wiring to VSS power supply wiring in the M1 wiring layer. Contacts 281, 282, 283, 284, and 285 and contacts 291, 292, 293, 294, and 295 determine the memory value of the memory cell. That is, each memory cell stores data "1" when both nodes are connected to the VSS power supply wiring via contacts or when both nodes are connected to the bit line BL via contacts. On the other hand, each memory cell stores data "0" when one node is connected to the VSS power supply wiring via contacts and the other node is connected to the bit line BL via contacts.

[0115] 10 , memory cell M00 has one node connected to VSS power supply line 225 in the M1 wiring layer via contact 291, and the other node connected to bit line 215 in the BM0 wiring layer via contact 281, and therefore stores data "0." Memory cell M10 has both nodes connected to bit line 215 in the BM0 wiring layer via contacts 281 and 282, and therefore stores data "1." Memory cell M01 has one node connected to bit line 216 in the BM0 wiring layer via contact 283, and the other node connected to VSS power supply line 226 in the M1 wiring layer via contact 294, and therefore stores data "0." Memory cell M11 has one node connected to VSS power supply line 226 in the M1 wiring layer via contact 294, and the other node connected to bit line 216 in the BM0 wiring layer via contact 284, and therefore stores data "0."

[0116] In the configuration example of Figure 10, in the BM0 wiring layer, the bit lines 215, 216, 217, and 218 are arranged so as to overlap with the nanosheet FET in a planar view. Therefore, the wiring width of the bit lines 215, 216, 217, and 218 can be increased, thereby reducing their wiring resistance, thereby improving the operating speed and stability of the mask ROM. In addition, an increase in the area of ​​the mask ROM can be suppressed.

[0117] 10, the BM0 wiring layer is provided with wirings 219a, 219b, 219c, 219d, and 219e extending in the Y direction. The wirings 219a, 219b, 219c, 219d, and 219e supply VSS. The wirings 219a, 219b, 219c, 219d, and 219e function as shield wirings between bit lines and suppress crosstalk noise between the bit lines. This improves operational stability. Note that the wirings 219a, 219b, 219c, 219d, and 219e do not necessarily have to be provided.

[0118] As described above, according to this modification, the bit lines 215 and 216 are formed in the BM0 wiring layer, and the power supply wirings 225 and 226 are formed in the M1 wiring layer. Therefore, the wiring width of the bit lines 215 and 216 can be increased, thereby improving the operating speed of the mask ROM. Furthermore, the wiring width of the power supply wirings 225 and 226 can be increased, thereby improving the operating speed and operational stability of the mask ROM. Furthermore, the parasitic capacitance of the bit lines 215 and 216 and the power supply wirings 225 and 226 can be suppressed, thereby improving the operating speed.

[0119] In the above-described embodiment, the nanosheet FET has three overlapping sheets in a planar view, and the cross-sectional shape of the sheets is rectangular, but the number and cross-sectional shape of the nanosheet FET are not limited to this.

[0120] The present disclosure enables the operating speed and stability of a mask ROM to be improved without increasing the area, and is therefore useful for, for example, miniaturizing semiconductor chips and improving their performance.

[0121] 11, 12, 13, 14 Ground power supply wiring 21, 22, 23, 24 Bit lines 25a, 25b, 25c, 25d, 25e Ground power supply wiring 31, 35 Active area 32a, 32b, 36a, 36b Nanosheet 41, 42 Gate wiring 51, 52, 53, 54, 55, 56 Local wiring 71, 72, 73, 74, 75, 76, 77, 78 Contact 111, 112, 113, 114 Ground power supply wiring 121, 122, 122, 123 Bit lines 131, 135 Active area 132a, 132b, 132c, 132d, 136a, 136b, 136c, 136d Nanosheet 141, 142, 143, 144 Gate wiring 171, 172, 173, 174, 175, 176, 177, 178 Contacts 211, 212, 213, 214 Ground power supply wiring 215, 216, 217, 218 Bit lines 219a, 219b, 219c, 219d, 219e Ground power supply wiring 221, 222, 223, 224 Bit lines 225, 226, 227, 228 Ground power supply wiring 229a, 229b, 229c, 229d, 229e Ground power supply wiring 231, 235 Active regions 232a, 232b, 232c, 232d Nanosheets 236a, 236b, 236c, 236d Nanosheets 241, 242, 243, 244 Gate wiring 261, 262, 263, 264, 265 271, 272, 273, 274, 275 Contacts 281, 282, 283, 284, 285 291, 292, 293, 294, 295 Contacts Mij (i=0 to m, j=0 to n) Memory cell BLj Bit line WLi Word line

Claims

1. A semiconductor memory device comprising: first and second ROM (Read Only Memory) memory cells adjacent to each other in a first direction; a word line extending in the first direction; first and second bit lines extending in a second direction perpendicular to the first direction; and first and second ground power wirings extending in the second direction; wherein the first ROM memory cell has a first nanosheet as a channel region and a first nanosheet FET (Field Effect Transistor) having a gate connected to the word line and a drain connected to the first bit line, and stores data depending on whether or not there is an electrical connection between the source of the first nanosheet FET and the first ground power wiring; and the second ROM memory cell has a second nanosheet as a channel region and a second nanosheet FET having a gate connected to the word line and a drain connected to the second bit line, and stores data depending on whether or not there is an electrical connection between the source of the second nanosheet FET and the second ground power wiring. the word line includes a first gate wiring that surrounds the periphery of the first nanosheet in the first direction and a third direction perpendicular to the first and second directions, and a second gate wiring that surrounds the periphery of the second nanosheet in the first and third directions; the first and second nanosheets face each other in the first direction, and the surface of the first nanosheet facing the second nanosheet in the first direction is exposed from the first gate wiring, and the surface of the second nanosheet facing the first nanosheet in the first direction is exposed from the second gate wiring; the first and second bit lines are formed in a first wiring layer on the front side of the first and second nanosheet FETs, and overlap with the first and second nanosheet FETs, respectively, in a planar view; and the first and second ground power wirings are formed in a second wiring layer on the back side of the first and second nanosheet FETs, and overlap with the first and second nanosheet FETs, respectively, in a planar view.

2. A semiconductor memory device according to claim 1, wherein the first ROM memory cell stores data depending on the presence or absence of a contact connecting the source of the first nanosheet FET and the first ground power wiring, and the second ROM memory cell stores data depending on the presence or absence of a contact connecting the source of the second nanosheet FET and the second ground power wiring.

3. A semiconductor memory device according to claim 1, further comprising a third ground power supply wiring formed in said first wiring layer, disposed between said first bit line and said second bit line, and extending in said second direction.

4. A semiconductor memory device according to claim 1, comprising a second word line extending in the first direction, wherein the first ROM memory cell has a third nanosheet as a channel region, overlaps with the first bit line and the first ground power wiring in a planar view, comprises a third nanosheet FET having a gate connected to the second word line, a drain connected to the first bit line, and a source shared with the first nanosheet FET, and stores data depending on whether the source shared by the first and third nanosheet FETs is electrically connected to the first ground power wiring; and the second ROM memory cell has a fourth nanosheet as a channel region, overlaps with the second bit line and the second ground power wiring in a planar view, has a gate connected to the second word line, a drain connected to the second bit line, and a source shared with the second nanosheet FET, and stores data depending on whether the source shared by the second and fourth nanosheet FETs is electrically connected to the second ground power wiring. the second word line includes a third gate wiring that surrounds the outer periphery of the third nanosheet in the first direction and the third direction, and a fourth gate wiring that surrounds the outer periphery of the fourth nanosheet in the first direction and the third direction, the third and fourth nanosheets face each other in the first direction, and the surface of the third nanosheet facing the fourth nanosheet in the first direction is exposed from the third gate wiring, and the surface of the fourth nanosheet facing the third nanosheet in the first direction is exposed from the fourth gate wiring.

5. A semiconductor memory device comprising: first and second ROM (Read Only Memory) memory cells adjacent to each other in a first direction; a word line extending in the first direction; first and second bit lines extending in a second direction perpendicular to the first direction; and first and second ground power wirings extending in the second direction, wherein the first ROM memory cell has a first nanosheet as a channel region and a first nanosheet FET (Field Effect Transistor) having a gate connected to the word line and a drain connected to the first bit line, and stores data depending on whether or not the source of the first nanosheet FET is electrically connected to the first ground power wiring; and the second ROM memory cell has a second nanosheet as a channel region and a second nanosheet FET having a gate connected to the word line and a drain connected to the second bit line, and stores data depending on whether or not the source of the second nanosheet FET is electrically connected to the second ground power wiring. the word line includes a first gate wiring that surrounds the periphery of the first nanosheet in the first direction and a third direction perpendicular to the first and second directions, and a second gate wiring that surrounds the periphery of the second nanosheet in the first and third directions; the first and second nanosheets face each other in the first direction, and a surface of the first nanosheet facing the second nanosheet in the first direction is exposed from the first gate wiring, and a surface of the second nanosheet facing the first nanosheet in the first direction is exposed from the second gate wiring; the first and second ground power wirings are formed in a first wiring layer on the front side of the first and second nanosheet FETs, and overlap with the first and second nanosheet FETs, respectively, in a planar view; and the first and second bit lines are formed in a second wiring layer on the back side of the first and second nanosheet FETs, and overlap with the first and second nanosheet FETs, respectively, in a planar view.

6. A semiconductor memory device according to claim 5, wherein the first ROM memory cell has a first local wiring extending in the first direction and connected to the source of the first nanosheet FET, and stores data depending on the presence or absence of a contact connecting the first local wiring and the first ground power supply wiring; and the second ROM memory cell has a second local wiring extending in the first direction and connected to the source of the second nanosheet FET, and stores data depending on the presence or absence of a contact connecting the second local wiring and the second ground power supply wiring.

7. A semiconductor memory device according to claim 5, further comprising a third ground power supply wiring formed in the second wiring layer, disposed between the first bit line and the second bit line, and extending in the second direction.

8. A semiconductor memory device according to claim 5, comprising a second word line extending in the first direction, wherein the first ROM memory cell has a third nanosheet as a channel region, overlaps with the first bit line and the first ground power wiring in a planar view, comprises a third nanosheet FET having a gate connected to the second word line, a drain connected to the first bit line, and a source shared with the first nanosheet FET, and stores data depending on whether or not the source shared by the first and third nanosheet FETs is electrically connected to the first ground power wiring; and the second ROM memory cell has a fourth nanosheet as a channel region, overlaps with the second bit line and the second ground power wiring in a planar view, comprises a fourth nanosheet FET having a gate connected to the second word line, a drain connected to the second bit line, and a source shared with the second nanosheet FET, and stores data depending on whether or not the source shared by the second and fourth nanosheet FETs is electrically connected to the second ground power wiring. the second word line includes a third gate wiring that surrounds the outer periphery of the third nanosheet in the first direction and the third direction, and a fourth gate wiring that surrounds the outer periphery of the fourth nanosheet in the first direction and the third direction, the third and fourth nanosheets face each other in the first direction, and the surface of the third nanosheet facing the fourth nanosheet in the first direction is exposed from the third gate wiring, and the surface of the fourth nanosheet facing the third nanosheet in the first direction is exposed from the fourth gate wiring.

9. A semiconductor memory device comprising: first and second ROM (Read Only Memory) memory cells adjacent to each other in a first direction; a word line extending in the first direction; first and second bit lines extending in a second direction perpendicular to the first direction; and first and second ground power wirings extending in the second direction; wherein the first ROM memory cell has a first nanosheet as a channel region and comprises a first nanosheet FET (Field Effect Transistor) having a gate connected to the word line, a source connected to the first bit line or the first ground power wiring, and a drain connected to the first bit line or the first ground power wiring, and stores data depending on whether the source and drain of the first nanosheet FET are connected to the same line or different lines of the first bit line and the first ground power wiring; and wherein the second ROM memory cell is a second nanosheet FET having a second nanosheet as a channel region, a gate connected to the word line, a source connected to the second bit line or the second ground power wiring, and a drain connected to the second bit line or the second ground power wiring, wherein data is stored depending on whether the source and drain of the second nanosheet FET are connected to the same line or different lines of the second bit line and the second ground power wiring; the word line includes a first gate wiring surrounding the periphery of the first nanosheet in the first direction and a third direction perpendicular to the first and second directions, and a second gate wiring surrounding the periphery of the second nanosheet in the first direction and the third direction; the first and second nanosheets face each other in the first direction, and the surface of the first nanosheet facing the second nanosheet in the first direction is exposed from the first gate wiring, and the surface of the second nanosheet facing the first nanosheet in the first direction is exposed from the second gate wiring; the first and second bit lines are formed in either a first wiring layer on the front surface side of the first and second nanosheet FETs or a second wiring layer on the back surface side of the first and second nanosheet FETs, and overlap the first and second nanosheet FETs, respectively, in a planar view;The first and second ground power supply wirings are formed in the other of the first wiring layer and the second wiring layer, and overlap the first and second nanosheet FETs, respectively, in a planar view.

10. A semiconductor memory device according to claim 9, wherein the first and second bit lines are formed in the first wiring layer, and the first and second ground power supply wirings are formed in the second wiring layer.

11. A semiconductor memory device according to claim 10, further comprising a third ground power supply wiring formed in the first wiring layer, disposed between the first bit line and the second bit line, and extending in the second direction.

12. A semiconductor memory device according to claim 9, wherein the first and second ground power supply wirings are formed in the first wiring layer, and the first and second bit lines are formed in the second wiring layer.

13. A semiconductor memory device according to claim 12, further comprising a third ground power supply wiring formed in the second wiring layer, disposed between the first bit line and the second bit line, and extending in the second direction.

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