Semiconductor storage device and information processing device

Abstract

This card controller (22) holds N2 logical blocks (32) that can be mapped to N1 physical blocks (31). The card controller (22) receives, from a host device (10), a set value indicating a number N3 (N3 < N2). The card controller (22) permits access by the host device (10) to N3 first logical blocks (32). The card controller (22) denies access by the host device (10) to (N2 - N3) second logical blocks (32) other than the first logical block. The card controller (22) maps N3 first logical blocks (32) to N3 first physical blocks (31). The card controller (22) sets (N1 - N3) second physical blocks (31) other than the first physical block as alternative blocks in which data can be written by the card controller (22).

Description

Semiconductor memory device and information processing device

[0001] The present disclosure relates to a semiconductor memory device and an information processing device.

[0002] Semiconductor memory devices such as flash memory have evolved to have higher density, capacity, and speed, and are being used in an increasingly wide range of industrial applications.

[0003] Flash memories need to implement a "smoothing process" to prevent accesses from concentrating on the same physical block. For example, Patent Document 1 discloses one technique related to the smoothing process of flash memories.

[0004] WO 2008 / 089643

[0005] "SD Specifications Part 1 Physical Layer Simplified Specification Version 9.10," SD Association, December 1, 2023, [Retrieved June 20, 2024], Internet <URL: https: / / www.sdcard.org / downloads / pls / pdf / ?p=Part1_Physical_Layer_Simplified_Specification_Ver9.10.jpg&f=Part1PhysicalLayerSimplifiedSpecificationVer9.10Fin_20231201.pdf&e=EN_SS9_1>

[0006] As the density, capacity, and speed of flash memory increase, the number of rewrites, i.e., the lifespan, of flash memory decreases. For example, NAND flash memory is classified into SLC (single memory cell), MLC (multi-level cell), TLC (triple memory cell), QLC (quad-level cell), etc. depending on the number of states that a cell that stores data has. SLC has a rewrite count of about 90,000 to 100,000, MLC has a rewrite count of about 8,000 to 10,000, TLC has a rewrite count of about 3,000 to 5,000, and QLC has a rewrite count of about 500 to 1,000. For this reason, semiconductor memory devices with longer lifespans than conventional ones are required.

[0007] An object of the present disclosure is to provide a semiconductor memory device having a longer lifespan than conventional devices, and an information processing device that writes and reads data to and from such a semiconductor memory device.

[0008] a first interface connected to an information processing device; a semiconductor memory element including a plurality of N1 physical blocks; and a first controller, wherein the first controller holds a plurality of N2 logical blocks, the number of which is N1 or less, that can be mapped to the plurality of N1 physical blocks; receives from the information processing device a usage area setting value indicating a number N3 that is smaller than the number N2; permits the information processing device to write and read data to N3 first logical blocks among the N2 logical blocks; denies the information processing device from writing and reading data to (N2-N3) second logical blocks other than the first logical blocks among the N2 logical blocks; maps the N3 first logical blocks to N3 first physical blocks among the plurality of N1 physical blocks; and sets the (N1-N3) second physical blocks other than the first physical block among the plurality of N1 physical blocks as alternative blocks to which data can be written by the first controller.

[0009] According to one aspect of the present disclosure, it is possible to provide a semiconductor memory device having a longer lifespan than conventional devices.

[0010] 1. A block diagram showing an example of the configuration of a host device 10 and an SD card 20 according to a first embodiment. A diagram explaining an example of mapping of logical blocks and physical blocks in the SD card 20 of FIG. 1. A diagram explaining an example of the operation of an SD card according to a comparative example. A diagram explaining an example of the operation of the SD card 20 of FIG. 1. A flowchart showing an example of SD card control processing executed by the host controller 12 of the host device 10 of FIG. 1. A flowchart showing an example of SD card control processing executed by a card controller 22 of the SD card 20 of FIG. 1. A flowchart showing an example of a subroutine of the used area setting processing (step S15) of FIG. 6. A flowchart showing an example of a subroutine of the memory access processing (step S16) of FIG. 6. A diagram explaining an example of the operation of an SD card 20 according to a second embodiment. A diagram explaining an example of the operation of a host device 10 and an SD card 20 according to a third embodiment. A flowchart showing an example of SD card control processing executed by the host controller 12 of the host device 10 according to the third embodiment. A flowchart showing an example of SD card control processing executed by the card controller 22 of the SD card 20 according to the third embodiment. A flowchart showing an example of a subroutine of the used area setting pre-processing (step S41) of FIG. 13 is a flowchart showing an example of a subroutine of the use area setting pre-processing (step S42) of FIG. 12.

[0011] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and redundant descriptions of substantially identical configurations may be omitted. This is to avoid unnecessary redundancy in the following description and to facilitate understanding by those skilled in the art.

[0012] The inventor(s) provide the accompanying drawings and the following description to enable those skilled in the art to fully understand the present disclosure, and do not intend for them to limit the subject matter described in the claims.

[0013] First Embodiment A semiconductor memory device and an information processing device according to a first embodiment will be described below with reference to FIGS.

[0014] [Configuration of First Embodiment] FIG. 1 is a block diagram showing an example of the configuration of a host device 10 and an SD card 20 according to the first embodiment.

[0015] The host device 10 includes a host interface 11, a host controller 12, a CPU (Central Processing Unit) 13, a RAM (Random Access Memory) 14, and an SSD (Solid State Drive) 15. The host interface 11 is connected to a card interface 21 (described below) of the SD card 20, and data is sent to and received from the SD card 20 via the host interface 11. The host interface 11 includes, but is not limited to, a legacy SD interface and / or a PCI Express interface. The host controller 12 controls the writing and reading of data to and from the SD card 20. The host controller 12 includes a processor that executes programs. The CPU 13 controls the overall operation of the host device 10. The RAM 14 temporarily stores programs and data required for the operation of the host device 10. The SSD 15 stores programs and data required for the operation of the host device 10.

[0016] The host controller 12 also references a valid data table 16 that indicates the logical addresses of valid data stored in the SD card 20, i.e., data accessible by the host device 10. The valid data table 16 is stored in the SD card 20 and is read from the SD card 20 by the CPU 13 when the host device 10 is started. The host controller 12 may also reference the valid data table 16 that has been read from the SD card 20 and stored in the RAM 14. The valid data table 16 is also called a FAT (File Allocation Table).

[0017] The host device 10 is an example of an information processing device. Examples of the host device 10 include industrial equipment such as robots, machine tools, and IoT (Internet of Things) devices, as well as personal computers, tablet terminal devices, smartphones, and digital cameras.

[0018] The SD card 20 includes a card interface 21, a card controller 22, and a NAND flash memory 23. The card interface 21 is connected to the host interface 11 of the host device 10, and data is sent to and received from the host device 10 via the card interface 21. The card interface 21 includes, but is not limited to, a legacy SD interface and / or a PCI Express interface. The card controller 22 controls the overall operation of the SD card 20, and in particular, controls the writing and reading of data to and from the NAND flash memory 23. The card controller 22 includes a processor that executes programs and a buffer memory that temporarily stores data to be written to or read from the NAND flash memory 23. The NAND flash memory 23 includes multiple physical blocks and stores desired data.

[0019] The card controller 22 also references an address conversion table 24, an alternative block list 25, an access denial list 26, and a used area setting value 27 (described later). The address conversion table 24, the alternative block list 25, the access denial list 26, and the used area setting value 27 may be stored in a non-volatile memory provided inside or outside the card controller 22, or may be stored in the NAND flash memory 23.

[0020] The SD card 20 is an example of a semiconductor storage device. The NAND flash memory 23 is an example of a semiconductor storage element. When the NAND flash memory 23 stores the address conversion table 24, the alternate block list 25, the access denial list 26, and the used area setting value 27, the NAND flash memory 23 is an example of a non-volatile memory provided outside the card controller 22.

[0021] The functions of each component of the host device 10 and the SD card 20 are not limited to being realized by only a single physical element, but may be realized by multiple elements having different locations and / or characteristics depending on the function.

[0022] [Operation of the First Embodiment] FIG. 2 is a diagram for explaining an example of mapping of logical blocks and physical blocks in the SD card 20 of FIG.

[0023] Writing and erasing data to flash memory requires special processing. In flash memory, the unit of erasable data is fixed, and it is not possible to directly rewrite only a portion of the data contained in this unit (called a "block"). Therefore, when rewriting data written to flash memory, the entire block containing the target data must first be read into buffer memory, the necessary portion of the read block must be rewritten, and then the rewritten block must be written to an erased block of the same size.

[0024] An example of a method for managing the NAND flash memory 23 will be described with reference to FIG. 2. The physical blocks 31 are actual storage locations of data in the NAND flash memory 23. The physical blocks 31 have physical block addresses (PBA). The logical blocks 32 are virtual blocks accessible by the host device 10. The logical blocks 32 have logical block addresses (LBA). The number of logical blocks 32 is slightly less than the number of physical blocks 31. The host device 10 cannot access addresses that are not included in the logical block addresses. The address translation table 24 shows the mapping of the logical blocks 32 to the physical blocks 31. Using the address translation table 24, it is possible to access more physical blocks 31 than logical blocks 32.

[0025] Of the physical blocks 31, the remaining portion exceeding the number of logical blocks 32 is set as an alternative block to which data can be written by the card controller 22 when rewriting data stored in the NAND flash memory 23. The alternative blocks are managed using an alternative block list 25. In the alternative block list 25, the alternative blocks may be arranged in any order. For example, the alternative blocks may be arranged in ascending order of the number of times they have been rewritten. In this case, when a new alternative block is added to the alternative block list 25, the new alternative block is inserted at an appropriate position based on the number of times it has been rewritten.

[0026] The overall size of the logical block 32 area is determined according to the value C_SIZE, which indicates the physical capacity of the SD card 20. According to the SD card 20 standard (see Non-Patent Document 1), the unit of addressing by the host device 10 is also determined according to the value C_SIZE. In this embodiment, the value C_SIZE is not changed, and therefore the overall size of the logical block 32 area is also not changed. Furthermore, according to the SD card 20 standard, for example, the size of a cluster, which is a unit for managing a logical area set when performing logical formatting, is determined according to the value C_SIZE. Furthermore, the overall size of the physical block 31 area is larger than the overall size of the logical block 32 area. The remaining portion of the physical block 31 area that exceeds the area of ​​the logical block 32 is used as a replacement block as described above, and is also used to store various parameters necessary for the operation of the SD card 20.

[0027] FIG. 3 is a diagram illustrating an example of the operation of an SD card according to a comparative example. An example of a method for managing alternate blocks according to the comparative example will be described with reference to FIG. 3. For ease of explanation, FIG. 3 illustrates physical blocks 31 and logical blocks 32 as a one-dimensional array. The physical blocks 31 have physical block addresses ranging from a start address (minimum value) P1 to an end address (maximum value) P2, and the logical blocks 32 have logical block addresses ranging from a start address (minimum value) L1 to an end address (maximum value) L2. The host device 10 accesses any logical block address between the start address L1 and the end address L2. The N2=(L2-L1+1) logical blocks 32 are mapped to (L2-L1+1) of the N1=(P2-P1+1) physical blocks 31 using the address conversion table 24. The remaining (P2-P1-L2+L1) physical blocks 31 are set as alternate blocks and registered in the alternate block list 25. The mapping from the logical blocks 32 to the physical blocks 31 is not fixed, but changes dynamically in response to the writing of data.

[0028] In the example of FIG. 3, there are 12 physical blocks 31 and 9 logical blocks 32, and 3 alternate blocks are set.

[0029] As technology advances, the primary goal of NAND flash memory is to increase capacity. To increase the capacity of NAND flash memory, for example, MLC, TLC, or QLC is used instead of SLC. Because MLC, TLC, and QLC have inferior durability compared to SLC, the number of rewrites is reduced. Such large-capacity NAND flash memory is designed to guarantee the number of rewrites by writing large amounts of data to the memory and fully utilizing the entire capacity. However, if a host device writes only a small amount of data to the NAND flash memory, for example, only a few kB to a few MB of a multi-GB NAND flash memory is used, the assumption of using the entire capacity is not met, making it difficult to guarantee the number of rewrites.

[0030] The present embodiment solves the above-mentioned problem, and provides a semiconductor memory device having a longer life than conventional devices, particularly when an information processing device writes only a small amount of data to a large-capacity semiconductor memory device.

[0031] FIG. 4 is a diagram illustrating an example of the operation of the SD card 20 of FIG. 1. An example of a method for managing alternate blocks according to this embodiment will be described with reference to FIG. 4. The card controller 22 receives a used area setting value 27 from the host device 10. The used area setting value 27 indicates a number N3 that is smaller than the number N2 of logical blocks 32 (N2 = (L2 - L1 + 1)). The card controller 22 permits the host device 10 to write and read data to N3 logical blocks 32 and denies the host device 10 from writing and reading data to the remaining (N2 - N3) logical blocks 32. The card controller 22 maps the N3 logical blocks 32 to N3 physical blocks 31. The card controller 22 sets the remaining (N1 - N3) physical blocks 31 as alternate blocks.

[0032] A logical block 32 to which the host device 10 is permitted to write and read data is also called a "used area," and a logical block 32 to which the host device 10 is denied to write and read data is also called an "unused area." The card controller 22 registers logical blocks 32 in the used area in the address translation table 24, and registers logical blocks 32 in the unused area in the access denial list 26. A logical block 32 registered in the access denial list 26 is also called an "access denial block." The card controller 22 also registers alternate blocks in the alternate block list 25.

[0033] As shown in Figure 4, if the logical blocks 32 of the used area and the logical blocks 32 of the unused area each have consecutive logical block addresses and the unused area is located after the used area, the used area setting value 27 may be the maximum value L3 of the logical block address of the used area.

[0034] In the example of Fig. 4, the used area includes six logical blocks 32, and the unused area includes three logical blocks 32. As shown in Fig. 4, by setting the used area and unused area of ​​the logical blocks 32 in accordance with the used area setting value 27, the number of alternate blocks included in the alternate block list 25 is increased compared to the case of Fig. 3. Having more alternate blocks increases the number of times the NAND flash memory 23 can be rewritten, thereby extending its lifespan.

[0035] In this specification, the operation according to the embodiment shown in FIG. 4 is also referred to as the "high reliability mode," and the operation shown in FIG. 3 is also referred to as the "normal mode." The host device 10 may operate the SD card 20 in either the high reliability mode or the normal mode depending on the size of data that an application being executed writes to the SD card 20. In this case, when the host device 10 writes a large amount of data to the SD card 20, for example, data that occupies most of the capacity of the SD card 20, the host device 10 operates the SD card 20 in the normal mode. On the other hand, when the host device 10 writes only a small amount of data to a large-capacity SD card 20, the host device 10 operates the SD card 20 in the high reliability mode.

[0036] Next, an example of the operation of the host device 10 and the SD card 20 according to the first embodiment will be further described with reference to FIGS.

[0037] Fig. 5 is a flowchart showing an example of an SD card control process executed by the host controller 12 of the host device 10 in Fig. 1. Fig. 6 is a flowchart showing an example of an SD card control process executed by the card controller 22 of the SD card 20 in Fig. 1.

[0038] The processing of FIGS. 5 and 6 starts when the card interface 21 is connected to the host interface 11 and the power supply of the host controller 12 is turned on.

[0039] 5, the host controller 12 initializes the host interface 11. In step S11 of FIG.

[0040] 5 and step S12 in Fig. 6, the host controller 12 and the card controller 22 communicate with each other to initialize the card controller 22. In the initialization of the card controller 22, the card controller 22 may generate the address conversion table 24. In the initialization of the card controller 22, the host controller 12 may also receive a value C_SIZE from the card controller 22.

[0041] 5, the host controller 12 inquires about the previous used area setting value PREV_MAX from the card controller 22. In step S13 in FIG. 6, the card controller 22 reads the used area setting value 27 from the nonvolatile memory and returns it to the host controller 12 as the previous used area setting value PREV_MAX.

[0042] 5, the host controller 12 determines whether to change the used area setting value 27. If the determination is YES, the process proceeds to step S5, and if the determination is NO, the process proceeds to step S6. In step S5, the host controller 12 sends a used area setting command including the new used area setting value 27 to the card controller 22. The used area setting command may further include a flag indicating whether the SD card 20 operates in normal mode or high reliability mode.

[0043] 6, the card controller 22 determines whether or not a used area setting command has been received, and if the determination is YES, the process proceeds to step S15, and if the determination is NO, the process proceeds to step S16. In step S15, the card controller 22 executes a used area setting process to set the used area and unused area of ​​the logical block 32.

[0044] 5, the host controller 12 writes or reads data to or from the SD card 20 by sending a write or read command to the SD card 20. In step S16 of Fig. 6, the card controller 22 executes memory access processing to write or read data to or from the NAND flash memory.

[0045] In step S7 of Fig. 5, the host controller 12 determines whether to end the writing and reading of data, and if YES, ends the process, and if NO, returns to step S6. In step S17 of Fig. 6, the card controller 22 determines whether to end the writing and reading of data, and if YES, ends the process, and if NO, returns to step S16.

[0046] FIG. 7 is a flowchart showing an example of a subroutine of the use area setting process (step S15) of FIG.

[0047] In step S21, the card controller 22 calculates the size LOG_MAX(C_SIZE) of the entire area of ​​the logical block 32 based on the value C_SIZE, and sets the calculated value LOG_MAX(C_SIZE) as the initial value of the used area setting value PREV_MAX.

[0048] In step S22, card controller 22 determines whether the argument of the used area setting command is correct, and if YES, proceeds to step S23, and if NO, proceeds to step S27. Here, card controller 22 checks whether used area setting value 27 included in the used area setting command is within a settable range.

[0049] In step S23, the card controller 22 sets the used area setting value 27 included in the received used area setting command as the used area setting value PREV_MAX. The card controller 22 sets the N3 logical blocks 32 indicated by the used area setting value PREV_MAX as used areas, and sets the remaining (N2-N3) logical blocks 32 as unused areas. The card controller 22 saves the used area setting value PREV_MAX in non-volatile memory.

[0050] In step S24, the card controller 22 sets the return value of the used area setting command to "1" (i.e., success).

[0051] In step S25, the card controller 22 registers in the alternate block list 25 a physical block corresponding to the logical block 32 in the unused area.

[0052] In step S26, the card controller 22 registers the logical block 32 in the unused area in the access denial list. For example, when the card controller 22 receives a write or read command addressed to the logical block address of a logical block 32 included in the access denial list, the card controller 22 may return an error or ignore the command.

[0053] In step S27, the card controller 22 sets the return value of the used area setting command to "0" (i.e., failure), and ends the process.

[0054] By executing the process of FIG. 6, the used area and unused area of ​​the logical block 32 are set.

[0055] By saving the usage area setting value PREV_MAX set in step S23, the next time the host device 10 writes or reads data to or from the SD card 20, the SD card 20 can operate using the saved usage area setting value PREV_MAX.

[0056] FIG. 8 is a flowchart showing an example of a subroutine of the memory access process (step S16) in FIG.

[0057] In step S31, the card controller 22 determines whether the logical block address included in the write or read command received from the host controller 12 is valid, and if YES, proceeds to step S32, and if NO, proceeds to step S38. If the logical block 32 specified by this logical block address is included in the access denial list, the card controller 22 determines that the logical block address is invalid.

[0058] In step S32, the card controller 22 determines whether or not a write command has been received, and if YES, proceeds to step S33, and if NO, proceeds to step S36.

[0059] In step S33, the card controller 22 reserves an alternate block for writing the data by referring to the alternate block list 25. In step S34, the card controller 22 writes the data to the alternate block. In step S35, the card controller 22 updates the address conversion table 24. At this time, if the logical block to which the data is to be written has already been mapped to a physical block, that is, if the data is to be rewritten, the card controller 22 registers the physical block storing the original data in the alternate block list 25 and updates the address conversion table 24.

[0060] In step S36, the card controller 22 determines whether or not a read command has been received, and if YES, the process proceeds to step S37, and if NO, the process proceeds to step S17 in FIG.

[0061] In step S37, the card controller 22 reads the data stored in the specified logical block and sets the data in the buffer that stores the return value of the read command.

[0062] In step S38, the card controller 22 returns an error to the host controller 12.

[0063] By executing the process of FIG. 7, data is written to and read from the NAND flash memory.

[0064] According to the first embodiment, when the host device 10 writes only a small amount of data to a large-capacity SD card 20, the card controller 22 sets the used area and unused area of ​​the logical block 32 in accordance with the used area setting value 27, and sets the physical block 31 that would have been mapped from the logical block 32 in the unused area as an alternate block. This increases the number of alternate blocks, and as a result, the number of times the NAND flash memory 23 can be rewritten can be increased, making it possible to provide a semiconductor memory device with a longer lifespan than conventional devices.

[0065] Conventional SD cards, i.e., SD cards that do not define used and unused areas of logical blocks 32 and operate as shown in FIG. 3, have a nearly constant lifespan regardless of the amount of data written to them. For example, when 32 GB, 16 GB, or 8 GB of the total capacity of a 32 GB SD card is used, the lifespan of the SD card is the same (e.g., one year). In contrast, with the SD card 20 according to this embodiment, by defining only 16 GB of the total capacity of the 32 GB SD card as the used area, the lifespan of the SD card 20 can be doubled compared to when 32 GB is used. Furthermore, by defining only 8 GB of the total capacity of the 32 GB SD card as the used area, the lifespan of the SD card 20 can be quadrupled compared to when 32 GB is used.

[0066] When the host device 10 writes only a small amount of data to a large-capacity SD card 20, the SD card 20 can be operated in a high-reliability mode that has a longer lifespan than conventional SD cards.

[0067] Effects of the First Embodiment The SD card 20 according to the first embodiment includes a card interface 21 connected to a host device 10, a NAND flash memory 23 including a plurality of N1 physical blocks 31, and a card controller 22. The card controller 22 holds a plurality of N2 logical blocks 32, N1 or less, that can be mapped to the plurality of N1 physical blocks 31. The card controller 22 receives from the host device 10 a used area setting value indicating a number N3 that is smaller than the number N2. The card controller 22 permits the host device 10 to write and read data to N3 first logical blocks 32 among the N2 logical blocks 32. The card controller 22 denies the host device 10 from writing and reading data to (N2-N3) second logical blocks 32 other than the first logical blocks 32 among the N2 logical blocks 32. The card controller 22 maps the N3 first logical blocks 32 to N3 first physical blocks 31 among the plurality of N1 physical blocks 31. The card controller 22 sets (N1-N3) second physical blocks 31 other than the first physical block 31 out of the plurality of N1 physical blocks 31 as replacement blocks into which data can be written by the card controller 22.

[0068] This configuration makes it possible to provide a semiconductor memory device with a longer lifespan than conventional devices.

[0069] In the SD card 20 according to the first embodiment, the N3 first logical blocks 32 may have N3 consecutive logical block addresses that fall within a first range, and the (N2-N3) second logical blocks 32 may have (N2-N3) consecutive logical block addresses that fall within a second range.

[0070] This configuration makes it possible to easily set the used area and unused area of ​​the logic block 32.

[0071] The SD card 20 according to the first embodiment may further include a nonvolatile memory that stores the used area setting value received from the host device 10. In this case, the card controller 22 sets an alternate block based on the used area setting value read from the nonvolatile memory.

[0072] This configuration allows the SD card 20 to continue operating based on the previously set used area setting value.

[0073] According to the SD card 20 of the first embodiment, when the card controller 22 receives a command from the host device 10 to write or read data to the second logical block, it either returns an error to the host device 10 or ignores the command.

[0074] This configuration allows the card controller 22 to deny the host device 10 from writing or reading data to or from the second logical block 32 .

[0075] The host device 10 according to the first embodiment includes a host interface 11 connected to an SD card 20 and a host controller 12 that transmits a used area setting value to the SD card 20 .

[0076] This configuration allows the semiconductor memory device to operate with a longer life than before.

[0077] According to the host device 10 of the first embodiment, the SD card 20 may further include a nonvolatile memory that stores the used area setting value received from the host device 10. In this case, the host controller 12 receives from the SD card 20 the used area setting value read from the nonvolatile memory.

[0078] This configuration allows the SD card 20 to continue operating based on the previously set used area setting value.

[0079] Second Embodiment A semiconductor memory device and an information processing device according to a second embodiment will be described below with reference to FIG.

[0080] [Configuration of Second Embodiment] The semiconductor memory device and information processing device according to the second embodiment have the same configuration as the semiconductor memory device and information processing device according to the first embodiment.

[0081] [Operation of Second Embodiment] The second embodiment is a modification of the operation of the first embodiment, and only the parts that differ from the first embodiment will be described below.

[0082] FIG. 9 is a diagram illustrating an example of the operation of the SD card 20 according to the second embodiment. For ease of explanation, FIG. 9 shows the logical blocks 32 as a two-dimensional array. In the first embodiment, particularly in the example of FIG. 4, all logical blocks 32 having logical block addresses L3+1 to L2 are registered in the access denial list 26. The physical blocks 31 to which these logical blocks 32 were to be mapped are collectively registered in the alternate block list 25. In the second embodiment, on the other hand, any logical block 32 among the logical blocks 32 having logical block addresses L3+1 to L2 is registered in the access denial list 26. The physical block 31 to which this logical block 32 was to be mapped is registered in the alternate block list 25. In the example of FIG. 9, logical blocks 32 containing the symbol "x" are registered in the access denial list 26. Of the logical blocks 32 having logical block addresses L3+1 to L2, logical blocks 32 not containing the symbol "x" are permitted to be written to and read from by the host device 10. This allows the host device 10 to use the memory card in a special way, such as temporarily storing temporary data.

[0083] As described above, according to the second embodiment, the host controller 12 can use the access denial list 26 to freely set logical blocks 32 to which the host device 10 is denied access to write and read data. For example, the host controller 12 may register logical blocks 32 in the access denial list 26 in ascending order of logical block address, starting with the logical block 32 having logical block address L3+1. Alternatively, the host controller 12 may register logical blocks 32 in the access denial list 26 in descending order of logical block address, starting with the logical block 32 having logical block address L2. Furthermore, the host controller 12 may prohibit the registration in the access denial list 26 of logical blocks 32 having logical block addresses within a predetermined range from logical block address L2. This increases the number of rewrites of the NAND flash memory 23 while maintaining compatibility with existing host devices 19, thereby providing a semiconductor memory device with a longer lifespan than conventional devices by registering physical blocks 31 that would have been mapped from logical blocks 32 registered in the access denial list 26 in the alternate block list 25.

[0084] In the second embodiment, the used area setting command may further include a parameter for specifying a method for managing access denial blocks.

[0085] Effects of the Second Embodiment According to the SD card 20 of the second embodiment, each of the N2 logical blocks 32 may have either N3 consecutive logical block addresses that fall within a first range or (N2-N3) consecutive logical block addresses that fall within a second range. In this case, the logical block address of at least one first logical block 32 falls within the first range. Furthermore, the logical block address of at least one second logical block 32 falls within the second range.

[0086] This configuration allows the logical block 32 to be freely set to deny the host device 10 the ability to write and read data.

[0087] Third Embodiment A semiconductor memory device and an information processing device according to a third embodiment will be described below with reference to FIGS.

[0088] [Configuration of the Third Embodiment] The semiconductor memory device and information processing device according to the third embodiment have the same configuration as the semiconductor memory device and information processing device according to the first embodiment.

[0089] [Operation of the Third Embodiment] The third embodiment is a partial modification of the operation of the second embodiment, and only the parts that differ from the second embodiment will be described below.

[0090] FIG. 10 is a diagram illustrating an example of the operation of the host device 10 and the SD card 20 according to the third embodiment. As described above, the valid data table 16 indicates the logical addresses of data accessible by the host device 10. In the example of FIG. 10, a portion of the valid data is stored in one of the logical blocks 32 having logical block addresses L3+1 to L2 (i.e., the unused area in the first embodiment). Also, in the example of FIG. 10, one of the logical blocks 32 having logical block addresses L1 to L3 (i.e., the used area logical block 32 in the first embodiment) is registered in the access denial list 26. In this case, logical blocks 32 for which data writing and reading by the host device 10 is permitted and logical blocks 32 for which data writing and reading are prohibited coexist, complicating control. Therefore, it is desirable to simplify the control of data writing and reading.

[0091] Fig. 11 is a flowchart showing an example of an SD card control process executed by the host controller 12 of the host device 10 according to the third embodiment. Fig. 12 is a flowchart showing an example of an SD card control process executed by the card controller 22 of the SD card 20 according to the third embodiment. The process of Fig. 11 includes the steps of the process of Fig. 5 as well as the used area setting pre-processing of step S41. The process of Fig. 12 includes the steps of the process of Fig. 6 as well as the used area setting pre-processing of step S42.

[0092] Fig. 13 is a flowchart showing an example of a subroutine of the use area setting pre-processing (step S41) of Fig. 11. Fig. 14 is a flowchart showing an example of a subroutine of the use area setting pre-processing (step S42) of Fig. 12.

[0093] In step S51 of FIG. 13, the host controller 12 determines whether or not valid data exists in the unused area by referring to the valid data table 16, and if YES, proceeds to step S52, and if NO, proceeds to step S53.

[0094] In step S52, the host controller 12 sends a transfer command to the card controller 22 to transfer the valid data from the unused area to the used area.

[0095] In step S61 of FIG. 14, the card controller 22 determines whether or not it has received a move command from the host controller 12 to move valid data from the unused area to the used area; if YES, it proceeds to step S62; if NO, it proceeds to step S63.

[0096] In step S62, the card controller 22 moves the valid data from the unused area to the used area. Alternatively, the card controller 22 may delete the valid data from the unused area. This leaves all valid data in the used area.

[0097] 13, the host controller 12 inquires of the card controller 22 about the contents of the access denial list 26. In step S63 of FIG.

[0098] In step S54 of FIG. 13, the host controller 12 determines whether or not there is an access denial block in the used area, and if YES, the process proceeds to step S55, and if NO, the process proceeds to step S5 of FIG.

[0099] In step S55, the host controller 12 sends a move command to the card controller 22 to move the access denial block in the used area to the unused area.

[0100] In step S64 of FIG. 14, the card controller 22 determines whether or not a move command for moving the access denial block in the used area to the unused area has been received from the host controller 12; if YES, the process proceeds to step S65; if NO, the process proceeds to step S14 of FIG. 12.

[0101] In step S65, the card controller 22 moves the access denial blocks to the unused area, so that all the access denial blocks are in the unused area.

[0102] According to the third embodiment, when there is a mixture of logical blocks 32 in which the host device 10 is permitted to write and read data and logical blocks 32 in which the host device 10 is denied access, the control of data writing and reading can be simplified by moving valid data and access-denied blocks.

[0103] [Effects of the Third Embodiment, etc.] According to the SD card 20 of the third embodiment, if the logical block address of at least one second logical block 32 is included in the first range, the card controller 22 may change the logical block address of the second logical block 32 to a logical block address included in the second range.

[0104] This configuration simplifies the control of data writing and reading by moving the access denial block.

[0105] According to the SD card 20 of the third embodiment, if a logical block 32 having a logical block address included in the second range stores valid data, the card controller 22 may change the logical block address of the logical block 32 to a logical block address included in the first range.

[0106] This configuration simplifies the control of writing and reading data by moving valid data.

[0107] [Other Embodiments] As described above, the first to third embodiments have been described as examples of the technology disclosed in the present application. However, the technology in the present disclosure is not limited to these, and can be applied to embodiments in which modifications, substitutions, additions, omissions, etc. are made as appropriate.

[0108] Furthermore, the accompanying drawings and detailed description are provided to explain the embodiments. Therefore, the components described in the accompanying drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem in order to illustrate the above technology. Therefore, the fact that these non-essential components are described in the accompanying drawings or detailed description should not be interpreted as immediately identifying these non-essential components as essential.

[0109] Furthermore, since the above-described embodiments are intended to illustrate the technology of the present disclosure, various modifications, substitutions, additions, omissions, etc. may be made within the scope of the claims or their equivalents.

[0110] As described in the second embodiment, when the host controller 12 specifies a logical block 32 to be registered in the access denial list 26, the host controller 12 may send a command to the card controller 22 to query the alternate block list 25. If the alternate block list 25 contains the upper limit number of physical blocks 31 (N1-N3), it is not possible to register a new logical block 32 in the access denial list 26 and register the corresponding physical block 31 in the alternate block list 25. Furthermore, when writing new data from the host device 10 to the SD card 20 while retaining data previously stored in the SD card 20 by another host device, writing may be restricted depending on the state of the alternate block. By referencing the alternate block list 25, the host controller 12 can efficiently specify the logical blocks 32 to be registered in the access denial list 26. Furthermore, by referencing the alternate block list 25, the host controller 12 can appropriately set the used and unused areas of the logical blocks 32.

[0111] [Summary of the embodiment] A semiconductor memory device according to a first aspect of the present disclosure comprises: a first interface connected to an information processing device; a semiconductor memory element including a plurality of N1 physical blocks; and a first controller, wherein the first controller holds a plurality of N2 logical blocks, N1 or less, that can be mapped to the plurality of N1 physical blocks; receives from the information processing device a usage area setting value indicating a number N3 that is smaller than the number N2; permits the information processing device to write and read data to N3 first logical blocks among the N2 logical blocks; denies the information processing device from writing and reading data to (N2-N3) second logical blocks other than the first logical block among the N2 logical blocks; maps the N3 first logical blocks to N3 first physical blocks among the plurality of N1 physical blocks; and sets the (N1-N3) second physical blocks other than the first physical block among the plurality of N1 physical blocks as alternative blocks to which data can be written by the first controller.

[0112] According to the semiconductor memory device of the second aspect of the present disclosure, in the semiconductor memory device of the first aspect, the N3 first logical blocks have N3 consecutive logical block addresses that fall within a first range, and the (N2-N3) second logical blocks have (N2-N3) consecutive logical block addresses that fall within a second range.

[0113] According to a third aspect of the present disclosure, in the semiconductor memory device of the first aspect, each of the N2 logical blocks has either N3 consecutive logical block addresses included in a first range or (N2-N3) consecutive logical block addresses included in a second range, the logical block address of at least one of the first logical blocks is included in the first range, and the logical block address of at least one of the second logical blocks is included in the second range.

[0114] According to a fourth aspect of the present disclosure, in the semiconductor memory device of the third aspect, when the logical block address of at least one of the second logical blocks is included in the first range, the first controller changes the logical block address of the second logical block to a logical block address included in the second range.

[0115] According to a semiconductor memory device according to a fifth aspect of the present disclosure, in the semiconductor memory device according to the third or fourth aspect, when a logical block having a logical block address included in the second range stores valid data, the first controller changes the logical block address of the logical block to a logical block address included in the first range.

[0116] According to a semiconductor memory device relating to a sixth aspect of the present disclosure, in the semiconductor memory device relating to one of the first to fifth aspects, the semiconductor memory device further includes a non-volatile memory that stores a usage area setting value received from the information processing device, and the first controller sets the alternative block based on the usage area setting value read from the non-volatile memory.

[0117] According to a semiconductor memory device according to a seventh aspect of the present disclosure, in the semiconductor memory device according to one of the first to sixth aspects, when the first controller receives a command from the information processing device to write or read data to the second logical block, it returns an error to the information processing device or ignores the command.

[0118] An information processing device according to an eighth aspect of the present disclosure includes a second interface connected to a semiconductor memory device according to one of the first to seventh aspects, and a second controller that transmits the usage area setting value to the semiconductor memory device.

[0119] According to an information processing device relating to a ninth aspect of the present disclosure, in the information processing device relating to the eighth aspect, the semiconductor storage device further includes a non-volatile memory that stores the usage area setting value received from the information processing device, and the second controller receives the usage area setting value read from the non-volatile memory from the semiconductor storage device.

[0120] The present disclosure is applicable to consumer devices that use semiconductor storage devices such as SD cards, and is also applicable to industrial devices including robot control devices and industrial equipment.

[0121] REFERENCE SIGNS LIST 10 Host device 11 Host interface 12 Host controller 13 CPU (Central Processing Unit) 14 RAM (Random Access Memory) 15 SSD (Solid State Drive) 16 Valid data table 20 SD card 21 Card interface 22 Card controller 23 NAND flash memory 24 Address conversion table 25 Alternate block list 26 Access denial list 27 Used area setting value 31 Physical block 32 Logical block

Claims

1. A semiconductor memory device comprising: a first interface connected to an information processing device; a semiconductor memory element including a plurality of N1 physical blocks; and a first controller, wherein the first controller holds a plurality of N2 logical blocks, the number of which is N1 or less, that can be mapped to the plurality of N1 physical blocks; receives from the information processing device a used area setting value indicating a number N3 that is smaller than the number N2; permits the information processing device to write and read data to N3 first logical blocks among the N2 logical blocks; denies the information processing device from writing and reading data to (N2-N3) second logical blocks other than the first logical blocks among the N2 logical blocks; maps the N3 first logical blocks to N3 first physical blocks among the plurality of N1 physical blocks; and sets the (N1-N3) second physical blocks other than the first physical block among the plurality of N1 physical blocks as alternate blocks to which data can be written by the first controller.

2. The semiconductor memory device according to claim 1, wherein the N3 first logical blocks have N3 consecutive logical block addresses that fall within a first range, and the (N2-N3) second logical blocks have (N2-N3) consecutive logical block addresses that fall within a second range.

3. A semiconductor memory device according to claim 1, wherein each of the N2 logical blocks has either N3 consecutive logical block addresses included in a first range or (N2-N3) consecutive logical block addresses included in a second range, the logical block address of at least one of the first logical blocks being included in the first range, and the logical block address of at least one of the second logical blocks being included in the second range.

4. The semiconductor memory device according to claim 3, wherein, when the logical block address of at least one of the second logical blocks is included in the first range, the first controller changes the logical block address of the second logical block to a logical block address included in the second range.

5. The semiconductor memory device according to claim 3, wherein, if a logical block having a logical block address included in the second range stores valid data, the first controller changes the logical block address of the logical block to a logical block address included in the first range.

6. The semiconductor memory device according to claim 1, further comprising a non-volatile memory for storing a usage area setting value received from the information processing device, and the first controller sets the alternate block based on the usage area setting value read from the non-volatile memory.

7. The semiconductor memory device according to claim 1, wherein when the first controller receives a command from the information processing device to write or read data to the second logical block, it returns an error to the information processing device or ignores the command.

8. An information processing device comprising: a second interface connected to the semiconductor storage device according to claim 1; and a second controller that transmits the used area setting value to the semiconductor storage device.

9. The information processing device according to claim 8, wherein the semiconductor storage device further comprises a non-volatile memory for storing the usage area setting value received from the information processing device, and the second controller receives the usage area setting value read from the non-volatile memory from the semiconductor storage device.

Images