Semiconductor device

Abstract

This semiconductor device comprises: a chip having a first main surface and a second main surface; a first-conductivity-type first impurity region on the surface layer portion of the first main surface; a plurality of trenches that are on the first main surface and are arranged at a first pitch; a second-conductivity-type second impurity region and a first-conductivity-type third impurity region that are on the surface layer portion of the first impurity region and are disposed in sequence from the second-main-surface side along the side surfaces of the trenches; an embedded electroconductive layer that is embedded in the trenches and faces the second impurity region with a trench-insulating film interposed therebetween; a plurality of second-conductivity-type bottom wells respectively formed at the bottoms of the plurality of trenches; and a plurality of second-conductivity-type first lower pillars that are arranged, at a second pitch different from the first pitch, within the first impurity region below the plurality of bottom wells.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2024-106915 filed with the Japan Patent Office on July 2, 2024, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] US Pat. No. 6,299,499 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.

[0004] US Patent Application Publication No. 2015 / 0028351

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device including: a chip having a first main surface and a second main surface; a first impurity region of a first conductivity type in a surface layer portion of the first main surface; a plurality of trenches in the first main surface arranged at a first pitch; a second impurity region of a second conductivity type and a third impurity region of the first conductivity type in a surface layer portion of the first impurity region arranged in this order from the second main surface side along side surfaces of the trenches; a buried conductive layer buried in the trenches and facing the second impurity region via a trench insulating film; a plurality of bottom wells of a second conductivity type formed at bottoms of the plurality of trenches, respectively; and a plurality of first lower pillars of a second conductivity type arranged at a second pitch different from the first pitch in the first impurity region below the plurality of bottom wells.

[0006] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a plan view showing an example layout of a chip. FIG. 4 is a perspective view showing an example layout of a chip. FIG. 5 is a plan view showing a main portion of an active region. FIG. 6 is a perspective view showing a main portion of an active region. FIG. 7 is a cross-sectional view showing a main portion of an active region. FIG. 8 is a cross-sectional view showing a main portion of an active region. FIG. 9 is a diagram showing an example layout of a first lower pillar. FIG. 10 is a diagram showing an example layout of a first lower pillar. FIG. 11 is a diagram showing an example layout of a first upper pillar. FIG. 12 is a diagram showing an example layout of a first upper pillar. FIG. 13 is a diagram showing an example layout of a first lower pillar and a first upper pillar. FIG. 14 is a diagram showing an example layout of a first lower pillar and a first upper pillar. FIG. 15 is a diagram showing an example layout of a first lower pillar and a first upper pillar. FIG. 16 is a diagram showing an example layout of a first lower pillar and a first upper pillar. FIG. 17 is a diagram showing a first modified example of the semiconductor device according to the first embodiment. FIG. 18 is a diagram showing a second modified example of the semiconductor device according to the first embodiment. FIG. 19 is a diagram showing a third modified example of the semiconductor device according to the first embodiment. FIG. 20 is a diagram showing a fourth modified example of the semiconductor device according to the first embodiment. FIG. 21 is a diagram showing a fifth modified example of the semiconductor device according to the first embodiment. FIG. 22 is a diagram showing a sixth modified example of the semiconductor device according to the first embodiment. FIG. 23 is a diagram showing a seventh modified example of the semiconductor device according to the first embodiment. FIG. 24 is a diagram showing an eighth modified example of the semiconductor device according to the first embodiment. FIG. 25 is a plan view showing a main portion of the active region of the semiconductor device according to the second embodiment. FIG. 26 is a perspective view showing a main portion of the active region. FIG. 27 is a perspective view showing a main portion of the active region. FIG. 28 is a diagram showing an example layout of first lower pillars. FIG. 29 is a diagram showing an example layout of the first lower pillars. FIG. 30 is a diagram showing an example layout of the first lower pillars. FIG. 31 is a diagram showing a first modified example of the semiconductor device according to the second embodiment. FIG. 32 is a diagram showing a second modified example of the semiconductor device according to the second embodiment. FIG. 33 is a diagram showing a third modified example of the semiconductor device according to the second embodiment. FIG. 34 is a diagram showing a fourth modified example of the semiconductor device according to the second embodiment.FIG. 35 is a diagram showing a fifth modification of the semiconductor device according to the second embodiment.

[0007] [Detailed Description] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are all schematic views and are not strictly illustrative, and the scale, ratio, angle, etc. are not necessarily the same. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions will be omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0008] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0009] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "p-type" may also be referred to as the "first conductivity type" and "n-type" as the "second conductivity type." Of course, "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. Unless otherwise specified, the trivalent element is at least one of boron, aluminum, gallium, and indium. Unless otherwise specified, the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0010] <Semiconductor device 1A according to the first embodiment> (1) Overall configuration of the semiconductor device 1A Fig. 1 is a plan view showing the semiconductor device 1A according to the first embodiment. Fig. 2 is a cross-sectional view taken along line II-II shown in Fig. 1. Fig. 3 is a plan view showing an example layout of the chip 2. Fig. 4 is a perspective view showing an example layout of the chip 2.

[0011] 1 to 4, semiconductor device 1A includes chip 2 including SiC single crystal. Chip 2 may be referred to as a "SiC chip" or a "semiconductor chip." In this embodiment, chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape. Hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example is shown in which chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of another polytype.

[0012] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as a "plan view"). The vertical direction Z is also the thickness direction of the chip 2 and the normal direction to the first main surface 3 (second main surface 4). The first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.

[0013] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0014] In the circumferential direction of the chip 2 (counterclockwise in FIG. 1 ) starting from the first side surface 5A, the second side surface 5B is connected to the first side surface 5A, the third side surface 5C is connected to the second side surface 5B, and the fourth side surface 5D is connected to the first side surface 5A and the third side surface 5C. The first side surface 5A and the third side surface 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X. The second side surface 5B and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0015] In this embodiment, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal.

[0016] The XY plane including the first direction X and the second direction Y forms a horizontal plane perpendicular to the vertical direction Z. Hereinafter, an axis extending along the vertical direction Z may be referred to as a "vertical axis." Also, below, the first direction X and the second direction Y may be referred to as a "horizontal direction." The horizontal direction is also a direction extending along the first main surface 3.

[0017] 4, the chip 2 (first main surface 3 and second main surface 4) has an off angle θoff inclined at a predetermined angle in a predetermined off direction Doff with respect to the c-plane of the SiC single crystal. That is, the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction Doff by the off angle θoff. Furthermore, the c-plane of the SiC single crystal is inclined with respect to the horizontal plane by the off angle θoff.

[0018] The off-direction Doff is preferably the a-axis direction (second direction Y) of the SiC single crystal. The off-angle θoff may be greater than 0° and less than or equal to 10°. The off-angle θoff may have a value belonging to any one of the ranges of greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.

[0019] The off angle θ is preferably 5° or less. The off angle θ is particularly preferably 2° or more and 4.5° or less. The off angle θ is typically set in the range of 4°±0.1°. Of course, this specification does not exclude a configuration in which the off angle θ is 0° (i.e., a configuration in which the first main surface 3 is a just plane with respect to the c-plane).

[0020] The semiconductor device 1A includes an n-type first semiconductor layer 6 formed in a surface layer portion of the second main surface 4. A drain potential as a first potential (high potential) is applied to the first semiconductor layer 6. The first semiconductor layer 6 may also be referred to as a "semiconductor region (layer)," a "base region (layer)," a "drain region (layer)," or the like.

[0021] The first semiconductor layer 6 extends in a layered form along the second main surface 4, and forms the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor layer 6 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and has the second main surface 4 and first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor layer 6 is made of a substrate (i.e., a SiC substrate) made of SiC single crystal. The first semiconductor layer 6 has the off direction Do and off angle θo described above.

[0022] The first semiconductor layer 6 is 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value: The first semiconductor layer 6 preferably has a substantially constant n-type impurity concentration in the thickness direction.

[0023] The first semiconductor layer 6 may have a first thickness T1 of 10 μm to 500 μm. The first thickness T1 may have a value belonging to at least one of the ranges of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, 200 μm to 300 μm, 300 μm to 400 μm, and 400 μm to 500 μm.

[0024] The semiconductor device 1A includes an n-type second semiconductor layer 7 formed in a surface layer portion of the first main surface 3. The second semiconductor layer 7 may also be referred to as a "semiconductor region (layer)," a "drift region (layer)," or the like. The second semiconductor layer 7 extends in a layered form along the first main surface 3, and forms the first main surface 3 and the first to fourth side surfaces 5A to 5D.

[0025] In this embodiment, the second semiconductor layer 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal). The second semiconductor layer 7 (epitaxial layer) has the off-direction Do and off-angle θo described above. The second semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the first semiconductor layer 6.

[0026] The second semiconductor layer 7 has a lower end and an upper end. The lower end of the second semiconductor layer 7 is the starting point of crystal growth, and the upper end of the second semiconductor layer 7 is the ending point of crystal growth. The lower end of the second semiconductor layer 7 is also the bottom of the second semiconductor layer 7. Since the second semiconductor layer 7 is grown continuously from the first semiconductor layer 6, the lower end of the second semiconductor layer 7 coincides with the upper end of the first semiconductor layer 6.

[0027] The second semiconductor layer 7 includes an n-type drift region 8 as an example of a first impurity region. In this embodiment, the drift region 8 is formed by a part (n-type portion) of the second semiconductor layer 7.

[0028] The boundary between the first semiconductor layer 6 and the second semiconductor layer 7 is not necessarily visible, but can be indirectly evaluated and / or determined from other configurations or elements. The second semiconductor layer 7 has an off-direction Do and an off-angle θo that are substantially identical to the off-direction Do and the off-angle θo of the first semiconductor layer 6.

[0029] The second semiconductor layer 7 has a second thickness T2 that is less than the first thickness T1. The second thickness T2 may be 5 μm or more and 15 μm or less. The second thickness T2 may have a value that belongs to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0030] The semiconductor device 1A includes an active region 9 set in a chip 2. The active region 9 is set in an inner portion of the chip 2 at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the chip 2 in a plan view. The active region 9 is set in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The planar area of ​​the active region 9 is preferably 50% to 90% of the planar area of ​​the first main surface 3.

[0031] The semiconductor device 1A includes a peripheral region 10 that is set outside the active region 9 in the chip 2. The peripheral region 10 is provided in a region between the periphery of the chip 2 and the active region 9 in a plan view. The peripheral region 10 extends in a strip shape along the active region 9 in a plan view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 9.

[0032] The semiconductor device 1A includes a plurality of trench electrode type trench structures 11 formed on the first main surface 3 in the active region 9. The trench structures 11 may also be referred to as "gate structures" or "trench gate structures." A gate potential is applied to the plurality of trench structures 11 as a control potential. The plurality of trench structures 11 provide the active region 9 with a MIS (Metal Insulator Semiconductor) structure.

[0033] The multiple trench structures 11 are arranged at intervals inward from the periphery of the active region 9. In this embodiment, the multiple trench structures 11 are arranged at intervals in the first direction X and are each formed in a strip shape extending in the second direction Y. In other words, the multiple trench structures 11 are arranged at intervals in the m-axis direction and each extend in the a-axis direction.

[0034] In this embodiment, the multiple trench structures 11 are arranged in stripes extending in the a-axis direction (second direction Y). The extending direction of the multiple trench structures 11 coincides with the off-direction Do of the second semiconductor layer 7. The multiple trench structures 11 are formed at intervals from the lower end (first semiconductor layer 6) of the second semiconductor layer 7 toward the first major surface 3, and face the first semiconductor layer 6 with a part of the second semiconductor layer 7 sandwiched therebetween.

[0035] The semiconductor device 1A includes a plurality of p-type bottom wells 12 formed at intervals in the horizontal direction in the second semiconductor layer 7 of the active region 9. Specifically, the plurality of bottom wells 12 are formed at the bottom of trench structures 11, respectively.

[0036] The semiconductor device 1A includes a plurality of p-type first lower pillars 13 formed at intervals in the horizontal direction in the second semiconductor layer 7 of the active region 9. The first lower pillars 13 may also be referred to as "first lower column layers," "first lower pillar layers (regions)," "first lower p-type layers (regions)," "first lower p-type zones," etc.

[0037] 3 , in this embodiment, the multiple first lower pillars 13 are arranged at intervals in the second direction Y and are each formed in a strip shape extending in the first direction X. That is, the multiple first lower pillars 13 are arranged at intervals in the a-axis direction and each extend in the m-axis direction. In addition, in this embodiment, the multiple first lower pillars 13 are arranged in stripes extending in the m-axis direction (first direction X).

[0038] The first lower pillars 13 form a superjunction structure SJ together with the drift region 8 that constitutes the second semiconductor layer 7. The multiple first lower pillars 13 are formed at intervals in the horizontal direction within the second semiconductor layer 7 and define multiple n-type second lower pillars 14, each made of a part of the drift region 8. The multiple first lower pillars 13, together with the multiple second lower pillars 14, form multiple lower pn junctions that have charge balance.

[0039] The first lower pillars 13 and the second lower pillars 14 form a lower superjunction structure SJ1. The charge-balanced state refers to a state in which, for adjacent first lower pillars 13, the depletion layer extending from one lower pn junction and the depletion layer extending from the other lower pn junction are connected within the second lower pillars 14.

[0040] Semiconductor device 1A includes p-type field regions 15 formed in the surface layer of first main surface 3 in peripheral region 10 (the peripheral portion of first main surface 3). The number of field regions 15 is typically four to eight. The field regions 15 are formed in an electrically floating state and relieve the electric field within chip 2 in the peripheral portion of first main surface 3. The number, width, depth, p-type impurity concentration, etc. of field regions 15 are arbitrary and can take various values ​​depending on the electric field to be relieved.

[0041] The multiple field regions 15 are formed at intervals in the region between the periphery of the chip 2 and the active region 9. The multiple field regions 15 are formed in strip shapes extending along the active region 9 in a plan view. Each of the multiple field regions 15 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y. In this embodiment, the multiple field regions 15 are formed in an annular shape (specifically, a rectangular annular shape) surrounding the active region 9 in a plan view.

[0042] The semiconductor device 1A includes an interlayer insulating film 16 covering the first main surface 3. The interlayer insulating film 16 may be referred to as an "insulating film," an "interlayer film," an "intermediate insulating film," or the like. The interlayer insulating film 16 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0043] 1 , semiconductor device 1A includes gate pad 17 disposed on interlayer insulating film 16. Gate pad 17 is an electrode to which a gate potential is applied from the outside. Gate pad 17 may also be referred to as a "gate pad electrode," a "first pad electrode," or the like. Gate pad 17 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 16 side.

[0044] In this embodiment, the gate pad 17 is disposed on a portion of the interlayer insulating film 16 that covers the active region 9. The gate pad 17 may be disposed at a distance from the outer periphery region 10 toward the active region 9. In this embodiment, the gate pad 17 is disposed on the periphery of the active region 9 in plan view.

[0045] 1 shows an example in which gate pad 17 is arranged in a region along the center of second side surface 5B on the periphery of active region 9. Of course, gate pad 17 may also be arranged in a region along the center of any of first to fourth side surfaces 5A to 5D. Of course, gate pad 17 may also be arranged at any corner of active region 9 in plan view. Also, gate pad 17 may also be arranged in the center of active region 9 in plan view. In this embodiment, gate pad 17 is formed in a quadrangular shape in plan view.

[0046] The semiconductor device 1A includes at least one gate wiring 18 (multiple in this embodiment) extending from the gate pad 17 onto the interlayer insulating film 16. The gate wiring 18 may also be referred to as a "wiring," a "wiring electrode," a "finger electrode," a "gate finger," or the like. The multiple gate wirings 18 may have a layered structure including a Ti-based metal film and an Al-based metal film stacked in this order from the interlayer insulating film 16 side. In this embodiment, the multiple gate wirings 18 include a first gate wiring 18A and a second gate wiring 18B.

[0047] The first gate wiring 18A is drawn out from the gate pad 17 toward the first side surface 5A, and extends in a line along the periphery of the active region 9 so as to intersect (specifically, perpendicular to) part (specifically, one end) of the plurality of trench structures 11. The first gate wiring 18A is electrically connected to one end of the plurality of trench structures 11.

[0048] The second gate wiring 18B is drawn out from the gate pad 17 toward the third side surface 5C and extends in a line along the periphery of the active region 9 so as to intersect (specifically, perpendicular to) part of (specifically, the other end portions) of the plurality of trench structures 11. The second gate wiring 18B is electrically connected to the other end portions of the plurality of trench structures 11.

[0049] The semiconductor device 1A includes a source pad 19 disposed on the interlayer insulating film 16 at a distance from the gate pad 17 and the gate wiring 18. The source pad 19 is an electrode to which a source potential is applied from the outside. The source pad 19 may also be referred to as a "source pad electrode," a "second pad electrode," or the like. The source pad 19 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 16 side.

[0050] The source pad 19 is disposed on a portion of the interlayer insulating film 16 that covers the active region 9. The source pad 19 may be disposed at an interval from the peripheral region 10 toward the active region 9. In this embodiment, the source pad 19 is formed in a polygonal shape having a recess that is recessed along the gate pad 17 in a plan view. Of course, the source pad 19 may also be formed in a quadrangular shape in a plan view.

[0051] The semiconductor device 1A includes a drain pad 20 covering the second main surface 4. The drain pad 20 is an electrode to which a drain potential is applied from the outside. The drain pad 20 may also be referred to as a "drain pad electrode," a "third pad electrode," or the like. The drain pad 20 forms ohmic contact with the first semiconductor layer 6 exposed from the second main surface 4. In other words, the drain pad 20 is electrically connected to the drift region 8 via the first semiconductor layer 6.

[0052] The drain pad 20 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2. The drain pad 20 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.

[0053] The breakdown voltage that can be applied between source pad 19 and drain pad 20 (between first main surface 3 and second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to any one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0054] (2) Detailed Structure of the Active Region 9 of the Semiconductor Device 1A Fig. 5 is a plan view showing a main portion of the active region 9. Fig. 6 is a perspective view showing a main portion of the active region 9. Figs. 7 and 8 are cross-sectional views showing a main portion of the active region 9. Fig. 7 shows the surface appearing on the right front side of Fig. 6, and Fig. 8 shows the surface appearing when the semiconductor device 1A is cut along the first bottom pillar 13.

[0055] 6 to 8 , semiconductor device 1A includes p-type body region 21 formed in a surface layer portion of drift region 8. In this embodiment, body region 21, which is an example of a second impurity region, is formed in a layer shape extending along first main surface 3. Body region 21 may be formed over the entire surface layer portion of drift region 8 and exposed from first to fourth side surfaces 5A to 5D. Body region 21 is formed at an interval from the lower end of second semiconductor layer 7 toward first main surface 3.

[0056] The body region 21 is 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the body region 21 may have the following peak value: The p-type impurity concentration of the body region 21 is preferably adjusted by at least one trivalent element. The trivalent element of the body region 21 may be at least one of boron, aluminum, gallium, and indium.

[0057] As described above, the semiconductor device 1A includes trench structures 11. Referring to FIG. 5, each trench structure 11 has a trench width WT in the arrangement direction. The trench width WT is preferably less than the second thickness T2 (see FIG. 4) of the second semiconductor layer 7. The trench width WT may be not less than 0.2 μm and not more than 1.5 μm.

[0058] The trench structure 11 has a trench depth DT in the vertical direction Z. The trench depth DT is preferably less than the second thickness T2 of the second semiconductor layer 7. The trench depth DT is preferably greater than the trench width WT. In other words, the multiple trench structures 11 preferably each have an aspect ratio DT / WT such that they extend in a vertically elongated columnar shape. The aspect ratio DT / WT is the ratio of the trench width WT to the trench depth DT. The aspect ratio DT / WT may be, for example, 1 or more and 5 or less, and preferably 1 or more and 3 or less. The trench depth DT may be 0.5 μm or more and 3.0 μm or less.

[0059] 6 , the plurality of trench structures 11 are arranged at intervals of a trench pitch PT in the first direction X. The trench pitch PT is preferably less than the second thickness T2 of the second semiconductor layer 7. The trench pitch PT may be not less than 0.5 μm and not more than 6.0 μm.

[0060] Each trench structure 11 includes a trench 22, a trench insulating film 23, and a buried conductive layer 24. The trench 22 may be referred to as an "element trench," a "gate trench," etc. The trench insulating film 23 may be referred to as an "element insulating film," a "gate insulating film," etc. The buried conductive layer 24 may be referred to as a "buried electrode," a "gate electrode," etc.

[0061] The trenches 22 are formed in the first main surface 3 and define the inner surfaces (side surfaces 25 and bottom surfaces 26 shown in FIGS. 6 to 8 ) of the trench structure 11. The bottom surfaces 26 of the trenches 22 preferably have a flat portion. Between adjacent trenches 22, mesa portions 27 are formed by part of the second semiconductor layer 7. The mesa portions 27 may also be referred to as "element mesa portions."

[0062] 5, the trench structures 11 (trenches 22) and mesa portions 27 are strip-shaped and extend along the second direction Y, and are arranged alternately in the first direction X. The trenches 22 and mesa portions 27 are arranged in a stripe pattern as a whole. The mesa width WM of the mesa portion 27 is preferably wider than the trench width WT. The mesa width WM may be 0.4 μm or more and 3.0 μm or less.

[0063] 7 and 8 , it is particularly preferable that the flat portion of bottom surface 26 of trench 22 extends substantially parallel to first major surface 3. That is, bottom surface 26 of trench 22 preferably has an off angle θo inclined at a predetermined angle in a predetermined off direction Do (see FIG. 4 ) with respect to the c-plane. That is, bottom surface 26 of trench 22 preferably has a flat portion extending in off direction Do. Of course, bottom surface 26 of trench 22 may be curved in an arc shape toward the lower end side of second semiconductor layer 7.

[0064] The trench insulating film 23 covers the inner surface of the trench 22. The trench insulating film 23 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the trench insulating film 23 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the trench insulating film 23 include a silicon oxide film made of an oxide of the chip 2.

[0065] The buried conductive layer 24 is buried in the trench 22 and faces the channel across the trench insulating film 23. In this embodiment, the buried conductive layer 24 faces the body region 21 across the trench insulating film 23. The buried conductive layer 24 may include p-type or n-type conductive polysilicon.

[0066] As described above, the semiconductor device 1A includes the bottom well 12. The bottom well 12 is formed in the bottom of the trench structure 11. More specifically, the bottom well 12 is formed in the bottom of the trench 22. The bottom well 12 is exposed from the bottom surface 26 of the trench 22 and is in contact with the trench insulating film 23. Therefore, the upper end of the bottom well 12 is exposed at the bottom surface 26 of the trench structure 11 (trench 22). The bottom well 12 relieves the electric field applied to the bottom of the trench 22. The bottom well 12 may also be referred to as an "electric field relaxation region," "electric field relaxation layer," "bottom electric field relaxation region," "bottom electric field relaxation layer," etc.

[0067] The bottom well 12 faces the buried conductive layer 24 via the trench insulating film 23 in the depth direction of the trench 22. At the bottom of the trench 22, the trench insulating film 23 is sandwiched between the buried conductive layer 24 and the bottom well 12.

[0068] The bottom well 12 is formed in the bottom of the trench 22 over the entire extension direction of the trench 22, and is formed in a band shape extending in the extension direction of the trench 22. With reference to Figures 7 and 8, the bottom well 12 is formed across the width direction of the trench 22, spanning between one end and the other end of the trench 22. In this embodiment, the bottom well 12 has, in the depth direction of the trench 22, one side surface formed on approximately the same plane as one side surface 25 of the trench 22 in the width direction, and another side surface formed on approximately the same plane as the other side surface 25 of the trench 22 in the width direction.

[0069] The impurity concentration of the bottom well 12 may be higher than that of the body region 21. The bottom well 12 may have an impurity concentration of, for example, 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration of the bottom well 12 may have the following peak value: The p-type impurity concentration of the bottom well 12 is preferably adjusted by at least one trivalent element. The trivalent element of the bottom well 12 may be at least one of boron, aluminum, gallium, and indium.

[0070] The plurality of bottom wells 12 overlap the plurality of trench structures 11 in the depth direction of the trench 22. Specifically, the plurality of bottom wells 12 overlap the plurality of trench structures 11 in a one-to-one correspondence in the thickness direction of the chip 2. In this configuration, the plurality of bottom wells 12 are connected to the bottom surfaces 26 of the corresponding trench structures 11. Therefore, the plurality of bottom wells 12 are arranged at intervals of the trench pitch PT in the first direction X.

[0071] The bottom well 12 has a relaxation depth DR in the vertical direction Z. The relaxation depth DR is preferably 0.1 μm or more and 1.5 μm or less. Each of the plurality of bottom wells 12 has a relaxation width WR in the arrangement direction. The relaxation width WR may be 0.2 μm or more and 1.5 μm or less.

[0072] The semiconductor device 1A includes a source region 28 as an example of a third impurity region in a surface layer portion of the first main surface 3. The source region 28 is formed in a region between the plurality of trench structures 11. The source region 28 is formed in a surface layer portion of the body region 21.

[0073] In this embodiment, a plurality of source regions 28 are formed across the mesa portion 27 in the width direction, from one side surface 25 of the mesa portion 27 to the other side surface 25 (one side surface 25 and the other side surface 25 of the trench 22). The plurality of source regions 28 are arranged at intervals in each mesa portion 27 along the extension direction of the trench 22. As a result, in each mesa portion 27, a plurality of channel sections CH are arranged at intervals in the second direction Y (extension direction of the trench 22). In the channel sections CH, channels are formed on both side surfaces 25 of the trench 22 on both sides of the mesa portion 27 in the first direction X.

[0074] The source region 28 has a higher n-type impurity concentration (peak value) than the second semiconductor layer 7 (drift region 8). １８ cm －３ 1x10 or more ２１ cm －３ The n-type impurity concentration may have the following peak value:

[0075] The semiconductor device 1A includes a body contact region 29 in a surface layer portion of the first main surface 3. The body contact region 29 is formed in a region between the plurality of trench structures 11. The body contact region 29 is formed adjacent to the source region 28 in a surface layer portion of the body region 21.

[0076] In this embodiment, a plurality of body contact regions 29 are formed across the mesa portion 27 in the width direction, from one side surface 25 to the other side surface 25 of the mesa portion 27. In each mesa portion 27, the plurality of source regions 28 and the plurality of body contact regions 29 are alternately arranged along the extension direction of the trench 22. Each of the source regions 28 and each of the body contact regions 29 is exposed from both side surfaces 25 of the trench 22 (both side surfaces 25 of the mesa portion 27).

[0077] 5 to 7, drift region 8 includes a stacked structure of base region 30 and high concentration region 31.

[0078] The base region 30 is formed closer to the second main surface 4 than the bottom well 12 and away from the body region 21. The base region 30 is formed in a layer shape extending along the first main surface 3 at a position away from the trench 22 and the bottom well 12 toward the second main surface 4. The base region 30 is formed over the entire surface portion of the second semiconductor layer 7 on the second main surface 4 side, and may be exposed from the first to fourth side surfaces 5A to 5D. The base region 30 forms the boundary surface of the second semiconductor layer 7 with the first semiconductor layer 6.

[0079] The n-type impurity concentration of the base region 30 is preferably lower than the n-type impurity concentration of the first semiconductor layer 6. The base region 30 has a dopant concentration of 1×10 １５ cm －３ 5x10 or more １６ cm －３ The n-type impurity concentration of the base region 30 may have a peak value of the following: The n-type impurity concentration of the base region 30 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the base region 30 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0080] The heavily doped regions 31 are formed between the base region 30 and the body region 21, on the sides of and below the trench 22 and the bottom well 12. In this embodiment, the heavily doped regions 31 further include a stacked structure of an upper heavily doped region 32 and a lower heavily doped region 33.

[0081] The upper heavily doped region 32 forms an upper layer in the stacked structure of the heavily doped region 31. The upper heavily doped region 32 is formed in a layer shape that contacts the body region 21 and extends along the first main surface 3. The upper heavily doped region 32 is formed over the entire surface portion of the drift region 8 on the first main surface 3 side, and may be exposed from the first to fourth side surfaces 5A to 5D. In this embodiment, the upper heavily doped region 32 forms a boundary surface between the drift region 8 and the body region 21.

[0082] The n-type impurity concentration of the upper heavily doped region 32 is preferably higher than the n-type impurity concentration of the base region 30. The upper heavily doped region 32 has an n-type impurity concentration of 1×10 １６ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration of the upper heavily doped region 32 may have a peak value of the following: The n-type impurity concentration of the upper heavily doped region 32 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the upper heavily doped region 32 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0083] The upper heavily doped region 32 is formed in the thickness direction of the chip 2 at a depth from the body region 21 to a depth deeper than the bottom of the trench 22. The upper heavily doped region 32 contacts the side of the bottom well 12 over the entire area from the first main surface 3 side to the second main surface 4 side in the thickness direction of the chip 2.

[0084] The lower highly doped region 33 forms a lower layer in the stacked structure of the high concentration region 31. The lower highly doped region 33 is formed on the second main surface 4 side relative to the upper highly doped region 32. The lower highly doped region 33 is sandwiched between the upper highly doped region 32 and the base region 30 in the thickness direction of the chip 2. The lower highly doped region 33 is formed in a layer shape extending along the first main surface 3, and may be exposed from the first to fourth side surfaces 5A to 5D.

[0085] In this embodiment, the lower heavily doped region 33 is formed in the thickness direction of the chip 2 from the bottom of the bottom well 12 to the base region 30. The lower heavily doped region 33 covers the bottom of the bottom well 12.

[0086] The n-type impurity concentration of the lower heavily doped region 33 is preferably higher than the n-type impurity concentration of the base region 30 and higher than the n-type impurity concentration of the upper heavily doped region 32. The lower heavily doped region 33 has an n-type impurity concentration of 1×10 １８ cm －３ 1x10 or more １９ cm －３ The n-type impurity concentration of the lower heavily doped region 33 may have a peak value of the following: The n-type impurity concentration of the lower heavily doped region 33 may be substantially constant in the thickness direction. Of course, the n-type impurity concentration of the lower heavily doped region 33 may have a concentration gradient that gradually increases and / or decreases in the thickness direction (crystal growth direction) of the chip 2.

[0087] In this embodiment, the n-type impurity concentrations of the base region 30, the upper heavily doped region 32, and the lower heavily doped region 33 are adjusted by nitrogen. The base region 30, the upper heavily doped region 32, and the lower heavily doped region 33 may have n-type impurity concentrations adjusted by at least one pentavalent element. For example, the n-type impurity concentrations of the base region 30, the upper heavily doped region 32, and the lower heavily doped region 33 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0088] 6 and 8 , the semiconductor device 1A includes a plurality of first lower pillars 13, as described above. Each first lower pillar 13 extends in a line across the plurality of trenches 22 and is connected to the bottom well 12 below each trench 22. The plurality of first lower pillars 13 are arranged at a lower pillar pitch PL that is different from the trench pitch PT. In this embodiment, the lower pillar pitch PL is narrower than the trench pitch PT. The lower pillar pitch PL may be 0.4 μm or more and 3.0 μm or less. The lower pillar pitch PL may be a fractional multiple of the trench pitch PT. For example, the lower pillar pitch PL may be 1 / 3 to 1 / 2 times the trench pitch PT.

[0089] The first bottom width W1 of the first bottom pillar 13 may be smaller than the bottom pillar pitch PL. The first bottom width W1 may be 0.2 μm or more and 1.5 μm or less. The first bottom width W1 may be constant in the thickness direction of the chip 2.

[0090] The impurity concentration (acceptor concentration Na) of the first lower pillar 13 is lower than the impurity concentration of the bottom well 12. The first lower pillar 13 has an impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the first bottom pillar 13 may have the following peak value. The p-type impurity concentration of the first bottom pillar 13 is preferably adjusted with at least one trivalent element. In this embodiment, the p-type impurity concentration of the first bottom pillar 13 is adjusted with aluminum.

[0091] The multiple first lower pillars 13 are arranged in the high concentration region 31. Preferably, the multiple first lower pillars 13 are arranged in the lower high concentration region 33, which has a relatively higher concentration, of the upper high concentration region 32 and the lower high concentration region 33. The multiple first lower pillars 13 extend from the upper surface to the lower surface of the lower high concentration region 33 in the thickness direction of the chip 2. The multiple first lower pillars 13 may extend in a direction normal to the first main surface 3.

[0092] The multiple first lower pillars 13 penetrate the lower heavily doped region 33 in the thickness direction of the chip 2, dividing the lower heavily doped region 33 into multiple regions. Each of the multiple divided regions is the above-mentioned second lower pillar 14. The second lower width W2 of the second lower pillar 14 may be larger than the first lower width W1. The second lower width W2 may be 0.2 μm or more and 1.5 μm or less.

[0093] The second lower pillar 14 is formed by the lower high-concentration region 33. Therefore, the impurity concentration (donor concentration Nd) of the second lower pillar 14 is the same as the impurity concentration of the lower high-concentration region 33. The second lower pillar 14 has an impurity concentration of 1×10 １８ cm －３ 1x10 or more １９ cm －３ The n-type impurity concentration may have the following peak value:

[0094] In the lower superjunction structure SJ1, the fact that the effective acceptor concentration (Na-Ndb) of the first lower pillar 13 and the donor concentration Nd of the second lower pillar 14 are close to each other contributes to stabilizing the charge balance of the lower superjunction structure SJ1. The charge balance is stabilized, for example, if it is within a range of 0.9 to 1.1 in the section from the top to the bottom of the first lower pillar 13 in the thickness direction of the chip 2.

[0095] Using the donor concentration Nd of the second lower pillar 14, the acceptor concentration Na of the first lower pillar 13, the second lower width W2, and the first lower width W1, the charge balance CB between the first lower pillar 13 and the second lower pillar 14 is expressed by the following equation (1).

[0096] CB = (Nd × W2) / (Na × W1) ... (1) Therefore, the donor concentration Nd of the second lower pillar 14, the acceptor concentration Na of the first lower pillar 13, the second lower width W2, and the first lower width W1 can be set appropriately so that the charge balance CB is in the range of 0.9 to 1.1.

[0097] 6 and 8 , the semiconductor device 1A includes a plurality of first upper pillars 34. Each first upper pillar 34 extends linearly in the first direction X. Each first upper pillar 34 is disposed apart from the side surface 25 of the trench 22 in each mesa portion 27. The plurality of first upper pillars 34 extend integrally from the first lower pillar 13 toward the first main surface 3 and are connected to the body region 21. The first upper pillar 34 electrically connects the body region 21 and the first lower pillar 13. The first upper pillar 34 also electrically connects the body region 21 and the bottom well 12 via the first lower pillar 13.

[0098] The multiple first upper pillars 34 are arranged at an upper pillar pitch PU that is different from the trench pitch PT. In this embodiment, the upper pillar pitch PU is narrower than the trench pitch PT. In this embodiment, the upper pillar pitch PU is equal to the lower pillar pitch PL. The upper pillar pitch PU may be 0.4 μm or greater and 3.0 μm or less. The upper pillar pitch PU may be a fractional multiple of the trench pitch PT. For example, the upper pillar pitch PU may be 1 / 3 to 1 / 2 times the trench pitch PT. The multiple first upper pillars 34 are connected to the multiple first lower pillars 13 and are arranged along the second direction Y at the same intervals as the multiple first lower pillars 13. In this embodiment, the first lower pillars 13 and the first upper pillars 34 may be considered as an integrated impurity region and may be simply referred to as a "first pillar," a "first pillar region," or the like.

[0099] The first upper width W3 of the first upper pillar 34 may be smaller than the upper pillar pitch PU. The first upper width W3 may be 0.2 μm or more and 1.5 μm or less. The first upper width W3 may vary in the thickness direction of the chip 2.

[0100] For example, the first upper pillar 34 may have a convex portion 35 that selectively bulges on both sides in the width direction. The first upper pillar 34 may include an upper tapered portion 36 whose width narrows from the convex portion 35 toward the first main surface 3, and a lower tapered portion 37 whose width narrows from the convex portion 35 toward the second main surface 4. The convex portion 35 may be located closer to the first main surface 3 than the center of the first upper pillar 34 in the depth direction. Therefore, the lower tapered portion 37 may be longer than the upper tapered portion 36 in the thickness direction of the chip 2.

[0101] The first upper width W3 of the first upper pillar 34 described above may be the width of the first upper pillar 34 at the position where the protrusion 35 is arranged. The width of the lower tapered portion 37 is narrower than the first upper width W3 and equal to the first lower width W1. The lower tapered portion 37 is connected to the first bottom pillar 13 so that its side edge is continuous with the side edge of the first bottom pillar 13.

[0102] The impurity concentration (acceptor concentration Na) of the first upper pillar 34 is lower than the impurity concentration of the bottom well 12. The first upper pillar 34 has an impurity concentration of 1×10 １５ cm －３ 1x10 or more １８ cm －３ The p-type impurity concentration of the first upper pillar 34 may have the following peak value. The p-type impurity concentration of the first upper pillar 34 is preferably adjusted with at least one trivalent element. In this embodiment, the p-type impurity concentration of the first upper pillar 34 is adjusted with aluminum.

[0103] 8 , each first upper pillar 34 is disposed apart from the side surface 25 of the trench 22 in each mesa portion 27. As a result, an isolation region 38 made of a part of the drift region 8 (in this embodiment, the upper heavily doped region 32) is disposed between the first upper pillar 34 and the trench 22 and the bottom well 12 in the first direction X. The isolation region 38 physically separates the first upper pillar 34 from the trench 22.

[0104] The multiple first upper pillars 34 are arranged in the high-concentration region 31. Preferably, the multiple first upper pillars 34 are arranged in the upper high-concentration region 32, which has a relatively lower concentration, of the upper high-concentration region 32 and the lower high-concentration region 33. The multiple first upper pillars 34 extend from the body region 21 to the first lower pillar 13 in the thickness direction of the chip 2. The multiple first upper pillars 34 may extend in a direction normal to the first main surface 3.

[0105] The multiple first upper pillars 34 penetrate the upper heavily doped region 32 in the thickness direction of the chip 2, dividing the upper heavily doped region 32 into multiple regions. Each of the multiple divided regions is a second upper pillar 39. Referring to FIG. 6 , the second upper pillar 39 is sandwiched between two first upper pillars 34 in the second direction Y. The second upper pillar 39 has a recess 40 in a portion that contacts the protrusion 35. The multiple first upper pillars 34 and the multiple second upper pillars 39 form an upper superjunction structure SJ2.

[0106] The second upper width W4 of the second upper pillar 39 may be larger than the first upper width W3. The second upper width W4 may be 0.2 μm or more and 1.5 μm or less.

[0107] The second upper pillar 39 is formed from the upper heavily doped region 32. Therefore, the impurity concentration (donor concentration Nd) of the second upper pillar 39 is equal to the impurity concentration of the upper heavily doped region 32. The second upper pillar 39 has an impurity concentration of 1×10 １６ cm －３ 1x10 or more １８ cm －３ The n-type impurity concentration may have the following peak value:

[0108] As described above, the semiconductor device 1A includes the interlayer insulating film 16 on the first main surface 3. A plurality of contact openings 41 are formed in the interlayer insulating film 16. The plurality of contact openings 41 include a plurality of contact openings 41 (not shown) that expose the plurality of trench structures 11 (buried conductive layer 24) and a plurality of contact openings 41 that expose the plurality of source regions 28. The plurality of contact openings 41 for the source regions 28 are formed in regions between the plurality of trench structures 11, and expose the plurality of source regions 28 and a plurality of body contact regions 29.

[0109] 7 and 8 , semiconductor device 1A includes a first main surface electrode 42. First main surface electrode 42 is formed on first main surface 3 so as to cover interlayer insulating film 16. First main surface electrode 42 has a laminated structure including a barrier layer 43 and a main body layer 44 laminated in this order from the first main surface 3 side.

[0110] The barrier layer 43 is formed in a film shape along the first main surface 3 and the inner surface of the contact opening 41. The barrier layer 43 is in ohmic contact with the first main surface 3. The barrier layer 43 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer.

[0111] The main body layer 44 is formed on the barrier layer 43. The main body layer 44 covers the entire main surface of the barrier layer 43. The main body layer 44 is electrically connected to the source region 28 and the body contact region 29 via the barrier layer 43. Therefore, in the semiconductor device 1A, the first main surface electrode 42 may include the aforementioned source pad 19. Although not shown, in the semiconductor device 1A, the first main surface electrode 42 may also include the aforementioned gate pad 17 and gate wiring 18. The bottom well 12, the first upper pillar 34, and the first lower pillar 13 are fixed to the source potential via the body contact region 29 and the body region 21.

[0112] The main body layer 44 includes at least one of a pure Al layer (meaning an Al layer made of Al with a purity of 99% or more), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0113] The semiconductor device 1A includes a resin layer 45 covering the first principal surface electrode 42. The resin layer 45 is formed in a film shape along the principal surface of the first principal surface electrode 42. The resin layer 45 may include a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The resin layer 45 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the resin layer 45 includes polybenzoxazole. Note that a passivation film (not shown) made of an insulating film such as silicon nitride may be interposed between the resin layer 45 and the first principal surface electrode 42.

[0114] (3) Layout of Superjunction Structures SJ1 and SJ2 Hereinafter, examples of the layout of the superjunction structures SJ1 and SJ2 of the semiconductor device 1A will be described with reference to FIGS.

[0115] 9 and 10 are plan view layouts of the first lower pillar 13 and the second lower pillar 14, illustrating an example layout of the lower superjunction structure SJ1. In FIGS. 9 and 10, the first lower pillar 13 is indicated by dot hatching, and the second lower pillar 14 is indicated by white space.

[0116] 9 and 10 , the first lower pillars 13 are formed in stripes that continuously cross the trenches 22 and the mesas 27. The second lower pillars 14 are also formed in stripes that continuously cross the trenches 22 and the mesas 27.

[0117] 9 , the lower extension direction De1 of the multiple first lower pillars 13, which is an example of a first intersecting direction, is a direction perpendicular to the extension direction (in this embodiment, the second direction Y) of the multiple trenches 22. Therefore, the multiple first lower pillars 13 and the multiple second lower pillars 14, which are linear and perpendicular to the multiple trenches 22, are arranged alternately in the second direction Y.

[0118] The lower arrangement direction Da1 of the first lower pillars 13 may be the a-axis direction (second direction Y), and the lower extension direction De1 of the first lower pillars 13 may be the m-axis direction (first direction X). In this case, the lower extension direction De1 intersects (specifically, is perpendicular to) the off-direction Doff of the second semiconductor layer 7, and therefore the multiple first lower pillars 13 are inclined by approximately the off-angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane ((1-100) plane) of the SiC single crystal. The m-plane of the SiC single crystal is a crystal plane perpendicular to the m-axis direction.

[0119] 10 , the lower extension direction De1 of the multiple first lower pillars 13, which is an example of a first intersecting direction, may intersect the multiple trenches 22 non-orthogonally. That is, the lower arrangement direction Da1 of the first lower pillars 13 may be a direction other than the m-axis direction (first direction X) and the a-axis direction (second direction Y), and the lower extension direction De1 of the first lower pillars 13 may be a direction other than the m-axis direction and the a-axis direction. In this case, the lower extension direction De1 intersects (specifically, is perpendicular to) the off-direction Doff of the second semiconductor layer 7, and therefore the multiple first lower pillars 13 are inclined by approximately the off-angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view taken from the m-plane ((1-100) plane) of the SiC single crystal. The m-plane of the SiC single crystal is a crystal plane perpendicular to the m-axis direction. For example, the lower extension direction De1 may be inclined from the a-axis toward one side (the left side of the paper) or the other side (the right side of the paper) of the m-axis in a plan view. When the a-axis is taken as the reference (0°), the multiple first lower pillars 13 have the lower extension direction De1 that forms a first extension angle θa1 with the a-axis.

[0120] The absolute value of the first extension angle θa1 may be greater than 0° and less than 90°. The first extension angle θa1 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or greater and less than 36°, 36° or greater and less than 54°, 54° or greater and less than 72°, and 72° or greater and less than 90°. The absolute value of the first extension angle θa1 is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0121] 11 and 12 are plan view layouts of the first upper pillar 34 and the second upper pillar 39, illustrating an example layout of the upper superjunction structure SJ2. In FIGS. 11 and 12, the first upper pillar 34 is indicated by cross-hatching, and the second upper pillar 39 is indicated by white outline.

[0122] 11 and 12 , the multiple first upper pillars 34 are arranged in a line along the intersecting direction of the multiple trenches 22. In this embodiment, the multiple first upper pillars 34 are arranged in a one-to-one correspondence with the multiple mesas 27, and the multiple first upper pillars 34 are arranged on the same straight line at intervals. The first upper pillars 34 of each mesa 27 have an end 46 at a position spaced apart from the trench 22 toward the inside of the mesa 27 in plan view.

[0123] The area between this end and the trench 22 is the isolation region 38. By providing the isolation region 38, a current path can be secured in the channel of the strip-shaped region (arrangement region 47) where the multiple first upper pillars 34 are arranged. The current flowing through this current path avoids the first lower pillars 13 (in this embodiment, avoids both sides in the second direction Y) and heads toward the first semiconductor layer 6 (see arrow I in FIG. 11 ).

[0124] The second upper pillars 39 are formed in stripes that continuously cross the trenches 22 and the mesas 27 .

[0125] 11 , the upper extension direction De2 of the multiple first upper pillars 34 (the direction in which the multiple first upper pillars 34 are arranged in a line) as an example of the first intersecting direction is a direction perpendicular to the extension direction (in this embodiment, the second direction Y) of the multiple trenches 22. Therefore, the multiple first upper pillars 34 and the multiple second upper pillars 39 in a line shape perpendicular to the multiple trenches 22 are arranged alternately in the second direction Y.

[0126] The upper arrangement direction Da2 of the first upper pillars 34 may be the a-axis direction (second direction Y), and the upper extension direction De2 of the first upper pillars 34 may be the m-axis direction (first direction X). The upper arrangement direction Da2 includes a direction in which a plurality of first upper pillars 34 assembled in a line is defined as one unit and the first upper pillars 34 are arranged at intervals. In this case, the upper extension direction De2 intersects (specifically, is perpendicular to) the off-direction Doff of the second semiconductor layer 7, and therefore the plurality of first upper pillars 34 are inclined by approximately the off-angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane ((1-100) plane) of the SiC single crystal. The m-plane of the SiC single crystal is a crystal plane perpendicular to the m-axis direction.

[0127] 12 , the upper extension direction De2 of the multiple first upper pillars 34, which is an example of a first intersecting direction, may intersect the multiple trenches 22 non-orthogonally. That is, the upper arrangement direction Da2 of the first upper pillars 34 may be a direction other than the m-axis direction (first direction X) and the a-axis direction (second direction Y), and the upper extension direction De2 of the first upper pillars 34 may be a direction other than the m-axis direction and the a-axis direction. In this case, since the upper extension direction De2 intersects (specifically, is perpendicular to) the off-direction Doff of the second semiconductor layer 7, the multiple first upper pillars 34 are inclined by approximately the off-angle θoff from the vertical axis toward the off-direction Doff in a cross-sectional view taken from the m-plane ((1-100) plane) of the SiC single crystal. The m-plane of the SiC single crystal is a crystal plane perpendicular to the m-axis direction. For example, the upper extending direction De2 may be inclined from the a-axis toward one side (the left side of the paper) or the other side (the right side of the paper) of the m-axis in a plan view. When the a-axis is set as a reference (0°), the multiple first upper pillars 34 have the upper extending direction De2 that forms a second extending angle θa2 with the a-axis.

[0128] The absolute value of the second extension angle θa2 may be greater than 0° and less than 90°. The second extension angle θa2 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or greater and less than 36°, 36° or greater and less than 54°, 54° or greater and less than 72°, and 72° or greater and less than 90°. The absolute value of the second extension angle θa2 is typically set to a value belonging to any one of the ranges of 30°±5°, 45°±5°, and 60°±5°.

[0129] 13 to 16 are diagrams showing layout examples of the first lower pillars 13 and the first upper pillars 34. Figures 13 to 16 show the overlapping state of the first lower pillars 13 and the first upper pillars 34 in a plan view. In Figures 13 to 16, the first lower pillars 13 are indicated by dot hatching, and the first upper pillars 34 are indicated by cross hatching.

[0130] 13, the first lower pillar 13 and the first upper pillar 34 may completely overlap in a plan view. With reference to FIGS. 14 to 16, the first lower pillar 13 and the first upper pillar 34 may partially overlap in a plan view, but may not overlap in a remainder.

[0131] 13 , the lower extension direction De1 and the upper extension direction De2 are both perpendicular to the extension direction of the multiple trenches 22. The lower pillar pitch PL and the upper pillar pitch PU are equal. The multiple first upper pillars 34 are arranged at intervals along a strip-shaped region (arrangement region 47) directly above each first lower pillar 13.

[0132] 14 , the lower extension direction De1 is perpendicular to the extension direction of the multiple trenches 22, whereas the upper extension direction De2 is non-perpendicular to the extension direction of the multiple trenches 22. As a result, the first upper pillar 34 includes an overlapping area 48 that overlaps with the first lower pillar 13 in a plan view, and a non-overlapping area 49 that does not overlap with the first lower pillar 13.

[0133] 15 , both the lower extension direction De1 and the upper extension direction De2 are non-orthogonal to the extension direction of the multiple trenches 22. However, the first extension angle θa1 and the second extension angle θa2 are different from each other. In other words, the lower extension direction De1 and the upper extension direction De2 intersect with each other. As a result, the first upper pillar 34 includes an overlapping area 48 that overlaps with the first lower pillar 13 in a plan view, and a non-overlapping area 49 that does not overlap with the first lower pillar 13.

[0134] 16 , the lower extension direction De1 is non-orthogonal to the extension direction of the multiple trenches 22, whereas the upper extension direction De2 is orthogonal to the extension direction of the multiple trenches 22. As a result, the first upper pillar 34 includes an overlapping area 48 that overlaps with the first lower pillar 13 in a plan view, and a non-overlapping area 49 that does not overlap with the first lower pillar 13.

[0135] (4) Effects of the Semiconductor Device 1A According to the semiconductor device 1A, the multiple first lower pillars 13 are arranged at a lower pillar pitch PL that is different from the trench pitch PT. This allows the lower pillar pitch PL to be set independently of the trench pitch PT. Therefore, even if the lower heavily doped region 33 is made more concentrated than the upper heavily doped region 32, the charge balance CB can be made closer to 1 by appropriately adjusting the lower pillar pitch PL. As a result, the charge balance CB can be stabilized. Furthermore, the lower heavily doped region 33, which has a higher concentration than the upper heavily doped region 32, can be used as part of the drift region 8 (the second lower pillar 14), thereby reducing the on-resistance of the MISFET in the active region 9.

[0136] On the other hand, in the upper region of the drift region 8 where the MIS structure is arranged, it is not necessary to narrow the trench pitch PT according to the lower pillar pitch PL. Therefore, it is possible to prevent the current path from being constricted due to the trench pitch PT being too narrow, thereby suppressing an increase in on-resistance. Furthermore, since the upper heavily doped region 32, which has a lower concentration than the lower heavily doped region 33, can be formed on the side of the bottom well 12 (electric field relaxation layer), it is possible to effectively alleviate electric field concentration near the bottom of the trench 22. As a result, the trench insulating film 23 can be appropriately protected.

[0137] (5) Modifications of the Semiconductor Device 1A Modifications applied to the semiconductor device 1A will be described below with reference to Figures 17 to 24. Figures 17 to 24 are diagrams showing first to eighth modifications of the semiconductor device 1A, respectively.

[0138] 17 , the lower pillar pitch PL may be smaller than the upper pillar pitch PU. The plurality of first lower pillars 13 may include contact pillars 13A connected to the first upper pillars 34 and non-contact pillars 13B that are physically separated from the first upper pillars 34 and do not come into contact with them.

[0139] 18 , when the upper pillar pitch PU is equal to the lower pillar pitch PL, the multiple first lower pillars 13 may be arranged offset from the multiple first upper pillars 34 in the second direction Y. As a result, the multiple first lower pillars 13 may be multiple non-contact pillars 13B that are physically separated from and do not contact the first upper pillars 34.

[0140] 19 , the lower pillar pitch PL may be greater than the upper pillar pitch PU. The plurality of first lower pillars 13 may include contact pillars 13A connected to the first upper pillars 34 and non-contact pillars 13B that are physically separated from the first upper pillars 34 and do not come into contact with them.

[0141] 20 , the first lower pillars 13 may extend in a direction inclined with respect to the normal direction to the first main surface 3. For example, if the second semiconductor layer 7 has an axial channel in the thickness direction of the chip 2, the depth direction of the first lower pillars 13 may be inclined with respect to the axial channel. The axial channel is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the second semiconductor layer 7, and is surrounded by atomic rows constituting a crystal axis extending in the stacking direction (crystal growth direction). In this embodiment, the axial channel is composed of a region surrounded by atomic rows aligned with the c-axis ((0001) axis) of the SiC single crystal. That is, the axial channel extends along the c-axis and has the off direction Doff and off angle θoff described above.

[0142] Referring to Figure 21, in this embodiment, the buried conductive layer 24 is buried in the trench 22 at a distance from the first main surface 3 toward the bottom surface 26 of the trench 22, and defines an open recess 50 at the opening end of the trench 22 that is recessed toward the bottom wall of the trench 22.

[0143] The semiconductor device 1A includes a buried insulator 51 instead of the interlayer insulating film 16. The buried insulator 51 is buried in the trench 22 (open recess 50) so as to expose the first main surface 3, and covers the buried conductive layer 24 within the trench 22. The buried insulator 51 is buried in the trench 22 at a distance from the first main surface 3 toward the buried conductive layer 24, and exposes a surface portion of the first main surface 3 at the open end of the trench 22. The buried insulator 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the buried insulator 51 includes a silicon oxide film.

[0144] 22 , each of the plurality of trench structures 11 includes a trench 22, a trench insulating film 23, a buried conductive layer 24, and a buried insulator 51. The trench 22 has the same configuration as in the first embodiment. In this configuration, the trench insulating film 23 includes an upper insulating film 52 and a lower insulating film 53.

[0145] The upper insulating film 52 is formed as an insulating film for channel control, and covers the wall surface of the trench 22 on the opening side relative to the bottom of the body region 21. The upper insulating film 52 may include a silicon oxide film. The lower insulating film 53 covers the wall surface of the trench 22 on the bottom surface 26 side relative to the bottom of the body region 21. The lower insulating film 53 may include a silicon oxide film.

[0146] In this embodiment, the buried conductive layer 24 has a multi-electrode structure (double electrode structure) including an upper electrode 54 , a lower electrode 55 and an intermediate insulating film 56 .

[0147] The upper electrode 54 is embedded in the opening side of the trench 22 with the trench insulating film 23 in between. Specifically, the upper electrode 54 is embedded in the opening side of the trench 22 with the upper insulating film 52 in between, and faces the body region 21 with the upper insulating film 52 in between. A gate potential is applied to the upper electrode 54 as a control potential. The upper electrode 54 controls the inversion and non-inversion of a channel (current path) in the body region 21 in response to the gate potential. The upper electrode 54 may include p-type or n-type conductive polysilicon.

[0148] The lower electrode 55 is buried on the bottom surface 26 side of the trench 22 with the trench insulating film 23 interposed therebetween. Specifically, the lower electrode 55 is buried on the bottom surface 26 side of the trench 22 with the lower insulating film 53 interposed therebetween, and faces the second upper pillar 39 with the lower insulating film 53 interposed therebetween. A gate potential or a source potential may be applied to the lower electrode 55. When a gate potential is applied to the lower electrode 55, the lower electrode 55 has the same potential as the upper electrode 54. Therefore, a voltage drop between the upper electrode 54 and the lower electrode 55 is suppressed. This suppresses electric field concentration in the trench structure 11.

[0149] On the other hand, when a source potential is applied to the lower electrode 55, the lower electrode 55 can function as a field electrode. Therefore, the parasitic capacitance between the lower electrode 55 (field electrode) and the second upper pillar 39 is reduced. This suppresses a decrease in switching speed due to the parasitic capacitance. The lower electrode 55 may include p-type or n-type conductive polysilicon.

[0150] The intermediate insulating film 56 is interposed between the upper electrode 54 and the lower electrode 55, and electrically insulates the upper electrode 54 and the lower electrode 55 within the trench 22. The intermediate insulating film 56 is continuous with the upper insulating film 52 and the lower insulating film 53. The intermediate insulating film 56 has a thickness smaller than that of the lower insulating film 53. The thickness of the intermediate insulating film 56 is preferably larger than that of the upper insulating film 52. The intermediate insulating film 56 may include a silicon oxide film.

[0151] The buried insulator 51 is buried in the trench 22 (open recess 50 ) so as to expose the first main surface 3 , and covers the upper insulating film 52 and the upper electrode 54 within the open recess 50 .

[0152] 23 , the first upper pillar 34 does not have to be formed. In this case, the first lower pillar 13 faces the body region 21 in the thickness direction of the chip 2, sandwiching the drift region 8 (in this embodiment, the upper heavily doped region 32).

[0153] 24 , the first upper pillar 34 may be physically separated from the first lower pillar 13 in the thickness direction of the chip 2. In this case, a part of the drift region 8 (in this embodiment, the upper heavily doped region 32) provides an n-type intermediate region 57 that physically separates the first lower pillar 13 and the second lower pillar 14.

[0154] Semiconductor device 1A further includes a p-type connection region 58 that electrically connects body region 21 and bottom well 12. Connection region 58 extends from body region 21 to bottom well 12 along the inner surface of trench 22. As a result, first lower pillar 13 is electrically connected to body region 21 via bottom well 12 and connection region 58, and is fixed to the source potential.

[0155] <Semiconductor device 1B according to the second embodiment> (1) Detailed structure of active region 9 of semiconductor device 1B Fig. 25 is a plan view showing a main portion of the active region of semiconductor device 1B according to the second embodiment. Fig. 26 and Fig. 27 are perspective views showing a main portion of active region 9 of semiconductor device 1B. Fig. 26 shows a cross section appearing near the center in the extension direction of trench 22, and Fig. 27 shows a cross section appearing near the end of trench 22 in the extension direction.

[0156] In the semiconductor device 1B, the first lower pillars 13 are linear and extend parallel to the extension direction of the trenches 22. Accordingly, the second lower pillars 14 disposed between the first lower pillars 13 are also linear and extend parallel to the extension direction of the trenches 22. The first lower pillars 13 may extend in a normal direction to the first main surface 3.

[0157] The multiple first lower pillars 13 are arranged at a lower pillar pitch PL that is narrower than the trench pitch PT. The multiple first lower pillars 13 are arranged at a lower pillar pitch PL that is different from the trench pitch PT. In this embodiment, the lower pillar pitch PL is narrower than the trench pitch PT. The lower pillar pitch PL may be 0.4 μm or more and 3.0 μm or less. The lower pillar pitch PL may be a fractional multiple of the trench pitch PT. For example, the lower pillar pitch PL may be 1 / 3 to 1 / 2 times the trench pitch PT.

[0158] The multiple first lower pillars 13 include contact pillars 13A and non-contact pillars 13B. The contact pillars 13A are first lower pillars 13 that are connected to the bottom well 12 and extend downward integrally from the bottom well 12. The contact pillars 13A only need to be in contact with the bottom well 12, and for example, the center lines of the contact pillars 13A in the width direction (in this embodiment, the first direction X) do not have to coincide with each other. The width center line of the contact pillars 13A may be offset from the width center line of the bottom well 12.

[0159] The non-contact pillar 13B is a first lower pillar 13 that is physically separated diagonally from the bottom well 12 below the MIS structure in which the body region 21 and the source region 28 are disposed. In this configuration, two non-contact pillars 13B are adjacent to each other.

[0160] The drift region 8 includes an inter-trench region 59 sandwiched between two adjacent trenches 22 and an inter-pillar region 60 sandwiched between two non-contact pillars 13B. In this embodiment, the inter-trench region 59 and the inter-pillar region 60 are formed by the high concentration region 31. More specifically, the inter-trench region 59 is formed by the upper high concentration region 32, and the inter-pillar region 60 is formed by the lower high concentration region 33. The inter-trench region 59 and the inter-pillar region 60 are connected to each other via the non-contact pillar 13B and the bottom well 12.

[0161] 27, semiconductor device 1B further includes a contact well 62 and a connection region 63 near end 61 of trench 22.

[0162] The contact well 62 is a p-type region that extends in a line across the plurality of trenches 22 below the trenches 22 and connects the plurality of bottom wells 12 to one another. Furthermore, the contact well 62 extends in a line across the plurality of first lower pillars 13 (contact pillars 13A and non-contact pillars 13B) below the trenches 22 and is connected to the first lower pillars 13.

[0163] The impurity concentration of the contact well 62 may be equal to the impurity concentration of the bottom well 12. The impurity concentration of the contact well 62 may be higher than the impurity concentration of the body region 21. The contact well 62 has an impurity concentration of, for example, 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The p-type impurity concentration may have the following peak value:

[0164] The connection region 63 is a p-type region that electrically connects the body region 21 and the bottom well 12 (contact well 62). The connection region 63 extends from the body region 21 to the bottom well 12 (contact well 62) along the inner surface of the trench 22. As a result, the first bottom pillar 13 (contact pillar 13A and non-contact pillar 13B) is electrically connected to the body region 21 via the bottom well 12 (contact well 62) and the connection region 63, and is fixed to the source potential.

[0165] (2) Superjunction Structure SJ1 Hereinafter, with reference to FIGS. 28 to 30, a layout example of the superjunction structure SJ1 of the semiconductor device 1A will be described.

[0166] 28 to 30 are plan view layouts of the first lower pillar 13 and the second lower pillar 14, showing layout examples of the lower superjunction structure SJ1. In Fig. 28 to 30, the first lower pillar 13 is shown by dot hatching, and the second lower pillar 14 is shown by white outline.

[0167] 28 , the first lower pillars 13 are formed in stripes extending parallel to the trenches 22 and the mesas 27. The second lower pillars 14 are also formed in stripes extending parallel to the trenches 22 and the mesas 27.

[0168] 29 , the first lower pillars 13 and the second lower pillars 14 may be formed in a stripe shape in a plan view, extending at a slight angle relative to the trenches 22 and the mesas 27. In the embodiment of FIG. 29 , the first lower pillars 13 and the second lower pillars 14 extend along the trenches 22 and the mesas 27.

[0169] Referring to FIG. 30, each of the first bottom pillars 13 may be formed in a line shape that is intermittently divided in the bottom extending direction De1.

[0170] (3) Effects of Semiconductor Device 1B According to the semiconductor device 1B, the multiple first lower pillars 13 are arranged at a lower pillar pitch PL that is different from the trench pitch PT. This allows the lower pillar pitch PL to be set independently of the trench pitch PT. Therefore, even if the lower heavily doped region 33 is made more concentrated than the upper heavily doped region 32, the charge balance CB can be made closer to 1 by appropriately adjusting the lower pillar pitch PL. As a result, the charge balance CB can be stabilized. Furthermore, the lower heavily doped region 33, which has a higher concentration than the upper heavily doped region 32, can be used as part of the drift region 8 (the second lower pillar 14), thereby reducing the on-resistance of the MISFET in the active region 9.

[0171] On the other hand, in the upper region of the drift region 8 where the MIS structure is arranged, it is not necessary to narrow the trench pitch PT according to the lower pillar pitch PL. Therefore, it is possible to prevent the current path from being constricted due to the trench pitch PT being too narrow, thereby suppressing an increase in on-resistance. Furthermore, since the upper heavily doped region 32, which has a lower concentration than the lower heavily doped region 33, can be formed on the side of the bottom well 12 (electric field relaxation layer), it is possible to effectively alleviate electric field concentration near the bottom of the trench 22. As a result, the trench insulating film 23 can be appropriately protected.

[0172] (4) Modifications of Semiconductor Device 1B Modifications applied to semiconductor device 1B will be shown below with reference to Figures 31 to 35. Figures 31 to 35 are diagrams showing first to fifth modifications of semiconductor device 1B, respectively.

[0173] 31 , the semiconductor device 1B further includes a plurality of first upper pillars 34. The plurality of first upper pillars 34 are linear and extend parallel to the extension direction of the plurality of trenches 22. The plurality of first upper pillars 34 extend integrally from a non-contact pillar 13B of the plurality of first lower pillars 13 toward the first main surface 3 and are connected to the body region 21. A plurality of the plurality of first upper pillars 34 may be arranged in each mesa portion 27, or only one may be arranged.

[0174] 32 , the first upper pillar 34 may be physically separated from the first lower pillar 13 in the thickness direction of the chip 2. In this case, a part of the drift region 8 (in this embodiment, the upper heavily doped region 32) provides an n-type intermediate region 57 that physically separates the first lower pillar 13 and the second lower pillar 14.

[0175] 33 , the multiple first bottom pillars 13 may extend in a direction inclined with respect to the normal direction to the first main surface 3. For example, when the second semiconductor layer 7 has an axial channel in the thickness direction of the chip 2, the depth direction of the multiple first bottom pillars 13 may be inclined with respect to the axial channel. The axial channel is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal constituting the second semiconductor layer 7, and is surrounded by atomic rows constituting a crystal axis extending in the stacking direction (crystal growth direction). In this embodiment, the axial channel is composed of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal. That is, the axial channel extends along the c-axis and has the off direction Doff and off angle θoff described above.

[0176] Referring to Figure 34, in this embodiment, the buried conductive layer 24 is buried in the trench 22 at a distance from the first main surface 3 toward the bottom surface 26 of the trench 22, and defines an open recess 50 at the opening end of the trench 22 that is recessed toward the bottom wall of the trench 22.

[0177] The semiconductor device 1B includes a buried insulator 51 instead of the interlayer insulating film 16. The buried insulator 51 is buried in the trench 22 (open recess 50) so as to expose the first main surface 3, and covers the buried conductive layer 24 within the trench 22. The buried insulator 51 is buried in the trench 22 at a distance from the first main surface 3 toward the buried conductive layer 24, and exposes a surface portion of the first main surface 3 at the open end of the trench 22. The buried insulator 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the buried insulator 51 includes a silicon oxide film.

[0178] 35 , each of the plurality of trench structures 11 includes a trench 22, a trench insulating film 23, a buried conductive layer 24, and a buried insulator 51. The trench 22 has the same configuration as in the first embodiment. In this configuration, the trench insulating film 23 includes an upper insulating film 52 and a lower insulating film 53.

[0179] The upper insulating film 52 is formed as an insulating film for channel control, and covers the wall surface of the trench 22 on the opening side relative to the bottom of the body region 21. The upper insulating film 52 may include a silicon oxide film. The lower insulating film 53 covers the wall surface of the trench 22 on the bottom surface 26 side relative to the bottom of the body region 21. The lower insulating film 53 may include a silicon oxide film.

[0180] In this embodiment, the buried conductive layer 24 has a multi-electrode structure (double electrode structure) including an upper electrode 54 , a lower electrode 55 and an intermediate insulating film 56 .

[0181] The upper electrode 54 is embedded in the opening side of the trench 22 with the trench insulating film 23 in between. Specifically, the upper electrode 54 is embedded in the opening side of the trench 22 with the upper insulating film 52 in between, and faces the body region 21 with the upper insulating film 52 in between. A gate potential is applied to the upper electrode 54 as a control potential. The upper electrode 54 controls the inversion and non-inversion of a channel (current path) in the body region 21 in response to the gate potential. The upper electrode 54 may include p-type or n-type conductive polysilicon.

[0182] The lower electrode 55 is embedded in the bottom surface 26 of the trench 22 with the trench insulating film 23 interposed therebetween. A gate potential or a source potential may be applied to the lower electrode 55. The lower electrode 55 may include p-type or n-type conductive polysilicon.

[0183] The intermediate insulating film 56 is interposed between the upper electrode 54 and the lower electrode 55, and electrically insulates the upper electrode 54 and the lower electrode 55 within the trench 22. The intermediate insulating film 56 is continuous with the upper insulating film 52 and the lower insulating film 53. The intermediate insulating film 56 has a thickness smaller than that of the lower insulating film 53. The thickness of the intermediate insulating film 56 is preferably larger than that of the upper insulating film 52. The intermediate insulating film 56 may include a silicon oxide film.

[0184] The buried insulator 51 is buried in the trench 22 (open recess 50 ) so as to expose the first main surface 3 , and covers the upper insulating film 52 and the upper electrode 54 within the open recess 50 .

[0185] Although embodiments of the present disclosure have been described, the present disclosure may be embodied in other forms.

[0186] For example, in each of the above-described embodiments, the superjunction structure arranged in the drift region 8 is a two-stage structure consisting of a lower superjunction structure SJ1 and an upper superjunction structure SJ2. However, each of the lower superjunction structure SJ1 and the upper superjunction structure SJ2 may be a multi-stage structure.

[0187] 6 may be a three-tiered structure including a first SJ structure, a second SJ structure, and a third SJ structure. In this case, the first lower pillars 13 of each SJ structure may be formed with independent impurity concentrations, depths, planar patterns, etc. For example, with respect to the planar pattern, the lower extension direction De1 of the first lower pillars 13 of the first SJ structure may be perpendicular to the extension direction of the trenches 22, the first lower pillars 13 of the second SJ structure may intersect with the trenches 22 at a first extension angle θa1 = 30°, and the first lower pillars 13 of the third SJ structure may intersect with the trenches 22 at a first extension angle θa1 = 60°.

[0188] For example, in each of the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. The first semiconductor layer 6 may include a silicon single crystal. The second semiconductor layer 7 may include a silicon single crystal.

[0189] In each of the above-described embodiments, a structure may be adopted in which the conductivity type of an “n-type” semiconductor region is inverted to “p-type” and the conductivity type of a “p-type” semiconductor region is inverted to “n-type.” A specific configuration in this case can be obtained by replacing “n-type” with “p-type” and “p-type” with “n-type” in the above description and accompanying drawings.

[0190] In each of the above-described embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0191] Below, examples of features extracted from this specification and the drawings are shown. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments. The "semiconductor device" in the following items may be replaced with "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "semiconductor rectifier device," "MISFET device," "IGBT device," "diode device," etc., as necessary.

[0192] [Supplementary Note 1-1] A chip (2) having a first main surface (3) and a second main surface (4); a first impurity region (8) of a first conductivity type in a surface layer portion of the first main surface (3); a plurality of trenches (22) in the first main surface (3) and arranged at a first pitch (PT); a second impurity region (21) of a second conductivity type and a third impurity region (28) of the first conductivity type in a surface layer portion of the first impurity region (8) and arranged in this order from the second main surface (4) side along a side surface of the trench (22); a buried conductive layer (24) buried in the trench (22) and facing the second impurity region (21) via a trench insulating film (23); and a plurality of bottom wells (12) of a second conductivity type formed in the bottoms of the plurality of trenches (22), respectively. a plurality of first lower pillars (13) of a second conductivity type arranged at a second pitch (PL) different from the first pitch (PT) in the first impurity region (8) below the plurality of bottom wells (12).

[0193] [Appendix 1-2] The semiconductor device (1A, 1B) according to Appendix 1-1, wherein the first impurity region (8) includes a second lower pillar (14) of a first conductivity type sandwiched between the plurality of first lower pillars (13), and a second upper pillar (39) of the first conductivity type sandwiched between the plurality of bottom wells (12) above the second lower pillar (14), and a second lower impurity concentration of the second lower pillar (14) is higher than a second upper impurity concentration of the second upper pillar (39).

[0194] [Appendix 1-3] The semiconductor device (1A, 1B) according to Appendix 1-2, wherein the first impurity region (8) further includes a base impurity region (30) located further below the plurality of first lower pillars (13) and having a base impurity concentration lower than the second upper impurity concentration.

[0195] [Appendix 1-4] The semiconductor device (1A, 1B) according to any one of Appendices 1-1 to 1-3, wherein a first lower impurity concentration of the first lower pillar (13) is lower than a bottom impurity concentration of the bottom well (12).

[0196] [Appendix 1-5] The semiconductor device (1A, 1B) according to Appendix 1-2 or Appendix 1-3, wherein when a first lower impurity concentration N1 of the first lower pillar (13), a width W1 of the first lower pillar (13), a second lower impurity concentration N2, and a width W2 of the second lower pillar (14), a charge balance CB between the first lower pillar (13) and the second lower pillar (14) is expressed by the following formula (1):

[0197] CB=(N2×W2) / (N1×W1)...(1)

[0198] [Appendix 1-6] The semiconductor device (1A) according to any one of Appendices 1-1 to 1-5, wherein the plurality of trenches (22) extend in a stripe pattern, and the plurality of first lower pillars (13) extend in a first intersecting direction with respect to the extension direction of the plurality of trenches (22) and are arranged at the second pitch (PL) narrower than the first pitch (PT).

[0199] [Appendix 1-7] The semiconductor device (1A) according to Appendix 1-6, further including a first upper pillar (34) of a second conductivity type, extending in a second intersecting direction relative to the extension direction of the plurality of trenches (22) in the first impurity region (8) above the first lower pillar (13) and connected to the second impurity region (21).

[0200] [Supplementary Note 1-8] The semiconductor device (1A) according to Supplementary Note 1-7, further comprising a plurality of mesa portions (27) partitioned by the plurality of trenches (22), wherein the plurality of first upper pillars (34) are arranged in a line in the second intersecting direction, and each of the first upper pillars (34) is disposed apart from a side surface (25) of the trench (22) in each of the mesa portions (27).

[0201] [Appendix 1-9] The semiconductor device (1A, 1B) according to Appendix 1-7 or Appendix 1-8, wherein the first upper pillar (34) extends integrally from the first lower pillar (13) toward the first main surface (3).

[0202] [Appendix 1-10] The semiconductor device (1A) according to Appendix 1-6, wherein the first lower pillar (13) extends in a line crossing the plurality of trenches (22) and is connected to the bottom well (12) below each of the trenches (22), and further includes a second conductivity type connection region (58) that extends along an inner surface of the trench (22) from the second impurity region (21) to the bottom well (12) and electrically connects the second impurity region (21) and the bottom well (12).

[0203] [Appendix 1-11] The semiconductor device (1A) according to Appendix 1-10, further including a first upper pillar (34) of a second conductivity type, in the first impurity region (8) above the second lower pillar (14), extending in a second intersecting direction relative to the extension direction of the plurality of trenches (22), connected to the second impurity region (21), and physically separated from the first lower pillar (13).

[0204] [Appendix 1-12] The semiconductor device (1A) according to Appendix 1-10, wherein the first lower pillar (13) faces the second impurity region (21) across the first impurity region (8) in the thickness direction of the chip (2).

[0205] [Supplementary Note 1-13] The semiconductor device (1A) according to any one of Supplementary Note 1-6 to Supplementary Note 1-12, wherein the first intersecting direction includes a direction perpendicular to the extension direction of the plurality of trenches (22).

[0206] [Supplementary Note 1-14] The semiconductor device (1A) according to any one of Supplementary Note 1-6 to Supplementary Note 1-13, wherein the first intersecting direction includes an inclined direction with respect to the extension direction of the plurality of trenches (22).

[0207] [Appendix 1-15] The semiconductor device (1B) according to any one of Appendices 1-1 to 1-5, wherein the plurality of trenches (22) extend in a stripe pattern, and the plurality of first lower pillars (13) extend parallel to the extension direction of the plurality of trenches (22) and are arranged at the second pitch (PL) narrower than the first pitch (PT).

[0208] [Appendix 1-16] The semiconductor device (1B) according to Appendix 1-15, wherein the plurality of first lower pillars (13) include at least two non-contact pillars (13B) that are physically separated from the bottom well (12) in a diagonal direction and adjacent to each other.

[0209] [Appendix 1-17] The semiconductor device (1B) according to Appendix 1-16, wherein the first impurity region (8) includes an inter-trench region (59) sandwiched between two adjacent trenches (22), and an inter-pillar region (60) sandwiched between the two non-contact pillars (13B) and connected to the inter-trench region (59) via a gap between the non-contact pillars (13B) and the bottom well (12).

[0210] [Supplementary Note 1-18] The semiconductor device (1B) according to Supplementary Note 1-16 or Supplementary Note 1-17, wherein the plurality of first lower pillars (13) further include a contact pillar (13A) extending integrally from the bottom well (12).

[0211] [Appendix 1-19] The semiconductor device (1B) according to any one of Appendices 1-15 to 1-18, further including a first upper pillar (34) of a second conductivity type, extending parallel to the extension direction of the plurality of trenches (22) and connected to the second impurity region (21), in the first impurity region (8) above the first lower pillar (13).

[0212] [Appendix 1-20] The semiconductor device (1A, 1B) according to any one of Appendices 1-1 to 1-19, wherein the chip (2) includes a SiC chip (2).

[0213] [Supplementary Note 1-21] The semiconductor device (1A, 1B) according to any one of Supplementary Note 1-1 to Supplementary Note 1-20, wherein the second pitch (PL) is a fractional multiple of the first pitch (PT).

[0214] [Appendix 1-22] The semiconductor device (1A, 1B) according to appendix 1-21, wherein the second pitch (PL) is 1 / 3 to 1 / 2 times the first pitch (PT).

[0215] 1A: Semiconductor device 1B: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First semiconductor layer 7: Second semiconductor layer 8: Drift region 9: Active region 10: Peripheral region 11: Trench structure 12: Bottom well 12: Bottom well 13: First lower pillar 13A: Contact pillar 13B: Non-contact pillar 14: Second lower pillar 15: Field region 16: Interlayer insulating film 17: Gate pad 18: Gate wiring 18A: First gate wiring 18B: Second gate wiring 19: Source pad 20: Drain pad 21: Body region 22: Trench 23 : Trench insulating film 24 : Buried conductive layer 25 : Side surface 26 : Bottom surface 27 : Mesa portion 28 : Source region 29 : Body contact region 30 : Base region 31 : High concentration region 32 : Upper high concentration region 33 : Lower high concentration region 34 : First upper pillar 35 : Convex portion 36 : Upper tapered portion 37 : Lower tapered portion 38 : Isolation region 39 : Second upper pillar 40 : Concave portion 41 : Contact opening 42 : First principal surface electrode 43 : Barrier layer 44 : Main body layer 45 : Resin layer 46 : End portion 47 : Array region 48 : Overlapping region 49 : Non-overlapping region 50 : Opening recess 51 : Buried insulator 52 : Upper insulating film 53 : Lower insulating film 54 : Upper electrode 55 : Lower electrode 56 : Intermediate insulating film 57 : Intermediate region 58 : Connection region 59 : Inter-trench region 60 : Inter-pillar region 61 : End 62 : Contact well 63 : Connection region

Claims

a plurality of trenches in the first main surface arranged at a first pitch; a second impurity region of a second conductivity type and a third impurity region of the first conductivity type in a surface layer of the first impurity region and arranged in this order from the second main surface along side surfaces of the trenches; a buried conductive layer buried in the trenches and facing the second impurity region via a trench insulating film; a plurality of bottom wells of a second conductivity type formed at the bottoms of the plurality of trenches; and a plurality of first lower pillars of a second conductivity type arranged at a second pitch different from the first pitch in the first impurity region below the plurality of bottom wells.

2. The semiconductor device according to claim 1, wherein the first impurity region includes a second lower pillar of a first conductivity type sandwiched between the plurality of first lower pillars, and a second upper pillar of a first conductivity type sandwiched between the plurality of bottom wells above the second lower pillar, and a second lower impurity concentration of the second lower pillar is higher than a second upper impurity concentration of the second upper pillar.

3. The semiconductor device according to claim 2, wherein the first impurity region further includes a base impurity region located further below the plurality of first lower pillars and having a base impurity concentration lower than the second upper impurity concentration.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first lower impurity concentration of the first lower pillar is lower than the bottom impurity concentration of the bottom well.

5. The semiconductor device according to claim 2 or 3, wherein, when the first lower impurity concentration of the first lower pillar is N1, the width of the first lower pillar is W1, the second lower impurity concentration is N2, and the width of the second lower pillar is W2, a charge balance CB between the first lower pillar and the second lower pillar is expressed by the following formula (1): CB=(N2×W2) / (N1×W1) (1) is within a range of 0.9 to 1.1 in a section from the top to the bottom of the first lower pillar in the thickness direction of the chip.

6. A semiconductor device according to any one of claims 1 to 5, wherein the plurality of trenches extend in a stripe pattern, and the plurality of first lower pillars extend in a first intersecting direction relative to the extension direction of the plurality of trenches and are arranged at the second pitch narrower than the first pitch.

7. The semiconductor device according to claim 6, further comprising a first upper pillar of a second conductivity type, extending in a second intersecting direction relative to the extension direction of the plurality of trenches, in the first impurity region above the first lower pillar, and connected to the second impurity region.

8. The semiconductor device according to claim 7, comprising a plurality of mesa portions partitioned by the plurality of trenches, wherein the plurality of first upper pillars are arranged in a line in the second intersecting direction, and each of the first upper pillars is disposed away from a side surface of the trench in each of the mesa portions.

9. The semiconductor device according to claim 7 or 8, wherein the first upper pillar extends integrally from the first lower pillar toward the first main surface.

10. The semiconductor device described in claim 6, wherein the first lower pillar extends in a line across the plurality of trenches and is connected to the bottom well below each of the trenches, and further includes a second conductivity type connection region that extends along the inner surface of the trench from the second impurity region to the bottom well and electrically connects the second impurity region and the bottom well.

11. The semiconductor device according to claim 10, further comprising a first upper pillar of a second conductivity type, extending in a second intersecting direction relative to the extension direction of the plurality of trenches in the first impurity region above the second lower pillar, connected to the second impurity region, and physically separated from the first lower pillar.

12. The semiconductor device according to claim 10, wherein the first lower pillar faces the second impurity region in the thickness direction of the chip, with the first impurity region interposed therebetween.

13. The semiconductor device according to any one of claims 6 to 12, wherein the first intersecting direction includes a direction perpendicular to the extending direction of the plurality of trenches.

14. The semiconductor device according to any one of claims 6 to 13, wherein the first intersecting direction includes an inclined direction with respect to the extending direction of the plurality of trenches.

15. A semiconductor device according to any one of claims 1 to 5, wherein the plurality of trenches extend in a stripe pattern, and the plurality of first lower pillars extend parallel to the extension direction of the plurality of trenches and are arranged at the second pitch narrower than the first pitch.

16. The semiconductor device of claim 15, wherein the first plurality of lower pillars comprises at least two non-contacting pillars that are physically separated from the bottom well in a diagonal direction and adjacent to each other.

17. The semiconductor device according to claim 16, wherein the first impurity region includes an inter-trench region sandwiched between two adjacent trenches, and an inter-pillar region sandwiched between the two non-contact pillars and connected to the inter-trench region via a gap between the non-contact pillar and the bottom well.

18. The semiconductor device of claim 16 or 17, wherein the first plurality of lower pillars further includes a contact pillar extending integrally from the bottom well.

19. The semiconductor device according to any one of claims 15 to 18, further comprising a first upper pillar of a second conductivity type, extending parallel to the extension direction of the plurality of trenches and connected to the second impurity region, in the first impurity region above the first lower pillar.

20. The semiconductor device according to any one of claims 1 to 19, wherein the chip includes a SiC chip.

Images