Semiconductor device and semiconductor module

Abstract

Provided is a semiconductor device comprising a first active unit that has a plurality of transistor parts and a plurality of diode parts alternately arranged in an arrangement direction. In the provided semiconductor device: the first active unit has a first end and a second end on the side opposite from the first end in the arrangement direction; the plurality of diode parts include a first diode part provided closest to the first end, and a second diode part provided closest to the second end; the plurality of transistor parts include a first transistor part provided closest to the first end, and a second transistor part provided closest to the second end; and the first diode part is provided closer to the first end than the first transistor part is.

Description

Semiconductor device and semiconductor module

[0001] The present invention relates to a semiconductor device and a semiconductor module.

[0002] Conventionally, in a semiconductor device in which a transistor portion such as an insulated gate bipolar transistor (IGBT) and a diode portion are formed on the same substrate, a technique has been known in which a particle beam such as helium ions is irradiated at a predetermined depth position in the semiconductor substrate to provide a lifetime control region including a lifetime killer (for example, see Patent Document 1). [Prior Art Documents] [Patent Documents] [Patent Document 1] JP 2017-135339 A General disclosure

[0003] In such a semiconductor device, a lifetime control region may also be provided in the transition region adjacent to the diode portion of the transistor portion.

[0004] In a first aspect of the present invention, there is provided a semiconductor device including a first active portion having a plurality of transistor portions and a plurality of diode portions alternately arranged in an arrangement direction, the semiconductor device including: a drift region of a first conductivity type provided in a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction in a front surface of the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided in the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a contact region of the second conductivity type provided above the drift region and having a doping concentration higher than that of the base region; and a contact region of the second conductivity type provided on the front surface of the semiconductor substrate closer to the center of the semiconductor substrate in the depth direction. and a lifetime control region formed by forming a first active portion on a first end portion and a second end portion opposite to the first end portion in the arrangement direction, the plurality of diode portions having a first diode portion provided closest to the first end portion and a second diode portion provided closest to the second end portion, the plurality of transistor portions having a first transistor portion provided closest to the first end portion and a second transistor portion provided closest to the second end portion, and the first diode portion being provided closer to the first end portion than the first transistor portion.

[0005] The second transistor section may be provided closer to the second end than the second diode section.

[0006] The second diode section may be provided closer to the second end than the second transistor section.

[0007] On the front surface of the semiconductor substrate, the areas of the first diode section and the second diode section may be different from the areas of the other diode sections.

[0008] On the front surface of the semiconductor substrate, the areas of the first diode section and the second diode section may be smaller than the areas of the other diode sections.

[0009] On the front surface of the semiconductor substrate, the areas of the first diode section and the second diode section may be larger than the areas of the other diode sections.

[0010] The semiconductor device includes a second active section separated from the first active section in a direction perpendicular to the arrangement direction and having the plurality of transistor sections and the plurality of diode sections arranged alternately in the arrangement direction, the second active section having a third end and a fourth end opposite the third end in the arrangement direction, the third end being adjacent to the first end in an extension direction of the plurality of transistor sections and the plurality of diode sections, and the fourth end being adjacent to the second end in the extension direction, the plurality of diode sections in the second active section having a third diode section provided closest to the third end and a fourth diode section provided closest to the fourth end, the plurality of transistor sections in the second active section having a third transistor section provided closest to the third end and a fourth transistor section provided closest to the fourth end, and an arrangement of the plurality of transistor sections and the plurality of diode sections in the second active section may be different from an arrangement of the plurality of transistor sections and the plurality of diode sections in the first active section.

[0011] The fourth diode section may be provided closer to the fourth end than the fourth transistor section.

[0012] Each transistor section may have a transition region provided on the side of the adjacent diode section, and the number of the transition regions in the first active section may be equal to the number of the transition regions in the second active section.

[0013] The first active section may be provided in a plurality of pieces, and in the first active section, the second diode section may be provided closer to the second end than the second transistor section, and in the second active section, the third transistor section may be provided closer to the third end than the third diode section, and the fourth transistor section may be provided closer to the fourth end than the fourth diode section.

[0014] Each transistor section may have a transition region provided on the side of the adjacent diode section, and the number of the transition regions in the first active section may be equal to the number of the transition regions in the second active section.

[0015] The semiconductor device may include a well region of a second conductivity type provided on the front surface of the semiconductor substrate in an outer peripheral region surrounding the first active portion, the well region having a doping concentration higher than that of the base region, and a cathode region of a first conductivity type provided in each diode portion on the back surface of the semiconductor substrate, the cathode region having a doping concentration higher than that of the drift region, and an outer end of the cathode region of the first diode portion may be located more inward than an inner end of the well region in the arrangement direction.

[0016] The semiconductor device may include an interlayer insulating film provided above a front surface of the semiconductor substrate and having a plurality of contact holes; an emitter electrode provided above the interlayer insulating film; a well region of a second conductivity type provided on the front surface of the semiconductor substrate in an outer circumferential region surrounding the first active portion, the well region having a doping concentration higher than that of the base region; and cathode regions of the first conductivity type provided in each diode portion on a rear surface of the semiconductor substrate, the cathode regions having a doping concentration higher than that of the drift region, the emitter electrode and the front surface of the semiconductor substrate in the first active portion and the well region may be connected via the plurality of contact holes, and the semiconductor device may further include a resistor portion provided from an outer end of the well region to an outermost contact hole of the plurality of contact holes.

[0017] The resistor portion may include at least one of the plurality of trench portions.

[0018] In a peripheral region surrounding the first active portion, a well region of a second conductivity type is provided on the front surface of the semiconductor substrate, the well region having a doping concentration higher than that of the base region, and a cathode region of a first conductivity type is provided in each diode portion on the back surface of the semiconductor substrate, the cathode region having a doping concentration higher than that of the drift region, and the lifetime control region may be provided extending from the first diode portion to at least a portion of the peripheral region in the arrangement direction.

[0019] A second aspect of the present invention provides a semiconductor module including the semiconductor device according to the first aspect and a cooling section that cools the semiconductor device from the first end side.

[0020] In a third aspect of the present invention, there is provided a semiconductor module comprising a semiconductor device according to the first aspect and another semiconductor device, wherein the semiconductor device is arranged so that the first end side of the semiconductor device does not face the other semiconductor device.

[0021] A fourth aspect of the present invention provides a semiconductor module including the semiconductor device according to the first aspect and a cooling section that cools the semiconductor device from the second end side.

[0022] In a fifth aspect of the present invention, there is provided a semiconductor module comprising a semiconductor device according to the first aspect and another semiconductor device, wherein the semiconductor device is arranged so that the second end side of the semiconductor device does not face the other semiconductor device.

[0023] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions.

[0024] 1 is a diagram showing an example of a top view of the semiconductor device 100. FIG. 1 is a top view showing an enlarged example of an area A in FIG. 1. FIG. 2 is a diagram showing a cross section a-a in FIG. 2. FIG. 3 is a diagram showing a different example of the cross section a-a in FIG. 2. FIG. 4 is a diagram showing a different example of the cross section a-a in FIG. 2. FIG. 5 is a diagram showing a different example of the cross section a-a in FIG. 2. FIG. 6 is a diagram showing a different example of the cross section a-a in FIG. 1. FIG. 7 is a diagram showing a different example of the cross section a-a in FIG. 2. FIG. 8 is a diagram showing a different example of the cross section a-a in FIG. 2. FIG. 9 is a diagram showing a different example of the cross section a-a in FIG. 9. FIG. 10 is a diagram showing a different example of the cross section a-a in FIG. 1. 10A . FIG. 10B is a top view showing an example of an arrangement of the transistor sections 70 and the diode sections 80 in the first active section 160 and the second active section 161. FIG. 10C is a top view showing another example of an arrangement of the transistor sections 70 and the diode sections 80 in the first active section 160 and the second active section 161. FIG. 10D is a top view showing an enlarged example of region B in FIG. 1. FIG. 10E is a view showing a cross section taken along the line c-c in FIG. 8. FIG. 10F is a view showing an example of a top view of a semiconductor module 1000 according to an embodiment. FIG. 10G is a view showing an example of a cross section taken along the line f-f in FIG. 10A. FIG. 10H is a view showing an example of a bottom view of the semiconductor module 1000. FIG. 10C is a view showing an example of a cross section taken along the line g-g in FIG. 10C. FIG. 10F is a schematic view showing an arrangement of the semiconductor devices 100 in the semiconductor module 1000. FIG. 10G is a schematic view showing another example of an arrangement of the semiconductor devices 100 in the semiconductor module 1000. FIG. 10H is a schematic view showing another example of an arrangement of the semiconductor devices 100 in the semiconductor module 1000.

[0025] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0026] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the front surface, and the other surface is referred to as the back surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor device is mounted.

[0027] In this specification, technical matters may be explained using orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is described without specifying positive or negative, it means a direction parallel to the +Z-axis and -Z-axis.

[0028] In this specification, orthogonal axes parallel to the front and back surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, an axis perpendicular to the front and back surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. Furthermore, in this specification, the direction parallel to the front and back surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0029] The region from the center of the semiconductor substrate in the depth direction to the front surface of the semiconductor substrate may be referred to as the front surface side. Similarly, the region from the center of the semiconductor substrate in the depth direction to the back surface of the semiconductor substrate may be referred to as the back surface side.

[0030] In this specification, when we say "same" or "equal," it may also include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0031] In this specification, the conductivity type of a doped region doped with an impurity is described as P-type or N-type. In this specification, the impurity may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as a dopant. In this specification, doping means introducing a donor or an acceptor into a semiconductor substrate to form a semiconductor exhibiting an N-type conductivity or a P-type conductivity.

[0032] Fig. 1 is a diagram showing an example of a top view of a semiconductor device 100. Fig. 1 shows the positions of each component as projected onto the front surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0033] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 has edges 102 in a top view. In this specification, the term "top view" simply refers to a view from the front surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of edges 102 that face each other in a top view. In FIG. 1 , the X-axis and the Y-axis are parallel to one of the edges 102. The Z-axis is perpendicular to the front surface of the semiconductor substrate 10.

[0034] The semiconductor substrate 10 has a first active portion 160 and a peripheral region 190. The first active portion 160 is a region through which a main current flows in the depth direction between the front and back surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the first active portion 160, but is omitted in FIG. 1 .

[0035] The first active section 160 has a first end X1 and a second end X2 opposite to the first end X1 in a predetermined element arrangement direction (the X-axis direction in this specification) on the front surface of the semiconductor substrate 10. Here, the first end X1 is on the positive side in the X-axis direction, and the second end X2 is on the negative side in the X-axis direction, but this may be reversed. The first active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD). In the example of FIG. 1 , a plurality of transistor sections 70 and a plurality of diode sections 80 are arranged in alternating stripes along the X-axis direction.

[0036] In FIG. 1 , the region where the transistor section 70 is disposed is marked with the symbol "I," and the region where the diode section 80 is disposed is marked with the symbol "F." In this specification, the direction perpendicular to the element arrangement direction in a top view may be referred to as the element extension direction (here, the Y-axis direction). The transistor section 70 and the diode section 80 may each have their longitudinal axis in a predetermined trench extension direction. In other words, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. Of the multiple diode sections 80, the diode section 80 provided closest to the first end X1 is referred to as the first diode section 80-1, and the diode section 80 provided closest to the second end X2 is referred to as the second diode section 80-2. Of the multiple transistor sections 70, the transistor section 70 provided closest to the first end X1 is referred to as the first transistor section 70-1, and the transistor section 70 provided closest to the second end X2 is referred to as the second transistor section 70-2.

[0037] The width of the transistor section 70 in the X-axis direction is larger than the width of the diode section 80 in the X-axis direction. Furthermore, the width of the transistor section 70 in the X-axis direction may be the same as the width of the diode section 80 in the X-axis direction. The element extension direction of the transistor section 70 and the diode section 80 may be the same as the trench extension direction of each trench section. The element arrangement direction of the transistor section 70 and the diode section 80 may be the same as the trench arrangement direction of each trench section, which will be described later.

[0038] The diode section 80 has an N+ type cathode region in a region that contacts the back surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is a region that overlaps with the cathode region in a top view. A P+ type collector region may be provided in a region other than the cathode region on the back surface of the semiconductor substrate 10. In this specification, an extension region of the diode section 80 that extends in the Y-axis direction to a gate runner, which will be described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region.

[0039] The transistor section 70 has a P+ type collector region in a region in contact with the back surface of the semiconductor substrate 10. In addition, the transistor section 70 has a gate structure, which has an N+ type emitter region, a P- type base region, a gate conductive portion, and a gate insulating film, periodically arranged on the front surface side of the semiconductor substrate 10.

[0040] The semiconductor device 100 includes a peripheral region 190 disposed between the first active unit 160 and the edge 102 of the semiconductor substrate 10 in a top view. In the present example, the peripheral region 190 is provided with a well region 11 surrounding the first active unit 160 in a top view. The region surrounded by the well region 11 in a top view may be the first active unit 160, and the region from the well region 11 toward the edge 102 may be the peripheral region 190.

[0041] The peripheral gate runner 47 may be disposed above the semiconductor substrate 10. In this example, the peripheral gate runner 47 may be disposed above the well region 11. The peripheral gate runner 47 is electrically connected to a gate conductive portion provided inside the gate trench portion via a gate insulating film.

[0042] In this example, the peripheral region 190 surrounds the first active portion 160 in a top view. The peripheral region 190 includes an edge termination region. The edge termination region relieves electric field concentration on the front surface side of the semiconductor substrate 10.

[0043] In this example, the peripheral region 190 has one or more auxiliary pads provided above the semiconductor substrate 10. As an example, the semiconductor device 100 has auxiliary pads such as an anode pad, a cathode pad, and a current detection pad. Each auxiliary pad may be provided above the well region 11. Each auxiliary pad may be connected to an external circuit via wiring such as a wire. Note that while FIG. 1 depicts the outline of each auxiliary pad and indicates the boundary with the protective film surrounding it, other exposed portions of the protective film are omitted, and the protective film will also be omitted from the following explanatory drawings.

[0044] In this example, the peripheral region 190 may include a current sensing unit 210. The current sensing unit 210 detects the current flowing through the transistor unit 70. The current sensing unit 210 may be provided inside the well region 11. The peripheral region 190 may further include a temperature sensing unit which is a PN junction diode formed of polysilicon or the like. The temperature sensing unit may be provided above the well region 11.

[0045] In this example, the peripheral region 190 may have a guard ring 92 as an edge termination region. The guard ring 92 is a P-type region that contacts the front surface of the semiconductor substrate 10. Note that although the edge termination region in this example has multiple guard rings 92, only one guard ring 92 is shown in FIG. 1 for brevity. By providing multiple guard rings 92, the depletion layer on the upper surface side of the first active section 160 can be extended outward, thereby improving the breakdown voltage of the semiconductor device 100. The edge termination region may further include at least one of a field plate and a resurf annularly disposed around the first active section 160.

[0046] In this specification, "inside" refers to the center side of the semiconductor substrate 10 when viewed from above, and "outside" refers to the side of the edge 102 of the semiconductor substrate 10 when viewed from above.

[0047] Fig. 2 is an enlarged top view of an example of region A in Fig. 1. The semiconductor device 100 includes a semiconductor substrate having a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a free wheel diode (FWD).

[0048] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, which are provided on the front surface of a semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0049] The semiconductor device 100 of this example also includes a gate metal layer 50 and an emitter electrode 52 provided above the front surface of the semiconductor substrate 10. The gate metal layer 50 and the emitter electrode 52 are provided separately from each other. The gate metal layer 50 and the emitter electrode 52 are electrically insulated from each other. An interlayer insulating film is provided between the gate metal layer 50 and the emitter electrode 52 and the front surface of the semiconductor substrate 10, but is not shown in FIG. 2. In this example, contact holes 54, 55, and 56 are provided through the interlayer insulating film. In FIG. 2, each contact hole is hatched with diagonal lines.

[0050] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 is electrically connected to the emitter region 12, the base region 14, and the contact region 15 on the front surface of the semiconductor substrate 10 via contact holes 54.

[0051] The emitter electrode 52 is connected to the dummy conductive portion in the dummy trench portion 30 by a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is provided on the front surface of the semiconductor substrate 10 via an insulating film such as an interlayer insulating film and a dummy insulating film of the dummy trench portion 30. The connection portion 25 may not be provided, and the dummy conductive portion and the emitter electrode 52 may be connected by a contact hole 56 provided above the dummy conductive portion.

[0052] The gate metal layer 50 is electrically connected to the semiconductor gate runner 48 through a contact hole 55. The gate metal layer 50 and the semiconductor gate runner 48 together form the peripheral gate runner 47. In some or all regions, the gate metal layer 50 and the semiconductor gate runner 48 may not both be provided, or only one of them may be provided.

[0053] The semiconductor gate runner 48 and the emitter electrode 52 are electrically isolated by an insulator such as an interlayer insulating film and an oxide film. The semiconductor gate runner 48 is provided on the front surface of the semiconductor substrate 10 via an insulating film such as the interlayer insulating film and the gate insulating film of the gate trench portion 40. In this example, the semiconductor gate runner 48 is provided from below the contact hole 55 to the end of the gate trench portion 40. At the end of the gate trench portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate 10 and is connected to the semiconductor gate runner 48.

[0054] The semiconductor gate runner 48 may be formed of impurity-doped polysilicon or the like. The semiconductor gate runner 48 connects to the gate conductive portion in the gate trench portion 40 on the front surface of the semiconductor substrate 10. The semiconductor gate runner 48 is not electrically connected to the dummy conductive portion in the dummy trench portion 30 or the emitter electrode 52. The semiconductor gate runner 48 may not be provided, and the gate conductive portion and the gate metal layer 50 may be connected by a contact hole 55 provided above the gate conductive portion. On the other hand, the gate metal layer 50 may not be provided.

[0055] The gate metal layer 50 and the emitter electrode 52 are formed of a conductive material containing metal. For example, the gate metal layer 50 and the emitter electrode 52 are formed of aluminum or an aluminum-silicon alloy. The gate metal layer 50 and the emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like below the region formed of aluminum or the like.

[0056] The emitter electrode 52 may have a plug formed of tungsten or the like in the contact hole 54. The plug may be formed by forming a barrier metal on the side of the contact hole 54 that contacts the semiconductor substrate 10, and burying tungsten so as to contact the barrier metal.

[0057] The plug may be in contact with the contact region 15 or the base region 14 below the contact hole 54. Alternatively, a P++-type plug region having a higher doping concentration than the contact region 15 may be provided below the contact hole 54 in which the plug is provided. The plug region can improve the contact resistance between the barrier metal and the contact region 15.

[0058] The plug region improves the contact resistance, thereby improving the latch-up resistance in the operation of the transistor section 70. On the other hand, in the operation of the diode section 80, the conduction loss can be suppressed.

[0059] The well region 11 extends from the peripheral gate runner 47 and is annular in top view. The well region 11 also extends inward from the peripheral gate runner 47 toward the first active section 160 by a predetermined width in the Y-axis direction and is annular in top view. In this example, the well region 11 is provided in a range farther toward the peripheral gate runner 47 than the Y-axis end of the contact hole 54. The well region 11 is a second conductivity type region having a higher doping concentration than the base region 14. The doping concentration of the well region 11 may be the same as or lower than the doping concentration of the contact region 15. The peripheral gate runner 47 is electrically insulated from the well region 11.

[0060] In this example, the base region 14 is P- type, and the well region 11 is P+ type. The well region 11 is formed from the front surface of the semiconductor substrate to a position deeper than the bottom end of the base region 14. The base region 14 is provided in contact with the well region 11 in the transistor section 70 and the diode section 80. The well region 11 is electrically connected to the emitter electrode 52.

[0061] Each of the transistor section 70 and the diode section 80 has a plurality of trench sections arranged in the trench arrangement direction (X-axis direction). In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the X-axis direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the X-axis direction.

[0062] The gate trench portion 40 in this example may have two extension portions 39 (portions of the trench that are linear along the Y-axis direction) extending along the trench extension direction (Y-axis direction) perpendicular to the trench arrangement direction, and a connection portion 41 connecting the two extension portions 39.

[0063] At least a portion of the connection portion 41 may be curved in top view. The connection portion 41 connects the ends of the two extension portions 39 in the Y-axis direction to the outer periphery gate runner 47, thereby functioning as a gate electrode to the gate trench portion 40. On the other hand, by making the connection portion 41 curved, electric field concentration at the ends can be alleviated more effectively than if the connection portion 41 were completed at the extension portion 39.

[0064] In the transistor section 70, the dummy trench section 30 is provided between the extension portions 39 of the gate trench section 40. In the example of Fig. 2, one dummy trench section 30 is provided between the extension portions 39, but two dummy trench sections 30 may be provided, or more than two dummy trench sections 30 may be provided.

[0065] Furthermore, the dummy trench portion 30 may not be provided between the extension portions 39, and the gate trench portion 40 may be provided instead. With such a structure, the electron current from the emitter region 12 can be increased, thereby reducing the on-voltage.

[0066] The dummy trench portion 30 may have a linear shape extending in the trench extension direction, and may have an extension portion 29 and a connection portion 31, similar to the gate trench portion 40. In the semiconductor device 100 shown in FIG. 2 , only dummy trench portions 30 having connection portions 31 are arranged, but in other examples, the semiconductor device 100 may include linear dummy trench portions 30 without connection portions 31.

[0067] The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are provided in the well region 11 when viewed from above. In other words, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction (positive side in the Z-axis direction) is covered by the well region 11. This makes it possible to alleviate electric field concentration at the bottom of each trench portion.

[0068] A mesa portion 60 is provided between each trench portion in the trench arrangement direction. The mesa portion 60 refers to a region sandwiched between the trench portions inside the semiconductor substrate 10. As an example, the depth position of the mesa portion 60 is from the front surface of the semiconductor substrate 10 to the bottom end of the trench portion.

[0069] The mesa portion 60 in this example is sandwiched between adjacent trench portions in the X-axis direction, and is provided on the front surface of the semiconductor substrate 10 so as to extend in the Y-axis direction along the trenches.

[0070] Each mesa portion 60 has a base region 14. In each mesa portion 60, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in a region sandwiched between the base regions 14 in a top view. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided between the base region 14 and the front surface of the semiconductor substrate 10 in the depth direction.

[0071] The mesa portion 60 of the transistor section 70 has an emitter region 12 exposed on the front surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 has a contact region 15 exposed on the front surface of the semiconductor substrate 10.

[0072] The contact regions 15 and the emitter regions 12 in the mesa portion 60 are each provided from one trench portion to the other trench portion in the X-axis direction. As an example, the contact regions 15 and the emitter regions 12 in the mesa portion 60 are alternately arranged along the Y-axis direction.

[0073] In another example, the contact region 15 and the emitter region 12 of the mesa portion 60 may be provided in a stripe pattern along the Y-axis direction. For example, the emitter region 12 is provided in a region that contacts the trench portion, and the contact region 15 is provided in a region sandwiched between the emitter regions 12.

[0074] The mesa portion 60 of the diode portion 80 does not have an emitter region 12. A base region 14 may be provided on the upper surface of the mesa portion 60 of the diode portion 80. The base region 14 may be disposed over the entire mesa portion 60 of the diode portion 80.

[0075] A contact hole 54 is provided above each mesa portion. The contact holes 54 are arranged in a region sandwiched between the base regions 14 in the Y-axis direction. In this example, the contact holes 54 are provided above the contact region 15, the base region 14, and the emitter region 12. The contact holes 54 may be arranged in the center of the mesa portion in the X-axis direction.

[0076] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate 10. A P+ type collector region 22 may be provided in a region of the back surface of the semiconductor substrate 10 where the cathode region 82 is not provided. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is indicated by a dotted line.

[0077] The cathode region 82 is disposed away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and a P-type region (well region 11) that has a relatively high doping concentration and is formed deep, thereby suppressing hole injection from the well region 11 and reducing reverse recovery loss. In this example, the end of the cathode region 82 in the Y-axis direction is disposed farther from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be disposed between the well region 11 and the contact hole 54.

[0078] The transistor section 70 has a boundary region 91 on the side of the adjacent diode section 80. The boundary region 91 is a region whose configuration is changed from the other transistor sections 70 so as to prevent structural and performance problems in the region adjacent to the diode section 80. The boundary region 91 includes multiple mesa sections 60. In FIG. 2, the boundary region 91 includes two mesa sections 60, but it may consist of one mesa section 60 or may include more than two mesa sections 60. A dummy trench section 30 may be provided in the boundary region 91, and no gate trench section 40 may be provided. The mesa section 60 closest to the diode section 80 of the boundary region 91 may not be provided with an emitter region 12. Note that the boundary region 91 need not be provided.

[0079] Furthermore, the transistor section 70 has a transition region 90 on the side of the adjacent diode section 80. The transition region 90 may include the boundary region 91 described above on the side closest to the diode section 80. The transition region 90 includes a plurality of mesa sections 60. The transition region 90 is a region that affects the characteristics of the diode section 80 due to its proximity to the diode section 80. Taking into consideration the effect on the diode section 80, the transition region 90 may have a different configuration from the transistor section 70 that is not in the transition region 90, thereby changing the characteristics. An example of the configuration of the transition region 90 will be described later.

[0080] 3A is a diagram showing the aa cross section of Fig. 2. The aa cross section is an XZ plane passing through the contact region 15, the base region 14, the gate trench portion 40, and the dummy trench portion 30. In the aa cross section, the semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24.

[0081] The interlayer insulating film 38 is provided on the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 may be an insulating film such as silicate glass doped with impurities such as boron or phosphorus. The interlayer insulating film 38 may be in contact with the front surface 21, or another film such as an oxide film may be provided between the interlayer insulating film 38 and the front surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 has a contact hole 54, as described with reference to FIG. 2 .

[0082] The emitter electrode 52 is provided on the front surface 21 of the semiconductor substrate 10 and on the upper surface of the interlayer insulating film 38. The emitter electrode 52 is electrically connected to the front surface 21 of the semiconductor substrate 10 via a contact hole 54 in the interlayer insulating film 38. A plug (not shown) made of tungsten (W) or the like may be embedded inside the contact hole 54 via a barrier metal film. A P++-type plug region may be provided in the surface layer of the semiconductor substrate 10 where the contact hole 54 is provided. The doping concentration of the plug region is higher than the doping concentration of the contact region 15.

[0083] The collector electrode 24 is provided on the rear surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 may be formed of a material containing a metal or a laminated film thereof.

[0084] The semiconductor substrate 10 may be a single semiconductor substrate such as a silicon substrate or a diamond substrate, or may be a compound semiconductor substrate such as a silicon carbide substrate or a nitride semiconductor such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate.

[0085] The semiconductor substrate 10 has a drift region 18 of a first conductivity type. In this example, the drift region 18 is N-type. The drift region 18 may be a remaining region of the semiconductor substrate 10 without other doped regions being provided therein.

[0086] One or more accumulation regions 16 may be provided in the Z-axis direction above the drift region 18. The accumulation region 16 is a region in which the same dopant as the drift region 18 is accumulated at a higher concentration than the drift region 18. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18.

[0087] The accumulation region 16 in this example is N+ type. The accumulation region 16 may be provided only in the transistor section 70, or may be provided in both the transistor section 70 and the diode section 80. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 in this example is provided only in the transistor section 70, and is not provided in the diode section 80.

[0088] In the transistor section 70, an emitter region 12 is provided above the base region 14 in contact with the front surface 21 of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench section 40. The doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. Examples of dopants for the emitter region 12 include arsenic (As), phosphorus (P), and antimony (Sb).

[0089] The diode section 80 has a base region 14 exposed on the front surface 21 of the semiconductor substrate 10. The base region 14 of the diode section 80 operates as an anode. The base region 14 of the diode section 80 may be formed with the same concentration and at the same depth as the base region 14 of the transistor section 70, or may be formed with a different concentration and at a different depth.

[0090] A buffer region 20 of the first conductivity type may be provided below the drift region 18. In this example, the buffer region 20 is N+ type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 and the cathode region 82.

[0091] In the transistor section 70, a collector region 22 is provided below the buffer region 20. The collector region 22 may be provided on the rear surface 23 of the semiconductor substrate 10 in contact with the cathode region 82.

[0092] In the diode section 80, a cathode region 82 is provided below the buffer region 20. The cathode region 82 may be provided at the same depth as the collector region 22 of the transistor section 70, or may be provided to a different depth. The cathode region 82 may be electrically floating, or may partially have a P+ type region in contact with the collector electrode 24. The diode section 80 may function as a free wheeling diode (FWD) that conducts in the reverse direction and passes a free wheeling current when the transistor section 70 is not conducting.

[0093] The semiconductor substrate 10 is provided with a gate trench portion 40 and a dummy trench portion 30. The gate trench portion 40 and the dummy trench portion 30 are provided so as to pass from the front surface 21 of the semiconductor substrate 10 through the base region 14 and the accumulation region 16 to reach the drift region 18. The trench portion passing through the doped region is not limited to a case where the trench portion is formed after the doped region is formed. A case where the doped region is formed between the trench portions after the trench portions are formed is also included in the case where the trench portion passes through the doped region.

[0094] The gate trench portion 40 has a gate trench provided in the front surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided to cover the inner wall of the gate trench. The gate insulating film 42 may be formed of an oxide film or a nitride film. The gate conductive portion 44 is provided so as to fill the inside of the gate trench more inward than the gate insulating film 42. The upper surface of the gate conductive portion 44 may be located in the same XY plane as the front surface 21 of the semiconductor substrate 10. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 may be formed of impurity-doped polysilicon or the like.

[0095] The gate conductive portion 44 may be provided to be longer in the depth direction than the base region 14. The gate trench portion 40 is covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel is formed by an electron inversion layer in the surface layer of the interface of the base region 14 that contacts the gate trench.

[0096] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in the XZ cross section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the front surface 21 of the semiconductor substrate 10. The dummy insulating film 32 is provided to cover the inner wall of the dummy trench. The dummy insulating film 32 may be formed of an oxide film or a nitride film. The dummy conductive portion 34 is provided so as to fill the inside of the dummy trench more inward than the dummy insulating film 32. The upper surface of the dummy conductive portion 34 may be located in the same XY plane as the front surface 21 of the semiconductor substrate 10. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0097] The gate trench portion 40 and the dummy trench portion 30 in this example are covered with an interlayer insulating film 38 on the front surface 21 of the semiconductor substrate 10. The bottoms of the dummy trench portion 30 and the gate trench portion 40 may have a downwardly convex curved shape (a curved shape in cross section).

[0098] In the diode section 80, a lifetime control region 72 including a lifetime killer is locally provided in the drift region 18. The lifetime killer is a crystal defect formed at a predetermined depth in the semiconductor substrate 10 by implanting, for example, helium ions, hydrogen ions (protons, deuterons), etc. The lifetime control region 72 promotes recombination between holes generated in the base region 14 of the diode section 80 and electrons injected from the cathode region 82, thereby suppressing peak current during reverse recovery.

[0099] The lifetime control region 72 may be formed by irradiating the semiconductor substrate 10 with a proton or helium particle beam from the front surface 21 or the back surface 23 using a mask. As an example, the proton or helium particle beam is irradiated onto the transistor section 70 and the diode section 80 through openings in a resist mask, with the region where the lifetime control region 72 is not to be formed being shielded by the resist mask formed above the front surface 21 of the semiconductor substrate 10. The proton or helium particle beam is not irradiated onto the region shielded by the mask.

[0100] 3A, the peak position in the Z-axis direction of the lifetime killer concentration distribution is indicated by an "x" symbol. The peak position in the Z-axis direction of the lifetime control region 72 in this example may be the same as the position in the Z-axis direction of the lower surface of the well region 11, or may be located lower than the position in the Z-axis direction of the lower surface of the well region 11. Furthermore, the lifetime control region 72 may be formed so that the lifetime killer concentration distribution has multiple peaks in the Z-axis direction.

[0101] The lifetime control region 72 in this example is provided continuously from the diode portion 80 to at least a portion of the transistor portion 70 on the front surface 21 side of the semiconductor substrate 10. In this example, the lifetime control region 72 is provided in the transition region 90 of the transistor portion 70. When the diode portion 80 is conductive, a hole current is generated not only in the base region 14 of the diode portion 80 but also from the base region 14 of the transistor portion 70 toward the cathode region 82. The transistor portion 70 has the transition region 90 provided with the lifetime control region 72, which promotes carrier annihilation and reduces reverse recovery loss.

[0102] However, in the trench portion of the transition region 90 of this example, when a particle beam of helium or protons is irradiated from the front surface 21 or the back surface 23 of the semiconductor substrate 10, damage occurs in the gate insulating film 42, causing a change in the interface state. When a gate voltage is applied to the irradiated gate insulating film 42, an inversion layer is more likely to form in the adjacent base region 14 than in the unirradiated gate insulating film 42. Therefore, the threshold voltage of the transition region 90 provided with the lifetime control region 72 is lower than that of the region other than the transition region 90 of the transistor section 70. Furthermore, the leakage current of the transition region 90 provided with the lifetime control region 72 is higher than that of the region other than the transition region 90 of the transistor section 70. Furthermore, the conduction loss of the transition region 90 provided with the lifetime control region 72 is higher than that of the region other than the transition region 90 of the transistor section 70.

[0103] In this example, the lifetime control region 72 is provided in the transition region 90, but is not provided in the region other than the transition region 90 of the transistor section 70. However, this is not limiting. In another example, as shown in Fig. 3B, the shape of the lifetime control region 72 may be changed between the transition region 90 and the region other than the transition region 90 to provide different characteristics. For example, the concentration of the lifetime killer or the position of the lifetime control region 72 in the Z-axis direction may be different.

[0104] 3C , the configuration of the accumulation region 16 may be changed to provide different characteristics between the transition region 90 and regions other than the transition region 90. For example, regardless of whether or not the accumulation region 16 is present, differences in the concentration of the accumulation region 16, differences in the integrated concentration in the Z-axis direction, etc. may be provided.

[0105] 3D , the arrangement of the contact region 15 may be changed to provide different characteristics between the transition region 90 and the region other than the transition region 90. Alternatively, the area of ​​the contact region 15 may be different between the transition region 90 and the region other than the transition region 90.

[0106] 3E, the shape of the contact hole 54 may be changed to provide different characteristics between the transition region 90 and the region other than the transition region 90. For example, the depth or width of the contact hole 54 may be changed between the transition region 90 and the region other than the transition region 90.

[0107] 3F , the transition region 90 may have an inactive region where the transistor is not conductive, without providing the gate trench portion 40 and the emitter region 12. The inactive region of the transition region 90 may not have the contact region 15 or the accumulation region 16. A boundary region 91 may be provided between the inactive region of the transition region 90 and the region of the transistor portion 70 other than the transition region 90.

[0108] 3G , there may be no difference in configuration between the transition region 90 and the region other than the transition region 90. In this case, the conduction loss in the transition region 90 is not increased compared to the region other than the transition region 90 of the transistor section 70, but the characteristics of the diode section 80 are affected, as in the other examples. In either configuration, the characteristics of the transistor section 70 and the diode section 80 are affected in the transition region 90.

[0109] 4 is a top view showing an example of the arrangement of the transistor sections 70 and the diode sections 80 in the first active section 260 according to the comparative example. The first active section 260 has a first end X1 and a second end X2 opposite to the first end X1 in the X-axis direction. Here, the first end X1 is on the positive side in the X-axis direction and the second end X2 is on the negative side in the X-axis direction, but this may be reversed.

[0110] The first active section 260 has a plurality of transistor sections 70 and a plurality of diode sections 80 arranged alternately in the X-axis direction. On the front surface 21 of the semiconductor substrate 10, the area of ​​the transistor sections 70 may be larger than the area of ​​the diode sections 80. Of the plurality of diode sections 80, the diode section 80 provided closest to the first end X1 will be referred to as the first diode section 80-1, and the diode section 80 provided closest to the second end X2 will be referred to as the second diode section 80-2. Of the plurality of transistor sections 70, the transistor section 70 provided closest to the first end X1 will be referred to as the first transistor section 70-1, and the transistor section 70 provided closest to the second end X2 will be referred to as the second transistor section 70-2.

[0111] In the first active section 260, the first transistor section 70-1 is provided closer to the first end X1 than the first diode section 80-1, and the second transistor section 70-2 is provided closer to the second end X2 than the second diode section 80-2. That is, in the first active section 260, the transistor sections 70 (the first transistor section 70-1 and the second transistor section 70-2) are arranged at both ends of the array. On the front surface 21 of the semiconductor substrate 10, the area of ​​each of the first transistor section 70-1 and the second transistor section 70-2 may be the same as the area of ​​the other transistor sections 70, or may be smaller than the area of ​​the other transistor sections 70.

[0112] In the example of Fig. 4, the first active section 260 has five transistor sections 70 and four diode sections 80. Each transistor section 70 has a transition region 90 on the side of the adjacent diode section 80. The transition region 90 is a region of the transistor section 70 that contacts the diode section 80. The four diode sections 80 shown in Fig. 4 are adjacent to the transistor section 70 at both ends in the X-axis direction, so eight transition regions 90 are provided that are proportional to the number of diode sections 80.

[0113] 5A is a top view showing an example of the arrangement of the transistor sections 70 and the diode sections 80 in the first active section 160. Like the first active section 260, the first active section 160 has a first end X1 and a second end X2 opposite the first end X1 in the X-axis direction. In FIG. 5A, the first end X1 is on the positive side in the X-axis direction and the second end X2 is on the negative side in the X-axis direction, but this may be reversed.

[0114] Like the first active section 260, the first active section 160 has a plurality of transistor sections 70 and a plurality of diode sections 80 arranged alternately in the X-axis direction. Of the plurality of diode sections 80, the diode section 80 provided closest to the first end X1 will be referred to as the first diode section 80-1, and the diode section 80 provided closest to the second end X2 will be referred to as the second diode section 80-2. Of the plurality of transistor sections 70, the transistor section 70 provided closest to the first end X1 will be referred to as the first transistor section 70-1, and the transistor section 70 provided closest to the second end X2 will be referred to as the second transistor section 70-2.

[0115] In this example, the first diode section 80-1 is provided closer to the first end X1 than the first transistor section 70-1. That is, the first diode section 80-1 is provided closest to the first end X1 in the arrangement of the transistor section 70 and the diode section 80. The first diode section 80-1 may be provided at the first end X1, or may be provided away from the first end X1.

[0116] In this example, the second transistor section 70-2 is provided closer to the second end X2 than the second diode section 80-2. That is, the second transistor section 70-2 is provided closest to the second end X2 in the arrangement of the transistor sections 70 and the diode section 80. The second transistor section 70-2 may be provided at the second end X2, or may be provided away from the second end X2.

[0117] On the front surface 21 of the semiconductor substrate 10, the area ratio of the transistor portion 70 to the diode portion 80 in the first active portion 160 in FIG. 5A may be the same as that of the first active portion 260 in FIG.

[0118] Similar to the first active section 260, each transistor section 70 has a transition region 90 on the side of the adjacent diode section 80. The first active section 160 in FIG. 5A has four transistor sections 70 and four diode sections 80, and therefore has seven transition regions 90.

[0119] The transition region 90 in this example is a region of the transistor portion 70 in which the lifetime control region 72 is provided to reduce reverse recovery loss in the diode portion 80. If the area ratio of the transition region 90 to the transistor portion 70 increases, the performance of the transistor portion 70 decreases. Also, the influence on the diode portion 80 increases.

[0120] The first active unit 160 of this example and the first active unit 260 of the comparative example have the same number of diode units 80. However, in the first active unit 160, no transistor unit 70 is provided on the first end X1 side of the first diode unit 80-1, and therefore no transition region 90 is provided. Therefore, the number of transition regions 90 in the first active unit 160 is smaller than the number of transition regions 90 in the first active unit 260.

[0121] In this way, in the first active section 160 of this example, the area ratio of the transition region 90 to the transistor section 70 on the front surface 21 of the semiconductor substrate 10 is reduced compared to the first active section 260, thereby improving the characteristics of the transistor section 70 and reducing the effect on the diode section 80. In this way, since the first active section 160 of this example has improved characteristics compared to the first active section 260, the area ratio of the transistor section 70 to the diode section 80 may be the same as or different from that of the first active section 260.

[0122] Fig. 5B is a top view showing another example of the arrangement of the transistor sections 70 and the diode sections 80 in the first active section 160. Here, the same components as those in the first active section 160 in Fig. 5A are denoted by the same reference numerals and will not be described again, and the following description will focus on the differences from Fig. 5A.

[0123] The second diode section 80-2 in this example is located closer to the second end X2 than the second transistor section 70-2. That is, in the first active section 160 in this example, the diode sections 80 (first diode section 80-1 and second diode section 80-2) are arranged at both ends of the array. The first active section 160 in FIG. 5B has three transistor sections 70 and four diode sections 80, and six transition regions 90. Unlike the first active section 160 in FIG. 5A, no transistor section 70 is located closer to the second end X2 than the second diode section 80-2, and therefore no transition region 90 is located either. Therefore, the number of transition regions 90 in the first active section 160 in FIG. 5B is even smaller than the number of transition regions 90 in the first active section 160 in FIG. 5A. Furthermore, since the number of transistor sections 70 is also smaller than in the first active section 160 in FIG. 5A, the area per transistor section 70 on the front surface 21 of the semiconductor substrate 10 is larger.

[0124] In this way, in the first active section 160 of this example, the area ratio of the transition region 90 to the transistor section 70 on the front surface 21 of the semiconductor substrate 10 is further reduced than in the first active section 260, thereby further improving the characteristics of the transistor section 70 and reducing the effect on the diode section 80. In this way, since the first active section 160 of this example has improved characteristics compared to the first active section 260, the area ratio of the transistor section 70 to the diode section 80 may be the same as or different from that of the first active section 260.

[0125] Figure 5C is a modified example of the arrangement of the transistor sections 70 and diode sections 80 shown in Figure 5B. The number of transistor sections 70 and diode sections 80 included in the first active section 160 in Figure 5C is the same as in Figure 5B. However, in this example, the areas of the first diode section 80-1 and the second diode section 80-2 on the front surface 21 of the semiconductor substrate 10 are different from the areas of the other diode sections 80.

[0126] As shown in FIG. 5C , the areas of the second diode section 80-1 and the second diode section 80-2 may be smaller than the areas of the other diode sections 80. That is, in the X-axis direction, the width W1 of the first diode section 80-1 and the width W2 of the second diode section 80-2 may be smaller than the width W of the other diode sections 80. The width W1 of the first diode section 80-1 and the width W2 of the second diode section 80-2 may be the same or different. In the first active section 160 of FIG. 5C , the total area of ​​the diode sections 80 is smaller than that of the first active section 160 of FIG. 5B , and therefore the area per transistor section 70 on the front surface 21 of the semiconductor substrate 10 is larger. Note that, depending on the desired characteristics, the area of ​​each diode section 80 in the first active section 160 of FIG. 5C may be changed to make the area ratio between the transistor section 70 and the diode section 80 the same as that of the first active section of FIG. 5B , or the total area of ​​the diode sections 80 may be larger than that of the first active section of FIG. 5B .

[0127] FIG. 5D is a modified example of the arrangement of the transistor sections 70 and diode sections 80 shown in FIG. 5B . The number of transistor sections 70 and diode sections 80 included in the first active section 160 in FIG. 5D is the same as that in FIG. 5B . As shown in FIG. 5D , the area of ​​the second diode section 80-1 and the second diode section 80-2 on the front surface 21 of the semiconductor substrate 10 may be larger than the area of ​​the other diode sections 80. That is, in the X-axis direction, the width W1 of the first diode section 80-1 and the width W2 of the second diode section 80-2 may be larger than the width W of the other diode sections 80. The width W1 of the first diode section 80-1 and the width W2 of the second diode section 80-2 may be the same or different. In the first active section 160 in FIG. 5D , the total area of ​​the diode sections 80 on the front surface 21 of the semiconductor substrate 10 is larger than that of the first active section 160 in FIG. 5B , and therefore the area per transistor section 70 is smaller. Depending on the desired characteristics, the area of ​​one diode section 80 may also be changed in the first active section 160 of FIG. 5D to make the area ratio of the transistor section 70 and the diode section 80 the same as in the first active section of FIG. 5B, or the total area of ​​the diode sections 80 may be smaller than that of the first active section of FIG. 5B.

[0128] In this way, as in the first active section 160 of Figures 5C and 5D, the area ratio of the transistor section 70 and the diode section 80 on the front surface 21 of the semiconductor substrate 10 can be set according to the area ratio of the required transition region 90.

[0129] FIG. 6 is a diagram illustrating another example of the top surface of the semiconductor device 100. The semiconductor device 100 of this example has multiple active sections divided in the Y-axis direction, with the transistor sections 70 and diode sections 80 arranged differently in each active section. In this example, the region surrounded by the well region 11 on the positive side of the boundary 49 in the Y-axis direction in a top view is referred to as the first active section 160, and the region surrounded by the well region 11 on the negative side of the boundary 49 in the Y-axis direction is referred to as the second active section 161. The boundary 49 may extend entirely in the X-axis direction, or may entirely or partially form an angle of 0° or more with the X-axis direction. In this example, the boundary 49 extends in the X-axis direction. The first active section 160 has a first end X1 and a second end X2 opposite the first end X1 in the X-axis direction. The second active section 161 is separated from the first active section 160 by the boundary 49 and, like the first active section 160, has multiple transistor sections 70 and multiple diode sections 80 arranged alternately in the X-axis direction. The second active portion 161 has a third end X3 and a fourth end X4 opposite to the third end X3 in the X-axis direction. In the Y-axis direction, the third end X3 is adjacent to the first end X1 of the first active portion 160, and the fourth end X4 is adjacent to the second end X2 of the first active portion 160.

[0130] The boundary 49 may further include an inner gate runner on the front surface 21 of the semiconductor substrate 10, extending in the X-axis direction near the center of the semiconductor substrate 10 and connecting to the peripheral gate runner 47. The inner gate runner is an example of a gate runner that, like the peripheral gate runner 47, electrically connects the conductive portions of the gate trench portions of the first active portion 160 and the second active portion 161 to the gate pad. The inner gate runner may be formed with a structure similar to that of the peripheral gate runner 47, and may include a well region 11, a gate metal layer 50, a semiconductor gate runner 48, etc.

[0131] FIG. 7A is a top view showing an example of the arrangement of the transistor sections 70 and the diode sections 80 in the first active section 160 and the second active section 161. FIG.

[0132] Of the multiple diode sections 80 in the second active section 161, the diode section 80 provided closest to the third end X3 is referred to as the third diode section 80-3, and the diode section 80 provided closest to the fourth end X4 is referred to as the fourth diode section 80-4. Of the multiple transistor sections 70 in the second active section 161, the transistor section 70 provided closest to the third end X3 is referred to as the third transistor section 70-3, and the transistor section 70 provided closest to the fourth end X4 is referred to as the fourth transistor section 70-4.

[0133] The arrangement of the plurality of transistor sections 70 and the plurality of diode sections 80 in the second active section 161 is different from the arrangement of the plurality of transistor sections 70 and the plurality of diode sections 80 in the first active section 160 .

[0134] In the first active section 160 of this example, the first diode section 80-1 is provided closer to the first end X1 than the first transistor section 70-1, and in the second active section 161, the third transistor section 70-3 is provided closer to the third end X3 than the third diode section 80-3. In other words, the first diode section 80-1 of the first active section 160 and the third transistor section 70-3 of the second active section 161 are adjacent to each other in the Y-axis direction.

[0135] In the first active unit 160 of this example, the second transistor unit 70-2 is provided closer to the second end X2 than the second diode unit 80-2, and in the second active unit 161, the fourth diode unit 80-4 is provided closer to the fourth end X4 than the fourth transistor unit 70-4. In other words, the second transistor unit 70-2 of the first active unit 160 and the fourth diode unit 80-4 of the second active unit 161 are adjacent to each other in the Y-axis direction.

[0136] 7A each has four transistor sections 70 and four diode sections 80, and seven transition regions 90. In other words, the number of transition regions 90 in the first active section 160 is equal to the number of transition regions 90 in the second active section 161. In this way, the transistor sections 70 and diode sections 80 in the first active section 160 and the second active section 161 are arranged symmetrically in the X-axis direction.

[0137] On the front surface 21 of the semiconductor substrate 10, the area of ​​each transistor portion 70 may be larger than the area of ​​each diode portion 80. In the Y-axis direction, the diode portion 80 of the first active portion 160 may be adjacent to the transistor portion 70 of the second active portion 161, and the diode portion 80 of the second active portion 161 may be adjacent to the transistor portion 70 of the first active portion 160.

[0138] 7B is a top view showing another example of the arrangement of transistor sections 70 and diode sections 80 in the first active section 160 and the second active section 161. In this example, a plurality of first active sections 160 are provided. The semiconductor device 100 in FIG. 7B has two first active sections 160 and one second active section 161, and the second active section 161 is adjacent to the first active section 160 on the positive and negative sides in the Y-axis direction.

[0139] In the first active section 160 of this example, the first diode section 80-1 is provided closer to the first end X1 than the first transistor section 70-1, and the second diode section 80-2 is provided closer to the second end X2 than the second transistor section 70-2. On the other hand, in the second active section 161, the third transistor section 70-3 is provided closer to the third end X3 than the third diode section 80-3, and the fourth transistor section 70-4 is provided closer to the fourth end X4 than the fourth diode section 80-4.

[0140] 6 has three transistor sections 70 and four diode sections 80, and has seven transition regions 90. The second active section 161 has four transistor sections 70 and three diode sections 80, and has seven transition regions 90. In other words, the number of transition regions 90 in the first active section 160 is equal to the number of transition regions 90 in the second active section 161. In this way, the diode sections 80 in the first active section 160 and the second active section 161 are arranged in a lattice pattern.

[0141] On the front surface 21 of the semiconductor substrate 10, the area of ​​each transistor portion 70 may be larger than the area of ​​each diode portion 80. In the Y-axis direction, the diode portion 80 of the first active portion 160 may be adjacent to the transistor portion 70 of the second active portion 161, and the diode portion 80 of the second active portion 161 may be adjacent to the transistor portion 70 of the first active portion 160.

[0142] FIG. 8 is an enlarged top view of an example of region B in FIG. 1 . Region B is an XY plane including the vicinity of the end of the first diode section 80-1 of the first active section 160 on the negative side in the Y-axis direction and the end on the positive side in the X-axis direction. In this example, the first active section 160 is surrounded by the well region 11 in a top view. In this example, the region surrounded by the well region 11 in a top view is the first active section 160, and the area from the well region 11 toward the edge 102 is the peripheral region 190. The well region 11 extends and overlaps the peripheral gate runner 47, forming a ring shape in a top view. A field plate 94 and a guard ring 92 are provided outside the well region 11, forming an edge termination region. The field plate 94 and the guard ring 92 are connected by a contact hole 57. The field plate 94 is insulated from the emitter electrode 52 and the peripheral gate runner 47.

[0143] The first diode section 80-1 in this example is provided more inward in the X-axis direction than the end (first end X1) of the first active section 160. An outer edge section 93 is provided in a region of the first diode section 80-1 adjacent to the first end X1. The outer edge section 93 in this example has a base region 14 provided on the front surface 21 of the semiconductor substrate 10. In other words, the outer edge section 93 has the same front surface structure as the diode section 80.

[0144] Fig. 9 is a view showing the cc cross section of Fig. 8. The outer edge portion 93 of this example differs in structure from the other diode portions 80 in that the collector region 22 is provided on the rear surface 23 of the semiconductor substrate 10.

[0145] When the first diode section 80-1 is provided at the first end X1 of the first active section 160, the cathode region 82 of the first diode section 80-1 is close to the well region 11. Therefore, the well region 11 may operate as a diode, increasing the reverse recovery current and resulting in increased reverse recovery loss. Therefore, in this example, an outer edge portion 93 is provided on the first end X1 side of the first diode section 80-1, so that the outer end of the cathode region 82 of the first diode section 80-1 is located more inward than the inner end of the well region 11 in the X-axis direction. This suppresses the diode operation of the well region 11 and prevents an increase in reverse recovery loss.

[0146] In another example, outer edge portion 93 may not be provided, and the boundary between cathode region 82 and collector region 22 may coincide with the boundary between base region 14 and well region 11, or cathode region 82 may be provided below well region 11. In still another example, an N-type semiconductor region having a lower concentration than cathode region 82 or a P-type semiconductor region having a lower concentration than collector region 22 may be provided on back surface 23 of outer edge portion 93 or peripheral region 190, instead of collector region 22.

[0147] The well region 11 also has a resistor portion 84 provided at the end portion closer to the edge 102 than the contact hole 54 provided closest to the edge 102. The resistor portion 84 may or may not have at least one trench portion (dummy trench portion 30).

[0148] The width of the resistor section 84 in the X-axis direction may be 20 μm to 200 μm, more preferably 30 μm to 120 μm, or 4% to 100%, more preferably 6% to 60% of the width of the first diode section 80-1.

[0149] In this way, by providing the resistor portion 84 without the contact hole 54 in the well region 11, it is possible to prevent the current from the cathode region 82 from concentrating on the edge 102 side of the well region 11.

[0150] The lifetime control region 72 of this example is provided to extend in the X-axis direction from the first diode portion 80-1 to at least a part of the well region 11. The lifetime control region 72 may be provided below the well region 11.

[0151] In this way, in this example, by providing the lifetime control region 72 below the base region 14 and well region 11 of the first diode section 80-1, it is possible to reduce the reverse recovery current and the reverse recovery loss.

[0152] In another example, the lifetime control region 72 does not have to be provided below the well region 11. In yet another example, the lifetime control region 72 does not have to be provided in the outer edge portion 93. In yet another example, the lifetime control region 72 may be provided below the guard ring 92.

[0153] 8 and 9 are not limited to the first active section 160 in FIGS. 5A to 5D, but may also be applied to the first active section 160 in FIGS. 6 to 7B.

[0154] 10A shows an example of a top view of a semiconductor module 1000 according to an embodiment. The longitudinal direction of a rectangular housing 1060 in the top view of FIG. 10A is the x-axis, and the lateral direction is the y-axis. The z-axis forms a right-handed system with the x-axis and y-axis.

[0155] The semiconductor module 1000 includes a heat dissipation base 1010, a housing 1060, and semiconductor cells 1110. The semiconductor module 1000 of this example includes three semiconductor cells 1110.

[0156] The housing 1060 is a terminal case made of resin. The housing 1060 defines an area for accommodating the semiconductor cell 1110 and is provided so as to surround the semiconductor cell 1110 in a top view.

[0157] The fin-integrated base 1205 has a heat dissipation base 1010 and cooling fins 1210, which will be described later. The fin-integrated base 1205 has a fin-integrated structure in which the heat dissipation base 1010 and the cooling fins 1210 are integrally formed. In this specification, a semiconductor module 1000 including a fin-integrated heat dissipation base 1010 is referred to as a fin-integrated semiconductor module. The fin-integrated semiconductor module 1000 can reduce warpage in the finished product by warping the fin-integrated heat dissipation base 1010 in advance and then reflowing it.

[0158] The heat dissipation base 1010 is provided on the underside of the semiconductor module 1000. The heat dissipation base 1010 may be a metal plate having a flat surface parallel to the xy plane. For example, the material of the heat dissipation base 1010 is a metal material containing aluminum or copper. The heat dissipation base 1010 is provided so as to overlap the housing 1060 when viewed from above.

[0159] The semiconductor cells 1110 are mounted on the upper surface of the heat dissipation base 1010. The semiconductor cells 1110 are fixed to the upper surface of the heat dissipation base 1010 with a bonding material such as solder. This allows heat generated in the semiconductor cells 1110 to be transferred to the heat dissipation base 1010. In this example, three semiconductor cells 1110 are arranged side by side in the x-axis direction, which is the longitudinal direction, but this is not limited to this example. The semiconductor cells 1110 are an assembly including an insulating substrate 1020 and any one of the semiconductor devices 100 shown in Figures 1 to 3G and Figures 5A to 9. In this example, four semiconductor devices 100 are provided, with two pairs of two semiconductor cells for each of the three semiconductor cells 1110.

[0160] The insulating substrate 1020 is soldered onto the heat dissipation base 1010. The insulating substrate 1020 may be a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate. The insulating substrate 1020 has a conductive plate 1021 and an insulating plate 1022.

[0161] The insulating plate 1022 is made of an insulating material such as ceramic. For example, the insulating plate 1022 is made of alumina (Al ２ O ３ ), aluminum nitride (AlN) or silicon nitride (Si ３ N ４ )

[0162] The conductive plate 1021 is a wiring pattern provided on the upper surface of the insulating plate 1022. For example, the material of the conductive plate 1021 is a metal material such as copper or a copper alloy. The conductive plate 1021 is solder-joined to the collector electrode 24 of the semiconductor device 100, for example, using solder. In another example, the conductive plate 1021 and the collector electrode 24 of the semiconductor device 100 may be joined by pressure bonding. In this way, the conductive plate 1021 is electrically connected to the semiconductor device 100. In the semiconductor cell 1110, the semiconductor device 100, the conductive plate 1021, and the metal wiring plate 1040 may be electrically connected to form a half-bridge circuit.

[0163] The metal wiring board 1040 is electrically connected to the semiconductor device 100. For example, the metal wiring board 1040 wires the emitter of the semiconductor device 100. One end of the metal wiring board 1040 may be connected to the emitter electrode 52 of the semiconductor device 100 via solder, for example. The other end of the metal wiring board 1040 may be connected to an external connection terminal for connecting to the outside of the semiconductor module 1000. The metal wiring board 1040 may be a conductive connection member formed by pressing a metal plate or the like. The metal plate may be a copper or copper alloy plate. The metal wiring board 1040 may have a nickel or other plating film on its surface. The cross section (z-x cross section) of the metal wiring board 1040 may have a rectangular portion. In another example, the metal wiring board 1040 may have a wire-like shape and be connected to the emitter electrode 52 of the semiconductor device 100 by ultrasonic bonding or the like.

[0164] The housing 1060 has a plurality of main terminals 1062. The main terminals 1062 include, for example, a U-phase terminal, a V-phase terminal, and a W-phase terminal for driving the U-phase, V-phase, and W-phase, respectively, in a three-phase inverter circuit. The main terminals 1062 also include, for example, a power supply terminal for supplying power to the three-phase inverter circuit.

[0165] 10B is a diagram showing an example of the ff cross section in Fig. 10A. The ff cross section is an xz cross section passing through the housing 1060 and the semiconductor cell 1110. The semiconductor module 1000 has a cooling unit 1200.

[0166] The cooling unit 1200 is disposed below the semiconductor cell 1110. A coolant can be supplied to the cooling unit 1200 from the outside. The cooling unit 1200 cools the semiconductor module 1000 by circulating the coolant. The cooling unit 1200 has a fin-integrated base 1205 and a cooling case 1220. Heat generated by the operation of the semiconductor device 100 is released to the outside of the semiconductor module 1000 via the cooling unit 1200 and the coolant.

[0167] The cooling fins 1210 form multiple flow paths for circulating the refrigerant. The cooling fins 1210 are arranged to extend in the Z-axis direction. One end of the cooling fin 1210 on the positive side of the Z-axis is connected to the underside of the heat dissipation base 1010. One end of the cooling fin 1210 on the negative side of the Z-axis may be in contact with the underside of the cooling case 1220. Multiple cooling fins 1210 are arranged at any intervals in the X-axis direction. The cooling fins 1210 may be straight fins, wave-shaped fins, pin fins, corrugated fins, or laminated fins. The cooling fins 1210 may be formed of a metal with the same composition as the cooling case 1220. The cooling fins 1210 are formed of a metal containing aluminum or copper, for example. The material of the cooling fins 1210 may be a metal containing aluminum to reduce weight.

[0168] The heat dissipation base 1010 has an integrated structure with the cooling fins 1210. That is, the heat dissipation base 1010 is provided in connection with the cooling fins 1210. In one example, the fin-integrated heat dissipation base 1010 is manufactured by forming the fins by cutting, brazing, pressing, forging, mounting, crimping, etc.

[0169] The cooling case 1220 houses the cooling fins 1210. The cooling case 1220 covers the bottom and side surfaces of the cooling fins 1210. The top surfaces of the cooling fins 1210 are covered by the heat dissipation base 1010. The cooling case 1220 may be formed of the same material as the heat dissipation base 1010. The cooling case 1220 may be a box-shaped part having a bottom plate and side walls. The cooling case 1220 may have a flange connected to the side wall. The flange may be joined to the heat dissipation base 1010.

[0170] The insulating substrate 1020 is solder-joined to the heat dissipation base 1010 by an under-substrate solder section 1025. The insulating substrate 1020 has a conductive plate 1021, an insulating plate 1022, and a conductive plate 1023.

[0171] The conductive plate 1023 is provided on the lower surface of the insulating plate 1022. The conductive plates 1021 and 1023 are formed of a conductive material or a metal material such as copper or a copper alloy. The conductive plate 1023 is provided on almost the entire lower surface of the insulating plate 1022.

[0172] The sealing resin 1050 seals the inside of the housing 1060. The sealing resin 1050 covers the periphery of the semiconductor cell 1110. The material of the sealing resin 1050 may be either an epoxy resin or a silicone gel. The lower surface of the sealing resin 1050 may be in contact with the upper surface of the heat dissipation base 1010. The side surface of the sealing resin 1050 may be in contact with the housing 1060. The upper surface of the sealing resin 1050 is located lower than the upper surface of the housing 1060.

[0173] The cooling case 1220 and the cooling fins 1210 may be formed by pressing, forging, or extrusion. The cooling case 1220 and the cooling fins 1210 may be assembled by brazing. The brazing material may be made of a metal having a lower melting point than the cooling case 1220. The brazing material may be made of a metal containing copper or aluminum as the low-melting-point metal.

[0174] 10C is an example of a bottom view of the semiconductor module 1000. On the bottom surface of the semiconductor module 1000, the heat dissipation base 1010 is provided with an opening 1016 for attaching a step jig.

[0175] The cooling fins 1210 are provided inside the cooling case 1220, extending along the y-axis direction and aligned in the x-axis direction. In this example, the cooling fins 1210 are straight fins having a rectangular shape with the y-axis direction as the longitudinal direction. The number and shape of the cooling fins 1210 are not limited to this example.

[0176] The coolant flow section 1230 is provided on the lower surface of the cooling case 1220. The coolant flow section 1230 circulates the coolant inside the cooling case 1220. In one example, the coolant flows into the cooling case 1220 from the coolant flow section 1230a and flows out of the cooling case 1220 from the coolant flow section 1230b. In FIG. 10C , the coolant flow section 1230a and the coolant flow section 1230b are provided at the ends of the cooling case 1220 in the longitudinal direction, but this is not limiting. The coolant flow section 1230a and the coolant flow section 1230b may be provided near the center or may be provided depending on the configuration of the semiconductor device 100.

[0177] Fig. 10D is a diagram showing an example of the gg cross section in Fig. 10C. The gg cross section is an xz cross section passing through the refrigerant flow section 1230a. The refrigerant flow section 1230 has a refrigerant flow section 1230a and a refrigerant flow section 1230b.

[0178] The refrigerant flow section 1230a is connected to an external device or the like and allows the refrigerant to flow into the cooling case 1220. The refrigerant flow section 1230a is provided with an opening 232a for allowing the refrigerant to flow in.

[0179] The refrigerant flow section 1230b is connected to an external device or the like, and allows the refrigerant to flow out from the cooling case 1220 to the outside. The refrigerant flow section 1230b is provided with an opening 232b for allowing the refrigerant to flow out. The refrigerant may circulate between the external device and the cooling section 1200.

[0180] The refrigerant flow part 1230 has a structure that protrudes from the bottom surface of the cooling case 1220. The refrigerant flow part 1230 may have a flange or a pipe for connection to an external device. The refrigerant flow part 1230 is manufactured to be aligned at an angle with the opening of the external device so that it can be inserted into the opening of the external device.

[0181] FIG. 10E is a schematic diagram showing the arrangement of semiconductor devices 100 in a semiconductor module 1000. The cooling unit 1200 of this example flows a coolant to cool the semiconductor device 100 from the positive side of the y-axis. The arrows in FIG. 10E indicate an example of a coolant flow path. The coolant is shown flowing from the positive side to the negative side of the y-axis along the cooling fin 1210 shown in FIG. 10C. The flow path from the coolant flow unit 1230a to the coolant flow unit 1230b may be configured so that the positive side of the y-axis of the first active unit 160 is upstream. That is, in this example, the first end X1 side of each semiconductor device 100 may be arranged so that the positive side of the x-axis. In another example, the first end X1 side of each semiconductor device 100 may be arranged so that the negative side of the x-axis of the first active unit 160 is upstream.

[0182] FIG. 10F is a schematic diagram showing a different arrangement of the semiconductor device 100 in the semiconductor module 1000. The cooling unit 1200 of this example flows a coolant so as to cool the semiconductor device 100 from the first end X1 side of the first active unit 160. The flow path from the coolant flow unit 1230a to the coolant flow unit 1230b may be configured so that the first end X1 side of the first active unit 160 is upstream. That is, in this example, the first end X1 side of each semiconductor device 100 may be arranged so that it is on the positive side of the y-axis. In this way, by cooling the semiconductor device 100 from the first end X1 side adjacent to the first diode unit 80-1, it is possible to suppress a temperature rise in each diode unit 80, particularly a temperature rise in each first diode unit 80-1.

[0183] FIG. 10G is a schematic diagram showing a different arrangement of the semiconductor device 100 in the semiconductor module 1000. The cooling unit 1200 of this example flows a coolant so as to cool the semiconductor device 100 from the second end X2 side of the first active unit 160. The flow path from the coolant flow unit 1230a to the coolant flow unit 1230b may be configured so that the second end X2 side of the first active unit 160 is upstream. That is, in this example, the semiconductor devices 100 may be arranged so that the second end X2 side is on the positive side of the y-axis. The semiconductor device 100 of this example has a second transistor unit 70-2 on the second end X2 side. In this way, by cooling the semiconductor device 100 from the second end X2 side adjacent to the second transistor unit 70-2, it is possible to suppress a temperature rise in each transistor unit 70, particularly a temperature rise in each second transistor unit 70-2.

[0184] FIG. 10H is a schematic diagram showing a different arrangement of semiconductor devices 100 in a semiconductor module 1000. This example differs from the example shown in FIG. 10F in that the first end X1 side of each semiconductor device 100 arranged on the negative side of the y-axis is arranged so that it faces the negative side of the y-axis. In FIG. 10F, the semiconductor device 100 arranged on the positive side of the y-axis is arranged so that the first end X1 side to which the first diode section 80-1 is adjacent is farther away from the semiconductor device 100 adjacent in the y-axis direction. However, in FIG. 10H, the semiconductor device 100 arranged on the negative side of the y-axis is also arranged so that the first end X1 side to which the first diode section 80-1 is adjacent is farther away from the semiconductor device 100 adjacent in the y-axis direction. In this way, by arranging the first end X1 side to which the first diode section 80-1 is adjacent so that it faces away from the adjacent semiconductor device, it is possible to suppress the temperature rise of each first diode section 80-1. The first end X1 of the semiconductor device 100 that is positioned on the most positive or negative side in the x-axis direction may be positioned so as to face outward (positive or negative) in the x-axis direction.

[0185] FIG. 10I is a schematic diagram showing a different arrangement of semiconductor devices 100 in a semiconductor module 1000. This example differs from the example shown in FIG. 10G in that the second end X2 side of each semiconductor device 100 arranged on the negative side of the y-axis is arranged on the negative side of the y-axis. In FIG. 10G, for the semiconductor device 100 arranged on the positive side of the y-axis, the second end X2 side to which the second transistor unit 70-2 is adjacent is arranged farther away from the semiconductor device 100 adjacent in the y-axis direction. In contrast, in FIG. 10I, for the semiconductor device 100 arranged on the negative side of the y-axis, the second end X2 side to which the second transistor unit 70-2 is adjacent is also arranged farther away from the semiconductor device 100 adjacent in the y-axis direction. In this way, by arranging the second end X2 side to which the second transistor unit 70-2 is adjacent farther away from the adjacent semiconductor device, it is possible to suppress the temperature rise of each second transistor unit 70-2. The second end X2 of the semiconductor device 100 that is positioned on the most positive or negative side in the x-axis direction may be positioned so as to face outward (positive or negative) in the x-axis direction.

[0186] The semiconductor device 100 having the arrangement shown in Figures 10E, 10F, and 10H is not limited to the example shown in Figures 1 and 5A, but may also be the examples shown in Figures 5B to 5D and 6 to 7B. The semiconductor device 100 having the arrangement shown in Figures 10G and 10I is not limited to the example shown in Figures 1 and 5A, but may also be the examples shown in Figures 6 to 7B. In the above examples, the semiconductor module 1000 has been described as having a cooling unit 1200 with cooling fins 1210 and a predetermined refrigerant flow path integrated with the wiring of the semiconductor device 100. However, in the present invention, a single or multiple packages with wiring of a single or multiple semiconductor devices 100 and arranged on a separately prepared cooler may also be treated as a semiconductor module.

[0187] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0188] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order.

[0189] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Accumulation region, 18...Drift region, 20...Buffer region, 21...Front surface, 22...Collector region, 23...Back surface, 24...Collector electrode, 25...Connection portion, 29...Extended portion, 30...Dummy trench portion, 31...Connection portion, 32...Dummy insulating film, 34...Dummy conductive portion, 38...Interlayer insulating film, 40...Gate trench portion, 39...Extended portion, 42...Gate insulating film, 41...Connection portion, 44...Gate conductive portion, 47...Peripheral gate runner, 48...Semiconductor gate runner, 49...Boundary, 50...Gate metal layer, 52...Emitter electrode, 54...Contact hole, 55...Contact hole, 56...Contact hole, 57...Contact hole, 60...Mesa portion, 70...Transistor portion, 72...Lifetime control region, 80...Diode portion, 82...Cathode region, 84...Resistance portion, 90...Transition region, 91...Boundary region, 92...Guard ring, 93...Outer edge portion, 94...Field plate, 100...Semiconductor device, 102...Edge, 160...First active portion, 161...Second active portion, 190...Peripheral region, 210...Current sense portion, 260...First active portion, 1000...Semiconductor module, 101 0...heat dissipation base, 1016...opening, 1020...insulating substrate, 1021...conductive plate, 1022...insulating plate, 1023...conductive plate, 1025...solder portion under substrate, 1040...metal wiring board, 1050...sealing resin, 1060...casing, 1062...main terminal, 1110...semiconductor cell, 1200...cooling portion, 1205...fin-integrated base, 1210...cooling fin, 1220...cooling case, 1230...refrigerant flow portion

Claims

1. A semiconductor device comprising a first active portion having a plurality of transistor portions and a plurality of diode portions arranged alternately in an arrangement direction, the semiconductor device comprising: a drift region of a first conductivity type provided in a semiconductor substrate; a plurality of trench portions extending in a predetermined trench extension direction on a front surface of the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of the first conductivity type provided on the front surface of the semiconductor substrate and having a doping concentration higher than that of the drift region; a contact region of a second conductivity type provided above the drift region and having a doping concentration higher than that of the base region; and a lifetime control region provided on the front surface of the semiconductor substrate closer to the center of the depth direction of the semiconductor substrate; wherein the first active portion has a first end and a second end opposite to the first end in the arrangement direction, and the plurality of diode portions have a first diode portion provided closest to the first end and a second diode portion provided closest to the second end, the plurality of transistor sections include a first transistor section provided closest to the first end and a second transistor section provided closest to the second end, and the first diode section is provided closer to the first end than the first transistor section.

2. The semiconductor device according to claim 1, wherein the second transistor section is provided closer to the second end than the second diode section.

3. The semiconductor device according to claim 1, wherein the second diode section is provided closer to the second end than the second transistor section.

4. The semiconductor device according to claim 3, wherein the areas of the first diode section and the second diode section on the front surface of the semiconductor substrate are different from the areas of the other diode sections.

5. The semiconductor device according to claim 3, wherein the areas of the first diode section and the second diode section on the front surface of the semiconductor substrate are smaller than the areas of the other diode sections.

6. The semiconductor device according to claim 3, wherein the areas of the first diode section and the second diode section on the front surface of the semiconductor substrate are larger than the areas of the other diode sections.

7. The semiconductor device according to claim 1, comprising a second active section separated from the first active section in a direction perpendicular to the arrangement direction and having the plurality of transistor sections and the plurality of diode sections arranged alternately in the arrangement direction, wherein the second active section has a third end and a fourth end opposite the third end in the arrangement direction, the third end being adjacent to the first end in the extension direction of the plurality of transistor sections and the plurality of diode sections, and the fourth end being adjacent to the second end in the extension direction, the plurality of diode sections in the second active section having a third diode section provided closest to the third end and a fourth diode section provided closest to the fourth end, the plurality of transistor sections in the second active section having a third transistor section provided closest to the third end and a fourth transistor section provided closest to the fourth end, and an arrangement of the plurality of transistor sections and the plurality of diode sections in the second active section differs from an arrangement of the plurality of transistor sections and the plurality of diode sections in the first active section.

8. The semiconductor device according to claim 7, wherein the fourth diode section is provided closer to the fourth end than the fourth transistor section.

9. The semiconductor device according to claim 7, wherein each transistor section has a transition region provided on the side of the adjacent diode section, and the number of said transition regions in said first active section is equal to the number of said transition regions in said second active section.

10. The semiconductor device according to claim 7, wherein a plurality of the first active sections are provided, and in the first active section, the second diode section is provided closer to the second end than the second transistor section, and in the second active section, the third transistor section is provided closer to the third end than the third diode section, and the fourth transistor section is provided closer to the fourth end than the fourth diode section.

11. The semiconductor device according to claim 10, wherein each transistor section has a transition region provided on the side of the adjacent diode section, and the number of said transition regions in said first active section is equal to the number of said transition regions in said second active section.

12. The semiconductor device according to claim 1, comprising: a well region of a second conductivity type provided on the front surface of the semiconductor substrate in a peripheral region surrounding the first active portion, the well region having a doping concentration higher than that of the base region; and a cathode region of a first conductivity type provided in each diode portion on the back surface of the semiconductor substrate, the cathode region having a doping concentration higher than that of the drift region, wherein, in the arrangement direction, the outer end of the cathode region of the first diode portion is located more inward than the inner end of the well region.

13. The semiconductor device according to claim 1, comprising: an interlayer insulating film provided above the front surface of the semiconductor substrate and having a plurality of contact holes; an emitter electrode provided above the interlayer insulating film; a well region of a second conductivity type provided on the front surface of the semiconductor substrate in a peripheral region surrounding the first active portion, the well region having a doping concentration higher than that of the base region; and cathode regions of a first conductivity type provided in each diode portion on the back surface of the semiconductor substrate, the cathode regions having a doping concentration higher than that of the drift region, wherein the emitter electrode is connected to the front surface of the semiconductor substrate in the first active portion and in the well region via the plurality of contact holes, and wherein the semiconductor device has a resistor portion provided from an outer edge of the well region to the outermost contact hole of the plurality of contact holes.

14. The semiconductor device according to claim 13, wherein the resistor portion comprises at least one of the plurality of trench portions.

15. The semiconductor device according to claim 1, further comprising: a well region of a second conductivity type provided on the front surface of the semiconductor substrate in a peripheral region surrounding the first active portion, the well region having a doping concentration higher than that of the base region; and a cathode region of a first conductivity type provided in each diode portion on the back surface of the semiconductor substrate, the cathode region having a doping concentration higher than that of the drift region, wherein the lifetime control region extends from the first diode portion to at least a portion of the peripheral region in the arrangement direction.

16. A semiconductor module comprising: a semiconductor device according to any one of claims 1 to 15; and a cooling section that cools the semiconductor device from the first end side.

17. A semiconductor module comprising the semiconductor device according to any one of claims 1 to 15 and another semiconductor device, wherein the semiconductor device is arranged so that the first end side of the semiconductor device does not face the other semiconductor device.

18. A semiconductor module comprising: a semiconductor device according to claim 2 or 7; and a cooling section that cools the semiconductor device from the second end side.

19. A semiconductor module comprising the semiconductor device according to claim 2 or 7 and another semiconductor device, wherein the semiconductor device is arranged so that the second end side of the semiconductor device does not face the other semiconductor device.

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