Memory and electronic device

Abstract

A memory and an electronic device. The memory comprises a plurality of bit-line functional groups, a plurality of memory cells, a first step structure and a second step structure which are located on a substrate, wherein the plurality of bit-line functional groups are arranged at intervals in a first direction perpendicular to the substrate, each bit-line functional group comprises a first bit line, a second bit line coupled to the first bit line, and a third bit line coupled to the first bit line, the first bit line extends in a second direction parallel to the substrate, the second bit line and the third bit line extend in a third direction parallel to the substrate, and the second direction intersects the third direction; and the second bit line and the plurality of memory cells are located on one side of the first bit line in the third direction, the third bit line, the first step structure and the second step structure are located on the other side of the first bit line in the third direction, and the first step structure and the second step structure are located on two opposite sides of the third bit line in the second direction. The stacked structure in the memory is compact, thereby facilitating an increase in the number of cuttable dies on a wafer.

Description

Memory and electronic devices Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory and electronic device. Background Technology

[0002] With the development of semiconductor technology, in order to further pursue the miniaturization of device structures within memory, the process has shifted from planar to three-dimensional, that is, arranging the various memory cells and related signal lines in three-dimensional space. This has become the main development direction of current memory structure research.

[0003] For example, in some three-dimensional memories, the stacked structure includes vertically stacked memory cells, vertically extending word lines, and horizontally extending and vertically stacked bit lines, which are externally connected by a stepped structure disposed at the edge of the stacked structure. For example, conductive steps are layered in the stepped structure so that the bit lines can be electrically connected to circuit structures (e.g., sense amplifiers) disposed outside the stacked structure through corresponding conductive steps and contact plugs located on the conductive steps.

[0004] However, as storage density continues to increase, the number of stacked layers needs to be increased, which will pose challenges to the arrangement of the ladder structure.

[0005] Summary of the Invention

[0006] According to a first aspect of the present disclosure, a memory is provided, comprising: a plurality of bit line functional groups, a plurality of memory cells, a first step structure, and a second step structure located on a substrate. The plurality of bit line functional groups are spaced apart along a first direction perpendicular to the substrate. Each bit line functional group includes a first bit line, a second bit line coupled to the first bit line, and a third bit line coupled to the first bit line. The first bit line extends along a second direction parallel to the substrate, and the second and third bit lines extend along a third direction parallel to the substrate, intersecting the third direction. The second bit line and the plurality of memory cells are located on one side of the first bit line in the third direction, and the third bit line, the first step structure, and the second step structure are located on the other side of the first bit line in the third direction, with the first step structure and the second step structure located on opposite sides of the third bit line in the second direction. The plurality of memory cells are respectively coupled to a corresponding second bit line. Each step structure in the first and second step structures includes a plurality of conductive steps extending along the second direction, and each conductive step is coupled to a corresponding third bit line.

[0007] In some embodiments, each of the first bit line, the second bit line, and the third bit line is in the shape of a ring.

[0008] In some embodiments, the first bit line, the second bit line, and the third bit line have the same material composition.

[0009] In some embodiments, the memory further includes: a first isolation pillar, a second isolation pillar, and a third isolation pillar located on the substrate; wherein the first bit line circumferentially surrounds the first isolation pillar, the second bit line circumferentially surrounds the second isolation pillar, and the third bit line circumferentially surrounds the third isolation pillar.

[0010] In some embodiments, the first isolation column, the second isolation column, and the third isolation column have the same material composition.

[0011] In some embodiments, each of the first and second stepped structures includes a plurality of conductive step groups, each of the conductive step groups including at least two conductive steps spaced apart along a first direction perpendicular to the substrate and having different extension lengths; in each of the conductive step groups, the conductive step with a shorter extension length is further away from the substrate than the conductive step with a longer extension length.

[0012] In some embodiments, each of the first and second stepped structures includes a first conductive step and a second conductive step, the first conductive step and the second conductive step having approximately the same extension length, the first conductive step being closer to the middle of the third bit line than the second conductive step, and the first conductive step being closer to the substrate than the second conductive step.

[0013] In some embodiments, the first stepped structure includes a third conductive step, and the second stepped structure includes a fourth conductive step. The orthographic projections of the third and fourth conductive steps on the substrate are arranged along the second direction. The third and fourth conductive steps have approximately the same extension length, and the third conductive step is further away from the substrate than the fourth conductive step.

[0014] In some embodiments, each conductive step in the first stepped structure is further away from the substrate than any conductive step in the second stepped structure.

[0015] In some embodiments, the memory further includes: a plurality of contact plugs, each located on the conductive step in a corresponding manner, wherein each contact plug is integrally formed with the corresponding conductive step.

[0016] In some embodiments, each of the second bit lines is provided with a memory cell coupled thereto on opposite sides in the second direction.

[0017] In some embodiments, each of the memory cells includes an access transistor and a capacitor, the access transistor being coupled to a corresponding second bit line, and the capacitor being coupled to the access transistor.

[0018] In some embodiments, the access transistor includes a first gate, a first active layer surrounding the first gate, and a first gate dielectric layer located between the first gate and the first active layer; the first gates opposite each other along the first direction are connected to form word lines, the first gate dielectric layers opposite each other along the first direction are connected to form an integral structure, and the first active layers opposite each other along the first direction are spaced apart from each other and respectively coupled to the corresponding second bit lines.

[0019] In some embodiments, the capacitor includes a first electrode, a second electrode surrounding the first electrode, and a capacitor dielectric layer located between the first electrode and the second electrode; the first electrodes opposite each other along the first direction are connected to form an integral structure, the capacitor dielectric layers opposite each other along the first direction are connected to form an integral structure, and the second electrodes opposite each other along the first direction are spaced apart from each other and respectively coupled to corresponding access transistors.

[0020] In some embodiments, the second bit line is configured as multiple lines.

[0021] In some embodiments, the memory further includes a plurality of selection transistors, wherein in each bit line function group, each of the second bit lines is coupled to the first bit line via a corresponding selection transistor.

[0022] In some embodiments, the selection transistor includes a second gate, a second active layer surrounding the second gate, and a second gate dielectric layer located between the second gate and the second active layer; the second gates opposite each other along the first direction are connected to form a selection control line, the second gate dielectric layers opposite each other along the first direction are connected to form an integral structure, and the second active layers opposite each other along the first direction are spaced apart from each other and coupled to the corresponding first bit line and the corresponding second bit line, respectively.

[0023] According to a second aspect of the present disclosure, an electronic device is provided, including a processor and a memory provided in any embodiment of the present disclosure. The memory is coupled to the processor.

[0024] In the memory provided in the embodiments of this disclosure, the extension length of the second bit line can be set according to the number of memory cells coupled thereto, the extension length of the first bit line can be set according to the number of second bit lines coupled thereto, and the extension length of the third bit line can be set according to the arrangement of the stepped structure coupled thereto. This makes the stacked structure in the memory more compact (i.e., its planar shape has a small circumscribed rectangle), which helps to increase the yield of memory chips per wafer (i.e., the number of dies per wafer, DPW). Attached Figure Description

[0025] Figure 1A is a schematic diagram of a partial planar structure of a three-dimensional memory;

[0026] Figure 1B is a schematic diagram of a cross section taken along line K1-K2 in Figure 1A;

[0027] Figure 2A is a partial planar structure diagram of a memory provided in some embodiments of this disclosure;

[0028] Figure 2B is a schematic diagram of a cross section taken along line A1-A2 in Figure 2A;

[0029] Figure 2C is a schematic diagram of a cross-section taken along line B1-B2 in Figure 2A;

[0030] Figure 2D is a schematic diagram of a cross section taken along line C1-C2 in Figure 2A;

[0031] Figure 3 is a schematic diagram of the structure of a storage unit provided in some embodiments of this disclosure;

[0032] Figure 4 is a partial planar structure diagram of another memory provided in some embodiments of this disclosure;

[0033] Figures 5A-5C are partial cross-sectional structural diagrams of some stages in the manufacturing process of a memory according to some embodiments of this disclosure;

[0034] Figures 6A-6F are partial cross-sectional structural diagrams of some stages in the manufacturing process of a memory according to some embodiments of this disclosure;

[0035] Figure 7 is a schematic block diagram of the structure of an electronic device provided in some embodiments of this disclosure. Detailed Implementation

[0036] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0037] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0038] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0039] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0040] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0041] In embodiments of this disclosure, the term "coupling" refers to the operative connection of two (or more) conductive structures to each other. Depending on actual needs, this may include, but is not limited to, the following: 1) two conductive structures are directly electrically connected; 2) two conductive structures are indirectly electrically connected (through other conductive structures); 3) although two conductive structures are not electrically connected (e.g., an insulating layer is provided between them), one of the two conductive structures can control the electrical performance of the other two conductive structures in response to an electrical signal, for example, a gate (or word line) is coupled to an active region (or channel region).

[0042] It should be noted that the technical solutions and technical features described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0043] Figure 1A is a schematic diagram of a planar structure of a three-dimensional memory, and Figure 1B is a schematic cross-sectional view taken along line K1-K2 in Figure 1A. As shown in Figures 1A and 1B, the three-dimensional memory includes multiple layers stacked sequentially along the vertical direction Z. Each layer includes a bit line BL extending along the horizontal direction X and multiple memory cells MC coupled to the bit line BL. For example, each memory cell may include a transistor coupled to the bit line BL and a capacitor coupled to the transistor.

[0044] As shown in Figures 1A and 1B, the three-dimensional memory also includes multiple word lines WL extending along the vertical direction Z, each word line WL being coupled to multiple vertically stacked memory cells MC. Specifically, each word line WL is coupled to a transistor in the multiple vertically stacked memory cells MC. As shown in Figures 1A and 1B, the word lines WL and memory cells MC are located on one side (the same side) of the bit line BL in the horizontal direction Y.

[0045] As shown in Figures 1A and 1B, the three-dimensional memory also includes a stepped structure located on the other side of the bit line BL in the horizontal direction Y. This stepped structure includes multiple conductive steps 210 that are coupled one-to-one with multiple bit lines WL at different levels. For example, as shown in Figures 1A and 1B, these multiple conductive steps 210 form two ascending steps (the distance from the conductive steps 210 to the substrate 100 gradually increases when viewed from the edge of the stepped structure towards the center). As shown in Figures 1A and 1B, the three-dimensional memory also includes contact plugs 220 located on each conductive step 210, so that the bit line BL can be electrically connected to a circuit structure (e.g., a sense amplifier) ​​disposed outside the stacked structure through the conductive steps 210 and the contact plugs 220.

[0046] Figure 1B also schematically illustrates a substrate 100, an etch stop layer 105, a first dielectric layer 110, a second dielectric layer 120, and a planarization layer 150, which can be referred to in the relevant description of the embodiments below.

[0047] In the three-dimensional memory shown in Figures 1A and 1B, considering the limited driving capability of the circuit structure, the extension length of the bit line BL is usually set according to the number of memory cells MC coupled to it. On the other hand, since the contact plug 220 is disposed on the conductive step 210, the area of ​​the conductive step 210 cannot be reduced indefinitely. That is to say, when the extension length of the bit line BL is determined, the number of conductive steps 210 in the above-mentioned stepped structure is limited, and thus the increase in the number of stacked structure layers will also be limited.

[0048] This disclosure provides a memory with at least some embodiments. The memory includes: a plurality of bit line functional groups, a plurality of memory cells, a first step structure, and a second step structure located on a substrate. The plurality of bit line functional groups are spaced apart along a first direction perpendicular to the substrate. Each bit line functional group includes a first bit line, a second bit line coupled to the first bit line, and a third bit line coupled to the first bit line. The first bit line extends along a second direction parallel to the substrate, and the second and third bit lines extend along a third direction parallel to the substrate, intersecting the third direction. The second bit line and the plurality of memory cells are located on one side of the first bit line in the third direction, and the third bit line, the first step structure, and the second step structure are located on the other side of the first bit line in the third direction, with the first step structure and the second step structure located on opposite sides of the third bit line in the second direction. The plurality of memory cells are respectively coupled to corresponding second bit lines. Each step structure in the first and second step structures includes a plurality of conductive steps extending along the second direction, and each conductive step is coupled to a corresponding third bit line.

[0049] In the memory provided in the embodiments of this disclosure, the extension length of the second bit line can be set according to the number of memory cells coupled thereto, the extension length of the first bit line can be set according to the number of second bit lines coupled thereto, and the extension length of the third bit line can be set according to the arrangement of the stepped structure coupled thereto. This makes the stacked structure in the memory more compact (i.e., its planar shape has a small circumscribed rectangle), which helps to increase the yield of memory chips per wafer (i.e., the number of dies per wafer, or DPW).

[0050] Figure 2A is a partial planar structure schematic diagram of a memory provided in some embodiments of this disclosure; Figure 2B is a cross-sectional schematic diagram taken along line A1-A2 in Figure 2A; Figure 2C is a cross-sectional schematic diagram taken along line B1-B2 in Figure 2A; Figure 2D is a cross-sectional schematic diagram taken along line C1-C2 in Figure 2A. It should be noted that, for clarity and simplicity, some insulating layers and / or dielectric layers in the memory are omitted in Figure 2A.

[0051] As shown in Figures 2A-2D, the memory includes multiple bit line functional groups (BLGs), multiple memory cells (MCs), a first ladder structure (SCa), and a second ladder structure (SCb) located on a substrate 100. The multiple bit line functional groups (BLGs) are arranged at intervals along a first direction Z perpendicular to the substrate 100. Each bit line functional group (BLG) includes a first bit line (BLa), a second bit line (BLb) coupled to the first bit line (BLa), and a third bit line (BLc) coupled to the first bit line (BLa). The first bit line (BLa), the second bit line (BLb), and the third bit line (BLc) in each bit line functional group (BLG) are located at the same level. The first bit line (BLa) extends along a second direction X parallel to the substrate 100, and the second bit line (BLb) and the third bit line (BLc) extend along a third direction Y parallel to the substrate 100. Both the second direction X and the third direction Y are perpendicular to the first direction Z, and the second direction X intersects the third direction Y. For example, the second direction X and the third direction Y are perpendicular to each other. For example, the orthographic projections of the first bit line BLa in different bit line functional groups BLG on the substrate 100 are basically overlapping, the orthographic projections of the second bit line BLb in different bit line functional groups BLG on the substrate 100 are basically overlapping, and the orthographic projections of the third bit line BLc in different bit line functional groups BLG on the substrate 100 are basically overlapping.

[0052] As shown in Figures 2A-2D, the second bit line BLb and multiple memory cells MC are located on one side of the first bit line BLa in the third direction Y. The third bit line BLc, the first ladder structure SCa and the second ladder structure SCb are located on the other side of the first bit line BLa in the third direction Y. The first ladder structure SCa and the second ladder structure SCb are located on opposite sides of the third bit line BLc in the second direction X.

[0053] As shown in Figures 2A-2D, multiple memory cells MC are coupled to corresponding second bit lines BLb. Each step structure in the first step structure SCa and the second step structure SCb includes multiple conductive steps ST extending along the second direction X, and each conductive step ST is coupled to the corresponding third bit line BLc.

[0054] For example, in the embodiments shown in Figures 2A-2D, the memory includes a stacked structure with 16 levels (T1-T16). It is understood that the stacked structure in the memory can have more or fewer levels. For example, the number of levels in the stacked structure in the memory can include, but is not limited to, 32, 64, 128, 256, etc. The arrangement of the conductive steps ST in Figures 2A-2D is described below with reference to Table 1.

[0055] Table 1. One arrangement of 16 conductive steps

[0056] For example, referring to Table 1 and Figures 2A-2D, the first step structure SCa includes conductive steps ST located in layers T1-T8, and the second step structure SCb includes conductive steps ST located in layers T9-T16. The natural number i in the table represents a conductive step ST located in the Ti layer, which is coupled to a third bit line BLc located in the same layer (i.e., the Ti layer).

[0057] Table 2 shows another arrangement of the conductive steps ST in Figures 2A-2D. The content of Table 2 can be understood in conjunction with the relevant descriptions in Table 1, and will not be repeated here. It is understood that in the embodiments shown in Figures 2A-2D, the arrangement of the conductive steps ST is not limited to that shown in Tables 1 and 2, and may include other suitable arrangements, as long as they are convenient for manufacturing.

[0058] Table 2. Another arrangement of the 16 conductive steps

[0059] Table 3. One arrangement of 32 conductive steps

[0060] Table 4. Another arrangement of the 32 conductive steps

[0061] It is understandable that when the number of stacked levels in the memory is other than a certain value, the arrangement of the conductive steps ST can be set with reference to the arrangement methods in Table 1 or Table 2. Tables 3 and 4 show one arrangement method for 32 conductive steps. The contents of Tables 3 and 4 can be understood in conjunction with the relevant explanations in Table 1, and will not be repeated here.

[0062] For example, in some embodiments, as shown in FIG2A, multiple second bit lines BLb can be configured. It should be noted that the number of second bit lines BLb and memory cells MC shown in FIG2A are illustrative and should not be regarded as a limitation of this disclosure.

[0063] For example, in some embodiments, as shown in FIG2A, each of the first bit line BLa, the second bit line BLb, and the third bit line BLc is loop-shaped. For example, the first bit line BLa can be a closed loop. For example, the second bit line BLb can be a closed loop or a non-closed loop; for example, in the case where the second bit line BLb is a non-closed loop, the opening of the non-closed loop is located at the end of the second bit line BLb away from the first bit line BLa. For example, the third bit line BLc can be a closed loop or a non-closed loop; for example, in the case where the second bit line BLb is a non-closed loop, the opening of the non-closed loop is located at the end of the third bit line BLc away from the first bit line BLa.

[0064] For example, in some embodiments, the first bit line BLa, the second bit line BLb, and the third bit line BLc have the same material composition. For example, the materials of the first bit line BLa, the second bit line BLb, and the third bit line BLc may include, but are not limited to, titanium nitride and / or tungsten. For example, the first bit line BLa, the second bit line BLb, and the third bit line BLc may be formed simultaneously.

[0065] For example, in some embodiments, as shown in Figures 2A-2D, the memory further includes a first isolation pillar 132, a second isolation pillar 134 and a third isolation pillar 136 located on the substrate 100, with a first bit line BL circumferentially surrounding the first isolation pillar 132, a second bit line BLb circumferentially surrounding the second isolation pillar 134, and a third bit line BLc circumferentially surrounding the third isolation pillar 136.

[0066] For example, in some embodiments, the first isolation pillar 132, the second isolation pillar 134, and the third isolation pillar 136 have the same material composition. For example, the materials of the first isolation pillar 132, the second isolation pillar 134, and the third isolation pillar 136 may include, but are not limited to, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or aluminum oxide. For example, the first isolation pillar 132, the second isolation pillar 134, and the third isolation pillar 136 may be formed simultaneously.

[0067] For example, in some embodiments, each of the first step structure SCa and the second step structure SCb includes multiple conductive step groups, each conductive step group including at least two conductive steps ST arranged at intervals along a first direction Z perpendicular to the substrate 100 and having different extension lengths (refer to the conductive steps in the same row under the "First Step Structure SCa" or "Second Step Structure SCb" column in Tables 1-4); in each conductive step group, the conductive step ST with a shorter extension length is further away from the substrate 100 than the conductive step ST with a longer extension length, so that contact plugs CT can be provided on both the conductive step ST with a shorter extension length and the conductive step ST with a longer extension length. For example, referring to Figures 2B and 2C, a conductive step ST with a shorter extension length located at layer T1 and a conductive step ST with a longer extension length located at layer T2 constitute a conductive step group, with the former being farther away from the substrate 100 than the latter; a conductive step ST with a shorter extension length located at layer T3 and a conductive step ST with a longer extension length located at layer T4 constitute a conductive step group, with the former being farther away from the substrate 100 than the latter; a conductive step ST with a shorter extension length located at layer T5 and a conductive step ST with a longer extension length located at layer T6 constitute a conductive step group, with the former being farther away from the substrate 100 than the latter; a conductive step ST with a shorter extension length located at layer T7 and a conductive step ST with a longer extension length located at layer T8 constitute a conductive step group, with the former being farther away from the substrate 100 than the latter; a conductive step ST with a shorter extension length located at layer T9 and a conductive step ST with a longer extension length located at layer T10 constitute a conductive step group, with the former being farther away from the substrate 100 than the latter; and so on.

[0068] For example, in some embodiments, each step structure in the first step structure SCa and the second step structure SCb includes a first conductive step and a second conductive step, the first conductive step and the second conductive step having approximately the same extension length, the first conductive step being closer to the middle of the third bit line BLc than the second conductive step, and the first conductive step being closer to the substrate 100 than the second conductive step. Exemplarily, referring to Table 1 and Figures 2A and 2B, the conductive step ST located at level T5 and the conductive step ST located at level T1 can be used as the first conductive step and the second conductive step, respectively, having approximately the same extension length, the former being closer to the middle of the third bit line BLc than the latter, and the former being closer to the substrate 100 than the latter; or, the conductive step ST located at level T7 and the conductive step ST located at level T3 can be used as the first conductive step and the second conductive step, respectively; or, the conductive step ST located at level T6 and the conductive step ST located at level T2 can be used as the first conductive step and the second conductive step, respectively; or, the conductive step ST located at level T8 and the conductive step ST located at level T4 can be used as the first conductive step and the second conductive step, respectively; and so on.

[0069] For example, in some embodiments, the first stepped structure SCa includes a third conductive step, and the second stepped structure SCb includes a fourth conductive step. The orthographic projections of the third and fourth conductive steps on the substrate 100 are arranged along the second direction X. The third and fourth conductive steps have approximately the same extension length, and the third conductive step is further away from the substrate than the fourth conductive step. Exemplarily, referring to Table 1 and Figures 2A and 2C, the conductive step ST located at level T1 and the conductive step ST located at level T9 can be used as the third and fourth conductive steps, respectively. The orthographic projections of the former and the latter on the substrate 100 are arranged along the second direction X. The former and the latter have approximately the same extension length, and the former is further away from the substrate 100 than the latter. Alternatively, the conductive step ST located at level T2 and the conductive step ST located at level T10 can be used as the third and fourth conductive steps, respectively. And so on.

[0070] For example, in some embodiments, referring to Table 1 (or Tables 2-4) and Figures 2A and 2C, each conductive step ST in the first stepped structure SCa is further away from the substrate 100 than any conductive step ST in the second stepped structure SCb.

[0071] It is understandable that the first-step structure SCa and the second-step structure SCb can be interchanged.

[0072] For example, in some embodiments, as shown in Figures 2A-2C, the memory further includes a plurality of contact plugs (CTs) located one-to-one on each conductive step (ST). For example, each contact plug CT is integrally formed with its corresponding conductive step (ST). For example, the contact plug CT and the conductive step (ST) have the same material composition. For example, the contact plug CT and the conductive step (ST) may include, but are not limited to, titanium nitride and / or tungsten.

[0073] For example, in some embodiments, as shown in Figures 2A and 2D, each second bit line BLb has a memory cell MC coupled to it on both opposite sides in the second direction X. For example, each memory cell MC includes an access transistor TR and a capacitor CAP, with the access transistor TR coupled to the corresponding second bit line BLb and the capacitor CAP coupled to the access transistor TR. It should be noted that the memory cell MC is not limited to DRAM (Dynamic Random Access Memory) memory cells. For example, the memory cell MC can also be a FeRAM (Ferroelectric Random Access Memory) memory cell, a PCM (Phase Change Memory) memory cell, an MRAM (Magnetic Random Access Memory) memory cell, etc. That is to say, the memory provided in the embodiments of this disclosure can be DRAM, FeRAM, PCM, MRAM, etc.

[0074] For example, in some embodiments, as shown in Figures 2A and 2D, the access transistor TR includes a first gate 143, a first active layer 141 surrounding the first gate 143, and a first gate dielectric layer 142 located between the first gate and the first active layer 141. That is, the access transistor TR can be a Channel-All-Around (CAA) transistor. The first gates 143, facing each other along the first direction Z, are connected to form a single structure (i.e., word lines 143). The first gate dielectric layers 142, facing each other along the first direction Z, are connected to form a single structure. The first active layers 141, facing each other along the first direction Z, are spaced apart from each other and coupled to their corresponding second bit lines BLb. For example, the material of the first active layer 141 can include, but is not limited to, polysilicon or metal oxides, such as indium gallium zinc oxide (IGZO). For example, the material of the first gate insulating layer 142 can include, but is not limited to, silicon oxide (SiO2) and / or a high-k dielectric. For example, the material of the word line 143 can include, but is not limited to, titanium nitride and / or tungsten.

[0075] For example, in some embodiments, as shown in Figures 2A and 2D, the capacitor CAP includes a first electrode 147, a second electrode 145 surrounding the first electrode 147, and a capacitor dielectric layer 146 located between the first electrode 147 and the second electrode 145; the first electrodes 147, facing each other along a first direction Z, are connected to form an integral structure (i.e., a common electrode 147), and the capacitor dielectric layers 146, facing each other along the first direction Z, are connected to form an integral structure; the second electrodes 145, facing each other along the first direction Z, are spaced apart from each other and respectively coupled to corresponding access transistors TR. For example, the material of the second electrode 145 may include, but is not limited to, titanium nitride and / or tungsten. For example, the material of the capacitor dielectric layer 146 may include, but is not limited to, silicon oxide (SiO2) and / or a high-k dielectric. For example, the material of the first electrode 147 may include, but is not limited to, titanium nitride and / or tungsten.

[0076] It should be noted that the structures of the memory cell MC (i.e., access transistor TR and capacitor CAP) shown in Figure 2D are schematic. Figure 3 is a schematic diagram of the structure of a memory cell (including access transistor and capacitor) provided in some embodiments of this disclosure. For example, as shown in Figure 3, in some embodiments, in the memory transistor TR of the memory cell MC, a portion of the cross-sectional shape of the first active layer 141 is "C" shaped, the first gate dielectric layer 142 conformally covers the first active layer 141, and the word line 143 includes branches extending laterally into the opening of the "C" shape of the first active layer 141. For example, as shown in Figure 3, in some embodiments, in the capacitor CAP of the memory cell MC, a portion of the cross-sectional shape of the second electrode 145 is "C" shaped, the capacitor dielectric layer 146 conformally covers the second electrode 145, and the common electrode 147 includes branches extending laterally into the opening of the "C" shape of the second electrode 145.

[0077] Figure 4 is a partial planar structure schematic diagram of another memory provided in some embodiments of this disclosure. For example, in some embodiments, based on the memory shown in Figure 2, the memory shown in Figure 4 may further include a plurality of selection transistors T0; in each bit line functional group BLG, each second bit line BLb is coupled to the first bit line BLa through a corresponding selection transistor T0.

[0078] For example, in some embodiments, the structure and material composition of the selection transistor T0 can be the same as those of the access transistor TR. For instance, the selection transistor T0 includes a second gate (referring to the aforementioned first gate 143), a second active layer surrounding the second gate (referring to the aforementioned first active layer 141), and a second gate dielectric layer located between the second gate and the second active layer (referring to the aforementioned first gate dielectric layer 142). That is, the selection transistor T0 can be a channel-all-around (CAA) transistor. The second gates, opposite each other along the first direction Z, are connected to form an integral structure (i.e., the selection control line), and the second gate dielectric layers, opposite each other along the first direction Z, are connected to form an integral structure. The second active layers, opposite each other along the first direction Z, are spaced apart from each other and coupled to the corresponding first bit line BLa and the corresponding second bit line BLb, respectively. For example, the selection transistor T0 and the access transistor TR can be formed simultaneously.

[0079] Figures 5A-5C are partial cross-sectional structural diagrams of some stages in the manufacturing process of a memory according to some embodiments of this disclosure. The manufacturing processes of the bit line functional group (BLG) and the memory cell (MC) will be briefly described below with reference to Figures 5A-5C.

[0080] For example, in some embodiments, the fabrication process of the bit line functional group (BLG) may include: referring to FIG5A, forming an etch stop layer 105, alternating layers of first dielectric layers 110 and second dielectric layers 120, and a mask layer 125 sequentially on a substrate 100, wherein adjacent first dielectric layers 110 and second dielectric layers 120 constitute a level; then, referring to FIG5B, forming an opening pattern on the mask layer 125, and etching the alternating layers of first dielectric layers 110 and second dielectric layers 120 to form a vertical opening VP, wherein the vertical opening VP exposes the upper surface of the etch stop layer 105; next, referring to FIG5C, laterally etching away portions of the second dielectric layers 120 of each level from the vertical opening VP to form a horizontal opening HP; subsequently, referring to the first bit line BLa and the first isolation pillar 132 in FIG2B, forming the first bit line BLa in the horizontal opening HP, and forming the first isolation pillar 132 filling the vertical opening VP. It is understandable that the formation process of the second bit line BLb and the second isolation pillar 134 is similar to that of the first bit line BLa and the first isolation pillar 132, and the formation process of the third bit line BLc and the third isolation pillar 136 is also similar to that of the first bit line BLa and the first isolation pillar 132, so it will not be repeated here. It is also understandable that in the process of forming the first bit line BLa, the second bit line BLb, and the third bit line BLc, the three need to satisfy the corresponding coupling relationship.

[0081] For example, in some embodiments, the fabrication process of the access transistor TR in the memory cell MC may include: referring to FIG5B, forming an opening pattern on a mask layer 125 and etching an alternately stacked first dielectric layer 110 and second dielectric layer 120 to form a vertical opening VP, wherein the vertical opening VP exposes the upper surface of the etch stop layer 105; then, referring to FIG5C, laterally etching away portions of the second dielectric layer 120 of each level from the vertical opening VP to form a horizontal opening HP; subsequently, referring to the first active layer 141, the first gate dielectric layer 142 and the word line WL in FIG2D or FIG3, forming the first active layer 141 in the horizontal opening HP, forming a first gate dielectric layer 142 conformally covering the first active layer 141, and forming a word line 143 filling the vertical opening VP. It is understood that if the second bit line BLb is formed before the first active layer 141, the horizontal opening on one side accommodating the first active layer 141 should expose the sidewall of the second bit line BLb so that the subsequently formed first active layer 141 can be coupled to the previously formed second bit line BLb. Similarly, if the second electrode 145 of the capacitor CAP is formed before the first active layer 141, the horizontal opening on the other side accommodating the first active layer 141 should expose the sidewall of the second electrode 145 so that the subsequently formed first active layer 141 can be coupled to the previously formed second electrode 145. It is also understood that the formation process of the select transistor T0 can be similar to the formation process of the access transistor TR, and will not be repeated here.

[0082] For example, in some embodiments, the manufacturing process of the capacitor CAP in the memory cell MC may include: referring to FIG5B, forming an opening pattern on a mask layer 125 and etching an alternately stacked first dielectric layer 110 and a second dielectric layer 120 to form a vertical opening VP, wherein the vertical opening VP exposes the upper surface of the etch stop layer 105; then, referring to FIG5C, laterally etching away portions of the second dielectric layer 120 of each level from the vertical opening VP to form a horizontal opening HP; subsequently, referring to the first active layer 141, the first gate dielectric layer 142 and the word line WL in FIG2D or FIG3, forming a second electrode 145 in the horizontal opening HP, forming a conformal capacitor dielectric layer 146 covering the second electrode 145, and forming a common electrode 147 filling the vertical opening VP. It is understood that if the first active layer 141 is formed before the second electrode 145, the horizontal opening on one side that accommodates the second electrode 145 should expose the sidewall of the first active layer 141 so that the second electrode 145 formed later can be coupled to the first active layer 141 formed earlier.

[0083] Figures 6A-6F are partial cross-sectional structural diagrams of some stages in the manufacturing process of a memory according to some embodiments of this disclosure. The manufacturing process of the first stepped structure SCa and the second stepped structure SCb will be briefly described below with reference to Figures 6A-6F.

[0084] For example, in some embodiments, the fabrication process of the first step structure SCa and the second step structure SCb may include: referring to Figures 6A and 6B, etching an alternately stacked first dielectric layer 110 and a second dielectric layer 120 to form a first initial step structure and a second initial step structure (after which the mask layer 125 may be removed); then, referring to Figures 6C and 6D, forming a planarization layer 150 covering the first initial step structure and the second initial step structure, and forming a vertical opening VO in the planarization layer 150, wherein the vertical opening VO exposes the second dielectric layer 120 at the top of each initial step; next, referring to Figures 6E and 6F, etching the second dielectric layer 120 at the top of each initial step from the vertical opening VO to form a horizontal opening HO, wherein the horizontal opening HO exposes the sidewall of the third bit line BLc; subsequently, referring to Figures 2 and 2C, forming a conductive step ST in the horizontal opening HO and a contact plug CT in the vertical opening VO, thereby obtaining the first step structure SCa and the second step structure SCb. For example, conductive material can be deposited to simultaneously form the conductive step ST and the contact plug CT.

[0085] For example, in embodiments of this disclosure, the substrate 100 may include, but is not limited to, a silicon substrate, a silicon-on-insulator substrate, etc. For example, the material of the etch stop layer 105 may include, but is not limited to, silicon carbide (SiC), silicon carbon oxide (SiCO), or silicon carbon nitride (SiCN). For example, the material of the first dielectric layer 110 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). For example, the material of the second dielectric layer 120 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). For example, the material of the mask layer 125 may include, but is not limited to, silicon nitride (SiN), silicon carbide (SiC), or silicon carbon nitride (SiCN). For example, the material of the planarization layer 150 may be the same as, but not limited to, the material of the first dielectric layer 110.

[0086] It is understandable that the materials of the etch stop layer 105, the first dielectric layer 110, and the second dielectric layer 120 are usually different from each other, and there is usually a certain etch selectivity between each pair. Similarly, the materials of the first dielectric layer 110, the second dielectric layer 120, and the mask layer 125 are usually different from each other, and there is usually a certain etch selectivity between each pair.

[0087] In the memory provided in the embodiments of this disclosure, the extension length of the second bit line BLb can be set according to the number of memory cells MC coupled thereto, the extension length of the first bit line BLa can be set according to the number of second bit lines BLb coupled thereto, and the extension length of the third bit line BLc can be set according to the arrangement of the stepped structures SCa and SCb coupled thereto. This makes the stacked structure in the memory more compact (i.e., its planar shape has a smaller circumscribed rectangle), which helps to increase the yield of memory chips per wafer (i.e., the number of dies per wafer, or DPW).

[0088] At least some embodiments of this disclosure also provide an electronic device. FIG7 is a schematic block diagram of an electronic device provided in some embodiments of this disclosure. As shown in FIG7, the electronic device 1 includes a processor 20 and a memory 10 coupled to each other, wherein the memory 10 is the memory provided in any of the foregoing embodiments.

[0089] For example, processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. Memory 10 may be configured to store data to be processed by processor 20 and / or data already processed by the processor.

[0090] For example, electronic device 1 includes, but is not limited to, mobile phones, tablets, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, in-vehicle devices, servers, workstations, etc.

[0091] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: Multiple bit line functional groups (BLG), multiple memory cells (MC), a first ladder structure (SCa), and a second ladder structure (SCb) are located on the substrate (100); The plurality of bit line functional groups are arranged at intervals along a first direction (Z) perpendicular to the substrate. Each bit line functional group includes a first bit line (BLa), a second bit line (BLb) coupled to the first bit line, and a third bit line (BLc) coupled to the first bit line. The first bit line extends along a second direction (X) parallel to the substrate, and the second bit line and the third bit line extend along a third direction (Y) parallel to the substrate. The second direction intersects with the third direction. The second bit line and the plurality of memory cells are located on one side of the first bit line in the third direction, the third bit line, the first step structure and the second step structure are located on the other side of the first bit line in the third direction, and the first step structure and the second step structure are located on opposite sides of the third bit line in the second direction. The plurality of memory cells are respectively coupled to the corresponding second bit line. Each of the first and second step structures includes a plurality of conductive steps (ST) extending along the second direction, and each conductive step is coupled to the corresponding third bit line.

2. The memory according to claim 1, characterized in that, Each of the first bit line, the second bit line, and the third bit line is ring-shaped.

3. The memory according to claim 1 or 2, characterized in that, The first bit line, the second bit line, and the third bit line have the same material composition.

4. The memory according to any one of claims 1-3, characterized in that, Also includes: The first isolation pillar (132), the second isolation pillar (134), and the third isolation pillar (136) are located on the substrate; Wherein, the first bit line circumferentially surrounds the first isolation post, the second bit line circumferentially surrounds the second isolation post, and the third bit line circumferentially surrounds the third isolation post.

5. The memory according to claim 4, characterized in that, The first isolation column, the second isolation column, and the third isolation column have the same material composition.

6. The memory according to any one of claims 1-5, characterized in that, Each of the first and second stepped structures includes multiple conductive step groups, and each conductive step group includes at least two conductive steps that are spaced apart along a first direction perpendicular to the substrate and have different extension lengths. In each of the conductive step groups, the conductive step with a shorter extension length is farther away from the substrate than the conductive step with a longer extension length.

7. The memory according to any one of claims 1-6, characterized in that, Each of the first and second stepped structures includes a first conductive step and a second conductive step, the first conductive step and the second conductive step having approximately the same extension length, the first conductive step being closer to the middle of the third bit line than the second conductive step, and the first conductive step being closer to the substrate than the second conductive step.

8. The memory according to any one of claims 1-7, characterized in that, The first stepped structure includes a third conductive step, and the second stepped structure includes a fourth conductive step. The orthographic projections of the third and fourth conductive steps on the substrate are arranged along the second direction. The third and fourth conductive steps have approximately the same extension length, and the third conductive step is further away from the substrate than the fourth conductive step.

9. The memory according to any one of claims 1-8, characterized in that, Each conductive step in the first stepped structure is further away from the substrate than any conductive step in the second stepped structure.

10. The memory according to any one of claims 1-9, characterized in that, Also includes: Multiple contact plugs (CTs) are located on the conductive steps in a one-to-one correspondence, wherein each contact plug is integrally formed with the corresponding conductive step.

11. The memory according to any one of claims 1-10, characterized in that, Each of the second bit lines has a memory cell coupled to it on both sides of the opposite side in the second direction.

12. The memory according to any one of claims 1-11, characterized in that, Each of the memory cells includes an access transistor (TR) and a capacitor (CAP), the access transistor being coupled to a corresponding second bit line and the capacitor being coupled to the access transistor.

13. The memory according to claim 12, characterized in that, The access transistor includes a first gate (143), a first active layer (141) surrounding the first gate, and a first gate dielectric layer (142) located between the first gate and the first active layer; The first gates opposite each other along the first direction are connected to form word lines (143), the first gate dielectric layers opposite each other along the first direction are connected to form an integral structure, and the first active layers opposite each other along the first direction are spaced apart from each other and respectively coupled to the corresponding second bit lines.

14. The memory according to claim 12 or 13, characterized in that, The capacitor includes a first electrode (147), a second electrode (145) surrounding the first electrode, and a capacitor dielectric layer (146) located between the first electrode and the second electrode; The first electrodes opposite each other along the first direction are connected to form an integral structure, the capacitor dielectric layers opposite each other along the first direction are connected to form an integral structure, and the second electrodes opposite each other along the first direction are spaced apart from each other and respectively coupled to the corresponding access transistors.

15. The memory according to any one of claims 1-14, characterized in that, The second bit line is set to multiple lines.

16. The memory according to claim 15, characterized in that, Also includes: Multiple selection transistors (T0), wherein, in each bit line functional group, each second bit line is coupled to the first bit line via a corresponding selection transistor.

17. The memory according to claim 16, characterized in that, The selection transistor includes a second gate, a second active layer surrounding the second gate, and a second gate dielectric layer located between the second gate and the second active layer; The second gates opposite each other along the first direction are connected to form a selection control line, the second gate dielectric layers opposite each other along the first direction are connected to form an integral structure, and the second active layers opposite each other along the first direction are spaced apart from each other and respectively coupled to the corresponding first bit line and the corresponding second bit line.

18. An electronic device, characterized in that, include: Processor (20); as well as The memory (10) according to any one of claims 1-17, wherein the memory is coupled to the processor.

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