Solar cell

Abstract

A solar cell, comprising: several first doped structures arranged at intervals, wherein the first doped structures are diffusion regions formed by inward diffusion from the back face of a silicon substrate; second doped structures alternately arranged with the first doped structures, wherein the second doped structures are located in areas recessed from the back face towards the front face of the silicon substrate, and the second doped structures are tunneling passivated contact structures, the doping type of the tunneling passivated contact structures being opposite to that of the diffusion regions; spacing regions, which are located between the first doped structures and the second doped structures; first electrodes, which are located on the back face of the first doped structures; and second electrodes, which are located on the back face of the tunneling passivated contact structures. By means of the optimization of the first doped structures and the second doped structures, first, the first doped structures are formed by diffusion; then, diffusion junctions in some areas are removed; after that, the tunneling passivated contact structures are deposited. This has high compatibility with the process flow of TOPCon cells and is suitable for industrial promotion.

Description

Solar cells

[0001] This invention is based on the following patent applications: Application No. 202410917310.3, filed on July 10, 2024; Application No. 202411097317.1, filed on August 9, 2024; Application No. 202411095535.1, filed on August 9, 2024; and Application No. 202411209958.1, filed on August 10, 2024. Applications filed on August 29, 2024; Application No. 202411205043.3, filed on August 29, 2024; Application No. 202411204726.7, filed on August 29, 2024; Application No. 202411204287.X, filed on August 29, 2024; and claiming priority to these Chinese patent applications, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of photovoltaics, and more particularly to a solar cell. Background Technology

[0003] Back contact (BC) batteries have both positive and negative electrodes located on the back of the battery, which reduces the current transmission path and lowers resistance; in addition, the absence of grid lines on the front improves light absorption efficiency and enhances battery performance.

[0004] However, despite the obvious advantages of BC batteries over other battery technologies, the structural design of the batteries affects the mass production process.

[0005] In view of this, it is necessary to provide an improved solar cell to solve the above-mentioned technical problems. Summary of the Invention

[0006] This invention provides a solar cell with an improved structural design on the back of the cell, which is beneficial for industrialization.

[0007] To achieve one of the above-mentioned objectives, the present invention adopts the following technical solution:

[0008] A solar cell includes: a plurality of first doped structures spaced apart, each first doped structure being a diffusion region formed by diffusion from the back side of a silicon substrate inward; a second doped structure alternately arranged with the first doped structures, the second doped structure being located in a region recessed from the back side to the front side of the silicon substrate, the second doped structure being a tunneling passivation contact structure with the opposite doping type to the diffusion region; a spacer region located between the first doped structures and the second doped structures; a first electrode located on the back side of the first doped structures; and a second electrode located on the back side of the tunneling passivation contact structure.

[0009] In one optional embodiment, the spacer region is recessed from the back side of the silicon substrate to the front side, and the recess depth of the spacer region at the location of the second doped structure is not less than the diffusion depth of the diffusion region.

[0010] In one optional embodiment, the width of the interval region is 10μm to 150μm.

[0011] In one optional embodiment, the spacer region is recessed from the back side of the silicon substrate to the front side, and the distance from the back surface of the spacer region to the back surface of the first doped structure is 1 μm to 20 μm.

[0012] In one optional embodiment, the distance from the back surface of the second doped structure to the front surface of the silicon substrate is not greater than the distance from the back surface of the first doped structure to the front surface of the silicon substrate.

[0013] In one optional embodiment, the dimension of the second doped structure in the thickness direction of the silicon substrate is not greater than the recess depth of the spacer region.

[0014] In one optional embodiment, the distance between the back surface of the first doped structure and the back surface of the second doped structure in the thickness direction of the silicon substrate is 1 μm to 10 μm.

[0015] In one optional embodiment, the diffusion region includes a gate line region and a non-gate line region, wherein the doping concentration of the gate line region is greater than the doping concentration of the non-gate line region, and the first electrode is in contact with the gate line region.

[0016] In one optional embodiment, the sheet resistance of the gate line region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the non-gate line region is 200 ohm / sq to 400 ohm / sq.

[0017] In one optional embodiment, the tunneling passivation contact structure includes at least one tunneling layer, a doped polysilicon layer located on the side of each tunneling layer facing away from the silicon substrate, and the second electrode is in contact with the doped polysilicon layer.

[0018] In one optional embodiment, the tunneling passivation contact structure includes n tunneling layers, n≥2, and the second electrode is in contact with at least one of the 2nd to nth doped polysilicon layers in the direction from the silicon substrate to the back side.

[0019] In one optional embodiment, the first doped structure is a P-type diffusion region, and the doped polysilicon layer is an N-type doped polysilicon layer; or the first doped structure is an N-type diffusion region, and the doped polysilicon layer is a P-type doped polysilicon layer.

[0020] In one alternative embodiment, the first doped structure is higher than the second doped structure in the direction from the front to the back of the silicon substrate.

[0021] In one optional embodiment, the height difference between the back surface of the first doped structure and the back surface of the second doped structure is 0.5 to 1.5 times the diffusion depth of the diffusion region.

[0022] In one optional embodiment, the base size of the surface of the spacer region facing the front side of the silicon substrate is 15μm~30μm, or the roughness of the surface of the spacer region facing the front side of the silicon substrate is not greater than 10nm.

[0023] In one optional embodiment, the back surface of the solar cell, excluding the spacer area, has a textured surface.

[0024] In an optional embodiment, the surface of the spacer region has a passivation film layer, the passivation film layer including a first charge film layer in contact with the silicon substrate and a second charge film layer located on the side of the first charge film layer away from the silicon substrate, the first charge film layer having the same charge type as the silicon substrate, and the first charge film layer and the second charge film layer having opposite charge types.

[0025] In one optional implementation, the thickness of the first charge film layer is less than the thickness of the second charge film layer.

[0026] In one optional embodiment, if the silicon substrate is N-type silicon, then the first charge film layer is a negative charge film layer and the second charge film layer is a positive charge film layer; or if the silicon substrate is P-type silicon, then the first charge film layer is a positive charge film layer and the second charge film layer is a negative charge film layer.

[0027] In one optional embodiment, the negative charge film layer includes a silicon oxide film layer and an aluminum oxide film layer located on the side of the silicon oxide film layer opposite to the silicon substrate.

[0028] In one optional embodiment, the thickness of the silicon oxide film is 0.5 nm to 2 nm, and the thickness of the aluminum oxide film is 1 nm to 20 nm.

[0029] In one optional embodiment, the positively charged film layer is selected from at least one of SiNx film layers or SiOxNy film layers.

[0030] In one optional embodiment, the thickness of the positively charged film layer is 10 nm to 100 nm.

[0031] The beneficial effects of this invention are as follows: The solar cell of this invention, by placing both the first and second electrodes on the back side, eliminates the obstruction of the front side by metal electrodes, resulting in a large light-receiving area, high light conversion efficiency, and improved cell efficiency. Furthermore, the first doped structure is a diffusion region formed by the diffusion of dopant from the back side of the silicon substrate inwards, while the second doped structure is located in a region recessed from the back side of the silicon substrate towards the front side. The second doped structure is a tunneling passivation contact structure, which can be formed by first diffusing the first doped structure, then removing a portion of the diffusion junction, and finally depositing the tunneling passivation contact structure. This design exhibits high compatibility with the TOPCon cell process flow and is suitable for industrialization. Attached Figure Description

[0032] Figure 1 is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;

[0033] Figure 2 is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0034] Figure 3 is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0035] Figure 4 is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0036] Figure 5 is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0037] Figure 6 is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0038] Figure 7 is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0039] Figure 8 is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;

[0040] Figure 9 is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention;

[0041] Figure 10 is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;

[0042] Figure 11 is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;

[0043] Figure 12 is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;

[0044] Figure 13 is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;

[0045] Figure 14 is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention. Embodiments of the present invention

[0046] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0047] In the various figures of this invention, for ease of illustration, some dimensions of structures or parts may be exaggerated relative to other structures or parts; therefore, only the basic structure of the subject matter of this invention is used to illustrate the invention.

[0048] Please refer to Figures 1 to 14, which show a preferred embodiment of the solar cell 100 of the present invention. It includes a silicon substrate 1, a first doped structure 2 located on the back side of the silicon substrate 1, a second doped structure 3 located on the back side of the silicon substrate 1, a spacer region 4 located between the first doped structure 2 and the second doped structure 3, a first electrode 91 located on the back side of the first doped structure 2, and a second electrode 92 located on the back side of the second doped structure 3.

[0049] The silicon substrate 1 is selected from N-type silicon wafers with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 2 Ω·cm to 3.5 Ω·cm. In an optional embodiment, the front side of the silicon substrate 1 has a textured structure, which has a good light-limiting effect and can further improve the light utilization rate.

[0050] The first doped structure 2 and the second doped structure 3 have opposite doping types, one being a P-type doped structure and the other an N-type doped structure. The first doped structure 2 and the second doped structure 3 are alternately arranged, and the two regions are separated by an isolation region 4. By placing both the first doped structure 2 and the second doped structure 3 on the back side of the solar cell, the current transport path between the P-type and N-type doped structures can be reduced, thus lowering the resistance. Furthermore, by placing both the first electrode 91 and the second electrode 92 on the back side, there are no metal electrodes obstructing the front side, resulting in a larger light-receiving area and improved cell efficiency.

[0051] The first doped structure 2 is a diffusion region formed by the diffusion of dopant sources directly inward from the back side of the silicon substrate 1. The diffusion depth of the dopant source along the thickness direction of the silicon substrate 1 is called the junction depth.

[0052] In the first embodiment, please refer to Figures 1 to 8. The first doped structure 2 is a P-type diffusion region, and the second doped structure 3 is an N-type tunneling passivation contact structure.

[0053] The first doped structure 2 is a P-type doped structure, specifically a P-type diffusion region formed by the inward diffusion of P-type dopant sources from the back side of the silicon substrate 1. In this case, the PN junction is located within the silicon substrate 1, which facilitates carrier separation and collection, thereby improving battery efficiency. P-type dopant sources include, but are not limited to, boron, aluminum, and gallium.

[0054] As shown in Figures 1, 3, 5, and 7, the doping concentration is consistent throughout the diffusion region.

[0055] As shown in Figures 2, 4, 6, and 8, the first doped structure 2 includes a gate line region 21 and a non-gate line region 22, wherein the doping concentration of the gate line region 21 is greater than the doping concentration of the non-gate line region 22.

[0056] The high doping concentration of the gate region 21 forms an ohmic contact with the first electrode 91, reducing the series resistance of the battery and increasing the fill factor FF. Conversely, the low doping concentration of the non-gate region 22 reduces the probability of carrier surface recombination, decreasing the reverse saturation current and thus increasing the open-circuit voltage Voc and short-circuit current Isc. Furthermore, the gate region 21 and the non-gate region 22 can create a P++ / P+ or N++ / N+ high-low junction laterally, which is beneficial for improving carrier collection and further increasing the short-circuit current Isc.

[0057] In an optional embodiment, the doping concentration of the gate region 21 is 5E18cm⁻¹. -3 ~1E20cm -3 The sheet resistance is 80 ohm / sq to 130 ohm / sq; the sheet resistance of the non-gate region 22 is 200 ohm / sq to 400 ohm / sq.

[0058] The second doped structure 3 is located in a region recessed from the back side to the front side of the silicon substrate 1, and the second doped structure 3 is a tunneling passivation contact structure. The tunneling passivation contact structure includes at least one tunneling layer 31 and a doped polysilicon layer 32 located on the side of each tunneling layer 31 facing away from the silicon substrate 1. The second electrode 92 is in contact with the doped polysilicon layer 32.

[0059] The tunneling layer 31 is selected from silicon oxide (SiOx) or silicon carbide (SiC), with a thickness of 1nm to 3nm, preferably 1nm to 2.5nm, more preferably 1nm to 2nm or 1.5nm to 2.5nm. The thickness of the tunneling layer 31 is optimized according to its density. When the tunneling layer 31 is SiOx, the thickness is between 1.4nm and 2.3nm; when the tunneling layer 31 is SiC, the film is more dense, with a thickness of 1nm to 1.8nm.

[0060] The doped polysilicon layer 32 is an N-doped polysilicon layer; the following explanation will use phosphorus doping as an example. The doping concentration is 1E19cm⁻¹. -3 ~1E21cm -3 1E20cm is preferred -3 ~9E20cm -3 The thickness is 80nm~120nm, and can be set to 90nm, 85nm, 100nm, 105nm, 110nm, or 115nm.

[0061] In one embodiment, the passivation contact structure includes a tunneling layer 31 and a doped polysilicon layer 32. The second electrode 92 is in contact with the doped polysilicon layer 32, thereby avoiding direct contact between the second electrode 92 and the silicon substrate 1 and improving battery efficiency.

[0062] In another embodiment, the tunneling passivation contact structure includes n tunneling layers 31 and a doped polycrystalline silicon layer 32 located on the side of each tunneling layer 31 facing away from the silicon substrate 1, where n ≥ 2. The multiple tunneling layers 31 can hinder the inward diffusion of metallic silver, preventing it from contacting the silicon substrate and forming a silicon-silver alloy.

[0063] In the direction from the silicon substrate 1 toward the back side, the second electrode 92 is in contact with at least one of the 2nd to nth doped polysilicon layers 32; that is, the second electrode 92 is in contact with part or all of the other doped polysilicon layers 2 except for the doped polysilicon layer 32 closest to the silicon substrate 1, and will not reach the innermost doped polysilicon layer, thus avoiding direct contact between silver and the silicon substrate.

[0064] In one embodiment, the passivation contact structure includes two doped polysilicon layers, and the second electrode 92 contacts only the doped polysilicon layer 32 furthest from the silicon substrate 1.

[0065] In another embodiment, the passivation contact structure includes three doped polysilicon layers 32, and the second electrode 92 is in contact only with the outermost doped polysilicon layer 32, or the second electrode 92 is in contact only with the first and second doped polysilicon layers 32 counted from the outside in.

[0066] In the second embodiment, please refer to Figures 9-14. The first doped structure 2 is an N-type diffusion region. The main difference between the N-type diffusion region and the P-type diffusion region is that the N-type diffusion region is formed by the diffusion of N-type dopant sources from the back side of the silicon substrate 1 inward. N-type dopant sources include, but are not limited to, phosphorus, arsenic, and antimony.

[0067] The second doped structure 3 is a P-type doped structure. The only difference between the P-type doped structure and the N-type doped structure is that the doped polysilicon layer 32 is a P-type doped polysilicon layer, and the doping source is a P-type doping source.

[0068] In addition, the width of the P-type doped structure is greater than that of the N-type doped structure, and the area of ​​the PN junction region is greater than that of the N-N+ region, which is beneficial to the generation, separation and collection of photogenerated carriers and can improve battery efficiency.

[0069] In one embodiment, the width of the P-type doped structure 2 is 1.5 to 2 times the width of the N-type doped structure.

[0070] Additionally, please refer to Figures 1-8 and 12-14. Along the direction from the front to the back of the silicon substrate 1, the first doped structure 2 is higher than the second doped structure 3. By having the first doped structure 2 higher than the second doped structure 3, on the one hand, the surface area of ​​the entire back side is increased, thus expanding the light-receiving area; on the other hand, since the back and sides of the first doped structure 2 are exposed outward, the light-absorbing area of ​​the first doped structure 2 is increased, enabling it to generate and successfully collect more charge carriers, thereby improving battery efficiency.

[0071] Of course, as shown in Figures 9 to 11, the second doped structure 3 is higher than the first doped structure 2 along the direction from the front to the back of the silicon substrate 1, which can also increase the back surface area, increase the back light-receiving area in the bifacial module, and improve the battery efficiency.

[0072] Preferably, as shown in Figures 1 to 11, the P-type doped structure is higher than the N-type doped structure. The greater the height difference, the larger the area of ​​the exposed P-type diffusion region, which is more conducive to light absorption and the higher the efficiency of the battery.

[0073] Please refer to Figures 1-8. The first doped structure 2 is a P-type diffusion region, and the first doped structure 3 is an N-type passivation contact structure. The height difference between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 0.5 to 1.5 times the diffusion depth of the P-type diffusion region.

[0074] Please refer to Figures 9-11. The first doped structure 2 is an N-type diffusion region, and the second doped structure 3 is a P-type passivation contact structure. The height difference between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 0.5 to 1.5 times the thickness of the P-type passivation contact structure.

[0075] The isolation region 4 separates the first doped structure 2 and the second doped structure 3 to prevent leakage problems caused by contact between the two.

[0076] In one embodiment, the width of the spacer region 4 is 10 μm to 150 μm. Under the premise of isolating leakage current, the narrower the width of the spacer region 4, the less recombination of charge carriers in that region, and the higher the battery efficiency. Preferably, the width is 50 μm to 100 μm.

[0077] In this invention, the spacer region 4 is recessed from the back side of the silicon substrate 1 to the front side, and the recessed depth of the spacer region 4 at the location of the second doped structure 2 is not less than the diffusion depth of the diffusion region. This design ensures that the spacer region 4 completely isolates the first doped structure 2 and the second doped structure 3.

[0078] In one embodiment, the recess depth at the location of the second doped structure 2 is less than the recess depth of the spacer region 4, which completely isolates the diffusion region and the passivation contact structure in both the extension direction and the thickness direction of the silicon substrate 1, resulting in a good isolation effect.

[0079] The distance from the back surface of the spacer region 4 (the side of the spacer region 4 facing the front of the silicon substrate 1) to the back surface of the first doped structure 2 is called the depth of the spacer region 4. The depth of the spacer region 4 is 1 μm to 20 μm, preferably 5 μm to 10 μm. Alternatively, the depth of the spacer region 4 preferably exceeds the diffusion depth of the diffusion region, ensuring that the spacer region 4 completely isolates the P-type doped structure 2 and the N-type doped structure 3. In one embodiment, the depth of the spacer region 4 is 1 to 1.5 times the diffusion depth of the P-type diffusion region.

[0080] In one embodiment, the distance from the back surface of the second doped structure 3 to the front surface of the silicon substrate 1 is not greater than the distance from the back surface of the first doped structure 2 to the front surface of the silicon substrate 1. Alternatively, the dimension of the second doped structure 3 in the thickness direction of the silicon substrate 1 is not greater than the recess depth of the spacer region 4.

[0081] With this design, the first doped structure 2 and the second doped structure 3 form a height difference on the back side of the silicon substrate 1, which increases the surface area of ​​the back side, that is, increases the light absorption area, and can improve the efficiency of the solar cell.

[0082] In one embodiment, the distance between the back surface of the first doped structure 2 and the back surface of the second doped structure 3 in the thickness direction of the silicon substrate 1 is 1 μm to 10 μm. This not only increases the surface area of ​​the back surface but also creates a stepped shape, allowing light to undergo multiple reflections on the back surface, which is more conducive to light absorption. Preferably, the height difference is 4 μm to 10 μm.

[0083] Alternatively, the surface of spacer region 4 facing the silicon substrate 1 has a textured structure, which can improve light absorption in this area and help improve cell efficiency; moreover, the overall cell fabrication process is simple. Alternatively, the back surface of spacer region 4 facing the silicon substrate 1 can be planar, which significantly reduces dangling bonds compared to a textured structure, lowering the probability of carrier recombination and thus improving cell efficiency. Furthermore, the planar spacer region 4 facilitates the subsequent formation of a continuous passivation film layer, further achieving a good passivation effect, and can improve cell efficiency by 0.1~0.2% while keeping other structures unchanged.

[0084] It should be noted that "the surface is planar" means that the base size of the surface of the spacer region 4 is 15μm~30μm, or the surface roughness of the spacer region 4 is comparable to that of the planar silicon wafer, generally not exceeding 10nm.

[0085] Based on the planar spacer region 4, a continuous passivation film can be formed on its surface, thereby improving the passivation effect in the region where spacer region 4 is located. Under the premise that other structures remain unchanged, the battery efficiency can be improved by 0.1%~0.2%.

[0086] Based on the above arbitrary structural design, the area outside the middle partition region 4 on the back of the battery has a textured surface, which can improve light absorption and increase battery efficiency. Maintaining the surface of the partition region 4 as a flat surface while having a textured surface in other areas on the back, and even on the front, is a technical challenge. This invention will be described in the preparation method below.

[0087] In addition, the back side of the solar cell 100 is provided with a back passivation layer 5 and a back anti-reflection layer 6. The first electrode 91 passes through the back anti-reflection layer 6 and the back passivation layer 5 and contacts the grid line region 21. The second electrode 92 passes through the back anti-reflection layer 6 and the back passivation layer 5 and contacts the doped polycrystalline silicon layer 32.

[0088] In one embodiment, the back passivation layer 5 is preferably an alumina layer, providing excellent field passivation for the first doped structure 2 and excellent interface passivation for the second doped structure 3. In this invention, the thickness of the back passivation layer 5 is preferably 3 nm to 6 nm.

[0089] In another embodiment, the back passivation layer 5, particularly the back passivation layer 5 at the spacer region 4, includes a first charge film layer in contact with the silicon substrate 1 and a second charge film layer located on the side of the first charge film layer facing away from the silicon substrate 1. The first charge film layer has the same charge type as the silicon substrate 1, and the first and second charge film layers have opposite charge types.

[0090] The surface of the silicon substrate 1 has dangling bonds. By using a first charge film layer with the same charge for interface passivation and then using a second charge film layer with the opposite charge for field passivation, the passivation effect of the entire passivation film layer can be improved.

[0091] In this invention, the silicon substrate is an N-type silicon wafer, the first charge film layer is a negative charge film layer, and the second charge film layer is a positive charge film layer. Those skilled in the art will understand that if the silicon substrate is a P-type silicon wafer, the first charge film layer is a positive charge film layer, and the second charge film layer is a negative charge film layer.

[0092] In one embodiment, the negative charge film layer includes a silicon oxide film layer and an aluminum oxide film layer located on the side of the silicon oxide film layer facing away from the silicon substrate. The silicon oxide film layer has a higher density than the aluminum oxide film layer, therefore, forming the silicon oxide film layer first on the surface of the spacer region 4 and then forming the aluminum oxide film layer can achieve the best passivation effect.

[0093] The thickness of the silicon oxide film is 0.5nm to 2nm (e.g., 1nm), and the thickness of the aluminum oxide film is 1nm to 20nm.

[0094] In one embodiment, the positively charged film layer is selected from at least one of SiNx film layers or SiOxNy film layers.

[0095] The thickness of the positively charged film is 10 nm to 100 nm.

[0096] Furthermore, the thickness of the first charge film layer is less than the thickness of the second charge film layer. The first charge film layer only needs to achieve interface passivation; if it is too thick, it will affect the formation of field passivation by the second charge film layer. In addition, the second charge film layer needs to overcome the influence of the first charge film layer in the middle to form a field passivation effect, so it needs to be set to a relatively large thickness.

[0097] In one embodiment, the thickness of the first charge film layer is 0.5 nm to 25 nm, preferably 2 nm to 10 nm. The thickness of the second charge film layer is 10 nm to 100 nm, preferably 20 nm to 50 nm.

[0098] With the surface of the spacer region 4 being planar, the passivation effect in this region can be optimized to the best state by combining it with a passivation film layer.

[0099] The back antireflection layer 6 is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm~130nm, which reduces reflectivity and improves light utilization.

[0100] In an optional embodiment, the solar cell 100 further includes a front passivation layer 7 and a front antireflection layer 8 sequentially disposed on the front side of the silicon substrate 1 to passivate surface defects on the front side. In this invention, the front passivation layer 7 and the back passivation layer 5 are made of the same material and have the same thickness, and can be deposited together; the front antireflection layer 8 and the back antireflection layer 6 are made of the same material and have the same thickness, and can also be deposited in the same process.

[0101] In the solar cell 100 of the present invention, the first doped structure 2 is a diffusion region formed by the diffusion of dopant from the back side of the silicon substrate 1 inward, and the second doped structure 3 is located in a region recessed from the back side to the front side of the silicon substrate 1, and the second doped structure 3 is a tunneling passivation contact structure. This structural design allows for the first doped structure 2 to be formed by diffusion on the back side of the silicon substrate, followed by the removal of a portion of the diffusion junction, and then the deposition of the tunneling passivation contact structure. It exhibits high compatibility with the process flow of TOPCon cells and is suitable for industrialization.

[0102] The following, with reference to Figures 1 to 8, provides a first method for fabricating a solar cell, taking the first doped structure 2 as a boron-doped P-type diffusion region and the second doped structure as a phosphorus-doped N-type tunneling passivation contact structure as an example.

[0103] S1 uses a boron diffusion process to form a diffusion region (boron junction) and a BSG layer on the back side of silicon substrate 1.

[0104] S11 First, a boron source is formed on the entire back side of the silicon substrate 1. The silicon substrate 1 is fixed in a quartz boat and placed in a tube furnace. The boron source and oxygen are introduced to deposit a layer of boron source (or a through-source) on the back side of the silicon substrate 1. The boron source is boron trichloride (BCl3), with a flow rate of 90 sccm to 150 sccm, an oxygen flow rate of 100 sccm to 500 sccm reacting with BCl3, and an oxygen flow rate of 1 slm to 10 slm for forming the oxide layer; or, the boron source is boron tribromide (BBr3), with a boron trichloride flow rate of 90 sccm to 150 sccm, an oxygen flow rate of 100 sccm to 500 sccm reacting with BBr3, and an oxygen flow rate of 1 slm to 10 slm for forming the oxide layer.

[0105] S12 forms a heavily doped gate region 21 by laser scanning in the gate region of the first doped structure 2. Laser parameters: laser gas power is 120W, using 63% power for wafer fabrication; laser frequency is 100kHz, and scan speed is 25m / s.

[0106] S13 then diffuses in the non-gate region.

[0107] In one optional embodiment, the heavily doped silicon substrate 1 is placed in a tube furnace, and oxygen is introduced into the tube furnace at a temperature of 950°C to 1000°C and an oxygen flow rate of 10 slm to 15 slm. At the high temperature, boron in the non-gate region diffuses inward to form a non-gate region 22, while a BSG layer is formed on the entire surface.

[0108] In one optional embodiment, the sheet resistance after depositing the boron source is 120 ohm / sq to 170 ohm / sq; after laser scanning, the doping concentration of the gate region 21 is 5E18cm. -3 ~1E20cm-3 The sheet resistance is 80 ohm / sq to 130 ohm / sq; after high-temperature oxidation, the sheet resistance of the non-gate region 22 is 200 ohm / sq to 400 ohm / sq.

[0109] In this invention, the diffusion depth of boron (boron junction depth) is 0.5 μm to 1.0 μm. By controlling the diffusion depth of boron, this invention optimizes the passivation effect and metal contact in the P-region. The boron diffusion depth is designed to be 0.5 μm to 1.0 μm, which ensures that the dark saturation current density J0 in the diffusion region is 2 fA / cm². 2 ~4fA / cm 2 With dark saturation current density J0 at 1fA / cm 2 ~3fA / cm 2 The second doped structure 3 achieves a balanced passivation effect. If the boron diffusion depth exceeds 1 μm, Auger recombination will increase, leading to a decrease in silicon wafer lifetime. If the boron diffusion depth is less than 0.5 μm, Ag may puncture the PN junction region during metal electrode fabrication. This invention uses a boron junction depth of 0.5 μm to 1.0 μm, which offers advantages in both bifaciality and efficiency of the battery.

[0110] S2 removes the BSG layer and boron junction outside the first doped structure 2:

[0111] S21 laser grooving removes the BSG layer outside the first doped structure 2.

[0112] The laser grooving mentioned in this invention can be selectively performed using one of the following methods: In one embodiment, an ultraviolet picosecond laser is used for laser grooving, with a spot power of 3W~20W, a spot diameter of 100μm~150μm, a frequency of 500kHz~600kHz, and a scan speed of 40m / s~80m / s. In another embodiment, a green picosecond laser is used for laser grooving, with a spot power of 5W~50W, a spot diameter of 100μm~500μm, a frequency of 500kHz~600kHz, and a scan speed of 40m / s~80m / s.

[0113] S22 removes the boron junction outside the first doped structure 2:

[0114] First, the BSG layers on the front and side surfaces of silicon substrate 1 are removed using an HF solution. In an optional embodiment, this step is performed in a chain machine.

[0115] In removing mask layers such as BSG, PSG, and silicon oxide layers formed by plating or deposition, the present invention can use an HF solution with a volume concentration of 5% to 20% or 0.01 mol / L to 0.03 mol / L, which will not be elaborated further below.

[0116] The material is then polished to remove the boron junction outside the first doped structure 2, as well as the boron junction wrapped around the front side. The boron junction and BSG layer of the first doped structure 2 are retained. In an optional embodiment, this step is performed in a tank mill.

[0117] This step removes the boron junction outside the first doped structure 2, as well as the BSG layers on the front and sides and the boron junction around the front. The process is simple and lays a good foundation for subsequent processes.

[0118] S3 Backside Tunneling Passivation Contact Structure and Mask Layer: A tunneling layer 31 and a phosphorus-doped amorphous silicon layer are grown on the entire backside using PECVD in-situ doping, with a mask layer grown on the outermost side. Here, multiple alternating layers of tunneling layers 31 and phosphorus-doped amorphous silicon layers are deposited to form a tunneling passivation contact structure including multiple tunneling layers 31 and doped polycrystalline silicon layers 32.

[0119] In one embodiment, the tunneling layer 31 is SiOx, and its thickness is preferably 1.4 nm to 2.3 nm.

[0120] In another embodiment, the tunneling layer 31 is SiC, which is more dense, and the thickness is preferably 1nm~1.8nm.

[0121] The thickness of the N-poly layer is preferably 80nm~120nm.

[0122] The mask layer is preferably a silicon oxide layer, with a thickness controlled in the range of 10nm to 50nm.

[0123] S4 uses a high-temperature annealing furnace, and the annealing temperature can be matched according to the tunneling conditions. The tunneling layer 31 has a large thickness, requiring a high annealing temperature. In an optional embodiment, the annealing temperature is 850℃~950℃, which can be optimally matched with conventional tunneling layers 31, ensuring a doping concentration of 1E19cm⁻¹ in the n-poly region electrochemical doping concentration test (ECV test). -3 ~1E21cm -3 .

[0124] During this process, a BSG layer is retained in the tunneling layer 31 of the first doped structure 2 to prevent the inward diffusion of phosphorus; while outside the first doped structure 2, phosphorus diffuses through the tunneling layer 31 into the silicon substrate 1 to form a phosphorus doped region.

[0125] The annealing temperature is related to the density and thickness of the tunneling layer 31. In one optional embodiment, when the tunneling layer 31 is silicon oxide, the thickness is 1.4 nm to 2.3 nm and the annealing temperature is 880 °C to 950 °C; when the tunneling layer 31 is silicon carbide, the thickness is 1 nm to 1.8 nm and the annealing temperature is 850 °C to 900 °C, so as to ensure that the phosphorus outside the first doped structure 2 diffuses inward to the silicon substrate 1.

[0126] S5 removes the mask layer, doped polysilicon layer 32, and tunneling layer 31 outside the second doped structure 3 that is spaced apart from the first doped structure 2:

[0127] S51 uses a laser process to remove the mask layer outside the second doped structure 3, exposing the underlying doped polycrystalline silicon layer 32. Laser parameters: laser power 50W~120W, preferably ultraviolet picosecond or green picosecond lasers, as lasers with less damage are more conducive to film opening.

[0128] S52 uses an HF solution to remove the mask layer wrapped around the front side. It is preferably operated in a chain conveyor.

[0129] S53 re-texturing alkaline solution removes the doped polysilicon layer 32 and tunneling layer 31 outside the second doped structure 3 on the back side (laser grooving area); at the same time, alkaline etching is performed on the front side of the silicon substrate 1 to form a textured tower base on the exposed silicon substrate 1, and finally it is cleaned.

[0130] A preferred trough-type texturing alkaline solution is used to remove the P-type doped polysilicon layer on the front side and the P-type doped polysilicon layer in the laser-grooved area on the back side, forming a textured structure in the laser-grooved areas on the front and back sides of the silicon substrate 1.

[0131] The texturing alkaline solution used in this invention is a commonly used texturing alkaline solution in the art, or it can be selected from 0.2mol / L~0.5mol / L NaOH solution or 0.2mol / L~0.5mol / L KOH solution.

[0132] In step S5, the film layers at the location of the second doped structure 3 and the location of the spacer region 4 can be removed in a patterned manner, so that the recess depths at the location of the second doped structure 3 and the location of the spacer region 4 are different.

[0133] Compared to related technologies that "first form a textured structure on the surface of silicon substrate 1 and then prepare other films", this invention forms a pyramid structure on the front side after the important structures and films of the first doped structure 2 and the second doped structure 3 are prepared. On the one hand, there is no need to polish the back side before boron diffusion; on the other hand, step S53 forms a pyramid structure on the front side while removing the doped polysilicon layer 32 and tunneling layer 31 on the back side, achieving multiple benefits; furthermore, when the front side is flat, it is more conducive to the deposition and cleaning of films in the above steps.

[0134] In addition, the boron junction, tunneling layer 31, and doped polysilicon layer 32 between the first doped structure 2 and the second doped structure 3 have all been removed to form an isolation region 4, thereby preventing leakage between the first doped structure 2 and the second doped structure 3.

[0135] In this invention, the width, depth, etc. of the isolation zone 4 are as described above, and will not be repeated here.

[0136] S6 forms a passivation layer on both sides, which is a non-essential process step.

[0137] In one embodiment, the back passivation layer and the front passivation layer are aluminum oxide layers. Using an ALD process, aluminum oxide is deposited on both the front and back sides, with a preferred thickness of 3 nm to 6 nm. Al2O3 provides excellent field passivation for the first doped structure 2 and excellent interface passivation for the second doped structure 3.

[0138] In another embodiment, the back passivation layer and the front passivation layer include a first charge film layer and a second charge film layer located on the side of the first charge film layer away from the silicon substrate. The materials and thicknesses of the first charge film layer and the second charge film layer are described above and will not be repeated here.

[0139] The first charge film layer includes a silicon oxide film layer and an aluminum oxide film layer located on the side of the silicon oxide film layer opposite to the silicon substrate. Its deposition methods include, but are not limited to, the following.

[0140] In one embodiment, an ALD process is used for deposition. The silicon substrate is placed in the ALD equipment, water is first introduced, the pulse time is 5s to 10s, and the number of processing cycles is 3 to 15 to form a silicon oxide layer with a thickness of 0.5nm to 2nm. Then, an aluminum oxide film layer with a thickness of 1nm to 20nm is deposited by conventional process.

[0141] In another embodiment, a layer of ultrathin silicon oxide is deposited on the front side using PECVD at a temperature of 200°C to 500°C, preferably 350°C to 450°C.

[0142] In another embodiment, a silicon oxide layer is formed on the surface of a silicon substrate in an oxygen atmosphere or an air atmosphere using a high-temperature method, with a temperature of 300°C to 900°C, preferably 500°C to 600°C.

[0143] The second charge film layer includes a SiNx film layer or a SiOxNy film layer, which can be deposited using PECVD.

[0144] The passivation film on the front side can also include a silicon oxide film, an aluminum oxide film, a SiNx film, or a SiOxNy film. The addition of a silicon oxide film not only improves the passivation effect on the front side but also enhances the UV resistance of the solar cell, preventing damage to the passivation effect under sunlight and improving the overall performance of the cell.

[0145] S7 Double-sided antireflection layer formation: This is a non-essential process step. A multilayer film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide is formed by chemical vapor deposition. The thickness of the antireflection layer is 60nm~130nm.

[0146] S8 electrode fabrication: The electrode is fabricated by screen printing and sintering, including the fabrication of the back main gate electrode and the fabrication of the back sub-gate electrodes of the first doped structure 2 and the second doped structure 3.

[0147] The S9 uses laser-assisted contact optimization (LECO) technology to laser sinter the first electrode 91 and the second electrode 92, which can improve the contact between silver and silicon in the electrodes, thereby increasing the battery efficiency by more than 0.2% to 0.3%. It can also change the electrode paste, such as using silver-coated copper paste with low silver content, to save costs.

[0148] In this invention, the laser wavelength used in the LECO technology is 1064nm or 532nm, and the laser width is 100 micrometers or 1mm~2mm.

[0149] The present invention also provides a second method for fabricating a solar cell to form the solar cell shown in Figures 9-11: the first doped structure 2 is an N-type diffusion region formed by phosphorus diffusion, the second doped structure is a boron-doped P-type tunneling passivation contact structure, and the P-type tunneling passivation contact structure extends beyond the N-type diffusion region in the direction from the silicon substrate to the back side.

[0150] The second method for preparing solar cells includes the following steps.

[0151] S1 silicon wafer processing: Select N-type silicon wafers with resistivity of 0.3Ω·cm~7Ω·cm, and polish or texturize them.

[0152] Polishing: Alkaline polishing is performed using KOH or NaOH and additives; or the surface of silicon substrate 1 is first textured and then polished. After polishing, the surfaces of the first doped structure 2 and the second doped structure 3 are planar, and the base is 15μm~30μm.

[0153] Texturing: Texturing is performed on the surface of silicon substrate 1 so that the surfaces of the first doped structure 2 and the second doped structure 3 are textured, with a base thickness of 3μm~15μm.

[0154] S2 prepares a P-type tunneling passivation contact structure and a BSG layer on the entire back side of the silicon substrate 1: the tunneling layer and the intrinsic silicon layer (i-Poly) are deposited alternately at least once; BCl3 or BBr3 is used as the diffusion source, the diffusion temperature is 850℃~960℃, boron diffusion is performed on the i-Poly to form a P-type doped polycrystalline silicon layer, and a BSG layer is formed on the surface.

[0155] S21 uses LPCVD process to deposit tunneling layer / i-Poly: first, a tunneling layer 31 with a thickness of 1.2~2nm is grown on the back side; then an i-poly layer with a thickness of 200~400nm is grown.

[0156] "Alternate at least once" means that 0, 1, 2...n tunneling layers can be grown in the middle of the i-poly layer. Specifically, if there are n alternations, then (n-1) tunneling layers can be grown in the middle of the i-poly layer.

[0157] S22 boron doping: can be achieved through tubular diffusion, using BCl3 or BBr3 as the diffusion source, with the temperature controlled at 850℃~960℃, sheet resistance of 50 ohm / sq~500 ohm / sq, and surface concentration of 1E18cm⁻¹. -3 ~1E20cm -3 The thickness of the BSG layer is 30nm~200nm.

[0158] S3 removes the BSG layer outside the P region and the P-type tunneling passivation contact structure.

[0159] S31 BSG layer removal. Laser grooving is used to remove the BSG layer outside the P-region on the back side of the silicon substrate, with the edge of the silicon substrate being the laser-grooved area. Hydrofluoric acid (HF) solution is used to remove the BSG layer wrapped around the front and sides; preferably, the HF solution is added in a chain machine to remove the BSG layer on the front side and the side edges of the silicon wafer.

[0160] S32 removes the P-type tunneling passivation contact structure.

[0161] Texturing alkaline solution is used to remove the P-type doped polysilicon layer in the laser-grooved area on the back side, as well as the P-type doped polysilicon layer wrapped around the front and sides, while forming a textured tower base in these areas.

[0162] Alternatively, polishing alkaline solution can be used to remove the P-type doped polysilicon layer in the laser-grooved area on the back side, as well as the P-type doped polysilicon layer wrapped around the front and sides, while simultaneously forming a planar tower base in these areas.

[0163] The polishing alkali solution of the present invention is a commonly used polishing alkali solution in the art, or it can be: 0.2mol / L~0.5mol / L sodium hydroxide (NaOH), 0.2mol / L~0.5mol / L potassium hydroxide (KOH), or 0.4mol / L~0.8mol / L tetramethylammonium hydroxide (TMAH), and the polishing time is 100s~300s.

[0164] S4 diffuses in the region outside the P region to form an N-type diffusion region and a PSG layer.

[0165] Phosphorus diffusion was performed in the region outside the P-region using a high-temperature diffusion furnace at a temperature of 850℃~950℃ to ensure a doping concentration of 1E15cm⁻¹ for the ECV test of the N-type diffusion region. -3 ~1E22cm -3 Preferably 1E20cm-3 ~1E21cm -3 This step can also be double-sided diffusion, so that an n+ field can be formed on the front side and an N+ field can be formed on the back side.

[0166] S5 removes the PSG layer and N-type diffusion region outside the N-region.

[0167] S51 removes the PSG layer. The PSG layer outside the N region (where spacer 4 is located) is removed by laser grooving, and the laser grooving area is located at the edge of the silicon substrate 1.

[0168] This invention establishes a laser-grooved area at the edge of the silicon substrate 1, forming a gap region 4 at the edge of the silicon substrate 1 to insulate the back side from the sides and the front side. In other embodiments, in all laser-grooving steps, grooving can be performed at the edge of the silicon substrate 1 or not, achieving insulation between the back side and the sides and the front side.

[0169] S52 removes the N-type diffusion zone in the laser-grooved area.

[0170] Polishing alkaline solution is used to remove the N-type diffusion zone in the laser grooving area and form a planar tower base interval zone 4 between the P and N zones.

[0171] Specifically, polishing alkaline solution is added in a trough polishing machine to remove the N-type diffusion region in the laser-grooved area on the back side, and a plane is formed in the spacer region 4. The surface of the spacer region 4 facing the front side of the silicon substrate 1 is a plane, and the base size of the plane is 15μm~30μm, or the roughness of the plane is not greater than 10nm.

[0172] In this step, the N-regions on the front and back sides are protected by PSG layer masks, and the P-region on the back side is protected by BSG layer masks, so the corresponding poly layers will not be damaged.

[0173] Alternatively, the polishing alkali solution can be replaced with a texturing alkali solution to remove the N-type diffusion zone in the laser grooving area and form a planar tower base interval zone 4 between the P and N zones.

[0174] In addition, before polishing or texturing, the PSG layer on the side can be removed by adding HF solution in a chain machine. Therefore, the N-type diffusion zone on the side is removed at the same time during polishing or texturing.

[0175] Finally, HF solution is used for cleaning to remove the BSG layer in the P region and the PSG layer in the N region.

[0176] S8 Formation of passivation layer on both sides: Refer to S6 in the first method for fabricating solar cells.

[0177] S9 Formation of antireflection layer on both sides: Refer to S7 in the first method for preparing solar cells.

[0178] S10 electrode fabrication: Electrodes are fabricated by screen printing and sintering, including the fabrication of the back main gate electrode, the fabrication of the back P-type tunneling passivation contact structure and the N-type doped structure 3 sub-gate electrode.

[0179] S11 uses LECO technology to laser sinter the first electrode 91 and the second electrode 92, referring to S9 in the first method for preparing a solar cell.

[0180] The present invention also provides a third method for preparing a solar cell to form the solar cell shown in Figures 12-14: the first doping structure 2 is an N-type diffusion region formed by phosphorus diffusion, the second doping structure is a boron-doped P-type tunneling passivation contact structure, and the N-type diffusion region extends beyond the P-type tunneling passivation contact structure in the direction from the silicon substrate to the back side.

[0181] The third method for preparing solar cells includes the following steps.

[0182] S1 Polishing: Select an N-type silicon wafer and perform alkaline polishing using KOH or NaOH and additives; or first texturize the surface of silicon substrate 1 and then polish it. The base of the P-type tunneling passivation contact structure is 3μm~15μm.

[0183] S2 phosphorus diffuses to form an N-type diffusion region (phosphorus knot) and a PSG layer.

[0184] Phosphorus diffusion was performed on the entire back side using a high-temperature diffusion furnace to form an N-type diffusion region and a PSG layer. The diffusion temperature was 850℃~950℃ to ensure that the doping concentration of the N-type diffusion region was 1E15cm⁻¹ in the ECV test. -3 ~1E22cm -3 Preferably 1E20cm -3 ~1E21cm -3 .

[0185] In one embodiment, phosphorus diffusion is performed on the back side while phosphorus diffusion is also performed on the front side of the silicon substrate 1, forming an N+ field on the front side of the silicon substrate 1.

[0186] S3 removes the PSG layer and phosphorus junction outside the first doped structure 2 (N region) on the back side.

[0187] S31 performs laser grooving outside the first doped structure 2 to remove the PSG layer outside the first doped structure 3.

[0188] S32 removes the phosphorus junction outside the first doped structure 2:

[0189] The PSG layer on the side of the silicon substrate 1 is preferably removed by an HF solution etching process or a laser process.

[0190] The material is then polished to remove the phosphorus junction outside the first doped structure 2 on the back side, as well as the phosphorus junction wrapped around the side. The phosphorus diffusion layer, the phosphorus junction of the first doped structure 2, and the BSG layer on the front side are all retained. This step is preferably performed in a tank mill.

[0191] S4 was used to prepare P-type tunneling passivated contact structures.

[0192] S41 uses LPCVD process to form tunneling layers / i-Poly: first, a tunneling layer 31 with a thickness of 1.2~2nm is grown on the back side; then an i-poly layer with a thickness of 200~400nm is grown. 0, 1, 2....n tunneling layers 31 can be grown in the middle of the poly layer.

[0193] S42 Boron doping: Boron diffusion can be performed on the intrinsic layer by using BCl3 or BBr3 as the diffusion source through tubular diffusion, with the temperature controlled at 850℃~1100℃, preferably 850℃~960℃, to form a P-type doped polycrystalline silicon layer, and a BSG layer is formed on the surface.

[0194] The sheet resistance of the p-type doped polysilicon layer is 50 ohm / sq to 500 ohm / sq, and the surface concentration is 1E18cm⁻¹. -3 ~1E20cm -3 The thickness of the BSG layer is 30~200nm.

[0195] S5 removes the BSG layer and P-type passivation contact structure outside the second doped structure 3.

[0196] S51 laser grooving removes the BSG layer outside the second doped structure 3, exposing the underlying doped polysilicon layer 32.

[0197] S52 uses a chain machine and HF solution to remove the BSG layer from the front side and the side of the silicon wafer.

[0198] S53 removes the P-type passivation contact structure.

[0199] In one embodiment, a texturing alkaline solution is used to remove the doped polysilicon layer 32 on the front side and the doped polysilicon layer 32 in the laser-grooved area on the back side. At the same time, alkaline etching is performed on the front side of the silicon substrate 1 to form a pyramid structure on the exposed silicon substrate 1. At this time, the surface of the spacer region 4 is also a texturized structure.

[0200] In another embodiment, a polishing alkaline solution is first used to remove the P-type doped polycrystalline silicon layer on the laser-grooved area, the front side, and the sides, forming a planar tower base. Then, a back mask layer is formed on the back side; this back mask layer is a silicon oxide layer with a thickness of 30nm~100nm. Under the protection of the back mask layer, a texturing alkaline solution is used to form a textured tower base on the front side of the silicon substrate 1, improving the light-limiting properties of the front side. Finally, a hydrofluoric acid solution is used to remove the back mask layer on the back side.

[0201] S6 Formation of passivation layer on both sides: Refer to S6 in the first method for fabricating solar cells.

[0202] S7 Formation of Antireflection Layer on Both Sides: Refer to S7 in the fabrication method of the first solar cell.

[0203] S8 electrode fabrication: Electrode fabrication is carried out by screen printing and sintering, including the fabrication of the back main gate electrode, the fabrication of the back P-type tunneling passivation contact structure and the N-type doped structure 3 sub-gate electrode.

[0204] S9 employs LECO technology to laser sinter the first electrode 91 and the second electrode 92, referring to S9 in the first method for fabricating a solar cell. In summary, the solar cell 100 of the present invention improves cell efficiency by placing both the first electrode 91 and the second electrode 92 on the back side, eliminating metal electrode obstruction on the front side, resulting in a large light-receiving area and high light conversion efficiency. Furthermore, by incorporating an SE structure in the first doped structure 2, the open-circuit voltage and short-circuit current of the cell are improved; and by incorporating a passivated contact structure in the second doped structure 3 to passivate its surface, the short-circuit current is increased, thus improving overall cell efficiency.

[0205] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0206] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that, include: A plurality of first doped structures are spaced apart, wherein the first doped structure is a diffusion region formed by diffusion from the back side of the silicon substrate inward; A second doped structure is alternately disposed with the first doped structure, wherein the second doped structure is a tunneling passivation contact structure and the doping type of the tunneling passivation contact structure is opposite to that of the diffusion region; The spacer region is located between the first doped structure and the second doped structure; The first electrode is located on the back side of the first doped structure; The second electrode is located on the back side of the tunneling passivation contact structure.

2. The solar cell according to claim 1, characterized in that: The second doped structure is located in a region recessed from the back side to the front side of the silicon substrate, the spacer region is recessed from the back side to the front side of the silicon substrate, and the recess depth at the location of the second doped structure and / or the spacer region is not less than the diffusion depth of the diffusion region.

3. The solar cell according to claim 1, characterized in that: The width of the interval region is 10μm~150μm; and / or The spacer region is recessed from the back side of the silicon substrate to the front side, and the distance from the back surface of the spacer region to the back surface of the first doped structure is 1μm~20μm.

4. The solar cell according to claim 1, characterized in that: The distance from the back surface of the second doped structure to the front surface of the silicon substrate is not greater than the distance from the back surface of the first doped structure to the front surface of the silicon substrate; or The dimension of the second doped structure in the thickness direction of the silicon substrate is not greater than the recess depth of the spacer region; or The distance between the back surface of the first doped structure and the back surface of the second doped structure in the thickness direction of the silicon substrate is 1 μm to 10 μm.

5. The solar cell according to claim 1, characterized in that: The diffusion region includes a gate line region and a non-gate line region, wherein the doping concentration of the gate line region is greater than that of the non-gate line region, and the first electrode is in contact with the gate line region.

6. The solar cell according to claim 5, characterized in that: The sheet resistance of the gate line region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the non-gate line region is 200 ohm / sq to 400 ohm / sq.

7. The solar cell according to claim 1, characterized in that: The tunneling passivation contact structure includes at least one tunneling layer, a doped polysilicon layer located on the side of each tunneling layer away from the silicon substrate, and the second electrode is in contact with the doped polysilicon layer.

8. The solar cell according to claim 7, characterized in that: The tunneling passivation contact structure includes n tunneling layers, n≥2, and the second electrode is in contact with at least one of the 2nd to nth doped polycrystalline silicon layers in the direction from the silicon substrate to the back side.

9. The solar cell according to any one of claims 1 to 8, characterized in that: The tunneling passivation contact structure includes at least one tunneling layer and a doped polysilicon layer located on the side of each tunneling layer facing away from the silicon substrate, wherein The first doped structure is a P-type diffusion region, and the doped polysilicon layer is an N-type doped polysilicon layer; or The first doped structure is an N-type diffusion region, and the doped polysilicon layer is a P-type doped polysilicon layer.

10. The solar cell according to claim 1, characterized in that: Along the direction from the front to the back of the silicon substrate, the first doped structure is higher than the second doped structure.

11. The solar cell according to claim 10, characterized in that: The height difference between the back surface of the first doped structure and the back surface of the second doped structure is 0.5 to 1.5 times the diffusion depth of the diffusion region.

12. The solar cell according to claim 1, characterized in that: The base size of the surface of the spacer region facing the front side of the silicon substrate is 15μm~30μm, or the roughness of the surface of the spacer region facing the front side of the silicon substrate is not greater than 10nm.

13. The solar cell according to claim 12, characterized in that: The back of the solar cell, except for the spacer area, has a textured surface.

14. The solar cell according to claim 1, characterized in that: The surface of the spacer region has a passivation film layer, which includes a first charge film layer in contact with the silicon substrate and a second charge film layer located on the side of the first charge film layer away from the silicon substrate. The first charge film layer has the same charge type as the silicon substrate, and the charge types of the first charge film layer and the second charge film layer are opposite.

15. The solar cell according to claim 14, characterized in that: The thickness of the first charge film layer is less than the thickness of the second charge film layer.

16. The solar cell according to claim 14, characterized in that: If the silicon substrate is N-type silicon, then the first charge film layer is a negative charge film layer, and the second charge film layer is a positive charge film layer; or If the silicon substrate is P-type silicon, then the first charge film layer is a positive charge film layer and the second charge film layer is a negative charge film layer.

17. The solar cell according to claim 16, characterized in that: The negative charge film layer includes a silicon oxide film layer and an aluminum oxide film layer located on the side of the silicon oxide film layer opposite to the silicon substrate.

18. The solar cell according to claim 17, characterized in that: The thickness of the silicon oxide film is 0.5 nm to 2 nm, and the thickness of the aluminum oxide film is 1 nm to 20 nm.

19. The solar cell according to claim 16, characterized in that: The positively charged film layer is selected from at least one of SiNx film layer or SiOxNy film layer.

20. The solar cell according to claim 19, characterized in that: The thickness of the positively charged film is 10 nm to 100 nm.

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