Manufacturing method for semiconductor device

Abstract

Provided in the present application is a manufacturing method for a semiconductor device. A buried oxide layer and a channel layer are sequentially stacked on a substrate. A gate electrode on the channel layer, a source electrode in contact with one end of the channel layer, and a drain electrode in contact with the other end of the channel layer are formed. A first dimension of the channel layer in a first direction on the surface of the substrate is greater than a second dimension of the gate electrode in the first direction, the difference between the first dimension and the second dimension is negatively correlated with the second dimension, and the first direction is the direction of a connecting line between the source electrode and the drain electrode. That is to say, the length of the channel layer is greater than the length of the gate electrode, and the greater the length of the gate electrode, the smaller the length difference between the two, bringing the channel layer and the gate electrode closer to each other. Thus, as the length of the gate electrode decreases, the extent of reduction in the channel layer is relatively small, which is conducive to suppressing short-channel effects. Moreover, for scenarios where the length of the gate electrode is relatively large, the length of the channel layer approximates that of the gate electrode, which avoids the problem of excessive series resistance caused by an overly long channel layer, thereby effectively providing a short-channel effect suppression capability and a higher on-state current.

Description

A method for manufacturing a semiconductor device

[0001] This application claims priority to Chinese Patent Application No. 202410917976.9, filed on July 9, 2024, entitled "A Method for Manufacturing a Semiconductor Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductors, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0003] Semiconductor technology has permeated application areas such as mobile phones, computers, network communications, and automobiles. Among them, network communications, electronic devices, and automotive electronics account for the vast majority of the semiconductor market. With the development of the times, fields such as 5G technology, artificial intelligence, and automotive electronics have placed higher demands on semiconductor devices: higher integration, lower power consumption, excellent reliability in harsh environments, and lower cost.

[0004] Traditional planar silicon MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are the most common transistor type in digital and analog circuits. MOSFETs operate based on the electric field effect, controlling the conductivity of solid materials. They utilize gate voltage to control the current between the source and drain. When a certain voltage is applied to the gate, charges are induced on the semiconductor surface beneath the gate. These charges form a conductive channel, allowing current to flow between the source and drain. However, due to the short-channel effect, the gate's control over the channel current in MOSFETs has decreased to an unacceptable level, necessitating processes with stronger gate control capabilities to optimize device performance. Advanced node semiconductor devices with stronger gate control capabilities mainly include FinFETs (Fin Field Effect Transistors) and Fully Depleted Silicon on Insulators (FDSOI).

[0005] Fully Depleted Silicon on Insulator (FDSOI) is a planar fabrication technology that relies on two main innovations. First, an ultrathin insulator layer, called a buried oxide (BOX) layer, is placed on top of the substrate. The transistor channel is then realized through a thin silicon layer on top of the BOX layer, known as the top silicon or SOI layer, forming a top silicon-buried oxide-substrate SOI structure. Due to the ultrathin thickness of the silicon layer, the transistor can be fully depleted without doping the channel. Thanks to its electrostatic properties and all-dielectric isolation, FDSOI technology is widely used in low-power, radio frequency (RF), and millimeter-wave technologies. By utilizing the ultrathin silicon film on the buried oxide layer and unique bulk bias technology, it meets the device requirements of these fields and has been applied at multiple technology nodes.

[0006] However, as Moore's Law continued to the 28nm technology node, the impact of short-channel effects on transistor performance became significant, greatly limiting the miniaturization of FDSOI MOSFETs. Summary of the Invention

[0007] In view of this, the purpose of this application is to provide a method for manufacturing a semiconductor device that effectively provides the ability to suppress short-channel effects and ensures a large on-state current.

[0008] This application provides a semiconductor device, including:

[0009] A substrate is provided on which a buried oxide layer and a trench layer are sequentially stacked;

[0010] A gate is formed on the channel layer; a first dimension of the channel layer in a first direction along the surface of the substrate is larger than a second dimension of the gate in the first direction, the difference between the first dimension and the second dimension being determined based on the second dimension and negatively correlated with the second dimension;

[0011] A source electrode is formed that contacts one end of the channel layer, and a drain electrode is formed that contacts the other end of the channel layer, wherein the first direction is the direction of the line connecting the source electrode and the drain electrode.

[0012] Optionally, the difference is linearly related to the second dimension.

[0013] Optionally, the difference is the product of the difference between the preset size and the second size and a preset value, wherein the preset size ranges from 20 to 60 nm and the preset value ranges from 0.1 to 3.

[0014] Optionally, the preset size ranges from 20 to 30 nm, and the preset value ranges from 1 to 3.

[0015] Optionally, the preset size ranges from 40 to 60 nm, and the preset value ranges from 0.1 to 0.8.

[0016] Optionally, the preset size is 50nm, and the preset value is 0.5.

[0017] Optionally, the thickness of the buried oxide layer is 15 nm, and the channel layer material is silicon with a thickness of 5 nm.

[0018] Optionally, the source includes a first substructure flush with the channel layer on one side and a second substructure on the first substructure, and the drain includes a third substructure flush with the channel layer on the other side and a fourth substructure on the third substructure.

[0019] Optionally, the method further includes:

[0020] A gate dielectric layer is formed between the gate and the channel layer.

[0021] Optionally, the method further includes:

[0022] The sidewalls that form the gate sidewalls.

[0023] This application provides a method for manufacturing a semiconductor device. A buried oxide layer and a channel layer are sequentially stacked on a substrate to form a gate on the channel layer, a source contacting one end of the channel layer, and a drain contacting the other end of the channel layer. A first dimension of the channel layer in a first direction along the surface of the substrate is larger than a second dimension of the gate in the first direction. The difference between the first dimension and the second dimension is negatively correlated with the second dimension. The first direction is the direction of the connection between the source and the drain. That is, the length of the channel layer is greater than the length of the gate, and the larger the gate length, the smaller the difference between the two lengths, making the channel layer and the gate closer. Thus, as the gate length decreases, the decrease in the channel layer length is smaller, which is beneficial for suppressing the short-channel effect. For cases with a large gate length, the lengths of the channel layer and the gate are close, avoiding the problem of excessive series resistance caused by an excessively long channel layer. Therefore, it can effectively provide the ability to suppress the short-channel effect and ensure a large on-state current. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 shows a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0026] Figure 2 is a flowchart of a semiconductor device manufacturing method provided in an embodiment of this application;

[0027] Figures 3-6 are schematic diagrams of the structures of various semiconductor devices provided in the embodiments of this application;

[0028] Figure 7 is a schematic diagram of a subthreshold swing provided in an embodiment of this application;

[0029] Figure 8 is a schematic diagram of a drain-induced barrier reduction provided in an embodiment of this application;

[0030] Figure 9 is a schematic diagram of an on-state current provided in an embodiment of this application;

[0031] Figure 10 is a schematic diagram of another subthreshold swing provided in an embodiment of this application;

[0032] Figure 11 is a schematic diagram of another drain-induced barrier reduction provided in an embodiment of this application;

[0033] Figures 12 and 13 are carrier concentration distribution diagrams provided in the embodiments of this application. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0036] This application is described in detail with reference to the schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not according to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0037] Referring to Figure 1, which is a schematic diagram of a semiconductor device provided in an embodiment of this application, the source 130 and drain 140 at both ends of the transistor are heavily doped, serving to provide charge carriers when the device is turned on. The middle channel layer 150 is lightly doped or undoped, and a PN junction is formed at the junction of the channel layer 150 with the source 130 and drain 140. The transistor is turned on and off by applying a bias to the gate 170 to adjust the potential barrier of the PN junction. For an n-type FDSOI MOSFET, i.e., the source 130 and drain 140 are heavily n-type doped, applying a positive bias to the gate 170 will turn on the channel. At this time, applying a positive bias to the drain 140 allows electrons from the source 130 to enter the drain 140 through the channel, and conductivity is possible between the source 130 and drain 140. When the device is turned off, the channel is not turned on, and applying a drain bias cannot allow charge carriers to pass through the channel.

[0038] A PN junction, also known as a P-type junction, is a special structure formed by tightly bonding P-type and N-type semiconductors onto a single semiconductor substrate. This structure creates a space charge region near the interface between the two semiconductors, called a PN junction. A PN junction exhibits unidirectional conductivity, meaning it allows current to flow in only one direction and prevents current from flowing in the opposite direction.

[0039] As Moore's Law extends to the 28nm technology node, the impact of the short-channel effect on transistor performance has become significant, greatly limiting the miniaturization of FDSOI MOSFETs. Due to the short-channel effect, the PN junction barrier is no longer solely controlled by the gate, but rather jointly controlled by the drain and gate. This reduces the gate's electrostatic control force. Specifically, due to the superposition of the lateral electric fields of the gate and drain, current congestion occurs at the corners of the channel-gate-drain junction, severely degrading carrier mobility. Furthermore, the shortened channel length allows some carriers to tunnel directly from the source to the drain, increasing the device's off-state current.

[0040] To suppress the short-channel effect, the channel doping concentration needs to be increased. However, continuously increasing the doping concentration will cause the transistor to generate more severe random doping fluctuations, affecting the consistency of the threshold voltage; it will also increase the probability of carrier scattering and reduce the on-state current of the device; high doping concentration increases the PN junction field strength, increases the probability of inter-band tunneling, and increases the gate leakage current.

[0041] Based on the above technical problems, this application provides a method for manufacturing a semiconductor device. A buried oxide layer and a channel layer are sequentially stacked on a substrate to form a gate on the channel layer, a source contacting one end of the channel layer, and a drain contacting the other end of the channel layer. A first dimension of the channel layer in a first direction along the surface of the substrate is larger than a second dimension of the gate in the first direction. The difference between the first dimension and the second dimension is negatively correlated with the second dimension. The first direction is the direction of the connection between the source and the drain. That is, the length of the channel layer is greater than the length of the gate, and the larger the gate length, the smaller the difference between the two lengths, making the channel layer and the gate closer. Thus, as the gate length decreases, the decrease in the channel layer length is smaller, which is beneficial for suppressing the short-channel effect. For cases with a large gate length, the lengths of the channel layer and the gate are close, avoiding the problem of excessive series resistance caused by an excessively long channel layer. Therefore, it can effectively provide the ability to suppress the short-channel effect and ensure a large on-state current.

[0042] To better understand the technical solution and effects of this application, the specific embodiments will be described in detail below with reference to the accompanying drawings.

[0043] Referring to Figure 2, which is a flowchart of a semiconductor device manufacturing method provided in an embodiment of this application, the method may include:

[0044] S101, a substrate is provided, on which a buried oxide layer and a trench layer are sequentially stacked.

[0045] In this embodiment, the substrate 100 can be a semiconductor substrate to provide support for the film layer thereon. For example, it can be a silicon substrate, germanium substrate, etc. The substrate 100 can be circular during the manufacturing process. For example, it can be a silicon wafer. Multiple chips can be formed on it to form an array, so as to realize the same batch manufacturing of multiple chips and improve manufacturing efficiency.

[0046] A buried oxide layer 110 and a channel layer can be formed on the substrate 100. When the channel layer is made of silicon, the substrate 100, buried oxide layer 110, and channel layer constitute an SOI substrate. The buried oxide layer 110 is an insulating layer used to isolate the channel layer from the substrate 100, preventing carriers in the channel layer from leaking from the substrate 100 during device operation. The buried oxide layer 110 can be, for example, silicon oxide or germanium oxide, and its thickness can be determined according to the node, for example, 15 nm. The channel layer material can be silicon or germanium, and its thickness can be determined according to the node, for example, 5 nm.

[0047] S102, forming a gate on the channel layer; the first dimension of the channel layer in a first direction along the surface of the substrate is greater than the second dimension of the gate in the first direction, the difference between the first dimension and the second dimension being determined based on the second dimension and negatively correlated with the second dimension.

[0048] S103, forming a source electrode that contacts one end of the channel layer and a drain electrode that contacts the other end of the channel layer, wherein the first direction is the direction of the line connecting the source electrode and the drain electrode.

[0049] A source, drain, and gate can be formed on the substrate. Referring to Figures 3-6, which are schematic diagrams of the structures of various semiconductor devices provided in the embodiments of this application, the gate 170 is located on the channel layer 150, the source 130 is in contact with one end of the channel layer 150, and the drain 140 is in contact with the other end of the channel layer 150. Taking the line direction connecting the source 130 and the drain 140 as the first direction, the channel layer 150 extends along the first direction. Taking the dimension of the channel layer 150 along the first direction as the first dimension, the first dimension is the first length, and taking the dimension of the gate 170 along the first direction as the second dimension, the second dimension is the second length.

[0050] Furthermore, a gate dielectric layer 171 may be formed between the gate 170 and the channel layer 150 to isolate the gate 170 and the channel layer 150. The gate dielectric layer 171 may be a high-k dielectric layer or silicon oxide, etc. Sidewalls may be formed on the sidewalls of the gate 170 facing the source 130 and the sidewalls facing the drain 140. The sidewalls include a first sidewall 172 and a second sidewall 173, which are used to isolate the gate 170 from the source 130 and the drain 140, respectively. A source contact 131 may be formed on the source 130, and a drain contact 141 may be formed on the drain 140. The source contact 131 and the drain contact 141 may be metal silicides to reduce contact resistance.

[0051] Typically, the first and second dimensions are equal, and the gate electric field generated by the gate 170 acts on the channel layer to control carrier transport in the channel layer 150. However, as transistor dimensions shrink, the size of the gate 170 gradually decreases, and the size of the channel layer 150 also decreases accordingly. This reduces the distance between the source and drain, making the channel layer 150 more susceptible to the electric field between the source and drain, thus reducing the controllability of the gate 170. Furthermore, with a shorter channel, some carriers can tunnel directly from the source to the drain, increasing the off-state current of the device. These adverse effects caused by a shorter channel are called the short-channel effect.

[0052] In this embodiment, the first dimension of the channel layer 150 along the surface of the substrate 100 in a first direction can be larger than the second dimension of the gate 170 along the first direction. The difference between the first and second dimensions is negatively correlated with the second dimension. The first direction is the connection direction between the source 130 and the drain 140. That is, the length of the channel layer 150 is greater than the length of the gate 170, and the larger the length of the gate 170, the smaller the length difference between the two, making the lengths of the channel layer 150 and the gate 170 closer. Thus, as the length of the gate 170 decreases, the decrease in the length of the channel layer 150 is smaller, which is beneficial for suppressing the short-channel effect. For the case where the length of the gate 170 is large, the lengths of the channel layer 150 and the gate 170 are close, avoiding the problem of excessive series resistance caused by an excessively long channel layer 150. Therefore, it can effectively provide the ability to suppress the short-channel effect and ensure a large on-state current. In addition, the channel resistance is increased by extending the channel layer 150, which reduces the leakage current between the source and drain, thus effectively reducing the off-state current of the device.

[0053] The source 130 includes a first substructure 132 flush with the channel layer 150 on one side (left side in the diagram) and a second substructure 133 on the first substructure 132. The first substructure 132 and the second substructure 133 are distinguished for the purpose of illustrating the device structure. The boundary between them is represented by a dashed line in the diagram, and they may not have an actual boundary line. The drain 140 includes a third substructure 142 flush with the channel layer 150 on the other side (right side in the diagram) and a fourth substructure 143 on the third substructure 142. The third substructure 142 and the fourth substructure 143 are distinguished for the purpose of illustrating the device structure. The boundary between them is represented by a dashed line in the diagram, and they may not have an actual boundary line. Of course, if the length of the channel layer 150 is equal to the length of the device, the sidewall of the channel layer 150 can be flush with the sidewall of the device, and there is no need to set the first substructure 132 and the third substructure 142.

[0054] Specifically, the difference between the first and second dimensions can be linearly related to the second dimension. This linear variation of the difference with respect to the second dimension facilitates control over each gate length. For example, this difference can be the product of the difference between the preset dimension and the second dimension and a preset value. Let the preset dimension be denoted as c, the preset value as a, the difference as Δx, the first dimension as x1, and the second dimension as x2. Then, Δx = a(c-x2) = a*ca*x2, and x1 = x2 + Δx = (1-a)*x2 + a*c. The preset dimension ranges from 20 to 60 nm, and the preset value ranges from 0.1 to 3.

[0055] This allows for determining the difference between the first and second dimensions when the gate length is less than a preset length. In this case, the difference is positive, satisfying the constraint that the first dimension is greater than the second dimension. When the gate length is greater than the preset length, the calculated difference is negative, failing to satisfy the constraint that the first dimension is greater than the second dimension. Therefore, the gate length can be set to equal the channel length. A smaller preset dimension allows for a larger preset value, effectively increasing the channel length. For example, when the preset dimension range is 20–30 nm, the preset value range is 1–3; when the preset dimension range is 40–60 nm, the preset value range is 0.1–0.8.

[0056] For example, the preset size can be 50nm, and the preset value can be 0.5. Thus, when the gate length (second dimension) is 15nm, the difference is 17.5, meaning the channel length (first dimension) is 32.5nm. When the gate length (second dimension) is 20nm, the difference is 15, meaning the channel length (first dimension) is 35nm. Simulations show that the channel dimensions corresponding to these two gate sizes achieve optimal performance.

[0057] Furthermore, if the calculated channel length is less than 20nm, it can be uniformly set to 20nm.

[0058] Thus, when the difference between the first and second dimensions is less than twice the sidewall, the channel sidewall can extend below the sidewall, as shown in Figure 3; when the difference between the first and second dimensions is equal to twice the sidewall, the channel sidewall can be flush with the outer sidewall of the sidewall, as shown in Figure 4; when the difference between the first and second dimensions is greater than twice the sidewall, the channel sidewall can extend beyond the sidewall, as shown in Figure 5. When the overall device size is small, the channel layer can extend to the entire device, as shown in Figure 6.

[0059] Referring to Figure 7, which is a schematic diagram of a subthreshold swing provided in an embodiment of this application, and referring to Figure 8, which is a schematic diagram of a drain-induced barrier reduction provided in an embodiment of this application, it can be seen from the figures that when the gate length is equal to the channel length, there is a significant increase in both the subthreshold swing and the drain-induced barrier reduction when the gate length decreases to below 60 nm, indicating a degradation in device performance. When the gate length decreases to below 20 nm, both increase significantly, the ability to resist short-channel effects deteriorates sharply, and the device performance is severely degraded. Therefore, setting the aforementioned preset size range is more reasonable.

[0060] Taking a gate length of 15nm as an example, multiple channel sizes can be set, such as 15nm, 20nm, 36nm, 45nm, and 75nm. Referring to Figure 9, which illustrates one type of on-state current provided by an embodiment of this application; Figure 10, which illustrates another type of subthreshold swing provided by an embodiment of this application; and Figure 11, which illustrates another type of drain-induced barrier reduction provided by an embodiment of this application, it can be seen from the figures that when the channel length is greater than 15nm and less than 60nm, the on-state current is increased, and the subthreshold swing and drain-induced barrier reduction are effectively reduced. The on-state current reaches its maximum when the channel length is 36nm. This is because when the channel length is small, the on-state current is small due to the short-channel effect. Conversely, when the channel length is large, the influence of the gate electric field on the edge position of the channel layer is reduced, and the series resistance between the source and drain is large, thus resulting in a smaller on-state current. In other words, channel extension within a suitable range effectively enhances the transistor's ability to suppress the short-channel effect.

[0061] Referring to Figures 12 and 13, which show the carrier concentration distribution provided in the embodiments of this application, the different colors in the source, drain, and channel indicate the electron concentration (eDensity). As can be seen from the figures, when the channel layer is not extended, carriers mainly accumulate in the channel layer and the areas near the sidewalls of the source and drain. Extending the channel layer allows for higher mobility of carriers in the sidewalls and below the source and drain, compensating for the negative impact of the increased effective channel length. In Figure 13, the electric field from the drain only affects the PN junction between the channel and the drain, and has little effect on the channel portion below the gate. Therefore, the channel portion below the gate has a uniform electric field distribution, improving carrier mobility and compensating for the increased channel resistance due to the increased effective channel length, resulting in a significant increase in the device's on-state current.

[0062] This invention proposes a transistor structure with extended transistor channel. By controlling the diffusion of source and drain impurities, the channel region is extended towards the sidewalls. This structure does not require changing the transistor size, does not increase manufacturing costs, and is easy to implement. It can effectively improve the short-channel effect suppression capability and greatly increase the on-state current. It can meet various application scenarios, has high market demand, and has high economic benefits.

[0063] This application provides a method for manufacturing a semiconductor device. A buried oxide layer and a channel layer are sequentially stacked on a substrate to form a gate on the channel layer, a source contacting one end of the channel layer, and a drain contacting the other end of the channel layer. A first dimension of the channel layer in a first direction along the surface of the substrate is larger than a second dimension of the gate in the first direction. The difference between the first dimension and the second dimension is negatively correlated with the second dimension. The first direction is the direction of the connection between the source and the drain. That is, the length of the channel layer is greater than the length of the gate, and the larger the gate length, the smaller the difference between the two lengths, making the channel layer and the gate closer. Thus, as the gate length decreases, the decrease in the channel layer length is smaller, which is beneficial for suppressing the short-channel effect. For cases with a large gate length, the lengths of the channel layer and the gate are close, avoiding the problem of excessive series resistance caused by an excessively long channel layer. Therefore, it can effectively provide the ability to suppress the short-channel effect and ensure a large on-state current.

[0064] The above description is merely a preferred embodiment of this application. Although this application has disclosed preferred embodiments above, it is not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which a buried oxide layer and a trench layer are sequentially stacked; Form the gate on the channel layer; The first dimension of the channel layer in a first direction along the surface of the substrate is larger than the second dimension of the gate in the first direction. The difference between the first dimension and the second dimension is determined based on the second dimension and is negatively correlated with the second dimension. A source electrode is formed that contacts one end of the channel layer, and a drain electrode is formed that contacts the other end of the channel layer, wherein the first direction is the direction of the line connecting the source electrode and the drain electrode.

2. The method according to claim 1, characterized in that, The difference is linearly related to the second dimension.

3. The method according to claim 2, characterized in that, The difference is the product of the difference between the preset size and the second size and the preset value. The preset size ranges from 20 to 60 nm, and the preset value ranges from 0.1 to 3.

4. The method according to claim 3, characterized in that, The preset size ranges from 20 to 30 nm, and the preset value ranges from 1 to 3.

5. The method according to claim 3 or 4, characterized in that, The preset size ranges from 40 to 60 nm, and the preset value ranges from 0.1 to 0.

8.

6. The method according to claim 5, characterized in that, The preset size is 50nm, and the preset value is 0.

5.

7. The method according to any one of claims 1-6, characterized in that, The thickness of the buried oxide layer is 15 nm, and the channel layer material is silicon with a thickness of 5 nm.

8. The method according to any one of claims 1-7, characterized in that, The source electrode includes a first substructure flush with the channel layer on one side and a second substructure on the first substructure, and the drain electrode includes a third substructure flush with the channel layer on the other side and a fourth substructure on the third substructure.

9. The method according to any one of claims 1-8, characterized in that, Also includes: A gate dielectric layer is formed between the gate and the channel layer.

10. The method according to any one of claims 1-9, characterized in that, Also includes: The sidewalls that form the gate sidewalls.

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