Digital beamforming circuit and phased array terminal

Abstract

The present invention provides a digital beamforming circuit and a phased array terminal. The digital beamforming circuit comprises a control unit, a configurable amplitude-phase weighting unit, a first high-speed interface, and a second high-speed interface. The configurable amplitude-phase weighting unit comprises N × N multipliers and N × N adders. The control unit determines a working mode on the basis of the number of beams, the number of array elements, and a parameter N of the configurable amplitude-phase weighting unit. The first high-speed interface and the second high-speed interface perform serial-to-parallel conversion or parallel-to-serial conversion on a data signal. The configurable amplitude-phase weighting unit performs amplitude-phase weighting on a first parallel data signal on the basis of the working mode to obtain a second parallel data signal. Because the configurable amplitude-phase weighting unit has an N × N structure, when an antenna unit is in a receiving state or a transmitting state, the digital beamforming circuit can be used to complete beamforming, without using two PFGAs, and without using an FPGA to provide a high-speed interface, thereby reducing costs, power consumption and resource waste.

Description

A digital beamforming circuit and phased array terminal

[0001] This application claims priority to Chinese Patent No. 202410931861.5, filed on July 11, 2024, entitled "A Digital Beamforming Circuit and Phased Array Terminal", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of satellite communication technology, and in particular to a digital beamforming circuit and a phased array terminal. Background Technology

[0003] Digital beamforming converts baseband data signals to beam data signals in the digital domain. In phased array terminals, digital beamforming is usually implemented using FPGA.

[0004] In existing technologies, when the number of array elements in the phased array antenna of a phased array terminal is large, beamforming needs to be implemented through a multi-stage approach due to the limited resources of a single FPGA. This implementation method requires numerous high-speed interfaces, necessitating a large number of high-performance FPGAs, leading to a sharp increase in cost and power consumption. Simultaneously, because only the high-speed interface resources of the FPGA are utilized, a large number of logic units and storage resources remain unused, resulting in resource waste. Summary of the Invention

[0005] This invention provides a digital beamforming circuit and a phased array terminal to solve the problems of high cost, high power consumption, and resource waste when digital beamforming is implemented using FPGA if the number of array elements is large.

[0006] In a first aspect, this application provides a digital beamforming circuit, including: a control unit, a first high-speed interface, a second high-speed interface, and a configurable amplitude and phase weighting unit;

[0007] The configurable amplitude and phase weighting unit is connected to the control unit, the first high-speed interface, and the second high-speed interface;

[0008] The control unit is used to determine the operating mode of the digital beamforming circuit based on the number of beams, the number of antenna elements, and the configurable amplitude and phase weighting unit parameters.

[0009] The first high-speed interface is used to convert the received first serial data signal into a first parallel data signal, wherein the first serial data signal is transmitted by the antenna unit or other digital beamforming circuit.

[0010] The configurable amplitude-phase weighting unit includes N multipliers and N multipliers. Based on the operating mode, the configurable amplitude-phase weighting unit performs amplitude-phase weighting processing on the first parallel data signal using a target multiplier from the N multipliers and a target adder from the N multipliers to obtain a second parallel data signal. The amplitude-phase weighting processing includes complex multiplication and / or complex addition operations. N is a parameter of the configurable amplitude-phase weighting unit, and N is a positive integer greater than or equal to 1.

[0011] The second high-speed interface is used to convert the second parallel data signal into a second serial data signal and send the second serial data signal to the baseband chip or other digital beamforming circuit.

[0012] Secondly, embodiments of this application also provide a digital beamforming circuit, including: a control unit, a first high-speed interface, a second high-speed interface, and a configurable amplitude and phase weighting unit;

[0013] The configurable amplitude and phase weighting unit is connected to the control unit, the first high-speed interface, and the second high-speed interface;

[0014] The control unit is used to determine the operating mode of the digital beamforming circuit based on the number of beams, the number of antenna elements, and the configurable amplitude and phase weighting unit parameters.

[0015] The second high-speed interface is used to convert the received third serial data signal into a third parallel data signal, wherein the third serial data signal is sent by the baseband chip or other digital beamforming circuit;

[0016] The configurable amplitude-phase weighting unit includes N multipliers and N multipliers. Based on the operating mode, the configurable amplitude-phase weighting unit performs amplitude-phase weighting processing on the third parallel data signal using a target multiplier from the N multipliers and a target adder from the N multipliers to obtain a fourth parallel data signal. The amplitude-phase weighting processing includes complex multiplication and / or complex addition operations. N is a parameter of the configurable amplitude-phase weighting unit, and N is a positive integer greater than or equal to 1.

[0017] The first high-speed interface is used to convert the fourth parallel data signal into a fourth serial data signal and send the fourth serial data signal to the antenna unit or other digital beamforming circuit.

[0018] Thirdly, this application also provides a phased array terminal, including an antenna unit, a baseband chip, and at least one digital beamforming circuit as described in any of the first aspects; or

[0019] Includes an antenna unit, a baseband chip, and at least one digital beamforming circuit as described in any of the second aspects;

[0020] The antenna unit, the at least one digital beamforming circuit, and the baseband chip are connected in sequence.

[0021] The beneficial effects of this invention are as follows:

[0022] This invention provides a digital beamforming circuit and a phased array terminal. The digital beamforming circuit includes a control unit, a configurable amplitude and phase weighting unit, a first high-speed interface, and a second high-speed interface. The configurable amplitude and phase weighting unit includes N multipliers (multiplier units) and N multipliers (adder units), where N is a positive integer greater than or equal to 1. The control unit determines the operating mode of the digital beamforming circuit based on the number of beams, the number of array elements, and the parameters of the configurable amplitude and phase weighting unit. Both the first and second high-speed interfaces can perform serial-to-parallel conversion and parallel-to-serial conversion. According to the operating mode, the configurable amplitude and phase weighting unit performs amplitude and phase weighting processing on a first parallel data signal or a third parallel data signal based on the amplitude and phase weighting vector, through the target multipliers in the multiplier units and the target adders in the adder units. Since both the multiplier and adder units in the configurable amplitude and phase weighting unit are N-by-N structures, the digital beamforming circuit can be used to perform amplitude and phase weighting of the data signal when the antenna unit is in receiving or transmitting mode. This eliminates the need for two types of PFGAs and the need for an FPGA to provide a high-speed interface, thereby reducing costs, power consumption, and resource waste. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 is a schematic diagram of a digital beamforming circuit provided in an embodiment of this application;

[0025] Figure 2 is a schematic diagram of a configurable amplitude-phase weighting unit provided in an embodiment of this application;

[0026] Figure 3 is a schematic diagram of another configurable amplitude-phase weighting unit provided in an embodiment of this application;

[0027] Figure 4 is a schematic diagram of the structure of a multiplier in a multiplier unit provided in an embodiment of this application;

[0028] Figure 5 is a schematic diagram of the connection relationship of a digital beamforming circuit provided in an embodiment of this application;

[0029] Figure 6 is a schematic diagram of another digital beamforming circuit connection relationship provided in an embodiment of this application;

[0030] Figure 7 is a schematic diagram of another digital beamforming circuit connection relationship provided in an embodiment of this application;

[0031] Figure 8 is a schematic diagram of another digital beamforming circuit connection relationship provided in an embodiment of this application;

[0032] Figure 9 is a schematic diagram of another digital beamforming circuit connection relationship provided in an embodiment of this application;

[0033] Figure 10 is a schematic diagram of another digital beamforming circuit connection relationship provided in an embodiment of this application;

[0034] Figure 11 is a schematic diagram of another digital beamforming circuit provided in an embodiment of this application;

[0035] Figure 12 is a schematic diagram of a high-speed interface provided in an embodiment of this application;

[0036] Figure 13 is a schematic diagram of the structure of a phased array terminal provided in an embodiment of this application. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0038] Digital beamforming converts baseband data signals to beam data signals in the digital domain. Based on the relative relationship between the bandwidth of the baseband data signal and the operating frequency of the phased array antenna, it is generally divided into narrowband digital beamforming (typically taking: bandwidth B / frequency f < 0.1) and wideband digital beamforming. In narrowband digital beamforming, the amplitude of each array element does not change before the arrival of the visible wave; only the phase of the signal complex envelope changes. Compared with wideband signal, the frequency dispersion has a smaller impact. Therefore, narrowband digital beamforming can be considered as a "spatial filter" that determines whether the signal is suppressed based on the incident direction of the beam center frequency signal. By controlling the weight vector of the spatial filter, the beam is enhanced in the desired direction and suppressed in the undesired direction.

[0039] Traditional L, S, and C band communication bandwidths are typically a few megabits, tens of megabits, or hundreds of megabits, usually not exceeding one hundred megabits. These can generally be treated as narrowband signals, achieving beamforming through amplitude and phase weighting in the time domain. Depending on whether digital beam signals are used to obtain the amplitude and phase weighting vector, digital beamforming algorithms are divided into adaptive beamforming and data-independent beamforming. In satellite internet applications, beam generation, pointing, scheduling, and management follow protocol standards and are usually handled by dedicated functional units or circuits. Beam resources are planned in advance, and beamforming vector weights, i.e., amplitude and phase weighting vectors, are generated through conventional windowing or array pattern synthesis to complete digital beamforming.

[0040] In phased array terminals, the amplitude and phase weight vectors of a beam are typically calculated using high-performance FPGAs or DSPs. This is usually derived by the beam control unit based on ephemeris information and user relationships, or by the beam elevation angle transmitted between integrated processing systems, combined with the array structure and beam pattern requirements. Digital beamforming, if involving multiple beams, requires multiple sets of amplitude and phase weight vectors corresponding to the number of array elements and beams. The resource scale is determined by the array element size, the number of beams, and the computation time requirements. Ultimately, the amplitude and phase weight calculation for multiple beams is usually performed within the FPGA; that is, digital beamforming is completed within the FPGA. When the array element size is large, due to the limited resources of a single FPGA, digital beamforming needs to be implemented through a multi-stage approach. In this implementation, the large number of high-speed interfaces necessitates many high-performance FPGAs, leading to a sharp increase in cost and power consumption. Simultaneously, because only the high-speed interface resources of the FPGA are used, a large number of logic units and storage resources remain unused, resulting in resource waste.

[0041] Based on the above problems, this application provides a digital beamforming circuit, as shown in FIG1, including: a control unit 11, a configurable amplitude and phase weighting unit 12, a first high-speed interface 13 and a second high-speed interface 14.

[0042] The configurable amplitude and phase weighting unit 12 is connected to the control unit 11, the first high-speed interface 13, and the second high-speed interface 14.

[0043] Control unit 11 is used to determine the operating mode of the digital beamforming circuit based on the number of beams, the number of array elements, and the parameters of the configurable amplitude and phase weighting unit.

[0044] When the antenna element is in receiving mode:

[0045] The first high-speed interface 13 is used to convert the received first serial data signal into a first parallel data signal, wherein the first serial data signal is transmitted by the antenna unit or other digital beamforming circuit.

[0046] The configurable amplitude-phase weighting unit 12 includes N multipliers and N multipliers and N adders. The configurable amplitude-phase weighting unit 12 is used to perform amplitude-phase weighting processing on the first parallel data signal based on the working mode, by using the target multiplier among the N multipliers and the target adder among the N multipliers and N adders, to obtain the second parallel data signal. The amplitude-phase weighting processing includes complex multiplication and / or complex addition operations. N is the configurable amplitude-phase weighting unit parameter, and N is a positive integer greater than or equal to 1.

[0047] The second high-speed interface 14 is used to convert the second parallel data signal into a second serial data signal and send the second serial data signal to the baseband chip or other digital beamforming circuit.

[0048] When the antenna element is in transmit mode:

[0049] The second high-speed interface 14 is used to convert the received third serial data into a third parallel data signal, wherein the third serial data signal is sent by the baseband chip or other digital beamforming circuit.

[0050] The configurable amplitude and phase weighting unit 12 is used to perform amplitude and phase weighting processing on the third parallel data signal based on the working mode, by multiplying the target multiplier in N multipliers and the target adder in N multipliers, to obtain the fourth parallel data signal.

[0051] The first high-speed interface 13 is used to convert the fourth parallel data signal into a fourth serial data signal and send the fourth parallel data signal to the antenna unit or other data beamforming circuit.

[0052] In this embodiment, the digital beamforming circuit includes a control unit, a configurable amplitude-phase weighting unit, a first high-speed interface, and a second high-speed interface. The configurable amplitude-phase weighting unit comprises N multipliers and N multipliers, where N is a positive integer greater than or equal to 1. The control unit determines the operating mode of the digital beamforming circuit based on the number of beams, the number of array elements, and the parameters of the configurable amplitude-phase weighting unit. Both the first and second high-speed interfaces can perform serial-to-serial or parallel-to-serial conversion. The configurable amplitude-phase weighting unit, according to the operating mode, performs amplitude-phase weighting processing on parallel data signals based on the amplitude-phase weighting vector, using the target multipliers in the multiplier unit and the target adders in the adder unit. Since both the multipliers and adders in the configurable amplitude-phase weighting unit are N multipliers, this digital beamforming circuit can be used to perform amplitude-phase weighting of data signals when the antenna element is in either receiving or transmitting mode. This eliminates the need for two types of PFGAs and the need for an FPGA to provide a high-speed interface, thereby reducing cost, power consumption, and resource waste.

[0053] The digital beamforming circuit provided in this application embodiment can be a digital beamforming chip. The digital beamforming circuit can include multiple operating modes, and the digital beamforming circuit can be used alone or connected to each other.

[0054] In implementation, the data signal received by the first high-speed interface 13 can be a serial data signal or a parallel data signal. If it is a serial data signal, i.e., the first serial data signal, the first high-speed interface 13 performs serial-to-parallel conversion on the received first serial data signal to obtain the first parallel data signal. If it is a parallel data signal, i.e., the fourth parallel data signal, the first high-speed interface 13 performs parallel-to-serial conversion on the received fourth parallel data signal to obtain the fourth serial data signal.

[0055] Specifically, the first serial data signal received by the first high-speed interface 13 can be sent by the antenna unit or by other digital beamforming circuits. If the first serial data signal received by the first high-speed interface 13 is sent by other digital beamforming circuits, then the first serial data signal represents the amplitude-phase weighting process value. The parallel data signal received by the first high-speed interface 13 is sent by the configurable amplitude-phase weighting unit in the digital beamforming circuit.

[0056] In implementation, the data signal received by the second high-speed interface 14 can be a serial data signal or a parallel data signal. If it is a serial data signal, i.e., the third serial data signal, the second high-speed interface 14 performs serial-to-parallel conversion on the received third serial data signal to obtain the third parallel data signal. If it is a parallel data signal, i.e., the second parallel data signal, the second high-speed interface 14 performs parallel-to-serial conversion on the second parallel data signal to obtain the second serial data signal.

[0057] Specifically, the third serial data signal received by the second high-speed interface 14 can be sent by the baseband chip or by other digital beamforming circuits. If it is sent by other digital beamforming units, the third serial data signal represents the amplitude-phase weighting process value. The second parallel data signal received by the second high-speed interface 14 is sent by the configurable amplitude-phase weighting unit in the digital beamforming circuit.

[0058] It should be noted that the second serial data signal in the embodiments of this application includes a second serial data signal representing the final data signal, or a second serial data signal representing the amplitude-phase weighting process value. The second serial data signal representing the final data signal is a data signal directly input to the baseband chip, and the second serial data signal representing the amplitude-phase weighting process value is a data signal input to other digital beamforming circuits.

[0059] The fourth serial data signal in this application embodiment also includes a fourth serial data signal representing the final data signal, or a fourth serial data signal representing the amplitude-phase weighting process value. The fourth serial data signal representing the final data signal is a data signal directly input to the antenna element, and the fourth serial data signal representing the amplitude-phase weighting process value is a data signal input to other digital beamforming circuits.

[0060] In one embodiment, the first high-speed interface 13 includes a first deserializer and a first serializer;

[0061] The first deserializer is used to convert the first serial data signal received from the antenna unit or the first serial data signal representing the amplitude-phase weighting process value sent by other digital beamforming circuits into a first parallel data signal.

[0062] The first serializer is used to convert the received fourth parallel data signal into a fourth serial data signal and send the fourth serial data signal to the antenna unit or other digital beamforming circuit.

[0063] In this embodiment, the data signal received by the first deserializer is a serial data signal. Specifically, when the digital beamforming circuit is used alone, the serial data signal received by the first deserializer is the serial data signal sent by the antenna unit. When the digital beamforming circuits are interconnected, the serial data signal received by the first deserializer in the next-level digital beamforming circuit is the first serial data signal sent by the previous-level digital beamforming circuit, representing the amplitude-phase weighting process value. The data signal received by the first serializer is a parallel data signal. Specifically, the parallel data signal received by the first serializer is the fourth parallel data signal sent by the configurable amplitude-phase weighting unit in the digital beamforming circuit.

[0064] In one embodiment, the second high-speed interface 14 includes a second deserializer and a second serializer;

[0065] The second deserializer is used to convert the received third serial data signal sent by the baseband chip, or the third serial data signal representing the amplitude-phase weighting process value sent by other digital beamforming circuits, into a third parallel data signal.

[0066] The second serializer is used to convert the received second parallel data signal into a second serial data signal and send the second serial data signal to the baseband chip or other digital beamforming circuit.

[0067] In this embodiment, the data signal received by the second deserializer is a serial data signal. Specifically, when the digital beamforming circuit is used alone, the serial data signal received by the second deserializer is the serial data signal sent by the baseband chip. When the digital beamforming circuits are interconnected, the serial data signal received by the second deserializer in the next stage digital beamforming circuit is the serial data signal sent by the previous digital beamforming circuit, representing the amplitude-phase weighting process value. The data signal received by the second serializer is a parallel data signal. Specifically, the serial data signal received by the second serializer is the second parallel data signal sent by the configurable amplitude-phase weighting unit in the digital beamforming circuit.

[0068] In this embodiment of the application, both the first deserializer and the second deserializer implement the conversion of serial data to parallel data, and both the first serializer and the second serializer implement the conversion of parallel data to serial data.

[0069] In implementation, when the antenna element is in receiving mode, the data signal is transmitted from the antenna element to the baseband chip. For example, a single digital beamforming circuit is used. The first deserializer of the first high-speed interface of the digital beamforming circuit receives the first serial data signal sent by the receiving array element of the antenna element. The first deserializer performs serial-to-parallel conversion on the received first serial data signal, converting it into a first parallel data signal. The first deserializer sends the converted first parallel data signal to a configurable amplitude-phase weighting unit. The target adder and target multiplier in the configurable amplitude-phase weighting unit perform amplitude-phase weighting processing on the first parallel data signal to obtain a second parallel data signal. The configurable amplitude-phase weighting unit sends the second parallel data signal to the second serializer of the second high-speed interface. The second serializer converts the received second parallel data signal into a second serial data signal representing the final data signal and sends it to the baseband chip.

[0070] When the antenna element is in the transmit state, the data signal is transmitted from the baseband chip to the antenna element. For example, using a single digital beamforming circuit, the second deserializer of the second high-speed interface of the digital beamforming circuit receives the third serial signal sent by the baseband chip. The second deserializer performs serial-to-parallel conversion on the received third serial data signal, converting it into a third parallel data signal. The second deserializer sends the converted third parallel data signal to a configurable amplitude-phase weighting unit. The target adder and target multiplier in the configurable amplitude-phase weighting unit perform amplitude-phase weighting processing on the third parallel data signal to obtain a fourth parallel data signal. The configurable amplitude-phase weighting unit sends the fourth parallel data signal to the first serializer of the first high-speed interface. The first serializer converts the received fourth parallel data signal into a fourth serial data signal representing the final data signal and sends the fourth serial data signal to the transmit element of the antenna element.

[0071] The above is a detailed description of the first high-speed interface and the second high-speed interface of the digital beamforming circuit provided in the embodiments of this application. The configurable amplitude and phase weighting unit in the digital beamforming circuit provided in the embodiments of this application is described below.

[0072] In one embodiment, as shown in Figures 1 and 2, the configurable amplitude-phase weighting unit 12 includes a multiplier unit 121 and an adder unit 122. The multiplier unit 121 is composed of N multipliers, and the adder unit 122 is composed of N adders.

[0073] Multiplier unit 121 is used to perform complex multiplication on the received parallel data signal according to the working mode and based on the amplitude-phase weighted vector, by multiplying N by the target multiplier among N multipliers to obtain a first operation result, wherein the parallel data signal includes a first parallel data signal or a third parallel data signal.

[0074] Adder unit 122 is used to perform complex addition on the second operation result by multiplying N by the target adder among N adders according to the working mode, so as to obtain a second parallel data signal. The second operation result includes one of the following: a first operation result, a first parallel data signal, and a third parallel data signal.

[0075] It should be noted that the first parallel data signal or the third parallel data signal input to the target adder are both sent by other digital beamforming circuits and represent the amplitude and phase weighting process values. This will be explained in detail below when introducing the interconnection and use of digital beamforming circuits.

[0076] In specific implementation, if only one digital beamforming circuit is used, the target adder performs complex addition on the first operation result. If multiple digital beamforming circuits are used, the subsequent digital beamforming circuit performs complex addition on the first parallel data signal representing the amplitude-phase weighting process value, or performs complex addition on the third parallel data signal representing the amplitude-phase weighting process value.

[0077] For any target multiplier, the target multiplier is used to perform complex multiplication on a first parallel data signal and its corresponding amplitude-phase weighting vector to obtain a first operation result, or to perform complex multiplication on a third parallel data signal and its corresponding amplitude-phase weighting vector to obtain a first operation result.

[0078] For any target adder, the target adder is used to perform complex addition on at least two first operation results, or to perform complex addition on a first parallel data signal representing the amplitude-phase weighted process value, or to perform complex addition on a third parallel data signal representing the amplitude-phase weighted process value.

[0079] In this embodiment, both the multiplier unit and the adder unit are configurable structures. The control unit determines the configuration information based on the working mode, and then configures the multiplier unit and the adder unit according to the configuration information. For example, if the control unit determines that 25 multipliers and 5 adders are needed based on the configuration information, then the control unit selects 5 rows and 5 columns of multipliers from the multiplier unit as the configured multiplier unit, which is the target multiplier. It also selects 5 adders in the first row from the adder unit as the configured adder unit, which is the target adder. The configured multiplier unit and the configured adder unit are used to perform complex multiplication and complex addition operations.

[0080] As shown in Figure 3, the configurable amplitude and phase weighting unit 12 may also include a register unit 123;

[0081] Register unit 123 is used to store some or all of the following: the first operation result, the second parallel data signal, and the fourth parallel data signal.

[0082] In this embodiment of the application, the register unit 123 in the configurable amplitude-phase weighting unit 12 stores part or all of the first operation result, the second parallel data signal and the fourth parallel data signal, so as to facilitate the operation of the multiplier unit 121 and the adder unit 122 in the configurable amplitude-phase weighting unit 12.

[0083] In practical implementation, N can be 32 or 64. When N equals 32, the digital beamforming circuit can handle a maximum of 32 phased array antennas and 32 beams. When N equals 64, the digital beamforming circuit can handle a maximum of 64 phased array antennas and 32 beams.

[0084] The digital beamforming circuit provided in this application embodiment has the flexible and reconfigurable characteristics of the configurable amplitude and phase weighting unit, which can adapt to different clock rates, different beam numbers, and different array element numbers to optimize power consumption and performance. The configurable amplitude and phase weighting unit is composed of a reconfigurable multiplier unit, a reconfigurable adder unit, and a register unit, all of which have configurable and reconfigurable characteristics.

[0085] For example, a typical standard reconfigurable multiplier unit consists of a series of 32x32 multiplier units. Each 32x32 multiplier unit, derived from the multiplication formula, comprises 16 9x9 multipliers, sign extension logic, and a coincidence extension controller, as shown in Figure 4. It can be configured to support multiplication operations of 16 8-bit, 4 16-bit, or 1 32-bit signed and unsigned numbers, as needed. For the 9x9 multiplier basic unit, further pipeline optimization, asynchronous circuit technology, and gated clocking techniques can be employed to reduce the power consumption of the basic multiplier unit. Based on the circuit structure in Figure 4, combined with clock management and network design, a high bit width and high clock configuration can be used when the data processing volume is large, while a low clock and small bit width approach can be used to meet the beamforming requirements of different bandwidth chips when the data volume is small.

[0086] The configurable amplitude and phase weighting unit 12 provided in this embodiment is designed as an N x N mirror symmetric architecture, that is, N multiplied by N multipliers and N multiplied by N adders, which ensures that the same set of hardware supports N antennas and N beam weighting, regardless of the transmission and reception mode. Considering chip power consumption, heat dissipation difficulty, chip yield, process node, performance and cost, a more reasonable N is 32 or 64. With the improvement of design capabilities, it may be developed to 128, 256, etc.

[0087] The above provides a detailed description of each part of the digital beamforming circuit provided in the embodiments of this application. The following provides a detailed description of the working mode and usage of the digital beamforming circuit.

[0088] In practical implementation, digital beamforming circuits can be used independently or interconnected. The operating modes of a digital beamforming circuit can include a first operating mode, a second operating mode, and a third operating mode. The control unit determines the operating mode of the digital beamforming circuit based on the number of beams, the number of antenna elements, and the configurable amplitude-phase weighting unit parameters. Specifically, if the number of elements is less than or equal to N, and the number of beams is less than or equal to N, the control unit determines the operating mode of the digital beamforming circuit as the first operating mode. If the number of beams is less than or equal to the configurable amplitude-phase weighting unit parameters, and the antenna element is in a receiving state, the control unit determines the operating mode of the digital beamforming circuit as either the first or second operating mode. If the number of beams is greater than the configurable amplitude-phase weighting unit parameters, and the antenna element is in a receiving state, the control unit determines the operating mode of the digital beamforming circuit as the third operating mode, the first operating mode, or the second operating mode.

[0089] Specifically, when the digital beamforming circuit operates in the first operating mode, both the target multiplier and the target adder in the amplitude-phase weighting unit can be configured to participate in the amplitude-phase weighting operation; when the digital beamforming circuit operates in the second operating mode, the multipliers in the amplitude-phase weighting unit can be bypassed, and only the target adder operates; when the digital beamforming circuit operates in the third operating mode, in addition to both the target multiplier and the target adder in the amplitude-phase weighting unit being configured to participate in the amplitude-phase weighting operation, the first high-speed interface or the second high-speed interface is also used to transmit data signals that have not undergone amplitude-phase weighting operation.

[0090] Furthermore, when the control unit determines that both the number of array elements and the number of beams are less than or equal to the configurable amplitude and phase weighting unit parameters, it determines to use one digital beamforming circuit. When the control unit determines that the number of beams is less than or equal to the configurable amplitude and phase weighting unit parameters and the antenna unit is in the receiving state, or when the control unit determines that the number of beams is greater than the configurable amplitude and phase weighting unit parameters and the antenna unit is in the receiving state, it determines to use multiple cascaded digital beamforming circuits.

[0091] The working modes and usage of digital beamforming circuits are explained in detail below.

[0092] When the number of array elements is less than or equal to the configurable amplitude and phase weighting unit parameters, and the number of beams is less than or equal to the configurable amplitude and phase weighting unit parameters, the control unit 11 determines the operating mode of the digital beamforming circuit as the first operating mode based on the number of beams, the number of array elements, and the configurable amplitude and phase weighting unit parameters. When the control unit determines the operating mode of the digital beamforming circuit as the first operating mode, if the antenna unit is in the receiving state, the control unit controls the configurable amplitude and phase weighting unit to perform complex multiplication on the first parallel data signal based on the amplitude and phase weighting vector to obtain multiple first operation results. Then, the multiple first operation results are subjected to complex addition to obtain the second parallel data signal.

[0093] If the antenna is in the transmitting state, the control unit controls the configurable amplitude and phase weighting unit to perform complex multiplication on the third parallel data signal based on the amplitude and phase weighting vector to obtain multiple first operation results. Then, the multiple first operation results are subjected to complex addition to obtain the fourth parallel data signal.

[0094] When the number of array elements is less than or equal to the configurable amplitude and phase weighting unit parameters, and the number of beams is less than or equal to the configurable amplitude and phase weighting unit parameters, only one digital beamforming circuit is needed. When the digital beamforming circuit operates in the first operating mode, the following describes the digital beamforming circuit under two conditions: when the antenna element is in the receiving state and when it is in the transmitting state.

[0095] As shown in Figure 5, when the antenna unit is in the receiving state, after the first high-speed interface 13 receives the first serial data signal, it performs serial-to-parallel conversion on the first serial data signal to obtain multiple first parallel data signals. The multiplier unit and adder unit in the configurable amplitude-phase weighting unit 12 perform amplitude-phase weighting processing on the multiple first parallel data signals based on the amplitude-phase weighting vector to obtain the second parallel data signal. The configurable amplitude-phase weighting unit 12 sends the second parallel data signal to the second high-speed interface 14. After receiving the second parallel data signal, the second high-speed interface 14 performs parallel-to-serial conversion on the second parallel data signal to obtain the second serial data signal. The second high-speed interface 14 sends the second serial data signal to the baseband chip.

[0096] Specifically, the control unit determines the number of multipliers and adders to use based on the antenna unit's transmit / receive status, the number of array elements, and the number of beams. For example, if the antenna unit is in receive mode, the number of receiving array elements is 108, and the number of beams is 52, the control unit determines that 5616 (52*108) multipliers and 5508 (51*108) adders are needed. In other words, the control unit determines the configuration information as 5616 multipliers and 5508 adders. The control unit selects 5616 multipliers as target multipliers from the multiplier unit and 5508 adders as target adders from the adder unit.

[0097] The first high-speed interface 13 converts the first serial data signal received from the antenna unit into a first parallel data signal. Then, the target multiplier performs complex multiplication on the first parallel data signal based on the amplitude-phase weighting vector to obtain a first operation result. The target adder performs complex addition on the first operation result to obtain a second parallel data signal. The second high-speed interface 14 performs parallel-to-serial conversion on the second parallel data signal to obtain a second serial data signal. The second high-speed interface 14 then sends the second serial data signal to the baseband chip.

[0098] As shown in Figure 6, when the antenna unit is in the transmitting state, the data signal received by the second high-speed interface 14 is the third serial data signal sent by the baseband chip. After receiving the third serial data signal, the second high-speed interface 14 performs serial-to-parallel conversion on the third serial data signal to obtain multiple third parallel data signals. The multiplier unit and adder unit in the configurable amplitude-phase weighting unit perform amplitude-phase weighting processing on the multiple third parallel data signals to obtain a fourth parallel data signal. The configurable amplitude-phase weighting unit sends the fourth parallel data signal to the first high-speed interface 13. The first high-speed interface 13 performs parallel-to-serial conversion on the fourth parallel data signal to obtain a fourth serial data signal. The first high-speed interface 13 sends the fourth serial data signal to the transmitting element of the antenna unit.

[0099] Specifically, the control unit determines the number of multipliers and adders to use based on the transmit / receive status of the antenna unit, the number of array elements, and the number of beams. For example, if the antenna unit is in transmit mode, the number of transmit array elements is 108, and the number of beams is 52, the control unit determines that 5616 (52*108) multipliers and 5508 (51*108) adders are needed. The control unit selects 5616 multipliers as target multipliers from the multiplier unit and 5508 adders as target adders from the adder unit.

[0100] The second high-speed interface 14 converts the received third serial data signal sent by the baseband chip into a third parallel data signal. Then, the target multiplier performs complex multiplication on the third parallel data signal based on the amplitude-phase weighting vector to obtain the first operation result. The target adder performs complex addition on the first operation result to obtain the fourth parallel data signal. The first high-speed interface 13 performs parallel-to-serial conversion on the fourth parallel data signal to obtain the fourth serial data signal. The first high-speed interface 13 sends the fourth serial data signal to the transmitting element of the antenna unit.

[0101] For example, if N equals 32, the number of beams is 8, and the number of array elements is 32, then with 32 array elements as input and 8 beams as output, 32 multipliers and 31 multipliers are needed. Since N equals 32, the multiplier unit in the digital beamforming circuit is 32 multipliers and the adder unit is 32 multipliers, which can meet the requirements of 32 multipliers and 31 multipliers.

[0102] With 8 beam inputs and 32 array elements, 8 x 32 multipliers and 7 x 32 adders are required. Since N equals 32, the digital beamforming circuit uses 32 x 32 multipliers and 32 x 32 adders, which satisfies the requirements of 8 x 32 multipliers and 7 x 32 adders. Therefore, when N equals 32, the number of beams is 8, and the number of array elements is 32, a single digital beamforming circuit can meet the requirements.

[0103] It should be noted that, as shown in Figures 5 and 6, the number of first high-speed interfaces 13 in this embodiment of the application can be M, and the number of second high-speed interfaces 14 can be K, where M and K are both positive integers greater than or equal to 1.

[0104] When the number of beams is less than or equal to the configurable amplitude and phase weighting unit parameters, and the number of array elements is greater than the configurable amplitude and phase weighting unit parameters, and the antenna element is in receiving mode, the digital beamforming circuit adopts a cascaded approach. In the cascaded digital beamforming circuit, the operating mode of the first-stage digital beamforming circuit is the first operating mode, and the operating mode of the subsequent-stage digital beamforming circuit is the second operating mode. The working principle of the digital beamforming circuit in the first operating mode can be referred to the above embodiment. The digital beamforming circuit in the second operating mode will be described in detail below.

[0105] It should be noted that in this application scenario, the digital beamforming circuit operating in the first mode outputs a second serial data signal that represents the amplitude-phase weighting process value.

[0106] When the digital beamforming circuit operates in the second operating mode, the control unit controls the multiplier unit in the configurable amplitude and phase weighting unit of the digital beamforming circuit to bypass, selects the target adder from the adder unit in the configurable amplitude and phase weighting unit, and performs complex addition on the first parallel data signal through the target adder to obtain the second parallel data signal.

[0107] For example, if the number of array elements is 108 and the number of beams is 52, and N equals 64, then the amplitude and phase weighting unit can be configured to include 4096 (64*64) multipliers and 4096 (64*64) adders. Obviously, using a single digital beamforming circuit cannot meet the computational requirements, so multiple digital beamforming circuits are required.

[0108] As shown in Figure 7, when the antenna unit is in the receiving state, each digital beamforming circuit in digital beamforming circuit 71 is a first-stage digital beamforming circuit, and each digital beamforming circuit in digital beamforming circuit 72 is a subsequent-stage digital beamforming circuit. The receiving array element in the antenna unit sends a first serial data signal to each first-stage digital beamforming circuit. For each first-stage digital beamforming circuit, the first high-speed interface in the first-stage digital beamforming circuit performs serial-to-parallel conversion on the first serial data signal to obtain a first parallel data signal. The target multiplier in the configurable amplitude-phase weighting unit performs complex multiplication on the first parallel data signal to obtain a first operation result. The target adder in the configurable amplitude-phase weighting unit performs complex addition on the first operation result to obtain a second parallel data signal representing the amplitude-phase weighting process value. The second high-speed interface performs parallel-to-serial conversion on the second parallel data signal to obtain a second serial data signal representing the amplitude-phase weighting process value, and sends the second serial data signal to the subsequent-stage digital beamforming circuit connected to the first-stage digital beamforming circuit.

[0109] It should be noted that in this application scenario, the first-stage digital beamforming circuit is the digital beamforming circuit directly connected to the antenna unit, and the subsequent-stage digital beamforming circuits are other digital beamforming circuits. For example, the subsequent-stage digital beamforming circuit 72 in Figure 7 includes multiple digital beamforming circuits connected in series. The first digital beamforming circuit in the series of multiple digital beamforming circuits is electrically connected to each first-stage digital beamforming circuit, and the last digital beamforming circuit in the subsequent-stage digital beamforming circuit is electrically connected to the baseband chip.

[0110] In this embodiment, the second serial data output by the first-stage digital beamforming circuit is a serial data signal characterizing the amplitude-phase weighting process value.

[0111] For each subsequent digital beamforming circuit, the first high-speed interface of the subsequent digital beamforming circuit performs serial-to-parallel conversion on the received second serial data signal representing the amplitude-phase weighting process value to obtain a first parallel data signal representing the amplitude-phase weighting process value. The target adder in the configurable amplitude-phase weighting unit of the subsequent digital beamforming circuit performs complex addition on the first parallel data signal to obtain a second parallel data signal. The second high-speed interface of the subsequent digital beamforming circuit performs parallel-to-serial conversion on the second parallel data signal to obtain a second serial data signal.

[0112] If the subsequent digital beamforming circuit is directly connected to the baseband chip, that is, the last subsequent digital beamforming circuit, then the second serial data signal output by the subsequent digital beamforming circuit is the final data signal. If the subsequent digital beamforming circuit is connected to other subsequent digital beamforming circuits, then the second serial data signal output by the subsequent digital beamforming circuit is a serial data signal representing the amplitude-phase weighting process value.

[0113] When the number of array elements is less than or equal to the configurable amplitude and phase weighting unit parameters, and the number of beams is greater than the configurable amplitude and phase weighting unit parameters, and the antenna element is in the transmit state, the digital beamforming circuit adopts a cascaded approach. In the cascaded digital beamforming circuit, the operating mode of the first-stage digital beamforming circuit is the first operating mode, and the operating mode of the subsequent-stage digital beamforming circuit is the second operating mode. The operating principle of the digital beamforming circuit in the first operating mode can be referred to the above embodiment, and the operating principle of the digital beamforming circuit in the second operating mode can be referred to the above embodiment, which will not be repeated here.

[0114] The following is a description using specific embodiments.

[0115] As shown in Figure 8, when the antenna unit is in the transmitting state, the digital beamforming circuit 81 is the first-stage digital beamforming circuit, and the digital beamforming circuit 82 is the second-stage digital beamforming circuit. The baseband chip sends a third serial data signal to each first-stage digital beamforming circuit. For each first-stage digital beamforming circuit, the second high-speed interface in the first-stage digital beamforming circuit performs serial-to-parallel conversion on the third serial data signal to obtain a third parallel data signal. The target multiplier in the configurable amplitude-phase weighting unit performs complex multiplication on the third parallel data signal to obtain a first operation result. The target adder in the configurable amplitude-phase weighting unit performs complex addition on the first operation result to obtain a fourth parallel data signal. The first high-speed interface performs parallel-to-serial conversion on the fourth parallel data signal to obtain a fourth serial data signal, and sends the fourth serial data signal to the second-stage digital beamforming circuit connected to the first-stage digital beamforming circuit.

[0116] It should be noted that the first-stage digital beamforming circuit is the digital beamforming circuit directly connected to the baseband chip, while the subsequent-stage digital beamforming circuits are other digital beamforming circuits. For example, the subsequent-stage digital beamforming circuit 82 in Figure 8 includes multiple digital beamforming circuits connected in series. The first subsequent-stage digital beamforming circuit in the series of multiple digital beamforming circuits is electrically connected to each first-stage digital beamforming circuit, and the last subsequent-stage digital beamforming circuit is electrically connected to the antenna element.

[0117] In this application scenario, the fourth serial data signal output by the first-stage digital beamforming circuit is a serial data signal that characterizes the amplitude-phase weighting process value.

[0118] For each subsequent digital beamforming circuit, the second high-speed interface of the subsequent digital beamforming circuit performs serial-to-parallel conversion on the received serial data signal to obtain a third parallel data signal. The target adder in the configurable amplitude and phase weighting unit of the subsequent digital beamforming circuit performs complex addition on the third parallel data signal to obtain a fourth parallel data signal. The first high-speed interface of the subsequent digital beamforming circuit performs parallel-to-serial conversion on the fourth parallel data signal to obtain a fourth serial data signal.

[0119] If the subsequent digital beamforming circuit is a subsequent digital beamforming circuit directly connected to the antenna element, i.e., the last subsequent digital beamforming circuit, then the fourth serial data signal output by this subsequent digital beamforming circuit is the final data signal. If the subsequent digital beamforming circuit is not directly connected to the antenna element, then the fourth serial data signal output by this subsequent digital beamforming circuit is a serial data signal representing the amplitude-phase weighting process value.

[0120] When the number of beams is greater than the configurable amplitude and phase weighting unit parameters, and the antenna unit is in receiving mode, the digital beamforming circuit adopts a cascaded approach. The cascaded digital beamforming circuit includes a first-stage digital beamforming circuit group and subsequent-stage digital beamforming circuits. The first-stage beamforming circuit group includes a first-stage digital beamforming circuit and a second-stage digital beamforming circuit. The first-stage digital beamforming circuit is connected to the antenna unit and is also connected to the second-stage digital beamforming circuit and the subsequent-stage digital beamforming circuit. The second-stage digital beamforming circuit is also electrically connected to the subsequent-stage digital beamforming circuit. If the cascaded digital beamforming circuit includes multiple subsequent-stage digital beamforming circuits, the multiple subsequent-stage digital beamforming circuits are connected in series. Among the multiple series-connected subsequent-stage digital beamforming circuits, the first subsequent-stage digital beamforming circuit is connected to each first-stage digital beamforming circuit and each second-stage digital beamforming circuit, and the last subsequent-stage digital beamforming circuit is also connected to the baseband chip.

[0121] The first-stage digital beamforming circuit operates in the third operating mode, the second-stage digital beamforming circuit operates in the first operating mode, and the subsequent-stage digital beamforming circuit operates in the second operating mode.

[0122] The first and second working modes can be referred to in the above embodiments. The third working mode will be described below.

[0123] When the digital beamforming circuit operates in the third operating mode and the antenna unit is in the receiving state, the first high-speed interface of the digital beamforming circuit performs serial-to-parallel conversion on the received first serial data signal to obtain a first parallel data signal. The configurable amplitude-phase weighting unit performs amplitude-phase weighting processing on a portion of the first parallel data signal to obtain a second parallel data signal representing the amplitude-phase weighting process value. The second high-speed interface in the first-stage digital beamforming circuit performs parallel-to-serial conversion on the second parallel data signal representing the amplitude-phase weighting process value to obtain a second serial data signal representing the amplitude-phase weighting process value, and sends the obtained second serial data signal representing the amplitude-phase weighting process value to the subsequent digital beamforming circuit.

[0124] The second high-speed interface of the first-stage data beamforming circuit performs parallel-to-serial conversion on other first parallel data signals (other first parallel data signals are those that have not passed through the configurable amplitude and phase weighting unit in the first-stage data beamforming circuit) and sends them to the second-stage digital beamforming circuit connected to the digital beamforming circuit. That is, the first-stage digital beamforming circuit does not perform amplitude and phase weighting processing on other first parallel data signals, but converts them into serial data signals and transmits the converted serial data signals to the second-stage digital beamforming circuit, which then performs amplitude and phase weighting processing on the received other first parallel data signals.

[0125] The second-stage digital beamforming circuit performs amplitude and phase weighting processing on the other received first parallel data signals to obtain a second parallel data signal representing the amplitude and phase weighting process value. This second parallel data signal is then converted from parallel to serial through the second high-speed interface of the digital beamforming circuit to obtain a second serial data signal representing the amplitude and phase weighting process value. This second serial data signal representing the amplitude and phase weighting process value is then sent to the subsequent digital beamforming circuit connected to the second-stage digital beamforming circuit.

[0126] As shown in Figure 9, when the antenna unit is in the receiving state, digital beamforming circuit 91 and digital beamforming circuit 92 constitute the first-stage digital beamforming circuit group. Among them, digital beamforming circuit 91 is the first-stage digital beamforming circuit in the first-stage digital beamforming circuit group, digital beamforming circuit 92 is the second-stage digital beamforming circuit in the digital beamforming circuit group, and digital beamforming circuit 93 is the subsequent-stage digital beamforming circuit.

[0127] The receiving element in the antenna unit sends a first serial data signal to the first-stage digital beamforming circuit 91. After receiving the first serial data signal, the first high-speed interface in the first-stage digital beamforming circuit 91 performs serial-to-parallel conversion on the first serial data signal to obtain a first parallel data signal. The configurable amplitude and phase weighting unit in the first-stage digital beamforming circuit 91 performs amplitude and phase weighting processing on a portion of the first parallel data signal to obtain a second parallel data signal characterizing the amplitude and phase weighting process value. The second high-speed interface in the first-stage digital beamforming circuit 91 performs parallel-to-serial conversion on other first parallel data signals and outputs the serial data signal after parallel-to-serial conversion to the second-stage digital beamforming circuit 82. The second high-speed interface in the first-stage digital beamforming circuit 91 performs parallel-to-serial conversion on the second parallel data signal and outputs the serial data signal after parallel-to-serial conversion to the subsequent digital beamforming circuit 93.

[0128] After receiving the serial data signal after parallel-to-serial conversion, the second-stage digital beamforming circuit 92 performs serial-to-parallel conversion on the received serial data signal through the first high-speed interface to obtain a first parallel data signal. The configurable amplitude and phase weighting unit performs amplitude and phase weighting processing on the first parallel data signal to obtain a second parallel data signal representing the amplitude and phase weighting process value. The second high-speed interface of the second-stage digital beamforming circuit 92 performs parallel-to-serial conversion on the second parallel data signal representing the amplitude and phase weighting process value and sends the serial data signal after parallel-to-serial conversion to the subsequent digital beamforming circuit.

[0129] It should be noted that the parallel-to-serial conversion data signals output by the first-stage digital beamforming circuit 91 and the second-stage digital beamforming circuit 92 are both serial data signals representing the amplitude-phase weighting process values.

[0130] After receiving the serial data signal after parallel-to-serial conversion, the other digital beamforming circuits in the subsequent digital beamforming circuit 93 (excluding the last digital beamforming circuit) perform serial-to-parallel conversion on the received serial data signal to obtain a first parallel data signal. The configurable amplitude-phase weighting unit performs complex addition on the first parallel data signal to obtain a second parallel data signal representing the amplitude-phase weighting process value. The second high-speed interface in the subsequent digital beamforming circuit 93 performs parallel-to-serial conversion on the second parallel data signal representing the amplitude-phase weighting process value to obtain a second serial data signal representing the amplitude-phase weighting process value.

[0131] The last digital beamforming circuit in the subsequent digital beamforming circuit 93 receives the second serial data signal representing the amplitude-phase weighting process value, performs serial-to-parallel conversion on the second serial data signal representing the amplitude-phase weighting process value to obtain the first parallel data signal, and the configurable amplitude-phase weighting unit performs complex addition on the first parallel data signal to obtain the second parallel data signal. The second high-speed interface performs parallel-to-serial conversion on the second parallel data signal to obtain the second serial data signal representing the final data signal, and sends the second serial data signal representing the final data signal to the baseband chip.

[0132] When the number of array elements is greater than the configurable amplitude and phase weighting unit parameters, and the antenna unit is in the transmit state, the digital beamforming circuit adopts a cascaded approach. The cascaded digital beamforming circuit includes a first-stage digital beamforming circuit group and subsequent-stage digital beamforming circuits. The first-stage beamforming circuit group includes a first-stage digital beamforming circuit and a second-stage digital beamforming circuit. The first-stage digital beamforming circuit is connected to the baseband chip and is also connected to the second-stage digital beamforming circuit and the subsequent-stage digital beamforming circuit. If the cascaded digital beamforming circuit includes multiple subsequent-stage digital beamforming circuits, the multiple subsequent-stage digital beamforming circuits are connected in series. Among the multiple series-connected subsequent-stage digital beamforming circuits, the first subsequent-stage digital beamforming circuit is connected to each first-stage digital beamforming circuit and each second-stage digital beamforming circuit, and the last subsequent-stage digital beamforming circuit is also connected to the antenna unit.

[0133] The first-stage digital beamforming circuit operates in the third operating mode, the second-stage digital beamforming circuit operates in the first operating mode, and the subsequent-stage digital beamforming circuit operates in the second operating mode.

[0134] The first working mode, the second working mode, and the third working mode can refer to the above embodiments, and the repeated parts will not be described again.

[0135] The following detailed description uses specific embodiments.

[0136] As shown in Figure 10, when the antenna unit is in the transmitting state, digital beamforming circuit 101 and digital beamforming circuit 102 constitute the first-stage digital beamforming circuit group. Among them, digital beamforming circuit 101 is the first-stage digital beamforming circuit in the first-stage digital beamforming circuit group, digital beamforming circuit 102 is the second-stage digital beamforming circuit in the digital beamforming circuit group, and digital beamforming circuit 103 is the subsequent-stage digital beamforming circuit.

[0137] The baseband chip sends a third serial data signal to the first-stage digital beamforming circuit 101. After receiving the third serial data signal, the second high-speed interface in the first-stage digital beamforming circuit 101 performs serial-to-parallel conversion on the third serial data signal to obtain a third parallel data signal. The configurable amplitude and phase weighting unit in the first-stage digital beamforming circuit 101 performs amplitude and phase weighting processing on a portion of the third parallel data signal to obtain a fourth parallel data signal characterizing the amplitude and phase weighting process value. The first high-speed interface in the first-stage digital beamforming circuit 101 performs parallel-to-serial conversion on the other third parallel data signals and outputs the serial data signal after parallel-to-serial conversion to the second-stage digital beamforming circuit 102.

[0138] The first high-speed interface in the first-stage digital beamforming circuit 101 performs parallel-to-serial conversion on the fourth parallel data signal representing the amplitude-phase weighting process value to obtain the fourth serial data signal representing the amplitude-phase weighting process value, and outputs the fourth serial data signal representing the amplitude-phase weighting process value to the subsequent digital beamforming circuit 103.

[0139] After receiving the serial data signal after parallel-to-serial conversion, the second-stage digital beamforming circuit 102 performs serial-to-parallel conversion on the received serial data signal to obtain a third parallel data signal. An configurable amplitude-phase weighting unit performs amplitude-phase weighting processing on the third parallel data signal to obtain a fourth parallel data signal representing the amplitude-phase weighting process value. The first high-speed interface of the second-stage digital beamforming circuit 102 performs parallel-to-serial conversion on the fourth parallel data signal representing the amplitude-phase weighting process value to obtain a fourth serial data signal representing the amplitude-phase weighting process value, and sends the fourth serial data signal representing the amplitude-phase weighting process value to the subsequent digital beamforming circuit.

[0140] In this embodiment of the application, the parallel-to-serial converted data signals output by the first-stage digital beamforming circuit 101 and the second-stage digital beamforming circuit 102 are both data signals representing the amplitude-phase weighting process values.

[0141] After receiving the fourth serial data signal representing the amplitude-phase weighting process value, the other downstream digital beamforming circuits in the downstream digital beamforming circuit 103 (excluding the last downstream digital beamforming circuit) perform serial-to-parallel conversion on the received fourth serial data signal representing the amplitude-phase weighting process value to obtain a third parallel data signal representing the amplitude-phase weighting process value. The configurable amplitude-phase weighting unit performs complex addition on the third parallel data signal representing the amplitude-phase weighting process value to obtain a fourth parallel data signal representing the amplitude-phase weighting process value. The first high-speed interface in the downstream digital beamforming circuit 103 performs parallel-to-serial conversion on the fourth parallel data signal representing the amplitude-phase weighting process value to obtain a fourth serial data signal representing the final data signal, and sends the fourth serial data signal representing the final data signal to the antenna unit.

[0142] In one embodiment, as shown in FIG11, the digital beamforming circuit provided in this application embodiment further includes a data buffer unit 24;

[0143] The data buffer unit 24 is used to store some or all of the following parallel data signals: a first parallel data signal, a second parallel data signal, a third parallel data signal, and a fourth parallel data signal, and to send the stored first parallel data signal or the third parallel data signal to the configurable amplitude and phase weighting unit 12, or to send the stored second parallel data signal to the second high-speed interface 14, and to send the stored fourth parallel data signal to the first high-speed interface 13.

[0144] As shown in Figure 11, the digital beamforming circuit provided in this embodiment of the application further includes a data synchronization unit 15;

[0145] The data synchronization unit 15 is used to synchronize the first parallel data signal stored in the data buffer unit 24, the third parallel data signal stored in the data buffer unit 24, the second parallel data signal stored in the data storage unit 24, and the fourth parallel data signal stored in the data storage unit 24.

[0146] In this embodiment, the data caching unit 24 stores the data, and the data synchronization unit 15 synchronizes the stored data, thereby enabling the synchronization of data received from different first high-speed interfaces or different second high-speed interfaces, and improving the performance of the digital beamforming circuit.

[0147] The digital beamforming circuit provided in this application embodiment can be applied to a phased array terminal. When the phased array terminal is working in the receiving array (the antenna unit is in the receiving state), the data from the antenna channel is deserialized in the first high-speed interface. After data storage, data alignment, rate conversion, and data interception processing are performed by the data buffer unit 24 and the data synchronization unit 15, the data received by different high-speed interfaces is synchronized. The data is then sent to the configurable amplitude and phase weighting unit 12, which is composed of a multiplier unit (N x N), an adder unit (N x N), and a register unit, for amplitude and phase weighting and beamforming of the signal. The final result data is sent to the serializer in the second high-speed interface and transmitted to the subsequent digital beamforming chip for further beamforming processing or transmitted to the baseband chip for processing.

[0148] When the phased array terminal is operating in the transmit array (antenna unit is in transmit state), the data from the baseband chip or the front-end digital beamforming circuit is deserialized through the second high-speed interface, and then sent to the configurable amplitude and phase weighting unit 12 (N x N) for signal power division and amplitude and phase weighting after passing through the data buffer unit 24 and the data synchronization unit 15. Finally, the weighted data of each channel is transmitted to the next stage digital beamforming circuit for processing or to the antenna channel (antenna unit) for processing through the serializer of the first high-speed interface.

[0149] For example, with 108 receiving elements and 52 beams, when the phased array terminal is in receiving mode, the 108 receiving elements receive data signals. The data signals received by each element are processed by each antenna channel, and the serial data signals processed by each antenna channel are sent to the first high-speed interface of the digital beamforming circuit. The first deserializer in the first high-speed interface converts the received serial data signals into parallel data signals. After the data signals sent by the 108 antenna channels are all converted from serial to parallel, they are processed by the data storage unit and the data synchronization unit. Complex multiplication is performed using 5616 multipliers, and then the results of the complex multiplication are added using 5508 adders to obtain the data signal corresponding to the beam.

[0150] The digital beamforming circuit provided in this application embodiment supports data pass-through and multi-level beamforming through high-speed interfaces (first high-speed interface and second high-speed interface), on-chip data buffer and inter-chip synchronization mechanism. It is not limited by the array element scale and the number of beams, and can meet the needs of thousands of array elements and hundreds of beams of spaceborne digital phased array. When the number of antennas and the number of beams are both ≤N, a single digital beamforming chip can complete beamforming.

[0151] However, antenna arrays are typically large, with hundreds or even thousands of elements. In scenarios where the number of beams is ≤ N and the number of array elements is > N, multiple digital beamforming chips need to be cascaded to complete beamforming, as shown in Figures 7 and 8. The first-stage digital beamforming chip operates in the first working mode. Each first-stage digital beamforming chip completes complex multiplication and addition operations on M beams of at least N antenna elements. The amplitude and phase weighting process values ​​of the M beams are transmitted to the subsequent digital beamforming chips through a high-speed interface (either the first or second high-speed interface). The subsequent digital beamforming chips are all configured in the second working mode. The control unit in the subsequent digital beamforming chip bypasses the multiplier unit and is in a turned-off state. The target adder in the adder unit completes the accumulation of the amplitude and phase weighting process values ​​output by the multiple first-stage data beamforming chips to form M final synthesized beams, which are output through the high-speed interface (either the first or second high-speed interface).

[0152] In scenarios where the number of beams is greater than N, the number of beams supported by a single digital beamforming chip is less than the system requirements. In this case, it is necessary to transmit the data of the same antenna element to multiple digital beamforming chips, as shown in Figures 9 and 10. The digital beamforming chip in the first-stage digital beamforming chip group that is directly connected to the antenna channel is used as the first-stage digital beamforming chip, and the working mode of the first-stage digital beamforming chip is configured as the third working mode. The serial port data entering the first-stage digital beamforming chip is both stored in the buffer and directly transmitted through the serial port to the second-stage digital beamforming chip used to implement MN beams. Depending on the number of beams, the number of chips that need to be configured as the third working mode may vary. Finally, the amplitude and phase weighted process values ​​output by the first-stage digital beamforming chip and the amplitude and phase weighted process values ​​output by the second-stage digital beamforming chip are both sent to the subsequent digital beamforming chips. The subsequent processing and configuration are similar to the previous cases and will not be repeated here.

[0153] In one embodiment, as shown in FIG11, the digital beamforming circuit provided in this application embodiment further includes a high-speed configuration interface 16 and a configuration data storage unit 17.

[0154] High-speed configuration interface 16 is used to receive the elevation angle and azimuth angle corresponding to the first serial data signal;

[0155] Configure data storage unit 17 for storing pitch angle and azimuth angle;

[0156] The control unit 11 is also used to determine the amplitude-phase weighting vector corresponding to the first serial data signal based on the pitch angle and azimuth angle.

[0157] High-speed configuration interface 16 is used to receive the elevation and azimuth angles corresponding to the third serial data signal;

[0158] Configure data storage unit 17 for storing pitch angle and azimuth angle;

[0159] The control unit 11 is also used to determine the amplitude and phase weighting vector corresponding to the third serial data signal based on the pitch angle and azimuth angle.

[0160] In practice, the high-speed configuration interface 16 can be reused using either the first high-speed interface 13 or the second high-speed interface 14, thereby reducing the number of high-speed interfaces and lowering costs.

[0161] In this embodiment, the pitch angle and azimuth angle are received through the high-speed configuration interface 16, and the pitch angle and azimuth angle are stored through the configuration data storage unit 17. The control unit calculates the amplitude-phase weighting vector based on the pitch angle and azimuth angle stored in the configuration data storage unit 17, so as to use it when performing amplitude-phase weighting processing on the first parallel data signal or the third parallel data signal. The method for calculating the amplitude-phase weighting vector based on the pitch angle and azimuth angle can refer to the calculation method provided in related technologies, and the repeated parts will not be described again.

[0162] The digital beamforming circuit provided in this application embodiment can adopt a flexible and configurable architecture for some high-speed interfaces (first high-speed interface 13, second high-speed interface 14, and high-speed configuration interface 16), as shown in Figure 12. The high-speed interface includes a link layer and a physical layer. The link layer supports multiple protocols, such as JESD204B / C and CPRI. Different protocols can be switched through high-level interface configuration and management, so that a set of low-level interfaces can meet the requirements of multiple high-speed transmission protocols. This can reduce the number of interfaces and meet various application scenarios such as multi-level beamforming, beam information and baseband data front-pass, and multi-beam data transparent transmission.

[0163] The JESD204B / C interface protocol is based on standard specifications and supports 8 / 10 or 64 / 66 encoding and decoding through coding control, adapting to the requirements of two protocol specifications. The CPRI interface protocol is optimized based on standard specifications and combined with the actual requirements of satellite beam generation. It mainly includes I / Q data mapping, demapping, framing and deframing, delay calibration, etc.

[0164] In practical implementation, the CPRI interface can be used for inter-stage connections of cascaded digital beamforming circuits to transmit signals characterizing amplitude and phase weighting process values. It can also be used to transmit amplitude and phase weighting vectors and configuration information, and can be connected to baseband chips. The JESD204B / C interface can be used for inter-stage connections of cascaded digital beamforming circuits to transmit signals characterizing amplitude and phase weighting process values. It can also be connected to antenna channels, and the number of channels can be optimized to match different data rate transmission requirements.

[0165] In this embodiment of the application, a single underlying interface can adapt to multiple high-speed transmission protocols, thus saving the number of high-speed interfaces.

[0166] In one embodiment, as shown in FIG11, the digital beamforming circuit provided in this application embodiment further includes some or all of the following: a telemetry and remote control unit 18, a clock reset and synchronization unit 19, a predistortion compensation and calibration unit 20, a low-speed interface 21, and an auxiliary unit 22, wherein:

[0167] The telemetry and remote control unit 18 is used to back up telemetry observations and remote control information;

[0168] The clock reset synchronization unit 19 is used to manage the clock signal and the reset signal, and to synchronize the high-speed interface and the high-speed configuration interface.

[0169] The pre-distortion compensation calibration unit 20 is used to improve the linearity of the power amplifier, compensate for channel delay, and calibrate the amplitude and phase imbalance of the quadrature branch in peak-to-average power ratio mode.

[0170] The low-speed interface 21 is used to transmit debugging information, temperature detection information, and monitoring information.

[0171] Auxiliary unit 22 is used for managing power supply and / or sensing temperature.

[0172] The digital beamforming circuit provided in this application comprehensively balances the multi-dimensional constraints of beamforming chip versatility, performance, cost, reliability, and yield. It proposes a general digital beamforming chip structure and implementation method. Combined with different application requirements, it can flexibly design configurable amplitude and phase weighted networks with different number of interfaces, interface rates, and different scales according to process characteristics, thereby optimizing the chip's versatility, advancement, and economy.

[0173] Based on the same inventive concept, this application also provides a phased array terminal. The principle of the phased array terminal in solving the problem is similar to that of the digital beamforming circuit described above, and the repeated parts will not be described again.

[0174] Figure 13 shows a schematic diagram of a phased array terminal provided in an embodiment of this application. The phased array terminal includes an antenna unit 1301, a baseband chip 1303, and any of the digital beamforming circuits 1302 described above.

[0175] Antenna unit 131, at least one digital beamforming circuit 1302 and baseband chip 1303 are connected in sequence.

[0176] In a specific implementation, the antenna unit 1301 is used to send a first serial data signal to the digital beamforming circuit 1302 when the phased array terminal is in the receiving state, or to receive a fourth serial data signal sent by the digital beamforming circuit 1302 when it is in the transmitting state.

[0177] The baseband chip 1303 is used to receive the second serial data signal sent by the digital beamforming circuit 1302 when the phased array terminal is in the receiving state, or to send the third serial data signal to the digital beamforming circuit 1302 when the phased array terminal is in the transmitting state.

[0178] The antenna unit includes array elements and antenna channels. The array elements can transmit the received data to the digital beamforming circuit through the antenna channels, and the array elements can also transmit the data received by the digital beamforming circuit through the antenna channels to other phased array terminals.

[0179] In the phased array terminal shown in Figure 13, the digital beamforming circuit 1302 can be a single digital beamforming circuit or multiple digital beamforming circuits interconnected. For details, please refer to the implementation of the digital beamforming circuit described above; repeated details will not be repeated.

[0180] The digital beamforming circuit and phased array terminal provided in this application embodiment, through symmetrical design and reconfigurable circuit, utilizes control unit and high-performance buffer and synchronization mechanism, with the advantages of low cost, low power consumption and high performance, while also taking into account versatility and flexibility, and adapting to different array modes, array element scale, beam number and signal bandwidth applications.

[0181] The configurable amplitude and phase weighting unit includes a multiplier unit, an adder unit, and a register unit. It is designed as an N*N symmetric network architecture, with N being 32 or 64. This means it can handle a maximum of 32 antennas and 32 beams, or a maximum of 64 antennas and 32 beams. When the number of beams is small or the number of antennas is reduced, the beamforming computing resources can be adjusted based on the underlying reconfigurable multiplier unit, reconfigurable adder unit, and register unit to maximize the utilization of chip resources.

[0182] Based on the controllable and configurable internal circuitry, the digital beamforming chip can be configured in the first, third, and second operating modes to meet different applications such as multi-level beamforming and multi-chip collaborative multi-level beamforming.

[0183] This invention proposes a reconfigurable high-speed interface architecture and circuit, which decouples the physical layer circuit from the protocol, supports multiple protocols at the link layer, such as JESD204B / C and CPRI, and enables switching between different link protocols through high-level interface configuration and management. A single low-level interface can meet the needs of adapting to multiple high-speed transmission protocols, thus reducing the number of interfaces.

[0184] This invention proposes a standard reconfigurable multiplier unit that flexibly configures a standard 32*32 multiplier unit into a configuration consisting of 16 9*9 multipliers, conformal extension logic, and a conformal extension controller. This configuration is configurable as needed, supporting multiplication operations of 16 8-bit, 4 16-bit, or 1 32-bit signed and unsigned numbers. For the 9*9 multiplier basic unit, further optimization techniques such as pipelined architecture, asynchronous circuitry, and gated clocking can be employed to reduce the power consumption of the multiplier basic unit, allowing for adjustment of power consumption based on different signal bandwidths.

[0185] This application provides a digital beamforming circuit or chip that comprehensively balances the multi-dimensional constraints of beamforming chip versatility, performance, cost, reliability, and yield. It proposes a general digital beamforming chip structure and implementation method. Combined with different application requirements, it can flexibly design configurable amplitude and phase weighting units with different number of interfaces, interface rates, and different scales according to process characteristics, thereby optimizing the chip's versatility, advancement, and economy.

[0186] The present application has been described above with reference to block diagrams and / or flowcharts illustrating methods, apparatus (systems), and / or computer program products according to embodiments of the present application. It should be understood that a block of a block diagram and / or flowchart, as well as combinations of blocks of block diagrams and / or flowcharts, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, and / or other programmable data processing means to produce a machine, such that the instructions, executable via the computer processor and / or other programmable data processing means, create methods for implementing the functions / actions specified in the blocks of the block diagrams and / or flowcharts.

[0187] Accordingly, this application can also be implemented using hardware and / or software (including firmware, resident software, microcode, etc.). Furthermore, this application can take the form of a computer program product on a computer-usable or computer-readable storage medium, having computer-usable or computer-readable program code implemented in the medium for use by or in conjunction with an instruction execution system. In the context of this application, a computer-usable or computer-readable medium can be any medium that can contain, store, communicate, transmit, or deliver a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0188] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A digital beamforming circuit, characterized in that, include: Control unit, first high-speed interface, second high-speed interface, and configurable amplitude and phase weighting unit; The configurable amplitude and phase weighting unit is connected to the control unit, the first high-speed interface, and the second high-speed interface; The control unit is used to determine the operating mode of the digital beamforming circuit based on the number of beams, the number of antenna elements, and the configurable amplitude and phase weighting unit parameters. The first high-speed interface is used to convert the received first serial data signal into a first parallel data signal, wherein the first serial data signal is transmitted by the antenna unit or other digital beamforming circuit. The configurable amplitude-phase weighting unit includes N multipliers and N multipliers. Based on the operating mode, the configurable amplitude-phase weighting unit performs amplitude-phase weighting processing on the first parallel data signal using a target multiplier from the N multipliers and a target adder from the N multipliers to obtain a second parallel data signal. The amplitude-phase weighting processing includes complex multiplication and / or complex addition operations. N is a parameter of the configurable amplitude-phase weighting unit, and N is a positive integer greater than or equal to 1. The second high-speed interface is used to convert the second parallel data signal into a second serial data signal and send the second serial data signal to the baseband chip or other digital beamforming circuit.

2. The circuit as described in claim 1, characterized in that, When both the number of array elements and the number of beams are less than or equal to the configurable amplitude and phase weighting unit parameters, the operating mode of the digital beamforming circuit is the first operating mode. The configurable amplitude-phase weighting unit is specifically used for: Based on the first working mode, the target multiplier and the target adder are determined; Based on the amplitude-phase weighted vector, the first parallel data signal is multiplied by the target multiplier to obtain multiple first operation results; The second parallel data signal is obtained by performing complex addition on the plurality of first operation results through the target adder.

3. The circuit as described in claim 1, characterized in that, When the number of beams is less than or equal to the configurable amplitude and phase weighting unit parameters, and the antenna unit is in a receiving state, if the digital beamforming circuit is the first stage in a cascaded digital beamforming circuit, then the operating mode of the digital beamforming circuit is the first operating mode. The configurable amplitude-phase weighting unit is specifically used for: Based on the first working mode, the target multiplier and the target adder are determined; Based on the amplitude-phase weighted vector, the target multiplier performs complex multiplication on the first parallel data signal to obtain multiple first operation results; The second parallel data signal is obtained by performing complex addition on the plurality of first operation results through the target adder.

4. The circuit as described in claim 3, characterized in that, If the digital beamforming circuit is located in the later stage of a cascaded digital beamforming circuit, then the operating mode of the digital beamforming circuit is the second operating mode. The configurable amplitude-phase weighting unit is specifically used for: Based on the second working mode, the target adder is determined; The second parallel data signal is obtained by performing complex addition on the first parallel data signal using the target adder.

5. The circuit as described in claim 1, characterized in that, When the number of beams is greater than the configurable amplitude and phase weighting unit parameters, and the antenna unit is in a receiving state, if the digital beamforming circuit is located in the first stage of the first-stage digital beamforming circuit group, then the operating mode of the digital beamforming circuit is the third operating mode. The configurable amplitude-phase weighting unit is specifically used for: Based on the third working mode, the target multiplier and target adder are determined; Based on the amplitude-phase weighted vector, the target multiplier performs complex multiplication on a portion of the first parallel data signal to obtain multiple first operation results. The second parallel data signal is obtained by performing complex addition on the plurality of first operation results through the target adder. The second high-speed interface is also used for: The other first parallel data signals are converted from parallel to serial, and the serial data signals obtained by the conversion are sent to the second-level digital beamforming circuit in the first-level digital beamforming circuit group.

6. The circuit as described in claim 5, characterized in that, If the digital beamforming circuit is located in the second stage of the first-stage digital beamforming circuit group, then the operating mode of the digital beamforming circuit is the first operating mode. The configurable amplitude-phase weighting unit is specifically used for: Based on the first working mode, the target multiplier and the target adder are determined; Based on the amplitude-phase weighted vector, the target multiplier performs complex multiplication on the first parallel data signal to obtain multiple first operation results; The second parallel data signal is obtained by performing complex addition on the plurality of first operation results through the target adder.

7. The circuit as described in claim 6, characterized in that, If the digital beamforming circuit is located in the later stage of a cascaded digital beamforming circuit, then the operating mode of the later stage digital beamforming circuit is the second operating mode. The configurable amplitude-phase weighting unit is specifically used for: Based on the second working mode, the target adder is determined; The second parallel data signal is obtained by performing complex addition on the first parallel data signal using the target adder.

8. The circuit as described in any one of claims 2, 3, 5, and 6, characterized in that, The configurable amplitude-phase weighting unit also includes a register unit; The register unit is used to store the first calculation result and / or the second parallel data signal.

9. The circuit as described in claim 1, characterized in that, The first high-speed interface includes a first deserializer; The first deserializer is used to convert the first serial data signal into the first parallel data signal; The second high-speed interface includes a second serializer; The second serializer is used to convert the second parallel data signal into the second serial data signal.

10. The circuit as described in claim 8, characterized in that, It also includes a data caching unit; The data buffer unit is used to store the first parallel data signal and / or the second parallel data signal.

11. The circuit as described in claim 10, characterized in that, It also includes a data synchronization unit; The data synchronization unit is used to synchronize the first parallel data signal stored in the data cache unit, and / or synchronize the second parallel data signal stored in the data cache unit.

12. The circuit as described in claim 11, characterized in that, It also includes a high-speed configuration interface and a configuration data storage unit; The high-speed configuration interface is used to receive the pitch angle and azimuth angle corresponding to the first serial data signal; The configuration data storage unit is used to store the pitch angle and azimuth angle; The control unit is also used for: The amplitude-phase weighted vector is determined based on the pitch angle and the azimuth angle.

13. The circuit as described in claim 12, characterized in that, It also includes some or all of the following: telemetry and remote control unit, clock reset and synchronization unit, pre-distortion compensation and calibration unit, low-speed interface, and auxiliary unit; The telemetry and remote control unit is used to back up telemetry observations and remote control information; The clock reset synchronization unit is used to manage the clock signal and the reset signal, and to synchronize the first high-speed interface and the high-speed configuration interface, or to synchronize the second high-speed interface and the high-speed configuration interface. The pre-distortion compensation calibration unit is used to perform delay compensation on the data channel and to calibrate the amplitude-phase imbalance of the orthogonal branch in peak-to-average ratio mode. The low-speed interface is used to transmit debugging information, temperature detection information, and monitoring information; The auxiliary unit is used to manage the power supply and / or the sensing temperature.

14. A digital beamforming circuit, characterized in that, include: Control unit, first high-speed interface, second high-speed interface, and configurable amplitude and phase weighting unit; The configurable amplitude and phase weighting unit is connected to the control unit, the first high-speed interface, and the second high-speed interface; The control unit is used to determine the operating mode of the digital beamforming circuit based on the number of beams, the number of antenna elements, and the configurable amplitude and phase weighting unit parameters. The second high-speed interface is used to convert the received third serial data signal into a third parallel data signal, wherein the third serial data signal is sent by the baseband chip or other digital beamforming circuit; The configurable amplitude-phase weighting unit includes N multipliers and N multipliers. Based on the operating mode, the configurable amplitude-phase weighting unit performs amplitude-phase weighting processing on the third parallel data signal using a target multiplier from the N multipliers and a target adder from the N multipliers to obtain a fourth parallel data signal. The amplitude-phase weighting processing includes complex multiplication and / or complex addition operations. N is a parameter of the configurable amplitude-phase weighting unit, and N is a positive integer greater than or equal to 1. The first high-speed interface is used to convert the fourth parallel data signal into a fourth serial data signal and send the fourth serial data signal to the antenna unit or other digital beamforming circuit.

15. The circuit as described in claim 14, characterized in that, When both the number of array elements and the number of beams are less than or equal to the configurable amplitude and phase weighting unit parameters, the operating mode of the digital beamforming circuit is the first operating mode. The configurable amplitude-phase weighting unit is specifically used for: Based on the first working mode, the target multiplier and the target adder are determined; Based on the amplitude-phase weighted vector, the target multiplier performs complex multiplication on the third parallel data signal to obtain multiple first operation results; The target adder performs complex addition on the multiple first operation results to obtain the fourth parallel data signal.

16. The circuit as described in claim 14, characterized in that, The first high-speed interface includes a first serializer; The first serializer is used to convert the fourth parallel data signal into the fourth serial data signal; The second high-speed interface includes a second deserializer; The second deserializer is used to convert the third serial data signal into the third parallel data signal.

17. A phased array terminal, characterized in that, Includes an antenna unit, a baseband chip, and at least one digital beamforming circuit as described in any one of claims 1 to 16; The antenna unit, the at least one digital beamforming circuit, and the baseband chip are connected in sequence.

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