Semiconductor device and manufacturing method therefor

Abstract

The present application relates to the technical field of semiconductors. Disclosed are a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a semiconductor substrate, wherein an epitaxial layer is provided on the surface on one side of the semiconductor substrate; a well region is provided in the surface on the side of the epitaxial layer that faces away from the semiconductor substrate; two first trenches and a second trench located between the first trenches are provided in the surface on the side of the epitaxial layer that faces away from the semiconductor substrate, and the depths of the first trenches and the second trench are both greater than the depth of the well region; a trench source electrode is provided in each first trench; a trench gate electrode is provided in the second trench; each trench source electrode comprises first source electrode regions and second source electrode regions, which are alternately distributed in the lengthwise direction of a first trench; and each trench source electrode is correspondingly provided with a first masking structure, and the first masking structure comprises: a first doped region, which is located in the epitaxial layer opposite the bottom of a first source electrode region, and a second doped region, which is located in the epitaxial layer opposite the bottom and side wall of a second source electrode region, and is connected to a metal source electrode above the epitaxial layer.

Description

A semiconductor device and its fabrication method

[0001] This application claims priority to Chinese Patent Application No. 202410918644.2, filed on July 10, 2024, entitled "A Semiconductor Device and a Method for Preparing the Same", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0003] In recent years, wide bandgap semiconductor materials (such as SiC and GaN) and ultra-wide bandgap semiconductor materials (such as gallium oxide, diamond, and aluminum nitride) have attracted widespread attention from the industry due to their excellent material properties.

[0004] Compared to traditional silicon materials, wide-bandgap and ultra-wide-bandgap semiconductor materials have significant advantages in physical properties such as bandgap width, critical breakdown electric field strength, and electron saturation drift velocity. Power devices (such as diodes and transistors) fabricated based on wide-bandgap or ultra-wide-bandgap semiconductor materials exhibit superior electrical characteristics, meeting the high-power, high-voltage, high-frequency, and high-temperature application requirements that silicon-based devices cannot satisfy. This represents one of the breakthrough paths beyond Moore's Law. Therefore, wide-bandgap and ultra-wide-bandgap semiconductor materials are widely used in new energy fields (such as photovoltaics, energy storage, charging piles, and electric vehicles), driving the development of the "new energy revolution."

[0005] Compared to semiconductor devices using traditional Si materials, although semiconductor devices using wide or ultra-wide bandgap semiconductor materials have better performance, their voltage withstand performance still needs improvement. Summary of the Invention

[0006] In view of the above problems, this application provides a semiconductor device and its fabrication method to improve its withstand voltage performance. The specific solution is as follows:

[0007] The first aspect of this application provides a semiconductor device, comprising:

[0008] A semiconductor substrate, wherein an epitaxial layer is present on one side surface of the semiconductor substrate; a well region is present on the side surface of the epitaxial layer opposite to the semiconductor substrate.

[0009] The epitaxial layer has two first trenches and a second trench located between the first trenches on the surface away from the semiconductor substrate. The depth of both the first trenches and the second trench is greater than the depth of the well region. A trench source is disposed in the first trench. A trench gate is disposed in the second trench. The trench source includes a first source region and a second source region that are alternately distributed along the length of the first trench.

[0010] Each trench source is provided with a first masking structure, which includes: a first doped region located in the epitaxial layer opposite to the bottom of the first source region; and a second doped region located in the epitaxial layer opposite to the bottom and sidewalls of the second source region, and the second doped region is connected to the metal source above the epitaxial layer.

[0011] Optionally, in the above semiconductor device, the portion of the second doped region opposite to the sidewall of the second source region extends to the upper surface of the epitaxial layer to connect with the metal source.

[0012] Alternatively, the portion of the second doped region opposite the sidewall of the second source region extends into the well region to connect with the metal source region based on the well region.

[0013] Optionally, in the above-mentioned semiconductor device, in the same first masking structure, the portion of the second doped region located below the bottom of the second source region is the same implantation region formed by the same ion implantation as the first doped region.

[0014] Optionally, in the above semiconductor device, the portion of the second doped region located on the sidewall of the second source region is a first implantation region formed before the first trench is fabricated, and the portion of the second doped region located below the bottom of the second source region is a second implantation region formed based on the first trench.

[0015] Optionally, the above-mentioned semiconductor device further includes: a second masking structure disposed corresponding to the trench gate;

[0016] The second masking structure includes a third doped region located within the epitaxial layer; the third doped region covers a portion of the bottom of the trench gate and is connected to two opposing second doped regions in the first direction;

[0017] The first direction is parallel to the plane of the semiconductor substrate and perpendicular to the length direction of the first trench.

[0018] Optionally, in the above semiconductor device, the depth of the first trench is greater than the depth of the second trench;

[0019] The portion of the second doped region opposite to the sidewall of the second source region and the third doped region are the same first implantation region formed by the same ion implantation. The upper surface of the first implantation region is flush with the upper surface of the epitaxial layer. The bottom depth of the first implantation region is greater than the depth of the second trench and less than the depth of the first trench.

[0020] Optionally, in the above semiconductor device, the depth of the first trench is greater than the depth of the second trench;

[0021] The upper surface of the third doped region is located below the bottom of the well region, and the bottom of the third doped region is located above the bottom of the first trench.

[0022] Optionally, in the above semiconductor device, the second masking structure further includes a fourth doped region, which at least covers a portion of the bottom of the trench gate and does not contact the first masking structure.

[0023] In the second trench, the third and fourth doped regions are alternately distributed along the length direction, and the third and fourth doped regions do not contact each other.

[0024] A second aspect of this application provides a method for fabricating any one of the aforementioned semiconductor devices, comprising:

[0025] A semiconductor substrate is provided, wherein an epitaxial layer is provided on one side surface of the semiconductor substrate; and a well region is provided in the side surface of the epitaxial layer opposite to the semiconductor substrate.

[0026] A trench source, a trench gate, and a first masking structure are formed within the surface of the epitaxial layer on the side facing away from the semiconductor substrate; wherein,

[0027] The epitaxial layer has two first trenches and a second trench located between the first trenches on the surface away from the semiconductor substrate. The depth of both the first trenches and the second trench is greater than the depth of the well region. A trench source is disposed in the first trench. A trench gate is disposed in the second trench. The trench source includes a first source region and a second source region that are alternately distributed along the length of the first trench.

[0028] Each trench source is provided with a first masking structure, which includes: a first doped region located in the epitaxial layer opposite to the bottom of the first source region; and a second doped region located in the epitaxial layer opposite to the bottom and sidewalls of the second source region, and the second doped region is connected to the metal source above the epitaxial layer.

[0029] Optionally, in the above preparation method, the method for forming the first masking structure includes:

[0030] Before the first trench is formed, a first implantation region is formed in the region of the epitaxial layer corresponding to the first trench by a first ion implantation.

[0031] After the first trench is formed, an isolation layer is formed on the sidewall of the first trench, and the isolation layer is exposed at the bottom of the first trench;

[0032] A second implantation region is formed in the epitaxial layer at the bottom of the first trench by a second ion implantation.

[0033] The width of the first implantation region is greater than the width of the first trench, the depth of the first trench is greater than the depth of the first implantation region, and the first trench penetrates the first implantation region from the middle to form the portion of the second doped region located on the sidewall of the second source region; the second implantation region is used to form the portion of the first doped region and the second doped region located below the bottom of the second source region.

[0034] Optionally, the above preparation method further includes: forming a second masking structure within a semiconductor substrate;

[0035] The second masking structure includes a third doped region located within the epitaxial layer; the third doped region covers a portion of the bottom of the trench gate and is connected to two opposing second doped regions in the first direction;

[0036] The first direction is parallel to the plane of the semiconductor substrate and perpendicular to the length direction of the first trench.

[0037] Optionally, in the above preparation method, the method for forming the second masking structure includes:

[0038] Through the first ion implantation, a first implantation region is simultaneously formed in the region of the epitaxial layer corresponding to the second trench;

[0039] The first implantation region corresponding to the trench gate region is used to form the third doped region. The upper surface of the first implantation region is flush with the upper surface of the epitaxial layer. The bottom depth of the first implantation region is greater than the depth of the second trench and less than the depth of the first trench.

[0040] Optionally, in the above preparation method, the method for forming the second masking structure includes:

[0041] An implantation region is formed within the epitaxial layer as a third doping region based on a single ion implantation.

[0042] The depth of the first trench is greater than the depth of the second trench; the upper surface of the third doped region is located below the bottom of the well region, and the bottom of the third doped region is located above the bottom of the first trench.

[0043] Optionally, in the above preparation method, the second masking structure further includes a fourth doped region, which at least covers a portion of the bottom of the trench gate and does not contact the first masking structure; wherein, in the length direction of the second trench, the third doped region and the fourth doped region are alternately distributed and do not contact each other.

[0044] By means of the above technical solution, in the semiconductor device and the method for fabricating the same provided in this application, trench sources are respectively provided on both sides of the trench gate, and a first masking structure is provided in the region corresponding to the trench source of the epitaxial layer. Based on the trench source and the first masking structure, the electric field of the trench gate can be shielded, thereby effectively preventing the gate dielectric layer in the trench gate from being broken down by the electric field and improving the withstand voltage performance of the device.

[0045] The first masking structure includes a first doped region and a second doped region. On one hand, the first doped region is located within the epitaxial layer below the bottom of the first source region, not covering the sidewalls of the first source region or covering the sidewalls of the first source region near the bottom of the first trench. The first doped region is located below the region directly opposite the trench source and trench gate, i.e., below the channel region. This prevents the diffusion of implanted ions during the formation of the first doped region from contaminating the channel region between the trench gate and trench source, facilitating further reduction of the device cell and increasing the effective cell area. On the other hand, the first masking structure can be electrically connected to the metal source through the second doped region to prevent the first masking structure from weakening or failing due to levitation depletion during device switching. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0047] The structures, proportions, sizes, etc., shown in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and purposes that this application can produce, should still fall within the scope of the technical content disclosed in this application.

[0048] Figure 1 is a cross-sectional view of a conventional semiconductor device with a dual trench source.

[0049] Figure 2 is a schematic diagram of the layout design principle of the doped region in the epitaxial layer of a semiconductor device according to an embodiment of this application;

[0050] Figure 3 is a cross-sectional view of the semiconductor device at position A-A' in Figure 2;

[0051] Figure 4 is a cross-sectional view of the semiconductor device at position B-B' in Figure 2;

[0052] Figure 5 is a schematic diagram of the layout design principle of the doped region in the epitaxial layer of another semiconductor device provided in an embodiment of this application;

[0053] Figure 6 is a cross-sectional view of the semiconductor device at position C-C' in Figure 5;

[0054] Figure 7 shows another cross-sectional view of the semiconductor device at position C-C' in Figure 5;

[0055] Figure 8 is a schematic diagram of the layout design principle of the doped region in the epitaxial layer of another semiconductor device provided in the embodiments of this application;

[0056] Figure 9 is a cross-sectional view of the semiconductor device at position B-B' in Figure 8;

[0057] Figure 10 is a schematic diagram of the layout design principle of the doped region in the epitaxial layer of another semiconductor device provided in the embodiments of this application;

[0058] Figure 11 is a cross-sectional view of the semiconductor device at position B-B' in Figure 10;

[0059] Figures 12-30 are schematic diagrams of the product structure at different process steps of a semiconductor device fabrication method provided in the embodiments of this application.

[0060] Reference numerals: 10-Electric field masking layer; 11-Semiconductor substrate; 12-Epipolar layer; 13-Trench source; 131-First source region; 132-Second source region; 14-Trench gate; 141-Gate dielectric layer; 15-Well region; 16-First trench; 17-Second trench; 18-First masking structure; 19-Metal source; 20-Second masking structure; 21-First contact region; 22-Second contact region; 23-Mask layer; 24-First implantation region; 25-Isolation layer; 26-Second implantation region; 31-First doped region; 32-Second doped region; 33-Third doped region; 34-Fourth doped region. Detailed Implementation

[0061] The embodiments of this application will now be clearly and completely described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0062] Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The terminology used in the embodiments of this application is only used to explain the specific embodiments of this application, and is not intended to limit this application.

[0063] Wide or ultra-wide bandgap semiconductor materials possess superior optical and electrical properties. Semiconductor devices employing these materials have a larger bandgap, enabling their application in many extreme and harsh environments. For example, in geothermal energy production and oil and gas extraction, they can achieve higher drilling speeds and lower failure rates. Furthermore, in high-temperature environments, they allow for higher operating temperatures in electronically controlled aluminum plants, steel mills, and coal-fired and gas-fired power plants, thereby improving the energy efficiency of these industrial processes.

[0064] Taking trench MOSFET devices as an example, semiconductor devices made of wide or ultra-wide bandgap semiconductor materials still have some problems that need to be improved: such as insufficient protection of the trench gate, the electric field at the corner of the trench gate is easy to accumulate, and the gate dielectric layer is easily broken down under high drain voltage.

[0065] While the aforementioned problem can be addressed by forming a grounded electric field masking structure inside the semiconductor device to reduce the electric field at the trench corner of the gate, ensuring the dynamic reliability of the semiconductor device requires constructing an electric field masking structure in the cell structure of each device unit. However, electric field masking structures generally require ultra-high energy ion implantation equipment. The scattering caused by high-temperature and high-energy ion implantation prevents further reduction of the cell linewidth in the semiconductor device, making continuous iterative optimization difficult.

[0066] Referring to Figure 1, which is a cross-sectional view of a conventional semiconductor device with a dual-trench source, the semiconductor device shown includes:

[0067] Semiconductor substrate 11;

[0068] An epitaxial layer 12 located on the surface of a semiconductor substrate 11;

[0069] A trench gate 14 and two trench sources 13 are disposed on the upper surface of the epitaxial layer 12, with the trench gate 14 located between the two trench sources 13.

[0070] The epitaxial layer 12 has an electric field masking layer 10 surrounding the trench source electrode 13 on its surface. The electric field masking layer 10 is uniform and constant along the length of the trench source electrode 13.

[0071] In the semiconductor device shown in Figure 1, a trench source 13 is disposed on each side of a trench gate 14, and an electric field masking layer 10 is disposed surrounding the trench source 13. The trench source 13 and the electric field masking layer 10 shield the electric field of the trench gate 14. Although this method can effectively prevent the breakdown of the gate dielectric layer 141 in the trench gate 14, when the device cell is further reduced, the scattering problem of the implanted ions (black circles in Figure 1) forming the electric field masking layer 10 due to the reduced distance between the trench source 13 and the trench gate 14 can lead to abnormal conduction in the channel region between the trench source 13 and the trench gate 14. This problem makes it difficult to reduce the device cell size and results in a low effective cell area.

[0072] To address the above problems, embodiments of this application provide a semiconductor device, including:

[0073] A semiconductor substrate, wherein an epitaxial layer is present on one side surface of the semiconductor substrate; a well region is present on the side surface of the epitaxial layer opposite to the semiconductor substrate.

[0074] The epitaxial layer has two first trenches and a second trench located between the first trenches on the surface away from the semiconductor substrate. The depth of the first trench and the second trench is greater than the depth of the well region. A trench source is disposed in the first trench. A trench gate is disposed in the second trench. The trench gate includes a first source region and a second source region that are alternately distributed along the length direction of the first trench.

[0075] Each trench source is provided with a first masking structure, which includes: a first doped region located in the epitaxial layer opposite to the bottom of the first source region; and a second doped region located in the epitaxial layer opposite to the bottom and sidewalls of the second source region, and the second doped region is connected to the metal source above the epitaxial layer.

[0076] In the semiconductor device provided in this application embodiment, trench sources are respectively provided on both sides of the trench gate, and a first masking structure is provided in the region corresponding to the trench source in the epitaxial layer. Based on the trench source and the first masking structure, the electric field of the trench gate can be shielded, thereby effectively preventing the gate dielectric layer in the trench gate from being broken down by the electric field and improving the withstand voltage performance of the device.

[0077] The first masking structure includes a first doped region and a second doped region. On one hand, the first doped region is located within the epitaxial layer below the bottom of the first source region, not covering the sidewalls of the first source region or covering the sidewalls of the first source region near the bottom of the first trench. The first doped region is located below the region directly opposite the trench source and trench gate, i.e., below the channel region. This prevents the diffusion of implanted ions during the formation of the first doped region from contaminating the channel region between the trench gate and trench source, facilitating further reduction of the device cell and increasing the effective cell area. On the other hand, the first masking structure can be electrically connected to the metal source through the second doped region to prevent the first masking structure from weakening or failing due to levitation depletion during device switching.

[0078] The above describes the core inventive concept of the technical solution of the embodiments of this application. In order to make the above-mentioned objectives, features and advantages of this application more obvious and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0079] Referring to Figures 2-4, Figure 2 is a schematic diagram of the layout design principle of the doped region in the epitaxial layer of a semiconductor device provided by an embodiment of this application, Figure 3 is a cross-sectional view of the semiconductor device at position A-A' in Figure 2, and Figure 4 is a cross-sectional view of the semiconductor device at position B-B' in Figure 2.

[0080] As shown in Figures 2-4, the semiconductor device includes:

[0081] A semiconductor substrate 11 has an epitaxial layer 12 on one side surface; a well region 15 is formed in the side surface of the epitaxial layer 12 facing away from the semiconductor substrate 11.

[0082] The epitaxial layer 12 has two first trenches 16 and a second trench 17 located between the first trenches 16 on the surface opposite to the semiconductor substrate 11. The depths of the first trenches 16 and the second trenches 17 are both greater than the depth of the well region 15. A trench source 13 is disposed in the first trench 16. A trench gate 14 is disposed in the second trench 17. The trench source 13 includes a first source region 131 and a second source region 132 that are alternately distributed along the length direction (vertical direction in FIG2) of the first trench.

[0083] Each trench source 13 is provided with a first masking structure 18. The first masking structure 18 includes: a first doped region 31, which is located in the epitaxial layer 12 opposite to the bottom of the first source region 131; and a second doped region 32, which is located in the epitaxial layer 12 opposite to the bottom and sidewall of the second source region 132, and the second doped region 32 is connected to the metal source 19 above the epitaxial layer 12.

[0084] In the semiconductor device provided in this application embodiment, trench sources 13 are respectively provided on both sides of the trench gate 14, and a first masking structure 18 is provided in the region corresponding to the trench source 13 of the epitaxial layer 12. Based on the trench source 13 and the first masking structure 18, the electric field of the trench gate 14 can be shielded, thereby effectively preventing the gate dielectric layer 141 in the trench gate 14 from being broken down by the electric field and improving the withstand voltage performance of the device.

[0085] Optionally, the two trench sources 13 can be symmetrically disposed on both sides of the trench gate 14. In other embodiments, the two trench sources 13 can also be of an asymmetrical structure.

[0086] Optionally, the first masking structures 18 corresponding to the two trench source electrodes 13 can be symmetrically disposed on both sides of the trench gate electrode 14. In other embodiments, the first masking structures 18 corresponding to the two trench source electrodes 13 can also be asymmetrical structures.

[0087] The first masking structure 18 includes a first doped region 31 and a second doped region 32.

[0088] On the one hand, the first doped region 31 is located in the epitaxial layer 12 below the bottom of the first source region 131 and does not cover the sidewall of the first source region 131. That is, the first doped region 31 is located below the bottom of the first trench 16 and does not exceed the bottom coverage area of ​​the first trench 16. Therefore, the first doped region 31 can not only achieve electric field masking in its area, but also, since the implantation region of the first doped region 31 is located in the region of the epitaxial layer 12 directly opposite the first trench 16, the first doped region 31 does not cover the sidewall of the first source region 131 or covers the sidewall of the first source region 131 near the bottom of the first trench. The first doped region 31 is located below the region directly opposite the trench source 13 and the trench gate 14, that is, below the channel region. The implanted ions of the first doped region 31 will not cause contamination to the channel region between the first trench 16 and the second trench 17. When the device cell size is further reduced, the first doped region 31 of the first source region 131 will not cause abnormal conduction of the channel region due to scattering. Therefore, it can prevent the diffusion of implanted ions during the formation of the first doped region 31 from contaminating the channel region between the trench gate 14 and the trench source 13, which facilitates further reduction of the device cell and improves the effective cell area.

[0089] On the other hand, the first masking structure 18 can be electrically connected to the metal source 19 through the second doped region 32 to prevent the first masking structure 18 from weakening or failing due to levitation depletion during device switching.

[0090] In this embodiment of the application, in the same trench source 13, the area ratio of the first source region 131 is greater than the area ratio of the second source region 132, so that the cross-sectional view at the corresponding A-A' position is the main structure of the device.

[0091] If the first masking structures 18 corresponding to the two trench source electrodes 13 are symmetrically arranged on both sides of the trench gate electrode 14, as shown in FIG2, the first doped region 31 in one first masking structure 18 and the first doped region 31 in the other first masking structure 18 are arranged opposite each other in the first direction (horizontal direction in FIG2), and the second doped region 32 in one first masking structure 18 and the second doped region 32 in the other first masking structure 18 are arranged opposite each other in the first direction.

[0092] In one embodiment of this application, as shown in FIG4, the portion of the second doped region 32 opposite to the sidewall of the second source region 132 extends to the upper surface of the epitaxial layer 12 to connect with the metal source 19. This allows the second doped region 32 to be directly electrically connected to the metal source 19, preventing the first masking structure 18 from weakening or failing in its electric field masking effect due to levitation depletion during device switching.

[0093] In other embodiments, the portion of the second doped region 32 opposite to the sidewall of the second source region 132 may extend at least to the well region 15, so as to connect the metal source 19 based on the well region 15 or the contact area within the well region, in order to prevent the first masking structure 18 from weakening or failing due to levitation depletion during device switching.

[0094] In one embodiment of this application, within the same first masking structure, the portion of the second doped region 32 located below the bottom of the second source region 132 and the first doped region 31 are formed by the same ion implantation. Both the portion of the second doped region 32 located below the bottom of the second source region 132 and the first doped region 31 are located within the epitaxial layer 12 below the bottom of the first trench 16. Therefore, they can be simultaneously fabricated within the epitaxial layer 12 below the bottom of the first trench 16 through the same ion implantation.

[0095] On the one hand, the portion of the second doped region 32 located below the bottom of the second source region 132 and the first doped region 31 can be prepared simultaneously, which is simple in preparation process and low in manufacturing cost.

[0096] On the other hand, ion implantation is performed based on the first trench 16. A second doped region 32 is formed in the epitaxial layer 12 below the bottom of the first trench 16, located below the bottom of the second source region 132, along with a first doped region 31, as shown in Figures 3 and 4. The second doped region 32 and the first doped region 31 are formed simultaneously, belonging to the same implantation region with the same thickness. The upper surface of this implantation region is the bottom of the first trench 16. In other words, the starting position of this ion implantation is the bottom of the first trench 16. Compared to starting ion implantation from the upper surface of the epitaxial layer 12, this significantly reduces the ion implantation depth. Therefore, the ion implantation energy can be reduced, thereby preventing the problem of implanted ions diffusing and contaminating the channel region due to excessively high ion implantation energy.

[0097] In this embodiment, the portion of the second doped region 32 located on the sidewall of the second source region 132 is a first implantation region formed before the preparation of the first trench 16, and the portion of the second doped region 32 located below the bottom of the second source region 132 is a second implantation region formed based on the first trench 16.

[0098] Before forming the first trench 16, a first implantation region is formed. The first implantation region is used to form the portion of the second doped region 32 located on the sidewall of the first trench 16. This implantation region is located in the epitaxial layer 12 above the bottom of the first trench 16. The implantation depth is relatively shallow, and ion implantation can start from the upper surface of the epitaxial layer 12. The ion implantation energy is relatively small, and the implanted ions can be well controlled within the first target area. The first target area is the epitaxial layer region where the portion of the second doped region 32 located on the sidewall of the first trench 16 is located. There will be no problem of significant ion scattering contamination of the channel region.

[0099] After the first trench 16 is formed, the second implantation region is formed. Ion implantation can be performed based on the first trench 16. Therefore, the implantation starting position of the second implantation region is the bottom of the first trench 16. Compared with the method of starting ion implantation from the upper surface of the epitaxial layer 12, the implantation depth of the second implantation region can be greatly reduced, thereby reducing the energy of the implanted ions. The implanted ions can be better controlled in the second target region. The second target region is the epitaxial layer region where the second doped region 32 is located below the bottom of the first trench 16. There will be no problem of significant ion scattering contamination of the channel region.

[0100] As can be seen from the above description, the second doped region 32 is formed by the first and second implantation regions formed by two ion implantations, which can reduce the ion implantation energy and prevent the ion implantation process of forming the second doped region 32 from contaminating the channel region. This makes it easier to further reduce the size of the device cell and increase the effective area of ​​the cell.

[0101] The first doped region 31 is in contact with the bottom of the first trench 16, and the second doped region 32 is in contact with the bottom and sidewalls of the first trench 16 to achieve a better electric field shielding effect.

[0102] In one embodiment of this application, as shown in FIG2, the first masking structures 18 corresponding to the two trench sources 13 are respectively set as separate injection regions within the epitaxial layer 12. In other embodiments, as described below, a second masking structure 20 can also be set within the epitaxial layer 12, and the first masking structures 18 on both sides of the trench gate 14 can be connected through the third doped region 33 in the second masking structure 20 to form a mesh-like masking structure, which can better improve the breakdown voltage performance of the device.

[0103] Referring to Figures 5 and 6, Figure 5 is a schematic diagram of the layout design principle of the doped region in the epitaxial layer of another semiconductor device provided in an embodiment of this application, and Figure 6 is a cross-sectional view of the semiconductor device at position C-C' in Figure 5. The cross-sectional views at positions A-A' and B-B' in Figure 5 are the same as the cross-sectional views at the same positions in Figure 2.

[0104] Unlike the embodiments described above, in the embodiments shown in Figures 5 and 6, the semiconductor device further includes a second masking structure 20 corresponding to the trench gate 14; the second masking structure 20 includes a third doped region 33 located within the epitaxial layer 12; the third doped region 33 covers a portion of the bottom of the trench gate 14 and connects to two opposing second doped regions 32 in a first direction; wherein, the first direction (the horizontal direction in Figure 5) is parallel to the plane of the semiconductor substrate 11 and perpendicular to the length direction of the first trench 16. The third doped region 33 contacts the bottom of the second trench 17 to achieve a better electric field shielding effect.

[0105] Based on the third doped region 33, the first masking structure 18 and the second masking structure 20 can be connected to form a grid, creating a grid-like masking structure within the epitaxial layer 12. This achieves better electric field shielding, better protects the trench gate 14, and further improves the device's breakdown voltage performance. The grid-like masking structure can be connected to the metal source 19 via the second doped region 32, or to the metal source 19 via both the second doped region 32 and the third doped region 33, to prevent the first masking structure 18 from weakening or failing due to levitation depletion during device switching.

[0106] In this embodiment, the depth of the first trench 16 is greater than the depth of the second trench 17, so that the depth of the trench source 13 is greater than the depth of the trench gate 14. This allows the trench source 13 on both sides of the trench gate 14 and the first masking structure 18 to better shield the electric field of the trench gate 14, preventing the gate dielectric layer 141 from being broken down, thereby improving the device's withstand voltage performance.

[0107] In one embodiment, as shown in FIG6, the portion of the second doped region 32 opposite to the sidewall of the second source region 132 and the third doped region 33 are formed in the same first implantation region by the same ion implantation. The upper surface of the first implantation region is flush with the upper surface of the epitaxial layer 12, and the bottom depth of the first implantation region is greater than the depth of the second trench 17 and less than the depth of the first trench 16. In this method, ion implantation can be performed in the epitaxial layer 12 before the formation of the first trench 16 to form the first implantation region. The third doped region 33 and the second doped region 32 are integrally connected by the first implantation region formed after the formation of the first trench 16.

[0108] Referring to Figure 7, which is another cross-sectional view of the semiconductor device at position C-C' in Figure 5, the difference from the method shown in Figure 6 is that, in the method shown in Figure 7, the upper surface of the third doped region 33 is located below the bottom of the well region 15, there is a gap between the third doped region 33 and the well region 15, the bottom of the third doped region 33 is located above the bottom of the first trench 16, and there is a gap between the bottom of the third doped region 33 and the bottom of the first trench 16.

[0109] Referring to Figures 8 and 9, Figure 8 is a schematic diagram of the layout design principle of the doped region in the epitaxial layer of another semiconductor device provided by an embodiment of this application, and Figure 9 is a cross-sectional view of the semiconductor device at position B-B' in Figure 8. The cross-sectional views at positions A-A' and C-C' in Figure 8 are the same as the cross-sectional views at the same positions in Figure 5.

[0110] Unlike the above embodiments, in the cross-sectional view of the B-B' position shown in Figures 8 and 9, the second masking structure 20 further includes a fourth doped region 34, which at least covers a portion of the bottom of the trench gate 14 and does not contact the first masking structure 18; wherein, in the length direction of the second trench 17, the third doped region 33 and the fourth doped region 34 are alternately distributed and do not contact each other.

[0111] In the configuration shown in FIG9, the fourth doped region 34 may cover a portion of the bottom of the trench gate 14 as shown in FIG9, and cover a portion of the sidewall of the trench gate 14 near the bottom of the second trench.

[0112] Referring to Figures 10 and 11, Figure 10 is a schematic diagram of the layout design principle of the doped region in the epitaxial layer of another semiconductor device provided by an embodiment of this application, and Figure 11 is a cross-sectional view of the semiconductor device at position B-B' in Figure 10. The cross-sectional views at positions A-A' and C-C' in Figure 11 are the same as the cross-sectional views at the same positions in Figures 5 and 8.

[0113] Unlike the above implementation, in the cross-sectional view of the B-B' position, in the manner shown in Figures 10 and 11, the fourth doped region 34 is located in the epitaxial layer 12 below the bottom of the trench gate 14, and does not extend beyond the shielding range of the trench gate 14 in the lateral direction. That is, the fourth doped region 34 is located between the opposite side walls of the second trench 17.

[0114] In the first direction, a third doped region 33 can be positioned between two opposing second doped regions 32, and the third doped region 33 connects the two second doped regions 32; a fourth doped region 34 can be positioned between two opposing second doped regions 32, and there is a distance between the fourth doped region 34 and the two second doped regions 32. In other embodiments, in the first direction, the fourth doped region 34 can also be positioned between two opposing first doped regions 31. The embodiments of this application do not limit the relative position of the fourth doped region 34 relative to the first doped regions 31 and the second doped regions 32.

[0115] The semiconductor device provided in this application embodiment further includes an ohmic contact region disposed within the surface of the well region 15. The ohmic contact region includes a first contact region 21 and a second contact region 22 alternately distributed within the surface of the well region 15. The first contact region 21 and the second contact region have different doping types.

[0116] In the semiconductor device, the first masking structure 18 and the second masking structure 20 have the same doping type, but different from the doping type of the epitaxial layer 12. The well region 15 has a different doping type than the epitaxial layer 12. The semiconductor substrate 11 has the same doping type as the epitaxial layer 12.

[0117] In this application's embodiments, the doping types include P-type doping and N-type doping. For two semiconductor devices with different doping types, one is P-type doped and the other is N-type doped. For two semiconductor devices with the same doping type, both are either N-type doped or both are P-type doped.

[0118] In one implementation, the well region 15, the first contact region 21, the first masking structure 18, and the second masking structure 20 can all be P-type doped. For example, the well region 15 can be P-doped, the first masking structure 18 and the second masking structure 20 can be P+ doped, and the first contact region 21 can be P++ doped, wherein the doping concentration of P-doping, P+ doping, and P++ doping increases sequentially. Alternatively, the epitaxial layer 12 can be N-doped, the semiconductor substrate 11 can be N+ doped, and the second contact region 22 can be N++ doped, wherein the doping concentration of N-doping, N+ doping, and N++ doping increases sequentially.

[0119] In this embodiment, the semiconductor device can be a MOS device, and further, it can be an NMOS device or a PMOS device. The doping type of each part of the semiconductor device can be set according to whether it is an NMOS or PMOS device. This embodiment does not limit the doping type or doping concentration of different regions in the semiconductor device.

[0120] As described above, this application improves the structure of a semiconductor device with a dual-trench source 13, designing a novel dual-trench source semiconductor device. A first masking structure 18 and a second masking structure 20 with periodic structures are formed within the epitaxial layer 12. The masking structures within the epitaxial layer 12 can be periodically connected to the metal source 19 based on the second doped region 32 or the third doped region 33. This semiconductor device can prevent the scattering and contamination of the channel region by implanted ions from the first masking structure 18 when the device cell size is further reduced, avoiding abnormal channel conduction problems. Furthermore, it can prevent the weakening or even failure of the electric field masking effect due to levitation depletion during device switching.

[0121] Based on the above embodiments, another embodiment of this application provides a method for fabricating a semiconductor device, used to fabricate the semiconductor device described in any of the above embodiments.

[0122] Referring to Figures 12-30, which are schematic diagrams of the product structure at different process steps of a semiconductor device fabrication method provided in this application embodiment, the fabrication method includes:

[0123] Step S11: As shown in Figures 12 and 13, a semiconductor substrate 11 is provided, and an epitaxial layer 12 is provided on one side surface of the semiconductor substrate 11; a well region 15 is provided in the side surface of the epitaxial layer 12 opposite to the semiconductor substrate 11.

[0124] First, as shown in Figure 12, an epitaxial layer 12 is formed on the surface of the semiconductor substrate 11. Optionally, the semiconductor substrate 11 can be a wide-bandgap or ultra-wide-bandgap semiconductor material, such as any one of silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN). An N-doped epitaxial layer 12 can be formed on the surface of an N+-doped semiconductor substrate 11 using an epitaxial process.

[0125] Then, as shown in Figure 13, a well region 15 and a first contact region 21 and a second contact region 22 located within the well region 15 are formed on the upper surface of the epitaxial layer 12 by ion implantation. A P-doped well region 15 can be formed on the upper surface of the epitaxial layer 12 by P-type ion implantation, a P++-doped first contact region 21 can be formed within the well region 15 by P-type ion implantation, and an N++-doped second contact region 22 can be formed within the well region 15 by N-type ion implantation.

[0126] Step S12: As shown in Figures 14-28 and related figures in the semiconductor device embodiment, a trench source 13, a trench gate 14, and a first masking structure 18 are formed in the surface of the epitaxial layer 12 on the side away from the semiconductor substrate 11.

[0127] The epitaxial layer 12 has two first trenches 16 and a second trench 17 located between the first trenches 16 on the surface opposite to the semiconductor substrate 11. The depths of the first trenches 16 and the second trenches 17 are both greater than the depth of the well region 15. A trench source 13 is disposed in the first trench 16, and a trench gate 14 is disposed in the second trench 17. The trench source 13 includes a first source region 131 and a second source region 132 that are alternately distributed along the length of the first trenches 16. Each trench source 13 is correspondingly provided with a first masking structure 18, which includes: a first doped region 31 located in the epitaxial layer 12 opposite to the bottom of the first source region 131; and a second doped region 32 located in the epitaxial layer 12 opposite to the bottom and sidewalls of the second source region 132, and the second doped region 32 is connected to the metal source 19 above the epitaxial layer 12.

[0128] In the above preparation method, the method for forming the first masking structure 18 includes:

[0129] Step S21: As shown in Figure 14 or Figure 15, before forming the first trench 16, a first implantation region 24 is formed in the region of the epitaxial layer 12 corresponding to the first trench 16 by a first ion implantation. A patterned mask layer 23 can be formed on the upper surface of the epitaxial layer 12 according to a pre-defined layout. Ion implantation is then performed based on the mask layer 23 to form the first implantation region 24. In this step, if the layout shown in Figure 2 or Figure 5 is used, the cross-sectional view at position B-B' is shown in Figure 14; if the layout shown in Figure 10 is used, the cross-sectional view at position B-B' is shown in Figure 15.

[0130] In Figure 14, the width of the first implantation region 24 corresponding to the trench source 13 is greater than the width of the first trench 16. This is so that after the first trench 16 is formed, a portion of the first implantation region 24 can be retained in the epitaxial layers 12 on both sides of the first trench 16, thereby forming the portion of the second doped region 32 located on the sidewall of the first source region 131. In Figure 15, the width of the first implantation region 24 corresponding to the trench gate 14 is not greater than the width of the second trench 17. This is so that after the second trench 17 is formed, only a portion of the first implantation region 24 located below the second trench 17 is retained as the fourth doped region 34.

[0131] In step S21, ion implantation is used to form the portion of the second doped region 32 located on the sidewall of the trench source 13, without involving the first doped region 31. Therefore, the implantation of the first doped region 31 is not involved, and the first doped region 31 is formed in subsequent processes.

[0132] Step S22: As shown in Figures 16-21, after forming the first trench 16, an isolation layer 25 is formed on the sidewall of the first trench 16, and the isolation layer 25 is exposed at the bottom of the first trench 16.

[0133] First, as shown in Figures 16-18, a first trench 16 is formed. Figure 16 is a cross-sectional view of each layout at position A-A', Figure 17 is a cross-sectional view of the layouts shown in Figures 2 and 5 at position B-B', and Figure 18 is a cross-sectional view of the layout shown in Figure 10 at position B-B'. To avoid affecting the first injection area 24 corresponding to the second trench 17 during etching of the first trench 16, comparing Figures 15 and 18, a new mask layer 23 is needed to mask the first injection area 24 corresponding to the second trench 17 before forming the first trench 16. Comparing Figures 14 and 17, and Figures 15 and 18, to retain portions of the first injection area 24 on both sides of the first trench 16, a new mask layer 23 is needed to mask the edge portion of the first injection area 24 corresponding to the first trench 16 before forming the first trench 16, exposing the area in the middle of the first injection area 24 that needs to be etched to form the first trench 16.

[0134] Then, based on Figures 16-18, as shown in Figures 19-21, an isolation layer 25 is formed. This process can be carried out using either CVD or ALD processes to prepare the isolation layer 25.

[0135] Step S23: Based on Figures 19-21, as shown in Figures 22-24, a second implantation region 26 is formed in the epitaxial layer 12 at the bottom of the first trench by a second ion implantation.

[0136] The width of the first implantation region 24 is greater than the width of the first trench 16, and the depth of the first trench 16 is greater than the depth of the first implantation region 24. The first trench 16 penetrates the first implantation region 24 from the middle to form the portion of the second doped region 32 located on the sidewall of the second source region 132. The second implantation region 26 is used to form the portion of the first doped region 31 and the second doped region 32 located below the bottom of the second source region 132.

[0137] Ion implantation is performed on the bottom of the first trench 16 based on the isolation layer 25 covering the sidewall of the first trench 16 to form a second implantation region 26. The second implantation region 26 corresponding to the first source region 131 can serve as the first doped region 31. The second implantation region 26 corresponding to the second source region 132 can be connected to the first implantation region 24 to form a second doped region 32.

[0138] Since the first doped region 31, which occupies a large area of ​​the device cell, is mainly located in the epitaxial layer 12 below the bottom of the trench source 13 and below the trench gate 14, the first doped region 31 is located below the channel region. Even if the first doped region 31 diffuses upward a certain distance from the bottom of the first trench 16 during the formation of the second implantation region 26, causing the first doped region 31 to exceed the bottom coverage area of ​​the first trench 16, since the second implantation region 26 is located below the channel region and the implantation is based on the first trench 16, the implantation depth of the second implantation region 26 is small, and the ion implantation energy is small. Therefore, the formation process of the first doped region 31 will not cause the implanted ions to contaminate the channel region, and will not affect the conduction performance of the channel region.

[0139] During the fabrication of semiconductor devices, the ion implantation depth and implantation energy of the first doped region 31 and the second doped region 32 are both low, which can effectively prevent implanted ion scattering from contaminating the channel region, making it easier to further reduce the device cell size and increase the effective cell area.

[0140] After forming the second implantation region 26, based on Figures 22-24, as shown in Figures 25-27, the isolation layer 25 is removed. The isolation layer 25 can be a silicon oxide layer, which can be removed using wet etching reagents such as HF solution, combined with a cleaning process to remove surface contaminants. After cleaning, drying is performed, followed by high-temperature activation annealing to activate the implanted ions. Optionally, the high-temperature ion activation process temperature for silicon carbide devices can be 1500℃~1900℃, and the process duration can be 10min~30min.

[0141] Subsequently, based on Figures 25-27, and as shown in Figures 28-30, etching is performed on the new mask layer 23 to form the second trench 17.

[0142] In subsequent processes, oxide layers are formed on the surfaces of the first trench 16 and the second trench 17 by oxidizing the trench sidewalls. The oxide layer covering the surface of the second trench 17 serves as the gate dielectric layer 141. After forming the oxide layers on the trench surfaces, polysilicon is filled into the trenches to form the trench gate 14 and the trench source 13. Finally, surface metal electrodes are fabricated, including forming a metal source 19 on the front side and a metal drain on the back side of the semiconductor substrate 11, to form a MOS structure.

[0143] The fabrication method provided in this application further includes forming a second masking structure 20 within the semiconductor substrate 11; the second masking structure 20 includes a third doped region 33 located within the epitaxial layer 12; the third doped region 33 covers a portion of the bottom of the trench gate 14 and connects to two opposing second doped regions 32 in a first direction; wherein, the first direction is parallel to the plane of the semiconductor substrate 11 and perpendicular to the length direction of the first trench 16. The structure of the third doped region 33 can be referred to Figures 5-7 of the above embodiments.

[0144] Optionally, the method for forming the second masking structure 20 includes: simultaneously forming a first implantation region 24 in the region of the epitaxial layer 12 corresponding to the second trench 17 by a first ion implantation. The first implantation region 24 corresponding to the trench gate region is used to form a third doped region; the upper surface of the first implantation region 24 is flush with the upper surface of the epitaxial layer 12, and the bottom depth of the first implantation region 24 is greater than the depth of the second trench 17 and less than the depth of the first trench 16. In this method, the second doped region 32 and the third doped region 33 can be formed simultaneously during the formation of the first implantation region 24, as shown in Figure 6.

[0145] In other methods, the formation of the second masking structure 20 includes: forming an implantation region within the epitaxial layer 12 as a third doped region 33 based on a single ion implantation; wherein the depth of the first trench 16 is greater than the depth of the second trench 17; the upper surface of the third doped region 33 is located below the bottom of the well region 15, and the bottom of the third doped region 33 is located above the bottom of the first trench 16. In this method, the third doped region 33 can be formed based on a single ion implantation, and the device structure is shown in Figure 7.

[0146] In the fabrication method provided in this application embodiment, the second masking structure 20 further includes a fourth doped region 34. The fourth doped region 34 at least covers a portion of the bottom of the trench gate 14 and does not contact the first masking structure 18. In the length direction of the second trench 17, the third doped region 33 and the fourth doped region 34 are alternately distributed, and the third doped region 33 and the fourth doped region 34 do not contact each other. The device structure is shown in Figure 9 or Figure 11. In this method, before forming the second trench 17, ion implantation can be performed in the region corresponding to the trench gate 14 through a single ion implantation to form the fourth doped region 34. The implanted regions corresponding to the third doped region 33 and the fourth doped region 34 can be formed through the same ion implantation or separately through a single ion implantation.

[0147] It should be noted that in the semiconductor device fabrication method provided in the embodiments of this application, the process sequence and layout can be flexibly designed based on the structure of the semiconductor device to be fabricated, and the semiconductor device fabrication method is not limited to the process sequence and layout design proposed in the embodiments of this application.

[0148] The various embodiments in this application are described in a progressive, parallel, or combined manner. Each embodiment focuses on its differences from other embodiments, and similar or identical parts between embodiments can be referred to interchangeably. The embodiments provided in this application can be combined with each other without contradiction.

[0149] It should be noted that, in the description of this application, the accompanying drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for ease of understanding and description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the drawings. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0150] The terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component positioned centrally in the middle.

[0151] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0152] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate, wherein one side surface of the semiconductor substrate has an epitaxial layer; The epitaxial layer has a well region on the side of its surface facing away from the semiconductor substrate; The epitaxial layer has two first trenches and a second trench located between the first trenches on the surface opposite to the semiconductor substrate. The depth of both the first trenches and the second trench is greater than the depth of the well region. A trench source is disposed in the first trench. A trench gate is disposed in the second trench; the trench source includes a first source region and a second source region that are alternately distributed along the length direction of the first trench; Each trench source is provided with a first masking structure, the first masking structure including: a first doped region, the first doped region being located in the epitaxial layer opposite the bottom of the first source region; The second doped region is located within the epitaxial layer at the bottom and opposite to the sidewalls of the second source region, and the second doped region is connected to the metal source above the epitaxial layer.

2. The semiconductor device according to claim 1, characterized in that, The portion of the second doped region opposite to the sidewall of the second source region extends to the upper surface of the epitaxial layer to connect with the metal source. Alternatively, the portion of the second doped region opposite the sidewall of the second source region extends into the well region to connect with the metal source based on the well region.

3. The semiconductor device according to claim 1, characterized in that, In the same first masking structure, the portion of the second doped region located below the bottom of the second source region is the same implantation region formed by the same ion implantation as the first doped region.

4. The semiconductor device according to claim 1, characterized in that, The portion of the second doped region located on the sidewall of the second source region is the first implantation region formed before the first trench is fabricated, and the portion of the second doped region located below the bottom of the second source region is the second implantation region formed based on the first trench.

5. The semiconductor device according to any one of claims 1-4, characterized in that, Also includes: A second masking structure is provided corresponding to the trench gate; The second masking structure includes a third doped region located within the epitaxial layer; The third doped region covers a portion of the bottom of the trench gate and is connected to two second doped regions opposite each other in the first direction; Wherein, the first direction is parallel to the plane where the semiconductor substrate is located and perpendicular to the length direction of the first trench.

6. The semiconductor device according to claim 5, characterized in that, The depth of the first trench is greater than the depth of the second trench; The portion of the second doped region opposite to the sidewall of the second source region and the third doped region are the same first implantation region formed by the same ion implantation. The upper surface of the first implantation region is flush with the upper surface of the epitaxial layer. The bottom depth of the first implantation region is greater than the depth of the second trench and less than the depth of the first trench.

7. The semiconductor device according to claim 5, characterized in that, The depth of the first trench is greater than the depth of the second trench; The upper surface of the third doped region is located below the bottom of the well region, and the bottom of the third doped region is located above the bottom of the first trench.

8. The semiconductor device according to claim 5, characterized in that, The second masking structure further includes a fourth doped region, which at least covers a portion of the bottom of the trench gate and does not contact the first masking structure. In the second trench, the third doped region and the fourth doped region are alternately distributed along the length direction, and the third doped region and the fourth doped region do not contact each other.

9. A method for fabricating a semiconductor device as described in any one of claims 1-8, characterized in that, include: A semiconductor substrate is provided, wherein one side surface of the semiconductor substrate has an epitaxial layer; The epitaxial layer has a well region on the side of its surface facing away from the semiconductor substrate; A trench source, a trench gate, and a first masking structure are formed within the surface of the epitaxial layer on the side opposite to the semiconductor substrate; wherein, The epitaxial layer has two first trenches and a second trench located between the first trenches on the surface opposite to the semiconductor substrate. The depth of both the first trenches and the second trench is greater than the depth of the well region. The trench source is disposed in the first trench. The trench gate is disposed in the second trench. The trench source includes a first source region and a second source region that are alternately distributed along the length of the first trench. Each trench source is provided with the first masking structure, which includes: a first doped region located in the epitaxial layer opposite to the bottom of the first source region; and a second doped region located in the epitaxial layer opposite to the bottom and sidewalls of the second source region, and the second doped region is connected to the metal source above the epitaxial layer.

10. The preparation method according to claim 9, characterized in that, The method for forming the first shielding structure includes: Before the first trench is formed, a first implantation region is formed in the region of the epitaxial layer corresponding to the first trench by a first ion implantation. After the first trench is formed, an isolation layer is formed on the sidewall of the first trench, and the isolation layer is exposed at the bottom of the first trench; A second implantation region is formed in the epitaxial layer at the bottom of the first trench by a second ion implantation. Wherein, the width of the first injection region is greater than the width of the first trench, the depth of the first trench is greater than the depth of the first injection region, and the first trench penetrates the first injection region from the middle to form the portion of the second doped region located on the sidewall of the second source region; the second injection region is used to form the portion of the first doped region and the second doped region located below the bottom of the second source region.

11. The preparation method according to claim 10, characterized in that, Also includes: A second masking structure is formed within the semiconductor substrate; The second masking structure includes a third doped region located within the epitaxial layer; The third doped region covers a portion of the bottom of the trench gate and is connected to two second doped regions opposite each other in the first direction; Wherein, the first direction is parallel to the plane where the semiconductor substrate is located and perpendicular to the length direction of the first trench.

12. The preparation method according to claim 11, characterized in that, The method for forming the second shielding structure includes: Through the first ion implantation, a first implantation region is simultaneously formed in the region of the epitaxial layer corresponding to the second trench; The first implantation region corresponding to the trench gate region is used to form the third doped region; the upper surface of the first implantation region is flush with the upper surface of the epitaxial layer, and the bottom depth of the first implantation region is greater than the depth of the second trench and less than the depth of the first trench.

13. The preparation method according to claim 11, characterized in that, The method for forming the second shielding structure includes: Based on a single ion implantation, an implantation region is formed within the epitaxial layer to serve as the third doped region; The depth of the first trench is greater than the depth of the second trench; the upper surface of the third doped region is located below the bottom of the well region, and the bottom of the third doped region is located above the bottom of the first trench.

14. The preparation method according to claim 11, characterized in that, The second masking structure further includes a fourth doped region, which at least covers a portion of the bottom of the trench gate and is not in contact with the first masking structure; wherein, along the length direction of the second trench, the third doped region and the fourth doped region are alternately distributed and are not in contact with each other.

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