Display panel, driving method, and electronic device

Abstract

A display panel (161), a driving method, and an electronic device (100), relating to the technical field of display. The display panel (161) comprises a pixel unit and a plurality of gate driving circuits (20); the pixel unit comprises a light-emitting element (21) and a pixel circuit (11); the pixel circuit (11) comprises a driving transistor (T0), a data writing transistor (T3), and a transistor group; the transistor group comprises a first transistor (T1) and a second transistor (T2) that are respectively connected to the driving transistor (T0); a first end of the first transistor (T1) is connected to a first end of the second transistor (T2). The plurality of gate driving circuits (20) include a target gate driving circuit, and a control end of a first transistor (T1) and a control end of a second transistor (T2) of the same transistor group are connected to the same target gate driving circuit. The number of gate driving circuits (20) can be reduced from two to one, thereby being conducive to achieving a narrow bezel.

Description

A display panel, driving method and electronic device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410940906.5, filed on July 12, 2024, entitled "A Display Panel, Driving Method, and Electronic Device," the entire contents of which are incorporated herein by reference; and to Chinese Patent Application No. 202411825301.8, filed on December 11, 2024, entitled "A Display Panel, Driving Method, and Electronic Device," the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to a display panel, driving method, and electronic device. Background Technology

[0004] Display panels made using organic light-emitting diodes (OLEDs) do not require a backlight and possess excellent characteristics such as high contrast, thinness, wide viewing angle, fast response speed, applicability to flexible panels, wide operating temperature range, and relatively simple construction and manufacturing process, making them widely used in various display devices. Typically, OLEDs in display panels are driven by pixel circuits, which consist of multiple transistors and capacitors. To control the conduction and switching of transistors in the pixel circuits, gate-on-array (GOA) circuits are usually placed at the bezel of the display panel. However, the large number of GOA circuits required for pixel circuits currently limits the bezel design of display panels, preventing further reduction in bezel size. Summary of the Invention

[0005] This application provides a display panel, a driving method, and an electronic device to reduce the number of gate driving circuits, which is beneficial for reducing the bezel of the display panel.

[0006] Firstly, this application provides a display panel including pixel units and multiple gate driving circuits. Each pixel unit includes a light-emitting element and a pixel circuit. Each pixel circuit includes a driving transistor, a data writing transistor, and a transistor group. A first terminal of the driving transistor is connected to a first power supply line, and a second terminal of the driving transistor is connected to the anode of the light-emitting element. A control terminal of the data writing transistor is used to receive a scan signal, and a first terminal of the data writing transistor is used to receive a data voltage signal. The second terminal of the data writing transistor is connected to the first terminal of the driving transistor. The transistor group includes a first transistor and a second transistor respectively connected to the driving transistor, and a first terminal of the first transistor is connected to the first terminal of the second transistor. Furthermore, the multiple gate driving circuits include a target gate driving circuit, and the control terminals of the first transistor and the second transistor in the same transistor group are connected to the same target gate driving circuit. Therefore, compared to the prior art where separate gate driving circuits are used to output signals to the control terminals of the first transistor and the second transistor, this application embodiment, by connecting the control terminals of the first transistor and the second transistor to the same target gate driving circuit, reduces the number of gate driving circuits from two to one, which is beneficial for achieving a narrow bezel.

[0007] In some possible implementations, the pixel circuit further includes a first reset transistor and a threshold compensation transistor. The control terminal of the first reset transistor is used to receive a first reset control signal, the control terminal of the threshold compensation transistor is used to receive a compensation control signal, and the second terminal of the first reset transistor is used to receive a first initialization signal. Furthermore, the first terminals of the first reset transistor, the first terminal of the threshold compensation transistor, and the second terminal of the driving transistor are interconnected, and the second terminal of the threshold compensation transistor is connected to the control terminal of the driving transistor. Thus, the first initialization signal can be input to the control terminal of the driving transistor through the first reset transistor and the threshold compensation transistor to reset the control terminal of the driving transistor.

[0008] In some possible implementations, the first reset transistor is turned on in response to the effective level of the first reset control signal, and the threshold compensation transistor is turned on in response to the effective level of the compensation control signal. The first terminals of the first reset transistor, the first terminal of the threshold compensation transistor, and the second terminal of the driving transistor are interconnected. The effective level of the compensation control signal is delayed by a set phase difference compared to the effective level of the first reset control signal, and the effective time of the compensation control signal overlaps with the effective time of the first reset control signal. Therefore, the first reset transistor and the threshold compensation transistor can be controlled to have a simultaneous on-time period, and when the first reset transistor and the threshold compensation transistor are on, a first initialization signal can be input to the control terminal of the driving transistor to reset the control terminal of the driving transistor.

[0009] In some possible implementations, the data write transistor is turned on in response to the effective level of the scan signal, the effective level of the scan signal not overlapping with the effective level of the first reset control signal, but overlapping with the effective level of the compensation control signal. This allows for a controlled period during which the data write transistor and the threshold compensation transistor are simultaneously turned on, and when both are on, a data voltage signal is input to the control terminal of the drive transistor. Furthermore, the first reset transistor and the data write transistor can be prevented from turning on simultaneously to avoid the first initialization signal affecting the data voltage signal input.

[0010] In some possible implementations, the pixel circuit further includes a first reset transistor and a threshold compensation transistor. The control terminal of the first reset transistor is used to receive a first reset control signal, the control terminal of the threshold compensation transistor is used to receive a compensation control signal, and the second terminal of the first reset transistor is used to receive a first initialization signal. Furthermore, the first terminal of the first reset transistor, the first terminal of the threshold compensation transistor, and the control terminal of the driving transistor are interconnected, and the second terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor. Thus, the first initialization signal can be input to the control terminal of the driving transistor through the first reset transistor to reset the control terminal of the driving transistor.

[0011] In some possible implementations, a first reset transistor is turned on in response to an effective level of a first reset control signal, and a threshold compensation transistor is turned on in response to an effective level of a compensation control signal. The first terminals of the first reset transistor, the first terminal of the threshold compensation transistor, and the control terminal of the driving transistor are interconnected, and the effective level of the compensation control signal does not overlap with the effective level of the first reset control signal. Therefore, when the first reset transistor is turned on, a first initialization signal can be input to the control terminal of the driving transistor to reset the control terminal of the driving transistor. Furthermore, the first reset transistor and the threshold compensation transistor can be controlled to not be turned on simultaneously, avoiding any impact on the signal at the control terminal of the driving transistor when the first reset transistor is turned on.

[0012] In some possible implementations, the first terminal of the first reset transistor, the first terminal of the threshold compensation transistor, and the control terminal of the driving transistor are interconnected. Within one frame, the effective level of the compensation control signal appears multiple times, the effective level of the first reset control signal appears multiple times, and the effective levels of the compensation control signal and the first reset control signal alternate. This allows the first reset transistor and the threshold compensation transistor to be turned on alternately multiple times, writing the data voltage signal to the control terminal of the driving transistor as many times as possible, reducing ghosting. This is especially beneficial when the display panel is used at a lower refresh rate, improving the display effect.

[0013] In some possible implementations, the data write transistor is turned on in response to the effective level of the scan signal, the effective level of the scan signal not overlapping with the effective level of the first reset control signal, but overlapping with the effective level of the compensation control signal. This allows for a controlled period during which the data write transistor and the threshold compensation transistor are simultaneously turned on, and when both are on, a data voltage signal is input to the control terminal of the drive transistor. Furthermore, the first reset transistor and the data write transistor can be prevented from turning on simultaneously to avoid the first initialization signal affecting the data voltage signal input.

[0014] In some possible implementations, the transistor group includes a first transistor group, a first reset transistor is the first transistor in the first transistor group, and a threshold compensation transistor is the second transistor in the first transistor group. Furthermore, the target gate driving circuit includes a first gate driving circuit, which is connected to the control terminals of the first reset transistor and the threshold compensation transistor, respectively, for outputting a first reset control signal to the first reset transistor and a compensation control signal to the threshold compensation transistor. Thus, by using the first gate driving circuit to output corresponding signals to the control terminals of the first reset transistor and the threshold compensation transistor, the gate driving circuit can be reduced from two to one, which is beneficial for achieving a narrow bezel.

[0015] In some possible implementations, the first gate drive circuit includes a plurality of cascaded first gate shift registers. The nth-level first gate shift register is connected to the control terminal of the first transistor in the first transistor group, and the (n+k)th-level first gate shift register is connected to the control terminal of the second transistor in the first transistor group, where n and k are positive integers. Thus, by connecting the control terminals of the first reset transistor and the threshold compensation transistor to different first gate shift registers in the first gate drive circuit, the signals from the control terminals of the first reset transistor and the threshold compensation transistor are output from different first gate shift registers within the same first gate drive circuit. This not only reduces the number of gate drive circuits from two to one, facilitating narrow bezel implementation, but also meets timing requirements.

[0016] In some possible implementations, the plurality of gate drive circuits further include a first reset control circuit, wherein the control terminal of the first reset transistor is connected to the first reset control circuit so that the first reset control circuit outputs a corresponding signal to the control terminal of the first reset transistor, thereby flexibly controlling the on / off state of the first reset transistor.

[0017] For example, the first reset control circuit includes a plurality of cascaded first reset shift register units, and the m-th level first reset shift register unit among the plurality of first reset shift register units is connected to the control terminal of the first reset transistor. Thus, by using the first reset shift register unit to output a corresponding signal to the control terminal of the first reset transistor, the on / off state of the first reset transistor can be flexibly controlled. Here, m is a positive integer. Furthermore, m and n can be the same or different.

[0018] In some possible implementations, the plurality of gate drive circuits further include a scan drive circuit, which comprises a plurality of cascaded scan shift registers. The control terminals of the threshold compensation transistor and the data write transistor are both connected to the same scan shift register. Thus, the control terminals of the threshold compensation transistor and the data write transistor are controlled by the same signal, which not only improves control synchronization but also reduces the number of gate drive circuits, further facilitating the achievement of a narrow bezel.

[0019] For example, the p-th level scan shift register unit in the plurality of scan shift register units is connected to the control terminal of the threshold compensation transistor and the control terminal of the data write transistor, so as to output the same signal to the control terminal of the threshold compensation transistor and the control terminal of the data write transistor. Here, p is a positive integer. Furthermore, p, m, and n can be partially or all the same, or all different.

[0020] In some possible implementations, the plurality of gate drive circuits further include a scan drive circuit and a compensation drive circuit. The control terminal of the data write transistor is connected to the scan drive circuit, and the control terminal of the threshold compensation transistor is connected to the compensation drive circuit. Thus, the compensation drive circuit can output a corresponding signal to the control terminal of the threshold compensation transistor, and the scan drive circuit can output a corresponding signal to the control terminal of the data write transistor, thereby allowing for flexible control of the on / off states of the threshold compensation transistor and the data write transistor.

[0021] For example, the scan driving circuit includes multiple cascaded scan shift register units. The p-th stage scan shift register unit is connected to the control terminal of the data writing transistor to output a corresponding signal to the control terminal of the data writing transistor. Similarly, the compensation driving circuit includes multiple cascaded compensation shift register units. The x-th stage compensation shift register unit is connected to the control terminal of the threshold compensation transistor to output a corresponding signal to the control terminal of the threshold compensation transistor. Here, x is a positive integer. Furthermore, x, p, m, and n may be partially or all the same, or all may be different.

[0022] In some possible implementations, oxide thin-film transistors (OTS) fabricated using metal oxide semiconductor materials (such as indium gallium zinc oxide (IGZO)) as the active layer have the characteristics of low leakage current and high uniformity. The first reset transistor and the threshold compensation transistor can be made into OTS, thereby reducing the impact of leakage current on the brightness of the light-emitting element.

[0023] In some possible implementations, the first reset transistor and the threshold compensation transistor are low-temperature polycrystalline silicon thin-film transistors, which can achieve high electron mobility, better switching speed and fast response.

[0024] In some possible implementations, the first reset transistor and the threshold compensation transistor are dual-gate transistors to reduce leakage current and improve display performance.

[0025] In some possible implementations, the pixel unit includes at least two light-emitting elements, and the transistor group includes at least two second transistor groups, each corresponding to one of the at least two light-emitting elements. In any second transistor group, the first terminal of the first transistor is connected to the first terminal of the driving transistor, the second terminal of the first transistor is used to connect to a first power supply line, the second terminal of the driving transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is used to connect to the anode of the corresponding light-emitting element. Furthermore, the target gate driving circuit includes at least two second gate driving circuits, each corresponding to one of the at least two second transistor groups. In any second transistor group, the control terminals of the first transistor and the second transistor are both connected to the same corresponding second gate driving circuit. This not only reduces the number of gate driving circuits, further facilitating the achievement of a narrow bezel, but also allows the pixel circuit to use a simple structure to drive multiple light-emitting elements and improves the synchronization of controlling the independent emission of different light-emitting elements.

[0026] In some possible implementations, the second gate driving circuit includes multiple cascaded second gate shift register units, and the control terminals of the first transistor and the second transistor in the second transistor group are both connected to the same second gate shift register unit. Therefore, the second gate shift register unit can output the same signal to the control terminals of the first transistor and the second transistor in the corresponding second transistor group, improving the synchronization of controlling the independent emission of different light-emitting elements.

[0027] For example, the y-th stage second gate shift register unit in the plurality of second gate shift register units is connected to the control terminals of the first transistor and the second transistor in the corresponding second transistor group, so as to output the same signal to the control terminals of the first transistor and the second transistor in the corresponding second transistor group through the y-th stage second gate shift register unit. Here, y is a positive integer. Furthermore, y, x, p, m, and n may be partially or all the same, or all may be different.

[0028] In some possible implementations, the first and second transistors in the second transistor group are low-temperature polysilicon transistors, which can achieve high electron mobility, better switching speed and fast response.

[0029] In some possible implementations, the pixel unit includes at least one light-emitting element, and the pixel circuit further includes a first light-emitting control transistor and at least one second light-emitting control transistor. A first terminal of the first light-emitting control transistor is connected to a first power supply line, a second terminal of the first light-emitting control transistor is connected to a first terminal of a driving transistor, and a control terminal of the first light-emitting control transistor is used to receive a first light-emitting control signal. Furthermore, at least one second light-emitting control transistor corresponds one-to-one with at least one light-emitting element; a first terminal of the at least one second light-emitting control transistor is connected to a second terminal of the driving transistor, a second terminal of the at least one second light-emitting control transistor is used to connect to the anode of the corresponding light-emitting element, and a control terminal of the at least one second light-emitting transistor is used to receive a second light-emitting control signal. This configuration allows the pixel circuit to drive one or more light-emitting elements to emit light using a simple structure.

[0030] In some possible implementations, the pixel unit includes a light-emitting element, the pixel circuit includes a second light-emitting control transistor, and the multiple gate driving circuits further include a first light-emitting control circuit. Furthermore, the first light-emitting control circuit includes multiple cascaded first light-emitting control shift register units, and the control terminals of both the first and second light-emitting control transistors are connected to the same first light-emitting control shift register unit. This configuration allows for synchronous control of the first and second light-emitting control transistors, and also reduces the number of signal lines and wiring complexity.

[0031] For example, the z-th level first light-emitting control shift register unit in the plurality of first light-emitting control shift register units is connected to the control terminals of both the first light-emitting control transistor and the second light-emitting control transistor, so as to output the same signal to the control terminals of the first light-emitting control transistor and the second light-emitting control transistor through the z-th level first light-emitting control shift register unit. Here, z is a positive integer. Furthermore, z, y, x, p, m, and n may be partially or all the same, or all may be different.

[0032] In some possible implementations, the pixel unit includes at least two light-emitting elements, the pixel circuit includes at least two second light-emitting control transistors, and the plurality of gate driving circuits further include second light-emitting control circuits and at least two third light-emitting control circuits. Furthermore, the control terminal of the first light-emitting control transistor is connected to the second light-emitting control circuit. Additionally, each of the at least two third light-emitting control circuits corresponds one-to-one with each of the at least two second light-emitting control transistors, and the second light-emitting control transistor is connected to its corresponding third light-emitting control circuit. This allows the signals at the control terminals of the first light-emitting control transistors and the control terminals of each of the second light-emitting control transistors to be decoupled from each other and to prevent interference.

[0033] For example, the second light-emitting control circuit includes a plurality of cascaded second light-emitting control shift register units. The g-th stage of these register units is connected to the control terminal of the first light-emitting control transistor, so as to output a corresponding signal to the control terminal of the first light-emitting control transistor through the g-th stage register unit. Here, g is a positive integer. Furthermore, g, z, y, x, p, m, and n may be partially or all the same, or all may be different.

[0034] For example, any third light-emitting control circuit includes a plurality of cascaded third light-emitting control shift register units. The h-th level third light-emitting control shift register unit is connected to the control terminal of the corresponding second light-emitting control transistor, so as to output a corresponding signal to the control terminal of the corresponding second light-emitting control transistor through the h-th level third light-emitting control shift register unit. Here, h is a positive integer. Furthermore, h, g, z, y, x, p, m, and n may be partially or all the same, or all may be different.

[0035] In some possible implementations, the pixel circuit further includes a second reset transistor corresponding to the light-emitting element. The first terminal of the second reset transistor is used to receive a second initialization signal, the second terminal of the second reset transistor is connected to the anode of the corresponding light-emitting element, and the control terminal of the second reset transistor is used to receive a second reset control signal. With this configuration, the second reset transistor can be used to reset the anode of the light-emitting element to adjust the anode voltage of the light-emitting element to a predetermined level, helping to eliminate unevenness in low grayscale brightness.

[0036] In some possible implementations, the plurality of gate drive circuits further include a second reset control circuit, the control terminal of which is connected. Thus, the second reset control circuit can output the required signal to the control terminal of the second reset transistor.

[0037] For example, the second reset control circuit includes a plurality of cascaded second reset shift register units. The j-th stage of the plurality of second reset shift register units is connected to the control terminal of the second reset transistor, so as to output a corresponding signal to the control terminal of the second reset transistor through the j-th stage second reset shift register unit. Here, j is a positive integer. Furthermore, j, h, g, z, y, x, p, m, and n may be partially or all the same, or all may be different.

[0038] In some possible implementations, the pixel circuit further includes a third reset transistor. The first terminal of the third reset transistor receives a third initialization signal, the second terminal is connected to either the first or second terminal of the driving transistor, and the control terminal of the third reset transistor receives a third reset control signal. Thus, the third initialization signal can be input to the first and second terminals of the driving transistor via the third reset transistor, resetting the first and second terminals of the driving transistor, achieving the on-bias stress (OBS) process, and reducing the hysteresis effect of the driving transistor.

[0039] In some possible implementations, the pixel circuit includes at least one second reset transistor, and the plurality of gate drive circuits further include a second reset control circuit. The second reset control circuit includes a plurality of cascaded second reset shift registers, and the control terminals of the at least one second reset transistor and the third reset transistor are both connected to the same second reset shift register. This reduces the number of signal lines and simplifies wiring. Furthermore, using the second reset control circuit to input the same signal to the control terminals of the second and third reset transistors facilitates synchronous control.

[0040] For example, the j-th stage second reset shift register unit in the plurality of second reset shift register units is connected to the control terminal of the at least one second reset transistor and the control terminal of the third reset transistor, so as to output corresponding signals to the control terminal of the at least one second reset transistor and the control terminal of the third reset transistor through the j-th stage second reset shift register unit.

[0041] In some possible implementations, the pixel circuit includes at least two second reset transistors. The plurality of gate drive circuits also include a second reset control circuit and a third reset control circuit. The at least two second reset transistors are connected to the second reset control circuit, and the control terminal of the third reset transistor is connected to the third reset control circuit. This decouples the signals from the control terminals of the second and third reset transistors, facilitating flexible control.

[0042] For example, the second reset control circuit includes a plurality of cascaded second reset shift register units. The j-th stage of the j-th stage second reset shift register unit is connected to the control terminal of the second reset transistor to output a corresponding signal to the control terminal of the second reset transistor. Similarly, the third reset control circuit includes a plurality of cascaded third reset shift register units. The f-th stage third reset shift register unit is connected to the control terminal of the third reset transistor to output a corresponding signal to the control terminal of the third reset transistor. Here, f is a positive integer. Furthermore, f, j, h, g, z, y, x, p, m, and n may be partially or all the same, or all may be different.

[0043] In some possible implementations, each second reset transistor is an oxide thin-film transistor, which facilitates the input of the second initialization signal to the anode of the corresponding light-emitting element, thus enabling a more thorough reset of the anode of the light-emitting element. Furthermore, the third reset transistor is a low-temperature polycrystalline silicon thin-film transistor, which can achieve high electron mobility, better switching speed, and faster response.

[0044] In some possible implementations, the second terminal of the third reset transistor is connected to the first terminal of the driving transistor. The third reset transistor is a single-gate transistor, which reduces the difficulty of layout design while implementing the OBS process.

[0045] In some possible implementations, the second terminal of the third reset transistor is connected to the second terminal of the driving transistor. The third reset transistor is a dual-gate transistor, which reduces leakage current and improves display performance.

[0046] In a second aspect, this application provides a driving method for a display panel, which is used to drive the display panel in the first aspect or the embodiments of the first aspect. The method includes: controlling the pixel circuit in the display panel to operate so as to drive the light-emitting element to emit light.

[0047] The control circuitry for the pixels in the display panel includes:

[0048] In the first reset phase, the first reset transistor and the threshold compensation transistor in the control pixel circuit are turned on.

[0049] During the data input and compensation stage, the threshold compensation transistor and data writing transistor in the control pixel circuit are turned on.

[0050] In the second reset phase, the third reset transistor and the second reset transistor in the control pixel circuit are turned on.

[0051] During the light-emitting stage, the first and second light-emitting control transistors in the control pixel circuit are turned on, or the transistors in the second transistor group of the control pixel circuit are turned on.

[0052] To accommodate different application scenarios, the display panel can operate at multiple different refresh rates. For example, in static image display scenarios, a lower refresh rate is needed to save power. Conversely, in high-frequency dynamic image display scenarios (such as game visuals), a higher refresh rate is needed to make the image smoother. Therefore, in this embodiment, to suit different application scenarios, the display panel can change its refresh rate. For example, the display panel can gradually change from one refresh rate to another. For example, the display panel can gradually decrease from a higher refresh rate to a lower refresh rate, thereby improving the problem of uneven brightness during refresh rate switching. Alternatively, the display panel can directly change from one refresh rate to a lower refresh rate.

[0053] In some possible implementations, when the display panel operates at different refresh rates, the first reset transistor, the threshold compensation transistor, and the data write transistor are driven based on the current refresh rate of the display panel.

[0054] In some possible implementations, when the display panel operates at different refresh rates, the third reset transistor is driven based on the maximum refresh rate of the display panel.

[0055] In some possible implementations, when the display panel operates at different refresh rates, the first light-emitting control transistor and the second reset transistor are driven based on the maximum refresh rate of the display panel.

[0056] In some possible implementations, when the display panel operates at different refresh rates, the transistors in the second transistor group are driven based on the maximum refresh rate of the display panel.

[0057] Thirdly, this application provides an electronic device that may include: a system processor, a timing controller, and a display panel as described in the first aspect or various embodiments of the first aspect. The system processor is connected to the timing controller, and the timing controller is connected to the display panel. During operation, the system processor sends processed grayscale information to the timing controller in each display frame, and the timing controller controls the pixel circuitry in the display panel to operate based on the received grayscale information.

[0058] Furthermore, the technical effects of the corresponding solutions in the second and third aspects can be referenced from the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions will not be detailed. Attached Figure Description

[0059] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0060] Figure 2 is a schematic diagram of a display device provided in an embodiment of this application;

[0061] Figure 3 is a schematic diagram of a display device provided in an embodiment of this application;

[0062] Figure 4 is a partial structural schematic diagram of a display panel provided in an embodiment of this application;

[0063] Figure 5 is a timing diagram of the gate control signal output by the first gate drive circuit shown in Figure 4;

[0064] Figure 6 is a signal timing diagram of the signals received by the pixel circuit shown in Figure 4 in a display frame;

[0065] Figure 7 illustrates, for example, the signals received by the pixel circuit when the display panel operates at different refresh rates;

[0066] Figure 8 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0067] Figure 9 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0068] Figure 10 is a schematic diagram of another structure of the display device provided in an embodiment of this application;

[0069] Figure 11a is a signal timing diagram of the pixel circuit shown in Figure 9 driving the light-emitting elements to emit light simultaneously;

[0070] Figure 11b is a signal timing diagram of a light-emitting element driven by the pixel circuit shown in Figure 9;

[0071] Figure 11c is a signal timing diagram of the pixel circuit shown in Figure 9 driving another light-emitting element to emit light;

[0072] Figure 12 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0073] Figure 13 is a schematic diagram of another structure of the display device provided in an embodiment of this application;

[0074] Figure 14a is a signal timing diagram of the pixel circuit shown in Figure 12 driving two light-emitting elements to emit light simultaneously;

[0075] Figure 14b is a signal timing diagram of a light-emitting element driven by the pixel circuit shown in Figure 12;

[0076] Figure 14c is a signal timing diagram of the pixel circuit shown in Figure 12 driving another light-emitting element to emit light;

[0077] Figure 15 shows the signals received by the pixel circuit when the display panel is operating at different refresh rates;

[0078] Figure 16 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0079] Figure 17 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0080] Figure 18 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0081] Figure 19 is a schematic diagram of another structure of the display device provided in an embodiment of this application;

[0082] Figure 20a is a signal timing diagram of a light-emitting element driven by the pixel circuit shown in Figure 18;

[0083] Figure 20b is a signal timing diagram of the pixel circuit shown in Figure 18 driving another light-emitting element to emit light;

[0084] Figure 21 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0085] Figure 22 is a schematic diagram of another structure of the display device provided in an embodiment of this application;

[0086] Figure 23a is a signal timing diagram of a light-emitting element driven by the pixel circuit shown in Figure 21;

[0087] Figure 23b is a signal timing diagram of the pixel circuit shown in Figure 21 driving another light-emitting element to emit light;

[0088] Figure 24 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0089] Figure 25 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0090] Figure 26 is a schematic diagram of another structure of the display device provided in an embodiment of this application;

[0091] Figure 27a is a signal timing diagram of a light-emitting element driven by the pixel circuit shown in Figure 26;

[0092] Figure 27b is a signal timing diagram of the pixel circuit shown in Figure 26 driving another light-emitting element to emit light;

[0093] Figure 28 is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are only used to distinguish the purpose of description and should not be construed as indicating or implying relative importance, nor as indicating or implying order. It is worth mentioning that "for connection" described in this application is not limited to physical or mechanical connections, but can also include electrical connections, whether direct or indirect. For example, A is used to connect B, which can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components. For example, A is used to connect B, which can also be a direct connection between A and C, a direct connection between C and B, with A and B connected through C.

[0095] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0096] The pixel circuits provided in this application embodiment can be applied to electronic devices with display functions. For example, the electronic device can be a terminal device, which may include, for example, mobile phones, laptops, televisions, set-top boxes, watches, personal computers (PCs), smart photo frames, wearable devices (such as smartwatches, virtual reality (VR) glasses, smart bracelets), indoor and outdoor signs, video game devices, clocks, etc.

[0097] The structure of the above-mentioned electronic device will be further explained below with reference to the accompanying drawings.

[0098] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Referring to Figure 1, the electronic device 100 may include: a radio frequency (RF) circuit 110, a battery 121, a battery management system (BMS) 122, a charge / discharge management module 123, a processor 130, a memory 140, an input unit 150, a display device 160, an audio circuit 170, a microphone 171, a speaker 172, a communication interface 180, and a wireless-fidelity (Wi-Fi) module 190, etc. Those skilled in the art will understand that the hardware structure of the electronic device 100 shown in Figure 1 does not constitute a limitation on the electronic device 100. The electronic device 100 provided in this embodiment of the application may include more or fewer components than shown, may combine two or more components, or may have different component configurations. The various components shown in Figure 1 can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits. Furthermore, one or more of the components shown in Figure 1 are disposed on a printed circuit board (PCB).

[0099] The following is a detailed description of each component of the electronic device 100 with reference to Figure 1:

[0100] RF circuit 110 can be used for receiving and sending data during communication or a call. For example, after receiving downlink data from a base station, RF circuit 110 sends it to processor 130 for processing. Additionally, RF circuit 110 can also send uplink data to be transmitted to the base station. Exemplarily, RF circuit 110 includes, but is not limited to, antennas, amplifiers, transceivers, couplers, low-noise amplifiers (LNAs), duplexers, etc. Furthermore, RF circuit 110 can communicate with other devices via wireless communication networks. Wireless communication can use any communication standard or protocol, including but not limited to Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Message Service (SMS), etc.

[0101] Wi-Fi technology is a short-range wireless transmission technology. Electronic device 100 can connect to an access point (AP) via Wi-Fi module 190, thereby enabling access to the data network. Wi-Fi module 190 can be used for receiving and sending data during communication.

[0102] Electronic device 100 can physically connect to other devices via communication interface 180. For example, communication interface 180 is connected to the communication interfaces of other devices via a cable, enabling data transmission between electronic device 100 and other devices.

[0103] Electronic device 100 can also perform communication services and interact with server-side devices or other electronic devices. Therefore, electronic device 100 needs to have data transmission capabilities, meaning it needs to include a communication module. Although Figure 1 shows communication modules such as RF circuit 110, Wi-Fi module 190, and communication interface 180, it is understood that electronic device 100 may contain at least one of the above components or other communication modules (such as a Bluetooth module) for data transmission. For example, when electronic device 100 is a mobile phone, it may include RF circuit 110, Wi-Fi module 190, or a Bluetooth module (not shown in Figure 1). When electronic device 100 is a computer, it may include communication interface 180, Wi-Fi module 190, or a Bluetooth module (not shown in Figure 1). When electronic device 100 is a tablet computer, it may include a Wi-Fi module or a Bluetooth module (not shown in Figure 1).

[0104] The memory 140 can be used to store computer programs and data. The processor 130 executes various functional applications and data processing of the electronic device 100 by running the computer programs and data stored in the memory 140. Exemplarily, the memory 140 may mainly include a program storage area and a data storage area. The program storage area may store the operating system (mainly including computer programs or modules corresponding to the kernel layer, system layer, application framework layer, and application layer). Exemplarily, the memory 140 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0105] The input unit 150 can be used to receive editing operations on various types of data objects, such as numbers or characters, input by the user, and to generate signal inputs related to user settings and function control of the electronic device 100. For example, the input unit 150 may include a touch panel 151 and other input devices 152. The touch panel 151, also known as a touchscreen, can collect touch operations performed by the user on or near it (e.g., operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touch panel 151) and drive corresponding connected devices according to a pre-set program. Furthermore, other input devices 152 may include, but are not limited to, one or more of the following: a physical keyboard, function keys (e.g., volume control buttons, power buttons, etc.), a trackball, a mouse, a joystick, etc.

[0106] The processor 130 is the control center of the electronic device 100. It connects various components via interfaces and lines, and executes computer programs and / or modules stored in the memory 140, as well as calling data stored in the memory 140, to perform various functions and process data of the electronic device 100, thereby realizing multiple services based on the electronic device 100. In this embodiment, the processor 130 can communicate with the display device 160 to implement the display control method provided in this embodiment, driving the display device 160 to perform display operations.

[0107] Audio circuitry 170, microphone 171, and speaker 172 provide an audio interface between the user and electronic device 100. Audio circuitry 170 converts audio data into signals recognizable by speaker 172 and transmits these signals to speaker 172, where they are converted into sound signals for output. Microphone 171 collects external sound signals (such as human speech or other sounds) and converts these signals into signals recognizable by audio circuitry 170, sending them to audio circuitry 170. Audio circuitry 170 can also convert the signals transmitted by microphone 171 into audio data and output the audio data to RF circuitry 110 for transmission to, for example, another electronic device, or output the audio data to memory 140 for further processing.

[0108] It is worth noting that, although not shown, the electronic device 100 may also include at least one sensor, a camera, a positioning device, a flash, a micro-projection device, a near field communication (NFC) device, etc., which will not be described in detail here. For example, at least one sensor may include, but is not limited to, a pressure sensor, a barometric pressure sensor, an accelerometer, a distance sensor, a fingerprint sensor, a touch sensor, a temperature sensor, and a battery sensor system (e.g., a voltage sensor, a current sensor, a temperature sensor, and a battery capacity calculation system). The battery sensor system may be housed in the power management system 122 or the charge / discharge management module 123.

[0109] Battery 121 is used to power various components in electronic device 100. Exemplarily, battery 121 can be logically connected to processor 130 or other components requiring power via a Battery Management System (BMS) 122, which manages the discharge of battery 121 to power various components. Exemplarily, charge / discharge management module 123 is connected to battery 121 and receives charging input from a charger to charge battery 121. Furthermore, charge / discharge management module 123 can also control the discharge of battery 121 to power other electronic devices (e.g., terminal devices), enabling electronic device 100 in this application to also use its own battery 121 to provide reverse power to other electronic devices (e.g., terminal devices). Exemplarily, the battery is a lithium battery, such as a graphite anode battery or a silicon-based lithium anode battery.

[0110] The display device 160 can be used to implement display functions, and the display device 160 can display images, videos, information input by the user or information provided to the user, as well as various menus or interfaces of the electronic device 100, to realize human-computer interaction.

[0111] Figure 2 is a schematic diagram of a display device provided in an embodiment of this application. The display device 160 may include a system processor 162, a timing controller (TCON) 163, and a display panel 161. The system processor 162 is connected to the timing controller 163, and the timing controller 163 is connected to the display panel 161. The display panel 161 has a display area AA and a border area BB. The display area AA may include multiple pixel units, which may be arranged in an array or in other ways.

[0112] Each pixel unit includes multiple sub-pixels 10 of different colors, and each sub-pixel 10 has a light-emitting element. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, with red sub-pixels including red light-emitting elements, green sub-pixels including green light-emitting elements, and blue sub-pixels including blue light-emitting elements. This allows for color mixing of red, green, and blue to achieve color display. During operation, the system processor 162 can acquire grayscale information of the image to be displayed in each display frame (this grayscale information includes a digital signal carrying the corresponding grayscale value for each sub-pixel in the display panel 161), process the grayscale information, and send it to the timing controller 163. The timing controller 163 controls the display panel 161 to operate according to the received grayscale information, causing the light-emitting elements of the sub-pixels in the display panel 161 to display the brightness of the corresponding grayscale value, thereby driving the display panel 161 to achieve the image display function. It is understood that the system processor 162 can be the same component as the processor 130, or a separate system processor 162 can be provided; this is not limited here.

[0113] It's worth noting that, for example, a displayed image can generally be composed of three colors: red, green, and blue, which are mixed to form a color image. Each color can display different brightness levels, and combinations of red, green, and blue at different brightness levels can form different color points. The grayscale values ​​mentioned above represent different brightness levels from the darkest to the brightest. The more levels there are, the more delicate the image effect can be. For example, the display panel can be a 6-bit (2 to the power of 6 luminance levels, i.e., 64 grayscale values: 0 to 63) panel, a 7-bit (2 to the power of 7 luminance levels, i.e., 128 grayscale values: 0 to 127) panel, an 8-bit (2 to the power of 8 luminance levels, i.e., 256 grayscale values: 0 to 255) panel, a 10-bit (2 to the power of 10 luminance levels, i.e., 1024 grayscale values: 0 to 1023) panel, a 12-bit (2 to the power of 12 luminance levels, i.e., 4096 grayscale values: 0 to 4095) panel, or a 16-bit (2 to the power of 16 luminance levels, i.e., 65536 grayscale values: 0 to 65535) panel to achieve image display.

[0114] Because light-emitting elements such as Organic Light Emitting Diodes (OLEDs), Quantum Dot Light Emitting Diodes (QLEDs), Micro Light Emitting Diodes (Micro LEDs), and Light Emitting Diodes (LEDs) have advantages such as self-illumination and low energy consumption, the light-emitting elements in the sub-pixels of this application embodiment can be one or more of OLEDs, QLEDs, Micro LEDs, and LEDs. To drive the light-emitting element to emit light, a pixel circuit needs to be set in the sub-pixel. The pixel circuit typically has a driving transistor that generates a driving current and a transistor that inputs a control signal. By controlling the on / off state of these transistors, the pixel circuit can be controlled to drive the light-emitting element to emit light.

[0115] Referring to Figure 2, in order to control the on / off state of the transistors that receive control signals in the pixel circuit, the bezel area BB of the display panel may include multiple gate driving circuits 20. These multiple gate driving circuits 20 are respectively connected to the control terminals of the transistors that receive control signals in the pixel circuit to control the on / off state of these transistors. In this embodiment, to reduce the number of gate driving circuits, a transistor group is provided in the pixel circuit. The transistor group includes a first transistor and a second transistor respectively connected to the driving transistor, with the first terminal of the first transistor connected to the first terminal of the second transistor. Furthermore, the multiple gate driving circuits include a target gate driving circuit. The control terminals of the first transistor and the second transistor in the same transistor group are connected to the same target gate driving circuit, thereby reducing the number of gate driving circuits from two to one, which is beneficial for achieving a narrow bezel. It is understood that, for ease of illustration, Figure 2 only shows one gate driving circuit 20. In addition, this embodiment uses the example where f, j, h, g, z, y, x, p, m, and n are all the same.

[0116] Figure 3 is a schematic diagram of a display device provided in an embodiment of this application, and Figure 4 is a partial schematic diagram of a display panel provided in an embodiment of this application. Referring to Figures 3 and 4, the pixel circuit 11 provided in this embodiment of this application may include: a driving transistor T0, a first reset transistor T1, a threshold compensation transistor T2, and a data writing transistor T3. The control terminal of the first reset transistor T1 is used to receive a first reset control signal RE1_n, and the second terminal of the first reset transistor T1 is used to receive a first initialization signal VINIT1. The first terminal of the first reset transistor T1, the first terminal of the threshold compensation transistor T2, and the second terminal of the driving transistor T0 are interconnected. The control terminal of the threshold compensation transistor T2 is used to receive a compensation control signal FC_n, and the second terminal of the threshold compensation transistor T2 is connected to the control terminal of the driving transistor T0. The control terminal of the data writing transistor T3 is used to receive a scan signal GA_n, the first terminal of the data writing transistor T3 is used to receive a data voltage signal DA, and the second terminal of the data writing transistor T3 is connected to the first terminal of the driving transistor T0. The first terminal of the driving transistor T0 is used to connect to the first power line VDDL, the second terminal of the driving transistor T0 is used to connect to the anode of the light-emitting element 21, and the cathode of the light-emitting element 21 is used to connect to the second power line VSSL. Exemplarily, the first power line VDDL transmits a high voltage, and the second power line VSSL transmits a low voltage.

[0117] In the prior art, due to the timing requirements of the drive, the signals of the control terminals of the first reset transistor T1 and the threshold compensation transistor T2 need to be provided by different gate drive circuits, resulting in the need to set two gate drive circuits in the display panel to drive the first reset transistor T1 and the threshold compensation transistor T2. Since the gate drive circuit is usually located in the bezel area BB of the display panel, it is not conducive to achieving a narrow bezel. Therefore, referring to Figures 3 and 4, the transistor group may include a first transistor group Z1, where the first reset transistor T1 is the first transistor in the first transistor group Z1, and the threshold compensation transistor T2 is the second transistor in the first transistor group Z1. Furthermore, the target gate drive circuit includes a first gate drive circuit 12, which is formed in the bezel area BB of the display panel 161 using GOA technology. The first gate drive circuit 12 is connected to the control terminals of the first reset transistor T1 and the threshold compensation transistor T2, respectively, so that the first gate drive circuit 12 is used to output a first reset control signal RE1_n to the first reset transistor T1 and a compensation control signal FC_n to the threshold compensation transistor T2. Based on this, the first gate driving circuit 12 can output signals to the control terminal of the first reset transistor T1 and the control terminal of the threshold compensation transistor T2 in the same pixel circuit. Compared with the existing method of using two gate driving circuits to output signals to the control terminal of the first reset transistor T1 and the control terminal of the threshold compensation transistor T2 in the same pixel circuit respectively, the gate driving circuit can be reduced from two to one, which is beneficial to achieving a narrow bezel.

[0118] Referring to Figure 4, the first gate drive circuit 12 may include multiple cascaded first gate shift register units, for example, N first gate shift register units: the first-stage first gate shift register unit sr1_1 to the Nth-stage first gate shift register unit sr1_N. Referring to the signal timing diagram shown in Figure 5, the first-stage first gate shift register unit sr1_1 to the Nth-stage first gate shift register unit sr1_N all receive a clock control signal. The input terminal of the first-stage first gate shift register unit sr1_1 receives a frame trigger signal, so that under the action of the frame trigger signal and the clock control signal, it outputs a gate control signal SR1_1 through its output terminal, and also provides the gate control signal SR1_1 to the input terminal of the second-stage first gate shift register unit sr1_2. Under the influence of the gate control signal SR1_1 and the clock control signal, the second-stage first gate shift register unit sr1_2 outputs the gate control signal SR1_2 through its output terminal, and also provides the gate control signal SR1_2 to the input terminal of the third-stage first gate shift register unit sr1_3. The rest follow the same logic, thus enabling the gate drive circuit to sequentially output gate control signals SR1_1 to SR1_N. Furthermore, during operation, the timing controller 163 can output a clock control signal and a frame trigger signal to the first gate drive circuit 12, controlling each first gate shift register unit to sequentially output the gate control signals SR1_1 to SR1_N.

[0119] Furthermore, the nth-level first gate shift register unit in the plurality of first gate shift register units is connected to the control terminal of the first transistor (i.e., the first reset transistor T1) in the first transistor group Z1. That is, the gate control signal SR1_n output by the nth-level first gate shift register unit serves as the first reset control signal RE1_n received by the control terminal of the first reset transistor T1. Also, the (n+k)th-level first gate shift register unit is connected to the control terminal of the second transistor (i.e., the threshold compensation transistor T2) in the first transistor group Z1. That is, the gate control signal SR1_n+k output by the (n+k)th-level first gate shift register unit serves as the compensation control signal FC_n received by the control terminal of the threshold compensation transistor T2. Based on this, a first gate drive circuit 12 is formed in the bezel area BB of the display panel 161 using GOA technology, and the control terminals of the first reset transistor T1 and the threshold compensation transistor T2 are connected to different first gate shift register units in the first gate drive circuit 12. This allows the signals of the control terminals of the first reset transistor T1 and the threshold compensation transistor T2 to be output from different first gate shift register units in the same first gate drive circuit 12, thereby reducing the number of gate drive circuits from two to one, which is beneficial for achieving a narrow bezel.

[0120] Where n and k are positive integers. For example, n can be any positive integer from 1 to N-1, and k can be a positive integer such as 1, 2, 3, 4, 5, etc. The specific values ​​of n and k can be determined according to the needs of the actual application scenario, and are not limited here.

[0121] Referring to Figure 3, the display area AA also includes a first control signal line SAL corresponding to each row of pixel units. The output terminal of the nth level first gate shift register unit is connected to the control terminal of the first reset transistor T1 in the qth row of pixel units through the first control signal line SAL corresponding to the qth row of pixel units, so as to input the gate control signal SR1_n to the control terminal of the first reset transistor T1 in the qth row of pixel units, and control the conduction and disconnection of the first reset transistor T1 in the qth row of pixel units.

[0122] Referring to Figure 3, the display area AA also includes a second control signal line SBL corresponding to each row of pixel units. The output terminal of the (n+k)th stage first gate shift register unit is connected to the control terminal of the threshold compensation transistor T2 in the (q)th row of pixel units through the second control signal line SBL corresponding to the (q)th row of pixel units, so as to input the gate control signal SR1_n+k to the control terminal of the threshold compensation transistor T2 in the (q)th row of pixel units, thereby controlling the conduction and disconnection of the threshold compensation transistor T2 in the (q)th row of pixel units. Furthermore, the output terminal of the (n+k)th stage first gate shift register unit is also connected to the control terminal of each first reset transistor T1 in the (q+k)th row of pixel units through the first control signal line SAL corresponding to the (q+k)th row of pixel units, so as to input the gate control signal SR1_n+k to the control terminal of each first reset transistor T1 in the (q+k)th row of pixel units, thereby controlling the conduction and disconnection of each first reset transistor T1 in the (q+k)th row of pixel units.

[0123] For example, when k=1, the two first gate shift registers connected to the first reset transistor T1 and the threshold compensation transistor T2 in the q-th row pixel unit are adjacent. Based on this, the second control signal line SBL corresponding to the q-th row pixel unit and the first control signal line SAL corresponding to the q+1-th row pixel unit are set to the same signal line, so that the control terminals of each threshold compensation transistor T2 in the q-th row pixel unit and the control terminals of each first reset transistor T1 in the q+1-th row pixel unit are connected to the same first gate shift register unit, thereby reducing the number of signal lines and reducing the wiring difficulty.

[0124] For example, q equals n, allowing each stage of the first gate shift register unit to be configured in a one-to-one correspondence with each row of pixel units. Alternatively, if q is less than n, some dummy gate shift register units can be configured starting from the first stage of the first gate shift register unit, making the signal of the first control signal line SAL corresponding to the input first row of pixel units more stable. Alternatively, if q is greater than n, a certain number of dummy pixel units can be configured starting from the first row of pixel units. These dummy pixel units may not be connected to the first gate shift register units, making the structure of the light-emitting pixel units more stable. In this embodiment, q equals n, and the nth row of pixel units is used as an example for explanation.

[0125] During operation, the first reset transistor T1 is turned on in response to the effective level of the first reset control signal RE1_n, and the threshold compensation transistor T2 is turned on in response to the effective level of the compensation control signal FC_n. When both the first reset transistor T1 and the threshold compensation transistor T2 are on, the first initialization signal VINIT1 can be input to the control terminal of the driving transistor T0 to reset the control terminal of the driving transistor T0. For this purpose, the first reset transistor T1 and the threshold compensation transistor T2 need to be simultaneously on for a period of time. Therefore, referring to the signal timing diagram shown in Figure 6, the effective level of the compensation control signal FC_n can be delayed by a set phase difference compared to the effective level of the first reset control signal RE1_n, so that the effective levels of the compensation control signal FC_n and the first reset control signal RE1_n overlap, with an overlap duration ta equal to the D1 time period. This allows both the first reset transistor T1 and the threshold compensation transistor T2 to be on during the D1 time period. It is understood that Figure 6 illustrates an example where both the effective levels of the compensation control signal FC_n and the first reset control signal RE1_n are high. Furthermore, RE1_n represents the first reset control signal received by the first reset transistor T1 in the nth row of pixel units, and FC_n represents the compensation control signal received by the threshold compensation transistor T2 in the nth row of pixel units. Additionally, the phase difference can be set according to the requirements of the actual application scenario and is not limited here.

[0126] In some embodiments of this application, since the gate control signal SR1_n output by the nth stage first gate shift register unit serves as the first reset control signal RE1_n, and the gate control signal SR1_n+k output by the (n+k)th stage first gate shift register unit serves as the compensation control signal FC_n, the gate control signal SR1_n and the gate control signal SR1_n+k need to be time-coordinated to determine which (n+k)th stage first gate shift register unit is specifically connected to the threshold compensation transistor T2. For example, referring to the signal timing diagram shown in Figure 5, taking the effective level of the gate control signals SR1_1 to SR1_N as high level, if the falling edge of the gate control signal SR1_n output by the nth-stage first gate shift register unit sr1_n is aligned with the rising edge of the gate control signal SR1_n+p output by the (n+p)th-stage first gate shift register unit sr1_n+1 to the (n+p-1)th-stage first gate shift register unit sr1_n+p-1 as the (n+k)th-stage first gate shift register unit sr1_n+k. For example, taking the first row of pixel units as an example, i.e., n=1, the control terminal of each first reset transistor T1 is connected to the output terminal of the first-stage first gate shift register unit sr1_1. Furthermore, the falling edge of the gate control signal SR1_1 output by the first-stage first gate shift register unit sr1_1 is aligned with the rising edge of the gate control signal SR1_5 output by the fifth-stage first gate shift register unit sr1_5. Therefore, the control terminal of each threshold compensation transistor T2 can be connected to the output terminal of one of the first gate shift register units from the second-stage first gate shift register unit sr1_2 to the fourth-stage first gate shift register unit sr1_4, thereby inputting one of the gate control signals SR1_2 to SR1_4 to the control terminal of the threshold compensation transistor T2. The rest can be deduced similarly, and will not be elaborated further here.

[0127] It is understandable that Figure 5 is only a schematic diagram of the gate control signals SR1_1 to SR1_N. In actual implementation, it can be determined according to the needs of the actual application scenario, and no limitation is made here.

[0128] To drive the light-emitting element 21 to emit light of different brightness, the pixel circuit 11 needs to input a data voltage signal DA. Therefore, a data writing transistor T3 is provided in the pixel circuit 11, and the data writing transistor T3 is turned on in response to the effective level of the scan signal GA_n, inputting the data voltage signal DA to the first terminal of the driving transistor T0, so as to input the data voltage signal DA into the pixel circuit. In practical applications, the data voltage signal DA needs to be input to the control terminal of the driving transistor T0 so that the driving transistor T0 generates a driving current for driving the light-emitting element 21 based on the voltage Vda of the data voltage signal DA. Therefore, the data writing transistor T3 and the threshold compensation transistor T2 need to be turned on simultaneously to input the voltage Vda of the data voltage signal DA to the control terminal of the driving transistor T0. Furthermore, the first reset transistor T1 and the data writing transistor T3 need to be prevented from being turned on simultaneously to avoid the first initialization signal VINIT1 affecting the Vda input. Based on this, the scan signal GA_n, the first reset control signal RE1_n, and the compensation control signal FC_n need to be coordinated in timing. For example, referring to Figure 6, the effective level time of the scan signal GA_n does not overlap with the effective level time of the first reset control signal RE1_n, but the effective level time of the scan signal GA_n overlaps with the effective level time of the compensation control signal FC_n, and the overlap duration is tb. It is understood that Figure 6 illustrates this with the effective level of the scan signal GA_n being low. Furthermore, GA_n represents the scan signal received by the data writing transistor T3 in the nth row pixel unit. Further, to ensure the writing of the data voltage signal DA is as complete as possible, the low-level time period of the scan signal GA_n can be incorporated into the high-level time period of the compensation control signal FC_n.

[0129] Due to factors such as manufacturing process and device aging, the threshold voltage Vth of the driving transistor T0 exhibits non-uniformity, resulting in uneven current flowing through the light-emitting elements 21 connected to different pixel circuits 11. This leads to uneven display brightness and affects the image display effect, thus requiring compensation for Vth. Furthermore, to drive the light-emitting elements 21 to emit light of varying brightness, the pixel circuit 11 also needs to input a data voltage signal DA. Therefore, in this embodiment, the pixel circuit 11 can compensate for Vth when inputting the data voltage signal DA, thereby not only compensating for Vth but also facilitating high-frequency driving. Further, to improve the compensation effect of the threshold voltage Vth, the effective level of the scanning signal GA_n can be cut off for a certain period before the effective level of the compensation control signal FC_n is cut off. For example, referring to Figure 6, the rising edge of the scanning signal GA_n can appear for a certain period before the falling edge of the compensation control signal FC_n appears.

[0130] In some embodiments of this application, in order to output a scan signal GA_n to the data writing transistor T3, referring to Figures 3 and 4, the plurality of gate driving circuits further include scan driving circuits (e.g., 13a, 13b). The scan driving circuits (e.g., 13a, 13b) may include a plurality of cascaded scan shift register units. The display area AA also includes a scan line GAL corresponding to each row of pixel units. The output terminal of the nth level scan shift register unit gar_n in the plurality of scan shift register units is connected to the control terminal of the data writing transistor T3 in the pixel circuit 11 of the nth row of pixel units through the scan line GAL corresponding to the nth row of pixel units, so as to output the scan signal GA_n to the control terminal of the data writing transistor T3 through the nth level scan shift register unit gar_n. In some embodiments of this application, two scan driving circuits can be configured, namely scan driving circuits 13a and 13b. Scan driving circuit 13a can be connected to the control terminal of each data writing transistor T3 in the odd-numbered row of pixel units. That is, the pixel unit connected to the output terminal of the nth-level scan shift register unit gar_n in scan driving circuit 13a is the odd-numbered (i.e., 2m-1)th row of pixel units. Scan driving circuit 13b can be connected to the control terminal of each data writing transistor T3 in the even-numbered row of pixel units. That is, the pixel unit connected to the output terminal of the nth-level scan shift register unit gar_n in scan driving circuit 13b is the even-numbered (i.e., 2m)th row of pixel units. In other embodiments of this application, one scan driving circuit can be configured, in which case the output terminal of the nth-level scan shift register unit gar_n is connected to the control terminal of the data writing transistor T3. Furthermore, during operation, the timing controller 163 outputs control signals to each scan shift register unit, controlling each scan shift register unit to sequentially output scan signals GA_n.

[0131] In some embodiments of this application, in order to output a data voltage signal DA to the data writing transistor T3, the bezel area BB further includes a source driving circuit 164, and the display area AA further includes a data line DAL corresponding to each column of pixel units. The source driving circuit 164 is connected to each data line DAL, and the first terminal of each data writing transistor T3 of a column of pixel circuits is connected to a data line DAL. During operation, the timing controller 163 converts the grayscale signal of the received digital voltage into an analog voltage data voltage signal DA and inputs it to the data line DAL, so that the data voltage signal DA is input through the data line DAL.

[0132] To prevent the light-emitting element 21 from emitting light and affecting the display effect when the first reset transistor T1 to the data write transistor T3 are turned on, referring to Figure 4, the pixel circuit 11 also includes a first light-emitting control transistor T4 and a second light-emitting control transistor T5. The control terminal of the first light-emitting control transistor T4 is used to receive a first light-emitting control signal, the first terminal of the first light-emitting control transistor T4 is used to connect to the first power line VDDL, and the second terminal of the first light-emitting control transistor T4 is connected to the first terminal of the driving transistor T0. The control terminal of the second light-emitting control transistor T5 is used to receive a second light-emitting control signal, the first terminal of the second light-emitting control transistor T5 is connected to the second terminal of the driving transistor T0, and the second terminal of the second light-emitting control transistor T5 is connected to the anode of the light-emitting element 21. Furthermore, during operation, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned off during the non-light-emitting phase and turned on during the light-emitting phase. Specifically, the first light-emitting control transistor T4 turns on in response to a valid level of the first light-emitting control signal EM1_n and turns off in response to an invalid level of the first light-emitting control signal EM1_n. The second light-emitting control transistor T5 turns on in response to the valid level of the second light-emitting control signal EM2_n and turns off in response to the invalid level of the second light-emitting control signal EM2_n. Based on this, the time periods of the valid level of the first reset control signal RE1_n, the valid level of the compensation control signal FC_n, and the valid level of the scan signal GA_n fall within the time periods of the invalid level of the first light-emitting control signal EM1_n and the invalid level of the second light-emitting control signal EM2_n. For example, referring to FIG6, taking the invalid level of the first light-emitting control signal EM1_n and the second light-emitting control signal EM2_n as high and the valid level of the first light-emitting control signal EM1_n and the second light-emitting control signal EM2_n as low, the first light-emitting control signal EM1_n and the second light-emitting control signal EM2_n are high in stages D5 to D3 and low in stage D4. That is, stages D5 to D3 are the non-light-emitting stage of the light-emitting element 21, and stage D4 is the light-emitting stage of the light-emitting element 21.

[0133] For example, the first light-emitting control signal EM1_n and the second light-emitting control signal EM2_n can be set to the same signal for easy synchronous control. Further, referring to Figures 3 and 4, the display area AA also includes a first light-emitting control signal line EML1 corresponding to each row of pixel units. The control terminals of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 in the same pixel circuit 11 are interconnected with the corresponding first light-emitting control signal line EML1, reducing the number of signal lines and simplifying wiring. Of course, in other embodiments of this application, the first light-emitting control signal EM1_n and the second light-emitting control signal EM2_n can also be set independently, i.e., different signal lines can be used for input, improving control flexibility.

[0134] To output signals to the control terminals of the first light-emitting control transistor T4 and the second light-emitting control transistor T5, referring to Figures 3 and 4, the plurality of gate driving circuits 20 further includes a first light-emitting control circuit 15. The first light-emitting control circuit 15 includes a plurality of cascaded first light-emitting control shift registers, and the control terminals of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are all connected to the same first light-emitting control shift register. For example, the nth-level first light-emitting control shift register emr1_n is connected to the control terminals of the first light-emitting control transistor T4 and the second light-emitting control transistor T5. Exemplarily, the output terminal of the nth-level first light-emitting control shift register emr1_n is connected to the control terminals of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 in the pixel circuit 11 of the nth row pixel unit through the first light-emitting control signal line EML1 corresponding to the nth row pixel unit, so as to output the same signal to the control terminals of the first light-emitting control transistor T4 and the second light-emitting control transistor T5 through the nth-level first light-emitting control shift register emr1_n. In addition, during operation, the timing controller 163 outputs control signals to each of the first light emission control shift register units, thereby controlling each of the first light emission control shift register units to output the first light emission control signal EM1_n in sequence.

[0135] The pixel circuit in this embodiment can also reset the anode of the light-emitting element 21 to adjust the anode voltage of the light-emitting element 21 to a predetermined level, helping to eliminate the non-uniformity of low grayscale brightness. For example, referring to FIG4, the pixel circuit 11 further includes a second reset transistor T6. The first terminal of the second reset transistor T6 is used to receive a second initialization signal VINIT2. The first terminal of the second reset transistor T6 is connected to the anode of the light-emitting element 21. The control terminal of the second reset transistor T6 is used to receive a second reset control signal RE2_n, so that the second reset transistor T6 is turned on in response to the effective level of the second reset control signal RE2_n, thereby inputting the second initialization signal VINIT2 to the anode of the light-emitting element 21 to reset the anode of the light-emitting element 21. To avoid the anode reset process affecting the input of other signals, the effective level of the second reset control signal RE2_n can be interspersed within the time period of the ineffective level of the second light-emitting control signal EM2_n. Therefore, the effective level time period of the second reset control signal RE2_n can be any stage within the ineffective level time period of the second light-emitting control signal EM2_n. For example, referring to FIG6, taking the effective level of the second reset control signal RE2_n as low as an example, the high level of the second light emission control signal EM2_n appears in stages D5 to D3, and the low level of the second reset control signal RE2_n can appear in any stage from stage D5 to D3.

[0136] To output a control signal to the second reset transistor T6, referring to Figures 3 and 4, the plurality of gate drive circuits 20 further includes a second reset control circuit 14. The control terminal of the second reset transistor T6 is connected to the second reset control circuit 14 to output a second reset control signal RE2_n to the second reset transistor T6 through the second reset control circuit 14. For example, the second reset control circuit 14 includes a plurality of cascaded second reset shift register units. The nth-stage second reset shift register unit rer2_n is connected to the control terminal of the second reset transistor T6. Exemplarily, the display area AA also includes a first reset signal line REL1 corresponding to each row of pixel units. The output terminal of the nth-stage second reset shift register unit rer2_n is connected to the control terminal of the second reset transistor T6 in the nth row of pixel units through the first reset signal line REL1 corresponding to the nth row of pixel units, so as to output the second reset control signal RE2_n to the second reset transistor T6 through the nth-stage first reset shift register unit rer1_n. In addition, during operation, the timing controller 163 outputs control signals to each of the second reset shift registers, controlling each of the second reset shift registers to output the required signals in sequence.

[0137] The pixel circuit 11 in this embodiment can also perform an OBS process to reduce the hysteresis effect of the driving transistor T0. For example, referring to FIG4, the pixel circuit 11 further includes a third reset transistor T7. The first terminal of the third reset transistor T7 is used to receive a third initialization signal VINIT3. The second terminal of the third reset transistor T7 is connected to the second terminal of the driving transistor T0. The control terminal of the third reset transistor T7 is used to receive a third reset control signal RE3_n, causing the third reset transistor T7 to turn on in response to the effective level of the third reset control signal RE3_n, inputting the third initialization signal VINIT3 to the first terminal of the driving transistor T0. When the driving transistor T0 is turned on, the third initialization signal VINIT3 is also input to the second terminal of the driving transistor T0, resetting both the first and second terminals of the driving transistor T0 and reducing the hysteresis effect of the driving transistor T0. Furthermore, to avoid the mutual interference between resetting the first and second terminals of the driving transistor T0, resetting the control terminal of the driving transistor T0, and writing the data voltage signal DA, the effective level of the third reset control signal RE3_n and the effective level of the scan signal GA_n can be designed not to overlap in duration, and the effective level of the third reset control signal RE3_n also cannot overlap in duration with the effective levels of the first reset control signal RE1_n and the compensation control signal FC_n. In some embodiments of this application, the effective level of the third reset control signal RE3_n can appear after the effective levels of the compensation control signal FC_n and the scan signal GA_n. For example, referring to FIG6, taking the effective level of the third reset control signal RE3_n as low as an example, the low level of the third reset control signal RE3_n appears in stage D3, the high level of the compensation control signal FC_n appears in stages D1 and D2, and the high level of the scan signal GA_n appears in stage D2. Furthermore, the effective level of the third reset control signal RE3_n can also occur before the effective level of the first reset control signal RE1_n. For example, referring to Figure 4, the low level of the third reset control signal RE3_n occurs in stage D5, and the high level of the first reset control signal RE1_n occurs in stages D6 and D1. It is understood that the low level of the third reset control signal RE3_n may or may not occur in stage D5, but the low level of the third reset control signal RE3_n must occur in stage D3 to ensure that the OBS process is performed after the data voltage signal DA is written and before the light-emitting element 21 emits light.

[0138] For example, the second reset control signal RE2_n and the third reset control signal RE3_n can be set to the same signal for easy synchronous control. Further, referring to Figures 3 and 4, the control terminals of the second reset transistor T6 and the third reset transistor T7 are both connected to the same second reset shift register unit rer2_n. That is, the output terminal of the nth-stage second reset shift register unit rer2_n is connected to the control terminals of the second reset transistor T6 and the third reset transistor T7 in the nth-row pixel unit via the first reset signal line REL1 corresponding to the nth-row pixel unit. This allows the same signal to be output to the second reset transistor T6 and the third reset transistor T7 through the nth-stage first reset shift register unit rer1_n, and also reduces the number of signal lines and wiring complexity. In other embodiments of this application, the second reset control signal RE2_n and the third reset control signal RE3_n can also be set independently, i.e., different signal lines can be used for input, improving control flexibility.

[0139] In specific implementations, the driving transistor T0, the first reset transistor T1, the threshold compensation transistor T2, the data writing transistor T3, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the second reset transistor T6, and the third reset transistor T7 can be configured as thin-film transistors (TFTs). The gate of the TFT can be the aforementioned control terminal, and the source of the TFT can be the aforementioned first terminal, and the drain of the TFT can be the aforementioned second terminal; alternatively, the source of the TFT can be the aforementioned second terminal, and the drain of the TFT can be the aforementioned first terminal. No specific limitation is imposed here.

[0140] LTPS TFTs, fabricated using low-temperature poly-silicon (LTPS) semiconductor materials as the active layer, exhibit high electron mobility and better switching speed, resulting in fast response. However, the high electron mobility of LTPS TFTs leads to relatively large leakage current, resulting in high power consumption at low frequencies and difficulty in maintaining static black levels, leading to poor image quality. Reducing the leakage current of LTPS TFTs requires increasing their size, impacting resolution and pixel density (Pixels Per Inch, PPI). Furthermore, oxide TFTs, fabricated using metal-oxide semiconductor materials (such as indium gallium zinc oxide (IGZO)) as the active layer, possess low leakage current and high uniformity, allowing LTPS TFTs and oxide TFTs to complement each other. Therefore, in this embodiment, some transistors can be configured as Oxide TFTs and others as LTPS TFTs. By combining Oxide TFTs and LTPS TFTs to form a Low Temperature Poly-Silicon Oxide (LTPO) pixel circuit, and applying this LTPO pixel circuit to the display panel, the power consumption of the display panel operating at low refresh rates can be reduced. Simultaneously, it can improve the problem of low refresh rate display abnormalities caused by LTPS TFT leakage, and improve the uniformity of display brightness. Based on this, in some embodiments of this application, the first reset transistor T1 and the threshold compensation transistor T2 can be configured as Oxide TFTs to reduce leakage of the storage capacitor CST and improve problems such as dark-state light leakage of the light-emitting element 21. Furthermore, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the second reset transistor T6, the third reset transistor T7, the data writing transistor T3, and the driving transistor T0 can be configured as LTPS TFTs to improve electron mobility.

[0141] In other embodiments of this application, all transistors in the pixel circuit 11 may be configured as P-type LTPS TFTs or N-type Oxide TFTs, and this is not limited here.

[0142] For example, the transistor configured as an LTPS TFT can be a P-type TFT, and the transistor configured as an Oxide TFT can be an N-type TFT. For instance, the first reset transistor T1 and the threshold compensation transistor T2 are N-type TFTs, while the first light-emitting control transistor T4, the second light-emitting control transistor T5, the second reset transistor T6, the third reset transistor T7, the data writing transistor T3, and the driving transistor T0 are P-type TFTs.

[0143] The working process of the pixel circuit provided in the embodiments of this application will be described below with reference to Figures 4 and 6. Specifically, in a display frame, the working process of the pixel circuit in any sub-pixel may include: D5 stage, D6 stage, D1 stage, D2 stage, D3 stage and D4 stage, wherein D5 stage is the third reset stage, D6 stage is the fourth reset stage, D1 stage is the first reset stage, D2 stage is the data input and compensation stage, D3 stage is the second reset stage, and D4 stage is the light emission stage.

[0144] During stage D5, both the second reset control signal RE2_n and the third reset control signal RE3_n are low, and both the second reset transistor T6 and the third reset transistor T7 are turned on. The second initialization signal VINIT2 is input to the anode of the light-emitting element 21 to reset the anode of the light-emitting element 21, thereby adjusting the anode voltage of the light-emitting element 21 to a predetermined level and helping to eliminate the unevenness of low grayscale brightness. The third initialization signal VINIT3 is input to the second terminal of the driving transistor T0, which is turned on under the voltage control of its control terminal and the second terminal. The third initialization signal VINIT3 is also input to the first terminal of the driving transistor T0 to reset the first and second terminals of the driving transistor T0, realizing the OBS process and reducing the hysteresis effect of the driving transistor T0. Furthermore, the first light emission control signal EM1_n, the second light emission control signal EM2_n, and the scan signal GA_n are all high, and the first light emission control transistor T4, the second light emission control transistor T5, and the data writing transistor T3 are all turned off. Both the first reset control signal RE1_n and the compensation control signal FC_n are at a low level, and both the first reset transistor T1 and the threshold compensation transistor T2 are turned off. It is worth noting that the voltage difference between the anode and cathode of the light-emitting element 21 needs to be greater than or equal to the minimum turn-on voltage V of the light-emitting element 21. L It only emits light when the light-emitting element 21 is activated. Therefore, to prevent the light-emitting element 21 from emitting light, the voltage V of the second initialization signal VINIT2 can be adjusted. init2 With voltage V ss The difference V between init2 -V ss Less than the on-state voltage V L V init2 -V ss <V L For example, V init2 ≤0V, for example, V init2 The voltage can be 0V, -1V, -2V, -3V, or other negative voltages; no specific limitation is made here. Furthermore, in order to input the third initialization signal VINIT3 into the first and second terminals of the driving transistor T0, the voltage V of the third initialization signal VINIT3 can be... init3When the voltage is set to positive, so that the third initialization signal VINIT3 is input to the second terminal of the driving transistor T0, the driving transistor T0 can be turned on, thereby causing the third initialization signal VINIT3 to also be input to the first terminal of the driving transistor T0. For example, V... init3 ≥4V. For example, V init3 It can be set to 4V, 5V, 6V, 7V or other positive voltages, without limitation.

[0145] In stage D6, the first reset control signal RE1_n is high, the first reset transistor T1 is turned on, and the first initialization signal VINIT1 is input to the second terminal of the driving transistor T0 to reset the control terminal of the driving transistor T0. The first light emission control signal EM1_n, the second light emission control signal EM2_n, the second reset control signal RE2_n, the third reset control signal RE3_n, and the scan signal GA_n are all high, while the compensation control signal FC_n is low, and the threshold compensation transistors T2 to T7 are all turned off.

[0146] In stage D1, both the first reset control signal RE1_n and the compensation control signal FC_n are high, the first reset transistor T1 and the threshold compensation transistor T2 are both turned on, and the first initialization signal VINIT1 is input to the control terminal and the second terminal of the driving transistor T0 to reset the control terminal and the second terminal of the driving transistor T0. Furthermore, the first light emission control signal EM1_n, the second light emission control signal EM2_n, the second reset control signal RE2_n, the third reset control signal RE3_n, and the scan signal GA_n are all high, and the data writing transistors T3 to T7 are all turned off. It is worth mentioning that the voltage V of the first initialization signal VINIT1... init1 For example, V is a negative voltage. init1 ≤-2V. For example, V init1 It can be set to -2V, -3V, -4V, -5V or other negative voltages, without limitation here.

[0147] In stage D2, the compensation control signal FC_n is high, and the threshold compensation transistor T2 is turned on. The scan signal GA_n is low, and the data writing transistor T3 is turned on. The data voltage signal DA is input to the control terminal of the driving transistor T0 through the data writing transistor T3 and the threshold compensation transistor T2, and the threshold voltage Vth of the driving transistor T0 is also input to the control terminal of the driving transistor T0, making the voltage at the control terminal of the driving transistor T0 Vda + Vth, where Vda represents the voltage of the data voltage signal DA. Furthermore, the first light emission control signal EM1_n, the second light emission control signal EM2_n, the second reset control signal RE2_n, and the third reset control signal RE3_n are all high, and the first light emission control transistor T4 to the third reset transistor T7 are all turned off. The first reset control signal RE1_n is low, and the first reset transistor T1 is turned off.

[0148] In stage D3, both the second reset control signal RE2_n and the third reset control signal RE3_n are low, and both the second reset transistor T6 and the third reset transistor T7 are turned on. The second initialization signal VINIT2 is input to the anode of the light-emitting element 21 to reset the anode of the light-emitting element 21, thereby adjusting the anode voltage of the light-emitting element 21 to a predetermined level and helping to eliminate the non-uniformity of low grayscale brightness. The third initialization signal VINIT3 is input to the second terminal of the driving transistor T0, which can turn on the driving transistor T0 under the voltage control of its control terminal and the second terminal. The third initialization signal VINIT3 is input to the first terminal of the driving transistor T0 to reset the first terminal and the second terminal of the driving transistor T0, realizing the OBS process and reducing the hysteresis effect of the driving transistor T0. Furthermore, the first light emission control signal EM1_n, the second light emission control signal EM2_n, and the scan signal GA_n are all high, and the first light emission control transistor T4, the second light emission control transistor T5, and the data writing transistor T3 are all turned off. Both the first reset control signal RE1_n and the compensation control signal FC_n are at a low level, and both the first reset transistor T1 and the threshold compensation transistor T2 are turned off.

[0149] During stage D4, both the first light-emitting control signal EM1_n and the second light-emitting control signal EM2_n are at low levels, and both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 are turned on. The voltage Vdd transmitted on the first power line VDDL is input to the first terminal of the driving transistor T0, causing the driving transistor T0 to generate a driving current I = K(Vda + Vth - Vdd - Vth) based on the voltage Vda + Vth at its control terminal and the voltage Vdd at its first terminal. 2 =K(Vda-Vdd) 2 K = (μC) oxW) / (2L), where L represents the length of the channel of the driving transistor T0, W represents the width of the channel of the driving transistor T0, and C ox The capacitance per unit area of ​​the gate insulating layer of the driving transistor T0 is represented by μ, and the mobility of the driving transistor T0 is represented by μ. These are structural parameters, and these values ​​are relatively stable within the same structure and can be considered constants. Furthermore, since the second light-emitting control transistor T5 is turned on, the driving current I is input into the light-emitting element 21, which can drive the light-emitting element 21 to emit light. It is understood that the voltage Vdd transmitted on the first power line VDDL can be configured as a constant high voltage, which is a positive value. The second power line VSSL can be loaded with a constant low voltage, which can be ground voltage or a negative value. In practical applications, the specific values ​​of the voltages transmitted on the first power line VDDL and the second power line VSSL can be determined according to the actual application scenario and are not limited here. Furthermore, the first reset control signal RE1_n and the compensation control signal FC_n are both low, and the first reset transistor T1 and the threshold compensation transistor T2 are both off. The second reset control signal RE2_n and the third reset control signal RE3_n are both high, and the second reset transistor T6 and the third reset transistor T7 are both off. When the scan signal GA_n is high, the data writing transistor T3 is turned off.

[0150] It is worth mentioning that, in this embodiment, during stage D2, the threshold voltage Vth is written to the control terminal of the driving transistor T0. This makes the formula for the driving current I during the light-emitting stage independent of the threshold voltage Vth, but related to the voltages Vdd and Vda. This solves the problem of uneven brightness caused by the drift of the threshold voltage Vth. Furthermore, by compensating for the threshold voltage Vth simultaneously with the input data voltage signal DA, it is also beneficial to achieve high-frequency driving. Furthermore, referring to Figure 6, the duration of the low level of the scan signal GA_n is within the duration of the high level of the compensation control signal FC_n. When the data writing transistor T3 is turned on, the threshold compensation transistor T2 is turned on, and after the data writing transistor T3 is turned off for a certain period of time, the threshold compensation transistor T2 is turned off again, so that the voltage at the first end of the driving transistor T0 continues to charge the control end of the driving transistor T0 through the driving transistor T0 and the threshold compensation transistor T2, so that the threshold voltage Vth is completely written to the control end of the driving transistor T0, which can make the threshold voltage Vth compensation more sufficient. Therefore, when the pixel compensation circuit provided in this embodiment of the invention is applied to the display panel 161, especially to the display panel 161 with a high refresh rate, the display effect of the image on the display panel 161 can be improved.

[0151] In some embodiments of this application, the D5 stage may be omitted, meaning that both the second reset control signal RE2_n and the second reset control signal RE2_n are at a high level during the D5 stage, which further facilitates the realization of high-frequency driving.

[0152] To accommodate different application scenarios, the display panel 161 can operate at multiple different refresh rates. For example, in static image display scenarios, a lower refresh rate is needed to save power. Alternatively, in high-frequency dynamic image display scenarios (such as game visuals), a higher refresh rate is needed to make the image smoother. Therefore, in this embodiment, the display panel 161 can change its refresh rate to suit different application scenarios. In some embodiments of this application, the display panel 161 can gradually change from one refresh rate to another. For example, the display panel 161 can gradually decrease from a higher refresh rate to a lower refresh rate. For instance, taking the refresh rates of the display panel 161 as 360Hz, 120Hz, 90Hz, 60Hz, 30Hz, and 1Hz as an example, the refresh rate of the display panel 161 can decrease from 120Hz to 90Hz, 60Hz, 30Hz, and finally to 1Hz, and vice versa. This can improve the problem of uneven brightness when switching between different refresh rates. In some embodiments of this application, the display panel 161 may also change directly from a refresh rate to a lower refresh rate. For example, the display panel 161 may change directly from a higher refresh rate to a lower refresh rate. For instance, if the refresh rate of the display panel 161 is 360Hz, 120Hz, 90Hz, 60Hz, 30Hz, or 1Hz, the refresh rate of the display panel 161 may change directly from 120Hz to 30Hz or 1Hz, and vice versa.

[0153] In some embodiments of this application, when the display panel 161 operates at its maximum refresh rate, the signals received by each pixel circuit 11 in a display frame can be driven based on the maximum refresh rate of the display panel 161. For example, taking the pixel circuit 11 and its received signals shown in FIG. 4 as an example, FIG. 7 exemplarily illustrates the signals received by the pixel circuit when the display panel operates at different refresh rates. FIG. 7(a) exemplarily illustrates the signals received by the pixel circuit when the display panel operates at its maximum refresh rate. Referring to FIG. 7(a), when the display panel 161 operates sequentially at its maximum refresh rate (e.g., 360Hz) in the a-th display frame, a+1-th display frame, a+2-th display frame, and a+3-th display frame, the signals received by the pixel circuit 11 in the a-th display frame, a+1-th display frame, a+2-th display frame, and a+3-th display frame are the same as the signals shown in FIG. 6, thereby making the operation process of the pixel circuit 11 in the a-th display frame, a+1-th display frame, a+2-th display frame, and a+3-th display frame essentially the same as the operation process of the pixel circuit in FIG. 4. In summary, when the display panel 161 is driven at the maximum refresh rate, the first reset transistor T1, threshold compensation transistor T2, data writing transistor T3, first light emission control transistor T4, second light emission control transistor T5, second reset transistor T6, and third reset transistor T7 of each pixel circuit 11 are driven based on the maximum refresh rate of the display panel 161.

[0154] In some embodiments of this application, when the display panel 161 operates at a refresh rate lower than the maximum refresh rate, each pixel circuit 11 receives a portion of the signals (e.g., EM1_n / EM2_n, RE1_n / RE2_n) in a display frame, driven based on the maximum refresh rate of the display panel 161, and receives another portion of the signals (e.g., GA_n, RE1_n, FC_n) driven based on the current refresh rate of the display panel 161. Exemplarily, each display frame may include a plurality of consecutive sub-display frames, where the first sub-display frame is defined as a refresh sub-frame, and the remaining sub-display frames are defined as hold sub-frames. The signals received by the pixel circuit in a refresh sub-frame are the same as those shown in FIG. 6. In each hold sub-frame, a portion of the signals received (e.g., EM1_n / EM2_n, RE2_n / RE3_n) are the same as those shown in FIG. 6, and the other portion of the received signals (e.g., GA_n, SR1_n, SR1_n+k) are all at an invalid level.

[0155] For example, taking the pixel circuit 11 shown in FIG4 and the signals it receives as an example, FIG7(b) exemplarily illustrates the signals received by the pixel circuit when the display panel operates at a refresh rate lower than the maximum refresh rate. Referring to FIG7(b), taking a maximum refresh rate of 360Hz as an example, FIG7(b) illustrates the signals received by the pixel circuit in the b-th display frame when the refresh rate is 120Hz. The b-th display frame may include one refresh subframe and two hold subframes (i.e., hold subframe 1 and hold subframe 2). The signals received by the pixel circuit 11 in the refresh subframe are the same as those shown in FIG6. In hold subframe 1 and hold subframe 2, the signals EM1_n / EM2_n and RE2_n / RE3_n are the same as those shown in FIG6, and the signal GA_n is high, while the signals SR1_n and SR1_n+k are low. Figure 7(c) illustrates the signals received by the pixel circuit in the c-th display frame when the refresh rate is 1Hz. The c-th display frame may include one refresh subframe and 359 hold subframes (i.e., hold subframe 1 to hold subframe 359). The signals received by the pixel circuit 11 in the refresh subframe are the same as those shown in Figure 6. In hold subframes 1 to 359, the signals EM1_n / EM2_n and RE2_n / RE3_n are the same as those shown in Figure 6, and the signal GA_n is high, while the signals RE1_n and FC_n are low. In summary, when the display panel 161 is driven at a refresh rate lower than the maximum refresh rate, the first light-emitting control transistor T4, the second light-emitting control transistor T5, the second reset transistor T6, and the third reset transistor T7 of each pixel circuit 11 are driven based on the maximum refresh rate of the display panel 161, while the first reset transistor T1, the threshold compensation transistor T2, and the data writing transistor T3 are driven based on the current refresh rate of the display panel 161.

[0156] In other embodiments of this application, the maximum refresh rate of the display panel 161 may also be set to 240Hz or other values, which are not limited here.

[0157] Figure 8 is a partial structural diagram of a display panel provided in an embodiment of this application. Referring to Figure 8, this embodiment is a modification of the embodiment shown in Figure 4 above. The similarities are not repeated here. The difference is that in the pixel circuit 11, the second terminal of the third reset transistor T7 is connected to the first terminal of the driving transistor T0, which can also realize the OBS process and improve the hysteresis effect of the driving transistor T0. In addition, the working process of the pixel circuit shown in Figure 8 can be referred to the working process of the pixel circuit shown in Figure 4, and the specific details are not repeated here.

[0158] Figure 9 is a partial structural diagram of a display panel provided in an embodiment of this application. Referring to Figure 9, this embodiment is a modification of the embodiment shown in Figure 4 above. The similarities are not repeated here, but the difference is that two light-emitting elements 21_1 to 21_2 are set in each sub-pixel. In practical applications, certain types of terminal devices (e.g., desktop computers, tablets, laptops, etc.) require privacy protection when used in public places. In this case, a smaller viewing angle is better to prevent information leakage. However, these terminal devices also serve entertainment functions, such as games and movies. In these cases, a better visual effect is needed so that people can share this wonderful time with friends. Therefore, two light-emitting elements 21_1 to 21_2 can be set in some or all sub-pixels, that is, the above function is achieved by using one pixel circuit to drive two light-emitting elements 21_1 to 21_2. Of the two light-emitting elements 21_1 and 21_2, one of them, 21_1, emits light with better collimation and a smaller viewing angle. At wide viewing angles, the light emitted by 21_1 is not visible, thus achieving a privacy-preventing display effect when 21_1 is emitting light. The other light-emitting element 21_2 has a better viewing angle; its light is visible at wide viewing angles, allowing for a shared display effect when 21_2 is emitting light. Furthermore, the selection of which light-emitting element 21 emits light can be based on the display requirements of the terminal device to achieve both privacy-preventing and shared display effects.

[0159] In existing technologies, the pixel circuits driving the two light-emitting elements 21_1 to 21_2 can only control these two elements to achieve two light-emitting states: one state is to control the simultaneous illumination of elements 21_1 to 21_2, and the other state is to control the illumination of element 21_1. They cannot independently control the individual illumination of each element. However, if the two elements 21_1 to 21_2 cannot illuminate independently, some elements will not receive compensation, affecting the display effect. Furthermore, this light-emitting driving method is singular, lacks flexibility, and has a limited range of application scenarios. Therefore, in this embodiment, the pixel circuit 11, based on the pixel circuit shown in FIG4, increases the number of second light-emitting control transistors T5 and second reset transistors T6, that is, it sets two second light-emitting control transistors T5_1 to T5_2 and two second reset transistors T6_1 to T6_2 to drive the two light-emitting elements 21_1 to 21_2 to operate in three light-emitting states, thereby realizing the independent light-emitting process of each light-emitting element 21_1 to 21_2, as well as the simultaneous light-emitting process of the light-emitting elements 21_1 to 21_2. It is worth mentioning that the two light-emitting elements 21_1 to 21_2 driven by the same pixel circuit are light-emitting elements of the same color to avoid color mixing and to display color images.

[0160] Referring to Figure 9, the pixel circuit 11 connects two light-emitting elements 21_1 to 21_2, and the pixel circuit 11 includes: a driving transistor T0, a first reset transistor T1, a threshold compensation transistor T2, a data writing transistor T3, a first light-emitting control transistor T4, two second light-emitting control transistors T5_1 to T5_2, two second reset transistors T6_1 to T6_2, a third reset transistor T7, and a storage capacitor CST. The second light-emitting control transistors T5_1 and T6_1 are correspondingly arranged with respect to the light-emitting element 21_1. The first terminal of the second light-emitting control transistor T5_1 is connected to the second terminal of the driving transistor T0, and the second terminal of the second light-emitting control transistor T5_1 is connected to the anode of the light-emitting element 21_1. The first terminal of the second reset transistor T6_1 is used to receive the second initialization signal VINIT2, and the second terminal of the second reset transistor T6_1 is used to connect to the anode of the light-emitting element 21_1. Furthermore, the second light-emitting control transistor T5_2 and the second reset transistor T6_2 are correspondingly arranged with the light-emitting element 21_2. The first terminal of the second light-emitting control transistor T5_2 is connected to the second terminal of the driving transistor T0, and the second terminal of the second light-emitting control transistor T5_2 is connected to the anode of the light-emitting element 21_2. The first terminal of the second reset transistor T6_2 is used to receive the second initialization signal VINIT2, and the second terminal of the second reset transistor T6_2 is used to connect to the anode of the light-emitting element 21_2.

[0161] Furthermore, the control terminal of the second light-emitting control transistor T5_1 is used to receive the second light-emitting control signal EM2a_n, so that the second light-emitting control transistor T5_1 is turned on under the control of the effective level of the second light-emitting control signal EM2a_n, and turned off under the control of the ineffective level of the second light-emitting control signal EM2a_n.

[0162] The control terminal of the second light-emitting control transistor T5_2 is used to receive the second light-emitting control signal EM2b_n, so that the second light-emitting control transistor T5_2 is turned on under the control of the effective level of the second light-emitting control signal EM2b_n, and turned off under the control of the ineffective level of the second light-emitting control signal EM2b_n.

[0163] In order to enable the light-emitting elements 21_1 to 21_2 to emit light independently, the first light-emitting control signal EM1_n, the second light-emitting control signal EM2a_n, and the second light-emitting control signal EM2b_n can be input through different signal lines, so that the control of the first light-emitting control transistor T4 and the second light-emitting control transistors T5_1 to T5_2 are decoupled from each other and do not interfere with each other.

[0164] To output a signal to the control terminal of the first light-emitting control transistor T4, referring to Figures 9 and 10, Figure 10 is a schematic diagram of another structure of the display device provided in an embodiment of this application. The plurality of gate driving circuits 20 further includes a second light-emitting control circuit 16. The control terminal of the first light-emitting control transistor T4 is connected to the second light-emitting control circuit 16 so as to output a corresponding signal to the control terminal of the first light-emitting control transistor T4 through the second light-emitting control circuit 16. For example, the second light-emitting control circuit 16 includes a plurality of cascaded second light-emitting control shift register units. The nth-level second light-emitting control shift register unit emr2_n is connected to the control terminal of the first light-emitting control transistor T4 in the pixel circuit 11 so as to output a corresponding signal to the control terminal of the first light-emitting control transistor T4 through the nth-level second light-emitting control shift register unit emr2_n. For example, the display area AA also includes a second light-emitting control signal line EML2 corresponding to each row of pixel units. The output terminal of the nth-level second light-emitting control shift register unit eMR2_n is connected to the control terminal of the first light-emitting control transistor T4 in the pixel circuit 11 of the nth row of pixel units through the second light-emitting control signal line EML2 corresponding to the nth row of pixel units. Furthermore, during operation, the timing controller 163 outputs control signals to each second light-emitting control shift register unit, controlling each second light-emitting control shift register unit to sequentially output the first light-emitting control signal.

[0165] To output signals to the control terminals of each of the second light-emitting control transistors T5_1 to T5_2, referring to Figures 9 and 10, the plurality of gate driving circuits 20 further includes two third light-emitting control circuits 17a and 17b. The third light-emitting control circuit 17a is connected to the control terminal of the second light-emitting control transistor T5_1, and the third light-emitting control circuit 17b is connected to the control terminal of the second light-emitting control transistor T5_2. This allows the third light-emitting control circuit 17a to output corresponding signals to the control terminal of the second light-emitting control transistor T5_1, and the third light-emitting control circuit 17b to output corresponding signals to the control terminal of the second light-emitting control transistor T5_2. For example, the third light-emitting control circuit 17a includes a plurality of cascaded third light-emitting control shift register units. The nth-level third light-emitting control shift register unit emr3a_n is connected to the control terminal of the second light-emitting control transistor T5_1 in the pixel circuit 11, so that the nth-level third light-emitting control shift register unit emr3a_n can output corresponding signals to the control terminal of the second light-emitting control transistor T5_1. The third light-emitting control circuit 17b includes a plurality of cascaded third light-emitting control shift register units. The nth-level third light-emitting control shift register unit emr3b_n is connected to the control terminal of the second light-emitting control transistor T5_2 in the pixel circuit 11, so as to output a corresponding signal to the control terminal of the second light-emitting control transistor T5_2 through the nth-level third light-emitting control shift register unit emr3b_n. For example, the display area AA also includes third light-emitting control signal lines EML3a to EML3b corresponding to each row of pixel units. The output terminal of the nth-level third light-emitting control shift register unit emr3a_n is connected to the control terminal of the second light-emitting control transistor T5_1 through the third light-emitting control signal line EML3a corresponding to the nth row of pixel units. The output terminal of the nth-level third light-emitting control shift register unit emr3b_n is connected to the control terminal of the second light-emitting control transistor T5_2 in the pixel circuit 11 through the third light-emitting control signal line EML3b corresponding to the nth row of pixel units. In addition, during operation, the timing controller 163 outputs control signals to each of the third light emission control shift register units emr3a_n and emr3b_n, controlling each of the third light emission control shift register units emr3a_n and emr3b_n to output the required signals.

[0166] It is understood that, in some embodiments of this application, the structure of the second light-emitting control circuit 16 can be adjusted to connect the second light-emitting control signal line EML2 and the third light-emitting control signal lines EML3a to EML3b corresponding to the nth row pixel unit to the same second light-emitting control circuit 16, thereby eliminating the third light-emitting control circuits 17a to 17b and further achieving a narrow bezel. Furthermore, during operation, the timing controller 163 outputs control signals to the second light-emitting control circuit, controlling the second light-emitting control circuit to output the required signals.

[0167] Referring to Figure 9, the control terminal of the second reset transistor T6_1 is used to receive the second reset control signal RE2_n. Therefore, the second reset transistor T6_1 can be turned on under the control of the valid level of the second reset control signal RE2_n, and turned off under the control of the invalid level of the second reset control signal RE2_n. Similarly, the control terminal of the second reset transistor T6_2 is used to receive the second reset control signal RE2_n. Therefore, the second reset transistor T6_2 can be turned on under the control of the valid level of the second reset control signal RE2_n, and turned off under the control of the invalid level of the second reset control signal RE2_n. The control terminals of the third reset transistor T7, the second reset transistor T6_1, and the second reset transistor T6_2 can be interconnected to input the same signal through the same signal line, reducing the number of signal lines and simplifying wiring.

[0168] It is understood that the connection relationships and implementation methods of the remaining transistors in the pixel circuit of this embodiment can refer to the description in the foregoing embodiments, and will not be repeated here. Furthermore, to clearly illustrate the structure of the display panel in this embodiment, Figure 9 illustrates an example of setting two light-emitting elements 21_1 to 21_2 in a sub-pixel. In other embodiments of this application, three, four, or more light-emitting elements can be set in the sub-pixel to improve the PPI. Moreover, when three, four, or more light-emitting elements are set, the second reset transistor and the second light-emitting control transistor corresponding to any light-emitting element satisfy the above-described structural relationship between the second reset transistor and the second light-emitting control transistor, which will not be repeated here.

[0169] The following section, in conjunction with the signal timing diagram, describes in detail the process by which the pixel circuit shown in Figure 9 drives the light-emitting elements 21_1 to 21_2 to emit light independently and simultaneously.

[0170] Figure 11a is a signal timing diagram of the pixel circuit shown in Figure 9 driving the light-emitting elements to emit light simultaneously. In a display frame, the operation of the pixel circuit 11 in any sub-pixel can include stages D5, D6, D1, D2, D3, and D4. In stages D5, D6, D1, D2, and D3, the first light-emitting control transistor T4 and the second light-emitting control transistors T5_1 to T5_2 are both off. In stage D4, the first light-emitting control transistor T4 and the second light-emitting control transistors T5_1 to T5_2 are both on. In stages D5 and D3, the second reset transistors T6_1 to T6_2 are all on. In stages D6, D1, D2, and D4, the second reset transistors T6_1 to T6_2 are all off. The operation of the remaining transistors in each stage can be referred to the operation process of Figure 4 based on Figure 6, and will not be described in detail here. With this configuration, the pixel circuit 11 drives the light-emitting elements 21_1 to 21_2 to emit light simultaneously.

[0171] Figure 11b is a signal timing diagram of the pixel circuit shown in Figure 9 driving a light-emitting element to emit light. In a display frame, the operation of the pixel circuit 11 in any sub-pixel can include stages D5, D6, D1, D2, D3, and D4. The second light-emitting control signal EM2b_n is high, controlling the second light-emitting control transistor T5_2 to be off in this display frame. In stages D5, D6, D1, D2, and D3, both the first light-emitting control transistor T4 and the second light-emitting control transistor T5_1 are off. In stage D4, both the first light-emitting control transistor T4 and the second light-emitting control transistor T5_1 are on. In stages D5 and D3, the second reset transistors T6_1 to T6_2 are on. In stages D6, D1, D2, and D4, the second reset transistors T6_1 to T6_2 are off. The operation of the remaining transistors in each stage can be referred to the operation process in Figure 4 based on Figure 6, and will not be elaborated here. With this configuration, pixel circuit 11 drives light-emitting element 21_1 to emit light, while light-emitting element 21_2 does not emit light.

[0172] Figure 11c is a signal timing diagram of the pixel circuit shown in Figure 9 driving another light-emitting element to emit light. In a display frame, the operation of the pixel circuit 11 in any sub-pixel can include stages D5, D6, D1, D2, D3, and D4. The second light-emitting control signal EM2a_n is high, controlling the second light-emitting control transistor T5_1 to be off in this display frame. In stages D5, D6, D1, D2, and D3, both the first light-emitting control transistor T4 and the second light-emitting control transistor T5_2 are off. In stage D4, both the first light-emitting control transistor T4 and the second light-emitting control transistor T5_2 are on. In stages D5 and D3, the second reset transistors T6_1 to T6_2 are on. In stages D6, D1, D2, and D4, the second reset transistors T6_1 to T6_2 are off. The operation of the remaining transistors in each stage can be referred to the operation process in Figure 4 based on Figure 6, and will not be elaborated here. With this configuration, pixel circuit 11 drives light-emitting element 21_2 to emit light, while light-emitting element 21_1 does not emit light.

[0173] Furthermore, the display panel provided in this embodiment can also operate at multiple different refresh rates. The specific process can be referred to the description in the above embodiments, and will not be repeated here.

[0174] Figure 12 is a partial structural diagram of a display panel provided in an embodiment of this application. Referring to Figure 12, this embodiment modifies the embodiment shown in Figure 9 above. The similarities are not repeated here, but the differences are: the control terminals of the third reset transistor T7 and the second reset transistors T6_1 to T6_2 are connected to different gate drive circuits. That is, the second reset control signal RE2_n and the third reset control signal RE3_n are output using different gate drive circuits, allowing the anode reset and OBS processes to be controlled by different signals, thus improving control flexibility. For example, the frequency of the anode reset can be reduced to improve the display effect.

[0175] Referring, as exemplarily to Figures 12 and 13, Figure 13 is a schematic diagram of another structure of the display device provided in an embodiment of this application. The plurality of gate driving circuits 20 further include a second reset control circuit 14 and a third reset control circuit 18. The control terminals of the second reset transistors T6_1 to T6_2 are connected to the second reset control circuit 14, so that the second reset control circuit 14 outputs corresponding signals to the control terminals of the second reset transistors T6_1 to T6_2. Furthermore, the control terminal of the third reset transistor T7 is connected to the third reset control circuit 18, so that the third reset control circuit 18 outputs corresponding signals to the control terminal of the third reset transistor T7.

[0176] For example, the second reset control circuit 14 includes a plurality of cascaded second reset shift register units. The nth-level second reset shift register unit rer2_n is connected to the control terminal of the second reset transistors T6_1 to T6_2 in the pixel circuit 11 so as to output the same signal to the second reset transistors T6_1 to T6_2 through the nth-level second reset shift register unit rer2_n.

[0177] For example, the third reset control circuit 18 includes a plurality of cascaded third reset shift register units. The nth-level third reset shift register unit rer3_n is connected to the control terminal of the third reset transistor T7 in the pixel circuit 11 so as to output a corresponding signal to the third reset transistor T7 through the nth-level third reset shift register unit rer3_n.

[0178] In addition, during operation, the timing controller 163 outputs control signals to each second reset shift register unit and each third reset shift register unit, controlling each second reset shift register unit to output the second reset control signal RE2_n in sequence, and controlling each third reset shift register unit to output the third reset control signal RE3_n in sequence.

[0179] For example, the display area AA also includes a first reset signal line REL1 and a second reset signal line REL2 corresponding to each row of pixel units. The control terminals of the second reset transistors T6_1 to T6_2 in the pixel circuit 11 are connected to the corresponding first reset signal line REL1, and the control terminal of the third reset transistor T7 in the pixel circuit 11 is connected to the corresponding second reset signal line REL2. Furthermore, the output terminal of the nth-stage second reset shift register unit rer2_n is connected to the control terminals of the second reset transistors T6_1 to T6_2 in the nth-row pixel unit via the first reset signal line REL1 corresponding to the nth-row pixel unit. The output terminal of the nth-stage third reset shift register unit rer3_n is connected to the control terminal of the third reset transistor T7 in the nth-row pixel unit via the second reset signal line REL2 corresponding to the nth-row pixel unit.

[0180] In some embodiments of this application, each of the second reset transistors T6_1 to T6_2 is configured as an Oxide TFT, such as an N-type Oxide TFT, so that the second initialization signal VINIT2 can be input to the anode of the light-emitting elements 21_1 to 21_2, so that the anode of the light-emitting elements 21_1 to 21_2 is reset more thoroughly.

[0181] Understandably, since the second light-emitting control transistors T5_1 to T6_2 are all off when the second reset transistors T6_1 to T6_2 are turned on, the effective level of the second reset control signal RE2_n can appear in any stage from D5 to D3. For example, the effective level of the second reset control signal RE2_n appears in stage D6, and is inactive in the remaining stages. For instance, referring to Figures 14a to 14c, Figure 14a is a signal timing diagram of the pixel circuit shown in Figure 12 driving two light-emitting elements 21_1 to 21_2 to emit light simultaneously; Figure 14b is a signal timing diagram of the pixel circuit shown in Figure 12 driving one light-emitting element 21_1 to emit light; and Figure 14c is a signal timing diagram of the pixel circuit shown in Figure 12 driving another light-emitting element 21_2 to emit light. In this case, the second reset transistors T6_1 to T6_2 are turned on in stage D6 and are off in the other stages. Furthermore, the operation of the remaining transistors in each stage can be referred to in Figure 9 based on the operation of Figures 11a to 11c, and will not be elaborated here. With this configuration, the pixel circuit 11 can drive the light-emitting elements 21_1 to 21_2 to emit light simultaneously, or drive the light-emitting element 21_1 to emit light individually, or drive the light-emitting element 21_2 to emit light individually.

[0182] Furthermore, the display panel 161 provided in this application embodiment can also operate at multiple different refresh rates. The specific process can be referred to the description in the above embodiments, and will not be repeated here. Moreover, in this application embodiment, the anode reset and OBS processes are controlled by different signals, allowing for flexible control of the anode reset frequency. For example, the anode reset frequency can be reduced to improve the display effect.

[0183] Taking the simultaneous illumination of two light-emitting elements 21_1 to 21_2 driven by the pixel circuit as an example, Figure 15 shows the signals received by the pixel circuit when the display panel operates at different refresh rates. Figure 15(a) exemplarily shows the signals received by the pixel circuit when the display panel operates at the maximum refresh rate. Referring to Figure 15(a), when the display panel 161 operates sequentially at the maximum refresh rate (e.g., 360Hz) in the a-th display frame, a+1-th display frame, a+2-th display frame, and a+3-th display frame, the signals received by the pixel circuit in the a-th display frame, a+1-th display frame, a+2-th display frame, and a+3-th display frame are the same as the signals shown in Figure 14a. Therefore, the operation process of the pixel circuit in the a-th display frame, a+1-th display frame, a+2-th display frame, and a+3-th display frame is basically the same as the operation process of the pixel circuit in conjunction with Figure 14a. Figure 15(b) exemplarily illustrates the signals received by the pixel circuit in the b-th display frame when the refresh rate is 120Hz. The b-th display frame may include one refresh subframe and two hold subframes (i.e., hold subframe 1 and hold subframe 2). The signals received by the pixel circuit in the refresh subframe are the same as those shown in Figure 14a. In hold subframes 1 and 2, signals EM1_n, EM2a_n, EM2b_n, and RE3_n are the same as those shown in Figure 14a, and signal GA_n is high, while signals RE1_n, RE2_n, and FC_n are low. Figure 15(c) exemplarily illustrates the signals received by the pixel circuit in the c-th display frame when the refresh rate is 1Hz. The c-th display frame may include one refresh subframe and 359 hold subframes (i.e., hold subframe 1 to hold subframe 359). The signals received by the pixel circuit in the refresh subframe are the same as those shown in Figure 14a. In hold subframes 1 to 359, signals EM1_n, EM2a_n, EM2b_n, and RE3_n are the same as those shown in Figure 14a, and signal GA_n is high, while signals RE1_n, RE2_n, and FC_n are low.

[0184] It is understandable that when the pixel circuit 11 drives the light-emitting element 21_1 or the light-emitting element 21_2 to emit light individually, the received signal can be deduced in the same way, which will not be elaborated here.

[0185] Furthermore, the display panel provided in this embodiment can also operate at multiple different refresh rates. The specific process can be referred to the description in the above embodiments, and will not be repeated here.

[0186] Figure 16 is a partial structural diagram of a display panel provided in an embodiment of this application. Referring to Figure 16, this embodiment is a modification of the embodiment shown in Figure 12 above. The similarities are not repeated here. The difference is that when the second terminal of the third reset transistor T7 is connected to the second terminal of the driving transistor T0 in the pixel circuit 11, in order to reduce the influence of leakage current on the dark state of the light-emitting elements 21_1 to 21_2, the third reset transistor T7 can be set as a dual-gate transistor. For example, the third reset transistor T7 may include a first sub-transistor T7a and a second sub-transistor T7b. The control terminals of the first sub-transistor T7a and the second sub-transistor T7b are connected to each other as the control terminals of the third reset transistor T7. The first terminal of the first sub-transistor T7a is used to receive the third initialization signal VINIT3. The second terminal of the first sub-transistor T7a is connected to the first terminal of the second sub-transistor T7b. The second terminal of the second sub-transistor T7b is connected to the second terminal of the driving transistor T0. Therefore, both the first sub-transistor T7a and the second sub-transistor T7b are turned on in response to a valid level of the second reset control signal RE2_n, and turned off in response to an invalid level of the second reset control signal RE2_n. Furthermore, the operation of the pixel circuit shown in Figure 16 can be compared with the operation of the pixel circuit shown in Figure 12, and will not be elaborated further here.

[0187] It is worth noting that, in this embodiment, the first reset transistor T1 to the second reset transistor T6 are all single-gate transistors for illustration. In practical applications, one or more of the first reset transistor T1 to the second reset transistor T6 can be configured as dual-gate transistors according to the needs of the actual application scenario.

[0188] Figure 17 is a partial structural diagram of a display panel provided in an embodiment of this application. Referring to Figure 17, this embodiment is a modification of the embodiment shown in Figure 12 above. The similarities are not repeated here, but the differences are: in the pixel circuit 11, when the second terminal of the third reset transistor T7 is connected to the first terminal of the driving transistor T0, the third reset transistor T7 can be set as a single-gate transistor to reduce the difficulty of layout design. Furthermore, this setting also enables the OBS process and improves the hysteresis effect of the driving transistor T0. In addition, the operation process of the pixel circuit shown in Figure 17 can be referred to the operation process of the pixel circuit shown in Figure 12, and the specifics are not repeated here.

[0189] Figure 18 is a partial structural schematic diagram of a display panel provided in an embodiment of this application. Referring to Figure 18, this embodiment is a modification of the embodiment shown in Figure 9 above. The similarities are not repeated here, but the differences are: the transistor group further includes two second transistor groups Z2_1 and Z2_2. The second transistor group Z2_1 corresponds to the light-emitting element 21_1. The second transistor group Z2_1 includes a first transistor T21_1 and a second transistor T22_1. The first terminal of the first transistor T21_1 and the first terminal of the second transistor T22_1 are connected through a driving transistor T0, that is, the first terminal of the first transistor T21_1 is connected to the first terminal of the driving transistor T0, and the first terminal of the second transistor T22_1 is connected to the second terminal of the driving transistor T0. The second terminal of the first transistor T21_1 is used to connect to the first power line VDDL, and the second terminal of the second transistor T21_1 is used to connect to the anode of the light-emitting element 21_1. Exemplarily, the first transistor T21_1 and the second transistor T22_1 are LTPS TFTs, such as P-type LTPS TFTs. For example, the first transistor T21_1 and the second transistor T22_1 are single-gate transistors, which can reduce the difficulty of layout design.

[0190] The second transistor group Z2_2 corresponds to the light-emitting element 21_2. The second transistor group Z2_2 includes a first transistor T21_2 and a second transistor T22_2. The first terminal of the first transistor T21_2 and the first terminal of the second transistor T22_2 are connected through a driving transistor T0, i.e., the first terminal of the first transistor T21_2 is connected to the first terminal of the driving transistor T0, and the first terminal of the second transistor T22_2 is connected to the second terminal of the driving transistor T0. The second terminal of the first transistor T21_2 is used to connect to the first power line VDDL, and the second terminal of the second transistor T21_2 is used to connect to the anode of the light-emitting element 21_2. Exemplarily, the first transistor T21_2 and the second transistor T22_2 are LTPS TFTs, such as P-type LTPS TFTs. Exemplarily, the first transistor T21_2 and the second transistor T22_2 are single-gate transistors, which can reduce the complexity of layout design.

[0191] Referring to Figures 18 and 19, Figure 19 is a schematic diagram of another structure of the display device provided in an embodiment of this application. The target gate driving circuit includes two second gate driving circuits 19a and 19b. The second gate driving circuit 19a corresponds to the second transistor group Z2_1, and the control terminals of the first transistor T21_1 and the second transistor T22_1 are connected to the second gate driving circuit 19a. The second gate driving circuit 19a outputs the same control signal EM3a_n to the control terminals of the first transistor T21_1 and the second transistor T22_1. The second gate driving circuit 19b corresponds to the second transistor group Z2_2, and the control terminals of the first transistor T21_2 and the second transistor T22_2 are connected to the second gate driving circuit 19b. The second gate driving circuit 19b outputs the same control signal EM3b_n to the control terminals of the first transistor T21_2 and the second transistor T22_2. This configuration not only reduces one gate driving circuit, further facilitating the realization of a narrow bezel, but also improves the synchronization of the independent light emission of the light-emitting elements 21_1 and 21_2.

[0192] The second gate driving circuit 19a includes a plurality of cascaded second gate shift register units. The nth-level second gate shift register unit sr2a_n is connected to the control terminal of the first transistor T21_1 and the control terminal of the second transistor T22_1 in the corresponding second transistor group Z2_1. The second gate driving circuit 19b includes a plurality of cascaded second gate shift register units. The nth-level second gate shift register unit sr2b_n is connected to the control terminal of the first transistor T21_2 and the control terminal of the second transistor T22_2 in the corresponding second transistor group Z2_2. This configuration not only reduces one gate driving circuit, further facilitating the realization of a narrow bezel, but also improves the synchronization of the independent light emission of the light-emitting elements 21_1 and 21_2.

[0193] For example, the display area AA also includes fourth light-emitting control signal lines EML4a to EML4b corresponding to each row of pixel units. The output terminal of the nth-stage second gate shift register unit sr2a_n is connected to the control terminals of the first transistor T21_1 and the second transistor T22_1 in the nth row of pixel units through the fourth light-emitting control signal line EML4a corresponding to the nth row of pixel units. The output terminal of the nth-stage second gate shift register unit sr2b_n is connected to the control terminals of the first transistor T21_2 and the second transistor T22_2 in the nth row of pixel units through the fourth light-emitting control signal line EML4b corresponding to the nth row of pixel units. Furthermore, during operation, the timing controller 163 outputs control signals to each second gate shift register unit, controlling each second gate shift register unit to output the required signals.

[0194] It is understood that, in order to clearly illustrate the structure of the display panel in the embodiments of this application, FIG18 is illustrated using an example of setting two light-emitting elements 21_1 to 21_2 in a sub-pixel. In other embodiments of this application, three, four or more light-emitting elements may be set in a sub-pixel, thereby increasing the PPI. Furthermore, when three, four or more light-emitting elements are set, the second transistor group corresponding to any light-emitting element satisfies the above-described structural relationship of the second transistor group, which will not be elaborated here.

[0195] For example, referring to Figure 20a, which is a signal timing diagram of the pixel circuit shown in Figure 18 driving a light-emitting element 21_1 to emit light, the control signal EM3b_n is high, and the first transistor T21_2 and the second transistor T22_2 are always off. During stages D5 to D3, the control signal EM3a_n is high, and the first transistor T21_1 and the second transistor T22_1 are off. In stage D4, the control signal EM3a_n is low, and the first transistor T21_1 and the second transistor T22_1 are turned on, causing the light-emitting element 21_1 to emit light. The operation of the remaining transistors in each stage can be referred to in Figure 9 based on the operation of Figure 11b, and will not be elaborated here. With this configuration, the pixel circuit 11 can drive the light-emitting element 21_1 to emit light independently.

[0196] For example, referring to Figure 20b, which is a signal timing diagram of the pixel circuit shown in Figure 18 driving another light-emitting element 21_2 to emit light, the control signal EM3a_n is high, and the first transistor T21_1 and the second transistor T22_1 are always off. In stages D5 to D3, the control signal EM3b_n is high, and the first transistor T21_2 and the second transistor T22_2 are off. In stage D4, the control signal EM3b_n is low, and the first transistor T21_2 and the second transistor T22_2 are turned on, causing the light-emitting element 21_2 to emit light. Furthermore, the operation of the remaining transistors in each stage can be referred to in Figure 9 based on the operation of Figure 11c, and will not be elaborated here. With this configuration, the pixel circuit 11 can drive the light-emitting element 21_2 to emit light independently.

[0197] In some embodiments, the pixel circuit 11 can also control the light-emitting elements 21_1 and 21_2 to emit light simultaneously. However, since the light-emitting element 21_1 can achieve a privacy-preventing display effect when it emits light, and the other light-emitting element 21_2 has better viewing angle characteristics, the light emitted by the light-emitting element 21_2 can be seen at a wide viewing angle. If the light-emitting elements 21_1 and 21_2 are controlled to emit light simultaneously, color mixing may occur. Therefore, in this embodiment, it is preferable to control the light-emitting elements 21_1 and 21_2 to emit light independently to improve the display effect.

[0198] Furthermore, the display panel provided in this embodiment can also operate at multiple different refresh rates. The specific process can be referred to the description in the above embodiments, and will not be repeated here.

[0199] Figure 21 is a partial structural diagram of a display panel provided in an embodiment of this application. Referring to Figure 21, this embodiment is a modification of the embodiment shown in Figure 18 above. The similarities are not repeated here, but the differences are: the first terminal of the first reset transistor T1, the first terminal of the threshold compensation transistor T2, and the control terminal of the driving transistor T0 are interconnected, and the second terminal of the threshold compensation transistor T2 is connected to the second terminal of the driving transistor T0. Thus, the gate reset and threshold voltage compensation processes of the driving transistor T0 can also be realized. Exemplarily, the first reset transistor T1 and the threshold compensation transistor T2 can be LTPS TFTs, for example, P-type LTPS TFTs.

[0200] In some embodiments of this application, to avoid the first initialization signal VINIT1 affecting the Vda input and to perform threshold voltage compensation during Vda writing, the effective level of the scan signal GA_n can be made so that the effective level of the first reset control signal RE1_n does not overlap, and the effective level of the scan signal GA_n overlaps with the effective level of the compensation control signal FC_n. For example, referring to the signal timing diagrams shown in Figures 23a and 23b, taking an example where the effective levels of the compensation control signal FC_n, the first reset control signal RE1_n, and the scan signal GA_n are all low, the low level of the scan signal GA_n does not overlap with the low level of the first reset control signal RE1_n, and the low level of the scan signal GA_n overlaps with the low level of the compensation control signal FC_n. Therefore, the first reset transistor T1 and the data writing transistor T3 cannot be turned on simultaneously, and the threshold compensation transistor T2 and the data writing transistor T3 have a period of simultaneous conduction.

[0201] In some embodiments of this application, to avoid the first initialization signal VINIT1 affecting the Vda input, the effective level of the compensation control signal FC_n and the effective level of the first reset control signal RE1_n can be made to not overlap. For example, referring to the signal timing diagrams shown in Figures 23a and 23b, the low level of the compensation control signal FC_n and the low level of the first reset control signal RE1_n do not overlap. Therefore, the first reset transistor T1 and the data write transistor T3 cannot be turned on simultaneously.

[0202] In some embodiments of this application, when the effective level of the compensation control signal FC_n and the effective level of the first reset control signal RE1_n do not overlap, the effective level of the compensation control signal FC_n and the effective level of the first reset control signal RE1_n may occur multiple times within one frame, and the effective levels of the compensation control signal FC_n and the first reset control signal RE1_n may alternate. For example, referring to Figures 23a and 23b, the low level of the compensation control signal FC_n and the low level of the first reset control signal RE1_n occur multiple times, and the low levels of the compensation control signal FC_n and the first reset control signal RE1_n alternate. This allows the first reset transistor T1 and the threshold compensation transistor T2 to be turned on alternately multiple times, writing the data voltage signal to the gate of the driving transistor T0 as many times as possible, reducing image retention, and improving the display effect, especially when the display panel is used at a lower refresh rate. Furthermore, to clearly illustrate the operation of the pixel circuit in the embodiments of this application, Figures 23a and 23b are shown as examples where the low level of the compensation control signal FC_n and the low level of the first reset control signal RE1_n each appear three times. In other embodiments of this application, the number of times the low level of the compensation control signal FC_n and the low level of the first reset control signal RE1_n appear may be two, four, five, or more times, and is not limited here.

[0203] To reduce the number of gate drive circuits 20, the control terminals of the threshold compensation transistor T2 and the data write transistor T3 can both be connected to the same scan shift register. For example, the control terminals of both the threshold compensation transistor T2 and the data write transistor T3 can be connected to the output terminal of the nth-stage scan shift register gar_n, so that the nth-stage scan shift register gar_n outputs the same signal to the control terminals of the threshold compensation transistor T2 and the data write transistor T3, thereby improving control synchronization. In other embodiments of this application, a separate gate drive circuit can also be used to output the corresponding signal to the control terminal of the threshold compensation transistor T2.

[0204] Referring, as exemplarily to Figures 21 and 22, Figure 22 is a schematic diagram of another structure of the display device provided in an embodiment of this application. The plurality of gate driving circuits 20 further includes a first reset control circuit 21. The control terminal of the first reset transistor T1 is connected to the first reset control circuit 21 to output a corresponding signal to the control terminal of the first reset transistor T1 through the first reset control circuit 21. For example, the first reset control circuit 21 includes a plurality of cascaded first reset shift register units. The nth-level first reset shift register unit rer1_n is connected to the control terminal of the first reset transistor T1 to output a corresponding signal to the control terminal of the first reset transistor T1 through the first reset control circuit 21. Furthermore, during operation, the timing controller 163 outputs control signals to each first reset shift register unit to control each first reset shift register unit to output the required signal. For example, the display area AA also includes a third control signal line SCL corresponding to each row of pixel units. The output terminal of the nth stage first reset shift register unit is connected to the control terminal of the first reset transistor T1 in the nth row of pixel units through the third control signal line SCL corresponding to the nth row of pixel units.

[0205] It is understood that, in order to clearly illustrate the structure of the display panel in the embodiments of this application, FIG21 is illustrated by showing the second terminal of the third reset transistor T7 connected to the first terminal of the driving transistor T0. In other embodiments of this application, the second terminal of the third reset transistor T7 may also be connected to the second terminal of the driving transistor T0.

[0206] The following description, in conjunction with Figures 21 and 23a (Figure 23a being a signal timing diagram illustrating how the pixel circuit shown in Figure 21 drives a light-emitting element 21_1 to emit light), illustrates the operation of the pixel circuit driving the light-emitting element 21_1 to emit light according to the embodiments of this application. Specifically, in a display frame, the operation of the pixel circuit in any sub-pixel can include stages D1, D2, D3, and D4. During this process, the control signal EM3b_n is at a high level, and the first transistor T21_2 and the second transistor T22_2 are always off.

[0207] During stage D1, the first reset control signal RE1_n, the second reset control signal RE2_n, and the third reset control signal RE3_n are all low, and the first reset transistor T1, the second reset transistors T6_1 to T6_2, and the third reset transistor T7 are all turned on, resetting the control terminal, first terminal, second terminal of the driving transistor T0, and the light-emitting elements 21_1 to 21_2. The control signal EM3a_n, the compensation control signal FC_n, and the scan signal GA_n are all high, and the data writing transistor T3, the threshold compensation transistor T2, the first transistor T21_1, and the second transistor T22_1 are all turned off.

[0208] In stage D2, the control signal EM3a_n is high, and both the first transistor T21_1 and the second transistor T22_1 are off. Meanwhile, the compensation control signal FC_n and the scan signal GA_n are low, the data write transistor T3 and the threshold compensation transistor T2 are on, and the data voltage Vda1 in the sub-pixel of the same sub-pixel column and the (n-2)th row pixel unit is written to the control terminal of the driving transistor T0 for pre-charging. The first reset control signal RE1_n is high, and the first reset transistor T1 is off. Afterwards, the first reset control signal RE1_n is low, the first reset transistor T1 is on, and the control terminal of the driving transistor T0 is reset. The compensation control signal FC_n and the scan signal GA_n are high, and the data write transistor T3 and the threshold compensation transistor T2 are off. Subsequently, the compensation control signal FC_n and the scan signal GA_n are low again, and the data writing transistor T3 and the threshold compensation transistor T2 are turned on again. The data voltage Vda2 in the sub-pixel of the same sub-pixel column and the (n-1)th row pixel unit is written to the control terminal of the driving transistor T0 for pre-charging. The first reset control signal RE1_n is high, and the first reset transistor T1 is turned off. Subsequently, the first reset control signal RE1_n is low, and the first reset transistor T1 is turned on, resetting the control terminal of the driving transistor T0. The compensation control signal FC_n and the scan signal GA_n are high, and the data writing transistor T3 and the threshold compensation transistor T2 are turned off. Subsequently, the compensation control signal FC_n and the scan signal GA_n are low again, and the data writing transistor T3 and the threshold compensation transistor T2 are turned on again. The data voltage Vda3 in the sub-pixel of the same sub-pixel column and the nth row pixel unit is written to the control terminal of the driving transistor T0. The first reset control signal RE1_n is high, and the first reset transistor T1 is turned off. This results in the voltage at the control terminal of the driving transistor T0 being Vda3 + Vth. Furthermore, by repeatedly inputting the data voltages of the sub-pixels in the same sub-pixel column of the first two rows of pixel units to the control terminal of the driving transistor T0, the control terminal of the driving transistor T0 is pre-charged, and residual charge at the control terminal of the driving transistor T0 is eliminated, reducing ghosting and improving the display effect.

[0209] During stage D3, the second reset control signal RE2_n and the third reset control signal RE3_n are low, and the second reset transistors T6_1 to T6_2 and the third reset transistor T7 are all turned on, resetting the first and second terminals of the driving transistor T0 and the light-emitting elements 21_1 to 21_2. The first reset control signal RE1_n, the control signal EM3a_n, the compensation control signal FC_n, and the scan signal GA_n are all high, and the first reset transistor T1, the data writing transistor T3, the threshold compensation transistor T2, the first transistor T21_1, and the second transistor T22_1 are all turned off.

[0210] During stage D4, the control signal EM3a_n is at a low level, and the first transistor T21_1 and the second transistor T22_1 are turned on. The driving transistor T0 generates a driving current I = K(Vda3+Vth-Vdd-Vth) based on the voltages Vda3+Vth and Vdd at its control terminal. 2 =K(Vda3-Vdd) 2 The driving current I is input into the light-emitting element 21_1, which can drive the light-emitting element 21_1 to emit light. The first reset control signal RE1_n, the second reset control signal RE2_n, the third reset control signal RE3_n, the compensation control signal FC_n, and the scan signal GA_n are all at high level, and the first reset transistor T1, the second reset transistors T6_1 to T6_2, the third reset transistor T7, the data writing transistor T3, and the threshold compensation transistor T2 are all turned off.

[0211] The following description, in conjunction with Figures 21 and 23b (Figure 23b being a signal timing diagram illustrating how the pixel circuit shown in Figure 21 drives another light-emitting element 21_2 to emit light), illustrates the operation of the pixel circuit driving the light-emitting element 21_2 to emit light according to the embodiments of this application. Specifically, in a display frame, the operation of the pixel circuit in any sub-pixel can include stages D1, D2, D3, and D4. During this stage, the control signal EM3a_n is high, and the first transistor T21_1 and the second transistor T22_1 are always off. Furthermore, the control signal EM3b_n is high during stages D1, D2, and D3, and the first transistor T21_2 and the second transistor T22_2 are off. During stage D4, the control signal EM3b_n is low, and the first transistor T21_2 and the second transistor T22_2 are on, driving the light-emitting element 21_2 to emit light. The operation of the remaining transistors can be referred to the operation process in Figure 21 based on Figure 23a, and will not be elaborated further here.

[0212] Furthermore, the display panel provided in this embodiment can also operate at multiple different refresh rates. The specific process can be referred to the description in the above embodiments, and will not be repeated here.

[0213] Figure 24 is a partial structural diagram of a display panel provided in an embodiment of this application. Referring to Figure 24, this embodiment is a modification of the embodiment shown in Figure 21 above. The similarities are not repeated here. The difference is that the first reset transistor T1 and the threshold compensation transistor T2 are dual-gate transistors, which reduce leakage current and improve display effect. Exemplarily, the first reset transistor T1 includes a third sub-transistor T1a and a fourth sub-transistor T1b. The control terminals of the third sub-transistor T1a and the fourth sub-transistor T1b are interconnected as the control terminals of the first reset transistor T1. The first terminal of the third sub-transistor T1a is used to receive the first initialization signal VINIT1. The second terminal of the third sub-transistor T1a is connected to the first terminal of the fourth sub-transistor T1b. The second terminal of the fourth sub-transistor T1b is connected to the control terminal of the driving transistor T0. The threshold compensation transistor T2 includes a fifth sub-transistor T2a and a sixth sub-transistor T2b. The control terminals of the fifth sub-transistor T2a and the sixth sub-transistor T2b are interconnected as the control terminals of the threshold compensation transistor T2. The first terminal of the fifth sub-transistor T2a is connected to the control terminal of the driving transistor T0. The second terminal of the fifth sub-transistor T2a is connected to the first terminal of the sixth sub-transistor T2b, and the second terminal of the sixth sub-transistor T2b is connected to the second terminal of the driving transistor T0. Furthermore, the operation of the pixel circuit shown in Figure 24 can be compared with the operation of the pixel circuit shown in Figure 21, and will not be elaborated here. In other embodiments of this application, such as in Figure 21, the first reset transistor T1 and the threshold compensation transistor T2 are single-gate transistors, reducing the difficulty of layout design. In addition, the display panel provided in this embodiment can also operate at multiple different refresh rates; the specific process can be referred to the description in the above embodiments, and will not be elaborated here.

[0214] In some embodiments of this application, the first terminal of each second reset transistor is used to receive a corresponding second initialization signal. For example, referring to FIG24, the first terminal of the second reset transistor T6_1 is used to receive the second initialization signal VINIT2_1, and the first terminal of the second reset transistor T6_2 is used to receive the second initialization signal VINIT2_2. The voltages of the second initialization signals VINIT2_1 and VINIT2_2 are different, which can improve the problem of brightness when displaying a black screen, thereby improving contrast. Exemplarily, the voltage of the second initialization signal VINIT2_1 is greater than the voltage of the second initialization signal VINIT2_2, or the voltage of the second initialization signal VINIT2_2 is greater than the voltage of the second initialization signal VINIT2_1. In other embodiments of this application, the voltages of the second initialization signals VINIT2_1 and VINIT2_2 may also be the same. In still other embodiments of this application, the first terminals of the second reset transistors T6_1 and T6_2 can be interconnected to receive the same second initialization signal, which can reduce the number of signal lines and reduce wiring difficulty.

[0215] Figure 25 is a partial structural schematic diagram of a display panel provided in an embodiment of this application. Referring to Figure 25, this embodiment is a modification of the embodiment shown in Figure 24 above. The similarities are not repeated here, but the differences are: the first reset transistor T1 and the threshold compensation transistor T2 are Oxide TFTs, for example, N-type Oxide TFTs. Furthermore, the first reset transistor T1 and the threshold compensation transistor T2 are single-gate transistors, which can reduce the difficulty of layout design.

[0216] In order to input a corresponding signal to the control terminal of the threshold compensation transistor T2, referring to Figures 25 and 26, Figure 26 is a schematic diagram of another structure of the display device provided in the embodiment of this application. The plurality of gate driving circuits 20 further includes a compensation driving circuit 22. The control terminal of the threshold compensation transistor T2 is connected to the compensation driving circuit 22 so that the compensation driving circuit 22 outputs a corresponding signal to the control terminal of the threshold compensation transistor T2. The signals of the control terminal of the threshold compensation transistor T2 and the control terminal of the data writing transistor T3 are decoupled, which can further realize flexible control.

[0217] For example, the compensation driving circuit 22 includes a plurality of cascaded compensation shift register units. The nth-level compensation shift register unit fc_n is connected to the control terminal of the threshold compensation transistor T2, so that the compensation driving circuit 22 outputs a corresponding signal to the control terminal of the threshold compensation transistor T2 to control the on / off state of the threshold compensation transistor T2. For example, the display area AA also includes a compensation control signal line FCL corresponding to each row of pixel units. The output terminal of the nth-level compensation shift register unit fc_n is connected to the control terminal of the threshold compensation transistor T2 through the compensation control signal line FCL corresponding to the nth row of pixel units. In addition, during operation, the timing controller 163 outputs control signals to each compensation shift register unit to control each compensation shift register unit to output the required signals.

[0218] The following description, in conjunction with Figures 25 and 27a (Figure 27a being a signal timing diagram illustrating how the pixel circuit shown in Figure 26 drives a light-emitting element 21_1 to emit light), describes the operation process of the pixel circuit driving the light-emitting element 21_1 to emit light according to the embodiments of this application. Specifically, in a display frame, the operation process of the pixel circuit in any sub-pixel may include: stage D1, stage D2, stage D3, and stage D4. During this process, the control signal EM3b_n is at a high level, and the first transistor T21_2 and the second transistor T22_2 are always off.

[0219] In stage D1, the second reset control signal RE2_n and the third reset control signal RE3_n first appear at a low level. After the second reset control signal RE2_n and the third reset control signal RE3_n transition from low to high, the first reset control signal RE1_n appears at a high level. Specifically, when the second reset control signal RE2_n and the third reset control signal RE3_n are low and the first reset control signal RE1_n is high, the first reset transistor T1, the second reset transistors T6_1 to T6_2, and the third reset transistor T7 are turned on, resetting the control terminal, the first terminal, the second terminal of the driving transistor T0, and the light-emitting elements 21_1 to 21_2. The control signal EM3a_n and the scan signal GA_n are both high, and the data writing transistor T3, the first transistor T21_1, and the second transistor T22_1 are all turned off. The compensation control signal FC_n is low, and the threshold compensation transistor T2 is turned off.

[0220] In stage D2, the control signal EM3a_n is high, and both the first transistor T21_1 and the second transistor T22_1 are off. The compensation control signal FC_n is high, and the threshold compensation transistor T2 is on. The scan signal GA_n is low, the data writing transistor T3 is on, and the data voltage Vda is written to the control terminal of the driving transistor T0, making the voltage at the control terminal of the driving transistor T0 Vda+Vth. The first reset control signal RE1_n is low, the second reset control signal RE2_n and the third reset control signal RE3_n are high, and the first reset transistor T1, the second reset transistors T6_1~T6_2 and the third reset transistor T7 are off.

[0221] In stage D3, the second reset control signal RE2_n and the third reset control signal RE3_n are low, and the second reset transistors T6_1 to T6_2 and the third reset transistor T7 are all turned on, resetting the first and second terminals of the driving transistor T0 and the light-emitting elements 21_1 to 21_2. The first reset control signal RE1_n and the compensation control signal FC_n are low, the first reset transistor T1 and the threshold compensation transistor T2 are turned off, the control signal EM3a_n and the scan signal GA_n are high, and the data writing transistor T3, the first transistor T21_1 and the second transistor T22_1 are all turned off.

[0222] During stage D4, the control signal EM3a_n is at a low level, and the first transistor T21_1 and the second transistor T22_1 are turned on. The driving transistor T0 generates a driving current I = K(Vda + Vth - Vdd - Vth) based on the voltages Vda + Vth and Vdd at its control terminal. 2 =K(Vda-Vdd) 2 The driving current I is input into the light-emitting element 21_1, which can drive the light-emitting element 21_1 to emit light. When the first reset control signal RE1_n and the compensation control signal FC_n are low, the first reset transistor T1 and the threshold compensation transistor T2 are disconnected. When the second reset control signal RE2_n, the third reset control signal RE3_n and the scan signal GA_n are high, the second reset transistors T6_1 to T6_2, the third reset transistor T7 and the data writing transistor T3 are all disconnected.

[0223] The following describes the operation of the pixel circuit driving the light-emitting element 21_2 to emit light, with reference to Figures 25 and 27b. Figure 27b is a signal timing diagram of the pixel circuit shown in Figure 26 driving another light-emitting element 21_2 to emit light. Specifically, in a display frame, the operation of the pixel circuit in any sub-pixel can include stages D1, D2, D3, and D4. During this stage, the control signal EM3a_n is high, and the first transistor T21_1 and the second transistor T22_1 are always off. Furthermore, the control signal EM3b_n is high during stages D1, D2, and D3, and the first transistor T21_2 and the second transistor T22_2 are off. During stage D4, the control signal EM3b_n is low, and the first transistor T21_2 and the second transistor T22_2 are on, driving the light-emitting element 21_2 to emit light. The operation of the remaining transistors can be referred to the operation process in Figure 25 based on Figure 27a, and will not be elaborated here.

[0224] Furthermore, the display panel provided in this embodiment can also operate at multiple different refresh rates. The specific process can be referred to the description in the above embodiments, and will not be repeated here.

[0225] Figure 28 is a partial structural schematic diagram of the display panel provided in another embodiment of this application. Referring to Figure 28, this embodiment is a modification of the embodiment shown in Figure 25 above. The similarities are not repeated here. The differences are: the transistor group further includes a first transistor group Z1, and the target gate driving circuit includes a first gate driving circuit 12, so as to output the compensation control signal FC_n and the first reset control signal RE1_n in Figures 27a and 27b using the first gate driving circuit 12. Furthermore, the connection relationship between the first transistor group Z1 and the first gate driving circuit 12 can be referred to Figure 4, and will not be repeated here. In addition, the working process of the pixel circuit shown in Figure 28 can be referred to the working process of Figures 25 based on Figures 27a and 27b, and will not be repeated here. Moreover, the display panel provided in this embodiment can also operate at multiple different refresh frequencies. The specific process can be referred to the description in the above embodiments, and will not be repeated here.

[0226] The above content is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, include: A pixel unit includes a light-emitting element and a pixel circuit. The pixel circuit includes a driving transistor, a data writing transistor, and a transistor group. A first terminal of the driving transistor is used to connect to a first power supply line, and a second terminal of the driving transistor is used to connect to the anode of the light-emitting element. A control terminal of the data writing transistor is used to receive a scan signal, and a first terminal of the data writing transistor is used to receive a data voltage signal. The second terminal of the data writing transistor is connected to the first terminal of the driving transistor. The transistor group includes a first transistor and a second transistor respectively connected to the driving transistor, and a first terminal of the first transistor is connected to the first terminal of the second transistor. Multiple gate driving circuits, including a target gate driving circuit, wherein the control terminals of the first transistor and the second transistor in the same transistor group are connected to the same target gate driving circuit.

2. The display panel as described in claim 1, characterized in that, The pixel circuit further includes a first reset transistor and a threshold compensation transistor. The control terminal of the first reset transistor is used to receive a first reset control signal, the control terminal of the threshold compensation transistor is used to receive a compensation control signal, and the second terminal of the first reset transistor is used to receive a first initialization signal. In this configuration, the first terminal of the first reset transistor, the first terminal of the threshold compensation transistor, and the second terminal of the driving transistor are interconnected, and the second terminal of the threshold compensation transistor is connected to the control terminal of the driving transistor; or, the first terminal of the first reset transistor, the first terminal of the threshold compensation transistor, and the control terminal of the driving transistor are interconnected, and the second terminal of the threshold compensation transistor is connected to the second terminal of the driving transistor.

3. The display panel as described in claim 2, characterized in that, The transistor group includes a first transistor group, the first reset transistor is the first transistor in the first transistor group, and the threshold compensation transistor is the second transistor in the first transistor group; The target gate driving circuit includes a first gate driving circuit, which is connected to the control terminal of the first reset transistor and the control terminal of the threshold compensation transistor, respectively, and is used to output the first reset control signal to the first reset transistor and the compensation control signal to the threshold compensation transistor.

4. The display panel as described in claim 3, characterized in that, The first gate drive circuit includes a plurality of cascaded first gate shift register units. The nth stage first gate shift register unit is connected to the control terminal of the first transistor in the first transistor group, and the (n+k)th stage first gate shift register unit is connected to the control terminal of the second transistor in the first transistor group. The n and the k are positive integers.

5. The display panel as described in claim 2, characterized in that, The plurality of gate drive circuits further include a first reset control circuit, wherein the control terminal of the first reset transistor is connected to the first reset control circuit.

6. The display panel as described in claim 5, characterized in that, The plurality of gate driving circuits further include a scan driving circuit, which includes a plurality of cascaded scan shift register units. The control terminal of the threshold compensation transistor and the control terminal of the data write transistor are both connected to the same scan shift register unit; or, The plurality of gate driving circuits further include a scan driving circuit and a compensation driving circuit. The control terminal of the data writing transistor is connected to the scan driving circuit, and the control terminal of the threshold compensation transistor is connected to the compensation driving circuit.

7. The display panel as described in any one of claims 2-6, characterized in that, The first reset transistor is turned on in response to the effective level of the first reset control signal, and the threshold compensation transistor is turned on in response to the effective level of the compensation control signal; Wherein, the first terminal of the first reset transistor, the first terminal of the threshold compensation transistor, and the second terminal of the driving transistor are interconnected; the effective level of the compensation control signal is delayed by a set phase difference compared to the effective level of the first reset control signal, and the effective level of the compensation control signal overlaps with the effective level of the first reset control signal; or... The first terminal of the first reset transistor, the first terminal of the threshold compensation transistor, and the control terminal of the driving transistor are interconnected, and the effective level of the compensation control signal does not overlap with the effective level of the first reset control signal.

8. The display panel as described in claim 7, characterized in that, The first terminal of the first reset transistor, the first terminal of the threshold compensation transistor, and the control terminal of the driving transistor are interconnected. Within one frame, the effective level of the compensation control signal appears multiple times, the effective level of the first reset control signal appears multiple times, and the effective level of the compensation control signal and the effective level of the first reset control signal appear alternately.

9. The display panel as described in claim 7 or 8, characterized in that, The data write transistor is turned on in response to the effective level of the scan signal, the effective level of the scan signal not overlapping with the effective level of the first reset control signal, and the effective level of the scan signal overlapping with the effective level of the compensation control signal.

10. The display panel according to any one of claims 2-9, characterized in that, The first reset transistor and the threshold compensation transistor are oxide thin-film transistors; or, The first reset transistor and the threshold compensation transistor are low-temperature polycrystalline silicon thin-film transistors; or, The first reset transistor and the threshold compensation transistor are dual-gate transistors.

11. The display panel as described in any one of claims 1-10, characterized in that, The pixel unit includes at least two light-emitting elements, and the transistor group includes at least two second transistor groups. The at least two second transistor groups correspond one-to-one with the at least two light-emitting elements. In any second transistor group, the first terminal of the first transistor is connected to the first terminal of the driving transistor, the second terminal of the first transistor is used to connect to the first power line, the second terminal of the driving transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is used to connect to the anode of the corresponding light-emitting element. The target gate driving circuit includes at least two second gate driving circuits, and the at least two second gate driving circuits correspond one-to-one with the at least two second transistor groups. In any second transistor group, the control terminal of the first transistor and the control terminal of the second transistor are both connected to the corresponding second gate driving circuit.

12. The display panel as claimed in claim 11, characterized in that, The second gate drive circuit includes multiple cascaded second gate shift register units, and the control terminals of the first transistor and the second transistor in the second transistor group are both connected to the same second gate shift register unit.

13. The display panel as described in claim 11 or 12, characterized in that, The first transistor and the second transistor in the second transistor group are low-temperature polycrystalline silicon transistors.

14. The display panel as described in any one of claims 1-10, characterized in that, The pixel unit includes at least one of the light-emitting elements, and the pixel circuit further includes a first light-emitting control transistor and at least one second light-emitting control transistor; The first terminal of the first light-emitting control transistor is used to connect to the first power line, the second terminal of the first light-emitting control transistor is connected to the first terminal of the driving transistor, and the control terminal of the first light-emitting control transistor is used to receive the first light-emitting control signal. The at least one second light-emitting control transistor corresponds one-to-one with the at least one light-emitting element. The first terminal of the at least one second light-emitting control transistor is connected to the second terminal of the driving transistor. The second terminal of the at least one second light-emitting control transistor is used to connect to the anode of the corresponding light-emitting element. The control terminal of the at least one second light-emitting control transistor is used to receive a second light-emitting control signal.

15. The display panel as claimed in claim 14, characterized in that, The pixel unit includes one light-emitting element, the pixel circuit includes a second light-emitting control transistor, and the plurality of gate driving circuits further include a first light-emitting control circuit. The first light-emitting control circuit includes multiple cascaded first light-emitting control shift register units, and the control terminals of the first light-emitting control transistor and the second light-emitting control transistor are both connected to the same first light-emitting control shift register unit.

16. The display panel as claimed in claim 14, characterized in that, The pixel unit includes at least two light-emitting elements, the pixel circuit includes at least two second light-emitting control transistors, and the plurality of gate driving circuits further include a second light-emitting control circuit and at least two third light-emitting control circuits; The control terminal of the first light-emitting control transistor is connected to the second light-emitting control circuit; The at least two third light-emitting control circuits correspond one-to-one with the at least two second light-emitting control transistors, and the second light-emitting control transistors are connected to the corresponding third light-emitting control circuits.

17. The display panel as described in any one of claims 1-16, characterized in that, The pixel circuit further includes a second reset transistor disposed corresponding to the light-emitting element; The first terminal of the second reset transistor is used to receive the second initialization signal, the second terminal of the second reset transistor is connected to the anode of the corresponding light-emitting element, and the control terminal of the second reset transistor is used to receive the second reset control signal.

18. The display panel as claimed in claim 17, characterized in that, The plurality of gate drive circuits further include a second reset control circuit, wherein the control terminal of the second reset transistor is connected to the second reset control circuit.

19. The display panel as described in any one of claims 1-18, characterized in that, The pixel circuit further includes a third reset transistor, the first terminal of which is used to receive a third initialization signal, the second terminal of which is connected to the first or second terminal of the driving transistor, and the control terminal of which is used to receive a third reset control signal.

20. The display panel as claimed in claim 19, characterized in that, The pixel circuit includes at least one second reset transistor, and the plurality of gate driving circuits further include a second reset control circuit. The second reset control circuit includes a plurality of cascaded second reset shift registers, and the control terminals of the at least one second reset transistor and the third reset transistor are both connected to the same second reset shift register.

21. The display panel as claimed in claim 19, characterized in that, The pixel circuit includes at least two second reset transistors, and the plurality of gate drive circuits further include a second reset control circuit and a third reset control circuit. The at least two second reset transistors are connected to the second reset control circuit, and the control terminal of the third reset transistor is connected to the third reset control circuit.

22. The display panel as claimed in claim 21, characterized in that, Each of the second reset transistors is an oxide thin-film transistor, and the third reset transistor is a low-temperature polycrystalline silicon thin-film transistor.

23. The display panel as described in any one of claims 19-22, characterized in that, The second terminal of the third reset transistor is connected to the first terminal of the driving transistor, and the third reset transistor is a single-gate transistor; Alternatively, the second terminal of the third reset transistor is connected to the second terminal of the driving transistor, and the third reset transistor is a dual-gate transistor.

24. A driving method for a display panel, characterized in that, The driving method is used to drive the display panel as described in any one of claims 1-23, the method comprising: The pixel circuit in the display panel is controlled to operate, so as to drive the light-emitting element to emit light; The method of controlling the operation of the pixel circuit in the display panel includes: In the first reset phase, the first reset transistor and the threshold compensation transistor in the pixel circuit are turned on. During the data input and compensation phase, the threshold compensation transistor and data writing transistor in the pixel circuit are turned on. In the second reset phase, the third reset transistor and the second reset transistor in the pixel circuit are turned on. During the light-emitting phase, the first and second light-emitting control transistors in the pixel circuit are turned on, or the transistors in the second transistor group of the pixel circuit are turned on.

25. The method as described in claim 24, characterized in that, When the display panel operates at different refresh rates, the first reset transistor, the threshold compensation transistor, and the data write transistor are driven based on the current refresh rate of the display panel; or, When the display panel operates at different refresh rates, the third reset transistor is driven based on the maximum refresh rate of the display panel; or... When the display panel operates at different refresh rates, the first light-emitting control transistor and the second reset transistor are driven based on the maximum refresh rate of the display panel; or... When the display panel operates at different refresh rates, the transistors in the second transistor group are driven based on the maximum refresh rate of the display panel.

26. An electronic device, characterized in that, include: The system processor, the timing controller, and the display panel as described in any one of claims 1-23; The system processor is connected to the timing controller, and the timing controller is connected to the display panel.

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