Wide-bandgap semiconductor device terminal structure and manufacturing method therefor

Abstract

Disclosed in the present invention are a wide-bandgap semiconductor device terminal structure and a manufacturing method therefor, which can be used in the field of semiconductors. The terminal structure comprises: a main junction embedded in a sandwich epitaxial structure, a field limiting ring structure, and a cut-off region; the main junction is in contact with an active region, and the field limiting ring structure is between the main junction and the cut-off region; the main junction comprises a first auxiliary trench, a first P-type ion doped region penetrating through a second N-type epitaxial layer and a P-type buried layer and embedded in the first N-type epitaxial layer, and first polysilicon located at an inner corner position of the first auxiliary trench; the field limiting ring structure comprises a plurality of second auxiliary trenches, a plurality of second P-type ion doped regions penetrating through the second N-type epitaxial layer, and second polysilicon located at inner corner positions of the plurality of second auxiliary trenches; and the cut-off region comprises a third auxiliary trench, an N-type cut-off region located in the P-type buried layer, and third polysilicon located at an inner corner position of the third auxiliary trench. Thus, a high-reliability terminal structure is provided for a wide-bandgap semiconductor device having a sandwich epitaxial structure.

Description

A wide bandgap semiconductor device termination structure and its manufacturing method

[0001] This invention claims priority to Chinese Patent No. 202410917550.3, filed with the State Intellectual Property Office of the People's Republic of China on July 9, 2024, entitled "A Wide Bandgap Semiconductor Device Terminal Structure and Manufacturing Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor technology, and more specifically to a wide-bandgap semiconductor device terminal structure and its manufacturing method. Background Technology

[0003] Wide-bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN), as well as ultra-wide-bandgap semiconductor materials such as gallium oxide (Ga2O3), exhibit superior performance in physical properties such as bandgap width, critical breakdown electric field strength, and electron saturation drift velocity. In recent years, the application of these wide-bandgap or ultra-wide-bandgap semiconductor materials in the fabrication of semiconductor devices has attracted increasing attention.

[0004] Currently, wide-bandgap semiconductor power devices are widely used in power electronics due to their lower power loss and higher conversion efficiency. On the other hand, sandwich epitaxial structures have excellent effects in improving the electrical performance of devices and reducing parasitic effects, making their application in power devices an important optimization direction. In practical applications, field-limiting rings (FLRs) or junction-terminated extensions (JTEs) are commonly used as termination structures in semiconductor power devices. However, on the one hand, FLR and JTE structures suffer from sensitivity to interface charges and poor breakdown voltage, making it difficult to guarantee device reliability; on the other hand, traditional termination structures are difficult to adapt to power devices based on sandwich epitaxial structures.

[0005] Therefore, how to provide a highly reliable termination structure for wide-bandgap semiconductor devices with sandwich epitaxial structures has become a problem that needs to be solved. Summary of the Invention

[0006] The purpose of this invention is to provide a wide bandgap semiconductor device termination structure and its manufacturing method, which can provide a highly reliable termination structure for wide bandgap semiconductor devices with sandwich epitaxial structures.

[0007] To achieve the above objectives, the first aspect of the present invention provides a wide bandgap semiconductor device termination structure matched to an active region based on a sandwich epitaxial structure, the termination structure comprising: a main junction, a field-limiting ring structure, and a cutoff region embedded in the sandwich epitaxial structure;

[0008] The sandwich epitaxial structure includes a first N-type epitaxial layer, a P-type buried layer, and a second N-type epitaxial layer stacked sequentially along a first direction; wherein the first N-type epitaxial layer is located on the side closer to the substrate, and the second N-type epitaxial layer is located on the side away from the substrate.

[0009] The active region, the main junction, the field limiting ring structure, and the cutoff region are arranged sequentially along the second direction; the main junction is in contact with the active region, and the field limiting ring structure is located between the main junction and the cutoff region; the second direction is perpendicular to the first direction.

[0010] The main junction includes a first auxiliary trench, a first P-type ion-doped region penetrating the second N-type epitaxial layer and the P-type buried layer and embedded in the first N-type epitaxial layer, and a first polysilicon located at the corner of the first auxiliary trench; the first P-type ion-doped region encloses the first auxiliary trench.

[0011] The field limiting ring structure includes a plurality of second auxiliary trenches, a plurality of second P-type ion-doped regions penetrating the second N-type epitaxial layer, and a second polysilicon located at the corner position inside the plurality of second auxiliary trenches; the plurality of second P-type ion-doped regions are arranged at intervals along a second direction; the second P-type ion-doped regions enclose the second auxiliary trenches;

[0012] The cutoff region includes a third auxiliary trench, an N-type cutoff region located in the P-type buried layer corresponding to the third auxiliary trench, and a third polysilicon located at the corner of the third auxiliary trench.

[0013] In this embodiment of the invention, the second P-type ion-doped region penetrates the second N-type epitaxial layer and contacts the P-type buried layer.

[0014] In this embodiment of the invention, the second P-type ion-doped region penetrates the second N-type epitaxial layer and the P-type buried layer, and is embedded in the first N-type epitaxial layer.

[0015] In this embodiment of the invention, a field oxide layer is further provided between the first auxiliary trench and the first polysilicon, between the plurality of second auxiliary trenches and the second polysilicon, and between the third auxiliary trench and the third polysilicon.

[0016] In this embodiment of the invention, one or more of the first polysilicon, the second polysilicon, and the third polysilicon are located at the bottom of the auxiliary trench; the auxiliary trench includes a first auxiliary trench, a second auxiliary trench, and a third auxiliary trench.

[0017] In this embodiment of the invention, the cutoff region further includes a P-type masking layer;

[0018] The P-type masking layer is located in the second N-type epitaxial layer that contacts the bottom of the third auxiliary trench.

[0019] In this embodiment of the invention, the cutoff region further includes a P-type masking layer;

[0020] The P-type masking layer is located in the second N-type epitaxial layer that contacts the bottom and sidewalls of the third auxiliary trench.

[0021] In this embodiment of the invention, the side of the second N-type epitaxial layer facing away from the substrate also has a P-type well region.

[0022] In this embodiment of the invention, the first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench are filled with an interlayer medium layer.

[0023] A second aspect of the present invention provides a method for manufacturing a wide-bandgap semiconductor device termination structure, the termination structure being matched to an active region based on a sandwich epitaxial structure, the method comprising:

[0024] A substrate having a sandwich epitaxial structure is provided; the substrate includes a substrate, a first N-type epitaxial layer, a P-type buried layer and a second N-type epitaxial layer stacked sequentially along a first direction, wherein the second N-type epitaxial layer includes at least a P-type well region with an active region;

[0025] By dry etching the side of the second N-type epitaxial layer away from the substrate, a first auxiliary trench, a plurality of second auxiliary trenches, and a third auxiliary trench are formed at intervals along a second direction; the first auxiliary trench is in contact with the P-type well region; the second direction is perpendicular to the first direction;

[0026] By implanting P-type ions, a first P-type ion-doped region is formed that encloses the first auxiliary trench, and a second P-type ion-doped region is formed that encloses the second auxiliary trench; the first P-type ion-doped region penetrates the second N-type epitaxial layer and the P-type buried layer and is embedded in the first N-type epitaxial layer; the second P-type ion-doped region penetrates the second N-type epitaxial layer.

[0027] An N-type cutoff region is formed in the P-type buried layer at the position corresponding to the third auxiliary trench by N-type ion implantation;

[0028] Polycrystalline silicon is deposited inside the first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench;

[0029] The polysilicon is etched to form a first polysilicon located at the corner of the first auxiliary trench, a second polysilicon located at the corner of a plurality of second auxiliary trenches, and a third polysilicon located at the corner of the third auxiliary trench.

[0030] Through the above technical solution, on the one hand, the terminal structure uses auxiliary trenches to assist ion implantation to form a first P-type ion-doped region and a second P-type ion-doped region. This allows for the formation of a deep main junction and field-limiting ring structure with relatively low ion implantation energy, reducing manufacturing costs and minimizing electric field congestion in the active region, thus improving the device's breakdown characteristics. On the other hand, each auxiliary trench has polysilicon at its corner position that acts as a field plate terminal. The combination of the field plate terminal structure and the field-limiting ring structure improves the device's electric field distribution and enhances its overall characteristics. Furthermore, the third auxiliary trench helps form an N-type cutoff region, preventing leakage current from flowing along the P-type buried layer to the scribe line and causing device failure, thus improving device reliability. In addition, the electric field also points to the third auxiliary trench through the N-type cutoff region, making it more prone to electric field accumulation at the bottom of the third auxiliary trench. To address this issue, the third polysilicon in this embodiment of the invention can better reduce the effect of the edge electric field, working together with the main junction and field-limiting ring structure to protect the terminal structure from breakdown, thereby improving the device's breakdown characteristics.

[0031] Other features and advantages of the embodiments of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0032] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0033] Figure 1 schematically illustrates a terminal structure of a wide bandgap semiconductor device according to an embodiment of the present invention;

[0034] Figure 2 schematically illustrates a terminal structure of a wide bandgap semiconductor device according to another embodiment of the present invention;

[0035] Figure 3 schematically illustrates a terminal structure of a wide bandgap semiconductor device according to yet another embodiment of the present invention;

[0036] Figure 4 schematically illustrates a terminal structure of a wide bandgap semiconductor device according to another embodiment of the present invention;

[0037] Figure 5 schematically illustrates a terminal structure of a wide bandgap semiconductor device according to another embodiment of the present invention;

[0038] Figure 6 schematically illustrates a flowchart of a method for manufacturing a wide bandgap semiconductor device terminal structure according to an embodiment of the present invention;

[0039] Figure 7 schematically illustrates the manufacturing process of a wide bandgap semiconductor device terminal structure according to an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for illustrating and explaining the embodiments of the present invention and are not intended to limit the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0041] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0042] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0043] Referring to Figure 1, this figure is a schematic diagram of a wide bandgap semiconductor device termination structure provided by an embodiment of the present invention. The termination structure is matched to the active region based on a sandwich epitaxial structure. The termination structure includes: a main junction 100, a field limiting ring structure 200, and a cutoff region 300 embedded in the sandwich epitaxial structure.

[0044] The sandwich epitaxial structure includes a first N-type epitaxial layer 401, a P-type buried layer 403, and a second N-type epitaxial layer 402 stacked sequentially along a first direction; wherein the first N-type epitaxial layer 401 is located on the side close to the substrate 404, and the second N-type epitaxial layer 402 is located on the side away from the substrate 404.

[0045] In one example, an N-type buffer layer 405 is also provided between the first N-type epitaxial layer 401 and the substrate 404 to reduce lattice mismatch and improve the quality of the sandwich epitaxial structure.

[0046] In one example, a metal layer is also provided on the side of the substrate 404 away from the second N-type epitaxial layer 402, serving as the drain electrode 406 of the active region.

[0047] The active region 01, the main junction 100, the field limiting loop structure 200, and the cutoff region 300 are arranged sequentially along the second direction; the main junction 100 is in contact with the active region 01, and the field limiting loop structure 200 is located between the main junction 100 and the cutoff region 300. The second direction is perpendicular to the first direction.

[0048] As an example, the active region 01 may include a substrate 404, an N-type buffer layer 405, a first N-type epitaxial layer 401, a P-type buried layer 403, a second N-type epitaxial layer 402, a drain electrode 406, a trench gate electrode 407, a source electrode 408, a P-type well region 409, an N-type source region 410, a P-type source region 411, and an N-type current channel 412.

[0049] Specifically, the drain electrode 406, substrate 404, N-type buffer layer 405, first N-type epitaxial layer 401, P-type buried layer 403, and second N-type epitaxial layer 402 are stacked sequentially along the first direction; the P-type well region 409 and N-type source region 410 are sequentially formed on the side of the second N-type epitaxial layer 402 away from the substrate 404, and the P-type well region 409 surrounds the N-type source region 410; the P-type source region 411 penetrates the P-type well region 409, the N-type source region 410, the second N-type epitaxial layer 402, and the P-type buried layer 404, and is embedded in the first N-type epitaxial layer 401; the trench gate electrode 407 penetrates the P-type well region 409 and the N-type source region. 410 is embedded in the second N-type epitaxial layer 402, which may include a gate trench embedded in the second N-type epitaxial layer 402, a gate dielectric layer 4071 located on the sidewall of the gate trench, a gate polysilicon 4072 filled inside the gate trench, an interlayer dielectric layer 4073 covering the top of the gate polysilicon 4072, and a masking layer 4074 surrounding the corner of the gate trench; the N-type current channel 412 is located in the P-type buried layer 403 and corresponds to the position of the gate trench in the first direction; the source electrode 408 is a metal layer covering the surface of the trench gate electrode 407, the N-type source region 410, and the P-type source region 411.

[0050] Among them, the P-type source region 411 can be formed by source trench-assisted ion implantation to reduce high-energy ion implantation; the source trench can be a single-level trench or a multi-level trench, the inner wall of the source trench is covered with a dielectric layer 4111, and the inside of the source trench is filled with source polycrystalline silicon 4112.

[0051] It is understood that the structure of the active region 01 described above is only an example provided by the embodiments of the present invention, and does not limit the active region matched by the terminal structure provided by the present invention.

[0052] The main junction 100 includes a first auxiliary trench, a first P-type ion-doped region 101 that penetrates the second N-type epitaxial layer 402 and the P-type buried layer 403 and is embedded in the first N-type epitaxial layer 401, and a first polysilicon 102 located at the corner of the first auxiliary trench. The first P-type ion-doped region 101 surrounds the first auxiliary trench.

[0053] Specifically, P-type ion implantation can be performed with the assistance of a first auxiliary trench, thereby forming a deeper first P-type ion doped region 101 with a lower ion implantation energy. This can reduce manufacturing costs and better reduce electric field congestion in the active region, thus improving the breakdown characteristics of the device.

[0054] The field confinement ring structure 200 includes multiple second auxiliary trenches, multiple second P-type ion-doped regions 201 penetrating the second N-type epitaxial layer 402, and second polysilicon 202 located at the corner positions inside the multiple second auxiliary trenches. The multiple second P-type ion-doped regions 201 are arranged at intervals along a second direction to form a field confinement ring (FLR); the second P-type ion-doped regions 201 enclose the second auxiliary trenches.

[0055] Specifically, P-type ion implantation can be performed with the assistance of a second auxiliary trench, thereby forming a deeper second P-type ion doped region 201 with a lower ion implantation energy. This can reduce manufacturing costs and better reduce electric field congestion in the active region, thus improving the breakdown characteristics of the device.

[0056] In one example, the ion implantation depth of the second P-type ion-doped region 201 can reach the first N-type epitaxial layer 401, and the resulting second P-type ion-doped region 201 penetrates the second N-type epitaxial layer 402 and the P-type buried layer 403, and is embedded in the first N-type epitaxial layer 401; or as shown in Figure 2, the ion implantation depth of the second P-type ion-doped region 201 can reach the P-type buried layer 403, and the resulting second P-type ion-doped region 201 penetrates the second N-type epitaxial layer 402 and is in contact with the P-type buried layer 403.

[0057] The cutoff region 300 includes a third auxiliary trench, an N-type cutoff region 301 located in the P-type buried layer 403 corresponding to the third auxiliary trench, and a third polysilicon 302 located at the corner of the third auxiliary trench.

[0058] In one example, the cutoff region 300 also includes a P-type masking layer 303, which is located in the second N-type epitaxial layer 402 that contacts the bottom of the third auxiliary trench. Specifically, the P-type masking layer 303 can be formed by P-type ion implantation with the assistance of the third auxiliary trench. The P-type masking layer 303 can reduce parasitic effects, improve electric field distribution, and enhance the breakdown characteristics of the device.

[0059] In one example, before forming the polysilicon located inside the trench, a field oxide layer 413 can be grown on the exposed surface of the terminal structure region on the side of the second N-type epitaxial layer 402 facing away from the substrate 404. The formed field oxide layer 413 is located between each auxiliary trench and the polysilicon, wherein the auxiliary trenches include a first auxiliary trench, a plurality of second auxiliary trenches, and a third auxiliary trench; that is, the field oxide layer 413 is located between the first auxiliary trench and the first polysilicon 102, between the plurality of second auxiliary trenches and the second polysilicon 202, and between the third auxiliary trench and the third polysilicon 302, which can play a role in relieving stress and reducing defects in the device; in addition, the field oxide layer 413 can also control the electric field distribution inside the device, thereby optimizing the breakdown characteristics of the device.

[0060] In one example, the surface of the terminal structure facing away from the substrate 404 is covered by an interlayer dielectric layer 414, and the interior of the first auxiliary trench, a plurality of second auxiliary trenches and the third auxiliary trench is filled with the interlayer dielectric layer 414, thereby preventing leakage at the top of the terminal structure.

[0061] Therefore, this invention provides a highly reliable termination structure for wide-bandgap semiconductor devices with sandwich epitaxial structures. On one hand, the termination structure is formed by ion implantation through auxiliary trenches to create a first P-type ion-doped region 101 and a second P-type ion-doped region 201. This allows for the formation of a deep main junction 100 and field-limiting ring 200 structure using relatively small ion implantation energy, reducing manufacturing costs and improving the electric field congestion in the active region, thus enhancing the device's breakdown characteristics. On the other hand, each auxiliary trench has polysilicon at its corner position that can act as a field plate termination. The combination of the field plate termination structure and the field-limiting ring structure can improve the electric field distribution of the device and enhance its overall characteristics. Furthermore, a third auxiliary trench helps form an N-type cutoff region 301, which can prevent leakage current from leaking along the P-type buried layer 403 to the scribe line and causing device failure, thereby improving the device's reliability. In addition, the electric field will also be directed to the third auxiliary trench through the N-type cutoff region 301. The electric field is more likely to accumulate at the bottom of the third auxiliary trench. In response to this problem, the third polysilicon 302 provided in this embodiment of the invention can better reduce the effect of the edge electric field. Together with the main junction 100 and the field limiting ring structure 200, it protects the terminal structure at the end from being broken down, thereby improving the breakdown characteristics of the device.

[0062] Referring to Figure 3, this figure is a schematic diagram of another wide bandgap semiconductor device termination structure provided by an embodiment of the present invention. The termination structure is matched to the active region based on the sandwich epitaxial structure. The termination structure includes: a main junction 100, a field limiting ring structure 200, and a cutoff region 300 embedded in the sandwich epitaxial structure.

[0063] The first polysilicon 102 included in the main junction 100 may be located at the corner and bottom of the first auxiliary trench; the second polysilicon 202 included in the field limiting ring structure 200 may be located at the corner and bottom of the second auxiliary trench; and the third polysilicon 302 included in the cutoff region 300 may be located at the corner and bottom of the third auxiliary trench.

[0064] In other embodiments provided by the present invention, one or more of the first polysilicon 102, the second polysilicon 202, and the third polysilicon 302 exist both at the corners and the bottom of the auxiliary trench, while another portion exists only at the corners of the auxiliary trench. In embodiments of the present invention, the auxiliary trench includes a first auxiliary trench, a plurality of second auxiliary trenches, and a third auxiliary trench.

[0065] During the polysilicon etching process, since the morphology of the etched polysilicon is uncertain, in order to ensure that polysilicon exists at the corner of the auxiliary trench, the etching amount can be reduced so that polysilicon is also retained at the bottom of the auxiliary trench. This ensures that the polysilicon can serve as the field plate termination structure and play its role in reducing the edge electric field of the device, thereby improving the breakdown characteristics of the device.

[0066] Referring to Figure 4, this figure is a schematic diagram of another wide bandgap semiconductor device termination structure provided by an embodiment of the present invention. The termination structure is matched to the active region based on the sandwich epitaxial structure. The termination structure includes: a main junction 100, a field limiting ring structure 200, and a cutoff region 300 embedded in the sandwich epitaxial structure.

[0067] The cutoff region 300 includes a P-type masking layer 303, which can be formed by ion implantation and is located in the second N-type epitaxial layer 402 that is in contact with the bottom and sidewalls of the third auxiliary trench. Thus, the third auxiliary trench is wrapped with the P-type masking layer 303, which can better modulate the electric field of the cutoff region 300 and better protect the third auxiliary trench.

[0068] Referring to Figure 5, this figure is a schematic diagram of another wide bandgap semiconductor device termination structure provided by an embodiment of the present invention. The termination structure is matched to the active region based on the sandwich epitaxial structure. The termination structure includes: a main junction 100, a field limiting ring structure 200, and a cutoff region 300 embedded in the sandwich epitaxial structure.

[0069] In the main junction 100, the field limiting ring structure 200, and the cutoff region 300, the second N-type epitaxial layer 402 also has a P-type well region 409 on the side facing away from the substrate 404, which can better protect the surface of the terminal structure facing away from the substrate.

[0070] Referring to Figure 6, which is a flowchart of a method for manufacturing a wide bandgap semiconductor device termination structure according to an embodiment of the present invention, the termination structure obtained by this method is matched to the active region based on a sandwich epitaxial structure. The method includes:

[0071] S601: Provides a substrate with a sandwich epitaxial structure.

[0072] As shown in Figure 7(a), the substrate includes a substrate 404, a first N-type epitaxial layer 401, a P-type buried layer 403 and a second N-type epitaxial layer 402 stacked sequentially along a first direction, wherein the second N-type epitaxial layer 402 includes at least a P-type well region 409 located in the active region 01.

[0073] For example, a P-type well region 409 can be formed on the side of the second N-type epitaxial layer 402 away from the substrate 404 by P-type ion implantation. The P-type well region 409 can be formed only in the active region 01, or it can be formed in both the active region 01 and the termination structure. Then, an N-type source region 410 can be formed on the side of the active region 01 away from the substrate 404 by N-type ion implantation, with the P-type well region 409 enclosing the N-type source region 410.

[0074] In one example, an N-type buffer layer 405 may also be present between the first N-type epitaxial layer 401 and the substrate 404 to reduce lattice mismatch and improve the quality of the sandwich epitaxial structure.

[0075] S602: Dry etching is performed on the side of the second N-type epitaxial layer 402 away from the substrate 404 to form a first auxiliary trench, a plurality of second auxiliary trenches and a third auxiliary trench distributed at intervals along the second direction.

[0076] The first auxiliary trench is in contact with the P-type trap region 409; the second direction is perpendicular to the first direction, as shown in Figure 7(b).

[0077] Preferably, the first auxiliary trench, multiple second auxiliary trenches, a third auxiliary trench, a source trench, and a gate trench can be formed simultaneously in the same dry etching process, thereby reducing the complexity and cost of the terminal structure manufacturing process. The assistance of the first auxiliary trench, multiple second auxiliary trenches, and the third auxiliary trench enables the formation of deeper first P-type ion-doped regions 101, second P-type ion-doped regions 201, and third P-type ion-doped regions 301 with lower ion implantation energy, thereby better reducing electric field congestion in the active region and improving the breakdown characteristics of the device.

[0078] Furthermore, the number and depth of the first auxiliary trench, multiple second auxiliary trenches, and third auxiliary trench are consistent with those of the source trench or gate trench, thereby unifying the trench etching process conditions and further avoiding increasing process complexity on the basis of the active region manufacturing process.

[0079] S603: A first P-type ion doped region 101 enclosing the first auxiliary trench and a second P-type ion doped region 201 enclosing the second auxiliary trench are formed by P-type ion implantation.

[0080] As shown in Figure 7(c), the first P-type ion doped region 101 penetrates the second N-type epitaxial layer 402 and the P-type buried layer 403 and is embedded in the first N-type epitaxial layer 401; the second P-type ion doped region 201 penetrates the second N-type epitaxial layer 402.

[0081] In one example, the ion implantation depth of the second P-type ion-doped region 201 can reach the first N-type epitaxial layer 401, and the resulting second P-type ion-doped region 201 penetrates the second N-type epitaxial layer 402 and the P-type buried layer 403, and is embedded in the first N-type epitaxial layer 401; or as shown in Figure 2, the ion implantation depth of the second P-type ion-doped region 201 can reach the P-type buried layer 403, and the resulting second P-type ion-doped region 201 penetrates the second N-type epitaxial layer 402 and is in contact with the P-type buried layer 403.

[0082] In one example, while forming the first P-type ion-doped region 101 and the second P-type ion-doped region 201 via P-type ion implantation, a P-type source region 411 can be formed in the same process step with the assistance of a source trench. This reduces the number of process steps and further avoids increasing process complexity beyond the existing active region fabrication process.

[0083] S604: An N-type cutoff region 301 is formed in the P-type buried layer 403 at the position corresponding to the third auxiliary trench by N-type ion implantation.

[0084] Specifically, referring to Figure 7(d), an N-type cutoff region 301 can be formed in the P-type buried layer 403 at the position corresponding to the third auxiliary trench through ion implantation; at the same time, an N-type current channel 412 can be formed in the P-type buried layer 403 at the position corresponding to the gate trench in the same process step, thereby reducing process steps and further avoiding increasing process complexity on the basis of active region manufacturing process.

[0085] In one example, after forming the N-type cutoff region 301, ion implantation can be used to form a masking layer 4074 and / or a P-type masking layer 303 in the second N-type epitaxial layer 402 that contacts the bottom of the gate trench and / or the third auxiliary trench, thereby protecting the gate trench and / or the third auxiliary trench and improving the breakdown characteristics of the device. The P-type masking layer 303 may contact only the bottom of the trench, or it may contact both the bottom of the trench and the trench sidewalls.

[0086] S605: Polycrystalline silicon is deposited inside the first auxiliary trench, multiple second auxiliary trenches, and the third auxiliary trench.

[0087] In one example, polysilicon can be deposited simultaneously inside the source trench, the gate trench, the first auxiliary trench, multiple second auxiliary trenches, and the third auxiliary trench.

[0088] In one example, as shown in Figure 7(e), before polysilicon deposition, a field oxide layer 413 can be grown on the exposed surface of the second N-type epitaxial layer 402 on the side opposite to the substrate 404 where the terminal structure is located, through methods such as thermal oxidation or wet oxidation. The formed field oxide layer 413 is located between the first auxiliary trench and the first polysilicon 102, between the multiple second auxiliary trenches and the second polysilicon 202, and between the third auxiliary trench and the third polysilicon 302, which can relieve stress and reduce defects in the device; in addition, the field oxide layer 413 can also control the electric field distribution inside the device, thereby optimizing the breakdown characteristics of the device.

[0089] S606: Etch polysilicon to form a first polysilicon 102 located at the corner of the first auxiliary trench, a second polysilicon 202 located at the corner of the multiple second auxiliary trenches, and a third polysilicon 302 located at the corner of the third auxiliary trench.

[0090] Specifically, as shown in Figure 7(f), the deposited polysilicon can be etched by means of reactive ion etching, plasma etching, etc., retaining the polysilicon located at the corner of each auxiliary trench and removing the polysilicon deposited at other locations to form the first polysilicon 102, the second polysilicon 202 and the third polysilicon 302.

[0091] In one example, during the polysilicon etching process, since the morphology of the etched polysilicon is uncertain, in order to ensure that polysilicon exists at the corner of the auxiliary trench, the etching amount can be reduced so that polysilicon is also retained at the bottom of the auxiliary trench. This ensures that the polysilicon can serve as the field plate termination structure and play its role in reducing the edge electric field of the device, thereby improving the breakdown characteristics of the device.

[0092] In one example, after polysilicon etching, an interlayer dielectric layer can be deposited on the side of the device structure away from the substrate 404 to fill each auxiliary trench and cover the side of the device structure away from the substrate 404. Then, the interlayer dielectric layer is etched to form an interlayer dielectric layer 4073 covering the top of the gate polysilicon 4072 and an interlayer dielectric layer 414 filling the interior of each auxiliary trench and covering the surface of the terminal structure away from the substrate 404. Finally, the source electrode 408 and the drain electrode 406 are formed by metal deposition.

[0093] Therefore, this invention provides a method for manufacturing a high-reliability terminal structure. The resulting terminal structure is adapted to wide-bandgap semiconductor devices based on sandwich epitaxial structures. On one hand, the terminal structure is formed by ion implantation through auxiliary trenches to form a first P-type ion-doped region 101 and a second P-type ion-doped region 201. This allows for the formation of a deep main junction 100 and field-limiting ring 200 structure using relatively small ion implantation energy, reducing manufacturing costs and improving the electric field congestion in the active region, thus enhancing the device's breakdown characteristics. On the other hand, each auxiliary trench has polysilicon at its corner position that can act as a field plate terminal. The combination of the field plate terminal structure and the field-limiting ring structure can improve the electric field distribution of the device and enhance its overall characteristics. Furthermore, a third auxiliary trench helps form an N-type cutoff region 301, which can prevent leakage current from leaking along the P-type buried layer 403 to the scribe line and causing device failure, thereby improving the device's reliability. In addition, the electric field will also be directed to the third auxiliary trench through the N-type cutoff region 301. The electric field is more likely to accumulate at the bottom of the third auxiliary trench. In response to this problem, the third polysilicon 302 provided in this embodiment of the invention can better reduce the effect of the edge electric field. Together with the main junction 100 and the field limiting ring structure 200, it protects the terminal structure at the end from being broken down, thereby improving the breakdown characteristics of the device.

[0094] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments; relevant parts can be referred to the descriptions in the method embodiments. The terminal structure and method embodiments described above are merely illustrative. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0095] The above description is merely one specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A wide bandgap semiconductor device termination structure, characterized in that, Matched to an active region based on a sandwich epitaxial structure, the terminal structure includes: a main junction, a field limiting loop structure, and a cutoff region embedded in the sandwich epitaxial structure; The sandwich epitaxial structure includes a first N-type epitaxial layer, a P-type buried layer, and a second N-type epitaxial layer stacked sequentially along a first direction; wherein the first N-type epitaxial layer is located on the side closer to the substrate, and the second N-type epitaxial layer is located on the side away from the substrate. The active region, the main junction, the field limiting ring structure, and the cutoff region are arranged sequentially along the second direction; the main junction is in contact with the active region, and the field limiting ring structure is located between the main junction and the cutoff region; the second direction is perpendicular to the first direction. The main junction includes a first auxiliary trench, a first P-type ion-doped region penetrating the second N-type epitaxial layer and the P-type buried layer and embedded in the first N-type epitaxial layer, and a first polysilicon located at the corner of the first auxiliary trench; the first P-type ion-doped region encloses the first auxiliary trench. The field limiting ring structure includes a plurality of second auxiliary trenches, a plurality of second P-type ion-doped regions penetrating the second N-type epitaxial layer, and a second polysilicon located at the corner position inside the plurality of second auxiliary trenches; the plurality of second P-type ion-doped regions are arranged at intervals along a second direction; the second P-type ion-doped regions enclose the second auxiliary trenches; The cutoff region includes a third auxiliary trench, an N-type cutoff region located in the P-type buried layer corresponding to the third auxiliary trench, and a third polysilicon located at the corner of the third auxiliary trench.

2. The terminal structure according to claim 1, characterized in that, The second P-type ion-doped region penetrates the second N-type epitaxial layer and contacts the P-type buried layer.

3. The terminal structure according to claim 1, characterized in that, The second P-type ion-doped region penetrates the second N-type epitaxial layer and the P-type buried layer, and is embedded in the first N-type epitaxial layer.

4. The terminal structure according to claim 1, characterized in that, A field oxide layer is also provided between the first auxiliary trench and the first polysilicon, between the plurality of second auxiliary trenches and the second polysilicon, and between the third auxiliary trench and the third polysilicon.

5. The terminal structure according to claim 1, characterized in that, One or more of the first polysilicon, the second polysilicon, and the third polysilicon are also located at the bottom of the auxiliary trench; the auxiliary trench includes a first auxiliary trench, a second auxiliary trench, and a third auxiliary trench.

6. The terminal structure according to claim 1, characterized in that, The cutoff region also includes a P-type masking layer; The P-type masking layer is located in the second N-type epitaxial layer that contacts the bottom of the third auxiliary trench.

7. The terminal structure according to claim 1, characterized in that, The cutoff region also includes a P-type masking layer; The P-type masking layer is located in the second N-type epitaxial layer that contacts the bottom and sidewalls of the third auxiliary trench.

8. The terminal structure according to claim 1, characterized in that, The second N-type epitaxial layer also has a P-type well region on the side facing away from the substrate.

9. The terminal structure according to claim 1, characterized in that, The first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench are filled with an interlayer medium layer.

10. A method for manufacturing a wide bandgap semiconductor device termination structure, characterized in that, The terminal structure is matched to an active region based on a sandwich epitaxial structure, and the method includes: A substrate having a sandwich epitaxial structure is provided; the substrate includes a substrate, a first N-type epitaxial layer, a P-type buried layer and a second N-type epitaxial layer stacked sequentially along a first direction, wherein the second N-type epitaxial layer includes at least a P-type well region with an active region; By dry etching the side of the second N-type epitaxial layer away from the substrate, a first auxiliary trench, a plurality of second auxiliary trenches, and a third auxiliary trench are formed at intervals along a second direction; the first auxiliary trench is in contact with the P-type well region; the second direction is perpendicular to the first direction; By implanting P-type ions, a first P-type ion-doped region is formed that encloses the first auxiliary trench, and a second P-type ion-doped region is formed that encloses the second auxiliary trench; the first P-type ion-doped region penetrates the second N-type epitaxial layer and the P-type buried layer and is embedded in the first N-type epitaxial layer; the second P-type ion-doped region penetrates the second N-type epitaxial layer. An N-type cutoff region is formed in the P-type buried layer at the position corresponding to the third auxiliary trench by N-type ion implantation; Polycrystalline silicon is deposited inside the first auxiliary trench, the plurality of second auxiliary trenches, and the third auxiliary trench; The polysilicon is etched to form a first polysilicon located at the corner of the first auxiliary trench, a second polysilicon located at the corner of a plurality of second auxiliary trenches, and a third polysilicon located at the corner of the third auxiliary trench.

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