High bandwidth memory control method and apparatus

Abstract

The present application provides a high bandwidth memory (HBM) control method, which is applied to a first apparatus. The first apparatus may acquire a traffic state of an uplink interface of the first apparatus, and the first apparatus may read data from the HBM by means of a downlink interface, or may write data into the HBM by means of the downlink interface. The HBM comprises a logic circuit and multiple DRAMs, the logic circuit being used for controlling the DRAMs. Since the operating frequency of the logic circuit affects the power consumption of the logic circuit, the higher the operating frequency, the higher the power consumption of the logic circuit. To reduce the power consumption of the logic circuit, after acquiring the traffic state, the first apparatus may adjust the operating frequency of the logic circuit on the basis of the traffic state and a preset threshold. It can thus be seen that, using the present solution, the logic circuit of the HBM no longer continuously operates at a relatively high operating frequency; instead, the logic circuit can be adjusted according to the traffic state, thereby effectively reducing the power consumption of the logic circuit, and correspondingly, the power consumption of the HBM.

Description

A control method and apparatus for high-bandwidth memory

[0001] This application claims priority to Chinese Patent Application No. 202410918787.3, filed on July 9, 2024, entitled "A Control Method and Apparatus for High Bandwidth Memory", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, and in particular to a control method and apparatus for high bandwidth memory (HBM). Background Technology

[0003] HBM is a high-performance semiconductor memory based on three-dimensional (3D) stacking technology. It boasts high bandwidth and energy efficiency and is commonly used in applications requiring high memory bandwidth, such as high-performance computing and network switching and forwarding equipment. HBM stacks several individual dynamic random access memory (DRAM) dies and logic dies together. During operation, the DRAM dies need to be periodically refreshed to prevent data loss, while the logic dies control the DRAM.

[0004] Currently, HBM has high power consumption, therefore, there is an urgent need for a solution to address the above issues. Summary of the Invention

[0005] This application provides a control method and apparatus for HBM, which can reduce the power consumption of HBM.

[0006] Firstly, this application provides a control method for an HBM (Hardware Body Module). This method can be applied to a first device, which can acquire the flow status of its uplink interface. The first device can read data from the HBM via a downlink interface and write data to the HBM via the downlink interface. The HBM includes logic circuitry and multiple DRAMs, with the logic circuitry controlling the DRAMs. Since the operating frequency of the logic circuitry affects its power consumption, a higher operating frequency results in higher power consumption. To reduce the power consumption of the logic circuitry, after acquiring the flow status, the first device can adjust the operating frequency of the logic circuitry based on the flow status and a preset threshold. Therefore, using this solution, the logic circuitry of the HBM no longer operates at a consistently high frequency but can adjust according to the flow status. For example, when the flow is low, the logic circuitry can operate at a lower frequency. This effectively reduces the power consumption of the logic circuitry, and correspondingly, also reduces the power consumption of the HBM.

[0007] In one possible implementation, the operating frequency of the logic circuit is used to determine the downlink interface rate and other parameters. Adjusting the operating frequency of the logic circuit also requires adjusting the downlink interface rate and other parameters, so that the logic circuit can operate at the adjusted operating frequency.

[0008] In one possible implementation, the first device can determine the target operating frequency of the logic circuit based on the flow rate status, the preset threshold, and the current operating frequency of the logic circuit, and further adjust the operating frequency of the logic circuit to the target operating frequency. That is, when determining the target operating frequency, the first device can consider not only the flow rate status and the preset threshold, but also the current operating frequency of the logic circuit, thereby making the determined target operating frequency more reasonable.

[0009] In one possible implementation, a pre-defined correspondence can be established between a threshold, the current operating frequency of the logic circuit, and the target operating frequency of the logic circuit. Accordingly, determining the target operating frequency can be achieved by first determining a preset threshold that matches the traffic flow state, then using this preset threshold and the current operating frequency to find the corresponding relationship, thereby determining the target operating frequency of the logic circuit, and finally adjusting the operating frequency of the logic circuit to the target operating frequency.

[0010] In one possible implementation, to avoid affecting the quality of service provided to the service (e.g., causing packet loss) due to adjusting the operating frequency of the logic circuit, the first device can determine an adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency and the target operating frequency, and further adjust the operating frequency of the logic circuit to the target operating frequency. The adjustment method can be a comprehensive adjustment method or a gradual adjustment method. The comprehensive adjustment method is used to adjust the rate of the downlink interface that needs adjustment in a single adjustment, while the gradual adjustment method is used to adjust the rate of multiple downlink interfaces that need adjustment in multiple adjustments.

[0011] In one possible implementation, the first device can determine the adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency, the target operating frequency, and a pre-determined correspondence between the current operating frequency, the target operating frequency, and the adjustment method. That is, the correspondence between the current operating frequency, the target operating frequency, and the adjustment method can be pre-set, and further, the adjustment method for adjusting the operating frequency of the logic circuit can be determined based on this correspondence.

[0012] In one possible implementation, if the current operating frequency is lower than the target operating frequency, continuing to operate the logic circuit at the current frequency may lead to a decrease in the quality of service provided to the business, such as packet loss. Therefore, to ensure the quality of service provided to the business, if the current operating frequency is lower than the target operating frequency, the first device can directly adjust the operating frequency of the logic circuit to the target operating frequency.

[0013] In one possible implementation, if the current operating frequency is greater than the target operating frequency, the first device may not immediately adjust the operating frequency of the logic circuit. Instead, it may further determine whether the time difference between the current moment and the moment when the first device last reduced the operating frequency of the logic circuit is greater than or equal to a preset time threshold. If the time difference is greater than or equal to the preset time threshold, the operating frequency of the logic circuit is adjusted to the target operating frequency. Conversely, if the time difference is less than the preset time threshold, the operating frequency of the logic circuit is maintained at the current operating frequency. Alternatively, the first device may adjust the operating frequency of the logic circuit to the target operating frequency only if multiple consecutive determinations indicate that a reduction in the operating frequency of the logic circuit is necessary. This approach avoids frequent adjustments to the operating frequency of the logic circuit, thereby ensuring the performance of HBM.

[0014] In one possible implementation, to further reduce the power consumption of the HBM, the first device can further adjust the refresh mode of the DRAM according to the adjusted operating frequency of the logic circuit (i.e., the target operating frequency). This ensures that the DRAM's refresh mode matches the target operating frequency, rather than the DRAM always being in the high-power normal mode, thereby reducing the DRAM's power consumption and correspondingly reducing the HBM's power consumption.

[0015] In one possible implementation, a correspondence between the operating frequency of the logic circuit and the refresh mode of the DRAM can be preset. In this way, the correspondence can be found using the target operating frequency to obtain the target refresh mode corresponding to the target operating frequency, and the refresh mode of the DRAM can be further adjusted to the target refresh mode.

[0016] In one possible implementation, when determining the refresh mode of the DRAM, in addition to considering the aforementioned target operating frequency, the aforementioned flow conditions can also be considered, thereby making the determined refresh mode match the aforementioned flow conditions, and consequently making the determined DRAM refresh mode more reasonable. In other words, the first device can adjust the refresh mode of the dynamic random access memory according to the target operating frequency and the flow conditions.

[0017] In one possible implementation, the correspondence between the operating frequency of the logic circuit, the flow status, and the refresh mode of the DRAM can be preset. In this way, the target refresh mode can be obtained by using the target operating frequency and the flow status of the uplink interface to find the correspondence, and then the refresh mode of the DRAM can be further adjusted to the target refresh mode.

[0018] In one possible implementation, the uplink interface traffic status can characterize the amount of traffic passing through the uplink interface. Considering that in practical applications, the number of interfaces (i.e., uplink interfaces) actually used for data transmission between the first and second devices can be set based on the traffic volume between them, as an example, the aforementioned traffic status can be characterized by the number of interfaces actually used for data transmission among the interfaces used by the first device for data interaction with the second device.

[0019] In one possible implementation, the uplink interface traffic status can characterize the amount of traffic passing through the uplink interface. Considering that in practical applications, the interface rate at which the first device interacts with the second device can be set based on the traffic volume between the first and second devices, therefore, as an example, the aforementioned traffic status can be characterized by the interface rate at which the first device interacts with the second device.

[0020] In one possible implementation, the uplink interface traffic status can characterize the amount of traffic passing through the uplink interface. Considering that whether the data is sent from the first device to the second device via the uplink interface or received from the second device via the uplink interface, the data will pass through the cache in the first device. Therefore, as an example, the aforementioned traffic status can be characterized by the usage of the cache used for caching data in the first device.

[0021] In one possible implementation, if the first device receives data from the uplink interface and needs to write the data to HBM, the first device can first determine the multiple storage units associated with the data to be written, and further determine whether the refresh mode of the multiple storage units is all in normal mode. If the refresh mode of the multiple storage units is all in normal mode, the first device can directly write the device to be written into the multiple storage units. If some or all of the multiple storage units have a refresh mode that is not in normal mode, the first device can control the logic circuit to modify the refresh mode of the aforementioned partial storage units to normal mode, and further write the device to be written into the multiple storage units. After the data to be written is written into the multiple storage units, the refresh mode of the multiple storage units can be further restored.

[0022] Secondly, this application provides a control device for a high-bandwidth memory, applied to a first device. The device includes: an acquisition unit, configured to acquire the traffic status of the uplink interface of the first device, wherein the first device is configured to read data from and / or write data to the high-bandwidth memory via a downlink interface, the high-bandwidth memory including logic circuitry and multiple dynamic random access memories, the logic circuitry being configured to control the multiple dynamic random access memories; and a processing unit, configured to adjust the operating frequency of the logic circuitry according to the traffic status and a preset threshold.

[0023] In one possible implementation, the operating frequency is used to determine the rate of the downlink interface.

[0024] In one possible implementation, the processing unit is configured to: determine the target operating frequency of the logic circuit based on the traffic status, the preset threshold, and the current operating frequency of the logic circuit; and adjust the operating frequency of the logic circuit to the target operating frequency.

[0025] In one possible implementation, the processing unit is configured to: determine the preset threshold that matches the traffic state, and determine the target operating frequency based on the preset threshold, the current operating frequency of the logic circuit, and a pre-determined correspondence between the preset threshold, the current operating frequency, and the target operating frequency; and adjust the operating frequency of the logic circuit to the target operating frequency.

[0026] In one possible implementation, adjusting the operating frequency of the logic circuit to the target operating frequency includes: determining an adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency and the target operating frequency; the adjustment method includes: a comprehensive adjustment method or a gradual adjustment method; the comprehensive adjustment method is used to adjust the rate of the downlink interface that needs to be adjusted in a single adjustment, and the gradual adjustment method is used to adjust the rate of multiple downlink interfaces that need to be adjusted in multiple adjustments; and adjusting the operating frequency of the logic circuit to the target operating frequency according to the adjustment method.

[0027] In one possible implementation, determining the adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency and the target operating frequency includes: determining the adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency, the target operating frequency, and a pre-determined correspondence between the current operating frequency, the target operating frequency, and the adjustment method.

[0028] In one possible implementation, adjusting the operating frequency of the logic circuit to the target operating frequency includes: if the current operating frequency is less than the target operating frequency, then directly adjusting the operating frequency of the logic circuit to the target operating frequency.

[0029] In one possible implementation, adjusting the operating frequency of the logic circuit to the target operating frequency includes: if the current operating frequency is greater than the target operating frequency, then if the time difference between the current moment and the moment when the first device last reduced the operating frequency of the logic circuit is greater than or equal to a preset time threshold, adjusting the operating frequency of the logic circuit to the target operating frequency.

[0030] In one possible implementation, the processing unit is further configured to: adjust the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit.

[0031] In one possible implementation, adjusting the refresh mode of the dynamic random access memory (DRAM) according to the adjusted operating frequency of the logic circuit includes: determining the target refresh mode of the DRAM based on the adjusted operating frequency of the logic circuit and a predetermined correspondence between the operating frequency and the refresh mode, and adjusting the refresh mode of the DRAM to the target refresh mode.

[0032] In one possible implementation, adjusting the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit includes: adjusting the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit and the flow status.

[0033] In one possible implementation, adjusting the refresh mode of the dynamic random access memory (DRAM) based on the adjusted operating frequency of the logic circuit and the flow status includes: determining the target refresh mode of the DRAM based on the adjusted operating frequency of the logic circuit, the flow status, and a predetermined correspondence between the operating frequency, flow status, and refresh mode, and adjusting the refresh mode of the DRAM to the target refresh mode.

[0034] In one possible implementation, the traffic status includes one or more of the following: the number of interfaces actually used for data transmission among the interfaces used by the first device for data interaction with the second device; the interface rate of the first device for data interaction with the second device; and the usage of the cache used for caching data in the first device.

[0035] In one possible implementation, the processing unit is further configured to: determine a plurality of storage units associated with the data to be written, and modify the refresh mode of the plurality of storage units to normal mode, wherein each of the plurality of storage units is used to store the data to be written; and after the data to be written is written into the plurality of storage units, restore the refresh mode of the plurality of storage units.

[0036] Thirdly, embodiments of this application provide an apparatus, including: a processor and a memory; the memory is used to store instructions or computer programs; the processor is used to execute the instructions or computer programs to perform the methods described in the first aspect above and any one of the first aspects above.

[0037] Fourthly, embodiments of this application provide a computer-readable storage medium, including instructions or a computer program, which, when run on a computer, cause the computer to perform the methods described in the first aspect above and any one of the first aspects above.

[0038] Fifthly, embodiments of this application provide a computer program product comprising instructions or computer programs, which, when run on a computer, causes the computer to perform the methods described in the first aspect and any one of the first aspects. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1a shows a schematic diagram of a system architecture including HBM;

[0041] Figure 1b shows a schematic diagram of the initialization process for a system including HBM in the conventional technology;

[0042] Figure 1c is a schematic diagram of a system architecture including HBM provided in an embodiment of this application;

[0043] Figure 2 is a flowchart illustrating a control method for HBM provided in an embodiment of this application;

[0044] Figure 3 is a schematic diagram of the refresh mode change process of a storage unit provided in an embodiment of this application;

[0045] Figure 4 is a flowchart illustrating another control method for DRAM provided in an embodiment of this application;

[0046] Figure 5 is a schematic diagram of a control device for a high-bandwidth memory provided in an embodiment of this application;

[0047] Figure 6 is a schematic diagram of the structure of a device provided in an embodiment of this application. Detailed Implementation

[0048] This application provides a control method and apparatus for HBM, which can reduce the power consumption of HBM.

[0049] To facilitate understanding, the application scenarios of this application will be introduced first.

[0050] Referring to Figure 1a, this figure illustrates a system architecture including HBM. As shown in Figure 1a, the system includes: a system-on-chip (SoC) and HBM. Wherein:

[0051] The SoC includes a data processing module and a high bandwidth memory controller (HBMC). The data processing module connects to other devices via uplink interfaces. In one example, the data processing module connects to another SoC via an uplink interface. In yet another example, the data processing module connects to optical modules via uplink interfaces; for example, each uplink interface connects to one optical module. For ease of understanding, Figure 1a shows four uplink interfaces. In practical applications, the number of uplink interfaces is not limited to the four shown in Figure 1a.

[0052] The SoC's downlink interface is the interface used by the HBMC to connect to the HBM. For ease of understanding, Figure 1a shows four downlink interfaces; however, in practical applications, the number of downlink interfaces is not limited to the four shown in Figure 1a. In one example, the downlink interface can be a serial input / output (SIO). Additionally, there is a control interface between the HBMC and the HBM, which will not be described in detail here. The HBM includes logic circuitry and multiple DRAMs; Figure 1a shows four DRAMs. These multiple DRAMs are used to store data. The logic circuitry is used to control these multiple DRAMs, for example, controlling the refresh mode of the multiple DRAMs, controlling the writing of data from the DRAMs, and controlling the reading of data from the DRAMs. The data mentioned here includes, but is not limited to, various table entries such as forwarding table entries.

[0053] For the system architecture shown in Figure 1a, the data processing module can read data from the HBM and send it to other devices or perform corresponding processing based on the read data. The data processing module can also write data from other devices into the HBM. For a single piece of data, it is written to at least two address spaces as backups. For example, for entry 1, it is stored in address 1 of DRAM1, address 2 of DRAM2, and address 3 of DRAM3. Using this method, during the data reading phase, different parts of the data can be read in parallel from the aforementioned multiple address spaces, thereby concatenating the complete data and improving data reading efficiency. For example, for entry 1, which includes three parts: part 1, part 2, and part 3, when reading entry 1, a parallel reading method can be used: part 1 is read from address 1, part 2 from address 2, and part 3 from address 3. The read parts 1, 2, and 3 are then concatenated to obtain the complete entry 1. This method effectively improves the reading efficiency of entry 1 compared to reading the complete entry 1 from a single address.

[0054] For DRAM, accessing a row within a bank typically precludes simultaneous access to another row within the same bank. Therefore, any two of the aforementioned at least two address spaces need to be distributed across different banks to allow for parallel access during the data read phase. Of course, the distribution of these at least two address spaces can be determined by the specific design of the DRAM chip, and is not limited to different banks. For example, if the DRAM chip is designed so that only one row can be accessed at a time within the same bank group, then any two of the aforementioned at least two address spaces must be distributed across different bank groups.

[0055] In some scenarios, reading data from HBM can also be referred to as "table lookup"; writing data into HBM can also be referred to as "table creation".

[0056] The data processing module includes a buffer for caching data. For data sent by the SoC to other devices via the uplink interface, the SoC first reads the data from the HBM, then buffers it in the buffer, and finally reads the data from the buffer and sends it to the other devices via the uplink interface. Similarly, for data received by the SoC from other devices via the uplink interface, the SoC also first buffers the data in the buffer, then reads the data from the buffer and writes it to the HBM via the downlink interface.

[0057] Currently, the logic circuits in HBM operate at a fixed frequency. This fixed frequency is determined during the aforementioned system initialization phase, and generally, it is the highest frequency supported by the logic circuits. The system initialization process can be understood by referring to Figure 1b and the description of Figure 1b below.

[0058] In addition, the DRAM in HBM has three refresh modes: normal mode, auto-refresh mode, and power-down mode. HBMC can control the banks in the DRAM to be in one of these three modes.

[0059] For a bank in DRAM, table lookups or deletions are only possible when it is in normal mode; therefore, normal mode is also referred to as the active state. Conversely, when a bank is in auto-refresh or power-down mode, table lookups and deletions are not possible. Correspondingly, the power consumption is highest when the bank's refresh mode is normal, lowest when it's power-down, and between the power consumption of normal mode and power-down mode when it's auto-refresh. Auto-refresh can also be simply referred to as refresh; in this application, the two terms can be used interchangeably.

[0060] Referring to Figure 1b, Figure 1b shows a schematic diagram of the initialization process for a system including HBM in the conventional technology.

[0061] As shown in Figure 1b, the initialization process for a system including HBM includes steps S1-S5.

[0062] S1: Initialize the SoC.

[0063] S2: Initialize the interface between the SoC and HBM.

[0064] The interface between the SoC and HBM mentioned here is the downlink interface mentioned earlier.

[0065] The specific implementations of S1 and S2 will not be repeated here.

[0066] S3: Set the operating frequency of the logic circuit.

[0067] The operating frequency set in S3 is the highest frequency that the logic circuit supports.

[0068] S4: Configure the parameters for the operating frequency set for the logic circuit to obtain the corresponding configuration parameters.

[0069] The configuration parameters mentioned in S4 include the downlink interface speed and other parameters of the logic circuit, which will not be described in detail here.

[0070] S5: Enable DRAM and set the refresh mode of each bank in DRAM to normal mode.

[0071] After executing S1-S5, you can then perform table lookup or table drop-off operations.

[0072] As described above, in traditional technology, because the logic circuits operate at their highest possible frequency, the refresh mode of each bank in DRAM is normal mode, resulting in higher power consumption for HBM.

[0073] To reduce the power consumption of HBM, this application provides a control method and apparatus for HBM, which can reduce the power consumption of HBM. The solutions provided by the embodiments of this application will be described below with reference to the accompanying drawings.

[0074] Referring to Figure 2, this figure is a flowchart illustrating a control method for HBM provided in an embodiment of this application. The method shown in Figure 2 can be applied to a first device, which may be, for example, the SoC shown in Figure 1a. The method shown in Figure 2 includes the following steps S101-S102.

[0075] In a specific example, the specific structure of the SoC shown in Figure 1a can be understood by referring to Figure 1c. As shown in Figure 1c, the SoC further includes a monitoring module, a computing module, and a frequency modulation module. The monitoring module, for example, can be used to execute S101 to obtain the uplink interface traffic status. The computing module and the frequency modulation module jointly execute S102, whereby the computing module determines, based on the traffic status obtained by the monitoring module, whether the operating frequency of the logic circuit needs to be adjusted. If the operating frequency of the logic circuit needs to be adjusted, the frequency modulation module adjusts the operating frequency of the logic circuit. The specific implementation methods of S101-S102 will be described below.

[0076] S101: The first device obtains the traffic status of the uplink interface of the first device. The first device is used to obtain data from the HBM and / or write data to the HBM through the downlink interface. The HBM includes logic circuitry and multiple DRAMs. The logic circuitry is used to control the DRAMs.

[0077] The uplink interface of the first device serves as the interface for data interaction between the first device and the second device. As described above in the system shown in Figure 1a, the second device can be a SoC or an optical module. In one example, the first device can receive data from the uplink interface and write the data into the HBM. In another example, the first device can read data from the HBM and send it to the second device via the uplink interface.

[0078] The uplink interface traffic status can characterize the amount of traffic passing through the uplink interface, or in other words, the amount of traffic exchanged between the first device and the second device. This application does not specifically limit the uplink interface traffic status; the uplink interface traffic status can be represented by any parameter that can characterize the amount of traffic passing through the uplink interface.

[0079] In one example, considering practical applications, the number of interfaces (i.e., uplink interfaces) actually used for data transmission between the first and second devices can be set according to the traffic volume between them. For instance, if the first device has four interfaces for data interaction with the second device, when the traffic volume between them is high, all four interfaces can be set to active status. In this scenario, the number of uplink interfaces used for data transmission between the first and second devices is four. When the traffic volume between them is low, two of the four interfaces can be set to active status, and the other two can be set to inactive status. In this scenario, the number of uplink interfaces used for data transmission between the first and second devices is two. Therefore, as an example, the aforementioned traffic volume status can be characterized by the number of interfaces actually used for data transmission among the interfaces used by the first device for data interaction with the second device.

[0080] In another example, considering practical applications, the interface rate at which the first device interacts with the second device can be set based on the traffic volume between the first and second devices. For instance, when the traffic volume between the first and second devices is high, the interface rate can be set higher, and when the traffic volume is low, the interface rate can be set lower. Therefore, as an example, the aforementioned traffic state can be characterized by the interface rate at which the first device interacts with the second device.

[0081] In another example, considering that whether the data sent by the first device to the second device via the uplink interface or received by the first device from the second device via the uplink interface, the data will pass through the cache in the first device. Specifically, for data sent by the first device to the second device via the uplink interface, the first device first reads the data from HBM, further caches the data in the cache, and then reads the data from the cache and sends it to the second device via the uplink interface. For data received by the first device from the second device via the uplink interface, the first device also first caches the data in the cache, and then reads the data from the cache and writes it to HBM via the downlink interface. Therefore, as an example, the aforementioned traffic status can be characterized by the usage of the cache used for caching data in the first device.

[0082] The cache usage mentioned here can refer to either the amount of cache used or the amount of cache remaining. The amount of cache used can be either the cache capacity already used or the cache utilization rate. The cache utilization rate refers to the ratio of the cache capacity already used to the total cache capacity. The amount of cache remaining mentioned here can be either the cache capacity not yet used or the cache free rate. The cache free rate refers to the ratio of the cache capacity not yet used to the total cache capacity.

[0083] S102: The first device adjusts the operating frequency of the logic circuit according to the flow rate status and the preset threshold.

[0084] In this embodiment, considering that if the logic circuit operates at a consistently high frequency, its performance is excessive when the flow rate between the first and second devices is low, while consistently operating at a high frequency results in high power consumption, this application adjusts the logic circuit's operating frequency according to the aforementioned flow rate state. This ensures the performance provided by the logic circuit matches the flow rate state, thereby preventing the logic circuit from operating at a consistently high frequency and reducing its power consumption, thus effectively reducing the power consumption of the HBM. In a specific example, the logic circuit's operating frequency can be adjusted based on the flow rate state and a preset threshold.

[0085] In this embodiment, the operating frequency of the logic circuit is used to determine the downlink interface speed and other parameters. Adjusting the operating frequency of the logic circuit also requires adjusting the downlink interface speed and other parameters. In a specific example, the first device can first adjust the downlink interface speed, and then the first device sends the operating frequency to be adjusted to the logic circuit via a network clock, so that the logic circuit can adjust its own operating frequency.

[0086] In one example, the correspondence between thresholds and the operating frequencies of logic circuits can be preset. For example, multiple thresholds can be set, and each threshold corresponds to an operating frequency of the logic circuit. Accordingly, in a specific implementation, S102 can determine a preset threshold that matches the flow state from among the multiple thresholds, further determine the target operating frequency of the logic circuit from the operating frequency corresponding to the preset threshold, and further adjust the operating frequency of the logic circuit to the target operating frequency.

[0087] The thresholds mentioned in the embodiments of this application (including preset thresholds) may correspond to a specific value or a range of values. The embodiments of this application do not impose specific limitations.

[0088] In another example, when determining the target operating frequency, the current operating frequency of the logic circuit can also be considered. That is, the target operating frequency can be determined based on the current operating frequency, the flow status, and the preset threshold, and the operating frequency of the logic circuit can be further adjusted to the target operating frequency.

[0089] This application does not specifically limit the implementation of "determining the target operating frequency based on the current operating frequency, the traffic state, and the preset threshold." In a specific example, the correspondence between the threshold, the current operating frequency of the logic circuit, and the target operating frequency of the logic circuit can be preset. Accordingly, in a specific implementation of S102, a preset threshold matching the traffic state can be determined first. Further, using the preset threshold and the current operating frequency, the correspondence can be found to determine the target operating frequency of the logic circuit, and the operating frequency of the logic circuit can be adjusted to the target operating frequency.

[0090] Regarding this correspondence, we will now use the following example to illustrate the traffic status, which includes the number of interfaces used by the first device for data interaction with the second device, the number of interfaces actually used for data transmission, and the utilization rate of the cache used for caching data in the first device. For ease of description, the "number of interfaces used by the first device for data interaction with the second device, the number of interfaces actually used for data transmission" will be simply referred to as "interface number," and the "utilization rate of the cache used for caching data in the first device" will be simply referred to as "cache utilization rate." In this scenario, the preset threshold may include a threshold corresponding to the number of interfaces and a threshold corresponding to the cache utilization rate. In this case, the aforementioned correspondence may include the correspondence shown in Table 1 and Table 2. The correspondence shown in Table 1 corresponds to the need to increase the operating frequency of the logic circuit, and the correspondence shown in Table 2 corresponds to the need to decrease the operating frequency of the logic circuit.

[0091] Table 1

[0092] Table 2

[0093] Regarding Tables 1 and 2, it should be noted that both tables illustrate the use of logic circuits supporting high, medium, low, and minimum operating frequencies as examples. The specific values ​​for these four operating frequencies are not specifically limited in this embodiment. During the initialization phase of a system including SoC and HBM, parameters can be adjusted for each of these four operating frequencies to obtain configuration parameters corresponding to each frequency, and these configuration parameters can be further saved. Accordingly, after switching the operating frequency of the logic circuit, the system can operate based on the pre-saved configuration parameters corresponding to the switched operating frequency.

[0094] Regarding the thresholds related to the number of interfaces, these include the idle line, the switching line, and the full line. It should be noted that the idle line, switching line, and full line can all be positive integers. The idle line is less than the switching line, the switching line is less than the full line, and the full line is less than or equal to the total number of interfaces. The total number of interfaces mentioned here can be understood as the total number of uplink interfaces included in the first device. For example, if the total number of interfaces is 4, then the idle line could be 1, the switching line could be 2, and the full line could be 4.

[0095] Regarding thresholds related to cache utilization, these can be categorized into three levels: high, medium, and low. Each level can further include upward and / or downward adjustment thresholds. In other words, the thresholds related to cache utilization can include six levels: high upward adjustment threshold, high downward adjustment threshold, medium upward adjustment threshold, medium downward adjustment threshold, low upward adjustment threshold, and low downward adjustment threshold. The order is: High upward adjustment threshold > High downward adjustment threshold > Medium upward adjustment threshold > Medium downward adjustment threshold > Low upward adjustment threshold > Low downward adjustment threshold. For example, the high upward adjustment threshold could be 90%, the high downward adjustment threshold could be 80%, the medium upward adjustment threshold could be 70%, the medium downward adjustment threshold could be 60%, the low upward adjustment threshold could be 40%, and the low downward adjustment threshold could be 20%.

[0096] According to Table 1, assuming that the number of traffic status indicator interfaces is between [0, idle line), the cache utilization rate is between [low adjustment line, medium adjustment line), and the current working frequency is "lowest", then the target working frequency can be determined to be "low".

[0097] Regarding the correspondence 13 shown in Table 1, it should be noted that once the number of interfaces is in the range of [full line, total number of interfaces], the target working frequency can be directly determined to be high, regardless of the cache utilization rate and the current working frequency.

[0098] The correspondences shown in Tables 1 and 2 will not be explained in detail here.

[0099] It should be noted that Tables 1 and 2 are only for ease of understanding of this solution, using traffic status including the number of interfaces and cache utilization as examples, and do not constitute a limitation on the embodiments of this application. For example, in some examples, traffic status may also include either the number of interfaces or cache utilization. In addition, the threshold corresponding to the number of interfaces may not be limited to the idle line, switching line, and full line shown in Tables 1 and 2. The threshold corresponding to cache utilization may also not be limited to the six thresholds mentioned above: high upward adjustment line, high downward adjustment line, medium upward adjustment line, medium downward adjustment line, low upward adjustment line, and low downward adjustment line.

[0100] In one example, if a pre-set correspondence cannot be found between the aforementioned preset threshold and the current operating frequency, then there is no need to adjust the operating frequency of the logic circuit; simply maintain the current operating frequency. For instance, assuming the traffic status indicator interface count is between [0, idle line), the cache utilization rate is between [low reduction line, medium reduction line), and the current operating frequency is "low," and no correspondence can be found in Tables 1 and 2 between the interface count between [0, idle line), the cache utilization rate between [low reduction line, medium reduction line), and the current operating frequency being "low," then the current operating frequency of the logic circuit can be maintained without adjustment.

[0101] In one example, if the current operating frequency is lower than the target operating frequency, continuing to operate the logic circuit at the current frequency may lead to a decrease in the quality of service provided to the business, such as packet loss. Therefore, to ensure the quality of service provided to the business, if the current operating frequency is lower than the target operating frequency, the first device can directly adjust the operating frequency of the logic circuit to the target operating frequency.

[0102] In another example, considering that in practical applications, the uplink traffic of the first device may fluctuate, for example, fluctuating within a certain range. In this scenario, if the operating frequency of the logic circuit is immediately adjusted to the target operating frequency after it is determined, it may lead to frequent adjustments of the logic circuit's operating frequency by the first device. Since the logic circuit cannot control the DRAM to perform table lookup and write operations during the frequency adjustment period, frequent adjustments of the logic circuit's operating frequency will affect the performance of HBM. Therefore, in this application, if the current operating frequency is greater than the target operating frequency, the first device may not immediately adjust the operating frequency of the logic circuit. Instead, it may further determine whether the time difference between the current moment and the moment when the first device last reduced the operating frequency of the logic circuit is greater than or equal to a preset time threshold. If the time difference is greater than or equal to the preset time threshold, the operating frequency of the logic circuit is adjusted to the target operating frequency. Conversely, if the time difference is less than the preset time threshold, the operating frequency of the logic circuit is maintained at the current operating frequency. Alternatively, if the first device determines multiple times that a reduction in the operating frequency of the logic circuit is necessary, it can adjust the operating frequency of the logic circuit to the target operating frequency. This approach avoids frequent adjustments to the logic circuit's operating frequency, thereby ensuring the performance of the HBM.

[0103] The embodiments of this application do not specifically limit the preset time threshold. The preset time threshold can be determined according to the actual situation, and will not be described in detail here.

[0104] In this embodiment, adjusting the operating frequency of the logic circuit from the current operating frequency to the target operating frequency can be implemented in two ways: a holistic adjustment and a gradual adjustment. The holistic adjustment refers to adjusting the rate of one or more downlink interfaces in a single step. That is, the rate of one or more downlink interfaces is adjusted simultaneously, and after the single adjustment, the logic circuit's operating mode is adjusted to the target operating frequency. The gradual adjustment refers to adjusting the rate of multiple downlink interfaces in multiple steps. That is, the rate of a portion of the downlink interfaces is adjusted each time, and after multiple adjustments, the logic circuit's operating mode is adjusted to the target operating frequency. Before all adjustments are completed, the frequency of the logic circuit lies between the current operating frequency and the target operating frequency after each adjustment. The logic circuit's frequency being between the current operating frequency and the target operating frequency can also be understood as the logic circuit being in an "intermediate state."

[0105] In one example, the adjustment method for adjusting the operating frequency of the logic circuit can be determined based on the current operating frequency and the target operating frequency. The operating frequency of the logic circuit can then be further adjusted based on this adjustment method.

[0106] In some embodiments, the number of downlink interfaces requiring rate adjustment can be determined based on the current operating frequency and the target operating frequency, and the time required to adjust the downlink interfaces requiring rate adjustment can be further determined. Further, based on this time, the adjustment method for adjusting the operating frequency of the logic circuit can be determined. As an example, when the time is short, the adjustment method for adjusting the operating frequency of the logic circuit is determined to be a general adjustment method; when the time is long, the adjustment method for adjusting the operating frequency of the logic circuit is determined to be a gradual adjustment method. As another example, the adjustment mode can be determined by combining the time and the aforementioned traffic status (e.g., the aforementioned cache utilization rate and the aforementioned number of interfaces). As a specific example, the time to clear the cache or the time to fill the cache can be determined based on the aforementioned traffic status. If the time to clear the cache or the time to fill the cache is greater than or equal to the aforementioned time, the adjustment method for adjusting the operating frequency of the logic circuit is determined to be a general adjustment method. Correspondingly, if the time to clear the cache or the time to fill the cache is less than the aforementioned time, the adjustment method for adjusting the operating frequency of the logic circuit is determined to be a gradual adjustment method.

[0107] In some other embodiments, a correspondence between the current operating frequency, the target operating frequency, and the adjustment method can be preset. Further, based on this correspondence, the adjustment method for adjusting the operating frequency of the logic circuit is determined. For example, refer to Table 3 below for understanding; a row in Table 3 represents a pair of "current operating frequency, target operating frequency, and adjustment method".

[0108] Table 3

[0109] If the current operating frequency is "high" and the target operating frequency is "medium", then according to the correspondence shown in Table 3, the adjustment method for adjusting the operating frequency of the logic circuit can be determined to be the overall adjustment method.

[0110] It should be noted that Table 3 only shows several possible correspondences for ease of understanding and does not constitute a limitation on the embodiments of this application.

[0111] As described above, traffic status is also an important factor in determining the adjustment of the operating frequency of the logic circuit, because traffic status can be used to determine when the cache is emptied or filled. Therefore, in this embodiment, the adjustment method for adjusting the operating frequency of the logic circuit can also be determined as an overall adjustment method by combining the pre-set correspondence between traffic status, current operating frequency, target operating frequency, and adjustment method. Taking traffic status including the number of interfaces and cache utilization as an example, the correspondence will be explained in conjunction with Tables 4 and 5.

[0112] The correspondences shown in Table 4 correspond to the need to increase the operating frequency of the logic circuit, while the correspondences shown in Table 5 correspond to the need to decrease the operating frequency of the logic circuit. Table 4 corresponds to Table 1 above, but with the addition of a last column, "Adjustment Method". Table 5 corresponds to Table 2 above, with the addition of a last column, "Adjustment Method".

[0113] Table 4

[0114] Table 5

[0115] Regarding Tables 4 and 5, it should be noted that the first device can also pre-store the adjustment steps for each step-by-step adjustment method. For example, for step-by-step adjustment method 1, the operating frequency is first adjusted from "high" to intermediate state 1, and then further adjusted from intermediate state 2 to the intermediate frequency "medium".

[0116] Correspondingly, for the intermediate state corresponding to the gradual adjustment method, the corresponding configuration parameters (such as the rate of each downlink interface and other configurations) are also adjusted for the intermediate state during the initialization phase. Therefore, when the logic circuit is in the intermediate state, the logic circuit can also control the DRAM, so that the logic circuit can work briefly for a certain period of time when it is in the intermediate state, in order to avoid cache abnormalities of the first device (such as cache overflow).

[0117] In one example, to further reduce HBM power consumption, the first device can further adjust the DRAM refresh mode according to the adjusted operating frequency of the logic circuit (i.e., the target operating frequency). As a specific example, the first device can adjust the DRAM refresh mode through the logic circuit. For instance, the first device can send a refresh mode adjustment command to the logic circuit, so that the logic circuit can adjust the DRAM refresh mode based on the command. This ensures that the DRAM refresh mode matches the target operating frequency, instead of the DRAM always being in the high-power normal mode, thereby reducing DRAM power consumption and correspondingly reducing HBM power consumption. In this application, adjusting the DRAM refresh mode can be understood as adjusting the refresh mode of the DRAM banks.

[0118] As an example, a specific algorithm can be used to calculate the target refresh mode corresponding to the target operating frequency, and the refresh mode of the DRAM can be further adjusted to the target refresh mode. For example, the target refresh mode corresponding to the target operating frequency can be obtained using methods such as large models.

[0119] As another example, the correspondence between the operating frequency of the logic circuit and the refresh mode of the DRAM can be preset. In this way, the correspondence can be found using the target operating frequency to obtain the target refresh mode corresponding to the target operating frequency, and the refresh mode of the DRAM can be further adjusted to the target refresh mode.

[0120] The correspondence between the operating frequency of the logic circuit and the refresh mode of the DRAM can be understood by referring to Table 6 below. As shown in Table 6, several possible correspondences are illustrated.

[0121] Table 6

[0122] Regarding Table 6, it should be noted that addresses A, B, C, and D can be understood as addresses corresponding to different banks of the DRAM.

[0123] Assuming the target operating frequency is high, based on the correspondence shown in Table 6, it can be determined that the refresh mode of address A in DRAM is refresh, and the refresh modes of addresses B, C and D are all normal.

[0124] In some embodiments, when determining the refresh mode of DRAM, in addition to considering the aforementioned target operating frequency, the aforementioned flow state can also be considered, so that the determined refresh mode matches the aforementioned flow state, and accordingly, the determined refresh mode of DRAM is more reasonable.

[0125] As an example, a specific algorithm can be used to determine the target refresh mode based on the traffic status and the target operating frequency, and then the refresh mode of the DRAM can be adjusted to the target refresh mode. For example, the traffic status and the target operating frequency can be processed using methods such as large models to obtain the target refresh mode.

[0126] As another example, the correspondence between the operating frequency of the logic circuit, the flow status, and the refresh mode of the DRAM can be preset. In this way, the target operating frequency and the flow status of the uplink interface can be used to find the correspondence, obtain the target refresh mode, and further adjust the refresh mode of the DRAM to the target refresh mode.

[0127] Regarding the correspondence between the operating frequency of the logic circuit, the flow status, and the refresh mode of the DRAM, we will now take the flow status, including the aforementioned number of interfaces, as an example and refer to Table 7 below for understanding. As shown in Table 7, several possible correspondences are illustrated.

[0128] Table 7

[0129] Assuming the target operating frequency is medium and the number of interfaces is between [switching lines, full lines), then based on the correspondence shown in Table 7, it can be determined that the refresh mode of address A in DRAM is refresh, and the refresh modes of addresses B, C and D are all normal.

[0130] It should be noted that Tables 6 and 7 are shown only for ease of understanding of this scheme. In some examples, the refresh mode of some blocks in DRAM can also be power-down. For example, if certain addresses in HBM are confirmed not to be used for a certain period of time, and currently do not store any data, or the data is only temporary, then the refresh mode of these addresses can be set to power-down mode to further reduce the power consumption of HBM.

[0131] In one example, if a first device receives data from an uplink interface and needs to write that data to HBM, the first device can first determine the multiple storage units associated with the data to be written, and further determine whether the refresh mode of these multiple storage units is all in normal mode. If the refresh mode of these multiple storage units is all in normal mode, the first device can directly write the data to be written into these multiple storage units. If some or all of the multiple storage units have a refresh mode that is not in normal mode, the first device can control the logic circuit to modify the refresh mode of the aforementioned partial storage units to normal mode, and further write the data to be written into these multiple storage units. After the data to be written is written into these multiple storage units, the refresh mode of these multiple storage units can be further restored. The storage unit mentioned here can be, for example, the bank mentioned above.

[0132] This can be understood in conjunction with Figure 3. Figure 3 is a schematic diagram illustrating the change process of the refresh mode of a storage unit according to an embodiment of this application.

[0133] As shown in Figure 3, the data to be written is associated with four storage units, corresponding to addresses 0, 1, 2, and 3. Addresses 0 and 1 have a normal refresh mode, while addresses 2 and 3 have a refresh mode. After writing the data, the refresh mode of addresses 2 and 3 can be changed back to normal. After the data has been written to addresses 0, 1, 2, and 3, the refresh mode of addresses 2 and 3 can be restored to refresh.

[0134] In one example, if data needs to be read from DRAM, it can be read from the bank in the normal refresh state based on the current DRAM refresh mode.

[0135] The solutions provided by the embodiments of this application have been described above. Next, with reference to the flowchart shown in Figure 4, a possible implementation of the embodiments of this application will be described. Figure 4 is a flowchart illustrating another control method for DRAM provided by the embodiments of this application.

[0136] The method shown in Figure 4 may include S1'-S210.

[0137] S1': Initialize the SoC.

[0138] S2': Initializes the interface between the SoC and HBM.

[0139] S1'-S2' is the same as S1-S2, so it will not be described again here.

[0140] S3': Sets the operating frequency of various logic circuits.

[0141] S4': Configure parameters for the various operating frequencies set for the logic circuit, obtain the corresponding configuration parameters, and save the configuration parameters corresponding to each operating frequency.

[0142] S5': Select one of the aforementioned operating frequencies as the initialization operating frequency of the logic circuit.

[0143] S3'-S5' differs from S3-S4 shown in Figure 1b. In S3-S4, only one operating frequency is set for the logic circuit, and this operating frequency is the highest frequency supported by the logic circuit. However, in S3'-S5', multiple operating frequencies are set for the logic circuit, and parameters are configured for each operating frequency, with the configuration parameters corresponding to each operating frequency saved. Accordingly, when adjusting the operating frequency of the logic circuit, it is possible to adjust the operating frequency of the logic circuit to a certain operating frequency set in S3'.

[0144] Regarding S5', it should be noted that any operating frequency can be selected from a variety of operating frequencies set for the logic circuit as the initial operating frequency of the logic circuit. For example, the minimum operating frequency can be selected as the initial operating frequency. Alternatively, the maximum operating frequency can be selected as the initial operating frequency of the logic circuit.

[0145] S6': Enable DRAM and set the refresh mode for each bank of DRAM.

[0146] In one example, S6' can be implemented by setting the refresh mode of each bank of the DRAM to normal mode. Of course, the banks of the DRAM can also be set to other refresh modes. For example, the refresh mode of the DRAM can be set to any of the DRAM modes in Table 7 above, without limitation here.

[0147] After executing S6', further executions S201-S210 are performed.

[0148] S201: Normal table lookup or table deletion, monitoring the traffic status of the uplink interface.

[0149] S202: Determine whether to adjust the operating frequency.

[0150] In its implementation, S202 can determine whether to adjust the operating frequency of the roadbed circuit based on the monitored uplink interface traffic status. For details on the implementation of S202, please refer to the description of S102 above; it will not be repeated here.

[0151] If it is determined that the operating frequency of the logic circuit needs to be adjusted, then execute S203-S204.

[0152] If it is determined that no adjustment to the operating frequency of the logic circuit is required, then execute S205.

[0153] S203: Determine the adjustment method for adjusting the operating frequency, and adjust the frequency of the logic circuit based on the adjustment method.

[0154] S204: Adjust the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit.

[0155] For details on the implementation of S203-S204, please refer to the relevant descriptions above; they will not be repeated here.

[0156] After executing S204, continue executing S205.

[0157] S205: Determine whether to use the table.

[0158] If it is determined that a table is required, then proceed with steps S206-S208.

[0159] If it is determined that the following table is not needed, proceed to step S209.

[0160] S206: Change the refresh mode of all storage units associated with the data to be written to normal mode.

[0161] S207: Write the data to be written.

[0162] S208: Restore the refresh mode of the plurality of storage units.

[0163] For details on the implementation of S206-S208, please refer to the relevant descriptions above; they will not be repeated here.

[0164] After executing S208, continue executing S209.

[0165] S209: Determine whether to look up a table.

[0166] If it is determined that a table lookup is required, proceed to step S210.

[0167] If it is determined that no table lookup is needed, then proceed with S201.

[0168] S210: Look up the table.

[0169] For details on the implementation of S210, please refer to the relevant descriptions above; they will not be repeated here.

[0170] Regarding the process shown in Figure 4, it should be noted that it is only one possible implementation of this application. The implementation of this application is not limited to that shown in Figure 4. For example, in one example, if it is determined in S202 that no adjustment of the operating frequency of the logic circuit is needed, it is also possible to first determine whether a table lookup is needed, and then determine whether a table deletion is needed. As another example, after executing S203, it may also include a step of determining whether the refresh mode of the DRAM needs to be adjusted, and so on. These will not be described in detail here.

[0171] Referring to Figure 5, this figure is a schematic diagram of a control device for a high-bandwidth memory provided in an embodiment of this application. The device 500 shown in Figure 5 can be applied to a first device to execute the method provided in the above method embodiment by the first device.

[0172] As shown in Figure 5, the device 500 includes an acquisition unit 501 and a processing unit 502.

[0173] The acquisition unit 501 is used to acquire the traffic status of the uplink interface of the first device. The first device is used to read data from the high-bandwidth memory and / or write data to the high-bandwidth memory through the downlink interface. The high-bandwidth memory includes logic circuits and multiple dynamic random access memories. The logic circuits are used to control the multiple dynamic random access memories.

[0174] The processing unit 502 is used to adjust the operating frequency of the logic circuit according to the flow status and the preset threshold.

[0175] In one possible implementation, the operating frequency is used to determine the rate of the downlink interface.

[0176] In one possible implementation, the processing unit 502 is configured to: determine the target operating frequency of the logic circuit based on the traffic status, the preset threshold, and the current operating frequency of the logic circuit; and adjust the operating frequency of the logic circuit to the target operating frequency.

[0177] In one possible implementation, the processing unit 502 is configured to: determine the preset threshold that matches the traffic state, and determine the target operating frequency based on the preset threshold, the current operating frequency of the logic circuit, and a predetermined correspondence between the preset threshold, the current operating frequency, and the target operating frequency; and adjust the operating frequency of the logic circuit to the target operating frequency.

[0178] In one possible implementation, adjusting the operating frequency of the logic circuit to the target operating frequency includes: determining an adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency and the target operating frequency; the adjustment method includes: a comprehensive adjustment method or a gradual adjustment method; the comprehensive adjustment method is used to adjust the rate of the downlink interface that needs to be adjusted in a single adjustment, and the gradual adjustment method is used to adjust the rate of multiple downlink interfaces that need to be adjusted in multiple adjustments; and adjusting the operating frequency of the logic circuit to the target operating frequency according to the adjustment method.

[0179] In one possible implementation, determining the adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency and the target operating frequency includes: determining the adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency, the target operating frequency, and a pre-determined correspondence between the current operating frequency, the target operating frequency, and the adjustment method.

[0180] In one possible implementation, adjusting the operating frequency of the logic circuit to the target operating frequency includes: if the current operating frequency is less than the target operating frequency, then directly adjusting the operating frequency of the logic circuit to the target operating frequency.

[0181] In one possible implementation, adjusting the operating frequency of the logic circuit to the target operating frequency includes: if the current operating frequency is greater than the target operating frequency, then if the time difference between the current moment and the moment when the first device last reduced the operating frequency of the logic circuit is greater than or equal to a preset time threshold, adjusting the operating frequency of the logic circuit to the target operating frequency.

[0182] In one possible implementation, the processing unit 502 is further configured to: adjust the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit.

[0183] In one possible implementation, adjusting the refresh mode of the dynamic random access memory (DRAM) according to the adjusted operating frequency of the logic circuit includes: determining the target refresh mode of the DRAM based on the adjusted operating frequency of the logic circuit and a predetermined correspondence between the operating frequency and the refresh mode, and adjusting the refresh mode of the DRAM to the target refresh mode.

[0184] In one possible implementation, adjusting the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit includes: adjusting the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit and the flow status.

[0185] In one possible implementation, adjusting the refresh mode of the dynamic random access memory (DRAM) based on the adjusted operating frequency of the logic circuit and the flow status includes: determining the target refresh mode of the DRAM based on the adjusted operating frequency of the logic circuit, the flow status, and a predetermined correspondence between the operating frequency, flow status, and refresh mode, and adjusting the refresh mode of the DRAM to the target refresh mode.

[0186] In one possible implementation, the traffic status includes one or more of the following: the number of interfaces actually used for data transmission among the interfaces used by the first device for data interaction with the second device; the interface rate of the first device for data interaction with the second device; and the usage of the cache used for caching data in the first device.

[0187] In one possible implementation, the processing unit 502 is further configured to: determine a plurality of storage units associated with the data to be written, and modify the refresh mode of the plurality of storage units to normal mode, wherein each of the plurality of storage units is used to store the data to be written; and after the data to be written is written into the plurality of storage units, restore the refresh mode of the plurality of storage units.

[0188] For details on the specific implementation of each unit of the device 500, please refer to the relevant descriptions in the above embodiments; they will not be repeated here.

[0189] It should be noted that the hardware structure of the aforementioned device 500 can be as shown in Figure 6, which is a schematic diagram of the structure of a device provided in an embodiment of this application.

[0190] Please refer to Figure 6. Device 600 includes a processor 610, a communication interface 620, and a memory 630. The number of processors 610 in device 600 can be one or more; Figure 6 shows an example of one processor. In this embodiment, the processor 610, communication interface 620, and memory 630 can be connected via a bus system or other means; Figure 6 shows an example of connection via a bus system 640.

[0191] Processor 610 may be a central processing unit (CPU), an NP, or a combination of CPU and NP. Processor 610 may further include hardware chips. These hardware chips may be ASICs, programmable logic devices (PLDs), or combinations thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0192] The memory 630 may include volatile memory, such as random-access memory (RAM); the memory 630 may also include non-volatile memory, such as flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory 630 may also include a combination of the above types of memory.

[0193] Optionally, the memory 630 stores an operating system and programs, executable modules, or data structures, or subsets thereof, or extended sets thereof. The programs may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and handling hardware-based tasks. The processor 610 can read the programs from the memory 630 to implement the methods provided in the embodiments of this application.

[0194] The bus system 640 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus system 640 can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 6, but this does not indicate that there is only one bus or one type of bus.

[0195] This application provides a computer-readable storage medium, including instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments.

[0196] This application provides a computer program product containing instructions or computer programs, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments.

[0197] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0198] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0199] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical business division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0200] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0201] Furthermore, the various business units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software business unit.

[0202] If the integrated unit is implemented as a software business unit and sold or used as a separate product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0203] Those skilled in the art will recognize that, in one or more of the examples above, the services described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0204] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention.

[0205] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A control method for high-bandwidth memory, characterized in that, The method includes: The first device acquires the traffic status of the uplink interface of the first device. The first device is used to read data from the high-bandwidth memory and / or write data to the high-bandwidth memory through the downlink interface. The high-bandwidth memory includes logic circuits and multiple dynamic random access memories. The logic circuits are used to control the multiple dynamic random access memories. The first device adjusts the operating frequency of the logic circuit according to the flow status and the preset threshold.

2. The method according to claim 1, characterized in that, The operating frequency is used to determine the rate of the downlink interface.

3. The method according to claim 1 or 2, characterized in that, The first device adjusts the operating frequency of the logic circuit according to the flow rate status and a preset threshold, including: The first device determines the target operating frequency of the logic circuit based on the flow status, the preset threshold, and the current operating frequency of the logic circuit. The first device adjusts the operating frequency of the logic circuit to the target operating frequency.

4. The method according to claim 3, characterized in that, The first device determines the target operating frequency of the logic circuit based on the flow status, the preset threshold, and the current operating frequency of the logic circuit, including: The first device determines the preset threshold that matches the traffic flow state, and determines the target operating frequency based on the preset threshold, the current operating frequency of the logic circuit, and the pre-determined correspondence between the preset threshold, the current operating frequency, and the target operating frequency.

5. The method according to claim 3 or 4, characterized in that, The first device adjusts the operating frequency of the logic circuit to the target operating frequency, including: The first device determines an adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency and the target operating frequency. The adjustment method includes an overall adjustment method or a step-by-step adjustment method. The overall adjustment method is used to adjust the rate of the downlink interface that needs to be adjusted in a single adjustment, and the step-by-step adjustment method is used to adjust the rate of multiple downlink interfaces that need to be adjusted in multiple adjustments. The first device adjusts the operating frequency of the logic circuit to the target operating frequency according to the adjustment method.

6. The method according to claim 5, characterized in that, The first device determines an adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency and the target operating frequency, including: The first device determines the adjustment method for adjusting the operating frequency of the logic circuit based on the current operating frequency, the target operating frequency, and the pre-determined correspondence between the current operating frequency, the target operating frequency, and the adjustment method.

7. The method according to any one of claims 3-6, characterized in that, The first device adjusts the operating frequency of the logic circuit to the target operating frequency, including: If the current operating frequency is less than the target operating frequency, the first device directly adjusts the operating frequency of the logic circuit to the target operating frequency.

8. The method according to any one of claims 3-6, characterized in that, The first device adjusts the operating frequency of the logic circuit to the target operating frequency, including: If the current operating frequency is greater than the target operating frequency, then if the time difference between the current moment and the moment when the first device last reduced the operating frequency of the logic circuit is greater than or equal to a preset time threshold, the first device will adjust the operating frequency of the logic circuit to the target operating frequency.

9. The method according to any one of claims 1-8, characterized in that, The method further includes: The first device adjusts the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit.

10. The method according to claim 9, characterized in that, The first device adjusts the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit, including: The first device determines the target refresh mode of the dynamic random access memory based on the adjusted operating frequency of the logic circuit and the predetermined correspondence between the operating frequency and the refresh mode, and adjusts the refresh mode of the dynamic random access memory to the target refresh mode.

11. The method according to claim 9, characterized in that, The first device adjusts the refresh mode of the dynamic random access memory according to the adjusted operating frequency of the logic circuit, including: The first device adjusts the refresh mode of the dynamic random access memory based on the adjusted operating frequency of the logic circuit and the flow status.

12. The method according to claim 11, characterized in that, The first device adjusts the refresh mode of the dynamic random access memory based on the adjusted operating frequency of the logic circuit and the flow status, including: The first device determines the target refresh mode of the dynamic random access memory based on the adjusted operating frequency of the logic circuit, the flow state, and the pre-determined correspondence between the operating frequency, flow state, and refresh mode, and adjusts the refresh mode of the dynamic random access memory to the target refresh mode.

13. The method according to any one of claims 1-12, characterized in that, The traffic status includes one or more of the following: The number of interfaces used by the first device for data interaction with the second device, and the number of interfaces actually used for data transmission. The interface rate at which the first device interacts with the second device for data exchange; The usage of the cache used for caching data in the first device.

14. The method according to any one of claims 1-13, characterized in that, The method further includes: The first device determines multiple storage units associated with the data to be written, and modifies the refresh mode of all multiple storage units to normal mode. Each of the multiple storage units is used to store the data to be written. After the data to be written is written into the plurality of storage units, the refresh mode of the plurality of storage units is restored.

15. A control device for a high-bandwidth memory, characterized in that, Applied to a first device, the device comprising: The acquisition unit is used to acquire the traffic status of the uplink interface of the first device. The first device is used to read data from the high-bandwidth memory and / or write data to the high-bandwidth memory through the downlink interface. The high-bandwidth memory includes logic circuits and multiple dynamic random access memories. The logic circuits are used to control the multiple dynamic random access memories. The processing unit is used to adjust the operating frequency of the logic circuit according to the traffic status and a preset threshold.

16. A device, characterized in that, include: Processor and memory; The memory is used to store instructions or computer programs; The processor is configured to execute the instructions or computer program to perform the method described in any one of claims 1-14.

17. A computer-readable storage medium, characterized in that, This includes instructions or computer programs that, when run on a computer, cause the computer to perform the method described in any one of claims 1-14.

18. A computer program product, characterized in that, This includes a computer program that, when running on a processor, performs the method described in any one of claims 1-14.

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