246 results about "High Bandwidth Memory" patented technology

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

The invention discloses a hardware accelerator and equipment oriented to triple sparse matrix multiplication and an application method thereof.The hardware accelerator comprises a high-bandwidth memory HBM, a crossbar switch network and an on-chip processing unit which are connected in sequence, and the on-chip processing unit comprises a hierarchical cache module, a global controller and a plurality of computing chips; each calculation piece comprises an RA calculation array, a TP calculation array and a local controller, wherein the RA calculation array and the TP calculation array are respectively used for executing front-end operation T = R * A and rear-end operation C = T * P in triple sparse matrix multiplication. The method aims at solving the problem that when a traditional universal processor processes triple sparse matrix multiplication, due to irregular memory access, uneven calculation load and sharp increase of middle parts and results, huge off-chip data carrying is confronted with serious performance and energy efficiency bottlenecks, and the calculation performance and energy efficiency of triple sparse matrix multiplication are improved.

A package includes a photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

Memory systems and methods of assembly are described in which a memory system includes a routing substrate, a processor on a first side of the routing substrate, a memory die stack on the first side of the routing substrate, and a buffer bridge die embedded in the routing substrate and electrically connecting the memory die stack with the processor.

The invention relates to the technical field of large language model deployment, and discloses a large language model weight inverse quantization reasoning device and method.The method comprises the steps that low-precision weight data is transmitted to a high-bandwidth storage from a host and then transmitted to an on-chip storage through the high-bandwidth storage; data conversion from a low-precision format to a high-precision format is completed in the on-chip memory, the data is multiplied by an inverse quantization factor to obtain recovered high-precision weight data, and the functional unit is responsible for executing general matrix multiplication of input data and the high-precision weight data after inverse quantization. And pipeline parallel execution of the inverse quantization operation and the general matrix multiplication operation is realized through a double-buffering technology. According to the invention, on the basis of a dual-path inverse quantization architecture of the vector processing unit and a dual-buffer mechanism in the on-chip memory, the problem of hardware adaptation of low-precision calculation is solved, and efficient execution of a low-precision conversion algorithm is realized under the condition of limited hardware resources.

Methods for fabricating flexible interposers for providing electrical connection between devices mounted at different vertical positions with respect to a substrate or a planar interposer. A bonded structure may comprise a bent flexible interposer extending from a first interposer portion between a main device on the substrate or the planar interposer and a second interposer portion above the main device and above or below a device positioned above the main device and electrically connected to the main device via a bent portion of the flexible interposer.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device may include: a first semiconductor chip; at least one semiconductor chip stack on a surface of the first semiconductor chip in a first direction of the semiconductor device, the at least one semiconductor chip stack configured to be electrically connected to the first semiconductor chip; and a dielectric on the first semiconductor chip in the first direction, and surrounding the at least one semiconductor chip stack in at least one second direction of the semiconductor device, perpendicular to the first direction, wherein the at least one semiconductor chip stack includes at least one second semiconductor chip.

The invention discloses a sparse LU decomposition acceleration method for an FPGA (field programmable gate array) with a flow-sensing high-bandwidth memory, belongs to the technical field of LU decomposition hardware acceleration, and aims to solve the problem of performance bottleneck and efficiency challenge faced by sparse LU decomposition on the FPGA. The acceleration method comprises the following steps of data stream preprocessing, wherein matrix data and metadata are stored and packaged based on a sparse storage format; customizing an FPGA hardware accelerator: carrying out HBM channel allocation and collaborative design of a control unit and memory management; parallel data flow management and scheduling are carried out, and sparse LU decomposition is executed; timely data supply is ensured through a multi-stage pipeline prefetching mechanism; and transmitting the task flow and the data flow to a special parallel processing engine for MAC / DIV calculation in combination with a flow sensing synchronous scheduling strategy.

The present disclosure relates methods, devices, systems, and techniques for high bandwidth memory (HBM). An example semiconductor device includes a first layer, a second layer, a first die between the first layer and the second layer, and a second die stacked together along a first direction. Each of the first die and the second die has a conductive layer. The first die and the second die are bonded through the second layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the first die and a second contact structure coupled to the conductive layer of the second die. The first contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer. The second contact structure extends through the second layer along the first direction without extending through the second die.

A system includes a high bandwidth memory (HBM) and a convolutional neural network (CNN) engine. The HBM includes a virtual bank portion and a system memory portion. The virtual bank portion is configured to store a feature map data and the system memory portion is configured to support data exchanges with a host. The CNN engine includes a convolutional unit configured to execute convolutional layer instructions, a depthwise convolutional unit configured to execute depthwise layer instructions, and a first on-chip buffer. The first on-chip buffer is configured to receive and store the feature map data from the virtual bank portion or receive and store data results from the convolutional unit. The first on-chip buffer is further configured to send the feature map data or the data results from the convolutional unit to the depthwise convolutional unit for processing.

The invention relates to the technical field of semiconductors, provides a semiconductor device, and is used for solving the technical problem that a large lifting space still exists in a high-bandwidth memory technology. The semiconductor device includes: a chip stacking structure including a first semiconductor chip and a second semiconductor chip stacking structure stacked in a first direction; the first semiconductor chip comprises a controller, a calculation module and an interface module; the controller is configured to execute a first access operation on storage data in the second semiconductor chip stacking structure and send the storage data to the interface module to allow external equipment to access the storage data in the second semiconductor chip stacking structure through the interface module; and performing a second access operation on the storage data in the second semiconductor chip stack structure and sending the storage data to the computing module to allow the computing module to perform a computing operation on the storage data. Therefore, the integration level can be improved, the data transmission path can be shortened, and bandwidth consumption and energy consumption loss can be reduced.

Overhang architectures for high bandwidth memory (HBM) multi-die assemblies and methods for making same. The overhang architecture places the DRAM (HBM) underneath the top IC die. The signal interconnects between the top IC die and the DRAM die are direct signal interconnects without lateral routing on a package substrate or on a motherboard.

The invention provides a semiconductor stacking structure and a preparation method thereof, a high-bandwidth memory and electronic equipment, and relates to the technical field of semiconductor chips. The semiconductor stacked structure comprises a plurality of stacked semiconductor structures, each semiconductor structure comprises a storage unit layer and a bonding layer, the bonding layer is arranged on the surface, facing the adjacent semiconductor structure, of the storage unit layer, and the bonding layer is coupled to the storage unit layer. Wherein two adjacent semiconductor structures are in bonding connection through a bonding layer. The semiconductor structure is applied to the dynamic random access memory so as to realize data reading and writing operation.

Memory systems and methods of assembly are described in which a memory system includes a routing substrate, a processor on a first side of the routing substrate, a memory die stack on the first side of the routing substrate, and a buffer bridge die embedded in the routing substrate and electrically connecting the memory die stack with the processor.

The embodiment of the invention provides a chip and a data processing method, and relates to the field of integrated circuits. The chip is used for processing a deep learning algorithm, and the deep learning algorithm comprises a calculation-intensive operator and a memory-access-intensive operator. The chip at least comprises a calculation core particle and a bandwidth core particle, the calculation core particle and the bandwidth core particle are coupled through a core particle interconnection interface, and the bandwidth core particle is further directly connected with the high-bandwidth memory; computing intensive operators are mapped to the computing core particles, and memory access intensive operators are mapped to the bandwidth core particles; the calculation core particle is used for executing a task corresponding to the calculation-intensive operator, and the bandwidth core particle is used for executing a task corresponding to the memory access-intensive operator. According to the method, operators with different requirements on computing power specifications and bandwidth specifications in the deep learning algorithm are processed through different core grains in the same chip, and the problem of hardware resource waste caused by great difference of different parts of the deep learning type algorithm on computing and bandwidth capability requirements is effectively solved.

A photonic integrated circuit (PIC) disposed on a substrate and comprising a semiconductor die hosting an active portion and a passive portion mutually coupled, the active portion being configured to consume electrical power when activated, and the passive portion comprising an optical transmission medium configured to propagate an optical signal to or from the active portion of the PIC; an electronic integrated circuit (EIC) electrically coupled to the active portion of the PIC and comprising components that electrically operate on the active portion of the PIC; and a packaging compound at least partially encapsulating the PIC, the packaging compound defining a cavity on a side of the semiconductor die that is opposite from the substrate, the cavity being filled with an optically transparent medium such that the optical signal can be received from or transmitted to the passive portion of the PIC through the cavity.

A memory device (e.g., a high-bandwidth (HBM) memory device) that includes a memory die having multiple pseudo channels per channel is disclosed. The memory die can include first memory banks associated with a first channel (e.g., having a first command address (CA) bus) and a first pseudo channel (e.g., having a first data (DQ) bus) and second memory banks associated with the first channel and a second pseudo channel (e.g., having a second DQ bus). Operations can be performed at the first memory banks or the second memory banks in response to a command received through the first CA bus. The operations can cause data to be returned to circuitry that routes the data to an interface to the first DQ bus or an interface to the second DQ bus based on whether the data resulted from operations at the first memory banks or the second memory banks.

System-in-package (SiP) devices, and associated systems and methods are disclosed herein. In some embodiments, a SiP device can include a base substrate, as well as a host device and an improved-thermal high-bandwidth memory (HBM) device each integrated with the base substrate. The improved-thermal HBM device can include an interface die and a stack of one or more memory dies carried by the interface die. The interface die includes an input / output (IO) circuit, which is communicably coupled via one or more IO circuit interfaces to the host device through communication channels of the base substrate. The IO circuit interfaces of the improved-thermal HBM device distributes physical interconnect bumps for transmit data and receive data in a dispersed manner along an edge of the interface die in a manner to reduce the occurrence of thermal hotspots.

The invention discloses a data management method, device and equipment and a computer readable storage medium, and belongs to the field of data storage. A storage system comprising a first memory (a nonvolatile memory) and a second memory (a high-bandwidth memory) is constructed, and a first management strategy and a second management strategy are used for cooperatively managing data; the first management strategy processes a data read-write instruction according to a fixed first data attribution scheme to guarantee the basic stability of a logic physical address mapping table and cache data storage; according to the second management strategy, a second data attribution scheme is flexibly determined according to the data mode of the data to be read and written, a storage path is optimized aiming at data with different characteristics, the double-strategy mechanism breaks through a traditional single management mode, persistent and reliable storage of an address mapping table can be ensured, efficient read and write of cache data can be achieved according to the data mode, and the data storage efficiency is improved. The flexibility and suitability of data management are improved, and the user experience is improved.

An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The apparatus may include multiple HBM cubes connected to a processor, such as a GPU. The HBM cubes may be connected in series or in parallel. One or more of the HBM cubes can include a secondary communication circuit configured to facilitate the expanded connection between the multiple cubes.

In an embodiment of the present inventive concept, a high bandwidth memory includes a base die, and a semiconductor stack disposed on the base die, the semiconductor stack comprising a plurality of underfill members and a plurality of memory dies that are alternately stacked. Each of the plurality of underfill members includes first sides, each of the plurality of memory dies includes second sides, and each of the first sides is recessed from a corresponding second side.

The present disclosure relates methods, devices, systems, and techniques for high bandwidth memory (HBM). An example semiconductor device includes a first layer, a second layer, a first die between the first layer and the second layer, and a second die stacked together along a first direction. Each of the first die and the second die has a conductive layer. The first die and the second die are bonded through the second layer. The semiconductor device further includes a first contact structure coupled to the conductive layer of the first die and a second contact structure coupled to the conductive layer of the second die. The first contact structure extends along the first direction and contacts the conductive layer of the first die without extending through the second layer.

An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The high bandwidth memory circuit can include two or more physical layer circuits to communicate with neighboring devices. The high bandwidth memory circuit can broadcast a status to the neighboring devices. The neighboring devices can be configured according to the operating demands of the high bandwidth memory circuit.

A management technique for high bandwidth memory is disclosed. A processing management circuit (PMC) has a main executing circuit and a main memory and is configured to manage at least one processor operation performed by at least one of a first processing element (PE) or a second PE. A shared memory is configured to be shared by the PMC, the first PE, and the second PE. A memory management circuit (MMC) is configured to manage a memory operation on the shared memory based on a memory access by at least one of the PMC, the first PE, or the second PE. The at least one processor operation includes at least one of a program launch, a program execution, and an interrupt delivery.

This invention relates to the field of chip technology, and more particularly to a memory system based on the UBM protocol packaging, comprising a UBM device, a silicon interposer, and a GPU, wherein the GPU includes a UBM physical layer; the UBM device, silicon interposer, and UBM physical layer are interconnected based on a preset UBM physical interconnect protocol, where UBM is an ultra-high bandwidth memory, with a bandwidth higher than that of HBM4; the UBM physical interconnect protocol includes: the UBM device being connected to the silicon interposer using a hybrid bonding packaging method, the UBM physical layer being connected to the silicon interposer using a hybrid bonding packaging method, and the UBM device and the UBM physical layer establishing an interconnection through wiring resources in the silicon interposer. This invention improves the bandwidth line density and bandwidth areal density of the memory system packaging structure.

The invention discloses a vertical channel thin film transistor for a 2T0C DRAM (Dynamic Random Access Memory) and a manufacturing method of the vertical channel thin film transistor. Comprising a substrate, a source electrode deposited on the substrate, an interlayer dielectric layer covering the source electrode, a gate dielectric layer deposited on the surface of the interlayer dielectric layer and a drain electrode arranged in the gate dielectric layer, and the drain electrode forms a conical ring shape; a vertical cylindrical channel is formed in the interlayer dielectric layer, and the bottom of the channel is located in the source electrode; and the vertical cylindrical channel is filled with an active layer. According to the invention, the regulation and control capability of the grid electrode is obviously enhanced through distributed grid electrode control, the short-channel effect is effectively inhibited, the saturation current density is greatly improved, the performance of the transistor is obviously improved, and the transistor is suitable for the fields of artificial intelligence accelerators, storage and calculation integrated chips, high-bandwidth memories and the like and has wide application prospects. And the requirements of high-performance calculation and storage application can be met.

The invention provides a matrix calculation optimization method and device, electronic equipment and a storage medium, and belongs to the technical field of data processing.The method comprises the steps that the data reading amount of each matrix calculation task to be processed is determined; grouping the plurality of calculation cores based on the physical distance between each calculation core and the plurality of high-bandwidth memories to obtain a plurality of calculation core groups; based on the data reading amount of each matrix calculation task, matching a plurality of to-be-processed matrix calculation tasks with a plurality of calculation core groups to obtain a task allocation scheme; and based on a task allocation scheme, allocating each matrix calculation task to a corresponding calculation core group. According to the matrix calculation optimization method and device, the electronic equipment and the storage medium provided by the invention, by comprehensively considering the data reading amount of the matrix calculation task and the physical layout characteristics of the calculation core, load-aware task allocation is realized, the performance bottleneck can be effectively avoided, and the calculation efficiency is improved. And the overall operation efficiency and the hardware resource utilization rate of a plurality of matrix calculation tasks are remarkably improved.

The application provides a packaging method and structure of a multilayer stacked high-width-band memory, which comprises the following steps: providing a buffer chip and a plurality of groups of memory chips, each group of memory chips comprising a first memory chip and a second memory chip; wherein the buffer chip is provided with a plurality of first conductive vias, and the first memory chip and the second memory chip are each provided with a plurality of second conductive vias corresponding to the plurality of first conductive vias; mixing bonding the first memory chip and the second memory chip in each group of memory chips to form a plurality of memory micro-modules; sequentially stacking the plurality of memory micro-modules on the buffer chip; and forming a plastic encapsulation layer to wrap the plurality of memory micro-modules and the buffer chip. The double-chip mixed bonding forms a memory micro-module, which can realize super-multilayer chip stacking, improve production efficiency, realize bonding height reduction, greatly increase the number of chip layers, and increase the capacity.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.