Coordinated near-far memory controller for process-in-hbm

Abstract

A method of coordinating memory commands in a high-bandwidth memory HBM+ system, the method including sending a host memory controller command from a host memory controller to a memory, receiving the host memory controller command at a coordinating memory controller, forwarding the host memory controller command from the coordinating memory controller to the memory, and scheduling, by the coordinating memory controller, a coordinating memory controller command based on the host memory controller command.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S)[0001]The present application claims priority to, and the benefit of, U.S. Provisional Patent Application No. 62 / 536,919, filed on Jul. 25, 2017, the contents of which are incorporated herein by reference in its entirety.BACKGROUND1. Field[0002]Some embodiments of the present disclosure relate generally to memory bandwidth management, and may also relate to a high-bandwidth memory (HBM) system including a processor and a memory controller on a HBM logic die, and to methods of processing in the HBM.2. Description of the Related Art[0003]FIG. 1 is a block diagram of a high-bandwidth memory HBM+ system.[0004]Referring to FIG. 1, a conventional HBM system may generally use a single master, which is generally an off-HBM memory host controller that is used to control a corresponding memory.[0005]In a HBM+ system 100, however, a single slave (e.g., a main memory, which may be a volatile memory, such as a dynamic random access memory (DRAM) on a DRAM...

AI Technical Summary

Benefits of technology

The patent text describes techniques for improving the performance of a system called HBM+ by coordinating two or more memory controllers. This means that the host memory controller should check if the coordinating memory controller has processed all the previous commands before sending any additional ones to the same bank of memory. This helps to avoid congestion and ensures optimal performance. Additionally, the method also includes setting a timeout value for each command and refraining from sending additional memory requests if the previous command is not processed within the set time. Overall, this reduces latency and improves overall performance of the system.

Problems solved by technology

However, the above potential solution is not applicable to the HBM+ system 100.

Further, the HBM logic die of a conventional HBM is unable to perform compute functions exclusively within the HBM logic die.

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