Hbm with in-memory cache manager

Abstract

A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matchesthe tag value stored at the tag address.

Description

[0001] This application claims U.S. Provisional Application Serial No. 62 / 367,062, filed July 26, 2016, entitled "High Bandwidth Memory with Memory Cache Manager," and Serial No. 15 / 272,339, filed September 21, 2016 Priority and benefit of the U.S. application of , the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] One or more aspects of embodiments according to the present invention relate to high bandwidth memory, and more particularly, to a system and method for using high bandwidth memory as a cache memory. Background technique [0003] High-bandwidth memory (HBM) is a high-performance RAM interface for three-dimensional (3D) stacked dynamic RAM (DRAM). Prior art systems using HBM as cache memory may have a cache manager on the host to perform cache management functions. This arrangement places a burden on the host and the interface between the host and the HBM. [0004] Therefore, there is a need for an improved syste...

AI Technical Summary

Problems solved by technology

This arrangement can tax the host and the interface between the host and the HBM

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