LDPC-code-based communication method and communication apparatus

Abstract

An LDPC-code-based communication method and communication apparatus. A device can perform encoding or decoding on the basis of an LDPC matrix, wherein the LDPC matrix is determined on the basis of an LDPC base graph; the column weight of a j-th column in a first region comprised in the base graph is 3, the j-th column comprises an element a corresponding to an i1-th row and the j-th column, an element b corresponding to an i2-th row and the j-th column, and an element c corresponding to an i3-th row and the j-th column, and the row weight of the i2-th row is 3; and in a lifting value set, the difference between the minimum girth of a core parity-check matrix corresponding to shift values of the element a, the element b and the element c and the maximum value of the minimum girth of the core parity-check matrix is less than or equal to 6. In a lifting value set, the settings of shift values of an element a, an element b and an element c can significantly increase the minimum girth of a core parity-check matrix, thereby ensuring the encoding / decoding performance of LDPC codes.

Description

Communication methods and devices based on LDPC codes

[0001] This application claims priority to Chinese Patent Application No. 202410939994.7, filed on July 12, 2024, entitled "Communication Method and Communication Device Based on LDPC Code", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of coding, and more specifically, to a communication method and communication device based on LDPC codes. Background Technology

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using simple feedback shift registers, reducing the coding complexity of LDPC codes.

[0004] Currently, the base graphs (BGs) of QC-LDPC codes described in the standard include BG1 and BG2. In future communication networks, LDPC codes may be applied to more types of communication scenarios, such as high-throughput, low-power, ultra-reliable low-latency communication (URLLC) scenarios. How to improve the encoding and decoding performance of LDPC codes has become a research hotspot. Summary of the Invention

[0005] The embodiments of this application provide a communication method and communication device based on LDPC codes, which can improve the minimum circle length of the core parity check matrix of LDPC codes and the encoding and decoding performance of LDPC codes for different boost values.

[0006] In a first aspect, a communication method is provided, which can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0007] The method includes: acquiring an information bit sequence; determining an LDPC parity check matrix, wherein the LDPC core parity check matrix in the parity check matrix is ​​determined based on an LDPC base map, the base map includes a first region, the first region consists of core rows and core parity columns corresponding to the base map, the first region has exactly one column with a column weight of 3, exactly one row with a row weight of 3, all columns in the first region except those with a column weight of 3 have a column weight of 2, all rows in the first region except those with a row weight of 3 have a row weight of 2, and the shift values ​​corresponding to the two elements in each column with a column weight of 2 are the same, wherein, in the first region The column weight of column j is 3. Column j includes element a corresponding to row i1, column j; element b corresponding to row i2, column j; and element c corresponding to row i3, column j. The row weight of row i2 is 3. In the lift value set, the difference between the minimum circle length of the core parity check matrix corresponding to the shift values ​​of elements a, b, and c and the maximum value of the minimum circle length of the core parity check matrix is ​​less than or equal to 6. The lift value set includes {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}. The information bit sequence is encoded according to the LDPC parity check matrix to obtain the codeword sequence. The codeword sequence is then output.

[0008] It should be understood that this LDPC base map corresponds to the LDPC base matrix. The first region in this LDPC base map can be considered as part B of the LDPC base matrix. Part B is a square matrix and corresponds to the core parity bit (or core parity unit). The core parity bit can be the parity corresponding to the highest bit rate, or it can be a parity bit with a degree greater than or equal to 2, or it can be a parity node corresponding to the set of rows with the highest row weight (row weight significantly higher than other rows). For a detailed explanation, please refer to Figure 4 below.

[0009] It should be understood that element b is located at the intersection of the three-column overlap and the three-row overlap in the first region.

[0010] Based on the above scheme, the shift values ​​of elements a, b, and c in the boost value set are set in a way that improves the minimum circle length of the core parity check matrix and the encoding and decoding performance of the LDPC code compared with the existing scheme.

[0011] In addition, when the boost value is greater than or equal to 9, a 4x4 core parity check matrix can reach the maximum value of the minimum circle length of the core parity check matrix under this LDPC base map setting; or, when the boost value is greater than or equal to 8, a 3x3 core parity check matrix can reach the maximum value of the minimum circle length of the core parity check matrix under this LDPC base map setting, thereby further ensuring that the minimum circle length of the core parity check matrix is ​​the maximum value of the minimum circle length of the core parity check matrix, and improving the encoding and decoding performance of LDPC codes.

[0012] Secondly, a communication method is provided, which can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0013] The method includes: obtaining a codeword sequence; determining an LDPC parity-check matrix, wherein the LDPC core parity-check matrix in the parity-check matrix is ​​determined based on an LDPC base map, the base map includes a first region, the first region consists of core rows and core parity columns corresponding to the LDPC base map, the first region has exactly one column with a column weight of 3, exactly one row with a row weight of 3, all columns in the first region except for the column with a column weight of 3 have a column weight of 2, all rows in the first region except for the row with a row weight of 3 have a row weight of 2, and the translation values ​​corresponding to the two elements in each column with a column weight of 2 are the same, wherein the first... The column weight of column j in the region is 3. Column j includes element a corresponding to row i1 and column j, element b corresponding to row i2 and column j, and element c corresponding to row i3 and column j. The row weight of row i2 is 3. In the lift value set, the difference between the minimum circle length of the core parity check matrix corresponding to the shift values ​​of elements a, b, and c and the maximum value of the minimum circle length of the core parity check matrix is ​​less than or equal to 6. The lift value set includes {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}. Based on the LDPC parity check matrix, the codeword sequence is decoded to obtain the information bit sequence.

[0014] It should be understood that the second aspect corresponds to the first aspect mentioned above, and for details and technical effects, please refer to the first aspect mentioned above.

[0015] It should also be understood that, in conjunction with the 4x4 core check matrix, the following will provide exemplary examples of the shift values ​​of elements a, b, and c, which ensure that the difference between the minimum circle length of the 4x4 core check matrix and the maximum value of the minimum circle length of the 4x4 core check matrix is ​​less than or equal to 6.

[0016] Combining the first or second aspect, in some possible implementations, the lift value is 9 in the lift value set, the minimum cycle length corresponding to the lift value is 18, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 3 1}, {0 3 4}, {0 3 1}, {0 3 7}, {0 6 2}, {0 6 5}, or {0 6 8}, where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 9 in the lift value set.

[0017] Combining the first or second aspect, in some possible implementations, the lift value is 10 from the lift value set, the maximum value of the minimum loop length corresponding to the lift value is 18, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 7}, {0 1 8}, {0 2 9}, {0 3 1}, {0 3 4}, {0 4 3}, {0 6 7}, {0 7 6}, {0 7 9}, {0 8 1}, {0 9 2}, or {0 9 3}, where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 10 from the lift value set.

[0018] Combining the first or second aspect, in some possible implementations, the lift value is 11 from the lift value set, the minimum cycle length corresponding to the lift value is 18, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. The values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 5}, {0 1 9}, {0 2 7}, {0 2 8}, {0 2 10}, {0 3 1}, {0 3 4}, {0 3 5}, {0 4 3}, {0 4 5}, {0 4 9}, {0 5 1}, {0 5 3}, {0 5 9}, {0 6 2}, {0 6 8}, {0 6 3 4}, {0 6 4 5 ... {0 7 2}, {0 7 6}, {0 7 8}, {0 8 6}, {0 8 7}, {0 8 10}, {0 9 1}, {0 9 3}, {0 9 4}, {0 10 2}, {0 10 6} or {0 10 7}, where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 11 in the lift value set.

[0019] Combining the first or second aspect, in some possible implementations, the lift value is 12 from the lift value set, the minimum cycle length corresponding to the lift value is 18, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. The values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 8}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 8}, {0 4 3}, {0 4 5}, {0 4 9}, {0 4 11}, {0 5 4}, {0 7 8}, {0 8 1}, {0 8 3}, {0 8 7}, {0 8 9}, {0 9 4}, {0 9 7 ... 8}, {0 9 11} or {0 11 4}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 12 in the lift value set.

[0020] Combining the first or second aspect, in some possible implementations, the lift value is 13 from the lift value set, the minimum cycle length corresponding to the lift value is 18, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. The values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 6}, {0 1 9}, {0 1 10}, {0 1 11}, {0 2 5}, {0 2 7}, {0 2 8}, {0 2 9}, {0 2 12}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 7}, {0 3 12}, {0 4 1}, {0 4}. 3}、{0 4 5}、{0 4 10}、{0 4 11}、{0 5 3}、{0 5 4}、{0 5 6}、{0 5 7}、{0 5 11}、{0 6 1}、{0 6 2}、{0 6 8}、{0 6 10}、{0 6 11}、{0 7 2}、{0 7 3}、{0 7 5}、{0 7 11}、{0 7 12}、{0 8 2}、{0 8 6}、{0 8 7}、{0 8 9}、{0 8 10}、{0 9 2}、{0 9 3}、{0 9 8}、{0 9 10}、{0 9 12}、{0 10 {1}, {0 10 6}, {0 10 8}, {0 10 9}, {0 10 12}, {0 11 1}, {0 11 4}, {0 11 5}, {0 11 6}, {0 11 8}, {0 12 2}, {0 12 3}, {0 12 4}, {0 12 7} or {0 12 9}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 13 in the lift value set.

[0021] Combining the first or second aspect, in some possible implementations, the lift value is 14 from the lift value set, the minimum cycle length corresponding to the lift value is 18, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. The values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 6}, {0 1 9}, {0 1 11}, {0 1 12}, {0 2 5}, {0 2 11}, {0 2 13}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 8}, {0 3 12}, {0 3 13}, {0 4 1}, {0 4 3}, {0 4 5}, {0 5 2}、{0 5 3}、{0 5 4}、{0 5 6}、{0 5 11}、{0 5 13}、{0 6 1}、{0 6 5}、{0 6 11}、{0 8 3}、{0 8 9}、{0 8 13}、{0 9 1}、{0 9 3}、{0 9 8}、{0 9 10}、{0 9 11}、{0 9 12}、{0 10 9}、{0 10 11}、{0 10 13}、{0 11 1}、{0 11 2}、{0 11 6}、{0 11 9}、{0 11 10}、{0 11 13}、{0 12 1}、{0 12 3}, {0 12 9}, {0 13 2}, {0 13 3}, {0 13 5}, {0 13 8}, {0 13 9}, or {0 13 10}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 14 in the lift value set.

[0022] Combining the first or second aspect, in some possible implementations, the lift value is 15 from the lift value set, the minimum cycle length corresponding to the lift value is 18, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Here, the values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 5}, {0 1 7}, {0 1 10}, {0 1 12}, {0 1 13}, {0 2 5}, {0 2 8}, {0 2 9}, {0 2 10}, {0 2 11}, {0 2 14}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 10}, {0 3 4 5 6 6 7 8 9 ... 11}、{0 3 14}、{0 4 1}、{0 4 3}、{0 4 5}、{0 4 7}、{0 4 10}、{0 4 13}、{0 5 1}、{0 5 2}、{0 5 3}、{0 5 4}、{0 5 6}、{0 5 7}、{0 5 8}、{0 5 9}、{0 5 11}、{0 5 12}、{0 5 13}、{0 5 14}、{0 6 2}、{0 6 5}、{0 6 7}、{0 6 8}、{0 6 10}、{0 6 13}、{0 7 1}、{0 7 4}、{0 7 5}、{0 7 9}、{0 7 10}、{0 7 13}、{0 8 2}、{0 8 5}、{0 8 6}、{0 8 10}、{0 8 11}、{0 8 14}、{0 9 2}、{0 9 5}、{0 9 7}、{0 9 8}、{0 9 10}、{0 9 13}、{0 10 1}、{0 10 2}、{0 10 3}、{0 10 4}、{0 10 6}、{0 10 7}、{0 10 8}、{0 10 9}、{0 10 11}、{0 10 12}、{0 10 13}、{0 10 14}、{0 11 2}、{0 {11 5}, {0 11 8}, {0 11 10}, {0 11 12}, {0 11 14}, {0 12 1}, {0 12 4}, {0 12 5}, {0 12 10}, {0 12 11}, {0 12 14}, {0 13 1}, {0 13 4}, {0 13 5}, {0 13 6}, {0 13 7}, {0 13 10}, {0 14 2}, {0 14 3}, {0 14 5}, {0 14 8}, {0 14 10}, or {0 14 11}, where A, B,C and x are both integers, y is a positive integer, and y is the lift value 15 in the lift value set.

[0023] Combining the first or second aspect, in some possible implementations, the lift value is 16 from the lift value set, the maximum value of the minimum circle length corresponding to the lift value is 18, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among these, the values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 7}, {0 1 10}, {0 1 11}, {0 1 12}, {0 1 14}, {0 2 5}, {0 2 7}, {0 2 13}, {0 2 15}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 10}, {0 3 12}, {0 3 14}, {0 3 ...1}, {0 3 10}, {0 3 12}, {0 3 14}, {0 3 15}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 1}, {0 3 4 1}、{0 4 3}、{0 4 5}、{0 4 7}、{0 4 9}、{0 4 11}、{0 4 13}、{0 4 15}、{0 5 2}、{0 5 3}、{0 5 4}、{0 5 6}、{0 5 7}、{0 5 12}、{0 6 5}、{0 6 7}、{0 6 13}、{0 6 15}、{0 7 1}、{0 7 2}、{0 7 4}、{0 7 6}、{0 7 12}、{0 7 13}、{0 7 3}、{0 9 4}、{0 9 10}、{0 9 12}、{0 9 14}、{0 9 15}、{0 10 1}、{0 10 3}、{0 10 9}、{0 10 11}、{0 11 4}、{0 11 9}、{0 11 10}、{0 11 12}、{0 11 13}、{0 11 14}、{0 12 1}、{0 12 3}、{0 12 5}、{0 12 7}、{0 12 9}、{0 12 11}、{0 12 13}、{0 12 15}、{0 13 2}、{0 13 4}、{0 13 6}、{0 13 11}、{0 13 12}、{0 13 15}、{0 14 1}、{0 14 3}, {0 14 9}, {0 14 11}, {0 15 2}, {0 15 4}, {0 15 5}, {0 15 6}, {0 15 9}, or {0 15 12}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 16 in the lift value set.

[0024] Combining the first or second aspect, in some possible implementations, the lift value is 4 in the lift value set, the minimum circle length corresponding to the lift value is 12, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 2 1} or {0 2 3}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 4 in the lift value set.

[0025] Combining the first or second aspect, in some possible implementations, the lift value is 5 in the lift value set, the minimum circle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 2 3}, {0 3 2}, or {0 4 1}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 5 in the lift value set.

[0026] Combining the first or second aspect, in some possible implementations, the lift value is 6 in the lift value set, the minimum circle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A,y)mod(B,y)mod(C,y)} are: {0 2 3} or {0 4 3}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 6 in the lift value set.

[0027] Combining the first or second aspect, in some possible implementations, the lift value is 7 in the lift value set, the minimum circle length corresponding to the lift value is 16, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 3}, {0 2 6}, {0 3 2}, {0 4 5}, {0 5 1}, or {0 6 4}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 7 in the lift value set.

[0028] Combining the first or second aspect, in some possible implementations, the lift value is 8 from the lift value set, the minimum circle length corresponding to the lift value is 16, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(+x B,y)mod(C+x,y)} are: {0 1 3}, {0 1 4}, {0 1 6}, {0 3 1}, {0 3 2}, {0 3 4}, {0 5 4}, {0 5 6}, {0 5 7}, {0 7 2}, {0 7 4}, or {0 7 5}, where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 8 from the lift value set.

[0029] Thirdly, a communication method is provided, which can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0030] The method includes: acquiring an information bit sequence; determining an LDPC parity check matrix, wherein the LDPC core parity check matrix in the parity check matrix is ​​determined based on an LDPC base map, the base map includes a first region, the first region consists of core rows and core parity columns corresponding to the base map, the first region has exactly one column with a weight of 3, exactly one row with a weight of 3, all columns in the first region except those with a weight of 3 have a weight of 2, all rows in the first region except those with a row weight of 3 have a weight of 2, and the shift values ​​corresponding to the two elements in each column with a weight of 2 are the same, wherein, in the first region The column weight of column j is 3. Column j includes element a corresponding to row i1, column j; element b corresponding to row i2, column j; and element c corresponding to row i3, column j. The row weight of row i2 is 3. In the lift value set, the difference between the minimum circle length of the core parity check matrix corresponding to the shift values ​​of elements a, b, and c and the maximum value of the minimum circle length of the core parity check matrix is ​​less than or equal to 6. The lift value set includes {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}. The information bit sequence is encoded according to the LDPC parity check matrix to obtain the codeword sequence. The codeword sequence is then output.

[0031] Fourthly, a communication method is provided, which can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0032] The method includes: obtaining a codeword sequence; determining an LDPC parity-check matrix, wherein the LDPC core parity-check matrix in the parity-check matrix is ​​determined based on an LDPC base map. The base map includes a first region, which consists of a core row and a core parity column corresponding to the LDPC base map. The first region has exactly one column with a weight of 3, exactly one row with a weight of 3, and all columns in the first region except those with a weight of 3 have a weight of 2. All rows in the first region except those with a row weight of 3 have a weight of 2. In columns with a weight of 2, the shift values ​​corresponding to the two elements in each column are the same. The column weight of column j in the first region is 3. Column j includes element a corresponding to row i1, column j; element b corresponding to row i2, column j; and element c corresponding to row i3, column j. The row weight of row i2 is 3. In the lift value set, the difference between the minimum circle length of the core parity check matrix corresponding to the shift values ​​of elements a, b, and c and the maximum value of the minimum circle length of the core parity check matrix is ​​less than or equal to 6. The lift value set includes {4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}. Based on the LDPC parity check matrix, the codeword sequence is decoded to obtain the information bit sequence.

[0033] It should be understood that the third and fourth aspects are similar to the first and second aspects mentioned above, and the specific technical effects and descriptions can be found in the description of the first aspect mentioned above.

[0034] It should also be understood that, in conjunction with the 3x3 core check matrix, the following will provide exemplary examples of the shift values ​​of elements a, b, and c that ensure the difference between the minimum circle length of the 3x3 core check matrix and the maximum value of the minimum circle length of the 3x3 core check matrix is ​​less than or equal to 6.

[0035] Combining the third or fourth aspect, in some possible implementations, the lift value is 8 in the lift value set, the minimum circle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 6}, {0 3 2}, {0 5 6}, or {0 7 2}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 8 in the lift value set.

[0036] Combining the third or fourth aspect, in some possible implementations, the lift value is 9 in the lift value set, the minimum cycle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. The values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 3}, {0 1 4}, {0 1 6}, {0 1 7}, {0 2 3}, {0 2 5}, {0 2 6}, {0 2 8}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 3 7}, {0 3 8}, {0 4 1}, {0 4 3}, {0 4 6}, {0 4 3}, {0 4 4 6}, {0 4 4 3 ...4 3}, {0 4 4 4 3}, {0 4 4 4 3}, {0 4 4 4 5}, {0 4 4 5}, {0 4 4 5}, {0 4 4 5}, {0 4 4 5}, {0 4 4 5}, {0 4 4 5}, {0 4 4 5 {7}, {0 5 2}, {0 5 3}, {0 5 6}, {0 5 8}, {0 6 1}, {0 6 2}, {0 6 4}, {0 6 5}, {0 6 7}, {0 6 8}, {0 7 1}, {0 7 3}, {0 7 4}, {0 7 6}, {0 8 2}, {0 8 3}, {0 8 5}, or {0 8 6}, where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 9 in the lift value set.

[0037] Combining the third or fourth aspect, in some possible implementations, the lift value is 10 from the lift value set, the minimum cycle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Here, the values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 7}, {0 1 8}, {0 2 9}, {0 3 1}, {0 3 2}, {0 3 4}, {0 4 3}, {0 6 7}, {0 7 6}, {0 7 8}, {0 7 9}, {0 8 1}, {0 9 2}, {0 9 3}, or {0 9 6}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 10 in the lift value set.

[0038] Combining the third or fourth aspect, in some possible implementations, the lift value is 11 from the lift value set, the minimum cycle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Here, the values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 5}, {0 1 8}, {0 1 9}, {0 2 5}, {0 2 7}, {0 2 8}, {0 2 10}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 4 3}, {0 4 5}, {0 4 9}, {0 4 10}, {0 5 1}, {0 3 4}, {0 3 5}, {0 4 3}, {0 4 5}, {0 4 9}, {0 4 10}, {0 5 1}, {0 3 4}, {0 3 5}, {0 3 4}, {0 3 5}, {0 4 6}, {0 4 10}, {0 3 5 ... {5 3}, {0 5 7}, {0 5 9}, {0 6 2}, {0 6 4}, {0 6 8}, {0 6 10}, {0 7 1}, {0 7 2}, {0 7 6}, {0 7 8}, {0 8 6}, {0 8 7}, {0 8 9}, {0 8 10}, {0 9 1}, {0 9 3}, {0 9 4}, {0 9 6}, {0 10 2}, {0 10 3}, {0 10 6} or {0 10 7}, where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 11 in the lift value set.

[0039] Combining the third or fourth aspect, in some possible implementations, the lift value is 12 from the lift value set, the minimum cycle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. The values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 8}, {0 1 10}, {0 2 5}, {0 2 11}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 3 8}, {0 3 10}, {0 5 2}, {0 5 4}, {0 5 8}, {0 7 4}, {0 7 ... {0 9 2}, {0 9 4}, {0 9 7}, {0 9 8}, {0 9 10}, {0 9 11}, {0 10 1}, {0 10 7}, {0 11 2}, {0 11 4} or {0 11 8}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 12 in the lift value set.

[0040] Combining the third or fourth aspect, in some possible implementations, the lift value is 13 from the lift value set, the minimum cycle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. The values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 5}, {0 1 6}, {0 1 9}, {0 1 10}, {0 1 11}, {0 2 5}, {0 2 7}, {0 2 8}, {0 2 9}, {0 2 10}, {0 2 12}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5 ... 7}、{0 3 12}、{0 4 1}、{0 4 3}、{0 4 5}、{0 4 7}、{0 4 10}、{0 4 11}、{0 5 3}、{0 5 4}、{0 5 6}、{0 5 7}、{0 5 11}、{0 5 12}、{0 6 1}、{0 6 2}、{0 6 4}、{0 6 8}、{0 6 10}、{0 6 11}、{0 7 2}、{0 7 3}、{0 7 5}、{0 7 9}、{0 7 11}、{0 7 12}、{0 8 1}、{0 8 2}、{0 8 6}、{0 8 7}, {0 8 9}, {0 8 10}, {0 9 2}, {0 9 3}, {0 9 6}, {0 9 8}, {0 9 10}, {0 9 12}, {0 10 1}, {0 10 6}, {0 10 8}, {0 10 9}, {0 10 11}, {0 10 12}, {0 11 1}, {0 11 3}, {0 11 4}, {0 11 5}, {0 11 6}, {0 11 8}, {0 12 2}, {0 12 3}, {0 12 4}, {0 12 7}, {0 12 8}, or {0 12 9}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 13 in the lift value set.

[0041] Combining the third or fourth aspect, in some possible implementations, the lift value is 14 from the lift value set, the minimum cycle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Here, the values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 5}, {0 1 6}, {0 1 9}, {0 1 10}, {0 1 11}, {0 1 12}, {0 2 5}, {0 2 11}, {0 2 13}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 3 8}, {0 3 12}, {0 3 4}, {0 3 5}, {0 3 8}, {0 3 12}, {0 3 3 4}, {0 3 5}, {0 3 8}, {0 3 12}, {0 3 3 5}, {0 3 3 4}, {0 3 5}, {0 3 3 4}, {0 3 5}, {0 3 8}, {0 3 12}, {0 3 3 5 ... 13}、{0 4 1}、{0 4 3}、{0 4 5}、{0 5 2}、{0 5 3}、{0 5 4}、{0 5 6}、{0 5 8}、{0 5 11}、{0 5 13}、{0 6 1}、{0 6 5}、{0 6 11}、{0 8 3}、{0 8 9}、{0 8 13}、{0 9 1}、{0 9 3}、{0 9 6}、{0 9 8}、{0 9 10}、{0 9 11}、{0 9 12}、{0 10 9}、{0 10 11}、{0 10 13}、{0 11 1}、{0 11 2}、{0 The given values ​​are: {11 6}, {0 11 9}, {0 11 10}, {0 11 12}, {0 11 13}, {0 12 1}, {0 12 3}, {0 12 9}, {0 13 2}, {0 13 3}, {0 13 4}, {0 13 5}, {0 13 8}, {0 13 9}, or {0 13 10}. Where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 14 in the lift value set.

[0042] Combining the third or fourth aspect, in some possible implementations, the lift value is 15 from the lift value set, the minimum circle length corresponding to the lift value is 14, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Here, the values ​​of {ABC}, {A+x B+x C+x}, or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 1 5}, {0 1 7}, {0 1 10}, {0 1 12}, {0 1 13}, {0 2 5}, {0 2 8}, {0 2 9}, {0 2 10}, {0 2 11}, {0 2 14}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5 ...3 5}, {0 3 3 3 5}, {0 3 3 3 5}, {0 3 3 3 5}, {0 3 3 3 5}, {0 3 3 3 5}, {0 3 7}、{0 3 10}、{0 3 11}、{0 3 14}、{0 4 1}、{0 4 3}、{0 4 5}、{0 4 7}、{0 4 10}、{0 4 13}、{0 6 2}、{0 6 4}、{0 6 5}、{0 6 7}、{0 6 8}、{0 6 10}、{0 6 13}、{0 6 14}、{0 7 1}、{0 7 4}、{0 7 5}、{0 7 9}、{0 7 10}、{0 7 13}、{0 8 2}、{0 8 5}、{0 8 6}、{0 8 10}、{0 8 11}、{0 8 14}、{0 9 1}、{0 9 2}、{0 9 5}、{0 9 7}、{0 9 8}、{0 9 10}、{0 9 11}、{0 9 13}、{0 11 2}、{0 11 5}、{0 11 8}、{0 11 10}、{0 11 12}、{0 11 14}、{0 12 1}、{0 12 4}、{0 12 5}、{0 12 8}、{0 12 10}、{0 12 11}、{0 12 13}、{0 12 14}、{0 13 1}、{0 13 4}、{0 13 5}、{0 13 6}、{0 13 7}, {0 13 10}, {0 14 2}, {0 14 3}, {0 14 5}, {0 14 8}, {0 14 10}, or {0 14 11}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 15 in the lift value set.

[0043] Combining the third or fourth aspect, in some possible implementations, the lift value is 4 in the lift value set, the minimum circle length corresponding to the lift value is 8, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 2}, {0 1 3}, {0 1 4}, {0 2 1}, {0 2 3}, {0 3 1}, or {0 3 2}, where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 4 in the lift value set.

[0044] Combining the third or fourth aspect, in some possible implementations, the lift value is 5 in the lift value set, the minimum circle length corresponding to the lift value is 10, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 3}, {0 1 4}, {0 2 1}, {0 2 3}, {0 3 2}, {0 3 4}, {0 4 1}, or {0 4 2}, where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 5 in the lift value set.

[0045] In conjunction with the third or fourth aspect, in some possible implementations, the lift value is 6 in the lift value set, the minimum circle length corresponding to the lift value is 12, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 3}, {0 2 3}, {0 4 3} or {0 5 3}, where A, B, C and x are all integers, y is a positive integer, and y is the lift value 6 in the lift value set.

[0046] Combining the third or fourth aspect, in some possible implementations, the lift value is 7 in the lift value set, the minimum circle length corresponding to the lift value is 12, the translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Among them, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 3}, {0 1 5}, {0 2 3}, {0 2 6}, {0 3 1}, {0 3 2}, {0 4 5}, {0 4 6}, {0 5 1}, {0 5 4}, {0 6 2}, or {0 6 4}, where A, B, C, and x are all integers, y is a positive integer, and y is the lift value 7 in the lift value set.

[0047] Fifthly, a communication apparatus is provided for performing the method provided in any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided in any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0048] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0049] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0050] In a sixth aspect, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0051] In one implementation, the device is either a transmitting device or a receiving device.

[0052] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0053] In a seventh aspect, a communication device is provided, comprising: at least one processor and a communication interface, the at least one processor being configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the foregoing aspects or their implementations. The communication interface may be implemented in hardware or software.

[0054] In one implementation, the device further includes the memory.

[0055] Eighthly, a processor is provided for executing the methods provided in the above aspects.

[0056] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0057] Ninthly, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any of the foregoing aspects or their implementations.

[0058] In a tenth aspect, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0059] Eleventhly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in memory through the communication interface and executes the methods provided in any of the above aspects or their implementations. The communication interface can be implemented in hardware or software.

[0060] Optionally, as one implementation, the chip also includes a memory that stores computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the methods provided by any of the above aspects or their implementations.

[0061] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0062] In a twelfth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed.

[0063] In a thirteenth aspect, a communication system is provided, comprising at least one of the transmitting end device or receiving end device described above. Attached Figure Description

[0064] Figure 1 is a schematic diagram of a network architecture to which embodiments of this application can be applied.

[0065] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0066] Figure 3 shows the Tanner plot of the parity-check matrix H of an LDPC.

[0067] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0068] Figure 5 is a schematic diagram of the information transmission process.

[0069] Figure 6 is a schematic flowchart of a communication method 600 provided in this application.

[0070] Figure 7 is a schematic diagram of a 4-row, 4-column LDPC base map provided in this application.

[0071] Figure 8 is a schematic diagram of a first region of 4 rows and 4 columns provided in this application.

[0072] Figure 9 is a schematic diagram of a first region of 3 rows and 3 columns provided in this application.

[0073] Figure 10 is a schematic block diagram of a communication device 1000 provided in an embodiment of this application.

[0074] Figure 11 is a schematic block diagram of the communication device 1100 provided in an embodiment of this application. Detailed Implementation

[0075] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0076] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when," "under the circumstances," "if," and "if" indicate that the device will take corresponding action under certain objective conditions, not that there is a time limit, nor do they require the device to perform a judgment action during implementation, nor do they imply any other limitations.

[0077] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0078] The following describes a communication system to which embodiments of this application can be applied.

[0079] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0080] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0081] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of this application. As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application in other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0082] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0083] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, or RAN equipment including CU and DU nodes, or RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes. Alternatively, network equipment may also be a radio controller, relay station, vehicle-mounted equipment, or wearable device in a cloud radio access network (CRAN) scenario. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication systems. A base station may support networks with the same or different access technologies, without limitation.

[0084] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0085] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0086] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, ultra-reliable low-latency communication (URLLC) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0087] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0088] 1. LDPC code

[0089] LDPC codes are a type of linear block code. Linear block codes divide the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0090] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit sequence length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0091] In 1981, Tanner represented the parity-check matrix H graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint, which will be explained below with reference to Figures 2 and 3.

[0092] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0093] In Figure 2, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 2, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0094] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0095] As shown in Figure 3, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices. The cycle starts and ends at one vertex in this group of vertices and passes through each node only once. The length of the cycle (or cycle length) is defined as the number of edges it contains, while the perimeter of the graph, also known as the graph's circumference, is defined as the minimum cycle length in the graph. In Figure 3, the perimeter is 4, as shown by the bolded lines. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is also corresponding to each codeword bit of the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is also corresponding to the parity bits of the LDPC. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, then the element (i, j) in the H matrix has a value of 1; if there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge. Furthermore, in a Tanner graph, a cycle is a closed loop formed by connecting variable nodes, check nodes, and edges end-to-end.

[0096] 2. QC-LDPC code

[0097] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base graph (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG Basis matrix H BGAn element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The expansion process of the base matrix is ​​described below.

[0098] Based on the basis matrix and the boosting value Z c (Lifting size) allows the basis matrix to be expanded into a complete parity-check matrix for encoding or decoding. In this application, Z... c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process involves lifting all elements in the basis matrix to a Z-shape. c ×Z c A square matrix, in which 0 is promoted to Z. c ×Z c The zero matrix is ​​promoted to an identity matrix, and then cyclically shifted based on the shifting value (SV) corresponding to the 1. This cyclic shift can be to the left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, 2, and 3, the cyclically shifted matrix after shifting to the right is as follows:

[0099] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0100] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0101] (3) When the translation value is 2, the corresponding cyclically shifted matrix is:

[0102] (4) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0103] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrix is ​​represented by an exponential matrix H, where each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. This significantly reduces the storage space required for the complete parity check matrix H. bThe elements in it can also be called QC blocks.

[0104] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0105] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the array represents a Z. c Square matrix of order Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0106] For example, As shown below:

[0107] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0108] It is understandable that the above exponent matrix H... b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0109] 3. Increase value Z c (Lifting Size) and (Shifting Value)

[0110] The storage content of the 5G LDPC code regarding shifting values ​​includes: (1) a list of lifting sizes; and (2) a list of shifting values ​​that correspond one-to-one with the rows of the lifting size list.

[0111] For example, the list of Lifting Sizes is shown in Table 1.

[0112] Table 1

[0113] The j-th row of the Lifting Size list includes Where a j ∈{2,3,5,7,9,11,13,15}, max(kj )∈{7,7,6,5,5,5,4,4}; The row index of Lifting Size corresponds one-to-one with the column index of Shifting Value, that is, the lifting size in each row of the Lifting Size list corresponds to a set of Shifting Values.

[0114] For example, the list of Shifting Values ​​is shown in Table 2.

[0115] Table 2

[0116] It is understandable that the basis matrix H BG The elements in the matrix include 0 and 1, meaning all elements are either 0 or 1. Table 2 stores all rows of the base matrix and the associated columns for each row. If an associated column exists, it indicates that the value at that position in the base matrix is ​​1; otherwise, it is 0.

[0117] For a fixed lift index, a non-zero position in the base matrix corresponds to one translation value. For example, H... BG The shift value corresponding to row 0, column 0 when the promotion index is 0 is 211, H BG The shift value corresponding to the 6th column of the 1st row in the middle when the lifting index = 3 is 66, H BG The shift value corresponding to the second row and ninth column of the middle column when the promotion index is 7 is 206.

[0118] It's understandable that LDPC encoding requires first determining the lift value, and then constructing a parity check matrix based on the corresponding shift value. For example, if the determined lift value is 40, and the lift value index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the shift value in the column corresponding to lift value index = 2 in Table 2.

[0119] 4. Column weight and row weight

[0120] For a given column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a given row of a matrix, row weight refers to the number of non-zero elements contained in that row. It can be understood that the matrix involved in the descriptions of row and column weights is the parity check matrix H.

[0121] 5. Structure of the basis matrix

[0122] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0123] As shown in Figure 4(a), the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 4(b). Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or it can be a parity with a degree greater than or equal to 2, or it can be the parity node corresponding to the row set with the largest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 4(b) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4(b). The raptor-like region can correspond to part E in Figure 4(b) and can be an identity matrix corresponding to the parity bits of the low-rate extension.

[0124] The parity-check matrix of the LDPC code shown in Figure 4 adopts a "raptor-like" structure, which can be gradually extended to low code rates from a high code rate core matrix. In actual use, as shown in Figure 4(a), the first X rows and the first Y columns of the parity-check matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0125] It should be noted that the parity check matrix can be represented by the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and will not be described in detail here.

[0126] 6. Information column and validation column

[0127] The columns of the LDPC base matrix consist of information columns and check columns.

[0128] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0129] Check columns: Corresponding to check bits (or check digits, etc.), these can include core check columns and extended check columns. The core check columns are the columns corresponding to part B, and the extended check columns are the columns corresponding to part C or part E. Extended check columns can also be called raptor-like columns.

[0130] 7. Core rows, core columns, core matrix, and core check columns

[0131] Core rows: The core rows of the LDPC base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0132] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0133] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or the part consisting of part A and part B.

[0134] Core check columns: N columns following the information columns in the LDPC base matrix, where N equals the number of rows corresponding to the core rows. For example, the information columns are 1 to K. b If the column is K, then the core verification column is K. b +1 to K b +N columns.

[0135] 8. Message length, code length, and code rate

[0136] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0137] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0138] Code rate refers to the ratio of the length of the bit sequence of information to be transmitted to the code length.

[0139] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, media access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0140] 9. Information Transmission Process

[0141] Figure 5 is a schematic diagram of the information transmission process applicable to this application. As shown in Figure 5, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the transmitting end device, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the receiving end device. The embodiments of this application mainly involve the source coding, channel coding, channel decoding, and source recovery shown in Figure 5.

[0142] Currently, the main characteristics of irregular repeat-accumulate (IRA) LDPC codes include a double-diagonal structure. The degree distribution of an IRA-LDPC code consists of one triple column and the remaining columns are double columns. In this IRA-LDPC code, the two shift values ​​of the double column are the same, and in the triple column, two of the three shift values ​​are the same, while the third shift value is different from the other two.

[0143] It should be understood that the shift value characteristics of IRA-LDPC codes ensure that encoding can be performed in a simple manner. Specifically, the encoding process involves XORing all parity equations to obtain the bit values ​​of the parity nodes corresponding to the three columns. Then, new parity bit values ​​are obtained based on the currently obtained bit values, until all parity bits are obtained. However, LDPC codes require high reliability and cannot have significant error floors. Due to the special shift value characteristics of IRA-LDPC codes, a large number of small trap sets are formed at each boost value, making LDPC codes prone to error floors during the encoding and decoding process.

[0144] In view of this, this application proposes a communication method based on LDPC codes. It is designed such that, under different boost values, the corresponding translation values ​​can ensure that the minimum circle length of the LDPC core parity check matrix is ​​the maximum value of the minimum circle length of the LDPC base map, thereby avoiding the error layering caused by a small minimum circle length and improving the encoding and decoding performance of LDPC codes.

[0145] Figure 6 is a schematic flowchart of a communication method 600 based on LDPC codes provided in this application. The method includes the following steps.

[0146] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0147] S610, the transmitting device obtains the information bit sequence.

[0148] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0149] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0150] S620, the transmitting device determines the LDPC check matrix.

[0151] The LDPC parity-check matrix is ​​determined based on the LDPC base graph (or LDPC base matrix), which will be referred to as the base graph below. The base graph includes a first region, which consists of the core rows and core parity columns corresponding to the base graph.

[0152] It should be understood that the first region has exactly one column with a weight of 3 and exactly one row with a weight of 3. The weight of all columns in the first region except for the column with a weight of 3 is 2, and the weight of all rows in the first region except for the row with a weight of 3 is 3. The shift values ​​corresponding to the two elements in each column with a weight of 2 are the same.

[0153] For example, the first region can be part B in Figure 4 above, and the first region is a square matrix. In this first region, only one column has a column weight of 3, and only one row has a row weight of 3. The column weights of all columns except those with a column weight of 3 are 2, and the row weights of all rows except those with a row weight of 3 are 2. Specific examples of this first region can be found in the schematic diagrams of the first region shown in Figures 7 and 8 provided in the embodiments of this application.

[0154] It should also be understood that the column weight of column j in the first region is 3, and column j includes three 1 elements, which can be represented as element a, element b, and element c. Element a can be located in row i1, column j of the first region; element b can be located in row i2, column j of the first region, where row i2 has a row weight of 3; and element c can be located in row i3, column j of the first region. The minimum circle length of the core check matrix corresponding to elements a, b, and c is the maximum value of the minimum circle length corresponding to the lift values ​​in the lift sets corresponding to elements a, b, and c.

[0155] The following is an example of how to determine the maximum value of the minimum circle length of the core verification matrix:

[0156] Figure 7 is a schematic diagram of a 4x4 LDPC base map. As shown in Figure 7, only one row is a triple row and only one column is a triple column; the other rows and columns are double rows and columns. The gray areas in Figure 7 represent locations where there are no parity relationships on the base map, while the white areas represent locations where there are parity relationships. The numbers 0, a, and b in the upper right corner of Figure 7 represent the translation values ​​(or offset values) corresponding to the elements at those locations. The following section uses 0, a, and b as an example, with a lift value of L, and discusses the maximum and minimum circle lengths of the 4x4 LDPC base map in conjunction with Figure 7:

[0157] Starting from the top left corner of Figure 7, find the starting point of the circle. The two values ​​enclosed in parentheses are: the left side represents the position of the variable value (or variable node), and the right side represents the position of the check value (or check node). In the circle path, for vertical processes, the variable nodes remain unchanged, and the check nodes are derived from the variable nodes and their translation values; for horizontal processes, the check nodes remain unchanged, and the variable nodes are derived from the check nodes and their translation values.

[0158] As shown in Figure 7, the arrows indicate the order of the paths, as indicated by the numbers:

[0159] 1. Starting from (0,0) and moving downwards, keeping the variables unchanged, check the offset -a to get (0,La);

[0160] 2. Starting from (0, La) to the right, the check remains unchanged, and the variable is shifted by 0 to obtain (La, La);

[0161] 3. Starting from (La, La) and moving downwards, keep the variables unchanged, check the offset of 0, and obtain (La, La);

[0162] 4. Starting from (La, La) and checking to the left, the variable is shifted by b, resulting in (L-a+b, La);

[0163] 5. Starting from (L-a+b, La) upwards, the variables remain unchanged, and the check offset is 0, (L-a+b, L-a+b);

[0164] 6. Starting from (L-a+b, L-a+b) to the right, the check remains unchanged, and the variable is offset by 0, resulting in (L-a+b, L-a+b);

[0165] 7. Starting from (L-a+b, L-a+b) downwards, keep the variables unchanged, check the offset of 0, and get (L-a+b, L-a+b);

[0166] 8. Starting from (L-a+b, L-a+b) to the right, the check remains unchanged, and the variable is offset by 0, resulting in (L-a+b, L-a+b);

[0167] 9. Starting from (L-a+b, L-a+b) downwards, keeping the variables unchanged, check the offset of 0, and obtain (L-a+b, L-a+b);

[0168] 10. Starting from (L-a+b, L-a+b) to the left, the check remains unchanged, and the variable is shifted by a to obtain (L+b, L-a+b);

[0169] 11. Starting from (L+b, L-a+b), keep the variables unchanged, check the offset -b, and get (L+b, L);

[0170] 12. Starting from (L+b, L) to the right, the check remains unchanged, and the variable is offset by 0 to obtain (L, L);

[0171] 13. Starting from (L, L) and keeping the variables unchanged, check the offset of 0 to get (L, L);

[0172] 14. Starting from (L, L) to the right, the check remains unchanged, and the variable is offset by 0 to obtain (L, L);

[0173] 15. Starting from (L, L) and keeping the variables unchanged, check the offset of 0 to get (L, L);

[0174] 16. Starting from (L, L) to the right, the check remains unchanged, and the variable is offset by 0 to obtain (L, L);

[0175] 17. Starting from (L, L) and keeping the variables unchanged, check the offset of 0 to get (L, L);

[0176] 18. Starting from (L, L) to the right, the check remains unchanged, and the variable is offset by 0, resulting in (L, L).

[0177] It should be understood that (L, L) modulo (0, 0) means the loop returns to the origin (or starting point), that is, the starting point and the ending point of the loop are the same point.

[0178] Therefore, with any translation values ​​of 0, a, and b, the 4x4 check matrix shown in Figure 7 requires at least 18 path selections to return to the origin. The maximum value of the minimum loop length of the core check matrix under the LDPC base map is independent of the values ​​of the translation and lift values ​​L. The maximum value of the minimum loop length of the 4x4 LDPC base map core check matrix is ​​18.

[0179] Based on the above method for determining the maximum value of the minimum circle length of the core check matrix, the following will exemplarily combine the cases where the first region is a 4x4 square matrix and a 3x3 square matrix, and exhaustively describe the translation values ​​corresponding to elements a, b, and c that satisfy the condition that the difference between the minimum circle length of the core check matrix corresponding to elements a, b, and c and the maximum value of the minimum circle length of the core check matrix is ​​less than or equal to 6, for different boost values.

[0180] Example 1:

[0181] Assuming the first region is a 4x4 square matrix, based on the characteristics of the first region described above, Figure 8 shows a schematic diagram of a 4x4 first region.

[0182] It should be understood that the maximum value of the minimum circle length of the 4x4 core check matrix is ​​18.

[0183] As shown in Figure 8, elements a, b, and c are located on the three 1 elements in the only column with a column weight of 3 in the first region, and the translation values ​​corresponding to the 1 elements in the other columns with a column weight of 2 are all the same.

[0184] For example, the lift value corresponding to elements a, b, and c is 9, and the minimum circle length corresponding to this lift value of 9 is 18. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0185] It should be understood that, given a lift value of 9 for elements a, b, and c, the specific values ​​of {ABC} that ensure the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of 18 for the minimum loop length of a 4x4 core check matrix are as follows:

[0186] {0 3 1}, {0 3 4}, {0 3 1}, {0 3 7}, {0 6 2}, {0 6 5}, or {0 6 8}.

[0187] For example, the lift value for elements a, b, and c is 10, and the minimum circle length corresponding to this lift value of 10 is 18. The translation values ​​for elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0188] It should be understood that, with a boost value of 10 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 4x4 core check matrix, which is 18. The value of {ABC} is as follows:

[0189] {0 1 7}, {0 1 8}, {0 2 9}, {0 3 1}, {0 3 4}, {0 4 3}, {0 6 7}, {0 7 6}, {0 7 9}, {0 8 1}, {0 9 2}, or {0 9 3}.

[0190] For example, the lift value corresponding to elements a, b, and c is 11, and the minimum circle length corresponding to this lift value of 11 is 18. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0191] It should be understood that, given a lift value of 11 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 4x4 core check matrix, which is 18. The values ​​of {A BC} are as follows:

[0192] {0 1 4}, {0 1 5}, {0 1 9}, {0 2 7}, {0 2 8}, {0 2 10}, {0 3 1}, {0 3 4}, {0 3 5}, {0 4 3}, {0 4 5}, {0 4 9}, {0 5 1}, {0 5 3}, {0 5 9}, {0 6 2}, {0 6 8}, {0 6 10}, {0 7 2}, {0 7 6}, {0 7 8}, {0 8 6}, {0 8 7}, {0 8 10}, {0 9 1}, {0 9 3}, {0 9 4}, {0 10 2}, {0 10 6} or {0 10 7}.

[0193] For example, the lift value corresponding to elements a, b, and c is 12, and the minimum circle length corresponding to this lift value of 12 is 18. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0194] It should be understood that, with a lift value of 12 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 4x4 core check matrix, which is 18. The values ​​of {ABC} are as follows:

[0195] {0 1 8}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 8}, {0 4 3}, {0 4 5}, {0 4 9}, {0 4 11}, {0 5 4}, {0 7 8}, {0 8 1}, {0 8 3}, {0 8 7}, {0 8 9}, {0 9 4}, {0 9 7}, {0 9 8}, {0 9 11} or {0 11 4}.

[0196] For example, the lift value corresponding to elements a, b, and c is 13, and the minimum circle length corresponding to this lift value of 13 is 18. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0197] It should be understood that, given a lift value of 13 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 4x4 core check matrix, which is 18. The values ​​of {A BC} are as follows:

[0198] {0 1 4}, {0 1 6}, {0 1 9}, {0 1 10}, {0 1 11}, {0 2 5}, {0 2 7}, {0 2 8}, {0 2 9}, {0 2 12}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 7}, {0 3 12}, {0 4 1}, {0 4 3}, {0 4 5}, {0 4 10}, {0 4 11}, {0 5 3}, {0 5 4}, {0 5 6}, {0 5 7}, {0 5 11}, {0 6 1}, {0 6 2}, {0 6 8}, {0 6 10}, {0 6 1 4} 11}、{0 7 2}、{0 7 3}、{0 7 5}、{0 7 11}、{0 7 12}、{0 8 2}、{0 8 6}、{0 8 7}、{0 8 9}、{0 8 10}、{0 9 2}、{0 9 3}、{0 9 8}、{0 9 10}、{0 9 12}、{0 10 1}、{0 10 6}、{0 10 8}、{0 10 9}、{0 10 12}、{0 11 1}、{0 11 4}、{0 11 5}、{0 11 6}、{0 11 8}、{0 12 2}、{0 12 3}、{0 12 4}, {0 12 7} or {0 12 9}.

[0199] For example, the lift value for elements a, b, and c is 14, and the minimum circle length corresponding to this lift value of 14 is 18. The translation values ​​for elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0200] It should be understood that, with a boost value of 14 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 4x4 core check matrix, which is 18. The values ​​of {A BC} are as follows:

[0201] {0 1 6}, {0 1 9}, {0 1 11}, {0 1 12}, {0 2 5}, {0 2 11}, {0 2 13}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 8}, {0 3 12}, {0 3 13}, {0 4 1}, {0 4 3}, {0 4 5}, {0 5 2}, {0 5 3}, {0 5 4}, {0 5 6}, {0 5 11}, {0 5 13}, {0 6 1}, {0 6 5}, {0 6 11}, {0 8 3}, {0 8 9}, {0 8 13}, {0 9 1}, {0 9 3}, {0 9 8}, {0 9 10}, {0 9 11}, {0 9 12}, {0 10 9}, {0 10 11}, {0 10 13}, {0 11 1}, {0 11 2}, {0 11 6}, {0 11 9}, {0 11 10}, {0 11 13}, {0 12 1}, {0 12 3}, {0 12 9}, {0 13 2}, {0 13 3}, {0 13 5}, {0 13 8}, {0 13 9}, or {0 13 10}.

[0202] For example, the lift value for elements a, b, and c is 15, and the minimum circle length corresponding to this lift value of 15 is 18. The translation values ​​for elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0203] It should be understood that, with a boost value of 15 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 4x4 core check matrix, which is 18. The values ​​of {A BC} are as follows:

[0204] {0 1 4}, {0 1 5}, {0 1 7}, {0 1 10}, {0 1 12}, {0 1 13}, {0 2 5}, {0 2 8}, {0 2 9}, {0 2 10}, {0 2 11}, {0 2 14}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 10}, {0 3 11}, {0 3 14}, {0 4 1}, {0 4 3}, {0 4 5}, {0 4 7}, {0 4 10}, {0 4 13}, {0 5 1}, {0 5 2}, {0 5 3}, {0 5 4}, {0 5 6}, {0 {0 5 7}, {0 5 8}, {0 5 9}, {0 5 11}, {0 5 12}, {0 5 13}, {0 5 14}, {0 6 2}, {0 6 5}, {0 6 7}, {0 6 8}, {0 6 10}, {0 6 13}, {0 7 1}, {0 7 4}, {0 7 5}, {0 7 9}, {0 7 10}, {0 7 13}, {0 8 2}, {0 8 5}, {0 8 6}, {0 8 10}, {0 8 11}, {0 8 14}, {0 9 2}, {0 9 5}, {0 9 7}, {0 9 8}, {0 9 7} 10}、{0 9 13}、{0 10 1}、{0 10 2}、{0 10 3}、{0 10 4}、{0 10 6}、{0 10 7}、{0 10 8}、{0 10 9}、{0 10 11}、{0 10 12}、{0 10 13}、{0 10 14}、{0 11 2}、{0 11 5}、{0 11 8}、{0 11 10}、{0 11 12}、{0 11 14}、{0 12 1}、{0 12 4}、{0 12 5}、{0 12 10}、{0 12 11}、{0 12 14}、{0 13 1}, {0 13 4}, {0 13 5}, {0 13 6}, {0 13 7}, {0 13 10}, {0 14 2}, {0 14 3}, {0 14 5}, {0 14 8}, {0 14 10}, or {0 14 11}.

[0205] For example, the lift value for elements a, b, and c is 16, and the minimum circle length corresponding to this lift value of 16 is 18. The translation values ​​for elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0206] It should be understood that, with a boost value of 16 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 4x4 core check matrix, which is 18. The values ​​of {ABC} are as follows:

[0207] {0 1 4}, {0 1 7}, {0 1 10}, {0 1 11}, {0 1 12}, {0 1 14}, {0 2 5}, {0 2 7}, {0 2 13}, {0 2 15}, {0 3 1}, {0 3 4}, {0 3 5}, {0 3 10}, {0 3 12}, {0 3 14}, {0 4 1}, {0 4 3}, {0 4 5}, {0 4 7}, {0 4 9}, {0 4 11}, {0 4 13}, {0 4 15}, {0 5 2}, {0 5 3}, {0 5 4}, {0 5 6}, {0 5 7}, {0 5 12}、{0 6 5}、{0 6 7}、{0 6 13}、{0 6 15}、{0 7 1}、{0 7 2}、{0 7 4}、{0 7 6}、{0 7 12}、{0 7 13}、{0 9 3}、{0 9 4}、{0 9 10}、{0 9 12}、{0 9 14}、{0 9 15}、{0 10 1}、{0 10 3}、{0 10 9}、{0 10 11}、{0 11 4}、{0 11 9}、{0 11 10}、{0 11 12}、{0 11 13}、{0 11 14}、{0 12 1}, {0 12 3}, {0 12 5}, {0 12 7}, {0 12 9}, {0 12 11}, {0 12 13}, {0 12 15}, {0 13 2}, {0 13 4}, {0 13 6}, {0 13 11}, {0 13 12}, {0 13 15}, {0 14 1}, {0 14 3}, {0 14 9}, {0 14 11}, {0 15 2}, {0 15 4}, {0 15 5}, {0 15 6}, {0 15 9}, or {0 15 12}.

[0208] For example, the lift value corresponding to elements a, b, and c is 4, and the minimum circle length corresponding to this lift value of 4 is 12. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0209] It should be understood that, with a lift value of 4 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length (12) of the core check matrix corresponding to elements a, b, and c is less than the maximum minimum loop length (18) of the 4x4 core check matrix, and the difference is 6. The values ​​of {ABC} are as follows:

[0210] {0 2 1} or {0 2 3}.

[0211] For example, the lift value corresponding to elements a, b, and c is 5, and the minimum circle length corresponding to this lift value of 5 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0212] It should be understood that, with a boost value of 5 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length (14) of the core check matrix corresponding to elements a, b, and c is less than the maximum minimum loop length (18) of the 4x4 core check matrix, and the difference is 4. The values ​​of {ABC} are as follows:

[0213] {0 1 4}, {0 2 3}, {0 3 2}, or {0 4 1}.

[0214] For example, the lift value corresponding to elements a, b, and c is 6, and the minimum circle length corresponding to this lift value of 6 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0215] It should be understood that, with a lift value of 6 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length (14) of the core check matrix corresponding to elements a, b, and c is less than the maximum minimum loop length (18) of the 4x4 core check matrix, and the difference is 4. The values ​​of {ABC} are as follows:

[0216] {0 2 3} or {0 4 3}.

[0217] For example, the lift value corresponding to elements a, b, and c is 7, and the minimum circle length corresponding to this lift value of 7 is 16. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0218] It should be understood that, with a lift value of 7 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length (16) of the core check matrix corresponding to elements a, b, and c is less than the maximum minimum loop length (18) of the 4x4 core check matrix, and the difference is 2. The values ​​of {ABC} are as follows:

[0219] {0 1 3}, {0 2 6}, {0 3 2}, {0 4 5}, {0 5 1}, or {0 6 4}.

[0220] For example, the lift value corresponding to elements a, b, and c is 8, and the minimum circle length corresponding to this lift value of 8 is 16. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0221] It should be understood that, given a boost value of 8 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length (16) of the core check matrix corresponding to elements a, b, and c is less than the maximum minimum loop length (18) of the 4x4 core check matrix, with a difference of 2. The values ​​of {ABC} are as follows:

[0222] {0 1 3}, {0 1 4}, {0 1 6}, {0 3 1}, {0 3 2}, {0 3 4}, {0 5 4}, {0 5 6}, {0 5 7}, {0 7 2}, {0 7 4}, or {0 7 5}.

[0223] It should be understood that the above describes the minimum loop length for each lift value when the lift value is from the lift value set {4,5,6,7,8,9,10,11,12,13,14,15,16}. Under different lift values, the translation values ​​{ABC} corresponding to elements a, b, and c ensure that the difference between the minimum loop length and the maximum value of the minimum loop length of the core check matrix is ​​less than or equal to 6. Specifically, when the lift value is greater than or equal to 9, the 4x4 core check matrix can reach the maximum value of the minimum loop length, 18.

[0224] It should also be understood that the specific values ​​of {ABC} shown in the above example are examples where the translation values ​​corresponding to the two elements in each column with a column weight of 2 in the first region are exactly the same.

[0225] It should also be understood that the specific values ​​of {A+x B+x C+x} can still satisfy the specific values ​​in the examples above. Suppose that the translation values ​​corresponding to elements a, b, and c are uniformly shifted to the left by x, then adding the shift value x to the translation values ​​{ABC} corresponding to elements a, b, and c respectively to obtain {A+x B+x C+x} will still satisfy any of the values ​​in the examples above, in which case x is a positive integer. Suppose that the translation values ​​corresponding to elements a, b, and c are uniformly shifted to the right by x, then adding the shift value x to the translation values ​​corresponding to elements a, b, and c respectively to obtain {A+x B+x C+x} will still satisfy any of the values ​​in the examples above, in which case x is a negative integer.

[0226] It should also be understood that the specific values ​​of {mod(A+x, y)mod(B+x, y)mod(C+x, y)} can still satisfy the specific values ​​in the above examples. Specifically, when the translation values ​​of elements a, b, and c are greater than the lift value, the modulo operation can be performed on the translation values ​​corresponding to elements a, b, and c. Here, y is the lift value. After performing the modulo operation on the translation values ​​corresponding to elements a, b, and c, the resulting {mod(A+x, y)mod(B+x, y)mod(C+x, y)} still satisfies any of the values ​​in the above examples.

[0227] It should also be understood that Figure 7 above can be a 4x4 core verification matrix obtained after row and column transformation. Here, A, B, and C are the translation values ​​corresponding to elements a, b, and c obtained after the row and column transformation.

[0228] For example, when the two shift values ​​in two overlapping columns of a 4x4 core check matrix are different, add (or subtract) a number to all shift values ​​in the row corresponding to the shift value of one of the elements, making the two shift values ​​in those two overlapping columns the same. By adjusting the overlapping columns in the 4x4 matrix, when the two shift values ​​in each overlapping column are the same, observe whether the three shift values ​​corresponding to the overlapping columns in the 4x4 core check matrix conform to the relationships {ABC}, {A+x B+x C+x}, or {mod(A+x, y)mod(B+x, y)mod(C+x, y)}.

[0229] For example, the core verification matrix with 4 rows and 4 columns is:

[0230] In the aforementioned 4x4 core check matrix, the first column has a 3-column overlap, the third row has a 3-row overlap, and the remaining rows and columns have a 2-column overlap. The shift value corresponding to the position of -1 in the 4x4 core check matrix is ​​0.

[0231] In this 4x4 matrix, the two shift values ​​in each of the two columns are different. The core check matrix is ​​transformed by row and column transformations. For example, if the two shift values ​​in the second column are 17 and 18, to make them the same, the row with a shift value of 18 (row 2) is uniformly subtracted by 1, updating the shift values ​​of row 2 to 17, 20, and the shift values ​​of column 2 to 17, 17. Similarly, if the two shift values ​​in the third column are 20 (updated from 21) and 23, to make them the same, the row with a shift value of 23 (row 3) is uniformly subtracted by 3, updating the shift values ​​of row 3 to B, 20, and 22. Finally, if the two shift values ​​in the fourth column are 22 (updated from 25) and 15, to make them the same, the row with a shift value of 15 (row 4) is uniformly added by 7, updating the shift values ​​of row 4 to C and 22. The updated 4x4 core check matrix is ​​now:

[0232] As can be seen, the two shift values ​​of each column in the two-column weighted matrix of the updated 4x4 core check matrix are the same. At this time, the three shift values ​​of the three-column weighted matrix of the updated 4x4 core check matrix are A, B, and C, and the values ​​of A, B, and C satisfy any one of the values ​​in the example above.

[0233] Example 2:

[0234] Assuming the first region is a 3x3 square matrix, based on the relevant characteristics of the first region described above, Figure 9 shows a schematic diagram of a 3x3 first region.

[0235] It should be understood that the maximum value of the minimum circle length of the 3x3 core check matrix is ​​14.

[0236] As shown in Figure 9, elements a, b, and c are located on the three 1 elements in the only column with a column weight of 3 in the first region, and the translation values ​​corresponding to the 1 elements in the other columns with a column weight of 2 are all the same.

[0237] For example, the lift value corresponding to elements a, b, and c is 8, and the minimum circle length corresponding to this lift value of 8 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0238] It should be understood that, given a lift of 8 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 3x3 core check matrix, which is 14. The values ​​of {A BC} are as follows:

[0239] {0 1 6}, {0 3 2}, {0 5 6}, or {0 7 2}.

[0240] For example, the lift value corresponding to elements a, b, and c is 9, and the minimum circle length corresponding to this lift value of 9 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0241] It should be understood that when the boost value for elements a, b, and c is 9, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 3x3 core check matrix, which is 14. The values ​​of {ABC} are as follows:

[0242] {0 1 3}, {0 1 4}, {0 1 6}, {0 1 7}, {0 2 3}, {0 2 5}, {0 2 6}, {0 2 8}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 3 7}, {0 3 8}, {0 4 1}, {0 4 3}, {0 4 6}, {0 4 7}, {0 5 2}, {0 5 3}, {0 5 6}, {0 5 8}, {0 6 1}, {0 6 2}, {0 6 4}, {0 6 5}, {0 6 7}, {0 6 8}, {0 7 1}, {0 7 3}, {0 7 4} 4}, {0 7 6}, {0 8 2}, {0 8 3}, {0 8 5}, or {0 8 6}.

[0243] For example, the lift value corresponding to elements a, b, and c is 10, and the maximum value of the minimum loop length corresponding to this lift value of 10 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0244] It should be understood that, with a boost value of 10 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 3x3 core check matrix, which is 14. The values ​​of {A BC} are as follows:

[0245] {0 1 4}, {0 1 7}, {0 1 8}, {0 2 9}, {0 3 1}, {0 3 2}, {0 3 4}, {0 4 3}, {0 6 7}, {0 7 6}, {0 7 8}, {0 7 9}, {0 8 1}, {0 9 2}, {0 9 3}, or {0 9 6}.

[0246] For example, the lift value corresponding to elements a, b, and c is 11, and the maximum value of the minimum loop length corresponding to this lift value of 11 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0247] It should be understood that when the boost value for elements a, b, and c is 11, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 3x3 core check matrix, which is 14. The values ​​of {ABC} are as follows:

[0248] {0 1 4}, {0 1 5}, {0 1 8}, {0 1 9}, {0 2 5}, {0 2 7}, {0 2 8}, {0 2 10}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 4 3}, {0 4 5}, {0 4 9}, {0 4 10}, {0 5 1}, {0 5 3}, {0 5 7}, {0 5 9}, {0 6 2}, {0 6 4}, {0 6 8}, {0 6 10}, {0 7 1}, {0 7 2}, {0 7 6}, {0 7 8}, {0 8 6}, {0 8 7}, {0 1 4} {8 9}, {0 8 10}, {0 9 1}, {0 9 3}, {0 9 4}, {0 9 6}, {0 10 2}, {0 10 3}, {0 10 6} or {0 10 7}.

[0249] For example, the lift value corresponding to elements a, b, and c is 12, and the maximum value of the minimum loop length corresponding to this lift value of 12 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0250] It should be understood that, with a lift value of 12 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 3x3 core check matrix, which is 14. The values ​​of {ABC} are as follows:

[0251] {0 1 4}, {0 1 8}, {0 1 10}, {0 2 5}, {0 2 11}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 3 8}, {0 3 10}, {0 5 2}, {0 5 4}, {0 5 8}, {0 7 4}, {0 7 8}, {0 7 10}, {0 9 2}, {0 9 4}, {0 9 7}, {0 9 8}, {0 9 10}, {0 9 11}, {0 10 1}, {0 10 7}, {0 11 2}, {0 11 4} or {0 11 8}.

[0252] For example, the lift value corresponding to elements a, b, and c is 13, and the maximum value of the minimum loop length corresponding to this lift value of 13 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0253] It should be understood that, given a lift value of 13 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 3x3 core check matrix, which is 14. The values ​​of {ABC} are as follows:

[0254] {0 1 4}, {0 1 5}, {0 1 6}, {0 1 9}, {0 1 10}, {0 1 11}, {0 2 5}, {0 2 7}, {0 2 8}, {0 2 9}, {0 2 10}, {0 2 12}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 3 7}, {0 3 12}, {0 4 1}, {0 4 3}, {0 4 5}, {0 4 7}, {0 4 10}, {0 4 11}, {0 5 3}, {0 5 4}, {0 5 6}, {0 5 7}, {0 5 11}, {0 5 6}, {0 5 7}, {0 5 11}, {0 5 6} 12}、{0 6 1}、{0 6 2}、{0 6 4}、{0 6 8}、{0 6 10}、{0 6 11}、{0 7 2}、{0 7 3}、{0 7 5}、{0 7 9}、{0 7 11}、{0 7 12}、{0 8 1}、{0 8 2}、{0 8 6}、{0 8 7}、{0 8 9}、{0 8 10}、{0 9 2}、{0 9 3}、{0 9 6}、{0 9 8}、{0 9 10}、{0 9 12}、{0 10 1}、{0 10 6}、{0 10 8}、{0 10 9}、{0 10 11}, {0 10 12}, {0 11 1}, {0 11 3}, {0 11 4}, {0 11 5}, {0 11 6}, {0 11 8}, {0 12 2}, {0 12 3}, {0 12 4}, {0 12 7}, {0 12 8}, or {0 12 9}.

[0255] For example, the lift value corresponding to elements a, b, and c is 14, and the maximum value of the minimum circle length corresponding to this lift value of 14 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0256] It should be understood that, given a lift value of 14 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 3x3 core check matrix, which is 14. The values ​​of {ABC} are as follows:

[0257] {0 1 4}, {0 1 5}, {0 1 6}, {0 1 9}, {0 1 10}, {0 1 11}, {0 1 12}, {0 2 5}, {0 2 11}, {0 2 13}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 3 8}, {0 3 12}, {0 3 13}, {0 4 1}, {0 4 3}, {0 4 5}, {0 5 2}, {0 5 3}, {0 5 4}, {0 5 6}, {0 5 8}, {0 5 11}, {0 5 13}, {0 6 1}, {0 6 5}, {0 6 11}、{0 8 3}、{0 8 9}、{0 8 13}、{0 9 1}、{0 9 3}、{0 9 6}、{0 9 8}、{0 9 10}、{0 9 11}、{0 9 12}、{0 10 9}、{0 10 11}、{0 10 13}、{0 11 1}、{0 11 2}、{0 11 6}、{0 11 9}、{0 11 10}、{0 11 12}、{0 11 13}、{0 12 1}、{0 12 3}、{0 12 9}、{0 13 2}、{0 13 3}、{0 13 4}、{0 13 5}, {0 13 8}, {0 13 9} or {0 13 10}.

[0258] For example, the lift value corresponding to elements a, b, and c is 15, and the maximum value of the minimum loop length corresponding to this lift value of 15 is 14. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0259] It should be understood that, with a boost value of 15 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length of the core check matrix corresponding to elements a, b, and c is equal to the maximum value of the minimum loop length of a 3x3 core check matrix, which is 14. The values ​​of {ABC} are as follows:

[0260] {0 1 4}, {0 1 5}, {0 1 7}, {0 1 10}, {0 1 12}, {0 1 13}, {0 2 5}, {0 2 8}, {0 2 9}, {0 2 10}, {0 2 11}, {0 2 14}, {0 3 1}, {0 3 2}, {0 3 4}, {0 3 5}, {0 3 7}, {0 3 10}, {0 3 11}, {0 3 14}, {0 4 1}, {0 4 3}, {0 4 5}, {0 4 7}, {0 4 10}, {0 4 13}, {0 6 2}, {0 6 4}, {0 6 5}, {0 6 7}、{0 6 8}、{0 6 10}、{0 6 13}、{0 6 14}、{0 7 1}、{0 7 4}、{0 7 5}、{0 7 9}、{0 7 10}、{0 7 13}、{0 8 2}、{0 8 5}、{0 8 6}、{0 8 10}、{0 8 11}、{0 8 14}、{0 9 1}、{0 9 2}、{0 9 5}、{0 9 7}、{0 9 8}、{0 9 10}、{0 9 11}、{0 9 13}、{0 11 2}、{0 11 5}、{0 11 8}、{0 11 {0 11 12}, {0 11 14}, {0 12 1}, {0 12 4}, {0 12 5}, {0 12 8}, {0 12 10}, {0 12 11}, {0 12 13}, {0 12 14}, {0 13 1}, {0 13 4}, {0 13 5}, {0 13 6}, {0 13 7}, {0 13 10}, {0 14 2}, {0 14 3}, {0 14 5}, {0 14 8}, {0 14 10}, or {0 14 11}.

[0261] For example, the lift value corresponding to elements a, b, and c is 4, and the maximum value of the minimum loop length corresponding to this lift value of 4 is 8. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0262] It should be understood that, with a lift value of 4 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length (8) of the core check matrix corresponding to elements a, b, and c is less than the maximum value (14) of the minimum loop length of the 3x3 core check matrix, and the difference is 6. The values ​​of {ABC} are as follows:

[0263] {0 1 2}, {0 1 3}, {0 1 4}, {0 2 1}, {0 2 3}, {0 3 1}, or {0 3 2}.

[0264] For example, the lift value corresponding to elements a, b, and c is 5, and the maximum value of the minimum circle length corresponding to this lift value of 5 is 10. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0265] It should be understood that, with a boost value of 5 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length (10) of the core check matrix corresponding to elements a, b, and c is less than the maximum value (14) of the minimum loop length of the 3x3 core check matrix, and the difference is 4. The values ​​of {ABC} are as follows:

[0266] {0 1 3}, {0 1 4}, {0 2 1}, {0 2 3}, {0 3 2}, {0 3 4}, {0 4 1}, or {0 4 2}.

[0267] For example, the lift value corresponding to elements a, b, and c is 6, and the maximum value of the minimum loop length corresponding to this lift value of 6 is 12. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0268] It should be understood that, with a lift value of 6 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length (12) of the core check matrix corresponding to elements a, b, and c is less than the maximum minimum loop length (14) of the 3x3 core check matrix, and the difference is 2. The values ​​of {ABC} are as follows:

[0269] {0 1 3}, {0 2 3}, {0 4 3}, or {0 5 3}.

[0270] For example, the lift value corresponding to elements a, b, and c is 7, and the maximum value of the minimum loop length corresponding to this lift value of 7 is 12. The translation values ​​corresponding to elements a, b, and c are A, B, and C, respectively, where A, B, and C are all integers.

[0271] It should be understood that, with a lift value of 7 for elements a, b, and c, the value of {ABC} ensures that the minimum loop length (12) of the core check matrix corresponding to elements a, b, and c is less than the maximum minimum loop length (14) of the 3x3 core check matrix, and the difference is 2. The values ​​of {ABC} are as follows:

[0272] {0 1 3}, {0 1 5}, {0 2 3}, {0 2 6}, {0 3 1}, {0 3 2}, {0 4 5}, {0 4 6}, {0 5 1}, {0 5 4}, {0 6 2}, or {0 6 4}.

[0273] It should be understood that the above describes the maximum value of the minimum loop length corresponding to each lift value when the lift value is from the lift value set {4,5,6,7,8,9,10,11,12,13,14,15}. Under different lift values, the specific values ​​of the translation values ​​{ABC} corresponding to elements a, b, and c that ensure the minimum loop length of the core check matrix corresponding to the translation value {ABC} is equal to the maximum value of the minimum loop length corresponding to different lift values ​​are described.

[0274] It should also be understood that the specific values ​​of {ABC} shown in the above example are examples where the translation values ​​corresponding to the two elements in each column with a column weight of 2 in the first region are exactly the same.

[0275] It should also be understood that the specific values ​​of {A+x B+x C+x} can still satisfy the specific values ​​in the examples above. Suppose that the translation values ​​corresponding to elements a, b, and c are uniformly shifted to the left by x, then adding the shift value x to the translation values ​​{ABC} corresponding to elements a, b, and c respectively to obtain {A+x B+x C+x} will still satisfy any of the values ​​in the examples above, in which case x is a positive integer. Suppose that the translation values ​​corresponding to elements a, b, and c are uniformly shifted to the right by x, then adding the shift value x to the translation values ​​corresponding to elements a, b, and c respectively to obtain {A+x B+x C+x} will still satisfy any of the values ​​in the examples above, in which case x is a negative integer.

[0276] It should also be understood that the specific values ​​of {mod(A+x, y)mod(B+x, y)mod(C+x, y)} can still satisfy the specific values ​​in the above examples. Specifically, when the translation values ​​of elements a, b, and c are greater than their lift values, the modulo operation can be performed on the translation values ​​corresponding to elements a, b, and c. Here, y is the lift value in the lift value set. After performing the modulo operation on the translation values ​​corresponding to elements a, b, and c, the resulting {mod(A+x, y)mod(B+x, y)mod(C+x, y)} still satisfies any of the values ​​in the above examples.

[0277] It should also be understood that Figure 8 above can be a square matrix obtained after row and column transformations. Here, A, B, and C are the translation values ​​corresponding to elements a, b, and c obtained after the row and column transformations.

[0278] Specifically, when the two shift values ​​in two columns of a 3x3 core check matrix are different, all shift values ​​of the row weight corresponding to the shift value of one element are incremented (or decremented) by a number to make the two shift values ​​in the two column weights the same. By adjusting the two column weights in the 3x3 core check matrix, when the two shift values ​​in each pair of the two column weights are the same, observe whether the three shift values ​​corresponding to the three column weights in the 3x3 core check matrix conform to the relationships {ABC}, {A+x B+x C+x}, or {mod(A+x, y)mod(B+x, y)mod(C+x, y)}. Similar to the 4x4 core check matrix described above, please refer to the exemplary description above; it will not be repeated here.

[0279] S630: The transmitting device encodes the information bit sequence according to the LDPC parity check matrix to obtain the codeword sequence.

[0280] S640, the transmitting device sends a codeword sequence to the receiving device. Correspondingly, the receiving device receives the codeword sequence from the transmitting device.

[0281] It should be noted that, since channel noise may be introduced during the transmission of the codeword sequence, the LDPC codeword sequence output or transmitted by the transmitting device may be different from the LDPC codeword sequence received by the receiving device.

[0282] In S650, the receiving device decodes the codeword sequence according to the LDPC parity check matrix to obtain the information bit sequence.

[0283] The LDC parity check matrix used for decoding by the receiving device is the same as the LDPC parity check matrix used for encoding by the sending device. The specific method by which the receiving device determines the LDPC parity check matrix can be found in the description on the sending device side, and will not be detailed here.

[0284] This scheme achieves the following: in the lift value set, the minimum circle length of the core parity check matrix corresponding to the translation values ​​of elements a, b, and c is the maximum value of the minimum circle length corresponding to the lift value in the lift value set, ensuring that the circle length of the LDPC base map is the maximum value of the minimum circle length, thereby improving the encoding and decoding performance of LDPC codes.

[0285] Optionally, in this application, a generator matrix can be determined first, and the information bit sequence can be LDPC encoded based on the generator matrix. The method for determining the generator matrix is ​​the same as that proposed in this application, and will not be repeated here.

[0286] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0287] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0288] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0289] The method embodiments provided in this application have been described in detail above with reference to Figures 1 to 9. The apparatus embodiments of this application will be described below with reference to Figures 10 and 11. It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 9 and 10 include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0290] Figures 10 and 11 are schematic diagrams of possible apparatus structures provided in embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0291] Figure 10 is a schematic block diagram of a communication device 1000 provided in an embodiment of this application. As shown in Figure 10, the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used for data processing. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0292] In one possible design, the device 1000 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 1020 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 1010 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0293] In another possible design, the device 1000 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 1010 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1020 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0294] It is understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 1000 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 1000 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0295] The apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0296] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In the embodiments of this application, the device in FIG10 can be the receiving end device or transmitting end device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitations are imposed here.

[0297] Figure 11 is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is used to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0298] Optionally, the device 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 stores instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0299] Optionally, the memory 1130 may be integrated into the processor 1110.

[0300] In one possible scenario, device 1100 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0301] It is understood that the device 1100 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 1120 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 1100 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0302] Optionally, the memory 1130 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be used to execute instructions stored in the memory, and when the processor 1110 executes instructions stored in the memory, the processor 1110 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0303] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0304] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0305] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0306] Optionally, the memory (e.g., 1030) in this embodiment may be integrated into the processor (e.g., 1010).

[0307] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0308] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0309] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0310] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0311] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0312] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0313] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0314] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0315] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0316] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0317] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the information bit sequence; The LDPC parity check matrix is ​​determined, wherein the LDPC core parity check matrix is ​​determined based on the LDPC base graph, and the base graph includes a first region, which consists of the core rows and core parity columns corresponding to the base graph. The first region has exactly one column with a column weight of 3 and exactly one row with a row weight of 3. All columns in the first region except for the column with a column weight of 3 have a column weight of 2. All rows in the first region except for the row with a row weight of 3 have a row weight of 2. In the column with a column weight of 2, the two elements in each column have the same shift value. Wherein, the column weight of column j in the first region is 3, and column j includes element a corresponding to row i1 and column j, element b corresponding to row i2 and column j, and element c corresponding to row i3 and column j. The row weight of row i2 is 3. In the lift value set, the difference between the minimum circle length of the core check matrix corresponding to the translation value of element a, element b, and element c and the maximum value of the minimum circle length of the core check matrix is ​​less than or equal to 6. The lift value set includes {4,5,6,7,8,9,10,11,12,13,14,15,16}. The information bit sequence is encoded according to the LDPC parity check matrix to obtain a codeword sequence; Output the codeword sequence.

2. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the codeword sequence; The LDPC parity-check matrix is ​​determined, wherein the LDPC core parity-check matrix is ​​determined based on the LDPC base graph. The base graph includes a first region, which consists of the core rows and core parity columns corresponding to the LDPC base graph. The first region has exactly one column with a column weight of 3 and exactly one row with a row weight of 3. All columns in the first region except for the column with a column weight of 3 have a column weight of 2. All rows in the first region except for the row with a row weight of 3 have a row weight of 2. In the column with a column weight of 2, the two elements in each column have the same shift value. Wherein, the column weight of column j in the first region is 3, and column j includes element a corresponding to row i1 and column j, element b corresponding to row i2 and column j, and element c corresponding to row i3 and column j. The row weight of row i2 is 3. In the lift value set, the minimum circle length of the core check matrix corresponding to the translation values ​​of elements a, b, and c is less than or equal to 6 compared with the maximum value of the minimum circle length of the core check matrix. The lift value set includes {4,5,6,7,8,9,10,11,12,13,14,15,16}. The codeword sequence is decoded according to the LDPC parity check matrix to obtain the information bit sequence.

3. The method according to claim 1 or 2, characterized in that, The lift value is 9 in the set of lift values, and the minimum loop length corresponding to the lift value is 18. The translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 3 1}, {0 3 4}, {0 3 1}, {0 3 7}, {0 6 2}, {0 6 5}, or {0 6 8}, Wherein, A, B, C and x are all integers, y is a positive integer, and y is 9 in the set of boost values.

4. The method according to claim 1 or 2, characterized in that, The lift value is 10 from the set of lift values, and the minimum loop length corresponding to the lift value is 18. The translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 7}、{0 1 8}、{0 2 9}、{0 3 1}、{0 3 4}、{0 4 3}、{0 6 7}、{0 7 6}、{0 7 9}、{0 8 1}、{0 9 2}、 Or {0 9 3}, Wherein, A, B, C and x are all integers, y is a positive integer, and y is 10 in the set of boost values.

5. The method according to claim 1 or 2, characterized in that, The lift value is 11 in the set of lift values, and the minimum loop length corresponding to the lift value is 18. The translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}、{0 1 5}、{0 1 9}、{0 2 7}、{0 2 8}、{0 2 10}、{0 3 1}、{0 3 4}、{0 3 5}、{0 4 3}、{0 4 5}、 {0 4 9}, {0 5 1}, {0 5 3}, {0 5 9}, {0 6 2}, {0 6 8}, {0 6 10}, {0 7 2}, {0 7 6}, {0 7 8}, {0 8 6}, {0 8 7}, {0 8 10}, {0 9 1}, {0 9 3}, {0 9 4}, {0 10 2}, {0 10 6} or {0 10 7}, Wherein, A, B, C, and x are all integers, y is a positive integer, and y is 11 in the set of boost values.

6. The method according to claim 1 or 2, characterized in that, The lift value is 12 from the set of lift values, and the minimum loop length corresponding to the lift value is 18. The translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 8}、{0 3 1}、{0 3 4}、{0 3 5}、{0 3 8}、{0 4 3}、{0 4 5}、{0 4 9}、{0 4 11}、{0 5 4}、{0 7 8}、 {0 8 1}, {0 8 3}, {0 8 7}, {0 8 9}, {0 9 4}, {0 9 7}, {0 9 8}, {0 9 11} or {0 11 4}, Wherein, A, B, C and x are all integers, y is a positive integer, and y is 12 in the set of boost values.

7. The method according to claim 1 or 2, characterized in that, The lift value is 13 from the set of lift values, and the minimum loop length corresponding to the lift value is 18. The translation value corresponding to element a is A, the translation value corresponding to element b is B, and the translation value corresponding to element c is C. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}、{0 1 6}、{0 1 9}、{0 1 10}、{0 1 11}、{0 2 5}、{0 2 7}、{0 2 8}、{0 2 9}、{0 2 12}、{0 3 1}、{0 3 4}、{0 3 5}、{0 3 7}、{0 3 12}、{0 4 1}、{0 4 3}、{0 4 5}、{0 4 10}、{0 4 11}、{0 5 3}、{0 5 4}、{0 5 6}、{0 5 7}、{0 5 11}、{0 6 1}、{0 6 2}、{0 6 8}、{0 6 10}、{0 6 11}、{0 7 2}、{0 7 3}、{0 7 5}、{0 7 11}、{0 7 12}、{0 8 2}、{0 8 6}、{0 8 7}、{0 8 9}、{0 8 {0 9 2}, {0 9 3}, {0 9 8}, {0 9 10}, {0 9 12}, {0 10 1}, {0 10 6}, {0 10 8}, {0 10 9}, {0 10 12}, {0 11 1}, {0 11 4}, {0 11 5}, {0 11 6}, {0 11 8}, {0 12 2}, {0 12 3}, {0 12 4}, {0 12 7} or {0 12 9} Wherein, A, B, C and x are all integers, y is a positive integer, and y is 13 in the set of boost values.

8. The method according to claim 1 or 2, characterized in that, The lift value is 14 from the set of lift values, and the minimum loop length corresponding to the lift value is 18. The translation value A corresponding to element a, the translation value B corresponding to element b, and the translation value C corresponding to element c. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 6}、{0 1 9}、{0 1 11}、{0 1 12}、{0 2 5}、{0 2 11}、{0 2 13}、{0 3 1}、{0 3 4}、{0 3 5}、{0 3 8}、{0 3 12}、{0 3 13}、{0 4 1}、{0 4 3}、{0 4 5}、{0 5 2}、{0 5 3}、{0 5 4}、{0 5 6}、{0 5 11}、{0 5 13}、{0 6 1}、{0 6 5}、{0 6 11}、{0 8 3}、{0 8 9}、{0 8 13}、{0 9 1}、{0 9 3}、{0 9 8}、{0 9 10}、{0 9 11}、{0 9 12}、{0 10 9}、{0 10 11}、{0 10 13}、{0 11 1}、{0 11 2}、{0 {11 6}, {0 11 9}, {0 11 10}, {0 11 13}, {0 12 1}, {0 12 3}, {0 12 9}, {0 13 2}, {0 13 3}, {0 13 5}, {0 13 8}, {0 13 9}, or {0 13 10}. Wherein, A, B, C and x are all integers, y is a positive integer, and y is 14 in the set of boost values.

9. The method according to claim 1 or 2, characterized in that, The lift value is 15 from the set of lift values, and the minimum loop length corresponding to the lift value is 18. The translation value A corresponding to element a, the translation value B corresponding to element b, and the translation value C corresponding to element c. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}、{0 1 5}、{0 1 7}、{0 1 10}、{0 1 12}、{0 1 13}、{0 2 5}、{0 2 8}、{0 2 9}、{0 2 10}、{0 2 11}、{0 2 14}、{0 3 1}、{0 3 4}、{0 3 5}、{0 3 10}、{0 3 11}、{0 3 14}、{0 4 1}、{0 4 3}、{0 4 5}、{0 4 7}、{0 4 10}、{0 4 13}、{0 5 1}、{0 5 2}、{0 5 3}、{0 5 4}、{0 5 6}、{0 5 7}、{0 5 8}、{0 5 9}、{0 5 11}、{0 5 12}、{0 5 13}、{0 5 14}、{0 6 2}、{0 6 5}、{0 6 7}、{0 6 8}、{0 6 10}、{0 6 13}、{0 7 1}、{0 7 4}、{0 7 5}、{0 7 9}、{0 7 10}、{0 7 13}、{0 8 2}、{0 8 5}、{0 8 6}、{0 8 10}、{0 8 11}、{0 8 14}、{0 9 2}、{0 9 5}、{0 9 7}、{0 9 8}、{0 9 10}、{0 9 13}、{0 10 1}、{0 10 2}、{0 10 3}、{0 10 4}、{0 10 6}、{0 10 7}、{0 10 8}、{0 10 9}、{0 10 11}、{0 10 12}、{0 10 13}、{0 10 14}、{0 11 2}、{0 11 5}、{0 11 8}、{0 11 10}、{0 11 12}、{0 11 14}、{0 12 1}、{0 12 4}、{0 12 5}、{0 12 10}、{0 12 11}、{0 12 14}、{0 13 1}、{0 13 4}、{0 13 5}、{0 13 6}、{0 13 7}、{0 13 10}、{0 14 2}、{0 14 3}、{0 14 5}、{0 14 8}, {0 14 10}, or {0 14 11} Wherein, A, B, C and x are all integers, y is a positive integer, and y is 15 in the set of boost values.

10. The method according to claim 1 or 2, characterized in that, The lift value is 16 from the set of lift values, and the minimum loop length corresponding to the lift value is 18. The translation value A corresponding to element a, the translation value B corresponding to element b, and the translation value C corresponding to element c. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}、{0 1 7}、{0 1 10}、{0 1 11}、{0 1 12}、{0 1 14}、{0 2 5}、{0 2 7}、{0 2 13}、{0 2 15}、{0 {3 1}, {0 3 4}, {0 3 5}, {0 3 10}, {0 3 12}, {0 3 14}, {0 4 1}, {0 4 3}, {0 4 5}, {0 4 7}, {0 4 9}, {0 4 11}, {0 4 13}, {0 4 15}, {0 5 2}, {0 5 3}, {0 5 4}, {0 5 6}, {0 5 7}, {0 5 12}, {0 6 5}, {0 6 7}, {0 6 13}, {0 6 15}, {0 7 1}, {0 7 2}, {0 7 4}, {0 7 6}, {0 7 12}, {0 7 2}, {0 7 4}, {0 7 6}, {0 7 12}, {0 7 2} 13}、{0 9 3}、{0 9 4}、{0 9 10}、{0 9 12}、{0 9 14}、{0 9 15}、{0 10 1}、{0 10 3}、{0 10 9}、{0 10 11}、{0 11 4}、{0 11 9}、{0 11 10}、{0 11 12}、{0 11 13}、{0 11 14}、{0 12 1}、{0 12 3}、{0 12 5}、{0 12 7}、{0 12 9}、{0 12 11}、{0 12 13}、{0 12 15}、{0 13 2}、{0 13 4}, {0 13 6}, {0 13 11}, {0 13 12}, {0 13 15}, {0 14 1}, {0 14 3}, {0 14 9}, {0 14 11}, {0 15 2}, {0 15 4}, {0 15 5}, {0 15 6}, {0 15 9}, or {0 15 12}, Wherein, A, B, C and x are all integers, y is a positive integer, and y is 16 in the set of boost values.

11. The method according to claim 1 or 2, characterized in that, The lift value is 4 in the set of lift values, and the minimum loop length corresponding to the lift value is 12. The translation value A corresponding to element a, the translation value B corresponding to element b, and the translation value C corresponding to element c. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 2 1} or {0 2 3}, Wherein, A, B, C and x are all integers, y is a positive integer, and y is 4 in the set of boost values.

12. The method according to claim 1 or 2, characterized in that, The lift value is 5 in the set of lift values, and the minimum loop length corresponding to the lift value is 14. The translation value A corresponding to element a, the translation value B corresponding to element b, and the translation value C corresponding to element c. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 4}, {0 2 3}, {0 3 2}, or {0 4 1}, Wherein, A, B, C and x are all integers, y is a positive integer, and y is 5 in the set of boost values.

13. The method according to claim 1 or 2, characterized in that, The lift value is 6 in the set of lift values, and the maximum value of the minimum loop length corresponding to the lift value is 14. The translation value A corresponding to element a, the translation value B corresponding to element b, and the translation value C corresponding to element c. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 2 3} or {0 4 3}, Wherein, A, B, C and x are all integers, y is a positive integer, and y is 6 in the set of boost values.

14. The method according to claim 1 or 2, characterized in that, The lift value is 7 in the set of lift values, and the minimum loop length corresponding to the lift value is 16. The translation value A corresponding to element a, the translation value B corresponding to element b, and the translation value C corresponding to element c. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 3}, {0 2 6}, {0 3 2}, {0 4 5}, {0 5 1}, or {0 6 4}, Wherein, A, B, C and x are all integers, y is a positive integer, and y is 7 in the set of boost values.

15. The method according to claim 1 or 2, characterized in that, The lift value is 8 from the set of lift values, and the minimum loop length corresponding to the lift value is 16. The translation value A corresponding to element a, the translation value B corresponding to element b, and the translation value C corresponding to element c. Where, the values ​​of {ABC}, {A+x B+x C+x} or {mod(A+x,y)mod(B+x,y)mod(C+x,y)} are: {0 1 3}、{0 1 4}、{0 1 6}、{0 3 1}、{0 3 2}、{0 3 4}、{0 5 4}、{0 5 6}、{0 5 7}、{0 7 2}、{0 7 4}、 Or {0 7 5}, Wherein, A, B, C and x are all integers, y is a positive integer, and y is 8 in the set of boost values.

16. A communication device, characterized in that, The device includes at least one processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, the processor causing the method as described in any one of claims 1 to 15 to be implemented via logic circuits or executing code instructions.

17. The communication device according to claim 16, characterized in that, The communication device is a chip or chip system.

18. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, cause the method as described in any one of claims 1 to 15 to be implemented.

19. A computer program product, characterized in that, Includes a computer program that, when run, causes the method as described in any one of claims 1 to 15 to be implemented.

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