Storage device

Abstract

Provided is a novel storage device. According to the present invention, each of a gate of a first transistor, an output terminal of a first buffer, and a first terminal of a second transistor is connected to a word line, a first terminal of a third transistor is connected to a first power supply terminal of the first buffer, a first terminal of a fourth transistor is connected to a second power supply terminal of the first buffer, a gate of the second transistor is connected to an output terminal of an inverter, a gate of the third transistor is connected to an output terminal of a second buffer, a gate of the fourth transistor is connected to the output terminal of the inverter, and the inverter has a function that outputs a signal obtained by inverting a logical value of a signal outputted from the second buffer.

Description

storage device

[0001] One aspect of the present invention relates to a storage device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. More specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, systems including these devices, and driving methods or manufacturing methods thereof.

[0003] It is known that a transistor including an oxide semiconductor in a channel formation region has an extremely small off-state current. For example, Patent Document 1 discloses a low-power processing unit (e.g., a CPU) that utilizes the low off-state current of the transistor. Furthermore, Patent Document 2 discloses a storage device (e.g., a main memory, a cache memory, etc.) that can store data for a long period of time by utilizing the low off-state current of the transistor.

[0004] Furthermore, for example, Patent Document 3 discloses a technique for increasing the density of an integrated circuit by stacking the transistors.

[0005] It is also known that the electrical characteristics of an OS transistor change little when irradiated with radiation. For example, Patent Document 4 discloses evaluation results showing that when an OS transistor is irradiated with radiation, the change in the subthreshold slope is small, the change in the field-effect mobility is small, and an extremely small off-state current is maintained.

[0006] JP 2012-257187 A JP 2011-151383 A International Publication No. 2021 / 053473 International Publication No. 2023 / 180849

[0007] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] An object of one embodiment of the present invention is to provide a highly reliable storage device.An object of one embodiment of the present invention is to provide a storage device with low power consumption.An object of one embodiment of the present invention is to provide a miniaturized storage device.An object of one embodiment of the present invention is to provide a storage device with high operation speed.An object of one embodiment of the present invention is to provide a novel storage device.An object of one embodiment of the present invention is to provide a method for driving the storage device.

[0009] The above-mentioned problem does not preclude the existence of other problems. A person skilled in the art can naturally derive other problems from the description in this specification, drawings, claims, etc., and can extract other problems from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily solve all of these problems (the above-mentioned problem and other problems).

[0010] (1) One aspect of the present invention provides a memory cell and a driver, wherein the memory cell includes a first transistor and a storage unit, and the driver includes a first buffer, a second buffer, an inverter, a second transistor, and a third transistor, wherein a first terminal of the first transistor is electrically connected to the storage unit, a second terminal of the first transistor is electrically connected to a bit line, a gate of the first transistor is electrically connected to a word line, an output terminal of the first buffer is electrically connected to the word line, a first terminal of the second transistor is electrically connected to the word line, a gate of the second transistor is electrically connected to an output terminal of the inverter or an output terminal of the second buffer, and a second terminal of the second transistor is electrically connected to the bit line. the terminal is electrically connected to a first power supply line or a second power supply line, the gate of the third transistor is electrically connected to an output terminal of the second buffer or an output terminal of the inverter, the third transistor has a function of controlling the supply of a signal from the output terminal of the first buffer to the word line, the first power supply terminal of the first buffer, the first power supply terminal of the second buffer, and the first power supply terminal of the inverter are each electrically connected to the first power supply line, the second power supply terminal of the first buffer, the second power supply terminal of the second buffer, and the second power supply terminal of the inverter are each electrically connected to the second power supply line, and the inverter has a function of outputting a signal obtained by inverting the logical value of a signal output from the second buffer.

[0011] (2) In the above (1), each of the first to third transistors may be an n-channel transistor, the gate of the second transistor may be electrically connected to an output terminal of the inverter, the second terminal of the second transistor may be electrically connected to a first power supply line, and the gate of the third transistor may be electrically connected to an output terminal of the second buffer, and the potential applied to the second power supply line may be higher than the potential applied to the first power supply line.

[0012] (3) In the above (1) or (2), at least one of the first to third transistors may include an oxide semiconductor in a channel formation region.

[0013] (4) One aspect of the present invention includes a memory cell and a driver. The memory cell includes a first transistor and a storage unit. The driver includes a first buffer, a second buffer, an inverter, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor is electrically connected to the storage unit. A second terminal of the first transistor is electrically connected to a bit line. A gate of the first transistor is electrically connected to a word line. An output terminal of the first buffer is electrically connected to the word line. A first terminal of the second transistor is electrically connected to the word line. A first terminal of the third transistor is electrically connected to a first power supply terminal of the first buffer. A first terminal of the fourth transistor is electrically connected to a second power supply terminal of the first buffer. a gate of the third transistor electrically connected to the output terminal of the second buffer, a gate of the fourth transistor electrically connected to the output terminal of the inverter or the output terminal of the second buffer, a second terminal of the second transistor electrically connected to a first power supply line or a second power supply line, the second terminal of the third transistor, the first power supply terminal of the second buffer, and the first power supply terminal of the inverter each electrically connected to the first power supply line, the second terminal of the fourth transistor, the second power supply terminal of the second buffer, and the second power supply terminal of the inverter each electrically connected to the second power supply line, and the inverter has a function of outputting a signal obtained by inverting the logical value of a signal output from the second buffer.

[0014] (5) In the above (4), each of the first to third transistors may be an n-channel transistor, the fourth transistor may be a p-channel transistor, the gate of the second transistor may be electrically connected to an output terminal of the inverter, the gate of the fourth transistor may be electrically connected to the output terminal of the inverter, the second terminal of the second transistor may be electrically connected to a first power supply line, and the potential applied to the second power supply line may be higher than the potential applied to the first power supply line.

[0015] (6) In the above (4) or (5), at least one of the first to third transistors may include an oxide semiconductor in a channel formation region.

[0016] (7) One aspect of the present invention includes a memory cell and a driver. The memory cell includes a first transistor and a storage unit. The driver includes a first buffer, a second buffer, an inverter, a second transistor, and a third transistor. A first terminal of the first transistor is electrically connected to the storage unit. A second terminal of the first transistor is electrically connected to a bit line. A gate of the first transistor is electrically connected to a word line. A first terminal of the second transistor is electrically connected to the word line. A first terminal of the third transistor is electrically connected to the word line. A second terminal of the third transistor is electrically connected to an output terminal of the first buffer. A gate of the second transistor is electrically connected to the inverter. a gate of the third transistor electrically connected to an output terminal of the second buffer or an output terminal of the inverter; a second terminal of the second transistor electrically connected to a first power supply line or a second power supply line; a first power supply terminal of the first buffer, a first power supply terminal of the second buffer, and a first power supply terminal of the inverter each electrically connected to the first power supply line; a second power supply terminal of the first buffer, a second power supply terminal of the second buffer, and a second power supply terminal of the inverter each electrically connected to the second power supply line; and the inverter has a function of outputting a signal obtained by inverting the logical value of a signal output from the second buffer.

[0017] (8) In the above (7), each of the first to third transistors may be an n-channel transistor, the gate of the second transistor may be electrically connected to an output terminal of the inverter, the gate of the third transistor may be electrically connected to an output terminal of the second buffer, the second terminal of the second transistor may be electrically connected to a first power supply line, and the potential applied to the second power supply line may be higher than the potential applied to the first power supply line.

[0018] (9) In the above (7) or (8), at least one of the first to third transistors may include an oxide semiconductor in a channel formation region.

[0019] (10) In the memory device described in (1), the gate of the second transistor is electrically connected to an output terminal of the inverter, the second terminal of the second transistor is electrically connected to a first power supply line, the gate of the third transistor is electrically connected to an output terminal of the second buffer, a potential applied to the second power supply line is higher than a potential applied to the first power supply line, the first transistor includes a first oxide semiconductor in a channel formation region, and each of the second transistor and the third transistor includes a second oxide semiconductor in a channel formation region.

[0020] (11) In the above (10), each of the first oxide semiconductor and the second oxide semiconductor may contain indium, and the indium content in the second oxide semiconductor may be higher than the indium content in the first oxide semiconductor.

[0021] (12) In the above (10), the off-current of the first transistor may be smaller than the off-current of the third transistor, and the field-effect mobility of the third transistor may be higher than the field-effect mobility of the first transistor.

[0022] (13) In the memory device described in (4), a gate of the second transistor is electrically connected to an output terminal of the inverter, a gate of the third transistor is electrically connected to an output terminal of the second buffer, a gate of the fourth transistor is electrically connected to the output terminal of the inverter, a second terminal of the second transistor is electrically connected to a first power supply line, a potential applied to the second power supply line is higher than a potential applied to the first power supply line, the first transistor includes a first oxide semiconductor in a channel formation region, and each of the second transistor and the third transistor includes a second oxide semiconductor in a channel formation region.

[0023] (14) In the above (13), each of the first oxide semiconductor and the second oxide semiconductor may contain indium, and the indium content in the second oxide semiconductor may be higher than the indium content in the first oxide semiconductor.

[0024] (16) In the above (13), the off-current of the first transistor may be smaller than the off-current of the third transistor, and the field-effect mobility of the third transistor may be higher than the field-effect mobility of the first transistor.

[0025] (16) In the memory device described in (7), the gate of the second transistor is electrically connected to an output terminal of the inverter, the gate of the third transistor is electrically connected to an output terminal of the second buffer, the second terminal of the second transistor is electrically connected to a first power supply line, a potential applied to the second power supply line is higher than a potential applied to the first power supply line, the first transistor includes a first oxide semiconductor in a channel formation region, and each of the second transistor and the third transistor includes a second oxide semiconductor in a channel formation region.

[0026] (17) In the above (16), each of the first oxide semiconductor and the second oxide semiconductor may contain indium, and the indium content in the second oxide semiconductor may be higher than the indium content in the first oxide semiconductor.

[0027] (18) In the above (16), the off-current of the first transistor may be smaller than the off-current of the third transistor, and the field-effect mobility of the third transistor may be higher than the field-effect mobility of the first transistor.

[0028] According to one embodiment of the present invention, a highly reliable storage device can be provided. According to one embodiment of the present invention, a storage device with low power consumption can be provided. According to one embodiment of the present invention, a miniaturized storage device can be provided. According to one embodiment of the present invention, a storage device with high operating speed can be provided. According to one embodiment of the present invention, a novel storage device can be provided. According to one embodiment of the present invention, a driving method of the storage device can be provided.

[0029] Note that the above-described effects do not preclude the existence of other effects. A person skilled in the art can naturally derive other effects from the description in this specification, drawings, claims, etc., and can extract other effects from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not necessarily have all of these effects (the above-described effects and other effects).

[0030] FIG. 1 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 2 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 3 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 4 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 5 is a circuit diagram illustrating an example of the configuration of a memory device. FIGS. 6A and 6C are circuit diagrams illustrating an example of the configuration of a memory device. FIGS. 6B and 6D are circuit symbols illustrating an example of the configuration of a memory device. FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 7G, and 7H are circuit diagrams illustrating an example of the configuration of a memory cell. FIG. 8 is a schematic diagram illustrating an example of the configuration of a memory device. FIG. 9 is a schematic diagram illustrating an example of the configuration of a memory device. FIG. 10 is a timing chart illustrating an example of the operation of a memory device. FIG. 11 is a circuit diagram illustrating an example of the operation of a memory device. FIG. 12 is a circuit diagram illustrating an example of the operation of a memory device. FIG. 13 is a circuit diagram illustrating an example of the operation of a memory device. FIG. 14 is a circuit diagram illustrating an example of the operation of a memory device. FIG. 15 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 16 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 17 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 18 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 19 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 20 is a circuit diagram illustrating an example of the operation of a memory device. FIG. 21 is a circuit diagram illustrating an example of the operation of a memory device. FIG. 22 is a circuit diagram illustrating an example of the operation of a memory device. FIG. 23 is a circuit diagram illustrating an example of the operation of a memory device. FIG. 24 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 25 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 26 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 27 is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 28A is a circuit diagram illustrating an example of the configuration of a memory device. FIG. 28B is a circuit symbol illustrating an example of the configuration of a memory device. FIG. 29 is a schematic diagram illustrating an example of the configuration of a memory device. FIGS. 30A and 30B are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIG. 31A is a top view illustrating an example of the configuration of a semiconductor device. FIGS. 31B, 31C, and 31D are cross-sectional views illustrating an example of the configuration of a semiconductor device. FIG. 32 is a cross-sectional view illustrating an example of the configuration of a semiconductor device.

[0047] Figures 33A, 33B, and 33C are cross-sectional views illustrating an example of the configuration of a semiconductor device. Figure 34 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. Figures 35A and 35B are views illustrating the carrier concentration dependence of Hall mobility. Figure 35C is a cross-sectional view illustrating an indium oxide film. Figure 36 is a view showing various memory devices by layer. Figures 37A and 37B are views illustrating an example of an electronic component. Figures 38A and 38B are views illustrating an example of an electronic device. Figures 38C, 38D, and 38E are views illustrating an example of a mainframe computer. Figure 39A is a view illustrating an example of space equipment. Figure 39B is a view illustrating an example of a storage system applicable to a data center. Figures 39C and 39D are views illustrating an example of an electronic device. 40A1, 40A2, 40A3, 40A4, 40A5, 40A6, 40A7 and 40B1, 40B2, 40B3, 40B4, 40B5, 40B6 are diagrams for explaining electrical connections.

[0031] In this specification, a semiconductor device refers to a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode), or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. Examples of semiconductor devices include electronic circuits including semiconductor elements, chips equipped with electronic circuits, electronic components with chips housed in packages, and electronic devices equipped with electronic components. Furthermore, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, projection devices, electro-optical devices, light-receiving devices, detection devices, power supply devices, communication devices, information processing devices, arithmetic units, control devices, memory devices, input devices, output devices, input / output devices, signal processing devices, arithmetic processing devices, electronic computers, and electronic devices may themselves be semiconductor devices and may also include semiconductor devices.

[0032] The following description of the embodiments will be given with reference to the drawings. However, the embodiments can be implemented in many different forms. Therefore, it will be readily understood by those skilled in the art that various changes can be made to the embodiments and their details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0033] In this specification and the like, the configuration shown in each embodiment can be appropriately combined with the configuration shown in another embodiment to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0034] In addition, in the drawings illustrating the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, thereby omitting repeated description thereof. Furthermore, when the drawings indicate similar functions, for example, the same hatching patterns may be used and no particular reference numerals may be used. Furthermore, in the drawings, for example, in perspective views or top views (also called "plan views"), the illustration of some components may be omitted for ease of understanding. Furthermore, in the drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0035] In addition, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. The drawings are schematic illustrations to facilitate understanding of the present invention and are not limited to, for example, the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by processes such as etching. However, these may not be reflected in the drawings to facilitate understanding. Furthermore, for example, in actual circuit operation, variations in voltage or current may occur due to noise or timing errors. However, these may not be reflected in the drawings to facilitate understanding.

[0036] Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, it may be difficult to separate components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings may not be limited to the descriptions therein, and may be rephrased appropriately.

[0037] Furthermore, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". Furthermore, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the elements may be described without the identifying symbol.

[0038] In this specification and the like, the "conductive state" or "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor are considered to be electrically short-circuited, or a state in which a current can flow between the source and drain (also referred to as a state in which a current can flow). For example, a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage, may be referred to as the "conductive state" or "on state." In addition, the "non-conductive state," "cutoff state," or "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically cut off. For example, a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage, may be referred to as the "non-conductive state," "cutoff state," or "off state."

[0039] In this specification and the like, the voltage between the gate and the source (gate-source) (based on the source potential unless otherwise specified) may be referred to as the "gate voltage," the voltage between the drain and the source (drain-source) (based on the source potential unless otherwise specified) may be referred to as the "drain voltage," and the voltage between the backgate and the source (backgate-source) (based on the source potential unless otherwise specified) may be referred to as the "backgate voltage." Furthermore, the current flowing between the drain and the source (positive in the direction from the drain to the source unless otherwise specified) may be referred to as the "drain current." Note that, in an n-channel transistor, terms such as "high gate voltage," "high drain voltage," and "high backgate voltage" can be interchangeable with terms such as "low gate voltage," "low drain voltage," and "low backgate voltage" in a p-channel transistor, as appropriate. Furthermore, in an n-channel transistor, descriptions such as a low gate voltage, a low drain voltage, and a low back gate voltage can be interchanged with descriptions such as a high gate voltage, a high drain voltage, and a high back gate voltage in a p-channel transistor, as appropriate.

[0040] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing between the gate and the source and drain (also referred to as gate leakage current) may be collectively referred to as leakage current.

[0041] In this specification and the like, one of the source or drain (also referred to as two input / output terminals) of a transistor may be referred to as a first terminal, and the other of the source or drain of the transistor may be referred to as a second terminal. That is, a transistor has at least a gate (also referred to as a gate terminal), a first terminal, and a second terminal. One terminal of a capacitor (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other terminal of the capacitor (also referred to as the other of the pair of terminals) may be referred to as a second terminal. One terminal of a display element may be referred to as a first terminal, and the other terminal of the display element may be referred to as a second terminal. One terminal of a liquid crystal element may be referred to as a first terminal, and the other terminal of the liquid crystal element may be referred to as a second terminal. One terminal of a light-emitting element may be referred to as a first terminal, and the other terminal of the light-emitting element may be referred to as a second terminal. One terminal of a light-receiving element may be referred to as a first terminal, and the other terminal of the light-receiving element may be referred to as a second terminal. In addition, one of the anode or cathode of the diode (also referred to as one of a pair of terminals) may be referred to as a first terminal, and the other of the anode or cathode of the diode (also referred to as the other of the pair of terminals) may be referred to as a second terminal.

[0042] Embodiment 1 A memory device according to one embodiment of the present invention will be described with reference to the drawings.

[0043] <Configuration Example 1 of Memory Device> FIG. 1 is a circuit diagram illustrating a memory device 100A of one embodiment of the present invention.

[0044] The memory device 100A includes a memory array 110 and a driver 111A. The memory array 110 includes memory cells 101. The driver 111A includes a drive circuit 102A and a drive circuit 103A.

[0045] The memory cell 101 includes a transistor M11 and a memory portion MEM. One of the source and the drain of the transistor M11 is connected to the memory portion MEM. The other of the source and the drain of the transistor M11 is connected to a wiring BL. The gate of the transistor M11 is connected to a wiring WL. Note that the wiring connecting the one of the source and the drain of the transistor M11 and the memory portion MEM may be referred to as a wiring MN in the following description.

[0046] The transistor M11 can be, for example, an n-channel transistor.

[0047] The memory unit MEM has a function of storing data. The memory unit MEM can hold, for example, a low potential (e.g., potential V0) corresponding to one of binary data (e.g., "0") and a high potential (e.g., potential V1) corresponding to the other of the binary data (e.g., "1"). The transistor M11 functions as a switch for controlling writing of data to the memory unit MEM. The transistor may also function as a switch for controlling reading of data from the memory unit MEM. The wiring BL functions as a bit line. The wiring WL functions as a word line.

[0048] The memory unit MEM may have, for example, a capacitive element, and by holding charge accumulated in the dielectric of the capacitive element, it can store data corresponding to a potential according to the amount of charge. The memory unit MEM may also have, for example, a transistor, and by holding charge accumulated in the gate insulating film of the transistor, it can store data corresponding to a potential according to the amount of charge. The memory unit MEM may also have, for example, a flip-flop, and can store data in the flip-flop.

[0049] In the memory cell 101, for example, by applying a potential (for example, potential H) higher than the potential V1 to the wiring WL, the transistor M11 is turned on, and data can be written to the memory portion MEM. Also, for example, by applying a potential (for example, potential L) lower than the potential V0 to the wiring WL, the transistor M11 is turned off, and the data written to the memory portion MEM can be held.

[0050] A specific example of a configuration that can be applied to the memory cell 101 will be described later.

[0051] The drive circuit 102A includes a buffer X21, a transistor M21, and a transistor M22. The drive circuit 103A includes a transistor M31, a buffer X31, and an inverter X32.

[0052] The input terminal of the buffer X21 is connected to the wiring RL. The output terminal of the buffer X21 is connected to the wiring WL. The low power supply terminal of the buffer X21 is connected to one of the source or drain of the transistor M21. The high power supply terminal of the buffer X21 is connected to one of the source or drain of the transistor M22. The other of the source or drain of the transistor M21 is connected to the wiring VLS. The other of the source or drain of the transistor M22 is connected to the wiring VLD.

[0053] One of the source and drain of the transistor M31 is connected to the wiring WL. The other of the source and drain of the transistor M31 is connected to the wiring VLS. The input terminal of the buffer X31 is connected to the wiring GL. The output terminal of the buffer X31 is connected to the input terminal of the inverter X32. The low power supply terminal of the buffer X31 and the low power supply terminal of the inverter X32 are each connected to the wiring VLS. The high power supply terminal of the buffer X31 and the high power supply terminal of the inverter X32 are each connected to the wiring VLD.

[0054] The gate of the transistor M21 is connected to the output terminal of the buffer X31. The gate of the transistor M22 is connected to the output terminal of the inverter X32. The gate of the transistor M31 is connected to the output terminal of the inverter X32.

[0055] The wirings VLS and VLD each function as a power supply line, for example. A potential L is applied to the wiring VLS. A potential H is applied to the wiring VLD. The wirings RL and GL each function as a signal line, for example. Either a potential L or a potential H is applied to the wirings RL and GL.

[0056] In the driver circuit 102A, for example, an n-channel transistor can be used as the transistor M21. The transistor M21 functions as a switch that controls the supply of a potential (for example, a potential L) from the wiring VLS to the low power supply terminal of the buffer X21. Furthermore, for example, a p-channel transistor can be used as the transistor M22. The transistor M22 functions as a switch that controls the supply of a potential (for example, a potential H) from the wiring VLD to the high power supply terminal of the buffer X21.

[0057] The buffer X21 has a function of outputting, from its output terminal, a signal having the same logical value as the logical value of a signal input to its input terminal. When the transistors M21 and M22 of the buffer X21 are both on, if a potential L is input to the input terminal, the potential L is output from the output terminal, and if a potential H is input to the input terminal, the potential H is output from the output terminal. The buffer X21 can also improve the ability to drive a load connected to the output terminal. When the transistors M21 and M22 of the buffer X21 are both off, the output terminal becomes high impedance. Therefore, it can be said that the transistors M21 and M22 each have a function of controlling the supply of a signal from the output terminal of the buffer X21 to the wiring WL.

[0058] In the driver circuit 103A, for example, an n-channel transistor can be used as the transistor M31. The transistor M31 functions as a switch that controls the supply of a potential (for example, a potential L) from the wiring VLS to the wiring WL.

[0059] The buffer X31 has a function of outputting from its output terminal a signal having the same logical value as the logical value of a signal input to its input terminal. When a potential L is input to the input terminal of the buffer X31, a potential L is output from the output terminal, and when a potential H is input to the input terminal, a potential H is output from the output terminal. The buffer X31 can also improve the ability to drive a load connected to the output terminal.

[0060] Furthermore, the inverter X32 has the function of outputting from the output terminal a signal obtained by inverting the logical value of a signal input to the input terminal. When a potential L is input to the input terminal of the inverter X32, a potential H is output from the output terminal, and when a potential H is input to the input terminal, a potential L is output from the output terminal. In this case, it can also be said that the inverter X32 has the function of outputting a signal obtained by inverting the logical value of the signal output from the buffer X31. Furthermore, the inverter X32 can improve the ability to drive a load connected to the output terminal.

[0061] One of the low power supply terminal or the high power supply terminal of the buffer X21 may be referred to as the first power supply terminal, and the other may be referred to as the second power supply terminal. Also, one of the low power supply terminal or the high power supply terminal of the buffer X31 may be referred to as the first power supply terminal, and the other may be referred to as the second power supply terminal. Also, one of the low power supply terminal or the high power supply terminal of the inverter X32 may be referred to as the first power supply terminal, and the other may be referred to as the second power supply terminal.

[0062] In the memory device 100A, when the potential of the wiring RL and the potential of the wiring GL are both at potential H, the potential of the wiring WL is at potential H. When at least one of the potential of the wiring RL and the potential of the wiring GL is at potential L, the potential of the wiring WL is at potential L. In other words, in the memory device 100A, by applying potential H to both the potential of the wiring RL and the potential of the wiring GL, the transistor M11 in the memory cell 101 is turned on, and data can be written to the memory unit MEM.

[0063] In the memory device 100A, for example, an n-channel transistor may be used as the transistor M22 as shown in Fig. 2. In this case, the gate of the transistor M22 may be connected to the output terminal of the buffer X31.

[0064] 3, a p-channel transistor may be used as the transistor M31. In this case, the gate of the transistor M31 may be connected to the output terminal of the buffer X31.

[0065] 4, for example, a p-channel transistor may be used as the transistor M11. In this case, the other of the source and the drain of the transistor M31 may be connected to the wiring VLD. That is, the transistor M31 may function as a switch that controls the supply of potential from the wiring VLD to the wiring WL. In this case, in the description of the memory device 100A, descriptions regarding the positive and negative voltage relationships and the magnitude relationships of potentials may be reinterpreted as appropriate.

[0066] Also, for example, as shown in FIG. 5, a configuration in which a p-channel transistor is used as the transistor M11 (see FIG. 4) and a configuration in which a p-channel transistor is used as the transistor M31 (see FIG. 3) may be combined.

[0067] The configurations shown in FIGS. 1 to 5 may be appropriately combined.

[0068] Here, for example, a case where the memory device 100A is used in an environment with strong radiation, such as outer space, will be described. In this case, if the potential of the wiring WL in the memory cell 101 is unintentionally inverted from potential L to potential H due to radiation exposure, the transistor M11 may be erroneously turned on, and data stored in the memory unit MEM may be destroyed. Therefore, a configuration including a driver circuit 102A and a driver circuit 103A, as in the memory device 100A, is preferable.

[0069] In the memory device 100A, radiation reaches each transistor constituting the memory device 100A randomly, so the possibility of unintended signal inversion due to radiation exposure occurring simultaneously in two or more locations is low. In other words, the possibility of unintended signal inversion due to radiation exposure occurring simultaneously in both the drive circuit 102A and the drive circuit 103A is low. Therefore, by configuring the memory device 100A as described below, it is possible to make malfunctions of the memory cell 101 due to radiation exposure less likely to occur.

[0070] In the memory cell 101, when data is stored in the memory portion MEM, the potentials of the wirings RL, GL, and WL are all at the potential L, and the transistor M11 is off.

[0071] At this time, even if, for example, radiation irradiation unintentionally inverts a signal in at least a part of the driver circuit 102A and the potential of the wiring RL inverts from potential L to potential H, the transistor M31 is in the on state and the output terminal of the buffer X21 has high impedance, so the potential of the wiring WL remains at potential L. This prevents the transistor M11 from erroneously turning on and destroying the data stored in the memory unit MEM.

[0072] Furthermore, even if, for example, a signal is unintentionally inverted in at least a part of the driver circuit 103A due to radiation irradiation and the potential of the wiring GL is inverted from the potential L to the potential H, the transistor M31 is turned off and the potential L is output from the output terminal of the buffer X21, so the potential of the wiring WL remains at the potential L. This prevents the transistor M11 from being erroneously turned on and destroying the data stored in the memory unit MEM.

[0073] Due to this effect, in the memory device 100A, malfunction of the memory cells 101 due to radiation exposure is less likely to occur, thereby improving the reliability of the memory device.

[0074] Note that if radiation irradiation causes an unintended inversion of a signal in at least a part of the driver circuit 102A, causing the potential of the wiring RL to invert from potential L to potential H, and if radiation irradiation causes an unintended inversion of a signal in at least a part of the driver circuit 103A, causing the potential of the wiring GL to invert from potential L to potential H, simultaneously, the potential of the wiring WL may invert from potential L to potential H, potentially destroying data stored in the memory unit MEM. Therefore, in order to prevent radiation irradiation from causing an unintended inversion of a signal in at least a part of the driver circuit 102A and an unintended inversion of a signal in at least a part of the driver circuit 103A simultaneously, it is preferable to increase the distance between the driver circuits 102A and 103A.

[0075] For example, it is preferable to set the distance between the driver circuit 102A and the driver circuit 103A greater than the range affected by radiation. For example, the distance between the driver circuit 102A and the driver circuit 103A may be greater than the distance between the driver circuit 102A and the memory unit MEM. For example, the distance between the driver circuit 102A and the driver circuit 103A may be greater than the distance between the driver circuit 103A and the memory unit MEM. For example, the driver circuit 102A and the driver circuit 103A may be arranged to face each other across the memory unit MEM. This prevents radiation exposure from unintentionally inverting a signal in at least a portion of the driver circuit 102A and unintentionally inverting a signal in at least a portion of the driver circuit 103A, which would otherwise occur simultaneously, thereby preventing data stored in the memory unit MEM from being destroyed. Therefore, in the memory device 100A, malfunction of the memory cell 101 due to radiation exposure is less likely to occur. This improves the reliability of the memory device.

[0076] The operation of the storage device 100A will be described in detail later.

[0077] In one embodiment of the present invention, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used as a transistor included in the memory device 100A. The semiconductor is not limited to a simple semiconductor whose main component is a single element (such as silicon or germanium), but can also be, for example, a compound semiconductor (such as silicon germanium or gallium arsenide), an oxide semiconductor, or the like.

[0078] For example, as the transistors constituting the memory device 100A, a transistor containing silicon in a channel formation region (Si transistor) may be used, a transistor containing an oxide semiconductor in a channel formation region (OS transistor) may be used, or both a Si transistor and an OS transistor may be used.

[0079] Furthermore, various types of transistors can be used as the transistors that make up the memory device 100A, such as MOS field effect transistors, junction field effect transistors, or bipolar transistors.

[0080] In addition, transistors of various structures can be used as transistors constituting the memory device 100A. For example, transistors of various structures can be used, such as top-gate transistors (e.g., planar transistors and staggered transistors), bottom-gate transistors (e.g., inverted planar transistors and inverted staggered transistors), dual-gate transistors (structures in which gates are arranged on both sides (e.g., top and bottom) of a channel formation region), FIN transistors, TRI-GATE transistors, and GAA transistors (gate-all-around transistors). In addition, for example, vertical transistors (transistors whose channel length direction is vertical (also referred to as the height direction or the direction perpendicular to the formation surface)) can be used.

[0081] A structural example of a transistor that can be used in the memory device 100A will be described in Embodiment 2 or the like.

[0082] In one embodiment of the present invention, OS transistors are preferably used as at least some of the transistors included in the memory device 100A.

[0083] The OS transistor has a characteristic of having an extremely small off-state current because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width in a room temperature environment is 1 aA (1×10 −１８ A) Below, 1zA (1×10 −２１ A) or less, or 1 yA (1 x 10 −２４ In the case of a Si transistor (a transistor including silicon in a channel formation region), the off-state current per 1 μm of channel width in a room temperature environment can be 1 fA (1×10 −１５ A) or more and 1 pA (1 × 10 −１２Therefore, it can be said that the off-state current of an OS transistor is smaller than that of a Si transistor by about 10 orders of magnitude.

[0084] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-state current of an OS transistor is unlikely to decrease even in a high-temperature environment. Therefore, a semiconductor device including an OS transistor can operate stably and achieve high reliability even in a high-temperature environment.

[0085] Furthermore, an OS transistor has a high withstand voltage between the source and the drain (also referred to as drain withstand voltage). Therefore, a semiconductor device including an OS transistor can operate stably and with high reliability even when driven at high voltage.

[0086] Furthermore, as shown in Patent Document 4, the electrical characteristics of an OS transistor may change little due to radiation exposure. For example, the subthreshold slope of an OS transistor changes little due to radiation exposure. Furthermore, the field-effect mobility of an OS transistor changes little due to radiation exposure. Furthermore, an OS transistor can maintain an extremely small off-state current even after radiation exposure. Therefore, a semiconductor device including an OS transistor can operate stably and achieve high reliability even in an environment with strong radiation, such as outer space.

[0087] Furthermore, since OS transistors can be freely arranged on, for example, a silicon substrate on which Si transistors are provided, they can be easily integrated. Furthermore, since OS transistors can be manufactured using the same manufacturing equipment as Si transistors, OS transistors can be manufactured at low cost.

[0088] In one embodiment of the present invention, an OS transistor can be used as the transistor M11 included in the memory cell 101.

[0089] An OS transistor has an extremely low off-state current. Therefore, by using an OS transistor as the transistor M11, data written to the memory cell 101 can be stored for a long period of time. This reduces the frequency of data refresh, thereby reducing the power consumption of the storage device.

[0090] In addition, the electrical characteristics of an OS transistor may change little due to radiation exposure. Therefore, by using an OS transistor as the transistor M11, unintentional inversion of data written to the memory cell 101 due to radiation exposure can be suppressed. Therefore, the reliability of the memory device can be improved.

[0091] In one embodiment of the present invention, Si transistors may be used as both n-channel transistors and p-channel transistors in the driver circuits 102A and 103A. Alternatively, OS transistors may be used as at least some of the n-channel transistors and Si transistors may be used as the p-channel transistors.

[0092] By using an OS transistor as an n-channel transistor and a Si transistor as a p-channel transistor, the OS transistor can be stacked over the Si transistor, thereby reducing the area occupied by the driver circuit 102A and the driver circuit 103A. This reduces the area overhead of each of the driver circuits 102A and 103A, thereby enabling the miniaturization of the memory device.

[0093] Furthermore, by using an OS transistor as the n-channel transistor and a Si transistor as the p-channel transistor, the off-state current of the OS transistor is extremely small, so that the static current consumption of each of the driver circuits 102A and 103A can be reduced, thereby reducing the power consumption of the storage device.

[0094] Note that various oxide semiconductors can be used for the OS transistor. When an OS transistor is used as a transistor included in the memory device 100A, it is preferable to use an oxide semiconductor that exhibits low off-state current and high on-state current. This can improve the operation speed of the memory device 100A in addition to the above-described effects. Examples of oxide semiconductors that exhibit low off-state current and high on-state current include indium oxide.

[0095] The oxide semiconductor that can be used for the OS transistor will be described in detail in Embodiment 2 or the like.

[0096] [Inverter and Buffer] Here, examples of configurations that can be applied to the inverter and the buffer will be described.

[0097] 6A and 6B are a circuit diagram and a circuit symbol for explaining an example of the inverter INV, which can be applied to the inverter X32 described above.

[0098] The inverter INV includes an n-channel transistor Mn1 and a p-channel transistor Mp1. The gates of the transistors Mn1 and Mp1 are connected to an input terminal of the inverter INV (corresponding to the terminal connected to the wiring IL). One of the source or drain of the transistor Mn1 and one of the source or drain of the transistor Mp1 are connected to an output terminal of the inverter INV (corresponding to the terminal connected to the wiring OL). The other of the source or drain of the transistor Mn1 is connected to a low power supply terminal of the inverter INV (corresponding to the terminal connected to the wiring VLn). The other of the source or drain of the transistor Mp1 is connected to a high power supply terminal of the inverter INV (corresponding to the terminal connected to the wiring VLp).

[0099] 6C and 6D are a circuit diagram and a circuit symbol for explaining an example of the buffer BUF. The buffer BUF can be applied to each of the buffer X21 and the buffer X31 described above.

[0100] The buffer BUF includes an n-channel transistor Mn1, a p-channel transistor Mp1, an n-channel transistor Mn2, and a p-channel transistor Mp2. The gates of the transistors Mn1 and Mp1 are connected to an input terminal of the buffer BUF (corresponding to a terminal connected to the wiring IL). One of the source or drain of the transistor Mn1 and one of the source or drain of the transistor Mp1 are connected to a gate of the transistor Mn2 and one of the source or drain of the transistor Mp2, respectively. One of the source or drain of the transistor Mn2 and one of the source or drain of the transistor Mp2 are connected to an output terminal of the buffer BUF (corresponding to a terminal connected to the wiring OL). The other of the source or drain of the transistor Mn1 and the other of the source or drain of the transistor Mn2 are connected to a low power supply terminal of the buffer BUF (corresponding to a terminal connected to the wiring VLn). The other of the source or the drain of the transistor Mp1 and the other of the source or the drain of the transistor Mp2 are each connected to a high power supply terminal (corresponding to the terminal connected to the wiring VLp) of the buffer BUF.

[0101] [Memory Cell] Next, a description will be given of a configuration example that can be applied to the memory cell 101. An OS transistor can be used as a transistor included in the memory cell described below.

[0102] The memory cell 101a shown in FIG. 7A includes a transistor M11 and a memory unit MEM. The memory unit MEM includes a capacitor C11. One of the source or drain of the transistor M11 is connected to one terminal of the capacitor C11. The other of the source or drain of the transistor M11 is connected to a wiring BL that functions as a bit line. The gate of the transistor M11 is connected to a wiring WL that functions as a word line. The other terminal of the capacitor C11 is connected to a wiring CL. Note that the wiring that connects the one of the source or drain of the transistor M11 and one terminal of the capacitor C11 may be referred to as a wiring MN in the following description.

[0103] The memory cell 101a can store binary data by associating the amount of charge stored in the capacitor C11, i.e., the amount of charge held in the wiring MN, with "1" or "0." Note that, for example, ternary or more levels of data may be stored. When writing data, the memory cell 101a applies a potential corresponding to the data from the wiring BL to the wiring MN by controlling the conduction state of the transistor M11, and can hold a charge corresponding to the potential. When reading data, the memory cell 101a can extract the charge held in the wiring MN to the wiring BL by controlling the conduction state of the transistor M11.

[0104] Note that when data is read from the memory cell 101a, the charge held in the wiring MN is extracted to the wiring BL, and the potential of the wiring MN changes. That is, when data is read from the memory cell 101a, the stored data is destroyed. That is, when data is read from the memory cell 101a, destructive reading occurs. Therefore, after data is read from the memory cell 101a, data needs to be written back (refreshed).

[0105] In one embodiment of the present invention, for example, an n-channel OS transistor can be used as the transistor M11.

[0106] Note that the memory cell 101a shown in FIG. 7A is a dynamic random access memory (DRAM) memory cell. In particular, a memory cell using an OS transistor as the transistor M11 may be referred to as a DOSRAM (registered trademark). Since the DOSRAM uses an OS transistor with extremely low off-state current, it can store data for a long period of time. Furthermore, it can store multi-valued data or analog data. Furthermore, since once-written data can be stored for a long period of time, the frequency of data refresh can be reduced. Furthermore, since the electrostatic capacitance of the cell capacitance (capacitor element C11) can be reduced, the cell size can be reduced. Therefore, by using the DOSRAM, it is possible to reduce the power consumption and improve the recording density of a semiconductor device or a memory device.

[0107] The memory cell 101b shown in FIG. 7B is a modification of the memory cell 101a shown in FIG. 7A, and differs in that it does not have the capacitance element C11.

[0108] 7B, charge can be stored in the parasitic capacitance (the capacitance between the gate and either the source or the drain of the transistor M11) shown by the dashed line. That is, the parasitic capacitance shown by the dashed line corresponds to the memory unit MEM. By adopting such a configuration, for example, the cell size can be reduced, and the recording density of the semiconductor device and the memory device can be improved.

[0109] The memory cell 101c shown in FIG. 7C includes a transistor M11 and a memory unit MEM. The memory unit MEM includes a transistor M12 and a capacitor C11. One of the source or drain of the transistor M11 is connected to the gate of the transistor M12 and one terminal of the capacitor C11. The other of the source or drain of the transistor M11 is connected to a wiring WBL that functions as a write bit line. The gate of the transistor M11 is connected to a wiring WWL that functions as a write word line. One of the source or drain of the transistor M12 is connected to a wiring RBL that functions as a read bit line. The other of the source or drain of the transistor M12 is connected to a wiring PL. The other terminal of the capacitor C11 is connected to a wiring RWL that functions as a read word line. Note that the wiring that connects the one of the source or drain of the transistor M11, the gate of the transistor M12, and one terminal of the capacitor C11 to each other may be referred to as a wiring MN.

[0110] The memory cell 101c can store binary data by associating the amount of charge stored in the capacitor C11, i.e., the amount of charge held in the wiring MN, with "1" or "0." Note that, for example, ternary or more levels of data may be stored. When writing data, the memory cell 101c applies a potential corresponding to the data from the wiring WBL to the wiring MN by controlling the conduction state of the transistor M11, and can hold a charge corresponding to the potential. When reading data, the memory cell 101c can output a potential corresponding to the data to the wiring RBL by turning the transistor M12 on or off depending on the potential of the wiring MN.

[0111] In one embodiment of the present invention, for example, an n-channel OS transistor can be used as the transistor M11, and for example, an n-channel transistor (such as an OS transistor or a Si transistor) can be used as the transistor M12.

[0112] The memory cell 101c shown in FIG. 7C is a gain cell type memory cell. In particular, a memory cell using an OS transistor as the transistor M11 may be referred to as NOSRAM (registered trademark). NOSRAM is an abbreviation for Nonvolatile Oxide Semiconductor RAM. Since NOSRAM uses an OS transistor with extremely low off-state current, it can store data for a long period of time. It can also store multilevel data or analog data. Furthermore, since the writing transistor (transistor M11) and the reading transistor (transistor M12) are different, data reading is nondestructive. Therefore, it can be used, for example, as a nonvolatile memory.

[0113] 7D is a modified example of the memory cell 101c shown in FIG. 7C, and differs in that it does not include the capacitor element C11 and that the other of the source and the drain of the transistor M12 is connected to the wiring RWL.

[0114] 7D, charge can be stored in a parasitic capacitance added to the wiring MN. By adopting such a configuration, for example, the cell size can be reduced, and the recording density of the semiconductor device and the memory device can be improved.

[0115] The memory cell 101e shown in Figure 7E is a modified example of the memory cell 101c shown in Figure 7C, and differs in that the other of the source or the drain of the transistor M11 is connected to the wiring BL, and one of the source or the drain of the transistor M12 is connected to the wiring BL.

[0116] 7E, the wiring BL can function as both a write bit line and a read bit line. By adopting such a configuration, for example, the cell size can be reduced, and the recording density of the semiconductor device and the memory device can be improved.

[0117] The memory cell 101f shown in Fig. 7F is a modification of the memory cell 101c shown in Fig. 7C, and differs in that it includes a transistor M12p instead of the transistor M12. The transistor M12p can be, for example, a p-channel Si transistor.

[0118] 7F, since data is read using a p-channel transistor, it may be possible to simplify the configuration and operation of the sense amplifier, for example. By adopting such a configuration, it is possible to reduce the layout area of ​​the driver circuit, and to miniaturize the semiconductor device and memory device.

[0119] The memory cell 101g shown in FIG. 7G is a modified example of the memory cell 101c shown in FIG. 7C , and differs in that it further includes a transistor M13. One of the source or drain of the transistor M12 is connected to one of the source or drain of the transistor M13, the other of the source or drain of the transistor M12 is connected to a wiring PL, the other of the source or drain of the transistor M13 is connected to a wiring RBL, and the gate of the transistor M13 is connected to a wiring RWL. The other terminal of the capacitor C11 is connected to a wiring CL instead of the wiring RWL. The transistor M13 can be, for example, an n-channel transistor (e.g., an OS transistor or a Si transistor).

[0120] 7G, the parasitic capacitance between the wiring MN and the wiring RBL can be reduced. With this configuration, for example, it is possible to suppress the introduction of noise into the wiring MN via the gate capacitance of the transistor M12, thereby improving the reliability of the semiconductor device and the memory device.

[0121] The memory cell 101h shown in FIG. 7H includes transistors M11, M12, M13, and M14, as well as memory units MEM1 and MEM2. The memory unit MEM1 includes inverters X11 and X12. The memory unit MEM2 includes capacitors C11 and C12. One of the source or drain of the transistor M11 is connected to one of the source or drain of the transistor M13, the input terminal of the inverter X11, and the output terminal of the inverter X12. One of the source or drain of the transistor M12 is connected to one of the source or drain of the transistor M14, the output terminal of the inverter X11, and the input terminal of the inverter X12. The other of the source or drain of the transistor M13 is connected to one terminal of the capacitor C11. The other of the source or drain of the transistor M14 is connected to one terminal of the capacitor C12. The other of the source and drain of the transistor M11 is connected to a wiring BL that functions as one of a pair of bit lines. The other of the source and drain of the transistor M12 is connected to a wiring BLB that functions as the other of the pair of bit lines. The gates of the transistors M11 and M12 are connected to a wiring WL that functions as a word line. The gates of the transistors M13 and M14 are connected to a wiring BRL. The other terminal of the capacitor C11 and C12 is connected to a wiring CL.

[0122] The memory cell 101h can store binary data, "1" or "0," in an inverter loop formed by an inverter X11 and an inverter X12. When writing data, the memory cell 101h can apply potentials corresponding to the data to the inverter loop from the wirings BL and BLB by controlling the conduction states of the transistors M11 and M12. When reading data, the memory cell 101h can extract potentials corresponding to the data stored in the inverter loop from the wirings BL and BLB by controlling the conduction states of the transistors M11 and M12.

[0123] Furthermore, by controlling the conduction states of transistors M13 and M14, memory cell 101h can apply potentials corresponding to the data stored in the inverter loop to one terminal of capacitor C11 and one terminal of capacitor C12, respectively, and can hold charges corresponding to these potentials. In other words, data can be backed up. Furthermore, by controlling the conduction states of transistors M13 and M14, memory cell 101h can extract the charges held in one terminal of capacitor C11 and one terminal of capacitor C12, respectively, to the inverter loop. In other words, data can be recovered.

[0124] In one embodiment of the present invention, the transistors M11, M12, M13, and M14 can be, for example, n-channel OS transistors. The inverters X11 and X12 can be inverter circuits provided in a standard circuit library. That is, the transistors included in the inverters X11 and X12 can be, for example, n-channel and p-channel Si transistors.

[0125] Note that the memory cell 101h shown in FIG. 7H is a memory cell of a back-up capable static random access memory (SRAM). In particular, a configuration in which OS transistors are used as the transistors M11, M12, M13, and M14 may be referred to as an oxide semiconductor SRAM (OS-SRAM).

[0126] Note that one embodiment of the present invention is not limited to the memory cells 101a to 101h, and memory cells having structures each of which can be appropriately combined can be used.

[0127] 7A and 7B can be applied to the memory device 100A. That is, the driver circuit 102A and the driver circuit 103A can be connected to the wiring WL shown in each of FIGS. 7A and 7B. This can prevent the transistor M11 from being turned on erroneously and thus prevent data stored in the memory portion MEM from being corrupted.

[0128] 7C to 7G can be applied to the memory device 100A. That is, the driver circuit 102A and the driver circuit 103A can be connected to the wirings WWL shown in each of FIGS. 7C to 7G. This can prevent the transistor M11 from being erroneously turned on, thereby preventing data stored in the memory portion MEM from being corrupted. The driver circuit 102A and the driver circuit 103A can also be connected to the wirings RWL shown in each of FIGS. 7C to 7G.

[0129] The memory cell 101h shown in FIG. 7H can also be applied to the memory device 100A described above. That is, the driver circuit 102A and the driver circuit 103A can be connected to the wiring WL shown in FIG. 7H. This can prevent the transistors M11 and M12 from being erroneously turned on and data stored in the memory portion MEM1 from being corrupted. The driver circuit 102A and the driver circuit 103A can also be connected to the wiring BRL shown in FIG. 7H. This can prevent the transistors M13 and M14 from being erroneously turned on and data stored in the memory portion MEM2 from being corrupted.

[0130] Note that any of the memory cells 101a to 101h shown in FIGS. 7A to 7H can be applied to a memory device 100B shown in FIG. 15 and the like, which will be described later.

[0131] [Stacking Example] As described above, in one embodiment of the present invention, by using an OS transistor as an n-channel transistor and a Si transistor as a p-channel transistor, the OS transistor can be stacked over the Si transistor, thereby reducing the area occupied by the OS transistor.

[0132] 8 is a schematic diagram showing a memory device 100A in which a layer (layer LY2) in which n-channel transistors are provided is disposed above a layer (layer LY1) in which p-channel transistors are provided. In FIG. 8, transistors M11, M21, M22, M31, and a buffer X21 are illustrated as part of the memory device 100A. A buffer BUF is also used as the buffer X21, and transistors Mn1, Mp1, Mn2, and Mp2 are illustrated.

[0133] 8, the transistors M22, Mp1, and Mp2 are provided on a layer LY1, and the transistors M11, M21, M31, Mn1, and Mn2 are provided on a layer LY2 disposed above the layer LY1.

[0134] As a result, for example, in the driver 111A, the transistor M21 can be stacked on the transistor M22, the transistor Mn1 can be stacked on the transistor Mp1, and the transistor Mn2 can be stacked on the transistor Mp2. In this case, for example, by arranging at least some of the components of the transistor M22 and at least some of the components of the transistor M21 so that they overlap each other, the occupied area can be reduced. Furthermore, for example, by arranging at least some of the components of the transistor Mp1 and at least some of the components of the transistor Mn1 so that they overlap each other, the occupied area can be reduced. Furthermore, for example, by arranging at least some of the components of the transistor Mp2 and at least some of the components of the transistor Mn2 so that they overlap each other, the occupied area can be reduced.

[0135] Figure 9 is a modified example of the memory device 100A shown in Figure 8, and is a schematic diagram showing how a layer (layer LY3) in which the memory array 110 is provided is arranged above the layer (layer LY1 and layer LY2) in which the driver 111A is provided.

[0136] 9, the transistors M22, Mp1, and Mp2 are provided on a layer LY1. The transistors M21, M31, Mn1, and Mn2 are provided on a layer LY2 above the layer LY1. The transistor M11 is provided on a layer LY3 above the layer LY2.

[0137] As a result, although not shown, for example, by arranging the memory array 110 above the driver 111A, the occupied area can be reduced. Also, although not shown, for example, by arranging the memory array 110 above at least a part of a circuit (such as a sense amplifier) ​​that has the function of writing and reading data to and from the memory cells 101, the occupied area can be reduced.

[0138] Here, in one embodiment of the present invention, in the memory device 100A, n-channel transistors (such as the transistor M11) included in the memory array 110 and n-channel transistors (such as the transistor M21, the transistor M31, the transistor Mn1, and the transistor Mn2) included in the driver 111A may have different characteristics.

[0139] For example, the transistor M11 is preferably a transistor with a small off-state current so that data written to the memory cell 101 can be stored for a long period of time. For example, the transistors M21, M31, Mn1, and Mn2 are preferably each a transistor with a small off-state current so that static current consumption can be reduced, and are preferably each a transistor with a large on-state current so that operating speed can be improved.

[0140] Therefore, for example, the off-state current of the transistor M11 may be smaller than the off-state currents of the transistors M21, M31, Mn1, and Mn2. Also, for example, the on-state currents of the transistors M21, M31, Mn1, and Mn2 may be larger than the on-state current of the transistor M11. That is, for example, the field-effect mobility of the transistors M21, M31, Mn1, and Mn2 may be higher than the field-effect mobility of the transistor M11.

[0141] For example, when an OS transistor is used as an n-channel transistor, an oxide semiconductor including a channel formation region of the transistor M11 (also referred to as a first oxide semiconductor) and an oxide semiconductor including a channel formation region of each of the transistors M21, M31, Mn1, and Mn2 (also referred to as a second oxide semiconductor) may contain different elements or have different compositions.

[0142] For example, the first oxide semiconductor and the second oxide semiconductor may have different indium contents (ratios of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained in the oxide semiconductors). In this case, for example, the indium content in the second oxide semiconductor may be higher than the indium content in the first oxide semiconductor. For example, an oxide containing indium and zinc (such as indium gallium zinc oxide (IGZO) described later) may be used as the first oxide semiconductor, and indium oxide may be used as the second oxide semiconductor.

[0143] As a result, the hole mobility of the second oxide semiconductor can be made higher than that of the first oxide semiconductor. Therefore, the field-effect mobility of the OS transistor including the second oxide semiconductor can be made higher than that of the OS transistor including the first oxide semiconductor. That is, the on-state current of the OS transistor including the second oxide semiconductor can be made higher than that of the OS transistor including the first oxide semiconductor.

[0144] Furthermore, when the first oxide semiconductor contains an element such as gallium in addition to indium, the band gap can be made larger than that of the second oxide semiconductor, and therefore the off-state current of the OS transistor including the first oxide semiconductor can be made smaller than that of the OS transistor including the second oxide semiconductor.

[0145] Therefore, the off-state current of the transistor M11 can be reduced. Furthermore, the off-state current of each of the transistors M21, M31, Mn1, and Mn2 can be reduced and the on-state current can be increased. Therefore, it is possible to achieve both reduced power consumption and improved operating speed of the memory device.

[0146] The stacked structure shown in Fig. 8 can also be applied to, for example, the memory device 100B shown in Fig. 15 (described later). In this case, for example, the driver 111B is provided on the layer LY1 and the layer LY2, and the memory array 110 is provided on the layer LY2. The stacked structure shown in Fig. 9 can also be applied to, for example, the memory device 100B shown in Fig. 15 (described later). In this case, for example, the driver 111B is provided on the layer LY1 and the layer LY2, and the memory array 110 is provided on the layer LY3.

[0147] 8 can also be applied to, for example, the memory device 100C shown in FIG. 24, which will be described later. In this case, for example, the driver 111A is provided on the layers LY1 and LY2, the scan flip-flop 820 is provided on the layers LY1 and LY2, and the backup circuit 830 is provided on the layer LY2. In addition, the stacked structure shown in FIG. 9 can also be applied to, for example, the memory device 100C shown in FIG. 24, which will be described later. In this case, for example, the driver 111A is provided on the layers LY1 and LY2, the scan flip-flop 820 is provided on the layers LY1 and LY2, and the backup circuit 830 is provided on the layer LY3.

[0148] [Operation Example] Next, the operation of the storage device 100A will be described.

[0149] Fig. 10 is a timing chart illustrating an example of the operation of the memory device 100 A. Figs. 11 to 14 are circuit diagrams illustrating an example of the operation of the memory device 100 A.

[0150] In the following description of the operation, it is assumed that a potential H is applied to the wiring VLD and a potential L is applied to the wiring VLS. The potential of a signal applied to each of the wirings RL and GL is either the potential L or the potential H. The potential L is a potential that can turn off the transistor M11. The potential H is a potential that can turn on the transistor M11.

[0151] 10 shows the potentials of the wirings RL, GL, and WL in each period of operation. Note that in the timing chart, for ease of explanation, even if each period is illustrated as having the same length in the drawing, the length of each period may be different.

[0152] 11 to 14 also show the state of the circuit at each point in time of operation (the potential of each wiring and each node, the state of each transistor, the current flowing through each wiring and each node, etc.). In this case, symbols indicating potential such as "H" or "L" (also called potential symbols) may be written with a boxed character next to each wiring and each node. An "x" symbol may be written over a transistor in an off state. When the output terminal of a buffer is in a high impedance state, the letters "Hi-Z" may be written with a boxed character next to the buffer. The direction of current flow (which may also be said to be the direction in which positive charge moves) or the state in which potential is supplied along each wiring and each node may be shown with a dashed arrow.

[0153] Immediately before the period T11, a potential L is applied to the wiring RL and the wiring GL. At this time, a potential L is applied to the gate of the transistor M21, and a potential H is applied to the gates of the transistors M22 and M31. Therefore, the transistors M21 and M22 are both off, and the output terminal of the buffer X21 has high impedance. Furthermore, the transistor M31 is on, and the potential of the wiring VLS is supplied to the wiring WL. Therefore, the potential of the wiring WL is potential L and the transistor M11 is off, so that data is stored in the memory unit MEM in the memory cell 101. The circuit state at this time is shown in FIG. 11. Note that in the following description, unless otherwise specified, the previous state is maintained.

[0154] During the period T11, there is a period in which the potential of the wiring RL is at potential H. This corresponds to, for example, a case in which a signal is unintentionally inverted in part of the driver circuit 102A due to radiation irradiation, causing the potential of the wiring RL to invert from potential L to potential H. At this time, the potential of the wiring GL remains at potential L, so the transistors M21 and M22 remain off, and the output terminal of the buffer X21 remains at high impedance. Furthermore, the transistor M31 remains on, and the potential of the wiring VLS is supplied to the wiring WL. Therefore, the potential of the wiring WL remains at potential L, and the transistor M11 remains off. The circuit state at this time is shown in FIG. 12.

[0155] During the period T12, there is a period in which the potential of the wiring GL is at potential H. This corresponds to, for example, a case in which a signal is unintentionally inverted in part of the driver circuit 103A due to radiation irradiation, causing the potential of the wiring GL to invert from potential L to potential H. At this time, potential H is applied to the gate of the transistor M21, and potential L is applied to the gates of the transistors M22 and M31. Therefore, the transistors M21 and M22 are turned on, and the transistor M31 is turned off. Here, the potential of the wiring RL remains at potential L, so potential L is output from the output terminal of the buffer X21 and supplied to the wiring WL. Therefore, the potential of the wiring WL remains at potential L, and the transistor M11 remains off. The circuit state at this time is shown in FIG. 13.

[0156] In the period T13, a potential H is applied to the wiring RL, and then a potential H is applied to the wiring GL. Then, a potential H is applied to the gate of the transistor M21, and a potential L is applied to the gates of the transistors M22 and M31. Therefore, the transistors M21 and M22 are turned on, and the transistor M31 is turned off. Here, since the potential of the wiring RL is the potential H, the potential H is output from the output terminal of the buffer X21 and supplied to the wiring WL. Therefore, the potential of the wiring WL becomes the potential H, and the transistor M11 is turned on. This enables data to be written to the memory unit MEM in the memory cell 101. The circuit state at this time is shown in FIG. 14.

[0157] Note that in the period T13, the potential H may be applied to the wiring GL and then the potential H may be applied to the wiring RL. Alternatively, the potential H may be applied to the wirings RL and GL simultaneously.

[0158] In the period T14, a potential L is applied to the wiring GL, and then a potential L is applied to the wiring RL. Then, a potential L is applied to the gate of the transistor M21, and a potential H is applied to the gates of the transistors M22 and M31. Therefore, the transistors M21 and M22 are turned off, and the output terminal of the buffer X21 becomes high impedance. Furthermore, the transistor M31 is turned on, and the potential of the wiring VLS is supplied to the wiring WL. Therefore, the potential of the wiring WL becomes potential L, and the transistor M11 is turned off. This allows the memory cell 101 to retain the data written to the memory unit MEM. The state of the circuit at this time is the same as that immediately before the period T11 (i.e., the same as that in FIG. 11 ).

[0159] Note that in the period T14, the potential L may be applied to the wiring RL and then the potential L may be applied to the wiring GL. Alternatively, the potential L may be applied to the wirings RL and GL simultaneously.

[0160] In this manner, in the memory device 100A, by applying the potential H to both the wiring RL and the wiring GL, the transistor M11 is turned on, and data can be written to the memory unit MEM. This prevents the transistor M11 from being erroneously turned on and the data stored in the memory unit MEM from being destroyed when the memory device 100A is irradiated with radiation that reaches the memory device 100A randomly. This improves the reliability of the memory device.

[0161] <Structure Example 2 of Memory Device> FIG. 15 is a circuit diagram illustrating a memory device 100B of one embodiment of the present invention.

[0162] The memory device 100B includes a memory array 110 and a driver 111B. The memory array 110 includes memory cells 101. The driver 111B includes a drive circuit 102B and a drive circuit 103B.

[0163] The storage device 100B can be said to be a modified example of the storage device 100A described above, and therefore the above description can be referred to as appropriate, and the description may be omitted here.

[0164] For the memory cell 101, the above description can be referred to as appropriate.

[0165] The drive circuit 102B includes a buffer X21. The drive circuit 103B includes a transistor M31, a transistor M32, a buffer X31, and an inverter X32.

[0166] An input terminal of the buffer X21 is connected to a wiring RL. An output terminal of the buffer X21 is connected to one of the source and drain of a transistor M32. The other of the source and drain of the transistor M32 is connected to a wiring WL. A low power supply terminal of the buffer X21 is connected to a wiring VLS. A high power supply terminal of the buffer X21 is connected to a wiring VLD.

[0167] One of the source and drain of the transistor M31 is connected to the wiring WL. The other of the source and drain of the transistor M31 is connected to the wiring VLS. The input terminal of the buffer X31 is connected to the wiring GL. The output terminal of the buffer X31 is connected to the input terminal of the inverter X32. The low power supply terminal of the buffer X31 and the low power supply terminal of the inverter X32 are each connected to the wiring VLS. The high power supply terminal of the buffer X31 and the high power supply terminal of the inverter X32 are each connected to the wiring VLD.

[0168] The gate of the transistor M32 is connected to the output terminal of the buffer X31. The gate of the transistor M31 is connected to the output terminal of the inverter X32.

[0169] The wirings VLS and VLD each function as a power supply line, for example. A potential L is applied to the wiring VLS. A potential H is applied to the wiring VLD. The wirings RL and GL each function as a signal line, for example. Either a potential L or a potential H is applied to the wirings RL and GL.

[0170] The above descriptions can be referred to as appropriate for the buffer X21, the buffer X31, and the inverter X32.

[0171] In the driver circuit 103B, for example, an n-channel transistor can be used as the transistor M31. The transistor M31 functions as a switch that controls the supply of a potential (for example, a potential L) from the wiring VLS to the wiring WL. For example, an n-channel transistor can be used as the transistor M32. The transistor M32 functions as a switch that controls the supply of a signal from the output terminal of the buffer X21 to the wiring WL.

[0172] In the memory device 100B, when the potential of the wiring RL and the potential of the wiring GL are both at potential H, the potential of the wiring WL is at potential H. When at least one of the potential of the wiring RL and the potential of the wiring GL is at potential L, the potential of the wiring WL is at potential L. In other words, in the memory device 100B, applying potential H to both the potential of the wiring RL and the potential of the wiring GL turns on the transistor M11 in the memory cell 101, and data can be written to the memory unit MEM.

[0173] In the memory device 100B, for example, as shown in FIG. 16, a p-channel transistor may be used as the transistor M31. In this case, the gate of the transistor M31 may be connected to the output terminal of the buffer X31. In the configuration shown in FIG. 16, the drive circuit 103B does not need to have the inverter X32. This allows the memory device to be miniaturized.

[0174] 17, a p-channel transistor may be used as the transistor M32. In this case, the gate of the transistor M32 may be connected to the output terminal of the inverter X32. Although not shown, an analog switch composed of an n-channel transistor and a p-channel transistor may be used instead of the transistor M32. In this case, the gate of the n-channel transistor may be connected to the output terminal of the buffer X31, and the gate of the p-channel transistor may be connected to the output terminal of the inverter X32.

[0175] 18, for example, a p-channel transistor may be used as the transistor M11. In this case, the other of the source and the drain of the transistor M31 may be connected to the wiring VLD. That is, the transistor M31 may function as a switch that controls the supply of potential from the wiring VLD to the wiring WL. In this case, in the description of the memory device 100B, descriptions regarding the positive and negative voltage relationships and the magnitude relationships of potentials may be reinterpreted as appropriate.

[0176] Also, for example, as shown in FIG. 19, a configuration may be used that combines a configuration in which a p-channel transistor is used for the transistor M11 (see FIG. 18), a configuration in which a p-channel transistor is used for the transistor M31 (see FIG. 16), and a configuration in which a p-channel transistor is used for the transistor M32 (see FIG. 17).

[0177] Note that the configurations shown in FIGS. 15 to 19 may be appropriately combined.

[0178] Here, in the memory device 100B, similarly to the memory device 100A described above, it is unlikely that unintended signal inversion due to radiation exposure will occur simultaneously in both the drive circuit 102B and the drive circuit 103B. Therefore, by configuring the memory device 100B as described below, it is possible to make malfunction of the memory cell 101 due to radiation exposure less likely to occur.

[0179] In the memory cell 101, when data is stored in the memory portion MEM, the potentials of the wirings RL, GL, and WL are all at the potential L, and the transistor M11 is off.

[0180] At this time, even if, for example, a signal is unintentionally inverted in at least a part of the driver circuit 102B due to radiation irradiation and the potential of the wiring RL is inverted from potential L to potential H, the transistor M31 is in the on state and the transistor M32 is in the off state, so the potential of the wiring WL remains at potential L. Therefore, it is possible to prevent the transistor M11 from being erroneously turned on and the data stored in the memory unit MEM from being destroyed.

[0181] Furthermore, even if, for example, radiation irradiation causes an unintentional signal inversion in at least a part of the driver circuit 103B, causing the potential of the wiring GL to invert from potential L to potential H, the transistor M31 is turned off, the transistor M32 is turned on, and the potential L is output from the output terminal of the buffer X21, so the potential of the wiring WL remains at potential L. This prevents the transistor M11 from being erroneously turned on, which could cause data stored in the memory unit MEM to be destroyed.

[0182] Due to this effect, in the memory device 100B, malfunction of the memory cells 101 due to radiation exposure is less likely to occur, thereby improving the reliability of the memory device.

[0183] For the transistors constituting the memory device 100B, the above description of the transistors constituting the memory device 100A can be referred to as appropriate.

[0184] [Operation Example] Next, the operation of the storage device 100B will be described. Since the storage device 100B can be considered a modified example of the storage device 100A, the operation will be described here using the timing chart shown in Figure 10 described above. Note that the description of the storage device 100A described above can be referred to as appropriate.

[0185] 20 to 23 are circuit diagrams illustrating an example of the operation of the storage device 100B.

[0186] In the following description of the operation, it is assumed that a potential H is applied to the wiring VLD and a potential L is applied to the wiring VLS. The potential of a signal applied to each of the wirings RL and GL is either the potential L or the potential H. The potential L is a potential that can turn off the transistor M11. The potential H is a potential that can turn on the transistor M11.

[0187] Immediately before the period T11, a potential L is applied to the wiring RL and the wiring GL. At this time, a potential H is applied to the gate of the transistor M31, and a potential L is applied to the gate of the transistor M32. Therefore, the transistor M31 is on, the transistor M32 is off, and the potential of the wiring VLS is supplied to the wiring WL. Therefore, the potential of the wiring WL is potential L and the transistor M11 is off, so that data is stored in the memory unit MEM in the memory cell 101. The state of the circuit at this time is shown in FIG. 20. Note that in the following description, unless otherwise specified, the previous state is assumed to be maintained.

[0188] During the period T11, there is a period in which the potential of the wiring RL is at the potential H. This corresponds to, for example, a case in which a signal is unintentionally inverted in part of the driver circuit 102B due to radiation irradiation, causing the potential of the wiring RL to invert from the potential L to the potential H. At this time, the potential of the wiring GL remains at the potential L, so the transistor M31 remains on, the transistor M32 remains off, and the potential of the wiring VLS is supplied to the wiring WL. Therefore, the potential of the wiring WL remains at the potential L, and the transistor M11 remains off. The circuit state at this time is shown in FIG. 21.

[0189] During the period T12, there is a period in which the potential of the wiring GL is at potential H. This corresponds to, for example, a case in which a signal is unintentionally inverted in part of the driver circuit 103B due to radiation irradiation, causing the potential of the wiring GL to invert from potential L to potential H. At this time, potential L is applied to the gate of the transistor M31, and potential H is applied to the gate of the transistor M32. As a result, the transistor M31 is turned off, and the transistor M32 is turned on. Here, because the potential of the wiring RL remains at potential L, potential L is output from the output terminal of the buffer X21 and is supplied to the wiring WL via the transistor M32. Therefore, the potential of the wiring WL remains at potential L, and the transistor M11 remains off. The circuit state at this time is shown in FIG. 22.

[0190] In the period T13, a potential H is applied to the wiring RL, and then a potential H is applied to the wiring GL. Then, a potential L is applied to the gate of the transistor M31, and a potential H is applied to the gate of the transistor M32. Therefore, the transistor M31 is turned off, and the transistor M32 is turned on. Here, since the potential of the wiring RL is the potential H, the potential H is output from the output terminal of the buffer X21 and supplied to the wiring WL via the transistor M32. Therefore, the potential of the wiring WL becomes the potential H, and the transistor M11 is turned on. This enables data to be written to the memory unit MEM in the memory cell 101. The circuit state at this time is shown in FIG. 23.

[0191] Note that in the period T13, the potential H may be applied to the wiring GL and then the potential H may be applied to the wiring RL. Alternatively, the potential H may be applied to the wirings RL and GL simultaneously.

[0192] In the period T14, a potential L is applied to the wiring GL, and then a potential L is applied to the wiring RL. Then, a potential L is applied to the gate of the transistor M32, and a potential H is applied to the gate of the transistor M31. Therefore, the transistor M31 is turned on, the transistor M32 is turned off, and the potential of the wiring VLS is supplied to the wiring WL. Therefore, the potential of the wiring WL becomes the potential L, and the transistor M11 is turned off. This allows the memory cell 101 to retain the data written to the memory unit MEM. The state of the circuit at this time is the same as that immediately before the period T11 (i.e., the same as that in FIG. 20).

[0193] Note that in the period T14, the potential L may be applied to the wiring RL and then the potential L may be applied to the wiring GL. Alternatively, the potential L may be applied to the wirings RL and GL simultaneously.

[0194] In this manner, in the memory device 100B, applying a potential H to both the wiring RL and the wiring GL turns on the transistor M11, allowing data to be written to the memory unit MEM. This prevents the transistor M11 from being erroneously turned on and data stored in the memory unit MEM from being destroyed when the memory device 100B is irradiated with radiation that reaches the memory device 100B randomly. This improves the reliability of the memory device.

[0195] Here, a comparison between the storage device 100A and the storage device 100B will be described.

[0196] The memory device 100A is configured such that the power supply to the buffer X21 is cut off by the transistors M21 and M22. Therefore, the memory device 100A has a configuration that can reduce static current consumption and power consumption compared to the memory device 100B.

[0197] The memory device 100B is configured such that the transistor M32 blocks the supply of potential from the output terminal of the buffer X21 to the wiring WL. Therefore, the memory device 100B can be configured to have a smaller number of transistors and be more compact than the memory device 100A.

[0198] Note that one embodiment of the present invention may be a configuration in which the storage device 100A and the storage device 100B are combined as appropriate.

[0199] <Modification of Storage Device> One embodiment of the present invention is not limited to the configurations of the storage device 100A and the storage device 100B described above.

[0200] 24 is a circuit diagram illustrating a memory device 100C, which is a modified example of the memory device 100A. The memory device 100C differs from the memory device 100A in that it has a register 800 instead of the memory array 110. The register 800 can be applied to, for example, a register included in an arithmetic processing unit. The register 800 has a unit memory circuit 810. In other words, the memory device 100C can be said to differ from the memory device 100A in that it has a unit memory circuit 810 instead of the memory cell 101. Note that the above-mentioned description of the memory device 100A can be referred to as appropriate, and therefore, the description here may be omitted.

[0201] The unit memory circuit 810 includes a scan flip-flop 820 and a backup circuit 830 .

[0202] The backup circuit 830 is connected to the scan flip-flop 820 via a wiring Q. The backup circuit 830 is also connected to the scan flip-flop 820 via a wiring SD.

[0203] The unit memory circuit 810 has a function of storing 1-bit information. Specifically, the unit memory circuit 810 has a function of storing and holding data provided from a wiring D in the scan flip-flop 820 and outputting the data to a wiring Q.

[0204] The unit memory circuit 810 may also have a function of storing 1-bit information even when the unit memory circuit 810 is powered off (power supply is cut off). Specifically, the unit memory circuit 810 may have a function of writing and holding data stored in the scan flip-flop 820 in the backup circuit 830, and a function of writing the held data back to the scan flip-flop 820.

[0205] The scan flip-flop 820 includes a selector 821 and a flip-flop 822. The backup circuit 830 includes a holding circuit 831 and a transistor M83. The holding circuit 831 includes a transistor M81, a transistor M82, and a capacitive element C81.

[0206] Various signals for controlling the operation of the unit memory circuit 810 are supplied to the wirings BK, RV, SE, PCK, and GBK.

[0207] The unit memory circuit 810 can store and hold data input from wiring D or data input from wiring SD in a flip-flop 822 in the scan flip-flop 820 in synchronization with a clock signal applied to wiring PCK, and output the data to wiring Q. The data held in the flip-flop 822 is written to a holding circuit 831 in the backup circuit 830 via wiring Q in response to a signal applied to wiring BK, and then held therein. This operation may be referred to as, for example, save, evacuation, store, or backup. Furthermore, the data held in the holding circuit 831 can be written back to the flip-flop 822 via wiring SD in response to a signal applied to wiring RV, and then held therein. This operation may be referred to as, for example, load, return, restore, or recovery.

[0208] The flip-flop 822 stores and holds data applied to an input terminal Df in synchronization with a clock signal applied to a wiring PCK, and outputs the data from an output terminal Qf. A flip-flop provided in a standard circuit library can be used as the flip-flop 822. For example, a positive edge trigger type D flip-flop can be used.

[0209] The selector 821 has a function of transmitting data provided to the wiring D or the wiring SD to the flip-flop 822 in response to a signal provided to the wiring SE. Data held in a holding circuit 831 in the backup circuit 830 or data input from the wiring SDI is provided to the wiring SD. Data for a scan test is provided to the wiring SDI. For example, a selector provided in a standard circuit library can be used as the selector 821.

[0210] The backup circuit 830 can hold the state of the scan flip-flop 820 in the holding circuit 831 when power gating is performed.

[0211] The holding circuit 831 is connected to each of the wiring Q and the wiring SD. In the holding circuit 831, the terminal (wiring) connected to the wiring Q serves as an input terminal, and the terminal (wiring) connected to the wiring SD serves as an output terminal. That is, in the unit memory circuit 810, the output terminal Qf of the flip-flop 822 is connected to the input terminal of the holding circuit 831, and the input terminal Df of the flip-flop 822 is connected to the output terminal of the holding circuit 831 via the selector 821.

[0212] In the holding circuit 831, one of the source or drain of the transistor M81 is connected to one terminal of the capacitance element C81. One of the source or drain of the transistor M82 is connected to one terminal of the capacitance element C81. The other terminal of the capacitance element C81 is connected to a wiring to which a constant potential is supplied. The other of the source or drain of the transistor M81 is connected to the input terminal of the holding circuit 831 (i.e., wiring Q). The other of the source or drain of the transistor M82 is connected to the output terminal of the holding circuit 831 (i.e., wiring SD). The gate of the transistor M81 is connected to wiring BK. The gate of the transistor M82 is connected to wiring RV.

[0213] In addition, in the holding circuit 831, the wiring that connects one of the source or drain of the transistor M81, one of the source or drain of the transistor M82, and one terminal of the capacitor C81 may be referred to as wiring SN.

[0214] In the backup circuit 830, one of the source and the drain of the transistor M83 is connected to the wiring SD. The other of the source and the drain of the transistor M83 is connected to the wiring SDI.

[0215] The gate of the transistor M83 is connected to a line GBK, which is supplied with a signal that controls whether or not a scan test is performed.

[0216] In one embodiment of the present invention, in the backup circuit 830, for example, OS transistors can be used as the transistors M81, M82, and M83. OS transistors have a characteristic of extremely low off-state current. Furthermore, the off-state current hardly increases even in a high-temperature environment. Therefore, in the retention circuit 831 in which the transistors M81 and M82 are OS transistors, data written to the wiring SN can be retained for a long period of time by turning off the transistors M81 and M82. For example, data can be retained even when power supply to the scan flip-flop 820 is cut off by power gating.

[0217] 24, in the memory device 100C, the driver circuit 102A and the driver circuit 103A are connected to the wiring BK, which corresponds to the wiring WL in the memory device 100A described above.

[0218] Therefore, in the memory device 100C, applying a potential H to both the wiring RL and the wiring GL turns on the transistor M81, enabling backup in the unit memory circuit 810. This prevents the transistor M81 from being erroneously turned on and the data held in the holding circuit 831 from being corrupted when the memory device 100C is irradiated with radiation that reaches the memory device 100C randomly. This improves the reliability of the memory device.

[0219] Although not shown, the driver circuit 102A and the driver circuit 103A may be connected to the wiring RV, which can prevent the transistor M82 from being erroneously turned on and the data held in the holding circuit 831 from being corrupted.

[0220] Although not shown, the memory device 100B described above may have a unit memory circuit 810 instead of the memory cell 101. That is, the memory device 100C may have a drive circuit 102B instead of the drive circuit 102A, and a drive circuit 103B instead of the drive circuit 103A.

[0221] <Structure Example 3 of Memory Device> A memory device of one embodiment of the present invention includes a plurality of memory cells arranged in a matrix and a plurality of driver circuits arranged in each row.

[0222] For example, the memory device 100A can have a plurality of memory cells 101 arranged in a matrix and a plurality of drive circuits 102A arranged for each row in the memory array 110. In this case, the memory device 100A may have one drive circuit 103A or a plurality of drive circuits 103A arranged for each row.

[0223] Fig. 25 is a circuit diagram showing an example of a configuration of a memory device 100A having one drive circuit 103A. Fig. 26 is a circuit diagram showing an example of a configuration of a memory device 100A having multiple drive circuits 103A arranged for each row.

[0224] 25 and 26 each illustrate a memory cell 101_11 arranged in the first row and the first column, a memory cell 101_12 arranged in the first row and the second column, a memory cell 101_21 arranged in the second row and the first column, and a memory cell 101_22 arranged in the second row and the second column, as an example of the memory array 110. Also, as an example of the memory cell 101_11, the memory cell 101_12, the memory cell 101_21, and the memory cell 101_22, the configuration of the memory cell 101g shown in FIG.

[0225] The figure also shows wirings WBL_1 and RBL_1 connected to the memory cells 101_11 and 101_21 arranged in the first column, and wirings WBL_2 and RBL_2 connected to the memory cells 101_12 and 101_22 arranged in the second column. The figure also shows wirings WWL_1 and RWL_1 connected to the memory cells 101_11 and 101_12 arranged in the first row, and wirings WWL_2 and RWL_2 connected to the memory cells 101_21 and 101_22 arranged in the second row.

[0226] As an example of the driver 111A, a configuration including a drive circuit section 112A and a drive circuit section 113A is illustrated.

[0227] For example, the driver circuit portion 112A includes a driver circuit 102A_1 connected to the wiring WWL_1 and a driver circuit 102A_2 connected to the wiring WWL_2.

[0228] In this case, an output terminal of the buffer X21 included in the driver circuit 102A_1 is connected to the wiring WWL_1. An input terminal of the buffer X21 included in the driver circuit 102A_1 is connected to the wiring RL_1. An output terminal of the buffer X21 included in the driver circuit 102A_2 is connected to the wiring WWL_2. An input terminal of the buffer X21 included in the driver circuit 102A_2 is connected to the wiring RL_2.

[0229] In the configuration shown in FIG. 25, the driver circuit portion 113A includes, for example, a driver circuit 103A connected to the wirings WWL_1 and WWL_2.

[0230] In this case, the gate of the transistor M21 included in each of the driver circuits 102A_1 and 102A_2 is connected to the output terminal of the buffer X31 included in the driver circuit 103A. The gate of the transistor M22 included in each of the driver circuits 102A_1 and 102A_2 is connected to the output terminal of the inverter X32 included in the driver circuit 103A. The driver circuit 103A also includes transistors M31_1 and M31_2. One of the source or the drain of the transistor M31_1 is connected to the wiring WWL_1. One of the source or the drain of the transistor M31_2 is connected to the wiring WWL_2. The other of the source or the drain of the transistor M31_1 and the other of the source or the drain of the transistor M31_2 are connected to the wiring VLS. The gates of the transistors M31_1 and M31_2 are connected to the output terminal of the inverter X32.

[0231] In the configuration shown in FIG. 26, the driver circuit portion 113A includes, for example, a driver circuit 103A_1 connected to the wiring WWL_1 and a driver circuit 103A_2 connected to the wiring WWL_2.

[0232] In this case, the gate of the transistor M21 included in the driver circuit 102A_1 is connected to the output terminal of the buffer X31 included in the driver circuit 103A_1. The gate of the transistor M22 included in the driver circuit 102A_1 is connected to the output terminal of the inverter X32 included in the driver circuit 103A_1. One of the source and the drain of the transistor M31 included in the driver circuit 103A_1 is connected to the wiring WWL_1. The input terminal of the buffer X31 included in the driver circuit 103A_1 is connected to the wiring GL_1. The gate of the transistor M21 included in the driver circuit 102A_2 is connected to the output terminal of the buffer X31 included in the driver circuit 103A_2. The gate of the transistor M22 included in the driver circuit 102A_2 is connected to the output terminal of the inverter X32 included in the driver circuit 103A_2. One of the source and the drain of the transistor M31 included in the driver circuit 103A_2 is connected to the wiring WWL_2. An input terminal of the buffer X31 included in the driver circuit 103A_2 is connected to the wiring GL_2.

[0233] The memory device 100A shown in Fig. 25 has a configuration including one drive circuit 103 A. Therefore, the memory device 100A shown in Fig. 25 can be made smaller than the memory device 100A shown in Fig. 26.

[0234] 26 has a configuration including a plurality of drive circuits 103A arranged for each row, and therefore the memory device 100A shown in Fig. 26 can achieve improved reliability compared to the memory device 100A shown in Fig. 25.

[0235] FIG. 27 is a modified example of the storage device 100A shown in FIG.

[0236] In the memory device 100A shown in FIG. 27, each of the driver circuits 102A_1 and 102A_2 includes a level shifter LS21, a transistor M23, and a transistor M24, and the driver circuit 103A includes a level shifter LS31.

[0237] In this case, in each of the driver circuits 102A_1 and 102A_2, the output terminal of the level shifter LS21 is connected to the input terminal of the buffer X21. The low power supply terminal of the level shifter LS21 is connected to one of the source or drain of the transistor M23. The first high power supply terminal of the level shifter LS21 is connected to the wiring VLd. The second high power supply terminal of the level shifter LS21 is connected to one of the source or drain of the transistor M24. The other of the source or drain of the transistor M23 is connected to the wiring VLS. The other of the source or drain of the transistor M24 is connected to the wiring VLD. The gate of the transistor M23 is connected to the gate of the transistor M21. The gate of the transistor M24 is connected to the gate of the transistor M22. In addition, the input terminal of the level shifter LS21 in the driver circuit 102A_1 is connected to the wiring RL_1. An input terminal of the level shifter LS21 included in the driver circuit 102A_2 is connected to the wiring RL_2.

[0238] The transistor M23 can be, for example, an n-channel transistor, similar to the transistor M21, and the transistor M24 can be, for example, a p-channel transistor, similar to the transistor M22.

[0239] The level shifter LS21 has a function of converting the amplitude of a signal input to its input terminal. When the transistors M23 and M24 are both on, the level shifter LS21 receives a signal that varies between the potential of the low power supply terminal and the potential of the first high power supply terminal and outputs a signal that varies between the potential of the low power supply terminal and the potential of the second high power supply terminal from its output terminal. When the transistors M23 and M24 are both off, the level shifter LS21 receives a signal that varies between the potential of the low power supply terminal and the potential of the second high power supply terminal and outputs ...

[0240] In the driving circuit 103A, the output terminal of the level shifter LS31 is connected to the input terminal of the buffer X31. The low power supply terminal of the level shifter LS31 is connected to the wiring VLS. The first high power supply terminal of the level shifter LS31 is connected to the wiring VLd. The second high power supply terminal of the level shifter LS31 is connected to the wiring VLD. The input terminal of the level shifter LS31 in the driving circuit 103A is connected to the wiring GL.

[0241] The level shifter LS31 has a function of converting the amplitude of a signal input to its input terminal, and when a signal that changes between the potential of the low power supply terminal and the potential of the first high power supply terminal is input to its input terminal, the level shifter LS31 outputs a signal that changes between the potential of the low power supply terminal and the potential of the second high power supply terminal from its output terminal.

[0242] 27 , the potential of the wiring VLd is preferably set lower than the potential of the wiring VLD. This can reduce the operating voltage of circuits (not shown) other than the level shifter LS21 and the buffer X21 in each of the driver circuits 102A_1 and 102A_2. Furthermore, in the driver circuit 103A, the operating voltage of circuits (not shown) other than the level shifter LS31, the buffer X31, and the inverter X32 can be reduced. This can reduce the power consumption of the memory device.

[0243] The configurations shown in each of FIGS. 25 to 27 can also be applied to the storage device 100B.

[0244] [Level Shifter] Here, an example of a configuration applicable to a level shifter will be described.

[0245] 28A and 28B are a circuit diagram and a circuit symbol for explaining an example of the level shifter LS. The level shifter LS can be applied to each of the level shifter LS21 and the level shifter LS31 described above.

[0246] The level shifter LS includes an n-channel transistor Mn1, a p-channel transistor Mp1, an n-channel transistor Mn2, a p-channel transistor Mp2, an n-channel transistor Mn3, a p-channel transistor Mp3, a p-channel transistor Mp4, and a p-channel transistor Mp5. The gates of the transistors Mn1, Mp1, Mn3, and Mp3 are connected to an input terminal (corresponding to the terminal connected to the wiring IL) of the level shifter LS. One of the source or drain of the transistor Mn1 and one of the source or drain of the transistor Mp1 are connected to the gates of the transistors Mn2 and Mp2, respectively. One of the source or drain of the transistor Mn2 and one of the source or drain of the transistor Mp2 are connected to the gate of the transistor Mp5. One of the source or drain of transistor Mn3 and one of the source or drain of transistor Mp3 are connected to the gate of transistor Mp4 and the output terminal of the level shifter LS (corresponding to the terminal connected to wiring OL), respectively. The other of the source or drain of transistor Mp2 is connected to one of the source or drain of transistor Mp4. The other of the source or drain of transistor Mp3 is connected to one of the source or drain of transistor Mp5. The other of the source or drain of transistor Mn1, the other of the source or drain of transistor Mn2, and the other of the source or drain of transistor Mn3 are connected to the low power supply terminal of the level shifter LS (corresponding to the terminal connected to wiring VLn). The other of the source or drain of transistor Mp1 is connected to the first high power supply terminal of the level shifter LS (corresponding to the terminal connected to wiring VLp1). The other of the source or drain of the transistor Mp4 and the other of the source or drain of the transistor Mp5 are each connected to a second high power supply terminal (corresponding to the terminal connected to the wiring VLp2) of the level shifter LS.

[0247] <Configuration Example 4 of Storage Device> A storage device 700 of one embodiment of the present invention will be described.

[0248] 29 is a block diagram illustrating an example of the configuration of a memory device 700. The memory device 700 shown in FIG.

[0249] The memory array 721 has a plurality of memory cells 741. The plurality of memory cells 741 are arranged in a matrix of M rows and N columns, where M is an integer equal to or greater than 1, and N is an integer equal to or greater than 1.

[0250] In Figure 29, as representative examples, memory cell 741[1,1] arranged in the first row and first column, memory cell 741[1,N] arranged in the first row and Nth column, memory cell 741[M,1] arranged in the Mth row and first column, and memory cell 741[M,N] arranged in the Mth row and Nth column are shown.

[0251] In addition, Figure 29 shows, as representative examples, wiring WL[1] connected to N memory cells 741 arranged in the first row, wiring WL[M] connected to N memory cells 741 arranged in the Mth row, wiring BL[1] connected to M memory cells 741 arranged in the first column, and wiring BL[N] connected to M memory cells 741 arranged in the Nth column.

[0252] The drive circuit 722 includes a power switch 761, a power switch 762, and a peripheral circuit 771. The peripheral circuit 771 includes a peripheral circuit 781, a control circuit 772, and a voltage generation circuit 773.

[0253] In one embodiment of the present invention, for example, a Si transistor (a transistor including silicon in a channel formation region) can be used as a transistor included in the driver circuit 722. Therefore, for example, a CMOS circuit (e.g., a circuit operating complementarily, a CMOS logic gate, or a CMOS logic circuit) formed by connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor can be used as the driver circuit 722.

[0254] Alternatively, the driver circuit 722 may be a CMOS circuit in which the gate of an n-channel OS transistor and the gate of a p-channel Si transistor are connected to each other.

[0255] Furthermore, although not shown, the memory device 700 may have a configuration in which the memory array 721 has a plurality of sense amplifiers arranged in a matrix, and a plurality of memory cells 741 are stacked on the sense amplifiers. With such a configuration, the data stored in the memory array 721 can be read out in a massively parallel manner by simultaneously accessing the plurality of sense amplifiers.

[0256] For example, a signal is supplied to each of the terminal BW, terminal CE, terminal GW, terminal MCK, terminal WAKE, terminal ADDR, terminal WDA, terminal PON1, and terminal PON2 from outside the storage device 700. In addition, for example, a signal is output from the terminal RDA to outside the storage device 700.

[0257] For example, a clock signal is applied to terminal MCK. Furthermore, a control signal is applied to each of terminal BW, terminal CE, and terminal GW. A chip enable signal is applied to terminal CE. A global write enable signal is applied to terminal GW. A byte write enable signal is applied to terminal BW. An address signal is applied to terminal ADDR. Write data is applied to terminal WDA. Read data is applied to terminal RDA. A power gating control signal is applied to terminals PON1 and PON2. The signals applied to terminals PON1 and PON2 may be generated by, for example, control circuit 772.

[0258] The control circuit 772 has a function of controlling the operation of the memory device 700. The control circuit 772 has a function of performing a logical operation on signals provided to the terminals CE, GW, and BW, respectively, to determine an operation mode (e.g., a write operation or a read operation) of the memory device 700. The control circuit 772 also has a function of generating a signal that controls the peripheral circuit 781 so that the operation mode is executed.

[0259] The voltage generation circuit 773 has a function of generating an arbitrary potential for operating the driver circuit 722. For example, the voltage generation circuit 773 has a function of generating an arbitrary potential by inputting a clock signal provided to a terminal MCK in accordance with a signal provided to a terminal WAKE. For example, a signal that controls whether or not the clock signal provided to the terminal MCK is input to the voltage generation circuit 773 is provided to the terminal WAKE.

[0260] The peripheral circuit 781 has a function of writing and reading data to and from the memory cells 741. The peripheral circuit 781 has a function of generating various signals for controlling the operation of the memory cells 741, etc. The peripheral circuit 781 has a row decoder 782, a column decoder 784, a row driver 783, a column driver 785, a data driver 786, an input circuit 787, and an output circuit 788.

[0261] The row decoder 782 and the column decoder 784 have the function of decoding an address signal applied to the terminal ADDR. The row decoder 782 has the function of specifying a row to be accessed. The column decoder 784 has the function of specifying a column to be accessed. The row driver 783 has the function of selecting the row specified by the row decoder 782 and applying a desired signal to, for example, the corresponding memory cell 741. The column driver 785 has the function of selecting the column specified by the column decoder 784 and applying a desired signal to, for example, the corresponding memory cell 741.

[0262] The data driver 786 has a function of writing and reading data to and from the memory cells 741 selected by the row driver and the column driver. The input circuit 787 has a function of holding data provided to a terminal WDA from outside the memory device 700. The data (data Din) held in the input circuit 787 is written to the memory cells 741 via the data driver 786. The data stored in the memory cells 741 is read out to the output circuit 788 via the data driver 786. The output circuit 788 has a function of holding the read data (data Dout). It also has a function of outputting the held data from a terminal RDA to outside the memory device 700.

[0263] In the memory device 700 shown in Figure 29, for example, the row driver 783 has the function of supplying desired signals to the wirings WL[1] to WL[M], and the column driver 785 and the data driver 786 have the function of exchanging data with the wirings BL[1] to BL[N].

[0264] The power switch 761 has a function of controlling whether or not the potential applied to the terminal VMD is supplied to the peripheral circuit 771. The power switch 762 has a function of controlling whether or not the potential applied to the terminal VMH is supplied to the row driver 783. Here, for example, a high power supply potential (e.g., potential VDD) for operating the drive circuit 722 is applied to the terminal VMD, and a low power supply potential (e.g., potential VSS) is applied to the terminal VMS. Also, for example, a high power supply potential (e.g., a potential higher than potential VDD) for operating the memory cell 741 and the like is applied to the terminal VMH. The power switch 761 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON1. The power switch 762 is controlled to a conductive state or a non-conductive state by a signal applied to the terminal PON2.

[0265] Here, it is preferable to use transistors with small off-state current as each of the power switches 761 and 762. This can reduce the current that flows through the power switches when the power switches are turned off, for example, and therefore reduce power consumption in the power-off state. It is also preferable to use transistors with large on-state current as each of the power switches 761 and 762. This can reduce loss when the power switches are turned on, for example, and therefore reduce power consumption in the power-on state.

[0266] As a transistor with low off-state current, for example, an OS transistor may be used for each of the power switches 761 and 762. Various oxide semiconductors can be used for the OS transistor. In particular, an oxide semiconductor that can exhibit low off-state current and high on-state current is preferably used. Examples of oxide semiconductors that can exhibit low off-state current and high on-state current include indium oxide.

[0267] Note that the circuits and terminals of the driver circuit 722 may be omitted as appropriate. Other circuits and terminals may be added as appropriate.

[0268] In one embodiment of the present invention, the above-described storage device 100A can be applied to part of the storage device 700. Furthermore, the above-described storage device 100B can be applied to part of the storage device 700.

[0269] For example, when memory device 100A is applied to memory device 700, memory array 110 can be applied to memory array 721, and memory cell 101 can be applied to memory cell 741. Furthermore, driver 111A can be applied to row driver 783. Figure 29 shows a driver circuit unit 783a to which driver circuit unit 112A can be applied, and a driver circuit unit 783b to which driver circuit unit 113A can be applied.

[0270] 26 is applied to the memory device 700, the drive circuit unit 783b has a plurality of drive circuits arranged for each row. In this case, the row decoder 782 can be provided separately for the drive circuit unit 783a and the drive circuit unit 783b.

[0271] The same applies to the case where the storage device 100B is applied to the storage device 700, for example.

[0272] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0273] Embodiment 2 In this embodiment, a structural example of a transistor that can be used in the memory device described in the above embodiment will be described.

[0274] <Structure Example of Semiconductor Device> For the semiconductor device of one embodiment of the present invention, transistors with various structures can be used. In addition, a structure in which transistors with various structures are stacked can be used.

[0275] 30A and 30B are cross-sectional views of the semiconductor device 150. Note that Fig. 30A illustrates a cross-sectional view of the transistor 310 and the transistor 200 in the channel length direction (illustrated as the X direction). Fig. 30B illustrates a cross-sectional view of the transistor 310 and the transistor 200 in the channel width direction (illustrated as the Y direction).

[0276] As shown in FIGS. 30A and 30B, the transistor 200 is provided above the transistor 310 (shown in the Z direction).

[0277] 30A , one of the source and drain of transistor 310 (here, corresponding to low-resistance region 314a) is connected to conductive layer 330a via conductive layer 328a and the like. The other of the source and drain of transistor 310 (here, corresponding to low-resistance region 314b) is connected to conductive layer 330b via conductive layer 328b and the like. One of the source and drain of transistor 200 (here, corresponding to conductive layer 242a) is connected to conductive layer 248a via conductive layer 243a and the like. The other of the source and drain of transistor 200 (here, corresponding to conductive layer 242b) is connected to conductive layer 248b via conductive layer 243b and the like. The conductive layer 330d is connected to conductive layer 248d via conductive layer 356d, conductive layer 218d, conductive layer 246d, and the like. 30B , the gate electrode of transistor 310 (corresponding to conductive layer 316 here) is connected to conductive layer 330c via conductive layer 328c etc. The gate electrode of transistor 200 (corresponding to conductive layer 260 here) is connected to conductive layer 248c via conductive layer 246c etc.

[0278] The conductive layer may be formed of a conductor having a function as a plug or wiring.

[0279] In this specification and the like, a conductor that functions as a plug or wiring may have multiple components collectively assigned the same reference symbol. The wiring and the plug may be integrated. That is, a portion of the conductor may function as a wiring and a portion of the conductor may function as a plug.

[0280] For each plug or wiring, a conductive material such as a metal material, an alloy material, a nitride material, or an oxide material can be used in a single layer or a laminated layer.

[0281] In particular, it is preferable to use a high-melting-point material that has both heat resistance and conductivity for each plug or wiring. Examples of such materials include tungsten and molybdenum. It is also preferable to use a low-resistance conductive material that can reduce wiring resistance for each plug or wiring. Examples of such materials include aluminum and copper.

[0282] [Transistor 310] The transistor 310 will be described.

[0283] As shown in Figures 30A and 30B, the transistor 310 is provided over a substrate 311 and has a conductive layer 316 that functions as a gate electrode, an insulating layer 315 that functions as a gate insulating film, a semiconductor region 313 that functions as a channel formation region, a low-resistance region 314a that functions as one of the source region and the drain region, and a low-resistance region 314b that functions as the other of the source region and the drain region.

[0284] The transistor 310 also has an element isolation layer 318 buried in the substrate 311. The element isolation layer 318 is provided between two adjacent transistors 310.

[0285] The substrate 311 may be, for example, a semiconductor substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon, germanium, or the like, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Other examples include a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Other examples include a substrate in which a semiconductor is provided on an insulator substrate, or a substrate in which a semiconductor is provided on a conductor substrate. The semiconductor substrate may be a single-crystal semiconductor or a polycrystalline semiconductor.

[0286] In this embodiment, a case where a single crystal silicon substrate is used as the substrate 311 will be described as an example.

[0287] When a single crystal silicon substrate is used as the substrate 311, the transistor 310 can be said to be a Si transistor (a transistor including silicon in a channel formation region).

[0288] The transistor 310 may be either a p-channel type or an n-channel type. For example, by connecting the gate of an n-channel transistor 310 and the gate of a p-channel transistor 310, a CMOS circuit (e.g., a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be configured.

[0289] 30B , the transistor 310 can have a so-called Fin structure in which the top surface and the side surfaces in the channel width direction of a semiconductor region 313 made of a part of a substrate 311 are covered with a conductive layer 316 via an insulating layer 315. This increases the effective channel width, thereby improving the on-state characteristics of the transistor 310. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 310.

[0290] The transistor 310 preferably includes a semiconductor such as a silicon-based semiconductor, and preferably includes single crystal silicon, in the region where the channel of the semiconductor region 313 is formed, the region nearby the region, the low-resistance region 314a that serves as one of the source and drain regions, and the low-resistance region 314b that serves as the other of the source and drain regions. Alternatively, the transistor 310 may be formed of a material containing, for example, germanium, silicon germanium, gallium arsenide, or gallium aluminum arsenide. Alternatively, the transistor 310 may be configured using silicon whose effective mass is controlled by applying stress to the crystal lattice to change the lattice spacing. Alternatively, the transistor 310 may be a high electron mobility transistor (HEMT) using, for example, gallium arsenide, gallium aluminum arsenide, or the like.

[0291] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0292] For example, a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, can be used as the conductive layer 316. Alternatively, for example, a conductive material such as a metal material, an alloy material, or an oxide material can be used.

[0293] Note that the work function is determined by the material of a conductor; therefore, the threshold voltage of a transistor can be adjusted by selecting the material of the conductor.

[0294] For example, a material such as titanium nitride or tantalum nitride is preferably used as the conductive layer 316. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a stack of metal materials such as tungsten or aluminum. In particular, in terms of heat resistance, it is preferable to use a stack of tungsten, for example.

[0295] An insulating layer 320 , an insulating layer 322 , an insulating layer 324 , and an insulating layer 326 are stacked in this order to cover the transistor 310 .

[0296] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride is preferably used for the insulating layer 320, the insulating layer 322, the insulating layer 324, and the insulating layer 326. In particular, silicon oxide or silicon oxynitride is preferably used because of its thermal stability.

[0297] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0298] The insulating layer 322 may function as a planarizing film that planarizes steps caused by the transistor 310 or the like provided thereunder. For example, the top surface of the insulating layer 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0299] As the insulating layer 324, it is preferable to use an insulator having barrier properties that prevent impurities such as hydrogen from diffusing from the substrate 311 or the transistor 310, which are located below the insulating layer 324, to a region located above the insulating layer 324.

[0300] The insulator having a barrier property against hydrogen can be, for example, silicon nitride formed by chemical vapor deposition (CVD), or a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0301] Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor, such as the transistor 200 described later, the characteristics of the semiconductor element may deteriorate. Therefore, an insulator that suppresses hydrogen diffusion is preferably used between a region where the transistor 200 is provided and a region where the transistor 310 is provided. Specifically, the insulator that suppresses hydrogen diffusion is an insulator that releases a small amount of hydrogen.

[0302] The insulating layer 326 preferably has a lower dielectric constant than the insulating layer 324. For example, the relative dielectric constant of the insulating layer 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulating layer 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 324. By using a material with a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wirings.

[0303] Conductive layers 328 (such as conductive layers 328a, 328b, and 328c) are embedded in the insulating layers 320 and 322. Conductive layers 330 (such as conductive layers 330a, 330b, 330c, and 330d) are embedded in the insulating layers 324 and 326.

[0304] Each of the conductive layer 328 and the conductive layer 330 functions as a plug or a wiring.

[0305] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Figures 30A and 30B, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. Furthermore, a conductive layer 356 (such as a conductive layer 356d) is embedded in the insulating layer 350, the insulating layer 352, and the insulating layer 354.

[0306] The conductive layer 356 functions as a plug or a wiring. For example, the same material as the conductive layer 328 and the conductive layer 330 can be used for the conductive layer 356. In particular, it is preferable to use a conductor having a barrier property against hydrogen.

[0307] The insulating layers 350, 352, and 354 can be formed using materials similar to those of the insulating layers 324, 322, and 326. In particular, it is preferable to use an insulator that has a barrier property against hydrogen.

[0308] Here, a conductor having a barrier property against hydrogen is formed in the opening of the insulating layer 350 having a barrier property against hydrogen. With this structure, the transistor 310 and the transistor 200 can be separated by the conductor having a barrier property against hydrogen. Therefore, diffusion of hydrogen from the transistor 310 to the transistor 200 can be suppressed.

[0309] For example, tantalum nitride may be used as a conductor having a barrier property against hydrogen. Alternatively, a stack of tantalum nitride and highly conductive tungsten may be used. By using a stack of tantalum nitride and tungsten as the conductor, the conductor can suppress the diffusion of hydrogen while maintaining the conductivity of the wiring.

[0310] That is, by forming the conductive layer 356 as a stack of tantalum nitride and tungsten, diffusion of hydrogen from the transistor 310 can be suppressed while maintaining the conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer of the conductive layer 356 having a barrier property against hydrogen be in contact with the insulating layer 350 having a barrier property against hydrogen.

[0311] Although the wiring layer including the conductive layer 356 has been described here, the present invention is not limited to this. The wiring layer including the conductive layer 356 does not necessarily have to be provided, or two or more wiring layers similar to the wiring layer including the conductive layer 356 may be provided.

[0312] Note that the transistor 310 shown in FIGS. 30A and 30B is just an example, and the present invention is not limited to this configuration.

[0313] An insulating layer 212, an insulating layer 214, and an insulating layer 216 are stacked in this order over the insulating layer 354 and the conductive layer 356. The transistor 200 is provided over the insulating layer 216. An insulating layer 275, an insulating layer 280, an insulating layer 282, an insulating layer 283, and an insulating layer 285 are stacked in this order to cover the transistor 200.

[0314] In the insulating layer 212, the insulating layer 214, and the insulating layer 216, for example, a conductive layer 218 (such as the conductive layer 218d) is embedded.

[0315] The conductive layer 218 functions as a plug or a wiring. For the conductive layer 218, for example, the same materials as those of the conductive layer 328 and the conductive layer 330 can be used.

[0316] In particular, the conductive layer 218 and a region in contact with the insulating layer 214 are preferably made of a conductor that has a barrier property against both oxygen and impurities such as hydrogen and water. With such a structure, the transistor 310 and the transistor 200 can be separated by a conductor that has a barrier property against both oxygen and impurities such as hydrogen and water, and diffusion of hydrogen from the transistor 310 to the transistor 200 can be suppressed.

[0317] An insulating layer 288 is provided on the insulating layer 285 .

[0318] The parasitic capacitance generated between wirings can be reduced by using, for example, a material with a relatively low dielectric constant as the insulating layer 288. For example, the same material as the insulating layer 212 or the insulating layer 216 can be used as the insulating layer 288.

[0319] For example, conductive layers 246 (such as conductive layers 246c and 246d) are embedded in the insulating layers 275, 280, 282, 283, and 285. Furthermore, for example, conductive layers 248 (such as conductive layers 248a, 248b, 248c, and 248d) are embedded in the insulating layer 288.

[0320] Each of the conductive layers 246 and 248 functions as a plug or a wiring.

[0321] [Transistor 200] A configuration example of the transistor 200 will be described with reference to FIGS. 31A to 33C.

[0322] FIG. 31A is a top view of the transistor 200. FIG. 31B is a cross-sectional view of the portion indicated by the dashed dotted line A1-A2 in FIG. 31A and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 31C is a cross-sectional view of the portion indicated by the dashed dotted line A3-A4 in FIG. 31A and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 31D is a cross-sectional view of the portion indicated by the dashed dotted line A5-A6 in FIG. 31A. Note that some elements are omitted in the top view of FIG. 31A for clarity. Some elements may also be omitted in the subsequent top views.

[0323] The transistor 200 has a conductive layer 205, an insulating layer 221 on the conductive layer 205, an insulating layer 222 on the insulating layer 221, an insulating layer 224 on the insulating layer 222, a semiconductor layer 230 on the insulating layer 224, conductive layers 242a and 242b on the semiconductor layer 230, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0324] In the transistor 200, the conductive layer 260 functions as a first gate electrode (which can also be referred to as an upper gate electrode or a top gate electrode), and the insulating layer 250 functions as a first gate insulating film. The conductive layer 205 functions as a second gate electrode (which can also be referred to as a lower gate electrode or a bottom gate electrode), and the insulating layers 224, 222, and 221 each function as a second gate insulating film. The conductive layer 242a functions as one of a source electrode and a drain electrode, and the conductive layer 242b functions as the other of the source electrode and the drain electrode.

[0325] Note that the transistor 200 does not necessarily have to include the conductive layer 205. In this case, the conductive layer 260 can be simply called a gate electrode, and the insulating layer 250 can be simply called a gate insulating film.

[0326] An insulating layer 275 is provided over the conductive layer 242a and the conductive layer 242b, and an insulating layer 280 is provided over the insulating layer 275. An opening 289 reaching the insulating layer 222 and the semiconductor layer 230 is formed in the insulating layer 280 and the insulating layer 275, and the opening 289 overlaps with a region between the conductive layer 242a and the conductive layer 242b. In a top view, a side surface of the insulating layer 280 in the opening 289 coincides with a side surface of the conductive layer 242a and a side surface of the conductive layer 242b.

[0327] The insulating layer 250 and the conductive layer 260 are disposed inside the opening 289. An insulating layer 282 is provided in contact with the top surface of the insulating layer 280, the top end of the insulating layer 250, and the top surface of the conductive layer 260. An insulating layer 283 is provided over the insulating layer 282. An insulating layer 216 is provided under the insulating layer 221, an insulating layer 214 is provided under the insulating layer 216 and the conductive layer 205, and an insulating layer 212 is provided under the insulating layer 214. The insulating layer 212, the insulating layer 214, the insulating layer 280, the insulating layer 282, the insulating layer 283, and the insulating layer 285 function as interlayer films.

[0328] Openings reaching the conductive layer 242a are formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layers 243a and 241a are provided in the openings. The insulating layer 241a is provided in contact with the inner wall of the opening, and the conductive layer 243a is provided inside the insulating layer 241a. Furthermore, openings reaching the conductive layer 242b are formed in the insulating layers 285, 283, 282, 280, and 275, and the conductive layers 243b and 241b are provided in the openings. The insulating layer 241b is provided in contact with the inner wall of the opening, and the conductive layer 243b is provided inside the insulating layer 241b. The conductive layers 243a and 243b function as vias that connect a wiring or the like provided on the transistor 200 to the source or drain of the transistor 200.

[0329] In the semiconductor layer 230, a channel formation region and a source region and a drain region sandwiching the channel formation region are formed, as in the transistor 200. That is, the semiconductor layer 230 has a channel formation region, a source region, and a drain region. At least a part of the channel formation region overlaps with the conductive layer 260. The source region overlaps with the conductive layer 242a, and the drain region overlaps with the conductive layer 242b. Note that the source region and the drain region can be interchanged. The source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region. The semiconductor layer 230 may have a single-layer structure or a stacked structure of two or more layers.

[0330] A transistor according to one embodiment of the present invention includes a metal oxide (also referred to as an oxide semiconductor) that functions as a semiconductor in a semiconductor layer 230 including a channel formation region. That is, the transistor can be referred to as an OS transistor. Note that in this specification and the like, a semiconductor layer including an oxide semiconductor can be referred to as an oxide semiconductor layer. Furthermore, since the semiconductor layer 230 includes a metal oxide, the semiconductor layer 230 can be referred to as a metal oxide layer.

[0331] An OS transistor has an oxygen vacancy (V Ｏ The presence of oxygen vacancies and impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region is made i-type (intrinsic) or substantially i-type.

[0332] On the other hand, the source and drain regions of an OS transistor have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of an OS transistor are preferably n-type regions having a high carrier concentration and low resistance, as compared with a channel formation region, due to a high concentration of H or an impurity such as hydrogen, nitrogen, or a metal element.

[0333] The band gap of a metal oxide functioning as a semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap for a semiconductor layer, the off-state current of a transistor can be reduced. Since an OS transistor has a small off-state current, the power consumption of a semiconductor device can be sufficiently reduced.

[0334] Here, when an excessive amount of oxygen is supplied to the channel formation region of the semiconductor layer 230, electron traps due to the excess oxygen are formed in the insulating layer 250. As a result, the OS transistor is more likely to experience positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0335] Therefore, in one embodiment of the present invention, the impurity concentration in the channel formation region of the semiconductor layer 230 is preferably low. Furthermore, an appropriate amount of oxygen is preferably supplied to the channel formation region of the semiconductor layer 230. Furthermore, it is preferable to reduce the excessive amount of oxygen in the channel formation region of the semiconductor layer 230.

[0336] The semiconductor layer 230 preferably includes indium oxide. In this case, the semiconductor layer 230 includes indium and oxygen. For example, the semiconductor layer 230 preferably includes an indium oxide film. The higher the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements included in the metal oxide (also referred to as the indium (In) content), the higher the field-effect mobility of the transistor. Therefore, by using indium oxide for the semiconductor layer 230, the transistor can have a large on-state current and high frequency characteristics.

[0337] Furthermore, the indium oxide film preferably has crystallinity. For example, the indium oxide film preferably has crystal grains. Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains. In polycrystalline films, crystal grain boundaries are observed.

[0338] When a metal oxide contains indium and zinc, the metal oxide may have a c-axis aligned crystalline (CAAC) structure. The CAAC structure has fewer crystal grain boundaries in the a-b plane than a polycrystalline structure. Examples of metal oxides containing indium and zinc include indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)) and indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO).

[0339] In a crystalline oxide semiconductor layer, an indium oxide film is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO film. Therefore, it can be said that an indium oxide film is a film through which one or both of hydrogen and oxygen are more easily supplied and from which one or both of hydrogen and oxygen are more easily discharged than, for example, an IGZO film. Note that it can be said that an indium oxide film is a film that is highly permeable to one or both of hydrogen and oxygen than, for example, an IGZO film. In other words, it can be said that an indium oxide film is a film that has a lower barrier property against one or both of hydrogen and oxygen than, for example, an IGZO film.

[0340] 31A to 31D show an example in which the semiconductor layer 230 has a single-layer structure. The semiconductor layer 230 can also have a stacked structure of two or more layers. For example, when the semiconductor layer 230 has a two-layer structure of a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer 230 described above as the first semiconductor layer, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the first semiconductor layer as the second semiconductor layer. In this case, the first semiconductor layer can mainly function as a current path. That is, the first semiconductor layer has a channel formation region on the surface on the second semiconductor layer side and in the vicinity thereof.

[0341] The above-described structure can reduce carriers trapped at the interface of the first semiconductor layer and its vicinity. In addition, the channel can be located away from the surface of the insulating layer 250, reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0342] Examples of metal oxides that can be used for the second semiconductor layer include indium gallium oxide (In—Ga oxide), In—Zn oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), In—Ga—Zn oxide, indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), and indium tin oxide containing silicon oxide (ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and aluminum tin oxide (Al—Sn oxide) can be used.

[0343] Specifically, the In-Zn oxide used in the second semiconductor layer can have a composition of In:Zn = 1:1 [atomic ratio] or thereabouts, In:Zn = 2:1 [atomic ratio] or thereabouts, or In:Zn = 4:1 [atomic ratio] or thereabouts. Furthermore, the IGZO used in the second semiconductor layer can have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or thereabouts, In:Ga:Zn = 1:3:2 [atomic ratio] or thereabouts, or In:Ga:Zn = 1:3:4 [atomic ratio] or thereabouts. Note that a composition in the vicinity includes a range of plus or minus 30% of the desired atomic ratio.

[0344] The crystallinity of the metal oxide included in the second semiconductor layer is not particularly limited. For example, the second semiconductor layer may include at least one of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0345] Although not shown, in the transistor 200, a crystalline portion may be provided on part of the insulating layer 224, and the semiconductor layer 230 may be provided to cover the crystalline portion.

[0346] The crystalline portion has crystals. The crystalline portion functions as a seed or a nucleus when a process for increasing the crystallinity of the semiconductor layer 230 is performed. In other words, the crystalline portion functions as a seed or a nucleus when crystals grow in the semiconductor layer 230. In this specification and the like, the crystalline portion or the crystals contained in the crystalline portion can be referred to as a seed crystal or a crystal nucleus.

[0347] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). When indium oxide is used for the semiconductor layer 230, the crystal portion preferably has, for example, a hexagonal or trigonal crystal structure. In this case, the crystal portion has a crystal with a <001> crystal orientation relative to the surface or surface on which the crystal portion is formed, thereby forming the semiconductor layer 230 having a crystal with a <111> crystal orientation. When the crystal of the crystal portion has a <001> crystal orientation relative to the surface or surface on which the crystal portion is formed, the c-axis of the crystal is perpendicular to the surface or surface on which the crystal portion is formed. Note that a crystal with a hexagonal or trigonal crystal structure can sometimes be referred to as a crystal with a layered structure, and therefore the above structure can be considered as a structure in which the semiconductor layer 230 having a crystal with a cubic crystal structure is formed on a crystal portion having a crystal with a layered structure. In other words, it can also be considered as a stacked structure manufactured using a heteroepitaxial growth technique or a technique similar to heteroepitaxial growth.

[0348] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, in this specification, due to formatting restrictions, numbers may be expressed by adding a minus sign (-) before them instead of adding a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0349] In this specification, the crystal orientation of a crystal refers to the orientation relative to the surface of a film containing the crystal or the surface on which the crystal is formed. For example, a crystal with a crystal orientation of <100> is said to be a crystal whose (100) plane is parallel to the surface of a film containing the crystal or the surface on which the crystal is formed.

[0350] Specifically, zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), In—Al—Zn oxide, In—Ga—Zn oxide, or In—Sn—Zn oxide can be used as the crystal portion. It is preferable to use In—Ga—Zn oxide as the crystal portion. In this case, the crystal portion contains indium, gallium, zinc, and oxygen. Specifically, it is preferable to use a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition thereabout, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition thereabout. Metal oxides with these compositions are suitable for the crystal portion because they easily form a layered structure.

[0351] In—Ga—Zn oxide and In—Sn—Zn oxide are likely to have a CAAC structure. When an oxide having a CAAC structure is used for the crystal portion, the c-axis of the crystal nucleus is perpendicular to the surface of the crystal portion or the surface on which it is formed. In other words, by using an oxide that is likely to have a CAAC structure for the crystal portion, it is possible to improve the controllability of the crystal orientation of the crystal nucleus.

[0352] When an oxide that easily has a CAAC structure is used for the crystal portion, the semiconductor layer 230 can be formed having crystals with a <111> crystal orientation.

[0353] The crystal portion can also be made of an oxide having a cubic crystal structure. When the crystal of the crystal portion has the same crystal structure as the crystal of the semiconductor layer 230, the semiconductor layer 230 can grow epitaxially using the crystal portion as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. Note that crystals of oxides containing Group 3 elements in the periodic table tend to have a cubic crystal structure. Furthermore, the Group 3 elements in the crystals are primarily present as trivalent cations. Therefore, the crystal portion preferably contains at least one element that can become a trivalent cation. The element that can become a trivalent cation contained in the crystal portion is preferably scandium, yttrium, cerium, gadolinium, erbium, ytterbium, or the like.

[0354] The crystal portion can be made of, for example, an oxide containing one or both of yttrium and zirconium, erbium oxide, etc. Examples of oxides containing one or both of yttrium and zirconium include yttrium oxide, zirconium oxide, and yttrium zirconium oxide.

[0355] Furthermore, indium oxide may be used for the crystalline portion. By using indium oxide for the crystalline portion, the semiconductor layer 230 can be homoepitaxially grown using the crystalline portion as a nucleus, thereby improving the crystallinity of the semiconductor layer 230. In this case, the crystal orientation of the crystals in the crystalline portion and the crystal orientation of the crystals in the semiconductor layer 230 coincide with each other.

[0356] There are no particular limitations on the material that can be used for the crystal portion. The crystal portion may be made of an insulating material, a semiconductor material, or a conductive material. When a semiconductor material is used for the crystal portion, the crystal portion may be considered as part of the semiconductor layer 230.

[0357] The crystal portion may have, in a top view, a substantially circular shape such as a circle or an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, or a star-shaped polygon, or a shape with rounded corners. For example, the crystal portion may have a region extending along the top surface of the insulating layer 224. For example, the crystal portion may be provided in contact with the top surface of the insulating layer 224, or may be provided so as to fill a recess or an opening provided in the insulating layer 224. The transistor 200 may not have a crystal portion, for example. For example, the crystal portion may be provided outside the transistor formation region, and the crystal portion may be removed after a process for increasing the crystallinity of the semiconductor layer 230 is performed.

[0358] 32 to 33C are enlarged cross-sectional views of the transistor 200 shown in FIGS. 31A to 31D in the channel length direction.

[0359] By providing an insulating layer containing excess oxygen near the oxide semiconductor layer and performing heat treatment, oxygen can be supplied from the insulating layer to the oxide semiconductor layer, thereby reducing oxygen vacancies. However, excessive oxygen supplied to the source or drain region may cause a decrease in the on-state current or field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface may cause variations in the characteristics of the transistor. Furthermore, excessively large amounts of oxygen supplied from the insulating layer to the oxide semiconductor layer may adversely affect the electrical characteristics and reliability of the transistor. Furthermore, oxygen may diffuse into conductive layers such as the gate electrode, source electrode, and drain electrode, oxidizing the conductive layers and reducing their conductivity.

[0360] First, it is preferable to form at least one of an insulating layer having a barrier property against hydrogen and an insulating layer having a function of capturing or fixing hydrogen near the semiconductor layer 230, thereby reducing the hydrogen concentration in the channel formation region of the semiconductor layer 230 and its vicinity.

[0361] At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against hydrogen. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against impurities. At least one of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 preferably functions as a barrier insulating layer against oxygen. Note that all of the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283 do not necessarily need to be provided. As long as the insulating layer has sufficient barrier properties against hydrogen, impurities, oxygen, and the like, the insulating layer can be formed by appropriately selecting from the insulating layer 212, the insulating layer 214, the insulating layer 221, the insulating layer 222, the insulating layer 275, the insulating layer 282, and the insulating layer 283. For example, a structure can be used in which the insulating layer 216 and the conductive layer 205 are formed in contact with the upper surface of the insulating layer 212 without providing the insulating layer 214.

[0362] The insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 preferably have a function of suppressing diffusion of hydrogen. For example, the insulating layer 212, the insulating layer 221, the insulating layer 275, and the insulating layer 283 may be formed using silicon nitride, which has a higher hydrogen barrier property.

[0363] The insulating layer 214, the insulating layer 222, and the insulating layer 282 preferably have a function of capturing or fixing hydrogen. For example, aluminum oxide may be used for the insulating layer 214 and the insulating layer 282. For example, hafnium oxide, which is a high-k material, is preferably used for the insulating layer 222, which functions as the second gate insulating film.

[0364] 32 , by providing an insulating layer 212 having a function of suppressing hydrogen diffusion under the transistor 200, it is possible to suppress diffusion of hydrogen from the layer below the transistor 200. Furthermore, by providing an insulating layer 214 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 216 or the like can be captured or fixed in the insulating layer 214. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0365] Furthermore, by providing the insulating layer 221 having a function of suppressing hydrogen diffusion under the semiconductor layer 230, it is possible to suppress diffusion of hydrogen from below the semiconductor layer 230. Furthermore, by providing the insulating layer 222 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 224 or the like can be captured or fixed in the insulating layer 222. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0366] Furthermore, by providing an insulating layer 275 having the function of suppressing the diffusion of hydrogen so as to cover the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc., it is possible to suppress the diffusion of hydrogen from the insulating layer 280 to the semiconductor layer 230, the conductive layer 242a, the conductive layer 242b, etc.

[0367] Furthermore, by providing the insulating layer 283 having a function of suppressing hydrogen diffusion over the transistor 200, it is possible to suppress diffusion of hydrogen from above the transistor 200. Furthermore, by providing the insulating layer 282 having a function of capturing or fixing hydrogen, hydrogen contained in the insulating layer 280 or the like can be captured or fixed to the insulating layer 282. This makes it possible to reduce the hydrogen concentration in the semiconductor layer 230 and its vicinity.

[0368] In this manner, by surrounding the transistor 200 from above and below with barrier insulating layers against hydrogen, diffusion of hydrogen into the oxide semiconductor can be reduced, and the hydrogen concentration in the channel formation region can be reduced, thereby improving the electrical characteristics and reliability of the transistor 200.

[0369] Furthermore, excess oxygen is preferably contained in the insulating layer 280. By supplying the oxygen to the semiconductor layer 230 through the insulating layer 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0370] The insulating layer 282 is preferably formed by a sputtering method in an atmosphere containing oxygen gas, which allows oxygen to be added to the insulating layer 280. The insulating layer 282 may have a single-layer structure or a stacked structure of two or more layers.

[0371] As described above, by performing heat treatment on the insulating layer 280 containing excess oxygen, a suitable amount of oxygen can be supplied to the semiconductor layer 230 through the insulating layer 250. In the heat treatment, the insulating layers 282 and 283 having a barrier property against oxygen are formed on the insulating layer 280, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, the insulating layer 275 having a barrier property against oxygen is formed between the insulating layer 280 and the semiconductor layer 230, the conductive layer 242a, and the conductive layer 242b, so that the oxygen contained in the insulating layer 280 can be prevented from diffusing excessively from the insulating layer 280. Furthermore, by performing the heat treatment with openings formed in parts of the insulating layer 280, the insulating layer 282, and the insulating layer 283, part of the oxygen contained in the insulating layer 280 can be diffused outward, and the amount of oxygen supplied from the insulating layer 280 to the semiconductor layer 230 can be adjusted.

[0372] 32 shows an example in which the semiconductor layer 230 has a single-layer structure. Note that the semiconductor layer 230 can have a stacked structure of two or more layers. As shown in FIG. 33A, the semiconductor layer 230 can have a two-layer structure of a semiconductor layer 230_1 and a semiconductor layer 230_2 over the semiconductor layer 230_1.

[0373] 33A illustrates a structure in which the insulating layer 250 is in contact with the top surface of the semiconductor layer 230_2, but one embodiment of the present invention is not limited to this. For example, as shown in FIG. 33B , a structure can be adopted in which the semiconductor layer 230_2 in a region overlapping with the opening 289 is removed and the insulating layer 250 is in contact with the side surface of the semiconductor layer 230_2 and the top surface of the semiconductor layer 230_1. With such a structure, the distance between the conductive layer 260 and the semiconductor layer 230_1 can be shortened. Therefore, an electric field from the gate electrode can be suitably applied to the semiconductor layer 230_1.

[0374] The insulating layer 250 preferably has a structure that allows oxygen to diffuse from the insulating layer 280 to the semiconductor layer 230 and prevents the conductive layers 242 a, 242 b, and 260 from being oxidized.

[0375] The insulating layer 250 is formed within the opening 289 in contact with the top surface of the insulating layer 222, the side surface of the insulating layer 224, the side surface and top surface of the semiconductor layer 230, the side surface of the conductive layer 242a, the side surface of the conductive layer 242b, the side surface of the insulating layer 275, and the side surface of the insulating layer 280.

[0376] 31B shows an example in which the insulating layer 250 has a single layer structure. The insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 into two or more types of films, multiple functions can be imparted to the insulating layer 250. Examples of the functions of the insulating layer 250 include a function of extracting excess oxygen from the semiconductor layer 230, a function of extracting hydrogen from the semiconductor layer 230, and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0377] For example, as shown in FIG. 32, the insulating layer 250 preferably has a stacked structure of an insulating layer 250_1 in contact with the semiconductor layer 230, an insulating layer 250_2 over the insulating layer 250_1, and an insulating layer 250_3 over the insulating layer 250_2.

[0378] The insulating layer 250_1 can be formed using any of the materials applicable to the insulating layer 250. For example, the insulating layer 250_1, which has regions in contact with the side surfaces of the conductive layer 242a and the conductive layer 242b, has a function of capturing or adhering oxygen, thereby preventing the side surfaces of the conductive layer 242a and the conductive layer 242b from being oxidized and forming an oxide film on the side surfaces. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 200. Furthermore, this structure can reduce the amount of oxygen in the insulating layer 250_2 absorbed by the conductive layer 242a and the conductive layer 242b. Therefore, an appropriate amount of oxygen can be supplied from the insulating layer 250_2 to the semiconductor layer 230, thereby reducing oxygen vacancies in the channel formation region of the semiconductor layer 230.

[0379] Furthermore, by providing the insulating layer 250_1 between the insulating layer 280 and the insulating layer 250_2 and between the insulating layer 250_2 and the semiconductor layer 230, excessive supply of oxygen from the insulating layer 280 to the semiconductor layer 230 can be suppressed, and an appropriate amount of oxygen can be supplied to the semiconductor layer 230. Therefore, the amount of oxygen in the channel formation region of the semiconductor layer 230 and its vicinity can be controlled to an appropriate amount, thereby preventing an excessive positive shift of the transistor 200 and improving reliability. Furthermore, excessive oxidation of the source and drain regions can be suppressed, which can reduce the on-state current or the field-effect mobility of the transistor 200.

[0380] By adopting the above-described structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a transistor with excellent electrical characteristics. Furthermore, by adopting the above-described structure, the transistor can have excellent electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0381] Furthermore, a high-k material with a high dielectric constant can be used for the insulating layer 250_1. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for the insulating layer 250_1 makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating film. Furthermore, it makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulating film.

[0382] From the above, it is preferable to use an oxide containing one or both of aluminum and hafnium for the insulating layer 250_1, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide having an amorphous structure is preferably used because an amorphous film can be formed relatively easily using an ALD method. Aluminum oxide has a function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used for the insulating layer 250_1. Alternatively, hafnium oxide has a high function of capturing or fixing oxygen and hydrogen, and therefore can be suitably used for the insulating layer 250_1.

[0383] For example, the insulating layer 250_2 preferably includes a material with a low dielectric constant, such as a silicon oxide film or a silicon oxynitride film.

[0384] Silicon oxide or silicon nitride is an insulating material with high dielectric strength. This can reduce the gate leakage current of a transistor. Furthermore, a silicon oxide film or a silicon oxynitride film is also a film with high hydrogen permeability. Therefore, the insulating layer 250 may have a three-layer structure including an insulating layer 250_2, an insulating layer 250_1 on the insulating layer 250_2, and an insulating layer 250_3 on the insulating layer 250_1. With this structure, hydrogen in the semiconductor layer 230 can diffuse into the insulating layer 250_1 through the insulating layer 250_2 and be captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0385] The insulating layer 250_3 preferably has a barrier property against hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Furthermore, the insulating layer 250_3 preferably has a barrier property against oxygen. The insulating layer 250_3 is provided between the channel formation region of the semiconductor layer 230 and the conductive layer 260. With such a structure, oxygen contained in the channel formation region of the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and forming oxygen vacancies in the channel formation region of the semiconductor layer 230. Furthermore, oxygen contained in the semiconductor layer 230 can be prevented from diffusing into the conductive layer 260 and oxidizing the conductive layer 260. The insulating layer 250_3 is preferably at least less permeable to oxygen than the insulating layer 250_2. Furthermore, the insulating layer 250_3 preferably has a function of suppressing diffusion of hydrogen. This can prevent impurities such as hydrogen contained in the conductive layer 260 from diffusing into the semiconductor layer 230. For example, silicon nitride is preferably used as the insulating layer 250_3.

[0386] The insulating layer 250 can have a three-layer structure in which a hafnium oxide film, a silicon oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. The thicknesses of the hafnium oxide film, the silicon oxide film, and the silicon nitride film are 2 nm, 2 nm, and 1 nm, respectively. This structure allows excess oxygen in the semiconductor layer 230 to be discharged to the insulating layer 250, thereby reducing the amount of excess oxygen in the semiconductor layer 230. Furthermore, hydrogen in the semiconductor layer 230 can be captured or fixed. This allows the electrical characteristics and reliability of the transistor 200 to be improved. The insulating layer 250 can also have a three-layer structure in which a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

[0387] 33C , a structure in which an insulating layer 250_4 is provided over the insulating layer 250_2 may be used. The insulating layer 250_4 can be formed using an insulating material that can be used for the insulating layer 250_1. For example, by providing the insulating layer 250_4 having a function of capturing or fixing hydrogen between the insulating layer 250_3 and the insulating layer 250_2, hydrogen contained in the insulating layer 250_2 or the like can be captured or fixed.

[0388] Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side. With such a structure, hydrogen in the semiconductor layer 230 can be diffused to the insulating layer 250_1 or the insulating layer 250_4 and captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 can be reduced.

[0389] The insulating layer 250 is preferably a thin film. For example, the subthreshold swing value (also referred to as S value) can be reduced by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage held constant in the subthreshold region.

[0390] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 20 nm, more preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that it is sufficient that each layer constituting the insulating layer 250 has a region with the above-described thickness in at least a portion thereof.

[0391] Note that the insulating layer 250 having a four-layer structure may not include the insulating layer 250_3. For example, an insulating layer having a function of capturing or fixing oxygen may be used as the insulating layer 250_1, an insulating layer containing a material with a low dielectric constant may be used as the insulating layer 250_2, and an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 250_4. Specifically, the insulating layer 250 may have a three-layer structure in which an aluminum oxide film, a silicon oxide film, and a hafnium oxide film are stacked in this order from the semiconductor layer 230 side.

[0392] In order to thin the insulating layers 250_1 to 250_4 as described above, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method. In addition, in order to form the insulating layers 250_1 to 250_4 in the opening 289 with good coverage, the insulating layers 250_1 to 250_4 are preferably deposited by an ALD method.

[0393] It is preferable to use the ALD process two or more times in forming the insulating layer 250 having a stacked structure of multiple insulating films. For example, it is preferable that two or more of the multiple insulating films included in the insulating layer 250 are formed using the ALD process. By forming at least two or more types of insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 250. Furthermore, for example, it is possible to increase productivity by successively forming two or more types of insulating films using the ALD process.

[0394] Although the insulating layer 250 has been described above as having a three-layer structure or a four-layer structure, one embodiment of the present invention is not limited to this. The insulating layer 250 can have a structure including at least one of the insulating layers 250_1 to 250_4. When the insulating layer 250 includes one, two, or three of the insulating layers 250_1 to 250_4, the manufacturing process of the transistor can be simplified and productivity can be improved.

[0395] The conductive layer 205 is disposed so as to overlap with the semiconductor layer 230 and the conductive layer 260. Here, the conductive layer 205 is provided so as to be embedded in an opening formed in the insulating layer 216. Furthermore, the conductive layer 205 is preferably provided so as to extend in the channel width direction, as shown in FIGS. 31A and 31C . With this structure, when a plurality of transistors are provided, the conductive layer 205 functions as a wiring.

[0396] 32 , the conductive layer 205 preferably includes a conductive layer 205_1 and a conductive layer 205_2. The conductive layer 205_1 is provided in contact with the bottom and inner wall of the opening. The conductive layer 205_2 is provided so as to fill a recess in the conductive layer 205_1 that is formed to conform to the shape of the opening. Here, the height of the top surface of the conductive layer 205 coincides with the height of the top surface of the insulating layer 216.

[0397] Here, the conductive layer 205_1 contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0398] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 205_1, impurities such as hydrogen contained in the conductive layer 205_2 can be prevented from diffusing into the semiconductor layer 230 via the insulating layer 216 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 205_1, oxidation of the conductive layer 205_2 and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 205_1 can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 205_1 preferably contains titanium nitride.

[0399] The conductive layer 205_2 is preferably formed using a conductor with high conductivity. For example, the conductive layer 205_2 is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductive layer 205_2 preferably contains tungsten.

[0400] The conductive layer 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be adjusted by controlling the potential applied to the conductive layer 205 independently of the potential applied to the conductive layer 260. In particular, applying a negative potential to the conductive layer 205 can increase the Vth of the transistor 200 and reduce the off-state current. Therefore, applying a negative potential to the conductive layer 205 can reduce the drain current when the potential applied to the conductive layer 260 is 0 V, compared to when no negative potential is applied.

[0401] 32 shows a stacked structure of the conductive layer 205_1 and the conductive layer 205_2, one embodiment of the present invention is not limited thereto, and the conductive layer 205 may have a single-layer structure or a stacked structure of three or more layers. For example, the conductive layer 205_1 may have a two-layer structure of a tantalum nitride film and a titanium nitride film over the tantalum nitride film, and the conductive layer 205_2 having a tungsten film may be provided over the conductive layer 205_1. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in a lower layer of the transistor 200 can be prevented from diffusing into the conductive layer 205.

[0402] The insulating layer 224 functions as a second gate insulating film together with the insulating layers 221 and 222 .

[0403] The insulating layer 224 preferably includes, for example, a silicon oxide film or a silicon oxynitride film. This allows oxygen to be supplied from the insulating layer 224 to the semiconductor layer 230, thereby reducing oxygen vacancies. Note that the insulating layer 224 may have a stacked structure of two or more layers. In this case, the insulating layer 224 is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0404] The insulating layer 224 is preferably processed into an island shape, similar to the semiconductor layer 230. Thus, when a plurality of transistors 200 are provided, each transistor 200 has an insulating layer 224 of approximately the same size. As a result, the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 in each transistor 200 becomes approximately the same. Therefore, variation in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0405] Furthermore, by providing the insulating layer 224 in an island shape, at least a part of the lower surface of the conductive layer 260 can be provided below the lower surface of the semiconductor layer 230 (see FIG. 31C ). This allows the conductive layer 260 to be provided facing the upper surface and side surface of the semiconductor layer 230, and therefore the electric field of the conductive layer 260 can be applied to the upper surface and side surface of the semiconductor layer 230.

[0406] However, although not shown, the insulating layer 224 does not necessarily have to be processed into an island shape. When multiple transistors are provided on the same substrate, the insulating layer 224 is formed without being processed into an island shape, so that the semiconductor layer 230 of each transistor is formed on the same insulating layer 224. This can reduce variations in the amount of oxygen supplied from the insulating layer 224 to the semiconductor layer 230 of each transistor. Therefore, variations in the electrical characteristics of each transistor can be reduced.

[0407] The conductive layers 242a and 242b are preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such a conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 242a and 242b.

[0408] For the conductive layers 242a and 242b, it is preferable to use a nitride, such as a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. For example, tantalum nitride can be used for the conductive layers 242a and 242b. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, ITO, ITSO, or In—Zn oxide may also be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0409] Alternatively, each of the conductive layers 242a and 242b may have a stacked structure. In this case, the above-mentioned conductive material may be used for the lower layer (layer having a large contact area with the semiconductor layer 230) of the conductive layer 242a and the conductive layer 242b, and a conductive material with higher conductivity may be used for the upper layer of the conductive layer 242a and the conductive layer 242b. For example, tantalum nitride may be used for the lower layer, and tungsten may be used for the upper layer. Alternatively, ITO or ITSO may be used for the lower layer, and tungsten may be used for the upper layer.

[0410] The conductive layer 260 is provided in the opening 289 so as to cover the upper surface of the insulating layer 222, the side surface of the insulating layer 224, and the side and upper surface of the semiconductor layer 230 via the insulating layer 250. The height of the upper surface of the conductive layer 260 is the same as the height of the upper end of the insulating layer 250 and the height of the upper surface of the insulating layer 280.

[0411] The inner wall of the opening 289 may be perpendicular to the upper surface of the insulating layer 222 or may have a tapered shape. By making the inner wall tapered, the coverage of the insulating layer 250 provided in the opening 289 can be improved and defects such as voids can be reduced.

[0412] 31A and 31C, the conductive layer 260 is preferably provided so as to extend in the channel width direction. With this configuration, when a plurality of transistors are provided, the conductive layer 260 functions as a wiring.

[0413] 31C , in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the semiconductor layer 230 and the top surface of the semiconductor layer 230. In other words, the end of the side surface and the end of the top surface may be curved.

[0414] 32, the conductive layer 260 preferably has a two-layer structure. Here, the conductive layer 260 preferably includes a conductive layer 260_1 and a conductive layer 260_2 disposed over the conductive layer 260_1. For example, the conductive layer 260_1 is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 260_2.

[0415] For example, it is preferable to use titanium nitride for the conductive layer 260_1 and tungsten for the conductive layer 260_2. Alternatively, it is preferable to use tantalum nitride for the conductive layer 260_1 and copper for the conductive layer 260_2. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0416] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0417] The insulating layer 216, the insulating layer 280, and the insulating layer 285 preferably have a lower relative dielectric constant than the insulating layer 222. By using a material with a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0418] For example, the insulating layer 216, the insulating layer 280, and the insulating layer 285 can each be made of a material with a low dielectric constant, which will be described later in the section [Insulating Layer]. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. Furthermore, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing excess oxygen.

[0419] Furthermore, the upper surfaces of the insulating layer 216 and the insulating layer 280 may each be flattened.

[0420] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulating layer 280. For example, it is preferable that the insulating layer 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0421] The conductive layers 243a and 243b are preferably formed using a conductive material containing, for example, tungsten, copper, or aluminum as a main component. The conductive layers 243a and 243b may have a stacked structure.

[0422] 32, the conductive layer 243a and the conductive layer 243b may have a two-layer laminated structure. The conductive layer 243a has a conductive layer 243a1 formed to fit the shape of the opening and a conductive layer 243a2 formed inside the conductive layer 243a1. The conductive layer 243b has a conductive layer 243b1 formed to fit the shape of the opening and a conductive layer 243b2 formed inside the conductive layer 243b1.

[0423] The conductive layer 243a1 and the conductive layer 243b1 can be formed as a single layer or a stacked layer using a conductive material applicable to the conductive layer 205_1. By providing the conductive layer 243a1 and the conductive layer 243b1, impurities such as water and hydrogen can be prevented from entering the semiconductor layer 230 through the conductive layer 243a2 and the conductive layer 243b2. Note that the conductive layer 243a2 and the conductive layer 243b2 may be formed using a conductive material applicable to the conductive layer 243a and the conductive layer 243b.

[0424] 31B, the height of the upper surfaces of conductive layers 243a and 243b is the same as the height of the upper surface of insulating layer 285. Furthermore, as shown in Fig. 32, conductive layer 243a may be formed so that its lower portion is embedded in conductive layer 242a. Similarly, conductive layer 243b may be formed so that its lower portion is embedded in conductive layer 242b.

[0425] The insulating layers 241a and 241b may be barrier insulating layers applicable to the insulating layer 275 or the like. For example, silicon nitride may be used for the insulating layers 241a and 241b. The insulating layers 241a and 241b are provided in contact with the insulating layers 285, 283, 282, and 275. This can prevent impurities such as water and hydrogen contained in the insulating layer 280 or the like from being mixed into the semiconductor layer 230 through the conductive layers 243a and 243b. Silicon nitride is particularly suitable because it has a high barrier property against hydrogen. Furthermore, oxygen contained in the insulating layer 280 can be prevented from being absorbed by the conductive layers 243a and 243b.

[0426] The insulating layer 241 a and the insulating layer 241 b may have a stacked structure. In this case, a first insulating layer in contact with an inner wall of an opening such as the insulating layer 280 and a second insulating layer therein are preferably formed by combining a barrier insulating layer against oxygen and a barrier insulating layer against hydrogen.

[0427] 34 is a cross-sectional view of a semiconductor device 150A, which is a modification of the semiconductor device 150 described above. Note that FIG. 34 illustrates cross-sectional views of the transistor 310, the transistor 200_a, and the transistor 200_b in the channel length direction. Note that the description of the semiconductor device 150 described above can be referred to as appropriate, and therefore, the description may be omitted here.

[0428] 34 , a transistor 200_a is provided above a transistor 310. Conductive layers 248a_a, 248b_a, and 248d_a, each functioning as a plug or a wiring, are provided above the transistor 200_a. A transistor 200_b is provided above the conductive layers 248a_a, 248b_a, and 248d_a. A conductive layer 248a_b, 248b_b, and 248d_b, each functioning as a plug or a wiring, are provided above the transistor 200_b.

[0429] The transistor 200 — a and the transistor 200 — b each correspond to the transistor 200 described above.

[0430] 34 , one of the source and the drain of the transistor 200_a is connected to a conductive layer 248a_a. The other of the source and the drain of the transistor 200_a is connected to a conductive layer 248b_a. The conductive layer 330d is connected to a conductive layer 248d_a via a conductive layer 356d, a conductive layer 218d_a, a conductive layer 246d_a, and the like.

[0431] 34 , one of the source and the drain of the transistor 200_b is connected to a conductive layer 248a_b. The other of the source and the drain of the transistor 200_b is connected to a conductive layer 248b_b. The conductive layer 248d_a is connected to a conductive layer 248d_b via a conductive layer 218d_b, a conductive layer 246d_b, and the like.

[0432] The conductive layer 248a_a, the conductive layer 248b_a, the conductive layer 248d_a, the conductive layer 248a_b, the conductive layer 248b_b, and the conductive layer 248d_b correspond to the above-described conductive layer 248. The conductive layer 218d_a and the conductive layer 218d_b correspond to the above-described conductive layer 218. The conductive layer 246d_a and the conductive layer 246d_b correspond to the above-described conductive layer 246.

[0433] In the semiconductor device 150A, the semiconductor layer including the channel formation region of the transistor 200_a (semiconductor layer 230_a) and the semiconductor layer including the channel formation region of the transistor 200_b (semiconductor layer 230_b) may be made of different materials. This allows the transistors 200_a and 200_b to have different characteristics. For example, the semiconductor layer 230_a and the semiconductor layer 230_b may be made of oxide semiconductors containing different elements or having different compositions. This allows the transistors 200_a and 200_b to be OS transistors with different characteristics.

[0434] The composition of an oxide semiconductor can be analyzed by, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques may be used for the analysis.

[0435] 30 can be applied to, for example, the memory device 100A illustrated in FIG. 1, FIG. 8, and the like in Embodiment 1. That is, for example, in the memory device 100A illustrated in FIG. 8, the transistor 310 can be applied to each of the transistors M22, Mp1, and Mp2 provided in the layer LY1, and the transistor 200 can be applied to each of the transistors M11, M21, M31, Mn1, and Mn2 provided in the layer LY2.

[0436] 34 can be applied to, for example, the memory device 100A illustrated in FIG. 1, FIG. 9, and the like in Embodiment 1. That is, for example, in the memory device 100A illustrated in FIG. 9, the transistor 310 can be applied to each of the transistors M22, Mp1, and Mp2 provided in the layer LY1, the transistor 200_a can be applied to each of the transistors M21, M31, Mn1, and Mn2 provided in the layer LY2, and the transistor 200_b can be applied to the transistor M11 provided in the layer LY3.

[0437] Here, for example, the off-state current of the transistor 200_b may be smaller than the off-state current of the transistor 200_a. Furthermore, for example, the on-state current of the transistor 200_a may be larger than the on-state current of the transistor 200_b. That is, for example, the field-effect mobility of the transistor 200_a may be higher than the field-effect mobility of the transistor 200_b. This allows both reduced power consumption and improved operating speed of the memory device.

[0438] For example, the semiconductor layer 230_a and the semiconductor layer 230_b may be made of oxide semiconductors having different indium contents. In this case, for example, the indium content in the semiconductor layer 230_a may be higher than the indium content in the semiconductor layer 230_b. For example, indium oxide may be used for the semiconductor layer 230_a, and an oxide containing indium and zinc (such as IGZO) may be used for the semiconductor layer 230_b.

[0439] This allows the hole mobility of the semiconductor layer 230_a to be higher than that of the semiconductor layer 230_b. Therefore, the field-effect mobility of the transistor 200_a can be higher than that of the transistor 200_b. That is, the on-state current of the transistor 200_a can be higher than that of the transistor 200_b.

[0440] Furthermore, when the semiconductor layer 230_b contains an element such as gallium in addition to indium, the band gap can be made larger than that of the semiconductor layer 230_a. Therefore, the off-state current of the transistor 200_b can be made smaller than that of the transistor 200_a.

[0441] Therefore, the off-state current of the transistor 200 — a can be reduced and the on-state current of the transistor 200 — b can be reduced.

[0442] Note that although not shown, a structure may be employed in which the transistor 200_a including the semiconductor layer 230_a and the transistor 200_b including the semiconductor layer 230_b are provided in layers at the same height. For example, in the semiconductor device 150 illustrated in FIG. 30 , the transistors 200_a and 200_b may be provided over the insulating layer 216, and an insulating layer 275 or the like may be provided to cover the transistors 200_a and 200_b.

[0443] The semiconductor device 150 can also be applied to, for example, the memory device 100B shown in Figure 15 etc. of the first embodiment described above. The semiconductor device 150A can also be applied to, for example, the memory device 100B shown in Figure 15 etc. of the first embodiment described above.

[0444] The semiconductor device 150 can also be applied to, for example, the memory device 100C shown in Figure 24 etc. of the above-described first embodiment. The semiconductor device 150A can also be applied to, for example, the memory device 100C shown in Figure 24 etc. of the above-described first embodiment.

[0445] Note that one embodiment of the present invention is not limited to the configuration examples, operation examples, and the like described in this embodiment. The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments, etc.

[0446] Embodiment 3 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor according to one embodiment of the present invention will be described.

[0447] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0448] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0449] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 35A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 35B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0450] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 35B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 35A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 35A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 35A.

[0451] 35A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0452] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0453] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistance can be reduced to Ω·cm or less.

[0454] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0455] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 35A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0456] By using the above technical concept, a transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) a large on-current (in other words, high mobility); (2) a small off-current; (3) a normally-off state; (4) high reliability; and (5) a high cutoff frequency (fT). For example, a transistor having indium oxide in this specification and the like has high mobility, a small off-current, and is normally-off. The transistor has high mobility and is different from a normally-on transistor.

[0457] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0458] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0459] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0460] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0461] Unless otherwise specified, the channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating film, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, source electrode, and drain electrode.

[0462] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0463] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0464] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0465] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 35C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ In some cases, oxygen atoms are released as oxygen vacancies (Vo) in the film. If oxygen vacancies (Vo) exist in the film, the diffusing oxygen atoms compensate for the oxygen vacancies. Since oxygen easily diffuses in an indium oxide film, it can be said that oxygen vacancies are more easily compensated for in comparison with an IGZO film.

[0466] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0467] Furthermore, as shown in FIG. 35C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0468] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0469] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and smaller off-state current than a Si transistor.

[0470]

[0471] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0472] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0473] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0474] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0475] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0476] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0477] Embodiment 4 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described. The memory device according to one embodiment of the present invention is, for example, a memory device including an oxide semiconductor.

[0478] <Example of Hierarchical Structure of Storage Devices> Generally, computers and the like use various storage devices depending on the application. FIG. 36 shows various storage devices by hierarchy. The higher the storage device, the faster the operating speed is required, while the lower the storage device, the larger the storage capacity and recording density are required. FIG. 36 shows, from the top layer to the bottom, a register, a cache memory, a main memory, and storage. The cache memory may also include, from top to bottom, a primary cache (L1), a secondary cache (L2), and a tertiary cache (L3). While an example having up to a tertiary cache is shown here, a lower-level cache memory may also be included. The lowest-level cache memory may also be called an LLC (Last Level Cache) or an FLC (Final Level Cache). For example, a storage class memory may be included between the main memory and the storage.

[0479] Registers integrated into arithmetic processing units (also called processors) such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), NPUs (Neural Processing Units), and TPUs (Tensor Processing Units) are used to temporarily store the results of calculations performed by cores. They also have the function of retaining setting information for the arithmetic processing units. For this reason, they are frequently accessed by the arithmetic processing units. Therefore, registers are required to have high operating speeds.

[0480] For example, a static random access memory (SRAM) is used as the cache memory. The cache memory has the function of duplicating and storing a portion of the data stored in the main memory. By storing a copy of frequently used data, the speed of accessing the data can be increased. The cache memory is required to have a faster operating speed than the main memory.

[0481] The main memory may be, for example, a dynamic random access memory (DRAM). The main memory has a function of storing programs and data read from storage. The main memory is required to have a larger storage capacity and a higher recording density than cache memory.

[0482] Storage has the function of storing data that requires long-term storage and various programs used by processing units. Therefore, storage requires large storage capacity and high recording density. For example, a hard disk drive (HDD) or a solid state drive (SSD) located on top of an HDD can be used as the storage. For example, a large-capacity, non-volatile storage device such as a NAND flash memory (e.g., 3D NAND) can be used as the SSD.

[0483] A memory device according to one embodiment of the present invention (for example, a memory device using an oxide semiconductor) is excellent in that it has high operation speed, is capable of retaining data for a long period of time, has high rewrite endurance, and can be driven at a low voltage.

[0484] A storage device according to one aspect of the present invention is suitable as a storage device located in an area target1 that includes a tier where a cache memory is located, a tier where a main memory is located, and a tier where a storage is located, because it is capable of retaining data for a long period of time. In other words, a storage device according to one aspect of the present invention is suitable for use in an area target1 that includes, in addition to the area where the main memory is located, the boundary area between the main memory and the storage, and the boundary area between the main memory and the cache memory.

[0485] Therefore, for example, it is preferable to replace a DRAM used in a main memory with a storage device according to one embodiment of the present invention. Here, since DRAM requires a refresh operation and is a destructive readout storage device, it consumes more power than other storage devices. Therefore, by not using DRAM, it is possible to reduce power consumption. It is also preferable to replace, for example, a portion of an SRAM used in a cache memory and a portion of a 3D NAND used in storage with a storage device according to one embodiment of the present invention.

[0486] For example, a memory device according to one embodiment of the present invention includes a capacitor including a ferroelectric material, which enables data retention for a long time. Therefore, when the memory device is used as a replacement for a DRAM, the frequency of refresh can be reduced. Furthermore, the reliability of the memory device can be improved.

[0487] Furthermore, a storage device according to one embodiment of the present invention is suitable for use in the area target2 that includes a layer where the cache memory is located and a layer where the register is located, because the storage device according to one embodiment of the present invention has a high operating speed and can achieve excellent write and read operations. In other words, a storage device according to one embodiment of the present invention is suitable for use in the area target2 that includes a part of the area where the cache memory is located and an area where the register is located.

[0488] Therefore, for example, a storage device according to an embodiment of the present invention is preferably used as at least a part of a register included in a CPU, a GPU, an NPU, etc. Also, for example, a storage device according to an embodiment of the present invention is preferably used as at least a part of a cache memory (such as L1, L2, L3, LLC, and FLC).

[0489] One embodiment of the present invention can be configured without using a DRAM, which has conventionally been used as a main memory or the like. In this case, a storage device according to one embodiment of the present invention can be used in place of the DRAM. Such a configuration can dramatically reduce power consumption (for example, by one hundredth or one thousandth or less). Furthermore, the storage device according to one embodiment of the present invention may be stacked on a processor such as a CPU, a GPU, or an NPU. Such a configuration in which a processor and a storage device are stacked may be referred to as a monolithic stack. By configuring the processor and the storage device as a monolithic stack, for example, the power consumption required for data access between the processor and the storage device can be significantly reduced. Therefore, global warming can be mitigated by deploying information processing devices including supercomputers (also referred to as high performance computers (HPCs)), computers, servers, and the like, to which such a configuration is applied, all over the world.

[0490] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0491] In this embodiment, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)) that can use the semiconductor device described in the above embodiment will be described. The electronic components, electronic devices, mainframes, space equipment, and data centers that use the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0492] [Electronic Component] FIG. 37A is a perspective view of an electronic component 5700 and a substrate (mounting substrate 5704) on which the electronic component 5700 is mounted. The electronic component 5700 shown in FIG. 37A has a semiconductor device 5710 in a mold 5711. FIG. 37A omits some parts to show the interior of the electronic component 5700. The electronic component 5700 has lands 5712 on the outside of the mold 5711. The lands 5712 are connected to electrode pads 5713. The electrode pads 5713 are connected to the semiconductor device 5710 by wires 5714. The electronic component 5700 is mounted on, for example, a printed circuit board 5702. A plurality of such electronic components are combined and connected on the printed circuit board 5702 to complete the mounting substrate 5704.

[0493] The semiconductor device 5710 also includes a layer 5715 having an operation core and a layer 5716 having a memory. For example, an n-channel transistor and a p-channel transistor can be used for both the layer 5715 and the layer 5716. For example, a CMOS circuit may be configured using a p-channel transistor for the layer 5715 and an n-channel transistor for the layer 5716. However, one embodiment of the present invention is not limited thereto, and a structure may be used in which both an n-channel transistor and a p-channel transistor are used for the layer 5715 and an n-channel transistor is used for the layer 5716.

[0494] Alternatively, for example, a Si transistor may be used for the layer 5715 and an OS transistor may be used for the layer 5716 .

[0495] Here, for example, the transistor 310 included in the semiconductor device described in Embodiment 2 can be used as a p-channel transistor used in the layer 5715, and the transistor 200 included in the semiconductor device described in Embodiment 2 can be used as an n-channel transistor used in the layer 5716.

[0496] The memory-containing layer 5716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the processor core-containing layer 5715 and the memory-containing layer 5716 can be a monolithically stacked configuration. In a monolithically stacked configuration, the processor cores and memories of each layer can be connected to each other without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the processor core-containing layer 5715 and the memory-containing layer 5716, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster. Part of the function of the processor core-containing layer 5715 (part of the computing function) may be provided in a part of the memory-containing layer 5716.

[0497] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0498] It is also preferable that the memory cell arrays included in the memory-containing layer 5716 are formed using OS transistors, and the memory cell arrays are monolithically stacked. By monolithically stacking the memory cell arrays, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time. The access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory-containing layer 5716, it is more difficult to achieve a monolithically stacked structure than OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithically stacked structure.

[0499] That is, OS transistors have an excellent effect of enabling a wider memory bandwidth than Si transistors.

[0500] The semiconductor device 5710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into dices during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon, silicon carbide, and gallium nitride. For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0501] 37B is a perspective view of an electronic component 5730. The electronic component 5730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). The electronic component 5730 has an interposer 5731 provided on a package substrate 5732 (printed circuit board), and a semiconductor device 5735 and a plurality of semiconductor devices 5710 provided on the interposer 5731.

[0502] In the electronic component 5730, the semiconductor device 5710 can be used as, for example, a memory device such as a high bandwidth memory (HBM). The semiconductor device 5735 can be used as, for example, an integrated circuit (e.g., an arithmetic unit, a control unit, an arithmetic processing unit, or a signal processing unit) such as a CPU, a GPU, an NPU, a TPU, or an FPGA (Field Programmable Gate Array).

[0503] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used for the package substrate 5732. For example, a silicon interposer or a resin interposer can be used for the interposer 5731.

[0504] The interposer 5731 has a plurality of wirings and functions to connect a plurality of integrated circuits with different terminal pitches via each of the plurality of wirings. The plurality of wirings are provided in a single layer or multiple layers. The interposer 5731 also functions to connect the integrated circuits provided on the interposer 5731 to electrodes provided on the package substrate 5732. For these reasons, the interposer 5731 is sometimes referred to as a "rewiring substrate" or "intermediate substrate." The interposer 5731 may also be provided with through electrodes, which may be used to connect the integrated circuits to the package substrate 5732. When a silicon interposer is used for the interposer 5731, TSVs may also be used as the through electrodes.

[0505] It is preferable to use a silicon interposer as the interposer 5731. A silicon interposer does not require an active element, and therefore can be manufactured at lower cost than an integrated circuit. Furthermore, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0506] To achieve a wide memory bandwidth, an HBM needs to connect many wires. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0507] Furthermore, for example, SiP or MCM using a silicon interposer is less likely to suffer from a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer. Furthermore, since the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is less likely to occur. In particular, it is preferable to use a silicon interposer for a 2.5D package (2.5-dimensional packaging) in which multiple integrated circuits are arranged side by side on an interposer.

[0508] On the other hand, for example, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 5730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithically stacked configuration using OS transistors is preferable. Also, a composite structure may be used in which a memory cell array stacked using TSVs and a monolithically stacked memory cell array are combined.

[0509] The substrate on which the electronic component 5730 is mounted may be provided with a heat sink (heat dissipation plate) overlapping the electronic component 5730. When a heat sink is provided, it is preferable that the height of the integrated circuit provided on the interposer 5731 be the same. For example, it is preferable that the height of the electronic component 5730 be the same as that of the semiconductor device 5710 and the semiconductor device 5735.

[0510] In order to mount the electronic component 5730 on another substrate, the package substrate 5732 may have electrodes 5733 on its bottom. FIG. 37B shows an example in which the electrodes 5733 are formed with solder balls. By providing solder balls in a matrix on the bottom of the package substrate 5732, the electronic component 5730 can be mounted using a ball grid array (BGA) method. The electrodes 5733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 5732, the electronic component 5730 can be mounted using a pin grid array (PGA) method.

[0511] The electronic component 5730 can be mounted on other substrates using various mounting methods, not limited to BGA or PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0512] [Electronic Device] FIG. 38A is a perspective view of an electronic device 6500. The electronic device 6500 shown in FIG. 38A is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes, for example, a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. Note that the control device 6509 includes, for example, one or more selected from an arithmetic processing device, a memory device, and the like. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502 or the control device 6509, for example. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.

[0513] FIG. 38B is a perspective view of an electronic device 6600. The electronic device 6600 shown in FIG. 38B is an information terminal that can be used as a laptop personal computer. The electronic device 6600 includes, for example, a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, and a control device 6616. Note that the control device 6616 includes, for example, one or more selected from an arithmetic processing device, a memory device, and the like. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6615 or the control device 6616, for example. The use of the semiconductor device of one embodiment of the present invention for the control device 6616 is preferable because power consumption can be reduced.

[0514] [Mainframe] Fig. 38C is a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 38C has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0515] Fig. 38D is a perspective view illustrating an example configuration of a computer 5620. In Fig. 38D, the computer 5620 has a motherboard 5630. The motherboard 5630 has a plurality of slots 5631 and a plurality of connection terminals (not shown). A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.

[0516] PC card 5621 shown in Figure 38E is an example of a processing board equipped with, for example, a processing unit and a storage device. PC card 5621 has board 5622. Board 5622 also has connection terminals 5623, 5624, 5625, semiconductor devices 5626, 5627, 5628, and 5629. Note that Figure 38E illustrates semiconductor devices other than semiconductor devices 5626, 5627, and 5628, but for these semiconductor devices, the following descriptions of semiconductor devices 5626, 5627, and 5628 can be referenced.

[0517] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe (Peripheral Component Interconnect Express).

[0518] Each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for supplying power or inputting signals to the PC card 5621. Furthermore, each of the connection terminals 5623, 5624, and 5625 can be, for example, an interface for outputting signals calculated by the PC card 5621. Examples of standards for each of the connection terminals 5623, 5624, and 5625 include Universal Serial Bus (USB), Serial ATA (SATA), and Small Computer System Interface (SCSI). Furthermore, when a video signal is output from each of the connection terminals 5623, 5624, and 5625, examples of the respective standards include High-Definition Multimedia Interface (HDMI (registered trademark)).

[0519] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0520] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include a CPU, a GPU, an NPU, a TPU, and an FPGA. For example, the electronic component 5730 described above can be used as the semiconductor device 5627.

[0521] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 5700 described above can be used as the semiconductor device 5628.

[0522] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for learning and inference in artificial intelligence, for example.

[0523] [Space Equipment] The semiconductor device of one embodiment of the present invention can be used in space equipment such as equipment that processes and stores information, for example.

[0524] The semiconductor device of one embodiment of the present invention can include an OS transistor. The OS transistor exhibits small changes in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore suitable for use in an environment where radiation may be incident. For example, the OS transistor is suitable for use in outer space.

[0525] Fig. 39A shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig. 39A also shows a planet 6804 in outer space. Although outer space refers to an altitude of 100 km or higher, the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0526] 39A , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0527] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0528] The solar panel 6802 generates the power necessary for the operation of the satellite 6800 when irradiated with sunlight. However, for example, in a situation where the solar panel 6802 is not irradiated with sunlight or where the amount of sunlight irradiating the solar panel 6802 is small, the solar panel 6802 generates less power. Therefore, the satellite 6800 may not generate the power necessary for its operation. In order to operate the satellite 6800 even in a situation where the power generated by the solar panel 6802 is small, the satellite 6800 may be provided with a secondary battery 6805. The solar panel 6802 may also be called a solar cell module.

[0529] The satellite 6800 can generate a signal. The signal is transmitted via the antenna 6803. Furthermore, for example, a receiver installed on the ground or another satellite can receive the signal. For example, the receiver can measure the position of the receiver by receiving the signal transmitted by the satellite 6800. As described above, the satellite 6800 can constitute a satellite positioning system.

[0530] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more devices selected from an arithmetic processing device, a storage device, and the like. Note that the control device 6807 is preferably a semiconductor device including an OS transistor, which is one embodiment of the present invention. The OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure than a Si transistor. That is, the OS transistor is preferable because it has high reliability even in an environment where radiation may be incident.

[0531] That is, an OS transistor has an excellent effect of being more radiation resistant than a Si transistor.

[0532] The artificial satellite 6800 may also be configured to include a sensor. For example, the artificial satellite 6800 may be configured to include a visible light sensor, thereby enabling it to have the function of detecting sunlight reflected from an object on the ground. The artificial satellite 6800 may also be configured to include a thermal infrared sensor, thereby enabling it to have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 may function as, for example, an earth observation satellite.

[0533] Although an artificial satellite is shown here as an example of space equipment, the present invention is not limited thereto. The semiconductor device of one embodiment of the present invention can be used in space equipment such as a spaceship, a space capsule, or a space probe, for example.

[0534] [Data Center] The semiconductor device according to one embodiment of the present invention can be used in a storage system applied to a data center, for example. The data center is required to perform long-term management of data, for example, by ensuring the immutability of data. Managing long-term data requires, for example, the installation of storage and servers for storing huge amounts of data, the securing of a stable power source for retaining the data, or the securing of cooling equipment required for retaining the data. Therefore, for example, the data center building needs to be enlarged.

[0535] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, for example, it is possible to reduce the size of the storage system, the size of the power supply for storing data, and the scale of the cooling equipment. Therefore, it is possible to reduce the space required for the data center.

[0536] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and peripheral modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0537] Fig. 39B shows a storage system applicable to a data center. The storage system 7000 shown in Fig. 39B has a plurality of servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has a plurality of storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0538] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0539] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to write or read data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to write or read data.

[0540] The above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0541] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refreshing the cache memory can be reduced and the power consumption of the cache memory can be reduced.Furthermore, by using a stacked memory cell array, the cache memory can be miniaturized.

[0542] [Head-Mountable Electronic Device] A semiconductor device according to one aspect of the present invention can be used in head-mountable electronic devices (sometimes called wearable devices, headsets, etc.), such as devices for VR, devices for AR, devices for SR (Substitutional Reality), devices for MR (Mixed Reality), and devices that implement spatial computing such as spatial computers.

[0543] 39C and 39D , an example of a head-mountable electronic device will be described. These electronic devices have at least one of the following functions: a function for displaying AR content, a function for displaying VR content, a function for displaying SR content, a function for displaying MR content, and a function for displaying spatial computing content. By having an electronic device with the function for displaying at least one of AR, VR, SR, MR, spatial computing, or other content, it is possible to enhance the sense of immersion felt by the user.

[0544] 39C shows the appearance of an electronic device 8710. The electronic device 8710 has an attachment portion 8711, a lens 8712, a main body 8713, a display portion 8714, and a cable 8715. The attachment portion 8711 has a built-in battery 8716.

[0545] A cable 8715 supplies power from a battery 8716 to the main body 8713. The main body 8713 includes a wireless receiver and can display received image information such as image data on a display portion 8714. A camera provided in the main body 8713 captures the movements of the user's eyeballs, eyelids, and the like, and calculates the user's line of sight based on the information, thereby allowing the user's line of sight to be used as an input means.

[0546] The attachment portion 8711 may be provided with a plurality of electrodes at positions that come into contact with the user. The main body 8713 may have a function of recognizing the user's line of sight by detecting a current flowing through the electrodes in accordance with the movement of the user's eyeballs. The main body 8713 may also have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. The attachment portion 8711 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying biological information of the user on the display portion 8714. The attachment portion 8711 may also detect the movement of the user's head and change the image displayed on the display portion 8714 in accordance with the movement.

[0547] 39D shows the appearance of the electronic device 8720. The electronic device 8720 is a goggle-type information processing device.

[0548] The electronic device 8720 includes a housing 8721, operation buttons 8723, a band-shaped fixture 8724, and two display units 8722. The two display units 8722 allow a user to view one display unit per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax. The fixture 8724 is also provided with a battery 8725. While the battery 8725 may be provided in the housing 8721, providing the battery 8725 in the fixture 8724 is preferable because the center of gravity of the electronic device 8720 can be shifted rearward, improving the wearing comfort for the user. In addition to the battery 8725, a driver circuit for operating the display unit 8722 may be provided in the fixture 8724 to adjust the center of gravity of the electronic device 8720.

[0549] The operation button 8723 has a function of a power button, etc. In addition to the operation button 8723, other buttons may be provided.

[0550] Note that the semiconductor device of one embodiment of the present invention can be applied to any one or more of electronic components, electronic devices, mainframe computers, space equipment, and data centers to reduce power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can contribute to the reduction of carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention consumes low power and is therefore effective as a countermeasure against global warming.

[0551] The contents of this embodiment can be implemented by combining them as appropriate. The contents of this embodiment can also be implemented by combining them as appropriate with the contents of other embodiments.

[0552] (Additional Notes Regarding the Description of the Present Specification, etc.) The following additional notes will be given regarding the above-described embodiments and the explanation of each configuration in the embodiments.

[0553] In this specification, "connection" includes, for example, "electrical connection." When "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0554] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0555] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 40A1 and 40A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 40A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0556] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 40A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 40A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0557] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 40A6 and 40A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 40A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, the connection relationship will be the same as in Figures 40A6 and 40A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0558] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0559] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 40B1, 40B2, and 40B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 40B4 and 40B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," even when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 40B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0560] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0561] Note that even when independent components are shown connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0562] Furthermore, in this specification, the term "resistive element" may refer to, for example, a circuit element or wiring having a resistance value higher than 0 Ω. Therefore, in this specification, the term "resistive element" includes, for example, wiring having a resistance value, a transistor in which current flows from drain to source, a diode, or a coil. Therefore, the term "resistive element" may be replaced with, for example, terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" may be replaced with, for example, terms such as "resistive element." The resistance value may be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, the resistance value may be, for example, 1 Ω or more and 1×10 ９ It may be set to Ω or less.

[0563] When a wiring is used as a resistor, the resistance value of the resistor may be determined by the length of the wiring. Alternatively, the resistor may use a conductor having a different resistivity from the conductor used as the wiring. Alternatively, when a semiconductor is used as a resistor, the resistance value of the resistor may be determined by doping impurities into the semiconductor.

[0564] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification, a "capacitive element" is not limited to a circuit element including a pair of electrodes and a dielectric sandwiched between the electrodes. A "capacitive element" also includes, for example, a parasitic capacitance occurring between wirings, or a gate capacitance occurring between one of the source or drain of a transistor and the gate. Furthermore, terms such as "capacitive element," "parasitic capacitance," or "gate capacitance" can be replaced with terms such as "capacitance" or "capacitance." Conversely, terms such as "capacitance" or "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," or "gate capacitance." Furthermore, terms such as "pair of electrodes," "pair of wirings," "pair of terminals," "pair of conductive layers," "pair of conductors," "pair of conductive regions," and "pair of regions" of a "capacitive element" can sometimes be interchangeable. The capacitance value may be, for example, 0.05 fF to 10 pF, or may be, for example, 1 pF to 10 μF.

[0565] In this specification and the like, a transistor has three terminals called a gate (also referred to as a gate terminal, a gate region, or a gate electrode), a source (also referred to as a source terminal, a source region, or a source electrode), and a drain (also referred to as a drain terminal, a drain region, or a drain electrode). The transistor also has a region where a channel is formed between the drain and the source (also referred to as a channel formation region). A transistor can pass a current between the source and the drain through the channel formation region. That is, a transistor can transmit and receive an electric signal or generate a potential interaction between the source and the drain through the channel formation region. The channel formation region is a region through which a current mainly flows. The gate is a control terminal that controls the amount of current flowing in the channel formation region. The two terminals that function as a source and a drain are input / output terminals that input or output a current flowing in the channel formation region.

[0566] Note that one of the two input / output terminals functions as a source and the other as a drain depending on the conductivity type of the transistor (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor. Furthermore, for example, when the direction of current changes during circuit operation, the function as a source and the function as a drain may be interchanged. For this reason, in this specification, the terms "source" and "drain" are interchangeable. Furthermore, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) or "the other of the source or drain" (or second electrode or second terminal) are used.

[0567] Depending on the structure, a transistor may have a terminal called a back gate (also referred to as a back gate terminal, back gate region, or back gate electrode) in addition to the three terminals described above. In this case, in this specification and the like, one of the gate or the back gate of the transistor may be referred to as a first gate, and the other of the gate or the back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, when a transistor has three or more gates, in this specification and the like, each gate may be referred to as, for example, a first gate, a second gate, a third gate, or the like.

[0568] In this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used. A multi-gate transistor has channel formation regions connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, a multi-gate transistor can reduce off-state current and improve the transistor's breakdown voltage (improved reliability). Furthermore, when a multi-gate transistor operates in the saturation region, even if the voltage between the drain and source changes, the current between the drain and source does not change significantly, resulting in a voltage-current characteristic with a flat slope. A transistor having a voltage-current characteristic with a flat slope can realize an ideal current source circuit or an active load with a very high resistance value. As a result, a transistor having a voltage-current characteristic with a flat slope can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0569] Furthermore, in this specification, when a single circuit element is illustrated on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a single resistor is illustrated on a circuit diagram, the resistor is considered to include two or more resistors connected in series. For example, when a single capacitor is illustrated on a circuit diagram, the capacitor is considered to include two or more capacitors connected in parallel. For example, when a single transistor is illustrated on a circuit diagram, the transistor is considered to include two or more transistors connected in series, with the gates of the respective transistors connected to each other. Similarly, when a single switch is illustrated on a circuit diagram, the switch is considered to include two or more transistors, with the two or more transistors connected in series or in parallel, and with the gates of the respective transistors connected to each other.

[0570] Furthermore, in this specification and the like, a "node" can be rephrased as a "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on, for example, the circuit configuration or the device structure. Furthermore, for example, a "terminal" or "wiring" can be rephrased as a "node."

[0571] Furthermore, in this specification, "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative. In other words, a change in the reference potential will change, for example, the potential applied to wiring, the potential applied to a circuit, or the potential output from a circuit.

[0572] Furthermore, in this specification and the like, the terms "high-level potential (also referred to as "high-level potential," "H potential," or "H")" and "low-level potential (also referred to as "low-level potential," "L potential," or "L")" do not refer to any particular potential. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0573] Furthermore, in this specification, "electric current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of positively charged bodies is occurring" can be rephrased as "electrical conduction of negatively charged bodies is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "electric current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers include electrons, holes, anions, cations, and complex ions. Note that carriers vary depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in, for example, wiring, is the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification and the like, unless otherwise specified, regarding the positive / negative (or current direction) of a current, for example, a statement such as "a current flows from element A to element B" can be rephrased as "a current flows from element B to element A" etc. Furthermore, for example, a statement such as "a current is input to element A" can be rephrased as "a current is output from element A" etc.

[0574] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0575] Furthermore, in this specification, terms indicating arrangement, such as "above," "below," "upward," or "belowward," may be used for convenience in describing the positional relationship between components with reference to drawings. Furthermore, the positional relationship between components changes as appropriate depending on the orientation in which each component is depicted. Therefore, terms indicating arrangement described in this specification are not limited to these terms and can be rephrased appropriately. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees. Furthermore, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the left (or right) surface of a conductor" by rotating the orientation of the drawing by 90 degrees.

[0576] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B. Thus, the term "above" may be replaced with terms such as "above," "upper side," or "upper layer," and the term "below" may be replaced with terms such as "below," "lower side," or "lower layer."

[0577] Furthermore, in this specification, terms such as "row" or "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, terms such as "row" or "column" used in this specification are not limited to these terms and can be rephrased appropriately. For example, the expression "row direction" can be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0578] Furthermore, in this specification and the like, for example, terms such as "overlap" do not limit the state of the stacking order of components, etc. For example, the expression "electrode B overlapping insulating layer A" is not limited to the state in which electrode B is formed on insulating layer A. The expression "electrode B overlapping insulating layer A" does not exclude, for example, the state in which electrode B is formed under insulating layer A, or the state in which electrode B is formed on the right (or left) side of insulating layer A.

[0579] Furthermore, in this specification and the like, the terms "adjacent" or "close to" do not limit components to being in direct contact with each other. For example, the expression "electrode B adjacent to insulating layer A" does not necessarily mean that insulating layer A and electrode B are formed in direct contact with each other, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0580] Furthermore, in this specification and the like, terms such as "film" or "layer" may be interchangeable. For example, the term "conductive layer" may be interchangeable with the term "conductive film." For example, the term "insulating film" may be interchangeable with the term "insulating layer." Furthermore, terms such as "film" or "layer" may be interchangeable with other terms without using those terms. For example, the term "conductive layer" or "conductive film" may be interchangeable with the term "conductor." Furthermore, the term "conductor" may be interchangeable with the term "conductive layer" or "conductive film." For example, the term "insulating layer" or "insulating film" may be interchangeable with the term "insulator." Furthermore, the term "insulator" may be interchangeable with the term "insulating layer" or "insulating film."

[0581] Furthermore, in this specification and the like, terms such as "electrode," "wiring," or "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include, for example, cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes, for example, cases where multiple "electrodes," "wirings," or "terminals" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal." Furthermore, for example, a "terminal" can be part of a "wiring" or "electrode." Furthermore, for example, terms such as "electrode," "wiring," or "terminal" may be replaced with terms such as "region."

[0582] Furthermore, in this specification and the like, for example, terms such as "signal line" or "power line" may be changed to the term "wiring." Furthermore, for example, the term "potential" applied to wiring may be changed to the term "signal." The same is true in reverse, for example, terms such as "signal" may be changed to the term "potential."

[0583] In addition, in this specification, a "switch" refers to a circuit element that has multiple terminals and the ability to switch (select) between conduction and non-conduction between the terminals. In other words, a switch can be said to have the ability to control whether or not a current flows between the multiple terminals, or the ability to control whether or not an electrical signal or potential interaction occurs between the multiple terminals. For example, if a switch has two terminals and the two terminals are considered to be electrically short-circuited, the switch is said to be in a "conductive state" or "on state." Furthermore, if the two terminals are considered to be electrically disconnected, the switch is said to be in a "non-conductive state" or "off state." Note that switching the switch between a conductive state or a non-conductive state, or maintaining the switch in either a conductive state or a non-conductive state, may be referred to as "controlling the conduction state."

[0584] In other words, a switch is a device that has the function of controlling whether or not a current flows. Alternatively, a switch is a device that has the function of selecting and switching a path through which a current flows. For example, an electrical switch or a mechanical switch can be used as the switch. In other words, the switch is not limited to a specific type.

[0585] There are types of switches that are normally in a non-conductive state but can be made conductive by controlling the conductive state, and these switches are sometimes called "contact A." There are also types of switches that are normally in a conductive state but can be made non-conductive by controlling the conductive state, and these switches are sometimes called "contact B."

[0586] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, or diode-connected transistors), and logic circuits that combine these. Note that when a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0587] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. Such a switch has an electrode that can be mechanically moved, and the movement of the electrode selects a conductive state or a non-conductive state.

[0588] In this specification, the "channel length" of a transistor may refer to, for example, the distance between the source and drain in a region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate overlap, or the distance between the source and drain in a region where a channel is formed.

[0589] In addition, in this specification, the "channel width" of a transistor may refer to, for example, the length of the portion where the source and drain face each other in a region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is on) and the gate overlap, or the length of the portion where the source and drain face each other in a region where a channel is formed.

[0590] In this specification and the like, terms such as "substrate," "wafer," or "die" do not limit the functionality of these components. For example, terms such as "substrate," "wafer," or "die" may be used interchangeably.

[0591] In this specification, "parallel" does not necessarily mean strictly parallel. Therefore, the term "parallel" can be appropriately interchanged with terms such as "approximately parallel," "generally parallel," or "substantially parallel." Unless otherwise specified, "parallel," "generally parallel," "generally parallel," or "substantially parallel" may include, for example, a state in which two lines or planes are arranged at an angle of -5° or more and 5° or less. Alternatively, they may include a state in which two lines or planes are arranged at an angle of -10° or more and 10° or less. Alternatively, they may include a state in which two lines or planes are arranged at an angle of -30° or more and 30° or less. Therefore, "parallel" can mean, for example, "parallel or roughly parallel." Furthermore, "perpendicular" does not necessarily mean strictly perpendicular. Therefore, the term "perpendicular" can be appropriately interchanged with terms such as "generally vertical," "generally vertical," or "substantially vertical." Unless otherwise specified, "vertical," "approximately vertical," "generally vertical," or "substantially vertical" may include, for example, a state in which two straight lines or planes are arranged at an angle of 85° or more and 95° or less. Alternatively, it may also include a state in which two straight lines or planes are arranged at an angle of 80° or more and 100° or less. Alternatively, it may also include a state in which two straight lines or planes are arranged at an angle of 60° or more and 120° or less. Therefore, "vertical" may mean, for example, "vertical or roughly vertical."

[0592] In this specification, "equal heights" refers to the same height from a reference surface (e.g., a flat surface such as a substrate surface) in a cross-sectional view. For example, in a semiconductor device manufacturing process, a planarization process may expose the surface of a single layer or multiple layers. In this case, the surfaces to be planarized have the same height from the reference surface. However, depending on the processing equipment, processing method, or material of the processed surface during the planarization process, the heights of multiple layers may not be strictly equal. In this specification, "equal heights" is also used. For example, when there are two layers (here, a first layer and a second layer) with different heights relative to a reference surface, the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less. Therefore, "equal heights" may mean, for example, "equal heights or approximately equal heights."

[0593] In this specification, "edges coincide" means that, when viewed from above, at least a portion of the contours of stacked layers overlap. For example, this includes cases in which, in a semiconductor device manufacturing process, upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In this specification, this case is also referred to as "edges coincide." Therefore, "edges coincide" can mean, for example, "edges coincide or approximately coincide."

[0594] In this specification, for example, when referring to counting values ​​and measurement values, or to things, methods, and events that can be converted into counting values ​​or measurement values, terms such as "identical," "same," "equal," "simultaneous," "matching," or "uniform" (including synonyms thereof) are intended to include errors. Therefore, unless otherwise specified, these terms may include an error of plus or minus 10% or an error of plus or minus 20%. Thus, "identical" means "identical or approximately identical," "same" means "same or approximately the same," "equal" means "equal or approximately equal," "simultaneous" means "simultaneous or approximately simultaneous," "matching" means "matching or approximately matching," and "uniform" may mean "uniform or approximately uniform."

[0595] In this specification and the like, the term "impurity" in a semiconductor refers to, for example, a substance other than the main component constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities in a semiconductor may, for example, increase the defect state density of the semiconductor, decrease the carrier mobility, or decrease the crystallinity. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor. In particular, examples of impurities include hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. For example, the inclusion of impurities in an oxide semiconductor may cause oxygen vacancies in the oxide semiconductor.

[0596] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into, for example, oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply as OSs). For example, when a metal oxide is used as a semiconductor including a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide is used as a material capable of forming a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, the term "OS transistor" can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0597] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0598] In addition, in drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification, the "X direction" refers to the direction along the X axis, and unless otherwise specified, the forward direction and the reverse direction may not be distinguished. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other. In this specification, one of the X direction, Y direction, and Z direction may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0599] 100A: memory device, 100B: memory device, 100C: memory device, 101: memory cell, 101a: memory cell, 101b: memory cell, 101c: memory cell, 101d: memory cell, 101e: memory cell, 101f: memory cell, 101g: memory cell, 101h: memory cell, 102A: drive circuit, 102B: drive circuit, 103A: drive circuit, 103B: drive circuit, 110: memory array, 111A: driver, 111B: driver, 112A: drive circuit unit, 113A: drive circuit unit, M11: transistor, M12: transistor, M12p: transistor transistor, M13: transistor, M14: transistor, M21: transistor, M22: transistor, M23: transistor, M24: transistor, M31: transistor, M32: transistor, Mn1: transistor, Mn2: transistor, Mn3: transistor, Mp1: transistor, Mp2: transistor, Mp3: transistor, Mp4: transistor, Mp5: transistor, C11: capacitor, C12: capacitor, MEM: memory unit, X11: inverter, X12: inverter, X21: buffer, X31: buffer, X32: Inverter, INV: inverter, BUF: buffer, LS: level shifter, LS21: level shifter, LS31: level shifter, VLS: wiring, VLD: wiring, VLd: wiring, RL: wiring, GL: wiring, WL: wiring, WWL: wiring, RWL: wiring, BL: wiring, BLB: wiring, WBL: wiring, RBL: wiring, CL: wiring, PL: wiring, BRL: wiring, MN: wiring, VLn: wiring, VLp: wiring, VLp1: wiring, VLp2: wiring, IL: wiring, OL: wiring, 700: memory device, 721: memory array, 722: driver circuit, 741: memory cell, 761: power supply power switch, 762: power switch, 771: peripheral circuit, 772: control circuit, 773: voltage generation circuit, 781: peripheral circuit, 782: row decoder, 783: row driver, 783a: drive circuit unit, 783b: drive circuit unit, 784: column decoder, 785: column driver, 786: data driver, 787: input circuit, 788: output circuit, BW: terminal, CE: terminal, GW: terminal, MCK: terminal, WAKE: terminal, ADDR: terminal, RDA: terminal, WDA: terminal, PON1: terminal, PON2: terminal, VMD: terminal, VMS: terminal, VMH: terminal, 800: register,810: unit memory circuit, 820: scan flip-flop, 821: selector, 822: flip-flop, 830: backup circuit, 831: hold circuit, M81: transistor, M82: transistor, M83: transistor, C81: capacitance element, D: wiring, Q: wiring, SD: wiring, BK: wiring, RV: wiring, GBK: wiring, SDI: wiring, SE: wiring, PCK: wiring, SN: wiring, Df: input terminal, Qf: output terminal, 200: transistor, 200_a: transistor, 200_b: transistor, 310: transistor,

Claims

a memory cell and a driver; the memory cell includes a first transistor and a storage unit; the driver includes a first buffer, a second buffer, an inverter, a second transistor, and a third transistor; a first terminal of the first transistor electrically connected to the storage unit; a second terminal of the first transistor electrically connected to a bit line; a gate of the first transistor electrically connected to a word line; an output terminal of the first buffer electrically connected to the word line; a first terminal of the second transistor electrically connected to the word line; a gate of the second transistor is electrically connected to an output terminal of the inverter or an output terminal of the second buffer; a second terminal of the second transistor is electrically connected to a first power supply line or a second power supply line; a gate of the third transistor is electrically connected to an output terminal of the second buffer or an output terminal of the inverter; the third transistor has a function of controlling the supply of a signal from the output terminal of the first buffer to the word line; a first power supply terminal of the first buffer, a first power supply terminal of the second buffer, and a first power supply terminal of the inverter are each electrically connected to the first power supply line; a second power supply terminal of the first buffer, a second power supply terminal of the second buffer, and a second power supply terminal of the inverter are each electrically connected to the second power supply line; the inverter has a function of outputting a signal obtained by inverting the logical value of the signal output from the second buffer. storage device. 　 In claim 1, each of the first transistor to the third transistor is an n-channel transistor, a gate of the second transistor electrically connected to an output terminal of the inverter; a second terminal of the second transistor electrically connected to the first power supply line; a gate of the third transistor electrically connected to an output terminal of the second buffer; The potential applied to the second power supply line is higher than the potential applied to the first power supply line. storage device. 　 In claim 1 or claim 2, at least one of the first to third transistors includes an oxide semiconductor in a channel formation region; storage device. 　 a memory cell and a driver; the memory cell includes a first transistor and a storage unit; the driver includes a first buffer, a second buffer, an inverter, a second transistor, a third transistor, and a fourth transistor; a first terminal of the first transistor electrically connected to the storage unit; a second terminal of the first transistor electrically connected to a bit line; a gate of the first transistor electrically connected to a word line; an output terminal of the first buffer electrically connected to the word line; a first terminal of the second transistor electrically connected to the word line; a first terminal of the third transistor electrically connected to a first power supply terminal of the first buffer; a first terminal of the fourth transistor electrically connected to a second power supply terminal of the first buffer; a gate of the second transistor is electrically connected to an output terminal of the inverter or an output terminal of the second buffer; a gate of the third transistor electrically connected to an output terminal of the second buffer; a gate of the fourth transistor is electrically connected to an output terminal of the inverter or an output terminal of the second buffer; a second terminal of the second transistor is electrically connected to a first power supply line or a second power supply line; a second terminal of the third transistor, a first power supply terminal of the second buffer, and a first power supply terminal of the inverter are each electrically connected to the first power supply line; a second terminal of the fourth transistor, a second power supply terminal of the second buffer, and a second power supply terminal of the inverter are each electrically connected to the second power supply line; the inverter has a function of outputting a signal obtained by inverting the logical value of the signal output from the second buffer. storage device. 　 In claim 4, each of the first transistor to the third transistor is an n-channel transistor, the fourth transistor is a p-channel transistor, a gate of the second transistor electrically connected to an output terminal of the inverter; a gate of the fourth transistor electrically connected to an output terminal of the inverter; a second terminal of the second transistor electrically connected to the first power supply line; The potential applied to the second power supply line is higher than the potential applied to the first power supply line. storage device. 　 In claim 4 or claim 5, at least one of the first to third transistors includes an oxide semiconductor in a channel formation region; storage device. 　 a memory cell and a driver; the memory cell includes a first transistor and a storage unit; the driver includes a first buffer, a second buffer, an inverter, a second transistor, and a third transistor; a first terminal of the first transistor electrically connected to the storage unit; a second terminal of the first transistor electrically connected to a bit line; a gate of the first transistor electrically connected to a word line; a first terminal of the second transistor electrically connected to the word line; a first terminal of the third transistor electrically connected to the word line; a second terminal of the third transistor electrically connected to an output terminal of the first buffer; a gate of the second transistor is electrically connected to an output terminal of the inverter or an output terminal of the second buffer; a gate of the third transistor is electrically connected to an output terminal of the second buffer or an output terminal of the inverter; a second terminal of the second transistor is electrically connected to a first power supply line or a second power supply line; a first power supply terminal of the first buffer, a first power supply terminal of the second buffer, and a first power supply terminal of the inverter are each electrically connected to the first power supply line; a second power supply terminal of the first buffer, a second power supply terminal of the second buffer, and a second power supply terminal of the inverter are each electrically connected to the second power supply line; the inverter has a function of outputting a signal obtained by inverting the logical value of the signal output from the second buffer. storage device. 　 In claim 7, each of the first transistor to the third transistor is an n-channel transistor, a gate of the second transistor electrically connected to an output terminal of the inverter; a gate of the third transistor electrically connected to an output terminal of the second buffer; a second terminal of the second transistor electrically connected to the first power supply line; The potential applied to the second power supply line is higher than the potential applied to the first power supply line. storage device. 　 In claim 7 or claim 8, at least one of the first to third transistors includes an oxide semiconductor in a channel formation region; storage device. 　 In claim 1, a gate of the second transistor electrically connected to an output terminal of the inverter; a second terminal of the second transistor electrically connected to the first power supply line; a gate of the third transistor electrically connected to an output terminal of the second buffer; a potential applied to the second power supply line is higher than a potential applied to the first power supply line; the first transistor includes a first oxide semiconductor in a channel formation region; each of the second transistor and the third transistor includes a second oxide semiconductor in a channel formation region; storage device. 　 In claim 10, each of the first oxide semiconductor and the second oxide semiconductor contains indium; the indium content of the second oxide semiconductor is higher than the indium content of the first oxide semiconductor; storage device. 　 In claim 10, an off-current of the first transistor is smaller than an off-current of the third transistor; the field effect mobility of the third transistor is higher than the field effect mobility of the first transistor; storage device. 　 In claim 4, a gate of the second transistor electrically connected to an output terminal of the inverter; a gate of the third transistor electrically connected to an output terminal of the second buffer; a gate of the fourth transistor electrically connected to an output terminal of the inverter; a second terminal of the second transistor electrically connected to the first power supply line; a potential applied to the second power supply line is higher than a potential applied to the first power supply line; the first transistor includes a first oxide semiconductor in a channel formation region; each of the second transistor and the third transistor includes a second oxide semiconductor in a channel formation region; storage device. 　 In claim 13, each of the first oxide semiconductor and the second oxide semiconductor contains indium; the indium content of the second oxide semiconductor is higher than the indium content of the first oxide semiconductor; storage device. 　 In claim 13, an off-current of the first transistor is smaller than an off-current of the third transistor; the field effect mobility of the third transistor is higher than the field effect mobility of the first transistor; storage device. 　 In claim 7, a gate of the second transistor electrically connected to an output terminal of the inverter; a gate of the third transistor electrically connected to an output terminal of the second buffer; a second terminal of the second transistor electrically connected to the first power supply line; a potential applied to the second power supply line is higher than a potential applied to the first power supply line; the first transistor includes a first oxide semiconductor in a channel formation region; each of the second transistor and the third transistor includes a second oxide semiconductor in a channel formation region; storage device. 　 In claim 16, each of the first oxide semiconductor and the second oxide semiconductor contains indium; the indium content of the second oxide semiconductor is higher than the indium content of the first oxide semiconductor; storage device. 　 In claim 16, an off-current of the first transistor is smaller than an off-current of the third transistor; the field effect mobility of the third transistor is higher than the field effect mobility of the first transistor; storage device.

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