Semiconductor device and method for producing semiconductor device

Abstract

Provided is a highly reliable semiconductor device. The semiconductor device has a trench capacitor. The semiconductor device has an insulating layer provided with an opening. A first electrode of the capacitor is provided along a side surface of the opening of the insulating layer. An upper end surface of the first electrode has a lower height from a reference surface than an upper surface of the insulating layer. A ferroelectric layer containing oxygen is provided so as to have a region in contact with the first electrode in the opening. A region of the first electrode in contact with the ferroelectric layer becomes an oxide region. A second electrode of the capacitor is provided on the ferroelectric layer so as to have a region facing the first electrode across the ferroelectric layer in the opening.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] In recent years, development of semiconductor devices such as large-scale integration (LSI), central processing units (CPU), and memories (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. Furthermore, memories of various storage methods have been developed depending on the application, such as temporary storage during arithmetic processing and long-term storage of data. Typical memory storage methods include, for example, dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory.

[0005] Furthermore, as shown in Non-Patent Documents 1 and 2, research and development of memories using ferroelectrics is being actively carried out. For next-generation ferroelectric memories, ferroelectric HfO ２Research on Hf-based materials (Non-Patent Document 3), ０．５ Zr ０．５ O ２ Research on ferroelectricity of thin films (Non-Patent Document 4), HfO ２ Research on ferroelectricity of thin films (Non-Patent Document 5), and ferroelectric Hf ０．５ Zr ０．５ O ２ Research related to hafnium oxide is also being actively conducted, including the demonstration of integration of FeRAM (Ferroelectric Random Access Memory) using hafnium oxide with CMOS (Non-Patent Document 6).

[0006] T. S. Boescke, et al. , “Ferroelectricity in hafnium oxide thin films”, APL99, 2011N. Ramaswamy, et al. , “NVDRAM: A 32Gb Dual Layer 3D Stacked Non-volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI “Workloads”, IEDM 2023Zhen Fan, et al. , "Ferroelectric HfO2-based materials for next-generation ferroelectric memories," JOURNAL OF ADVANCED DIELECTRICS, Vol. 6, No. 2, 2016; Jun Okuno, et al., "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2," VLSI 2020; Akira Toriumi, "Ferroelectricity of HfO2 thin films," The Japan Society of Applied Physics, Vol. 88, No. 9, 2019. Francois, et al., "Demonstration of BEOL-compatible ferroelectric Hf0.5Zr0.5O2 scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications," IEDM 2019. Takashi Koida, "High-mobility transparent conductive film," National Institute of Advanced Industrial Science and Technology (AIST) Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13. pdf>

[0007] When a metal oxide such as hafnium oxide, zirconium oxide, or hafnium zirconium oxide is used as a ferroelectric, if oxygen is released from the ferroelectric, the remanent polarization may decrease and the withstand voltage may decrease when repeatedly rewriting. Therefore, if oxygen is released from the ferroelectric, the reliability of a memory having the ferroelectric may decrease.

[0008] An object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a manufacturing method thereof.An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption and a manufacturing method thereof.An object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed and a manufacturing method thereof.An object of one embodiment of the present invention is to provide a novel semiconductor device and a manufacturing method thereof.

[0009] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0010] One aspect of the present invention is a semiconductor device having a substrate, a first insulating layer, a first conductive layer, a second conductive layer, and a ferroelectric layer, wherein the first insulating layer, the first conductive layer, the second conductive layer, and the ferroelectric layer are provided on the substrate, the first insulating layer has an opening, the first conductive layer has a region along a side surface of the opening of the first insulating layer, the top surface of the first conductive layer is lower in height from the substrate than the top surface of the first insulating layer, the ferroelectric layer has a region in contact with the first conductive layer in the opening, the second conductive layer has a region facing the first conductive layer in the opening with the ferroelectric layer sandwiched therebetween, the first conductive layer has an oxide region, the oxide region includes a region in contact with the ferroelectric layer, and the ferroelectric layer contains oxygen.

[0011] Alternatively, in the above aspect, the oxide region may contain an oxide of an element contained in the first conductive layer.

[0012] Alternatively, in the above aspect, the angle of the top surface of the first conductive layer with respect to the top surface of the substrate may be greater than 0°.

[0013] Alternatively, in the above aspect, the second conductive layer may have a first layer and a second layer on the first layer, the first layer being arranged to fill the opening, and the thermal expansion coefficient of the first layer being greater than the thermal expansion coefficient of the second layer.

[0014] Alternatively, in the above aspect, the first layer may include titanium nitride, and the second layer may include tungsten.

[0015] Alternatively, in the above aspect, the semiconductor device may have a second insulating layer, a third insulating layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, wherein the second insulating layer is located on the second conductive layer and on the first insulating layer, the third conductive layer and the fourth conductive layer are located on the second insulating layer, the second insulating layer has a groove portion overlapping a region between the third conductive layer and the fourth conductive layer and having a region reaching the second conductive layer, the semiconductor layer has a region in contact with the second conductive layer, a region in contact with the third conductive layer, a region in contact with the fourth conductive layer, and a region along a part of a side surface of the second insulating layer in the groove, the third insulating layer is provided on the semiconductor layer so as to have a region located inside the groove, and the fifth conductive layer has a region inside the groove facing the semiconductor layer with the third insulating layer sandwiched therebetween.

[0016] Alternatively, in the above aspect, the semiconductor device may have a fourth insulating layer and a sixth conductive layer, the fourth insulating layer being located on the third to fifth conductive layers, the sixth conductive layer being located on the fourth insulating layer, and the sixth conductive layer being electrically connected to the third conductive layer and the fourth conductive layer.

[0017] Alternatively, in the above aspect, the groove and the fifth conductive layer may extend in a first direction, and the sixth conductive layer may extend in a second direction, the second direction being perpendicular to the first direction.

[0018] Alternatively, in the above embodiment, the semiconductor layer may contain indium.

[0019] Another embodiment of the present invention is a method for manufacturing a semiconductor device, including: forming a first insulating layer over a substrate; forming an opening in the first insulating layer; forming a conductive film to cover the opening; applying a photoresist to the conductive film; performing anisotropic etching on the photoresist to form a resist mask in the opening; and processing the conductive film to form a first conductive layer along a side surface of the opening in the first insulating layer; removing the resist mask; and performing oxidation treatment on the first conductive layer to form an oxide region in the first conductive layer; forming a ferroelectric layer containing oxygen to have a region in contact with the oxide region; and forming a second conductive layer over the ferroelectric layer to have a region located in the opening; and forming the first conductive layer so that a height of a top surface of the first conductive layer from the substrate is lower than a height of a top surface of the first insulating layer from the substrate.

[0020] Alternatively, in the above embodiment, in the oxidation treatment, a second insulating layer containing oxygen may be formed so as to have a region in contact with the first conductive layer, and then the second insulating layer may be removed.

[0021] Alternatively, in the above aspect, the second conductive layer may be formed by forming a first layer that fills the opening and a second layer on the first layer, and the thermal expansion coefficient of the first layer may be greater than the thermal expansion coefficient of the second layer.

[0022] Alternatively, in the above aspect, the first layer may be formed to contain titanium nitride, and the second layer may be formed to contain tungsten.

[0023] According to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that operates at high speed and a manufacturing method thereof can be provided. Alternatively, according to one embodiment of the present invention, a novel semiconductor device and a manufacturing method thereof can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0025] FIGS. 1A and 1B are perspective views showing a structural example of a semiconductor device. FIGS. 2A and 2B are plan views showing a structural example of a semiconductor device. FIGS. 3A, 3B, and 3C are cross-sectional views showing a structural example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 5A and 5B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 6A and 6B are cross-sectional views showing a structural example of a semiconductor device. FIG. 7A is a circuit diagram showing a structural example of a memory cell. FIG. 7B is a perspective view showing a structural example of a semiconductor device. FIGS. 8A, 8B, and 8C are plan views showing a structural example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 10A and 10B are cross-sectional views showing a structural example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing a structural example of a semiconductor device. FIG. 12 is a cross-sectional view showing a structural example of a semiconductor device. FIG. 13A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 13B and 13C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 14B and 14C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15B and 15C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16B and 16C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 17A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 17B and 17C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 18A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 18B and 18C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 19A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 19B and 19C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 20A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 20B and 20C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. Fig. 21A is a circuit diagram showing an example of the configuration of a memory cell. Fig. 21B is a plan view showing an example of the configuration of a semiconductor device. Fig. 22 is a cross-sectional view showing an example of the configuration of a semiconductor device. Fig. 23 is a cross-sectional view showing an example of the configuration of a semiconductor device. Fig. 24 is a cross-sectional view showing an example of the configuration of a semiconductor device.FIG. 25 is a diagram illustrating an example of hysteresis characteristics. FIGS. 26A and 26B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 26C is a cross-sectional view illustrating an indium oxide film. FIG. 27 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 28A and 28B are perspective views illustrating a configuration example of a semiconductor device. FIG. 29 is a block diagram illustrating a CPU. FIGS. 30A and 30B are perspective views of a semiconductor device. FIGS. 31A and 31B are perspective views of a semiconductor device. FIG. 32 is a conceptual diagram illustrating the hierarchy of a memory device. FIGS. 33A and 33B are diagrams illustrating an example of an electronic component. FIGS. 34A, 34B, and 34C are diagrams illustrating an example of a mainframe computer. FIG. 34D is a diagram illustrating an example of space equipment. FIG. 34E is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 35A and 35B are cross-sectional STEM images according to an example. FIGS. 36A and 36B are diagrams illustrating input voltage waveforms in an endurance test. 37A, 37B, and 38 are graphs showing the results of a rewrite endurance test according to an example, I-V characteristics, and a result of a rewrite endurance test according to an example, respectively.

[0026] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0027] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0028] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0029] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes, stacking order, or arrangement order. Furthermore, even if a term is not accompanied by an ordinal number in this specification, ordinal numbers may be accompanied in the claims to avoid confusion between components. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be accompanied by a different ordinal number in the claims. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be omitted in the claims.

[0030] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing a switching operation to control conduction or non-conduction. The term "transistor" used in this specification includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0031] In this specification and the like, a transistor using a metal oxide for a semiconductor layer and a transistor having a metal oxide for a channel formation region may be referred to as an OS transistor, and a transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0032] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A transistor has a region (also referred to as a channel formation region) where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0033] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0034] Note that impurities in a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The inclusion of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen deficiency (V) in the metal oxide. Ｏ In some cases, a nucleus (also referred to as a nucleus) may be formed.

[0035] In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. A nitride oxide refers to a material whose composition contains more nitrogen than oxygen. Here, when referring to an oxynitride, the composition may contain more oxygen than nitrogen, more nitrogen than oxygen, or equal amounts of nitrogen and oxygen.

[0036] To analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in a film, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) or electron spectroscopy for chemical analysis (ESCA) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less). When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0037] In this specification, the term "content" refers to the ratio of a component contained in a film. For example, if a metal oxide layer contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide layer is A, then the number of atoms of each of metal elements X, Y, and Z is A. Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide layer (atomic ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0038] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0039] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, in this specification, due to formatting restrictions, numbers may be expressed by adding a minus sign (-) before them instead of adding a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0040] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases where the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0041] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0042] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0043] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0044] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0045] Unless otherwise specified, in this specification, the off-state current refers to a leakage current between the source and drain when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0046] In this specification and the like, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0047] In this specification, when it is stated that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be rephrased as "A has a region located on B." Similarly, when it is stated that A contacts B or A overlaps B, at least a portion of A contacts B or overlaps B. Therefore, it can be rephrased as "A has a region contacting B" or "A has a region overlapping B," respectively. Similarly, in this specification, when it is stated that A covers B, at least a portion of A covers B. Therefore, for example, it can be rephrased as "A has a region covering B."

[0048] In this specification, "ends that match or approximately match" and "side surfaces that match or approximately match" refer to the overlapping of at least a portion of the contours between stacked layers in a plan view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the terms "ends that match or approximately match" or "side surfaces that match or approximately match" are also used.

[0049] In this specification and the like, a step disconnection refers to a phenomenon in which a layer, a film, or an electrode is separated due to the shape of the surface on which it is formed (for example, a step or the like).

[0050] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0051] In the drawings and the like relating to this specification, arrows indicating the X direction, Y direction, and Z direction may be used. In this specification and the like, the "X direction" refers to the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." The X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other, i.e., directions that are perpendicular to each other. In this specification and the like, the X direction may be referred to as the row direction, and the Y direction may be referred to as the column direction.

[0052] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

[0053] One aspect of the present invention relates to a ferroelectric capacitor and a memory having a ferroelectric capacitor. In this specification and the like, a capacitor using a ferroelectric layer as a dielectric layer is referred to as a ferroelectric capacitor. Also, a memory having a ferroelectric capacitor is referred to as a ferroelectric memory. In one aspect of the present invention, the ferroelectric capacitor has a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer. Therefore, the ferroelectric capacitor can be a MIM (Metal-Insulator-Metal) capacitor. Note that in a capacitor having a first electrode, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, the first electrode may be referred to as the lower electrode of the capacitor, and the second electrode may be referred to as the upper electrode of the capacitor.

[0054] Ferroelectrics have the property that when a voltage is applied, the polarization aligns in a certain direction, and remains aligned even after the voltage application is stopped. Furthermore, the polarization reverses when the polarity of the voltage is reversed. Ferroelectric memory can function as a non-volatile memory by applying the properties of ferroelectrics.

[0055] In this specification and the like, the term "semiconductor device" may refer to a ferroelectric capacitor or a ferroelectric memory, and may also refer to a transistor included in a ferroelectric memory.

[0056] A metal oxide can be used as the ferroelectric layer. Examples of metal oxides include hafnium oxide, zirconium oxide, and hafnium zirconium oxide. When a metal oxide is used as the ferroelectric layer, if oxygen is desorbed from the ferroelectric layer, the remanent polarization may decrease when data is repeatedly rewritten to the ferroelectric memory. Furthermore, if data is repeatedly rewritten to the ferroelectric memory, the withstand voltage of the ferroelectric capacitor may decrease. For these reasons, if oxygen is desorbed from the ferroelectric layer, the reliability of the ferroelectric memory may decrease.

[0057] Therefore, in one aspect of the present invention, a first electrode is formed, an oxidation treatment is performed on the first electrode to form an oxide region, and then a ferroelectric layer is formed in contact with the oxide region. This makes it possible to suppress absorption of oxygen in the ferroelectric layer by the first electrode compared to when a ferroelectric layer is formed without forming an oxide region on the first electrode. Therefore, it is possible to suppress desorption of oxygen from the ferroelectric layer and a decrease in the reliability of the ferroelectric memory. As described above, one aspect of the present invention can realize a highly reliable semiconductor device. Here, an example of the oxidation treatment is a method of forming an insulating layer containing oxygen and then removing the insulating layer.

[0058] In one embodiment of the present invention, the ferroelectric capacitor is a trench-type capacitor. In this specification and the like, a trench-type capacitor refers to a capacitor in which a first electrode, a dielectric layer on the first electrode, and a second electrode on the dielectric layer are provided so as to have a region located inside an opening in an interlayer insulating layer. A trench-type capacitor can increase the capacitance per occupied area compared to, for example, a parallel-plate type capacitor. This allows the occupied area of ​​the capacitor to be reduced while maintaining the capacitance. Therefore, miniaturization or high integration of semiconductor devices can be achieved.

[0059] In one embodiment of the present invention, the first electrode is provided along the side surface of an opening in an interlayer insulating layer. To form the first electrode, a conductive film is first formed to cover the opening. Next, a photoresist is applied to the conductive film, and anisotropic etching is performed on the entire surface of the photoresist to form a resist mask inside the opening. The conductive film is then processed to form the first electrode. When forming the first electrode using this method, the first electrode can be formed so that the height of the top surface of the first electrode from a reference plane is lower than the height of the top surface of the interlayer insulating layer from the reference plane. The reference plane can be, for example, the top surface of the substrate. The resist mask is removed after the first electrode is formed.

[0060] Furthermore, by forming the first electrode using the above-described method, the angle of the top surface of the first electrode relative to the top surface of the substrate can be made larger than 0°. That is, the top surface of the first electrode has a tapered shape. This makes it possible to suppress electric field concentration in the ferroelectric layer near the top surface of the first electrode. Therefore, it is possible to prevent dielectric breakdown in the ferroelectric layer, and a highly reliable semiconductor device can be realized.

[0061] 1A and 1B are perspective views illustrating a structural example of a semiconductor device of one embodiment of the present invention. Each of FIGS. 1A and 1B illustrates a structural example of a capacitor 100. FIG. 1B illustrates a cross-sectional structural example in which a part of the structure in FIG. 1A is omitted.

[0062] 2A and 2B are plan views illustrating a configuration example of a semiconductor device according to one embodiment of the present invention. Fig. 2A illustrates a configuration example of a capacitor 100. Fig. 2B omits some elements from Fig. 2A .

[0063] 3A is a cross-sectional view taken along dashed dotted line A1-A2 in FIGS. 2A and 2B. FIG. 3B is a cross-sectional view taken along dashed dotted line B1-B2 in FIGS. 2A and 2B. FIG. 3C is a cross-sectional view taken along dashed dotted line C1-C2 in FIG. 3A. FIGS. 3A to 3C show a configuration example of the capacitor 100. FIG. 3C is also called a plan view, and specifically can be said to be a plan view showing a cross-sectional configuration example taken along dashed dotted line C1-C2. FIG. 4A is an enlarged view of the capacitor 100 shown in FIG. 3A.

[0064] 1A to 4A, the X direction, Y direction, and Z direction are indicated by arrows. Note that the directions do not necessarily have to match between Figures 1A to 4A. In subsequent figures, the X direction, Y direction, and Z direction do not necessarily have to match between the figures.

[0065] 1A to 4A includes an insulating layer 140 on a substrate (not shown), a conductive layer 110 on the insulating layer 140, a capacitor 100 on the conductive layer 110, and an insulating layer 180 on the conductive layer 110 and the insulating layer 140. Here, the insulating layer 140 and the insulating layer 180 function as interlayer insulating layers and preferably have flat top surfaces. The insulating layer 140 can also function as a base insulating layer.

[0066] For example, at least one of silicon oxide, silicon oxynitride, silicon nitride oxide, and silicon nitride can be used for the insulating layer 140 and the insulating layer 180. For the conductive layer 110, a material with high conductivity, such as tungsten, copper, or aluminum, is preferably used.

[0067] The capacitor 100 has a conductive layer 115 on the conductive layer 110, a ferroelectric layer 130 on the conductive layer 115 and on the insulating layer 180, and a conductive layer 120 on the ferroelectric layer 130. Note that in Fig. 2B, the conductive layer 120, the ferroelectric layer 130, and the insulating layer 180 are omitted from Fig. 2A.

[0068] The conductive layer 115 has a region that functions as one of a pair of electrodes of the capacitor 100. The conductive layer 120 has a region that functions as the other of the pair of electrodes of the capacitor 100. In the capacitor 100, a ferroelectric layer 130 is sandwiched between the conductive layer 115 and the conductive layer 120. Therefore, the capacitor 100 constitutes an MIM capacitor. Here, the capacitor 100 is a ferroelectric capacitor because it has a ferroelectric layer as a dielectric layer. The conductive layer 115 is also referred to as the lower electrode of the capacitor 100. The conductive layer 120 is also referred to as the upper electrode of the capacitor 100.

[0069] 1A to 4A show an example in which the conductive layer 110 and the conductive layer 120 are provided in a strip shape. In this specification and the like, the term "strip shape" refers to a shape having an area extending in a certain direction (for example, the X direction, the Y direction, or the Z direction). 1A to 4A show an example in which the conductive layer 110 extends in the Y direction and the conductive layer 120 extends in the X direction.

[0070] As shown in FIGS. 1A to 4A , an opening 190 is provided in the insulating layer 180, reaching the conductive layer 110. The conductive layer 115, the ferroelectric layer 130, and the conductive layer 120 of the capacitor 100 are provided inside the opening 190. Thus, the capacitor 100 is a trench-type capacitor. Therefore, compared to a case where the capacitor 100 is a parallel-plate capacitor, for example, the capacitance per occupied area can be increased. This allows the occupied area of ​​the capacitor 100 to be reduced while maintaining the capacitance of the capacitor 100. Therefore, miniaturization or high integration of the semiconductor device can be achieved. In the plan view, the shape of the opening 190 is shown as the shape of the bottom of the opening 190.

[0071] The thicker the insulating layer 180, the greater the capacitance per occupied area in the capacitor 100. On the other hand, if the insulating layer 180 is too thick, the productivity of the semiconductor device decreases. The thickness of the insulating layer 180 in the region overlapping with the conductive layer 110 is, for example, preferably 30 nm to 3000 nm, more preferably 50 nm to 1000 nm, still more preferably 100 nm to 800 nm, still more preferably 200 nm to 700 nm, and even more preferably 300 nm to 600 nm, and can be typically 400 nm.

[0072] 2A, 2B, and 3C show an example in which the shape of the opening 190 in plan view is circular. By making the shape of the opening 190 circular in plan view, the processing accuracy when forming the opening 190 can be improved. Therefore, the opening 190 can be formed in a fine size. However, the present invention is not limited to this. In plan view, the opening 190 can be, for example, a circle or a substantially circle such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygon with rounded corners. Note that the circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0073] 1A, 1B, 3A, 3B, and 4A show an example in which the side surface of the opening 190 in the insulating layer 180 is perpendicular to the top surface of the conductive layer 110. In this case, the opening 190 has a cylindrical shape. With this configuration, miniaturization or high integration of the semiconductor device can be achieved.

[0074] The conductive layer 115 is provided along the side surface of the opening 190 in the insulating layer 180. The conductive layer 115 has a region in contact with the conductive layer 110. Here, FIGS. 1B , 3A, 3B, and 4A show an example in which the conductive layer 110 has a recess at a position overlapping the opening 190. In this case, the bottom of the opening 190 includes the bottom surface of the recess in the conductive layer 110. The sidewall of the opening 190 includes the side surface of the recess in the conductive layer 110 and the side surface of the insulating layer 180.

[0075] In this specification, the sidewall of an opening refers to the side surface of the layer in which the opening is formed, within the opening. Furthermore, when the opening reaches A, the top surface of A can be referred to as the bottom of the opening.

[0076] By providing a recess in the conductive layer 110 at a position overlapping the opening 190, the contact area between the conductive layer 110 and the conductive layer 115 can be increased compared to when the recess is not provided, and therefore the contact resistance between the conductive layer 110 and the conductive layer 115 can be reduced.

[0077] If the thickness of the conductive layer 115 is too thick, the conductive layer 120 will not be provided inside the opening 190. Alternatively, the volume of the conductive layer 120 inside the opening 190 will be small. On the other hand, if the thickness of the conductive layer 115 is too thin, the electrical resistance of the conductive layer 115 will be large. The thickness of the conductive layer 115 is preferably, for example, 1 nm to 30 nm, more preferably 2 nm to 20 nm, and even more preferably 3 nm to 10 nm, and can be typically 5 nm.

[0078] The ferroelectric layer 130 is provided on the conductive layer 115 and on the insulating layer 180 so as to have a region in contact with the conductive layer 115 inside the opening 190. The ferroelectric layer 130 is provided so as to cover the conductive layer 115. The ferroelectric layer 130 is provided along the side and top surfaces of the conductive layer 115 inside the opening 190. The top surface of the ferroelectric layer 130 and the side surface opposite to the conductive layer 115 can be in contact with the conductive layer 120.

[0079] Ferroelectric materials that can be used for the ferroelectric layer 130 include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Ferroelectric materials include materials in which element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. The ratio of the number of hafnium atoms to the number of element J1 can be set appropriately. For example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Ferroelectric materials include materials in which element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. The ratio of the number of zirconium atoms to the number of element J2 can be set appropriately. For example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. Furthermore, lead titanate (PbTiO Ｘ(X is a real number greater than 0), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate may be used as a piezoelectric ceramic having a perovskite structure. Also, as a ferroelectric, GaFeO with a κ-alumina structure may be used. ３ etc.

[0080] In the above description, metal oxides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the above metal oxides may be used. For example, SrTaO ２ N, BaTaO ２ Examples of suitable perovskite-type oxynitrides include N and other perovskite-type oxynitrides.

[0081] Furthermore, the ferroelectric may be, for example, a mixture or compound of multiple materials selected from the materials listed above. For example, the ferroelectric may have a layered structure of multiple materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change not only depending on the film formation conditions but also on various processes. For this reason, in this specification, the term ferroelectric is used to refer not only to materials that exhibit ferroelectricity, but also to materials that can have ferroelectricity.

[0082] Metal oxides containing either or both of hafnium and zirconium can exhibit ferroelectricity even in thin films of a few nanometers. Furthermore, metal oxides containing either or both of hafnium and zirconium can exhibit ferroelectricity even in very small areas. Therefore, by using metal oxides containing either or both of hafnium and zirconium, miniaturization of semiconductor devices can be achieved. Representative examples of metal oxides containing hafnium and zirconium include HfZrO Ｘ Also, HfZrO Ｘ It is also possible to use a metal oxide in which Y (yttrium) is added to HfZrO. Ｘ By adding Y (yttrium) to the above, the ferroelectricity can be enhanced.

[0083] It is believed that ferroelectricity is exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. It is also believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. It is particularly preferable for an insulating layer to contain crystals having an orthorhombic crystal structure, as this will exhibit ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0084] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0085] A metal oxide containing one or both of hafnium and zirconium is preferable as the ferroelectric layer because it can have ferroelectricity even in a thin film of a few nanometers as described above. The film thickness of the ferroelectric layer 130 is preferably 0.1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, and even more preferably 5 nm or more and 15 nm or more, and can be typically 10 nm.

[0086] Furthermore, a metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even in a small area, and is therefore preferable as a material having a ferroelectric layer. ２ Below, 10μm ２ Below, 1μm ２ or less than 0.1 μm ２ Even if the thickness is less than 10,000 nm, the film can still have ferroelectricity. ２ or less than 1000 nm ２ Even if the thickness is less than 100 Å, the ferroelectric layer may have ferroelectricity. By using a ferroelectric layer with a small area, the area occupied by the capacitor 100 can be reduced.

[0087] Here, when a metal oxide or a metal oxynitride is used as the ferroelectric layer 130, if oxygen contained in the ferroelectric layer 130 is desorbed, the remanent polarization may decrease when data is repeatedly rewritten to the ferroelectric memory including the capacitor 100. Furthermore, if data is repeatedly rewritten to the ferroelectric memory including the capacitor 100, the withstand voltage of the capacitor 100 may decrease. Therefore, if oxygen is desorbed from the ferroelectric layer 130, the reliability of the ferroelectric memory may decrease.

[0088] Therefore, in one embodiment of the present invention, the conductive layer 115 has an oxide region 115ox. The oxide region 115ox includes a region in contact with the ferroelectric layer 130. For example, the region of the conductive layer 115 in contact with the ferroelectric layer 130 and a region in the vicinity thereof are defined as the oxide region 115ox. For example, the oxide region 115ox is formed by performing an oxidation treatment on the conductive layer 115 after the formation of the conductive layer 115 and before the formation of the ferroelectric layer 130. The oxygen content in the oxide region 115ox is higher than the oxygen content in the region of the conductive layer 120 in contact with the ferroelectric layer 130, for example.

[0089] As a result, compared to when the ferroelectric layer 130 is formed without forming the oxide region 115ox in the conductive layer 115, it is possible to suppress absorption of oxygen contained in the ferroelectric layer 130 by the conductive layer 115. This makes it possible to suppress desorption of oxygen from the ferroelectric layer 130 and a decrease in the reliability of the ferroelectric memory. As a result, one aspect of the present invention can realize a highly reliable semiconductor device.

[0090] In this specification and the like, the oxide region 115ox is included in the conductive layer 115, that is, the oxide region 115ox can be part of the conductive layer 115. Note that the oxide region 115ox does not necessarily have to be included in the conductive layer 115.

[0091] The conductive layer 115 is preferably made of a conductive material that maintains low electrical resistance even when oxidized. This allows the electrical resistance of the oxide region 115ox to be maintained low. Therefore, an increase in the electrical resistance of the conductive layer 115 due to the formation of the oxide region 115ox can be suppressed. Therefore, even when the oxide region 115ox is formed in the conductive layer 115, a semiconductor device that operates at high speed can be realized. The conductive layer 115 is preferably made of, for example, a conductive material containing nitrogen. Examples of the conductive layer 115 that can be used include titanium nitride, tantalum nitride, ruthenium nitride, nitrides containing molybdenum, nitrides containing tungsten, titanium, and aluminum, and nitrides containing tantalum and aluminum.

[0092] The oxide region 115ox can contain an element contained in the conductive layer 115, such as an oxide of a metal element. When the conductive layer 115 contains nitrogen, the oxide region 115ox can contain an element contained in the conductive layer 115, such as an oxynitride of a metal element. For example, when titanium nitride is used as the conductive layer 115, the oxide region 115ox can contain titanium oxide and titanium oxynitride.

[0093] The oxidation treatment for forming the oxide region 115ox may be, for example, a method of forming an insulating layer containing oxygen and then removing the insulating layer. The insulating layer containing oxygen may be, for example, silicon oxide.

[0094] 4B is a diagram showing an example in which the entire conductive layer 115 shown in FIG. 4A is an oxide region 115ox. When the conductive layer 115 is thin, the entire conductive layer 115 may become the oxide region 115ox by the above-described oxidation treatment. Even in this case, by using a conductive material that maintains low electrical resistance even after oxidization for the conductive layer 115, the conductive layer 115 can function as one of a pair of electrodes of the capacitor 100.

[0095] As shown in FIGS. 4A and 4B , the top surface 103 of the conductive layer 115 can be located at a lower height from a reference plane than the top surface 105 of the insulating layer 180. The reference plane can be, for example, the top surface of the substrate or the top surface of the insulating layer 140. The angle θ of the top surface 103 relative to the reference plane can be greater than 0°. That is, the top surface 103 can have a tapered shape. Specifically, the height from the reference plane of the end of the top surface 103 opposite the insulating layer 180 (toward the center of the opening 190) can be lower than the height from the reference plane of the end of the top surface 103 on the insulating layer 180 side. Here, the top surface 103 can be rephrased as the top surface of the conductive layer 115, specifically the top surface including the topmost part of the conductive layer 115 (the part with the highest height from the reference plane).

[0096] As a result, it is possible to prevent electric field concentration in the ferroelectric layer 130 near the upper end surface 103. This makes it possible to prevent dielectric breakdown in the ferroelectric layer 130, thereby realizing a highly reliable semiconductor device.

[0097] Here, the larger the angle θ, the more effectively the electric field concentration on the ferroelectric layer 130 in the vicinity of the upper end surface 103 can be suppressed. On the other hand, if the angle θ is too large, it becomes difficult to fabricate the conductive layer 115. In light of the above, the angle θ is preferably greater than 5° and less than 85°, more preferably 10° to 80°, even more preferably 15° to 70°, and still more preferably 20° to 60°.

[0098] 4A and 4B show an example in which the region 102 between the upper surface 105 of the insulating layer 180 and the side surface of the opening 190 has a curved portion. The curved portion of the region 102 allows the ferroelectric layer 130 to cover the region 102 with good coverage. This makes it possible to prevent, for example, discontinuity of the ferroelectric layer 130, thereby realizing a highly reliable semiconductor device.

[0099] 4A and 4B show an example in which a region 101 between the side surface and bottom surface of the conductive layer 115 has a curved portion within the recess of the conductive layer 110. By having the curved portion in the region 101, it is possible to suppress electric field concentration in the ferroelectric layer 130 near the region 101. This makes it possible to prevent dielectric breakdown of the ferroelectric layer 130, and to realize a highly reliable semiconductor device.

[0100] The conductive layer 120 is provided on the ferroelectric layer 130 so as to have a region inside the opening 190 that faces the conductive layer 115 with the ferroelectric layer 130 sandwiched therebetween. The conductive layer 120 is provided so as to fill the opening 190. Note that FIGS. 1A to 3B show an example in which the upper end of the ferroelectric layer 130 coincides or approximately coincides with the lower end of the conductive layer 120.

[0101] 1A, 1B, 3A, 3B, etc., an example in which the conductive layer 120 has a two-layer structure including a conductive layer 120_1 and a conductive layer 120_2 over the conductive layer 120_1 is shown. The conductive layer 120_1 can be provided so as to fill the opening 190.

[0102] 3C , the ferroelectric layer 130 can be provided to cover the conductive layer 120_1, and the conductive layer 115 can be provided to cover the ferroelectric layer 130. For example, when the opening 190 of the insulating layer 180 has a circular shape in a plan view, the conductive layer 120_1 can be provided at the center of the circle. The outer periphery of the conductive layer 120_1, the outer periphery of the ferroelectric layer 130, and the outer periphery of the conductive layer 115 can be concentrically arranged around the center of the opening 190.

[0103] 3C , 4A , and 4B show the width D of the opening 190 in the insulating layer 180. Specifically, the width D is the width of the opening 190 in the region between the region 101 and the region 102. For example, if the shape of the opening 190 in a plan view is circular, the width D corresponds to the diameter of the circle. By making the film thickness of the conductive layer 120_1 thicker than the film thickness of the conductive layer 115, the film thickness of the ferroelectric layer 130, and the width D, the conductive layer 120_1 can be provided so as to fill the opening 190. For example, if the film thickness of the conductive layer 115 is 5 nm, the film thickness of the ferroelectric layer 130 is 10 nm, and the width D is 60 nm, the film thickness of the conductive layer 120_1 outside the opening 190 can be made 15 nm or more, so that the conductive layer 120_1 can be provided so as to fill the opening 190.

[0104] The thickness of the conductive layer 120_1 outside the opening 190 is preferably, for example, 15 nm to 100 nm, more preferably 20 nm to 70 nm, and even more preferably 25 nm to 50 nm, and typically can be 30 nm.

[0105] When the conductive layer 120_1 is provided so as to fill the opening 190, it is preferable to use a conductive material having a larger thermal expansion coefficient than the conductive material used for the conductive layer 120_2 as the conductive layer 120_1. This makes it easier for tensile stress to be applied from the conductive layer 120_1 to the ferroelectric layer 130 when the temperature is lowered after the heat treatment. The application of tensile stress to the ferroelectric layer 130 makes it easier for the crystal structure of the ferroelectric layer 130 to exhibit ferroelectricity. For example, crystals having an orthorhombic crystal structure are more likely to be formed in the ferroelectric layer 130. This increases the proportion of crystals having an orthorhombic crystal structure in the ferroelectric layer 130, thereby increasing the amount of remanent polarization. As a result, a highly reliable semiconductor device can be realized.

[0106] The conductive layer 120_2 is preferably formed using a material with high conductivity, for example, a material with higher conductivity than the conductive layer 120_1. This can reduce the electrical resistance of the conductive layer 120 compared to when the conductive layer 120 has a single-layer structure of the conductive layer 120_1. Therefore, a semiconductor device that operates at high speed can be realized.

[0107] The thickness of the conductive layer 120_2 in the region not overlapping with the opening 190 is, for example, preferably 5 nm to 500 nm, more preferably 10 nm to 100 nm, still more preferably 20 nm to 70 nm, and even more preferably 30 nm to 50 nm. Here, increasing the thickness of the conductive layer 120_2 makes it easier to reduce the electrical resistance of the conductive layer 120. For example, setting the thickness of the conductive layer 120_2 in the region not overlapping with the opening 190 to be equal to or greater than the thickness of the conductive layer 120_1 in that region makes it easier to reduce the electrical resistance of the conductive layer 120. For example, when the thickness of the conductive layer 120_1 outside the opening 190 is 30 nm, the thickness of the conductive layer 120_2 in that region is preferably 30 nm or more, more preferably 35 nm or more, and typically 40 nm.

[0108] As described above, it is preferable to use a material having a larger thermal expansion coefficient than the conductive layer 120_2 for the conductive layer 120_1, and a material having a higher conductivity than the conductive layer 120_1 for the conductive layer 120_2. For example, it is preferable to use titanium nitride for the conductive layer 120_1, and tungsten for the conductive layer 120_2.

[0109] As described above, a semiconductor device having the capacitor 100 can be a highly reliable semiconductor device.

[0110] 5A and 5B are diagrams showing an example in which the insulating layer 180 shown in FIGS. 3A and 3B has a three-layer structure including an insulating layer 180a, an insulating layer 180b on the insulating layer 180a, and an insulating layer 180c on the insulating layer 180b. Also, FIGS. 5A and 5B show an example in which the upper surface of the insulating layer 180b is flat. The insulating layer 180 may have a two-layer structure or a stacked structure of four or more layers.

[0111] The insulating layer 180a and the insulating layer 180c can be formed using a barrier insulating layer against oxygen. By using a barrier insulating layer against oxygen as the insulating layer 180a, it is possible to prevent the conductive layer 110 from being oxidized and the electrical resistance from increasing. By using a barrier insulating layer against oxygen as the insulating layer 180c, it is possible to prevent the conductive layer 120 from being oxidized and the electrical resistance from increasing. As described above, a semiconductor device that operates at high speed can be realized.

[0112] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties are defined as a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, and NO ２The term "oxygen" when used in reference to a corresponding substance refers to at least one of an oxygen atom, an oxygen molecule, and the like.

[0113] The insulating layer 180a and the insulating layer 180c can be formed using, for example, silicon nitride, silicon nitride oxide, an oxide containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, etc. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate).

[0114] The insulating layer 180b can be made of a material having a lower dielectric constant than the insulating layers 180a and 180c. This can suppress the formation of parasitic capacitance between the conductive layer 110 and the conductive layer 120, for example. This makes it possible to realize a semiconductor device that operates at high speed. The insulating layer 180b can be made of, for example, silicon oxide or silicon oxynitride.

[0115] The thickness of the insulating layer 180b is preferably equal to or greater than the thicknesses of the insulating layers 180a and 180c. This effectively prevents the formation of the parasitic capacitance described above. For example, the thickness of the insulating layer 180b in the region overlapping with the conductive layer 110 is preferably 60 nm to 3000 nm, more preferably 60 nm to 1000 nm, even more preferably 100 nm to 800 nm, still more preferably 200 nm to 600 nm, and even more preferably 300 nm to 400 nm, and typically 350 nm.

[0116] 6A and 6B are diagrams showing an example in which the conductive layer 115 shown in FIGS. 3A and 3B does not have an oxide region 115ox, and an insulating layer 116 is provided between the conductive layer 115 and the ferroelectric layer 130. As shown in FIGS. 6A and 6B , the insulating layer 116 is provided on the conductive layer 115 and the insulating layer 180 so as to have a region in contact with the conductive layer 115 inside the opening 190. The insulating layer 116 is provided so as to cover the conductive layer 115. The insulating layer 116 is provided along the side and top surfaces of the conductive layer 115 inside the opening 190. The insulating layer 116 can function as a dielectric of the capacitor 100.

[0117] 6A and 6B, the ferroelectric layer 130 is provided on the insulating layer 116. The ferroelectric layer 130 is provided inside the opening 190 along the side and top surfaces of the insulating layer 116.

[0118] 6A and 6B , the absorption of oxygen contained in the ferroelectric layer 130 into the conductive layer 115 can be suppressed more effectively than in the case where the insulating layer 116 is not provided and the conductive layer 115 does not have the oxide region 115ox. This can suppress the desorption of oxygen from the ferroelectric layer 130. As a result, a highly reliable semiconductor device can be realized.

[0119] For example, a nitride film, an oxide film, or an oxynitride film can be used as the insulating layer 116. Here, it is preferable to use a material with a high relative dielectric constant for the insulating layer 116, since this can increase the capacitance of the capacitor 100. For example, a silicon nitride film, a titanium oxide film, or a hafnium oxynitride film can be used as the insulating layer 116.

[0120] Furthermore, it is preferable to make the film thickness of the insulating layer 116 as thin as possible compared with the film thickness of the ferroelectric layer 130, since this increases the electrostatic capacitance of the capacitor 100. The film thickness of the insulating layer 116 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.2 nm or more and 5 nm or less, even more preferably 0.3 nm or more and 3 nm or less, and still more preferably 0.5 nm or more and 1 nm or less.

[0121] 7A is a circuit diagram showing a configuration example of a memory cell 150. The memory cell 150 has a capacitor 100 and a transistor 200. As described above, the capacitor 100 is a ferroelectric capacitor. Therefore, the memory cell 150 is a ferroelectric memory.

[0122] One of a pair of electrodes of the capacitor 100 is connected to a wiring PL. The other of the pair of electrodes of the capacitor 100 is connected to one of a source and a drain of the transistor 200. The other of the source and the drain of the transistor 200 is connected to a wiring BL. A gate of the transistor 200 is connected to a wiring WL.

[0123] The wiring PL functions as a power supply line for applying a predetermined potential to one of a pair of electrodes of the capacitor 100. The wiring BL functions as a bit line for writing data to the memory cell 150 and reading data from the memory cell 150. The wiring WL functions as a word line for controlling whether the transistor 200 is turned on or off.

[0124] Fig. 7B is a perspective view showing an example of the configuration of the memory cell 150. Fig. 8A is a plan view showing an example of the configuration of the memory cell 150. Figs. 8B and 8C are plan views showing some elements extracted from Fig. 8A.

[0125] Fig. 9A is a cross-sectional view taken along dashed lines A1-A2 in Fig. 8A to 8C. Fig. 9B is a cross-sectional view taken along dashed lines B1-B2 in Fig. 8A to 8C. Fig. 10A is a cross-sectional view taken along dashed lines A3-A3 in Fig. 8A to 8C. Fig. 10B is a cross-sectional view taken along dashed lines B3-B4 in Fig. 8A to 8C.

[0126] 9A and 9B show configuration examples of the capacitor 100. The configurations of the capacitor 100 shown in Figures 9A and 9B are similar to those of the capacitor 100 shown in Figures 3A and 3B, respectively. Note that the insulating layer 180 may have a stacked structure, similar to the insulating layer 180 shown in Figures 5A and 5B, for example.

[0127] 7B to 10B includes an insulating layer 140 over a substrate (not shown), a conductive layer 110 over the insulating layer 140, a capacitor 100 over the conductive layer 110, an insulating layer 180 over the conductive layer 110 and the insulating layer 140, a transistor 200 over the capacitor 100, an insulating layer 280 over the capacitor 100 and the insulating layer 180, an insulating layer 283 over the transistor 200 and the insulating layer 280, an insulating layer 285 over the insulating layer 283, a conductive layer 244a, a conductive layer 244b, and a conductive layer 245 over the conductive layer 244a, the conductive layer 244b, and the insulating layer 285. Here, the insulating layer 280 and the insulating layer 285 function as interlayer insulating layers and preferably have flat top surfaces.

[0128] The transistor 200 includes a conductive layer 120, conductive layers 240a and 240b over an insulating layer 280, a semiconductor layer 230 over the conductive layer 120, the conductive layer 240a, and the conductive layer 240b, an insulating layer 250 over the semiconductor layer 230, and a conductive layer 260 over the insulating layer 250. The semiconductor layer 230 can be formed using, for example, a metal oxide. In this case, the transistor 200 is an OS transistor.

[0129] The conductive layer 260 has a region that functions as a gate electrode of the transistor 200. The insulating layer 250 has a region that functions as a gate insulating layer of the transistor 200. The conductive layer 120 has a region that functions as one of a source electrode and a drain electrode of the transistor 200. The conductive layer 240a and the conductive layer 240b function as the other of the source electrode and the drain electrode of the transistor 200 and are connected to each other through the conductive layer 244a, the conductive layer 244b, and the conductive layer 245.

[0130] Fig. 8B shows the conductive layer 120, the semiconductor layer 230, the conductive layer 240a, the conductive layer 240b, and the insulating layer 280b selected from the elements shown in Fig. 8A. Fig. 8C shows the conductive layer 120, the conductive layer 240a, the conductive layer 240b, and the insulating layer 280b selected from the elements shown in Fig. 8A. That is, Fig. 8C omits the semiconductor layer 230 from Fig. 8B.

[0131] In the memory cell 150, the conductive layer 110 has a region that functions as the wiring PL shown in Fig. 7A. The conductive layer 260 has a region that functions as the wiring WL shown in Fig. 7A. The conductive layer 245 has a region that functions as the wiring BL shown in Fig. 7A.

[0132] 7B to 10B show an example in which the conductive layer 110, the conductive layer 260, and the conductive layer 245 are provided in a strip shape. In FIGS. 7B to 10B, an example is shown in which the conductive layer 245 extends in the X direction, and the conductive layer 110 and the conductive layer 260 extend in the Y direction. That is, in a plan view, FIGS. 7B to 10B show an example in which the wiring PL is provided parallel to the wiring WL and perpendicular to the wiring BL. Note that the wiring PL does not have to be provided parallel to the wiring WL, and may be provided parallel to the wiring BL, for example.

[0133] 7B and 9A to 10B show an example in which the insulating layer 280 has a three-layer structure including an insulating layer 280a, an insulating layer 280b on the insulating layer 280a, and an insulating layer 280c on the insulating layer 280b. Note that the insulating layer 280 may have a two-layer structure or a stacked structure of four or more layers.

[0134] 9A and 9B , the insulating layer 280a has a region in contact with the conductive layer 120. Specifically, the insulating layer 280a has a region in contact with the side surface of the conductive layer 120. The insulating layer 280a may have a region in contact with the top surface of the conductive layer 120, and may also have a region in contact with the ferroelectric layer 130. Furthermore, the insulating layer 280a may have a region in contact with the top surface of the insulating layer 180.

[0135] The insulating layers 280a, 280b, and 280c each have a groove 290. The groove 290 extends in a direction parallel to the direction in which the conductive layer 260 extends.

[0136] In this specification and the like, a groove can be rephrased as a slit or a trench. Also, a groove portion can be rephrased as a slit portion or a trench portion. Note that a groove portion may also be rephrased as a slit or a trench.

[0137] The groove portion 290 has a region that reaches the conductive layer 120. The groove portion 290 is provided as a recess in a region of the insulating layer 280a that does not overlap with the conductive layer 120. Note that FIG. 9A shows an example in which the conductive layer 120 has a recess. The recess can be included in the groove portion 290. Note that the recess does not have to be included in the groove portion 290. FIGS. 9A to 10A show an example in which the depth of the groove portion 290 in the region that does not overlap with the conductive layer 120 is deeper than the depth of the groove portion 290 in the region that overlaps with the conductive layer 120.

[0138] When the bottom surface of the recess in the conductive layer 120 is included in the groove 290, the bottom of the groove 290 includes the bottom surface of the recess in the conductive layer 120. Furthermore, the sidewall of the groove 290 includes the side surface of the recess in the conductive layer 120, the side surface of the insulating layer 280a, the side surface of the insulating layer 280b, and the side surface of the insulating layer 280c.

[0139] In the above case, the bottom of groove 290 includes the upper surface of conductive layer 120 and the upper surface of insulating layer 280a. In other words, the bottom of groove 290 includes the bottom surface of the recess in conductive layer 120 and the bottom surface of the recess in insulating layer 280a. Furthermore, the sidewall of groove 290 includes the side surface of the recess in conductive layer 120, the side surface of insulating layer 280a, the side surface of insulating layer 280b, and the side surface of insulating layer 280c. Groove 290 includes the groove in conductive layer 120, the groove in insulating layer 280a, the groove in insulating layer 280b, and the groove in insulating layer 280c.

[0140] In this specification and the like, the groove 290 provided in the insulating layer 280a may be referred to as a first groove. The groove 290 provided in the insulating layer 280b may be referred to as a second groove. The groove 290 provided in the insulating layer 280c may be referred to as a third groove. The first groove, the second groove, and the third groove may be provided so as to overlap one another. The recesses of the conductive layer 120 may be provided so as to overlap the first groove, the second groove, and the third groove. Note that the ordinal numbers may be interchanged as appropriate.

[0141] The groove portion 290 can be formed by processing the insulating layer 280c, the insulating layer 280b, and the insulating layer 280a using an etching process. In particular, a dry etching process is preferable because it is suitable for fine processing. Furthermore, for example, a recess can be formed in the conductive layer 120 by the dry etching process. The recess can be included in the groove portion 290 as described above.

[0142] Here, it is preferable to process the insulating layer 280b under conditions different from those for processing the insulating layer 280a. Specifically, it is preferable to process the insulating layer 280b under conditions that provide a high selectivity with respect to the insulating layer 280a. This makes it possible to prevent a portion of the insulating layer 280a from being unintentionally removed during processing of the insulating layer 280b.

[0143] In the region not overlapping with the groove 290, the top surface of the insulating layer 280a, the top surface of the insulating layer 280b, and the top surface of the insulating layer 280c can be flat. For example, after the insulating layer 280a is formed, planarization treatment is performed on the insulating layer 280a. As the planarization treatment, chemical mechanical polishing (CMP) treatment is preferable. Note that as the planarization treatment, treatment using etching (also referred to as etch-back treatment) may be performed. After the planarization treatment is performed on the insulating layer 280a, the insulating layer 280b and the insulating layer 280c are formed over the insulating layer 280a, so that the top surfaces of the insulating layer 280b and the insulating layer 280c can be flat. Here, by performing planarization treatment on the insulating layer 280a, for example, the thickness of the insulating layer 280a in the region overlapping with the conductive layer 120 can be made thinner than the thickness of the insulating layer 280a in the region not overlapping with the conductive layer 120.

[0144] The insulating layer 280a and the insulating layer 280c can be made of a barrier insulating layer against oxygen. The insulating layer 280b can be made of a material having a lower dielectric constant than the insulating layer 280a and the insulating layer 280c. By using a barrier insulating layer against oxygen as the insulating layer 280a, it is possible to prevent the conductive layer 120 from oxidizing and increasing its electrical resistance. By using a barrier insulating layer against oxygen as the insulating layer 280c, it is possible to prevent the conductive layer 240a and the conductive layer 240b from oxidizing and increasing their electrical resistance. By using a material having a lower dielectric constant than the insulating layer 280a and the insulating layer 280c as the insulating layer 280b, it is possible to prevent the formation of parasitic capacitance, for example, between the conductive layer 120 and the conductive layer 240a and between the conductive layer 120 and the conductive layer 240b. This makes it possible to realize a semiconductor device that operates at high speed.

[0145] The insulating layer 280a can be made of the same material as that used for the insulating layer 180a shown in Figures 5A and 5B. The insulating layer 280b can be made of the same material as that used for the insulating layer 180b shown in Figures 5A and 5B. The insulating layer 280c can be made of the same material as that used for the insulating layer 180c shown in Figures 5A and 5B.

[0146] Here, it is preferable that the thickness of the insulating layer 280b is equal to or greater than the thickness of the insulating layer 280c, because this effectively prevents parasitic capacitance from forming between the conductive layer 120 and the conductive layer 240a, and between the conductive layer 120 and the conductive layer 240b. When the thickness of the insulating layer 280b is equal to or greater than the thickness of the insulating layer 280c, i.e., when the thickness of the insulating layer 280c is equal to or less than the thickness of the insulating layer 280b, the thickness of the insulating layer 280c can be equal to or less than the thickness of the insulating layer 280a in the region where it does not overlap with the conductive layer 120. Furthermore, the thickness of the insulating layer 280c can be set to be approximately the same as the thickness of the insulating layer 280a in the region where it overlaps with the conductive layer 120. Note that the thickness of the insulating layer 280b, for example, affects the channel length of the transistor 200. Therefore, for example, the thickness of the insulating layer 280b is appropriately set according to the design value of the channel length of the transistor 200. Note that the thickness of the insulating layer 280c may also be set according to the design value of the channel length of the transistor 200.

[0147] The insulating layer 280b preferably has a region containing excess oxygen. This allows oxygen to be supplied from the insulating layer 280b to the semiconductor layer 230. Therefore, oxygen vacancies and V Ｏ H can be reduced.

[0148] The concentrations of impurities such as hydrogen or water in the insulating layer 180, the insulating layer 280a, the insulating layer 280b, and the insulating layer 280c are preferably reduced, which can prevent impurities such as hydrogen or water from entering the channel formation region of the transistor 200. For example, by forming the insulating layer 180, the insulating layer 280a, the insulating layer 280b, and the insulating layer 280c by a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentrations in the insulating layer 180, the insulating layer 280a, the insulating layer 280b, and the insulating layer 280c can be reduced.

[0149] At least some of the components of the transistor 200 are disposed inside the groove 290. Specifically, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are disposed so that at least some of them are located inside the groove 290. The conductive layer 240a and the conductive layer 240b are provided so as to face each other across the groove 290 in a plan view. Note that the groove 290 may be provided not only between the insulating layer 280a, the insulating layer 280b, and the insulating layer 280c, but also between the conductive layer 240a and the conductive layer 240b.

[0150] The width of the groove 290 in a direction perpendicular to the extension direction, for example, the width of the groove 290 in the X direction, is set by the film thickness of each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided inside the groove 290. The width of the groove 290 in a direction perpendicular to the extension direction is, for example, preferably 5 nm to 300 nm, more preferably 5 nm to 200 nm, more preferably 5 nm to 100 nm, more preferably 10 nm to 60 nm, more preferably 10 nm to 50 nm, more preferably 20 nm to 40 nm, and even more preferably 20 nm to 30 nm.

[0151] 8A to 9A show an example in which the inner side surface of the conductive layer 240a (the groove 290 side in plan view) coincides or substantially coincides with the sidewall of the groove 290. Also shown is an example in which the inner side surface of the conductive layer 240b (the groove 290 side in plan view) coincides or substantially coincides with the sidewall of the groove 290. With this configuration, the conductive layer 240a, the conductive layer 240b, and the groove 290 can be formed simultaneously.

[0152] The semiconductor layer 230 is provided so as to cover a portion of the groove 290. The semiconductor layer 230 has a region in contact with the upper surface of the conductive layer 240a outside the groove 290, a region in contact with the side surface of the conductive layer 240a, a region in contact with the upper surface of the conductive layer 240b, and a region in contact with the side surface of the conductive layer 240b. The semiconductor layer 230 also has a region in contact with the conductive layer 120 inside the groove 290. Specifically, the semiconductor layer 230 can have a region in contact with the bottom surface of the recess of the conductive layer 120 inside the groove 290 and a region in contact with the side surface of the recess.

[0153] Furthermore, the semiconductor layer 230 has a region along the sidewall of the groove 290. Inside the groove 290, the semiconductor layer 230 can have a region in contact with the side surface of the insulating layer 280a, a region in contact with the side surface of the insulating layer 280b, and a region in contact with the side surface of the insulating layer 280c.

[0154] 8A to 10B show an example in which the end of the semiconductor layer 230 is located outside the end of the conductive layer 240a and the end of the conductive layer 240b in the region where it does not overlap the groove 290. In the example shown in FIGS. 8A to 10B, it can be said that the semiconductor layer 230 covers the entire conductive layer 240a and the entire conductive layer 240b. Note that the lower end of the semiconductor layer 230 may have a region that coincides or substantially coincides with the upper end of the conductive layer 240a and a region that coincides or substantially coincides with the upper end of the conductive layer 240b in the region where it does not overlap the groove 290. Furthermore, the end of the semiconductor layer 230 may be located inside the end of the conductive layer 240a and the end of the conductive layer 240b in the region where it does not overlap the groove 290. That is, the end of the semiconductor layer 230 may have a region that overlaps with the conductive layer 240a and a region that overlaps with the conductive layer 240b in the region where it does not overlap the groove 290.

[0155] For example, a metal oxide can be used for the semiconductor layer 230. Indium oxide (also referred to as indium oxide) is preferably used as the metal oxide. This enables the transistor 200 to have a large on-state current. Furthermore, the transistor 200 can have a small off-state current. Note that indium oxide will be described in detail in Embodiment 2.

[0156] A metal oxide other than indium oxide may be used for the semiconductor layer 230. Examples of metal oxides other than indium oxide include oxides containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO). By using IGZO for the semiconductor layer 230, the transistor 200 can have a low off-state current.

[0157] The thickness of the semiconductor layer 230 is preferably 1 nm or more and 50 nm or less, more preferably 2 nm or more and 30 nm or less, more preferably 2.5 nm or more and 20 nm or less, more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 10 nm or less. It is preferable that at least a part of the semiconductor layer 230 has a region with the above-described thickness. For example, it is preferable that the channel formation region of the semiconductor layer 230 has a region with the above-described thickness. By setting the thickness of the semiconductor layer 230 within the above range, the crystallinity of the semiconductor layer 230 can be improved. By improving the crystallinity of the semiconductor layer 230, the semiconductor layer 230 can have crystal grains.

[0158] The insulating layer 250 is provided on the semiconductor layer 230 so as to have a region located inside the groove 290. The insulating layer 250 can be provided so as to cover the semiconductor layer 230.

[0159] The conductive layer 260 is provided on the insulating layer 250 so as to have a region located inside the groove 290. The conductive layer 260 can be provided so as to fill the groove 290. The conductive layer 260 has a region inside the groove 290 that faces the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0160] As described above, the semiconductor layer 230 is provided inside the groove 290. In addition, the transistor 200 has a configuration in which one of the source electrode and the drain electrode (here, the conductive layer 120) is located on the bottom and the other of the source electrode and the drain electrode (here, the conductive layer 240 a and the conductive layer 240 b) is located on the top, and thus current flows in the vertical direction. In other words, a channel is formed along the sidewall of the groove 290.

[0161] In the semiconductor layer 230, a region facing the conductive layer 260 with the insulating layer 250 sandwiched therebetween inside the groove 290 and a region in the vicinity thereof function as a channel formation region of the transistor 200. A region in the vicinity of the conductive layer 120 of the semiconductor layer 230 functions as one of a source region and a drain region. At least one of a region in the vicinity of the conductive layer 240a and a region in the vicinity of the conductive layer 240b of the semiconductor layer 230 functions as the other of the source region and the drain region. In other words, the channel formation region is sandwiched between the source region and the drain region. The source region and the drain region are low-resistance regions with higher carrier concentrations than the channel formation region.

[0162] With the above configuration, a channel formation region and a source region or a drain region can be formed inside the groove 290. This allows the transistor 200 to occupy a smaller area than a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for miniaturization or high integration of semiconductor devices.

[0163] The channel length of the transistor 200 is the distance between the source region and the drain region in the semiconductor layer 230. In FIG. 9A , the channel length Lc of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length Lc is the distance between the edge of the region where the semiconductor layer 230 and the conductive layer 240a contact each other and the edge of the region where the semiconductor layer 230 and the conductive layer 120 contact each other. Note that the channel length Lc may also be the distance between the edge of the region where the semiconductor layer 230 and the conductive layer 240b contact each other and the edge of the region where the semiconductor layer 230 and the conductive layer 120 contact each other in a cross-sectional view.

[0164] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. On the other hand, the channel length of the transistor 200 can be set by the film thicknesses of the insulating layers 280a, 280b, and 280c. Therefore, the channel length of the transistor 200 can be made into a very fine structure (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more) that is equal to or less than the exposure limit of photolithography. This increases the on-state current of the transistor 200, thereby improving its frequency characteristics.

[0165] Note that the channel length of the transistor 200 is determined by the film thicknesses of the insulating layers 280a, 280b, and 280c, etc. Therefore, the channel length does not affect the area occupied by the transistor 200, for example, the area of ​​the transistor 200 in a plan view. By setting the channel length of the transistor 200 to, for example, 1 μm or less, 500 nm or less, or 300 nm or less, productivity and yield can be improved in the formation of the groove 290, etc.

[0166] From the above, the channel length of the transistor included in the semiconductor device of one embodiment of the present invention is preferably 0.1 nm to 1 μm, more preferably 1 nm to 500 nm, and still more preferably 5 nm to 300 nm.

[0167] Here, by having a recess in the conductive layer 120 at a position overlapping the groove 290 of the insulating layer 280a, for example, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 260 inside the groove 290 can be lowered compared to when the recess is not provided. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Note that the surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the top surface of a substrate on which the semiconductor device is provided may be used as the reference.

[0168] By reducing the height of the bottom surface of the conductive layer 260, a gate electric field can be easily applied to the semiconductor layer 230. This can improve the electrical characteristics of the transistor 200. Furthermore, regardless of whether the conductive layer 120 or the conductive layer 240a and the conductive layer 240b is used as the drain electrode, the electrical characteristics of the transistor 200 can be improved.

[0169] In the semiconductor device of one embodiment of the present invention, when the semiconductor layer 230 is formed, a semiconductor film is formed so as to cover the groove 290, and then the semiconductor film is processed to remove a part of the semiconductor film. The semiconductor film can be processed by etching. In particular, dry etching is preferably used because it enables miniaturization or high integration of the semiconductor device. Here, when the semiconductor film is processed to form the semiconductor layer 230, a part of a region of the semiconductor film along the sidewall of the groove 290 is removed. The removal of the region is preferably performed under isotropic conditions.

[0170] When a semiconductor film is processed using a dry etching process under isotropic conditions, ions contained in the etching gas may not be sufficiently accelerated. This may result in a long processing time for the semiconductor film. Therefore, if, for example, a portion of the ferroelectric layer 130 is exposed due to the formation of the groove 290, the ferroelectric layer 130 will be exposed to the etching gas for a long time. This makes the ferroelectric layer 130 more susceptible to unintentional processing. Therefore, by providing the insulating layer 280a as described above, even when processing the semiconductor film requires a long time, it is possible to prevent, for example, the ferroelectric layer 130 from being unintentionally processed and partially removed. This prevents fluctuations in the electrical characteristics of, for example, the capacitor 100, thereby achieving a highly reliable semiconductor device. Furthermore, the manufacturing yield of the semiconductor device can be increased, thereby providing a semiconductor device that can be manufactured at low cost. Furthermore, the ferroelectric layer 130 can be made of a material with a low etching selectivity with respect to the semiconductor layer 230. This widens the range of materials that can be selected for the ferroelectric layer 130.

[0171] The insulating layer 283 is located over the conductive layer 260 and the insulating layer 250. The insulating layer 283 can be a barrier insulating layer against impurities such as hydrogen. This can prevent impurities such as hydrogen from penetrating into the transistor 200. Therefore, a highly reliable semiconductor device can be provided. An example of a barrier insulating layer against hydrogen is a silicon nitride film. Note that details of materials for the barrier insulating layer against hydrogen will be described later.

[0172] The insulating layer 285 is located over the insulating layer 283. The insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230 have an opening 270a that reaches the conductive layer 240a and an opening 270b that reaches the conductive layer 240b. A conductive layer 244a is provided in the opening 270a, and a conductive layer 244b is provided in the opening 270b. For example, the conductive layer 244a is provided to fill the opening 270a, and the conductive layer 244b is provided to fill the opening 270b. The conductive layer 244a may have a region in contact with the conductive layer 240a in the opening 270a. The conductive layer 244b may have a region in contact with the conductive layer 240b in the opening 270b. Hereinafter, the openings 270a and 270b may be collectively referred to as the opening 270. The conductive layers 244a and 244b may be collectively referred to as the conductive layer 244.

[0173] The conductive layer 245 is provided over the insulating layer 285, the conductive layer 244a, and the conductive layer 244b. The conductive layer 245 can have a region in contact with the top surface of the conductive layer 244a and a region in contact with the top surface of the conductive layer 244b. As described above, the conductive layer 240a and the conductive layer 240b can be connected via the conductive layer 244a, the conductive layer 245, and the conductive layer 244b.

[0174] The conductive layer 245 overlaps with the conductive layer 260 with the insulating layer 283 and the insulating layer 285 interposed therebetween. This allows for a smaller parasitic capacitance than, for example, when the conductive layer 240a and the conductive layer 240b are extended in the Y direction without providing the conductive layer 245. For example, the parasitic capacitance between the conductive layer 240a and the conductive layer 260 and the parasitic capacitance between the conductive layer 240b and the conductive layer 260 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that the height of the top surfaces of the conductive layers 244a and 244b and the insulating layer 285 is preferably the same or approximately the same.

[0175] As described above, the conductive layer 245 intersects with the conductive layer 260 in a plan view, for example, perpendicular or substantially perpendicular to the conductive layer 260. This allows the area where the conductive layer 245 and the conductive layer 260 overlap to be smaller than when the conductive layer 245 and the conductive layer 260 are arranged parallel to each other in a plan view. Therefore, the parasitic capacitance generated between the conductive layer 260 and the conductive layer 245 can be reduced. Therefore, the semiconductor device of one embodiment of the present invention can be a semiconductor device capable of high-speed operation. Note that, for example, when the insulating layer 285 is sufficiently thick and the parasitic capacitance per unit area generated between the conductive layer 260 and the conductive layer 245 is negligibly small, the conductive layer 260 and the conductive layer 245 may be arranged parallel to each other in a plan view.

[0176] 9A and 10B show an example in which the conductive layer 240a has a two-layer structure including a conductive layer 240a_1 and a conductive layer 240a_2 over the conductive layer 240a_1, and an example in which the conductive layer 240b has a two-layer structure including a conductive layer 240b_1 and a conductive layer 240b_2 over the conductive layer 240b_1.

[0177] 9A and 10B show an example in which the opening 270a is provided not only in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230 but also in the conductive layer 240a_2. Similarly, FIG. 9A shows an example in which the opening 270b is provided also in the conductive layer 240b_2. Also, an example in which the opening 270a reaches the conductive layer 240a_1 and the opening 270b reaches the conductive layer 240b_1 is shown. In this case, the conductive layer 244a can have a region in contact with the top surface of the conductive layer 240a_1 and the side surface of the conductive layer 240a_2. Similarly, the conductive layer 244b can have a region in contact with the top surface of the conductive layer 240b_1 and the side surface of the conductive layer 240b_2.

[0178] By having the conductive layer 244a in contact with the top surface of the conductive layer 240a_1, the contact resistance between the conductive layer 240a and the conductive layer 244a can be reduced, even if the contact resistance per unit area between the conductive layer 240a_2 and the conductive layer 244a is greater than the contact resistance per unit area between the conductive layer 240a_1 and the conductive layer 244a. Furthermore, by having the conductive layer 244a in contact with the side surface of the conductive layer 240a_2, the contact area between the conductive layer 240a and the conductive layer 244a can be increased compared to when the conductive layer 244a is in contact with only the top surface of the conductive layer 240a, for example. This reduces the contact resistance between the conductive layer 240a and the conductive layer 244a. Similarly, by having the conductive layer 244b in contact with the top surface of the conductive layer 240b_1 and the side surface of the conductive layer 240b_2, the contact resistance between the conductive layer 240b and the conductive layer 244b can be reduced.

[0179] Note that the conductive layer 240a_2 does not have to have the opening 270a, and the conductive layer 240b_2 does not have to have the opening 270b. In this case, the opening 270a reaches the top surface of the conductive layer 240a_2, and the opening 270b reaches the top surface of the conductive layer 240b_2. When the conductive layer 240a_2 does not have the opening 270a, the opening 270a can be formed more easily than when the conductive layer 240a_2 has the opening 270a. Similarly, when the conductive layer 240b_2 does not have the opening 270b, the opening 270b can be formed more easily than when the conductive layer 240b_2 has the opening 270b.

[0180] 9A and 10B , the opening 270a includes an opening in the insulating layer 285, an opening in the insulating layer 283, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240a_2. Similarly, in the example shown in FIG. 9A , the opening 270b includes an opening in the insulating layer 285, an opening in the insulating layer 283, an opening in the insulating layer 250, an opening in the semiconductor layer 230, and an opening in the conductive layer 240b_2. Note that the shapes and sizes of the openings 270a and 270b in a plan view may differ depending on the layer. Furthermore, when the shapes of the openings 270a and 270b in a plan view are circular, the openings in each layer may or may not be concentric.

[0181] 9A to 10A show an example in which the conductive layer 260 has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. The conductive layer 260_1 can be disposed to surround the bottom and side surfaces of the conductive layer 260_2.

[0182] In the semiconductor device of one embodiment of the present invention, an insulating layer can be provided over the conductive layer 245 and the insulating layer 285. The insulating layer is preferably a barrier insulating layer against hydrogen. With such a structure, diffusion of hydrogen from above the transistor 200 to the semiconductor layer 230 can be suppressed.

[0183] 11A and 11B are diagrams showing an example in which the insulating layer 180 shown in Fig. 9A and Fig. 9B has a three-layer structure including an insulating layer 180a, an insulating layer 180b on the insulating layer 180a, and an insulating layer 180c on the insulating layer 180b. That is, Fig. 11A and Fig. 11B show an example in which the insulating layer 180 has the same configuration as Fig. 5A and Fig. 5B, respectively.

[0184] 11A and 11B , it is preferable that the concentration of impurities such as hydrogen or water is reduced in at least the insulating layer 180c among the insulating layers 180a, 180b, and 180c. The reduced impurity concentration in the insulating layer 180c, which is closest to the semiconductor layer 230 among the layers included in the insulating layer 180, can prevent impurities such as hydrogen or water from entering the channel formation region of the transistor 200. For example, the hydrogen concentration in the insulating layer 180c can be reduced by depositing the insulating layer 180c by a sputtering method that does not require the use of hydrogen-containing molecules in the deposition gas.

[0185] Here, the insulating layer 180a and the insulating layer 180b may be formed by a method other than sputtering. For example, the insulating layer 180a can be formed using atomic layer deposition (ALD). In this case, the insulating layer 180a can be formed so as to cover the conductive layer 110 with good coverage. Here, the insulating layer 180c may have a different film thickness from the insulating layer 180a. For example, if the insulating layer 180a is formed by the ALD method and the insulating layer 180c is formed by the sputtering method, the film thickness of the insulating layer 180c may be thicker than the film thickness of the insulating layer 180a.

[0186] 12 is a diagram showing an example in which the conductive layer 120 shown in FIG. 11A has a three-layer structure including a conductive layer 120_1, a conductive layer 120_2 on the conductive layer 120_1, and a conductive layer 120_3 on the conductive layer 120_2. Note that the conductive layer 120 shown in FIG. 9A may have a three-layer stacked structure, for example. FIG. 12 shows an example in which the conductive layer 120_3 has a recess.

[0187] The conductive layer 120_3 is preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a conductive metal oxide, or a conductive material that has a function of suppressing oxygen diffusion. The conductive layer 120_3 is preferably made of, for example, a conductive material containing oxygen. Specifically, the conductive layer 120_3 is preferably made of an oxide conductor. Examples of oxide conductors include indium tin oxide (In—Sn oxide, also referred to as ITO), indium tin oxide containing silicon oxide (also referred to as ITSO), and indium zinc oxide (In—Zn oxide, also referred to as IZO (registered trademark)).

[0188] By using an oxide conductor for the conductive layer 120_3 that is mainly in contact with the semiconductor layer 230, the contact resistance with the semiconductor layer 230 can be reduced. This shortens the current path between the source and the drain, and increases the on-state current of the transistor 200. With such a structure, the conductive layer 120 can maintain conductivity even when in contact with the semiconductor layer 230.

[0189] <Constituent Materials of Semiconductor Device> Materials that can be used in the semiconductor device of this embodiment will be described below. Note that each layer that constitutes the semiconductor device of this embodiment may have a single-layer structure or a multilayer structure.

[0190] [Semiconductor Layer] For example, a metal oxide can be used for the semiconductor layer 230. As the metal oxide, it is preferable to use one having a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3.0 eV or more.

[0191] It is preferable to use indium oxide as the semiconductor layer 230. Alternatively, a metal oxide other than indium oxide may be used as the semiconductor layer 230. In this case, for example, gallium oxide or zinc oxide may be used as the semiconductor layer 230. When a metal oxide other than indium oxide is used as the semiconductor layer 230, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, it is preferable that the element M is one or more elements selected from aluminum, gallium, yttrium, and tin.

[0192] As the metal oxide used for the semiconductor layer 230, IGZO can be used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) can be used. Alternatively, an oxide containing indium, gallium, tin, and zinc can be used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) can be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) can be used.

[0193] Furthermore, the metal oxide containing indium and the element M preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider an oxide layer with a two-layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of the element M to the main component metal element in the metal oxide used for the first layer is preferably greater than the atomic ratio of the element M to the main component metal element in the metal oxide used for the second layer. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the first layer is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the second layer. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

[0194] In addition, the atomic ratio of In to the element M in the metal oxide used for the second layer is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the first layer. With this structure, an OS transistor having this structure can have large on-state current and high frequency characteristics.

[0195] Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:3:4 (atomic ratio) or a composition thereabout, or In:M:Zn = 1:1:0.5 (atomic ratio) or a composition thereabout. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:2 (atomic ratio) or a composition thereabout, or In:M:Zn = 4:2:3 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of 0.70 to 1.3 times the desired atomic ratio. For example, when the desired atomic ratio is 4, the atomic ratio of the neighboring composition is 2.8 or more and 5.2 or less.

[0196] In order to reduce the off-state current of a transistor, it is preferable to use, for example, IGZO as the metal oxide used in the semiconductor layer 230. When the semiconductor layer 230 contains IGZO, the amount of current flowing between the source and drain of the transistor when the gate-source voltage is 0 V is 1×10 per 1 μm of channel width at room temperature. −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ It will be A or below.

[0197] As described above, in a transistor in which the semiconductor layer 230 contains IGZO, when the gate-source voltage is lower than the threshold voltage, the amount of current flowing per 1 μm of channel width is 1×10 −１６ A or less, preferably 1 x 10 −１８ A or less, more preferably 1×10 −２０ In some cases, the amount of current flowing per 1 μm of channel width may be 1×10 −２０ A or less, more preferably 1×10 −２２ A or less, more preferably 1×10 −２４ In this specification, the operation of the transistor in this region may be referred to as an off state. In addition, the current flowing through the transistor at this time may be referred to as an off-state current.

[0198] The structure of a metal oxide can be divided into a single crystal structure and other structures (non-single crystal structures). Examples of non-single crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures can be used. However, use of a crystalline metal oxide, such as a CAAC structure or an nc structure, is preferable because a highly reliable semiconductor device can be obtained.

[0199] The metal oxide is preferably indium oxide. In particular, crystalline indium oxide is preferably used. Details of crystalline indium oxide will be described later. The metal oxide may be In—Ga—Zn oxide (indium-gallium-zinc oxide), Ga—Zn oxide, or gallium oxide.

[0200] The metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4, 1:3:2, 1:1:0.5, 1:1:1, 4:2:3, or 3:1:2. The metal oxide may have an atomic ratio of In:Zn=4:1.

[0201] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, a film with high crystallinity or high film density can be formed. Furthermore, when the metal oxide is formed by ALD, atoms can be deposited layer by layer, which has the advantages of enabling film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. After the metal oxide is formed, it is preferable to perform an impurity removal treatment to remove impurities (typically, impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of impurity removal treatments include plasma treatment, microwave treatment, and heat treatment.

[0202] A semiconductor material other than a metal oxide may be used as the semiconductor layer 230. Examples of such other semiconductor materials include semiconductors made of simple elements and compound semiconductors.

[0203] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0204] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. The boron nitride that can be used for the semiconductor layer 230 preferably includes an amorphous structure. The boron arsenide that can be used for the semiconductor layer 230 preferably includes crystals with a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0205] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 116, insulating layer 140, insulating layer 180, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 285, etc.) included in the semiconductor device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film may also be used for an insulating layer included in a semiconductor device.

[0206] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for an insulating layer functioning as an interlayer insulating layer can reduce parasitic capacitance between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength. Materials with a low dielectric constant can also be used for insulating layers functioning as base insulating layers.

[0207] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0208] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0209] Furthermore, a transistor using a metal oxide as a semiconductor layer can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0210] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Other examples include nitrides such as aluminum nitride and silicon nitride. Other examples include metal nitrides such as silicon nitride oxide. Other examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0211] Furthermore, an insulating layer, such as a gate insulating layer, that is in contact with a metal oxide layer or that is provided near the metal oxide layer is preferably an insulating layer having a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with a metal oxide layer or is located near the metal oxide layer, oxygen vacancies in the metal oxide layer can be reduced. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies. Examples of insulating layers that easily form a region containing excess oxygen include a silicon oxide film, a silicon oxynitride film, and a silicon oxide film having vacancies.

[0212] An insulating layer in contact with a metal oxide layer or an insulating layer provided near the metal oxide layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, it can suppress diffusion of hydrogen into the metal oxide layer. The barrier insulating layer against hydrogen can also be said to be an insulating layer having a function of suppressing diffusion of hydrogen.

[0213] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium (hafnium zirconium oxide).

[0214] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0215] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0216] The insulating layer may have a crystalline region and / or a grain boundary in a part thereof.

[0217] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0218] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium, silicon nitride, and silicon nitride oxide.

[0219] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0220] 1A to 10B show an example in which the insulating layer 140 has a single-layer structure. Note that the insulating layer 140 can have a stacked structure of two or more layers. For example, the insulating layer 140 can have a two-layer structure of a first insulating layer and a second insulating layer over the first insulating layer. In this case, for example, it is preferable to use a barrier insulating layer against hydrogen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. Specifically, it is preferable to use a silicon nitride film as the first insulating layer and a hafnium oxide film, a hafnium silicate film, or an aluminum oxide film as the second insulating layer.

[0221] It is preferable to use a barrier insulating layer against hydrogen as the insulating layer 250. When the insulating layer 250 provided on the semiconductor layer 230 has a barrier property against hydrogen, it is possible to suppress diffusion of hydrogen contained in the conductive layer 260 into the semiconductor layer 230. For example, a silicon nitride film is suitable as the insulating layer 250 because it has a high barrier property against hydrogen.

[0222] Furthermore, since the insulating layer 250 is in contact with the semiconductor layer 230, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen. This allows hydrogen contained in the semiconductor layer 230 to be more effectively captured or fixed. Therefore, the hydrogen concentration in the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor) can be reduced. Therefore, the V Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0223] In addition, an insulating layer having a region containing excess oxygen is preferably used as the insulating layer 250. This allows oxygen to be supplied from the insulating layer 250 to the semiconductor layer 230, thereby reducing oxygen vacancies in the semiconductor layer 230. A silicon oxide film, a silicon oxynitride film, or the like is suitable as the insulating layer 250 because it has a structure that is stable against heat.

[0224] 9A to 10B show an example in which the insulating layer 250 has a single-layer structure. Note that the insulating layer 250 can have a stacked structure of two or more layers. In this case, the insulating layer 250 is preferably formed of two or more types of films. By forming the insulating layer 250 using two or more types of films, the insulating layer 250 can be given multiple functions. Examples of the functions of the insulating layer 250 include a function of extracting hydrogen from the semiconductor layer 230 and a function of suppressing diffusion of hydrogen into the semiconductor layer 230.

[0225] For example, the insulating layer 250 can have a two-layer structure of a first insulating layer and a second insulating layer over the first insulating layer. In this case, the first insulating layer is in contact with the semiconductor layer 230. For example, it is preferable to use an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. With such a structure, the hydrogen concentration in the semiconductor layer 230 can be reduced and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0226] Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and a barrier insulating layer against hydrogen as the second insulating layer. Alternatively, for example, it is preferable to use an insulating layer having a region containing excess oxygen as the first insulating layer and an insulating layer having a function of capturing or fixing hydrogen as the second insulating layer. With such a structure, the amount of oxygen vacancies and the hydrogen concentration in the semiconductor layer 230 can be reduced, and diffusion of hydrogen into the semiconductor layer 230 can be suppressed. Therefore, a highly reliable transistor can be realized.

[0227] Furthermore, for example, the insulating layer 250 can have a third insulating layer between the semiconductor layer 230 and the first insulating layer. In other words, the insulating layer 250 can have a three-layer structure including a third insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer.

[0228] For example, it is preferable to use an insulating layer having a region containing excess oxygen or an insulating layer containing a material with a low dielectric constant as the third insulating layer, an insulating layer having a function of capturing or fixing hydrogen as the first insulating layer, and an insulating layer having barrier properties against hydrogen and oxygen as the second insulating layer. The third insulating layer is preferably a silicon oxide film or a silicon oxynitride film. By using an oxide film for the third insulating layer in contact with the semiconductor layer 230, oxygen can be supplied to the semiconductor layer 230. Furthermore, providing the second insulating layer can suppress diffusion of oxygen contained in the third insulating layer into the conductive layer 260, thereby suppressing oxidation of the conductive layer 260. Furthermore, a decrease in the amount of oxygen supplied from the third insulating layer to the semiconductor layer 230 can be suppressed.

[0229] Furthermore, for example, the insulating layer 250 can have a fourth insulating layer between the semiconductor layer 230 and the third insulating layer. In other words, the insulating layer 250 can have a four-layer structure including a fourth insulating layer, a third insulating layer on the fourth insulating layer, a first insulating layer on the third insulating layer, and a second insulating layer on the first insulating layer. The fourth insulating layer is a layer that contacts the semiconductor layer 230 among the two or more layers that the insulating layer 250 has.

[0230] It is preferable to use an insulating layer having a barrier property against oxygen as the fourth insulating layer. Note that the same configuration as that of the layers used in the above-described three-layer structure can be applied to the first to third insulating layers. The fourth insulating layer is a layer in contact with the semiconductor layer 230. When the fourth insulating layer has a barrier property against oxygen, oxygen can be prevented from being released from the semiconductor layer 230.

[0231] For example, an aluminum oxide film may be used as the fourth insulating layer. The aluminum oxide film has a function of capturing or fixing hydrogen or a barrier property against hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 230. Specifically, the insulating layer 250 preferably has a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 230 side.

[0232] A material that can have ferroelectricity may be used for the insulating layer 250. In this case, the insulating layer 250 may be made of a material that can be used for the ferroelectric layer 130.

[0233] The insulating layer 250 is preferably a thin film. For example, by setting the thickness of the insulating layer 250 to 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, the subthreshold swing value (also referred to as S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage kept constant in the subthreshold region.

[0234] The thickness of each layer constituting the insulating layer 250 is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm. It is preferable that each layer constituting the insulating layer 250 has a region with the above-mentioned thickness in at least a portion thereof.

[0235] [Conductive Layer] For each of the conductive layers (conductive layer 110, conductive layer 115, conductive layer 120, conductive layer 240a, conductive layer 240b, conductive layer 244, conductive layer 245, conductive layer 260, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, lanthanum, etc., or an alloy containing any of the above metal elements as a component, or an alloy combining any of the above metal elements, etc. As the alloy containing any of the above metal elements as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. Furthermore, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0236] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain low electrical resistance even when absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, ITO, indium tin oxide containing titanium oxide, ITSO, IZO (registered trademark), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0237] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0238] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0239] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0240] The conductive layer 120, the conductive layer 240a, and the conductive layer 240b are each conductive layers in contact with the semiconductor layer 230, and therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion, for each of them. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 120, the conductive layer 240a, and the conductive layer 240b.

[0241] By using a conductive material containing oxygen for the conductive layer 120, the conductive layer 120 can maintain its conductivity even if it absorbs oxygen. Similarly, by using a conductive material containing oxygen for the conductive layer 240a and the conductive layer 240b, the conductive layer 240a and the conductive layer 240b can maintain their conductivity even if they absorb oxygen. Furthermore, even when an insulating layer containing oxygen, such as hafnium oxide, is used as the insulating layer 140, the conductive layer 120 is preferably able to maintain its conductivity. For example, ITO, ITSO, In—Zn oxide, or the like is preferably used for each of the conductive layer 120, the conductive layer 240a, and the conductive layer 240b.

[0242] When the conductive layer 120, the conductive layer 240a, and the conductive layer 240b each have a stacked structure, by using a conductive material containing oxygen for the layer in the stacked structure that has the largest contact area with the semiconductor layer 230, the contact resistance between the conductive layer 120 and the semiconductor layer 230, between the conductive layer 240a and the semiconductor layer 230, and between the conductive layer 240b and the semiconductor layer 230 can be reduced.

[0243] 9A and 10B show an example in which the conductive layer 240a has a two-layer structure including a conductive layer 240a_1 and a conductive layer 240a_2 over the conductive layer 240a_1. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 240a_2 and a material having higher conductivity than the conductive layer 240a_2 for the conductive layer 240a_1. Specifically, it is preferable to use an oxide conductor (e.g., ITO, ITSO, or In—Zn oxide) for the conductive layer 240a_2 and tungsten for the conductive layer 240a_1. Furthermore, ruthenium, titanium nitride, tantalum nitride, or the like may be used for the conductive layer 240a_1. By using an oxide conductor for the conductive layer 240a_2 that is mainly in contact with the semiconductor layer 230, the contact resistance with the semiconductor layer 230 can be reduced. Furthermore, when a material having higher conductivity than an oxide conductor is used for the layer forming the conductive layer 240a, the conductivity of the conductive layer 240a can be increased.

[0244] Note that a conductive material containing oxygen can be used for the conductive layer 240a_1, and a material having higher conductivity than that of the conductive layer 240a_1 can be used for the conductive layer 240a_2. In this case, an oxide conductor is used for the layer of the conductive layer 240a that is closest to the channel formation region of the semiconductor layer 230. Therefore, the current path between the source and the drain can be shortened, and the on-state current of the transistor 200 can be increased.

[0245] 9A shows an example in which the conductive layer 240b has a two-layer structure including a conductive layer 240b_1 and a conductive layer 240b_2 over the conductive layer 240b_1. The conductive layer 240b_1 can be made of the same material as that used for the conductive layer 240a_1. The conductive layer 240b_2 can be made of the same material as that used for the conductive layer 240a_2.

[0246] The conductive layer 260 has a region that functions as a gate electrode. The conductive layer 260 is preferably made of a highly conductive material such as tungsten or ruthenium. Furthermore, the conductive layer 260 is preferably made of a conductive material that is resistant to oxidation, or a conductive material that has a function of suppressing oxygen diffusion. As described above, examples of the conductive material include a conductive material containing nitrogen (e.g., titanium nitride or tantalum nitride) and a conductive material containing oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0247] Furthermore, the conductive layer 260 preferably uses a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the aforementioned metal element and nitrogen (e.g., titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. Using such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0248] 9A to 10A has a two-layer structure including a conductive layer 260_1 and a conductive layer 260_2 over the conductive layer 260_1. In this case, for example, a titanium nitride film is preferably used as the conductive layer 260_1 and a tungsten film is preferably used as the conductive layer 260_2. Alternatively, a tantalum nitride film is preferably used as the conductive layer 260_1 and a copper film is preferably used as the conductive layer 260_2. Such a structure can increase the conductivity of the conductive layer 260.

[0249] The conductive layer 260 may also have a stacked structure of three or more layers, such as a tantalum nitride film, a titanium nitride film on the tantalum nitride film, and a tungsten film on the titanium nitride film.

[0250] The conductive layer 244 and the conductive layer 245 can be formed using a material that can be used for the conductive layer 240a and the conductive layer 240b. For example, a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, can be used for the conductive layer 244 and the conductive layer 245. Alternatively, a low-resistance conductive material, such as aluminum or copper, can be used. By using a low-resistance conductive material, wiring resistance can be reduced.

[0251] 9A shows an example in which the conductive layer 244 and the conductive layer 245 have a single-layer structure. Note that the conductive layer 244 and the conductive layer 245 can have a stacked structure of two or more layers.

[0252] [Substrate] Substrates on which transistors are formed can include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride or a metal oxide. Examples of substrates include substrates having a conductor or semiconductor provided on an insulating substrate, substrates having a conductor or insulator provided on a semiconductor substrate, and substrates having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate provided with elements may be used, such as a capacitor element, a resistor element, a switch element, a light-emitting element, or a memory element.

[0253] In this specification and the like, a semiconductor substrate made of silicon is referred to as a silicon substrate.

[0254] The above is the description of the materials that can be used for the semiconductor device of this embodiment mode.

[0255] 13A to 20C . In the drawings illustrating an example of a manufacturing method of a semiconductor device according to one embodiment of the present invention, specifically, a method for manufacturing a capacitor 100, unless otherwise specified, each figure (A) is a plan view. Each figure (B) is a cross-sectional view taken along dashed line A1-A2 in each figure (A). Each figure (C) is a cross-sectional view taken along dashed line B1-B2 in each figure (A).

[0256] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum deposition method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0257] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC (Direct Current) sputtering, which uses a direct current (DC) power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to form insulating films, while DC sputtering is mainly used to form metal conductive films. Pulsed DC sputtering is mainly used to form films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0258] CVD methods can be further classified into plasma-enhanced CVD (PECVD) methods that utilize plasma, thermal CVD (TCVD) methods that utilize heat, and photo-CVD (photo-CVD) methods that utilize light. CVD methods can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0259] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can minimize plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0260] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0261] Note that some precursors used in the ALD method contain elements such as carbon or chlorine. Therefore, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. The amounts of these elements can be quantified using XPS or SIMS. Note that the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but employs one or both of the following conditions: a high substrate temperature during film formation and / or an impurity removal treatment. Therefore, the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without these conditions.

[0262] Unlike film formation methods in which particles emitted from a target or the like are deposited, the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece. Therefore, it is a film formation method that is less affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.

[0263] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0264] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0265] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0266] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0267] Furthermore, when processing a thin film that constitutes a semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0268] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0269] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0270] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0271] Hereinafter, an example of a method for manufacturing the semiconductor device shown in FIGS. 2A, 5A, and 5B will be described.

[0272] 13A, 13B, and 13C, an insulating layer 140 is formed on a substrate (not shown), and then a conductive layer 110 is formed on the insulating layer 140. The conductive layer 110 can be formed by forming a conductive film that will become the conductive layer 110 and then processing the conductive film. The conductive film that will become the conductive layer 110 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the conductive film that will become the conductive layer 110, for example, a tungsten film with a thickness of 20 nm can be formed by a sputtering method.

[0273] 13A, 13B, and 13C, an insulating layer 180 is formed on the conductive layer 110 and the insulating layer 140. The insulating layer 180 can be formed by sequentially forming an insulating layer 180a, an insulating layer 180b, and an insulating layer 180c. The insulating layers 180a, 180b, and 180c can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon nitride film having a thickness of 5 nm can be formed by the ALD method as the insulating layer 180a. For example, a silicon oxide film having a thickness of 370 nm can be formed by the sputtering method as the insulating layer 180b.

[0274] The insulating layer 180c may be formed by the same method as the insulating layer 180a, or by a different method. The thickness of the insulating layer 180c may be different from that of the insulating layer 180a. For example, if the insulating layer 180a is formed by ALD and the insulating layer 180c is formed by sputtering, the thickness of the insulating layer 180a can be thinner than the thickness of the insulating layer 180c. For example, the thickness of the insulating layer 180a can be 5 nm, and the thickness of the insulating layer 180c can be 60 nm.

[0275] Here, it is preferable to perform planarization treatment such as CMP treatment on the upper surface of the insulating layer 180. For example, it is preferable to perform planarization treatment on the upper surface of the insulating layer 180b. For example, after forming a silicon oxide film with a thickness of 370 nm as the insulating layer 180b, planarization treatment is performed on the upper surface of the insulating layer 180b, so that the thickness of the insulating layer 180b in the region overlapping with the conductive layer 110 can be set to 350 nm. Note that when planarization treatment is performed on the upper surface of the insulating layer 180b, the insulating layer 180c can be formed on a flat surface.

[0276] Next, as shown in FIGS. 13A, 13B, and 13C, the insulating layer 180 is processed to form an opening 190 that reaches the conductive layer 110. Here, it is preferable to process the insulating layer 180 using a highly anisotropic etching method. In particular, processing by dry etching is preferable because it is suitable for fine processing. Note that a recess may be formed in the conductive layer 110 at a position that overlaps with the opening 190. FIG. 13B shows an example in which a region 101 with curved corners is formed in the conductive layer 110. For example, by adjusting the etching conditions, the region 101 with curved corners can be formed in the conductive layer 110.

[0277] 13A, 13B, and 13C, a conductive film 115f is formed to cover the opening 190. The conductive film 115f is formed along the sidewall of the opening 190, the upper surface of the conductive layer 110, and the upper surface of the insulating layer 180c.

[0278] The conductive film 115f is preferably formed by a CVD method or an ALD method because it is formed inside the opening 190. This allows the conductive film 115f to be formed with good coverage. For example, a titanium nitride film with a thickness of 5 nm can be formed by a CVD method as the conductive film 115f.

[0279] 13A, 13B, and 13C, a photoresist 131p is applied to the conductive film 115f. The photoresist 131p may be formed from at least one of a resist film, a spin-on-carbon (SOC) film, and a spin-on-glass (SOG) film. The photoresist 131p may be formed from, for example, an SOC film, an SOG film on the SOC film, or a resist film on the SOG film.

[0280] 14A, 14B, and 14C, anisotropic etching is performed on the entire surface of the photoresist 131p. This removes a portion of the photoresist 131p. For example, it is preferable to remove the portion of the photoresist 131p by dry etching. As a result, the resist mask 131 is formed inside the opening 190.

[0281] The anisotropic etching of the photoresist 131p can be performed, for example, until the upper surface of the conductive film 115f is exposed. For example, the anisotropic etching of the photoresist 131p can be performed until a predetermined time has elapsed since the upper surface of the conductive film 115f is exposed. In this case, the height of the upper surface of the resist mask 131 from the reference plane can be made lower than the height of the upper surface 105 of the insulating layer 180 from the reference plane. Note that the upper surface 105 can specifically be the upper surface of the insulating layer 180c.

[0282] 15A, 15B, and 15C, the conductive film 115f is subjected to an etching process. As a result, a conductive layer 115 is formed inside the opening 190. The etching process can be performed using a dry etching method or a wet etching method. In particular, processing using a dry etching method is preferable because it is suitable for fine processing.

[0283] The etching process on the conductive film 115f can be performed, for example, until the upper surface 105 is exposed. In this case, the conductive layer 115 can be formed so that the height of the upper end surface 103 of the conductive layer 115 from the reference plane is lower than the height of the upper surface 105 from the reference plane.

[0284] Here, it is preferable to form the conductive layer 115 so that the upper end surface 103 has a tapered shape. Specifically, the conductive layer 115 can be formed so that the height from the reference plane of the end of the upper end surface 103 on the resist mask 131 side is lower than the height from the reference plane of the end of the upper end surface 103 on the insulating layer 180 side. By forming the conductive layer 115 so that the upper end surface 103 has a tapered shape, as described above, it is possible to suppress electric field concentration in the ferroelectric layer 130 formed in a later process near the upper end surface 103. This makes it possible to prevent dielectric breakdown of the ferroelectric layer 130 and to manufacture a highly reliable semiconductor device.

[0285] 15B and 15C show an example in which a curved portion is formed in the region 102 between the upper surface of the insulating layer 180 and the side surface of the opening 190. When the conductive film 115f is subjected to an etching process, a curved portion may be formed in the region 102 of the insulating layer 180c.

[0286] 16A, 16B, and 16C, the resist mask 131 is removed. The resist mask 131 can be removed using, for example, a chemical solution. Alternatively, the resist mask 131 may be removed using an etching method.

[0287] 17A, 17B, and 17C, the conductive layer 115 is subjected to oxidation treatment. As a result, an oxide region 115ox is formed in the conductive layer 115. In the example shown in FIGS. 17A to 17C, an insulating layer 133 containing oxygen is formed to have a region in contact with the exposed surface of the conductive layer 115. As a result, at least a portion of the conductive layer 115 is oxidized by the oxygen contained in the insulating layer 133, and the oxide region 115ox is formed. The oxide region 115ox is formed to include a region of the conductive layer 115 in contact with the insulating layer 133. Note that the insulating layer 133 is formed to fill, for example, the opening 190. The insulating layer 133 is also formed to have a region located on the upper surface 105.

[0288] An oxide insulating film, for example, a silicon oxide film, can be formed as the insulating layer 133. In particular, TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ ) is preferably used to form a silicon oxide film by CVD, since this allows semiconductor devices to be manufactured with high productivity.

[0289] The insulating layer 133 may be formed by the ALD method, for example, by forming an insulating film with a low relative dielectric constant, such as a silicon oxide film, by the ALD method. In this case, the insulating layer 133 can be formed inside the opening 190 along the side surface and upper surface of the conductive layer 115. When a silicon oxide film is formed as the insulating layer 133 by the ALD method, the thickness of the insulating layer 133 is preferably 1 nm to 30 nm, more preferably 2 nm to 20 nm, and even more preferably 3 nm to 10 nm.

[0290] When the above-described oxidation treatment is performed by forming the insulating layer 133, the insulating layer 133 is removed after the oxide region 115ox is formed, as shown in FIGS. 18A, 18B, and 18C. This exposes the surface of the conductive layer 115, specifically the surface of the oxide region 115ox. The upper surface 105 is also exposed. The insulating layer 133 can be removed by, for example, wet etching. Alternatively, the insulating layer 133 may be removed by dry etching.

[0291] When performing oxidation treatment on the conductive layer 115 using the method shown in FIGS. 17A to 18C , it is preferable to form the insulating layer 180c using a material with a high etching selectivity with respect to the insulating layer 133. This prevents at least a portion of the insulating layer 180c from being removed when the insulating layer 133 is removed. This prevents the insulating layer 180 from becoming thin. For example, when a silicon oxide film is formed as the insulating layer 133, a silicon nitride film can be formed as the insulating layer 180c. Note that by forming the insulating layer 180c on the insulating layer 180b, the insulating layer 180b can be formed using a material with a low etching selectivity with respect to the insulating layer 133. The insulating layer 180b can be formed using, for example, the same material as the insulating layer 133. For example, both the insulating layer 180b and the insulating layer 133 can be silicon oxide films. As described above, forming the insulating layer 180c on the insulating layer 180b broadens the range of materials that can be used for the insulating layer 180b.

[0292] The method of oxidation treatment for the conductive layer 115 is not limited to the method shown in FIGS. 17A to 18C. For example, heat treatment may be performed in an atmosphere containing oxygen. Alternatively, plasma treatment or microwave treatment may be performed in an atmosphere containing oxygen. Note that the atmosphere containing oxygen may be an oxygen gas (O ２ ) as well as ozone (O ３ ), nitrous oxide (N ２ Oxygen-containing atmospheres include atmospheres containing gases of compounds containing oxygen, such as HCl, HCl, and HCl.

[0293] 6A and 6B, an insulating layer 116 may be formed to cover the conductive layer 115 without performing oxidation treatment on the conductive layer 115. As the insulating layer 116, for example, a silicon nitride film, a titanium nitride film, or a hafnium oxynitride film can be formed.

[0294] Next, as shown in FIGS. 19A, 19B, and 19C, the ferroelectric layer 130 is formed so as to have a region in contact with the oxide region 115ox. Since the ferroelectric layer 130 is formed inside the opening 190, it is preferable to form it using a CVD method or an ALD method. This allows the ferroelectric layer 130 to be formed with good coverage. The ferroelectric layer 130 is formed so as to contain oxygen, and specifically, a metal oxide film or a metal oxynitride film is formed. As the ferroelectric layer 130, for example, a hafnium zirconium oxide film having a thickness of 10 nm can be formed using the ALD method.

[0295] By forming the oxide region 115ox in the conductive layer 115 and then forming the ferroelectric layer 130 so as to have a region in contact with the oxide region 115ox, it is possible to suppress absorption of oxygen contained in the ferroelectric layer 130 into the conductive layer 115, compared to when the ferroelectric layer 130 is formed without forming the oxide region 115ox. Therefore, it is possible to suppress desorption of oxygen from the ferroelectric layer 130 and a decrease in the reliability of the ferroelectric memory. As described above, in one embodiment of the present invention, a highly reliable semiconductor device can be manufactured.

[0296] 19A, 19B, and 19C, a conductive film 120f, which will become the conductive layer 120 in a later step, is formed on the ferroelectric layer 130. The conductive film 120f is formed to have a region located inside the opening 190. The conductive film 120f can be formed using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0297] 19A, 19B, and 19C show an example in which a conductive film 120f_1 and a conductive film 120f_2 over the conductive film 120f_1 are formed as the conductive film 120f. The conductive film 120f_1 is a film that will become the conductive layer 120_1 in a later step. The conductive film 120f_2 is a film that will become the conductive layer 120_2 in a later step. The conductive film 120f_1 can be formed to fill the opening 190.

[0298] 19A and 19B show the width D of the opening 190. By making the film thickness of the conductive film 120f_1 thicker than the film thickness of the conductive layer 115, the film thickness of the ferroelectric layer 130, and the width D, the conductive film 120f_1 can be formed to fill the opening 190.

[0299] When the conductive film 120f_1 is formed so as to fill the opening 190, it is preferable to form the conductive film 120f_1 using a conductive material having a larger thermal expansion coefficient than the conductive film 120f_2. This makes it easier for the conductive film 120f_1 to apply tensile stress to the ferroelectric layer 130 when the temperature is lowered after the heat treatment. This increases the amount of remanent polarization in the ferroelectric layer 130, thereby enabling the manufacture of a highly reliable semiconductor device.

[0300] The conductive film 120f_2 is preferably formed using a material with high conductivity, for example, a material with higher conductivity than the conductive film 120f_1, thereby enabling the manufacture of a semiconductor device that operates at high speed.

[0301] For example, a titanium nitride film with a thickness of 30 nm can be deposited by a CVD method as the conductive film 120f_1, and for example, a tungsten film with a thickness of 40 nm can be deposited by a CVD method as the conductive film 120f_2.

[0302] The top surface of the conductive film 120f may be subjected to planarization treatment such as CMP treatment. For example, the top surface of the conductive film 120f_2 may be subjected to planarization treatment. For example, a film is formed over the conductive film 120f_2, and planarization treatment is performed on the film over the conductive film 120f_2 until the top surface of the conductive film 120f_2 is exposed, whereby the top surface of the conductive film 120f_2 can be planarized.

[0303] 20A, 20B, and 20C, the conductive film 120f is processed to form the conductive layer 120. Specifically, the conductive film 120f_2 is processed to form the conductive layer 120_2, and the conductive film 120f_1 is processed to form the conductive layer 120_1. For example, a resist mask is formed by photolithography, and then the conductive films 120f_2 and 120f_1 are processed according to the patterns of the resist mask, thereby forming the conductive layers 120_2 and 120_1, respectively. This processing can be performed by, for example, etching, and is preferably performed by dry etching, which facilitates microfabrication.

[0304] 20A, 20B, and 20C show an example in which not only the conductive film 120f but also the ferroelectric layer 130 is processed. The ferroelectric layer 130 can be processed using the same resist mask as that used to process the conductive film 120f. Alternatively, after processing the conductive film 120f to form the conductive layer 120, the resist mask may be removed and the ferroelectric layer 130 may be processed using the conductive layer 120 as a hard mask. When the ferroelectric layer 130 is processed using the above method, the upper end of the ferroelectric layer 130 can be aligned with the lower end of the conductive layer 120, specifically, with the lower end of the conductive layer 120_1. By processing the ferroelectric layer 130, at least a portion of the upper surface of the insulating layer 180 can be exposed.

[0305] After the conductive layer 120 is formed, it is preferable to perform heat treatment. This makes it easier for tensile stress to be applied from the conductive layer 120_1 to the ferroelectric layer 130 when the temperature is lowered after the heat treatment. This increases the amount of remanent polarization in the ferroelectric layer 130, thereby enabling the manufacture of a highly reliable semiconductor device. The heat treatment temperature can be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. Typically, the heat treatment temperature can be 400°C ± 25°C (375°C or higher and 425°C or lower). The treatment time can be 10 hours or less, or 1 minute to 5 hours or lower, or 1 minute to 2 hours or lower. When an RTA (Rapid Thermal Anneal) device is used, the treatment time can be, for example, 1 second to 5 minutes or lower.

[0306] In this way, the capacitor 100 can be formed.

[0307] 11A and 11B, after the steps shown in FIGS. 13A to 20C are performed, an insulating layer 280, a conductive layer 240a, and a conductive layer 240b are formed, and a groove 290 is formed in the insulating layer 280. Subsequently, a semiconductor layer 230, an insulating layer 250, a conductive layer 260, an insulating layer 283, and an insulating layer 285 are formed. Subsequently, an opening 270a reaching the conductive layer 240a and an opening 270b reaching the conductive layer 240b are formed in the insulating layer 285, the insulating layer 283, the insulating layer 250, and the semiconductor layer 230, respectively. Subsequently, a conductive layer 244a is formed to fill the opening 270a, and a conductive layer 244b is formed to fill the opening 270b. Subsequently, a conductive layer 245 is formed on the insulating layer 285, the conductive layer 244a, and the conductive layer 244b. 20A to 20C show an example in which the conductive layer 120 is formed to extend in the X direction, but when forming the memory cell 150, the conductive layer 120 is formed to have a shape that does not extend in the X direction, for example.

[0308] <Configuration Example 3 of Semiconductor Device> Hereinafter, a configuration example of a semiconductor device having a plurality of memory cells 150 will be described.

[0309] 21A is a circuit diagram showing a configuration example of 2×2 memory cells 150. In FIG. 21A, configuration examples of the 2×2 memory cells 150 are shown, including memory cell 150[1,1], memory cell 150[1,2], memory cell 150[2,1], and memory cell 150[2,2].

[0310] 21A , memory cell 150[1,1], memory cell 150[1,2], memory cell 150[2,1], and memory cell 150[2,2] have the same configuration as memory cell 150 shown in FIG. 7A . Here, in the example shown in FIG. 21A , wiring BL[1] is connected to memory cell 150[1,1] and memory cell 150[2,1] as wiring BL, and wiring BL[2] is connected to memory cell 150[1,2] and memory cell 150[2,2] as wiring BL. Furthermore, wiring WL[1] is connected to memory cell 150[1,1] and memory cell 150[1,2] as wiring WL, and wiring WL[2] is connected to memory cell 150[2,1] and memory cell 150[2,2] as wiring WL.

[0311] 21B is a plan view showing a specific configuration example of the semiconductor device shown in FIG. 21A. FIG. 22 is a cross-sectional view taken along dashed dotted line D1-D2 in FIG. 21B. Note that in FIGS. 21B and 22, the conductive layers 240a and 240b are collectively referred to as the conductive layer 240. The conductive layers 240a_1 and 240b_1 are collectively referred to as the conductive layer 240_1. Furthermore, the conductive layers 240a_2 and 240b_2 are collectively referred to as the conductive layer 240_2.

[0312] As described above, the conductive layer 110 has a region that functions as a wiring PL. The conductive layer 260 has a region that functions as a wiring WL. The conductive layer 245 has a region that functions as a wiring BL. In FIGS. 21B and 22, the conductive layer 260 having a region that functions as a wiring WL[1] is shown as a conductive layer 260[1], and the conductive layer 260 having a region that functions as a wiring WL[2] is shown as a conductive layer 260[2]. In FIGS. 21B and 22, the conductive layer 245 having a region that functions as a wiring BL[1] is shown as a conductive layer 245[1], and the conductive layer 245 having a region that functions as a wiring BL[2] is shown as a conductive layer 245[2].

[0313] 21B and 22 show an example in which the conductive layer 245[1] and the conductive layer 245[2] extend in the X direction. Also, FIG. 21B and 22 show an example in which the conductive layer 110, the conductive layer 260[1], and the conductive layer 260[2] extend in the Y direction.

[0314] As shown in FIGS. 21B and 22 , a conductive layer 240 can be shared between two memory cells 150 adjacent in the X direction. For example, one conductive layer 240 can be shared between memory cell 150[1,1] and memory cell 150[1,2]. Also, one conductive layer 240 can be shared between memory cell 150[2,1] and memory cell 150[2,2]. Then, a conductive layer 245 extending in the X direction can connect multiple conductive layers 240 provided in the X direction to each other. For example, a conductive layer 245[1] can be shared between memory cell 150[1,1] and memory cell 150[1,2]. Also, a conductive layer 245[2] can be shared between memory cell 150[2,1] and memory cell 150[2,2].

[0315] The conductive layer 260 extending in the Y direction can be shared among multiple memory cells 150 arranged in the Y direction. For example, the conductive layer 260[1] can be shared between the memory cell 150[1,1] and the memory cell 150[2,1], and the conductive layer 260[2] can be shared between the memory cell 150[1,2] and the memory cell 150[2,2].

[0316] 21B and 22, the semiconductor layer 230 can be shared between a plurality of memory cells 150 adjacent to each other in the X direction. Furthermore, as shown in FIG. 21B, a plurality of semiconductor layers 230 can be provided in one groove 290.

[0317] A memory cell array can be configured by arranging the memory cells 150 in a three-dimensional matrix.

[0318] The semiconductor device shown in FIG. 23 has n memory layers 160 (n is an integer of 2 or more; in the example shown in FIG. 23, n is an integer of 3 or more). Specifically, a memory layer 160[2] is provided on a memory layer 160[1], and (n-2) memory layers are further provided on the memory layer 160[2]. Here, a memory layer 160[n] is provided on the topmost layer. The number of memory cells 150 included in one memory layer 160 is not particularly limited, and two or more memory cells 150 may be included. For example, the conductive layer 247 connects the memory cells 150 included in the n memory layer 160 to a sense amplifier (not shown) provided below the memory layer 160[1]. In this way, stacking multiple memory cells 150 on top of each other can increase the storage capacity per unit area.

[0319] For example, the conductive layer 247 may function as a plug or wiring for connecting a circuit element such as a switch, a transistor, a capacitor, an inductor, a resistor, or a diode, a wiring, an electrode, or a terminal to the memory cell 150 .

[0320] The conductive layer 247 is provided inside an opening 251 formed in the insulating layer 140, the insulating layer 180, the insulating layer 280a, the insulating layer 280b, the insulating layer 280c, the insulating layer 250, the insulating layer 283, the insulating layer 285, or the like. Note that the conductive layer 247 can be formed using a conductive material or the like that can be used for the conductive layer 240a and the conductive layer 240b.

[0321] 23 shows an example in which the upper end of the ferroelectric layer 130 coincides or substantially coincides with the lower end of the conductive layer 120. In this case, the insulating layer 140, the insulating layer 180, the insulating layer 280a, the insulating layer 280b, the insulating layer 280c, the insulating layer 250, the insulating layer 283, the insulating layer 285, etc. have regions that do not overlap with the ferroelectric layer 130. Therefore, the opening 251 can be formed in this region, and therefore there is no need to form the opening 251 in the ferroelectric layer 130. This makes it possible to easily form the opening 251 with a high aspect ratio.

[0322] 23, by stacking multiple memory cells 150, cells can be integrated and arranged without increasing the area occupied by the memory cell array. In other words, a 3D memory cell array can be configured. This allows for a larger storage capacity per unit area.

[0323] 24 is a cross-sectional view showing a configuration example of a semiconductor device, illustrating an example in which a transistor 300 is provided below a memory cell 150. The transistor 300 can be provided to have a region overlapping with the memory cell 150. The transistor 300 can be provided in a driver circuit that has a function of driving the memory cell 150. The transistor 300 can be a transistor included in a sense amplifier, for example.

[0324] For example, by providing a sense amplifier so as to overlap the memory cell 150, it is possible to shorten the bit line connecting the sense amplifier and the memory cell 150. This reduces the bit line capacitance, enabling high-speed operation of the semiconductor device.

[0325] 24 can correspond to the semiconductor device 900 described in Embodiment 3. Specifically, the transistor 300 corresponds to the transistor included in the sense amplifier 927 in the semiconductor device 900. The memory cell 150 corresponds to the memory cell 950.

[0326] The transistor 300 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate, an insulating layer 315 functioning as a gate insulating layer, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 may be either a p-channel or n-channel transistor. The substrate 311 preferably contains a silicon-based semiconductor, specifically, single-crystal silicon.

[0327] Here, in the transistor 300 shown in FIG. 24 , a semiconductor region 313 (a part of a substrate 311) where a channel is formed has a convex shape. A conductive layer 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulating layer 315 interposed therebetween. Note that the conductive layer 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. Note that an insulating layer that is in contact with the top of the convex portion and functions as a mask for forming the convex portion may be provided. Here, the case where the convex portion is formed by processing a part of the semiconductor substrate is shown, but a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0328] Note that the transistor 300 illustrated in FIG. 24 is just an example, and the structure is not limited thereto. An appropriate transistor can be used depending on the circuit configuration or driving method.

[0329] Between each structure, a wiring layer provided with an interlayer insulating film, wiring, plugs, etc. may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Here, for a conductive layer functioning as a plug or wiring, the same reference numeral may be used to refer to multiple structures. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0330] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer insulating film over the transistor 300. A conductive layer 328 is embedded in the insulating layer 320 and the insulating layer 322, and a conductive layer 330 is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as plugs or wirings.

[0331] The insulating layer 322 may also function as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 322 may be planarized by a planarization process using a CMP method or the like to improve the planarity.

[0332] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in Fig. 24, an insulating layer 350, an insulating layer 352, and an insulating layer 354 are stacked in this order. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 352, and the insulating layer 354. The conductive layer 356 functions as a plug or a wiring.

[0333] The insulating layers 352, 354, and the like which function as interlayer insulating films can be formed using the insulating layers that can be used in the above-described semiconductor device.

[0334] Conductive layers functioning as plugs or wirings, such as the conductive layer 328, the conductive layer 330, and the conductive layer 356, can be formed using a conductive material applicable to the conductive layer 240a and the conductive layer 240b. A high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity is preferably used, and tungsten is preferred. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

[0335] The conductive layer 240a and the conductive layer 240b of the transistor 200 are connected to the low-resistance region 314b functioning as a source region or a drain region of the transistor 300 through the conductive layer 643, the conductive layer 645, the conductive layer 646, the conductive layer 356, the conductive layer 330, and the conductive layer 328.

[0336] The conductive layer 643 is embedded in the insulating layer 285, the insulating layer 283, the insulating layer 250, the insulating layer 280c, the insulating layer 280b, the insulating layer 280a, and the insulating layer 180. The conductive layer 645 is embedded in the insulating layer 180. The conductive layer 645 can be manufactured using the same material and in the same process as the conductive layer 110. The conductive layer 646 is embedded in the insulating layer 649. The insulating layer 649 insulates the transistor 300 from the conductive layer 110.

[0337] <Regarding hysteresis characteristics of ferroelectrics> Ferroelectrics have hysteresis characteristics. FIG. 25 is a diagram showing an example of the hysteresis characteristics of a ferroelectric. The hysteresis characteristics can be measured using a ferroelectric capacitor. In FIG. 25, the horizontal axis represents the voltage (electric field) applied to the ferroelectric layer. This voltage is the potential difference between one electrode and the other electrode in the ferroelectric capacitor. Note that the electric field strength can be found by dividing this potential difference by the thickness of the ferroelectric layer.

[0338] In Fig. 25, the vertical axis represents the polarization of the ferroelectric. When the polarization is positive, it indicates that the positive charges in the ferroelectric layer are biased toward one electrode of the ferroelectric capacitor, and the negative charges are biased toward the other electrode of the ferroelectric capacitor. On the other hand, when the polarization is negative, it indicates that the negative charges in the ferroelectric layer are biased toward one electrode of the ferroelectric capacitor, and the positive charges are biased toward the other electrode of the ferroelectric capacitor.

[0339] Furthermore, the polarization shown on the vertical axis of FIG. 25 may be positive when negative charges are biased toward one electrode side of the ferroelectric capacitor and positive charges are biased toward the other electrode side of the ferroelectric capacitor, and may be negative when positive charges are biased toward one electrode side of the ferroelectric capacitor and negative charges are biased toward the other electrode side of the ferroelectric capacitor.

[0340] 25, the hysteresis characteristics of a ferroelectric material can be represented by a curve 401 and a curve 402. The voltages at the intersections of the curves 401 and 402 are called saturated polarization voltages +VSP (also called "+VSP") and -VSP (also called "-VSP"). It can be said that +VSP and -VSP have opposite polarities.

[0341] When a voltage equal to or less than -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 401. On the other hand, when a voltage equal to or more than +VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 402. Note that +VSP may be referred to as a "positive saturation polarization voltage" or a "first saturation polarization voltage." Furthermore, -VSP may be referred to as a "negative saturation polarization voltage" or a "second saturation polarization voltage." The absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage may be the same or different.

[0342] When the polarization of the ferroelectric layer changes according to curve 401, the voltage at which the polarization becomes 0 is called the coercive voltage +Vc. When the polarization of the ferroelectric layer changes according to curve 402, the voltage at which the polarization becomes 0 is called the coercive voltage -Vc. The values ​​of +Vc and -Vc are between +VSP and -VSP. Note that +Vc may be called the "positive coercive voltage" or "first coercive voltage," and -Vc may be called the "negative coercive voltage" or "second coercive voltage." The absolute values ​​of the first coercive voltage and the second coercive voltage may be the same or different.

[0343] Furthermore, the maximum value of polarization when no voltage is applied to the ferroelectric layer (when the voltage is 0 V) ​​is called "residual polarization +Pr" or "residual polarization Pr1," and the minimum value is called "residual polarization -Pr" or "residual polarization Pr2." Furthermore, the absolute value of the difference between remanent polarization +Pr and remanent polarization -Pr is called "residual polarization 2Pr." The larger the remanent polarization 2Pr, the greater the fluctuation range of the capacitance value of the ferroelectric capacitor due to polarization reversal. The larger the remanent polarization 2Pr, the more preferable it is.

[0344] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0345] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0346] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0347] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0348] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 26A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 26B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0349] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 26B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 26A (see Non-Patent Document 7). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 26A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 26A.

[0350] 26A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm−３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0351] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0352] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0353] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0354] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 26A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0355] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0356] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0357] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0358] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0359] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0360] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0361] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can cause a decrease in field-effect mobility. These impurities can also inhibit the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and the like are elements that can be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0362] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0363] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0364] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 26C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0365] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0366] Furthermore, as shown in FIG. 26C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside permeates the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the film and is released as water molecules.

[0367] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0368] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0369]

[0370] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0371] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0372] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0373] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0374] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having such a structure is IGZO.

[0375] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0376] Embodiment 3 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described.

[0377] Fig. 27 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 27 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 27 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0378] The memory cell 950 can be, for example, the memory cell 150 described in the first embodiment.

[0379] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0380] In the semiconductor device 900, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0381] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0382] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0383] The voltage generating circuit 928 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a negative voltage.

[0384] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0385] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0386] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0387] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ 27, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it may be set to a plurality of power domains. In this case, a power switch can be provided for each power domain.

[0388] The driver circuit 910 and memory array 920 of the semiconductor device 900 may be provided on the same plane. Alternatively, as shown in FIG. 28A, the driver circuit 910 and memory array 920 may be provided overlapping each other. By providing the driver circuit 910 and memory array 920 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 28B, the memory array 920 may be provided in multiple layers on the driver circuit 910.

[0389] Next, an example of a processing unit that can include the semiconductor device will be described.

[0390] 29 shows a block diagram of the arithmetic device 960. The arithmetic device 960 shown in FIG. 29 can be applied to, for example, a CPU. The arithmetic device 960 can also be applied to processors such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have a larger number (several tens to several hundreds) of processor cores capable of parallel processing than a CPU.

[0391] The arithmetic device 960 shown in FIG. 29 has an ALU 962 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 962c, an instruction decoder 963, an interrupt controller 964, a timing controller 965, a register 966, a register controller 967, a bus interface 968, a cache 969, and a cache interface 969i on a substrate 961. The substrate 961 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may also have a rewritable ROM and a ROM interface. The cache 969 and the cache interface 969i may also be provided on separate chips.

[0392] The cache 969 is connected to a main memory provided on a separate chip via a cache interface 969i. The cache interface 969i has a function of supplying part of the data held in the main memory to the cache 969. The cache interface 969i also has a function of outputting part of the data held in the cache 969 to the ALU 962, register 966, etc. via the bus interface 968.

[0393] As will be described later, a memory array 920 can be provided stacked on the arithmetic unit 960. The memory array 920 can be used as a cache. In this case, the cache interface 969i may have a function of supplying data held in the memory array 920 to the cache 969. In this case, it is preferable that a drive circuit 910 be provided as part of the cache interface 969i.

[0394] It is also possible to use only the memory array 920 as a cache without providing the cache 969 .

[0395] The arithmetic device 960 shown in FIG. 29 is merely an example of a simplified configuration, and actual arithmetic devices 960 have a wide variety of configurations depending on their applications. For example, it is preferable to use a configuration including the arithmetic device 960 shown in FIG. 29 as one core, and to include multiple such cores, each of which operates in parallel, in a so-called multi-core configuration. The greater the number of cores, the higher the computational performance. The greater the number of cores, for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more. Furthermore, when extremely high computational performance is required, such as for server applications, a multi-core configuration having 16 or more, preferably 32 or more, and even more preferably 64 or more cores is preferable. Furthermore, the number of bits that the arithmetic device 960 can handle in its internal computation circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0396] An instruction input to the arithmetic unit 960 via the bus interface 968 is input to the instruction decoder 963, decoded, and then input to the ALU controller 962c, the interrupt controller 964, the register controller 967, and the timing controller 965.

[0397] The ALU controller 962c, interrupt controller 964, register controller 967, and timing controller 965 perform various controls based on the decoded instructions. Specifically, the ALU controller 962c generates signals for controlling the operation of the ALU 962. Furthermore, the interrupt controller 964 determines and processes interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, etc. while the arithmetic unit 960 is executing a program. The register controller 967 generates an address for the register 966 and reads and writes data from and to the register 966 depending on the state of the arithmetic unit 960.

[0398] Furthermore, the timing controller 965 generates signals that control the timing of the operations of the ALU 962, the ALU controller 962c, the instruction decoder 963, the interrupt controller 964, and the register controller 967. For example, the timing controller 965 includes an internal clock generation unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0399] 29 , a register controller 967 selects a holding operation in a register 966 in accordance with an instruction from an ALU 962. That is, the register controller 967 selects whether data is to be held by a flip-flop or by a capacitor in the memory cell of the register 966. If holding data by a flip-flop is selected, a power supply potential is supplied to the memory cell in the register 966. If holding data in a capacitor is selected, data is rewritten to the capacitor, and the supply of power supply potential to the memory cell in the register 966 can be stopped.

[0400] The memory array 920 and the arithmetic unit 960 can be provided overlapping each other. Perspective views of a semiconductor device 970A are shown in Figures 30A and 30B. The semiconductor device 970A has a layer 930 on which memory arrays are provided above the arithmetic unit 960. The layer 930 is provided with memory arrays 920L1, 920L2, and 920L3. The arithmetic unit 960 and each memory array have overlapping regions. To make the configuration of the semiconductor device 970A easier to understand, the arithmetic unit 960 and the layer 930 are shown separately in Figure 30B.

[0401] By stacking the layer 930 having the memory array and the arithmetic unit 960, the connection distance between them can be shortened, thereby increasing the communication speed between them. In addition, the short connection distance reduces power consumption.

[0402] As a method for stacking the layer 930 having a memory array and the arithmetic device 960, a method (also referred to as monolithic stacking) in which the layer 930 having a memory array is stacked directly on the arithmetic device 960 may be used, or a method in which the arithmetic device 960 and the layer 930 are formed on different substrates, and the two substrates are bonded together and connected using a through-via or conductive film bonding technology (Cu-Cu bonding, etc.) may be used. The former method does not require consideration of misalignment during bonding, and therefore can not only reduce the chip size but also reduce manufacturing costs.

[0403] Here, the arithmetic unit 960 does not have a cache 969, and the memory arrays 920L1, 920L2, and 920L3 provided in the layer 930 can each be used as a cache. In this case, for example, the memory array 920L1 can be used as an L1 cache (also referred to as a level 1 cache), the memory array 920L2 can be used as an L2 cache (also referred to as a level 2 cache), and the memory array 920L3 can be used as an L3 cache (also referred to as a level 3 cache). Of the three memory arrays, the memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 920L1 has the smallest capacity and the highest access frequency.

[0404] When the cache 969 provided in the arithmetic unit 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or a main memory. The main memory has a larger capacity than the cache and is accessed less frequently.

[0405] 30B, a driving circuit 910L1, a driving circuit 910L2, and a driving circuit 910L3 are provided. The driving circuit 910L1 is connected to the memory array 920L1 via a connection electrode 940L1. Similarly, the driving circuit 910L2 is connected to the memory array 920L2 via a connection electrode 940L2, and the driving circuit 910L3 is connected to the memory array 920L3 via a connection electrode 940L3.

[0406] Although the number of memory arrays functioning as caches is three in this example, the number may be one or two, or four or more.

[0407] When the memory array 920L1 is used as a cache, the driver 910L1 may function as part of the cache interface 969i, or may be configured to be connected to the cache interface 969i. Similarly, the driver circuits 910L2 and 910L3 may also function as part of the cache interface 969i, or may be configured to be connected thereto.

[0408] Whether the memory array 920 is made to function as a cache or as a main memory is determined by a control circuit 912 included in each drive circuit 910. The control circuit 912 can cause some of the memory cells 950 included in the semiconductor device 900 to function as RAM based on a signal supplied from the arithmetic device 960.

[0409] The semiconductor device 900 can cause some of the memory cells 950 to function as a cache and the other memory cells to function as a main memory. That is, the semiconductor device 900 can function as both a cache and a main memory. The semiconductor device 900 according to one embodiment of the present invention can function as, for example, a universal memory.

[0410] Furthermore, a layer 930 having one memory array 920 may be provided over the arithmetic device 960. Figure 31A shows a perspective view of a semiconductor device 970B.

[0411] In the semiconductor device 970B, one memory array 920 can be divided into multiple areas, each of which can be used for a different function. Figure 31A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.

[0412] Furthermore, in the semiconductor device 970B, the capacity of each of the areas L1 to L3 can be changed depending on the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​the area L1. This configuration can improve the efficiency of calculation processing and increase the processing speed.

[0413] Also, multiple memory arrays may be stacked. Figure 31B shows a perspective view of a semiconductor device 970C.

[0414] The semiconductor device 970C includes a layer 930L1 having a memory array 920L1, a layer 930L2 having a memory array 920L2 on top of that, and a layer 930L3 having a memory array 920L3 on top of that. The memory array 920L1, which is physically closest to the arithmetic unit 960, can be used as a higher-level cache, and the memory array 920L3, which is farthest, can be used as a lower-level cache or main memory. This configuration allows the capacity of each memory array to be increased, thereby further improving processing power.

[0415] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0416] Embodiment 4 In this embodiment, an example of the applicability of a semiconductor device according to one embodiment of the present invention will be described.

[0417] In semiconductor devices such as computers, various memory devices are used depending on the application. Figure 32 shows a conceptual diagram illustrating the hierarchy of memory devices used in semiconductor devices. In Figure 32, the conceptual diagram illustrating the hierarchy of memory devices is shown as a triangle, with memory devices located higher in the triangle being required to have a faster operating speed, and memory devices located lower in the triangle being required to have a larger memory capacity and a higher recording density.

[0418] In FIG. 32 , from the top layer of the triangle, there are shown memories integrated as registers in the CPU, GPU, and NPU arithmetic processing units, cache memories (sometimes simply referred to as caches, and typically L1, L2, and L3 caches), main memories such as DRAMs, and storage memories such as 3D NANDs and hard disks (also called HDDs: hard disk drives).

[0419] The memory embedded as a register in a processing unit such as a CPU, GPU, or NPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a high operating speed is required rather than a large storage capacity. Registers also have the function of storing setting information for the processing unit.

[0420] A cache memory has a function of duplicating and storing a portion of data stored in a DRAM. By duplicating frequently used data and storing it in the cache memory, the speed of accessing the data can be increased. A cache memory is required to have a smaller storage capacity than a DRAM, but a faster operating speed than a DRAM. Data rewritten in the cache memory is duplicated and supplied to the DRAM. Note that although only the L3 cache is illustrated in FIG. 32 , the cache memory is not limited to this. For example, a memory device using an oxide semiconductor according to one embodiment of the present invention can be suitably used for a last level cache (LLC) or a final level cache (FLC), which are located at the lowest level of a cache.

[0421] The DRAM has a function of holding programs, data, etc. read from the 3D NAND.

[0422] 3D NAND has the function of storing data that requires long-term storage, various programs used in computing devices (e.g., artificial neural network models), etc. Therefore, 3D NAND requires large storage capacity and high recording density rather than fast operating speed.

[0423] Hard disks have large capacity and are non-volatile. Instead of hard disks, solid state drives (SSDs) and the like can be used.

[0424] A memory device (OS memory) using an oxide semiconductor according to one embodiment of the present invention can retain data for a long period of time. Therefore, the memory device can be suitably used for the region of Target 1 shown in FIG. 32 . Note that, as indicated by diagonal hatching in FIG. 32 , Target 1 also includes part of the cache (L1, L2, L3) and part of the 3D NAND. In other words, Target 1 includes a boundary region between the DRAM and the 3D NAND and a boundary region between the DRAM and the cache (L1, L2, L3). Furthermore, the memory device using an oxide semiconductor according to one embodiment of the present invention has high operating speed and can therefore achieve excellent write and read operations. Therefore, the memory device can be suitably used for the region of Target 2 shown in FIG. 32 .

[0425] For example, the DRAM illustrated in FIG. 32 can be suitably replaced with a memory device including an oxide semiconductor according to one embodiment of the present invention. Here, the DRAM requires a refresh operation and is a destructive readout memory device, and therefore consumes more power than other memory devices. Therefore, a configuration without a DRAM can reduce power consumption. This configuration can reduce power consumption to one-hundredth or one-thousandth or less of that of a configuration using a DRAM. Therefore, global warming can be mitigated by deploying information processing devices including supercomputers (also referred to as high performance computers (HPCs)), computers, servers, and the like that employ such a configuration worldwide.

[0426] As described above, the memory device including an oxide semiconductor according to one embodiment of the present invention can be applied to a wide range of memories, from memories integrated as registers in arithmetic processing units such as CPUs, GPUs, and NPUs to memories located in the boundary region between DRAMs and 3D NANDs.

[0427] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0428] Embodiment 5 In this embodiment, an application example of a semiconductor device according to one embodiment of the present invention will be described.

[0429] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0430] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0431] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0432] [Electronic Component] FIG. 33A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 33A has a semiconductor device 981 inside a mold 984. FIG. 33A omits some parts in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.

[0433] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0434] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0435] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0436] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0437] 33B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0438] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA (Field Programmable Gate Array).

[0439] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0440] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0441] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0442] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0443] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0444] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0445] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 33B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0446] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0447] [Mainframe] Next, Fig. 34A shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 34A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0448] The computer 5620 can have the configuration shown in the perspective view in Fig. 34B, for example. In Fig. 34B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0449] PC card 5621 shown in Figure 34C is an example of a processing board equipped with a CPU, GPU, storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 34C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referred to.

[0450] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0451] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0452] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0453] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0454] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0455] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for learning and inference in artificial intelligence, for example.

[0456] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0457] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0458] Fig. 34D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 34D illustrates a planet 6804 in space.

[0459] 34D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0460] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0461] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0462] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0463] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0464] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0465] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0466] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0467] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires the construction of a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for data retention, or ensuring cooling equipment required for data retention.

[0468] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0469] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0470] Fig. 34E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 34E has multiple servers 7001sb as hosts 7001. It also has multiple storage devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.

[0471] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0472] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0473] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0474] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0475] Note that power consumption can be reduced by applying the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0476] This embodiment mode can be combined with other embodiment modes and examples as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0477] In this example, Sample A and Sample B including the capacitor 100, which is a ferroelectric capacitor, were fabricated, and the results of cross-sectional observation will be described. Also, the results of a rewrite endurance test for Sample A and Sample B, and the evaluation results of the I-V characteristics will be described.

[0478] 13A to 20C of the first embodiment. First, as shown in Fig. 13A to 13C, a tungsten film having a thickness of 20 nm was formed as the conductive layer 110 on a silicon substrate (not shown) by sputtering. The substrate temperature was set to 130°C.

[0479] Subsequently, a silicon nitride film having a thickness of 5 nm was formed as the insulating layer 180a by the ALD method at a substrate temperature of 400°C.

[0480] Next, a silicon oxide film with a thickness of 370 nm was formed as the insulating layer 180b by sputtering. The substrate temperature was set to 170°C. Oxygen gas and argon gas were used as the film formation gas, and the oxygen flow rate ratio in the film formation gas was set to 50%. Next, the insulating layer 180b was planarized by CMP, and the film thickness of the insulating layer 180b was set to 350 nm.

[0481] Thereafter, a silicon nitride film having a thickness of 60 nm was formed as the insulating layer 180c by sputtering at a substrate temperature of 200° C. Nitrogen gas and argon gas were used as the film formation gas, and the nitrogen flow rate ratio in the film formation gas was 74%.

[0482] Next, an SOC film, an SOG film, and a resist film were formed in this order by coating, after which a resist pattern was formed by photolithography, and the SOG film and the SOC film were processed using the resist pattern.

[0483] Next, based on the resist pattern, dry etching was performed on the insulating layer 180c, the insulating layer 180b, and the insulating layer 180a. As a result, openings 190 with a design width of 60 nm were formed in the insulating layer 180c, the insulating layer 180b, and the insulating layer 180a. Thereafter, the SOC film, the SOG film, and the resist film were removed.

[0484] Subsequently, a titanium nitride film having a thickness of 5 nm was formed as the conductive film 115f by the CVD method. ４ Gas 50 sccm, and NH ３ The deposition gas was 2700 sccm, the substrate temperature was 400° C., and the deposition gas pressure was 667 Pa. Then, a resist film having a thickness of 300 nm was applied as a photoresist 131p.

[0485] Next, as shown in FIGS. 14A to 14C, anisotropic etching was performed on the entire surface of the photoresist 131p using a dry etching process. This formed a resist mask 131. The dry etching process was performed using 200 sccm of oxygen gas as the etching gas. The substrate temperature was 40° C., the etching gas pressure was 3.00 Pa, and the bias power was 150 W. The dry etching process was performed until the top surface of the conductive film 115f was exposed, and was continued for another 5 seconds after exposure. In other words, over-etching was performed for 5 seconds, with the conductive film 115f as the end point.

[0486] 15A to 15C, the conductive film 115f was subjected to dry etching using the resist mask 131. Thus, the conductive layer 115 was formed. The dry etching was performed using a chlorine gas of 45 sccm, CF ４ The etching was performed using 55 sccm of hydrogen gas and 55 sccm of oxygen gas as etching gases. The substrate temperature was 40° C., the etching gas pressure was 0.67 Pa, and the bias power was 50 W. The processing time was 15 seconds.

[0487] Next, as shown in FIGS. 16A to 16C, an ashing process was performed to remove the resist mask 131. Next, as shown in FIGS. 17A to 17C, a silicon oxide film with a thickness of 300 nm was formed as the insulating layer 133 by CVD. The silicon oxide film was formed using TEOS as the deposition gas. Specifically, a gas with a flow ratio of ozone gas to TEOS of 8:1 was used as the deposition gas. The substrate temperature was set to 450° C. Thereafter, as shown in FIGS. 18A to 18C, a wet etching process was performed to remove the insulating layer 133.

[0488] 19A to 19C, a hafnium zirconium oxide film having a thickness of 10 nm was formed by ALD as the ferroelectric layer 130. The substrate temperature was set to 300°C.

[0489] Subsequently, a titanium nitride film having a thickness of 30 nm was formed as the conductive film 120f_1 by the CVD method. ４ Gas 50 sccm, and NH ３ The deposition gas was 2700 sccm, the substrate temperature was 400° C., and the deposition gas pressure was 667 Pa.

[0490] Subsequently, a tungsten film having a thickness of 50 nm was formed as the conductive film 120f_2 by the CVD method. ６ The deposition gases used were 250 sccm of nitrogen gas, 2200 sccm of hydrogen gas, 2000 sccm of argon gas, and 200 sccm of nitrogen gas. The substrate temperature was 400° C., and the deposition gas pressure was 10666 Pa.

[0491] Next, a titanium nitride film with a thickness of 50 nm was formed on the conductive film 120f_2 by a CVD method. After that, the titanium nitride film on the conductive film 120f_2 and the conductive film 120f_2 were subjected to planarization treatment by a CMP method. As a result, the titanium nitride film on the conductive film 120f_2 was removed, and the thickness of the conductive film 120f_2 was reduced to 40 nm.

[0492] Next, an SOC film, an SOG film, and a resist film were formed in this order by coating, after which a resist pattern was formed by photolithography, and the SOG film and the SOC film were processed using the resist pattern.

[0493] Next, based on the resist pattern, dry etching was performed on the conductive film 120f_2, the conductive film 120f_1, and the ferroelectric layer 130. As a result, the conductive layer 120_2 and the conductive layer 120_1 were formed as shown in FIGS. 20A to 20C. As a result, the conductive layer 120 including the conductive layer 120_1 and the conductive layer 120_2 on the conductive layer 120_1 was formed.

[0494] The dry etching process for the conductive film 120f_2 is performed using BCl ３ The dry etching process was performed using 200 sccm of oxygen gas as the etching gas. The processing time was 33 seconds. The etching gas pressure was 0.67 Pa, and the bias power was 50 W. The dry etching process for the conductive film 120f_1 was performed using 200 sccm of oxygen gas as the etching gas. The processing time was 60 seconds. The etching gas pressure was 0.67 Pa, and the bias power was 50 W. The dry etching process for the ferroelectric layer 130 was performed using 200 sccm of oxygen gas as the etching gas. The processing time was 15 seconds. The etching gas pressure was 12.0 Pa, and the bias power was 0 W. Here, in the dry etching process for the conductive film 120f_2, the conductive film 120f_1, and the ferroelectric layer 130, the substrate temperature was 40° C.

[0495] After the conductive layers 120_2 and 120_1 were formed, the SOC film, the SOG film, and the resist film were removed. In this manner, the capacitor 100 was formed.

[0496] In this manner, sample A was prepared.

[0497] 13A to 16C were first performed, and then the processes shown in FIGS. 19A to 20C were performed. The conditions for each process were the same as those for Sample A. That is, Sample B is a sample obtained by omitting the processes for forming and removing the insulating layer 133 from the process for producing Sample A.

[0498] Fig. 35A is a cross-sectional scanning transmission electron microscope (STEM) image of sample A. In Fig. 35, silicon substrate 111 is shown as the silicon substrate. Fig. 35B is an image of region R shown in Fig. 35A at a higher total magnification. The cross-sectional STEM image was taken using a scanning transmission electron microscope HD-2700 manufactured by Hitachi High-Tech Corporation, with an acceleration voltage of 200 kV.

[0499] 35A and 35B , it was confirmed that a capacitor 100 having a conductive layer 115, a ferroelectric layer 130, and a conductive layer 120 was formed in sample A. It was also confirmed that the capacitor 100 was formed so that the height of the upper end surface 103 of the conductive layer 115 from the upper surface of the silicon substrate 111 was lower than the height of the upper surface 105 of the insulating layer 180c from the upper surface of the silicon substrate 111. It was also confirmed that a conductive layer 120_1 was formed so as to fill the opening 190.

[0500] 36A and 36B show input voltage waveforms in a rewrite endurance test. In each of the figures, the vertical axis represents voltage V, and the horizontal axis represents time t. Voltage V represents the potential difference between conductive layer 115 and conductive layer 120.

[0501] In the rewrite endurance test, first, one cycle of the trapezoidal wave shown in FIG. 36A was applied repeatedly until the specified number of cycles was reached. Next, the P-V characteristics were evaluated every specified number of cycles using the triangular wave double pulse method shown in FIG. 36B. This resulted in obtaining the remanent polarization 2Pr. The frequency of the applied trapezoidal wave was 100 kHz, and the voltage was ±2.5 V. In FIG. 36A, a positive trapezoidal wave is indicated by "P" and a negative trapezoidal wave is indicated by "N."

[0502] In the triangular wave double pulse technique shown in FIG. 36B , two positive triangular wave pulses are applied, followed by two negative triangular wave pulses, and the response charge is measured. The applied triangular wave has a frequency of 1 kHz and a voltage ranging from −2.5 V to +2.5 V. As shown in FIG. 36B , a negative triangular wave pulse (poling) is applied before the application of the positive triangular wave pulse. In this specification, the triangular wave double pulse technique is sometimes referred to as the Triangle-PUND (Positive-up-Negative-down) technique. Note that in FIG. 36B , the two positive triangular wave pulses are indicated by “P” and “U,” respectively. Also, in FIG. 36B , the two negative triangular wave pulses are indicated by “N” and “D,” respectively.

[0503] 37A is a diagram showing the results of the rewrite endurance test for each of Sample A and Sample B. In FIG. 37A, the vertical axis represents the remanent polarization 2Pr [μC / cm ２ ] and the horizontal axis indicates the number of cycles [times].

[0504] As shown in FIG. 37A, for sample A, the number of cycles was 1×10 １０ On the other hand, in the case of sample B, no dielectric breakdown occurred even after 1×10 cycles. ８ This suggests that the formation of the insulating layer 133 oxidized the conductive layer 115, and therefore the absorption of oxygen contained in the ferroelectric layer 130 into the conductive layer 115 was more suppressed than in sample B.

[0505] 37B is a diagram showing the evaluation results of the I-V characteristics of each of Sample A and Sample B. In Fig. 37B, the vertical axis represents current I [A], and the horizontal axis represents voltage V [V]. Here, current I represents the current that passes through ferroelectric layer 130 and flows between conductive layer 115 and conductive layer 120. Furthermore, voltage V represents the potential difference between conductive layer 115 and conductive layer 120, as described above.

[0506] 37B , in the case where the voltage V was 1.4 V or more and 5.5 V or less, the magnitude of the current I in the sample A was smaller than that in the sample B when the voltage V was the same. Therefore, it was confirmed that the sample A had a higher withstand voltage than the sample B. This suggests that, as described above, the sample A was able to suppress the absorption of oxygen contained in the ferroelectric layer 130 into the conductive layer 115 more effectively than the sample B.

[0507] In this example, samples C1, C2, C3, C4, and C5 including the capacitor 100, which is a ferroelectric capacitor, were fabricated, and the results of a rewrite endurance test will be described.

[0508] 13A to 20C of Embodiment 1. First, as shown in FIGS. 13A to 13C, a tungsten film having a thickness of 20 nm was formed as the conductive layer 110 on a silicon substrate (not shown) by sputtering. The substrate temperature was set to 130° C.

[0509] Subsequently, a silicon nitride film having a thickness of 5 nm was formed as the insulating layer 180a by the ALD method at a substrate temperature of 400°C.

[0510] Next, a silicon oxide film with a thickness of 370 nm was formed as the insulating layer 180b by sputtering. The substrate temperature was set to 170°C. Oxygen gas and argon gas were used as the film formation gas, and the oxygen flow rate ratio in the film formation gas was set to 50%. Next, the insulating layer 180b was planarized by CMP, and the film thickness of the insulating layer 180b was set to 350 nm.

[0511] Thereafter, a silicon nitride film having a thickness of 60 nm was formed as the insulating layer 180c by sputtering at a substrate temperature of 200° C. Nitrogen gas and argon gas were used as the film formation gas, and the nitrogen flow rate ratio in the film formation gas was 74%.

[0512] Next, an SOC film, an SOG film, and a resist film were formed in this order by coating, after which a resist pattern was formed by photolithography, and the SOG film and the SOC film were processed using the resist pattern.

[0513] Next, based on the resist pattern, dry etching was performed on the insulating layer 180c, the insulating layer 180b, and the insulating layer 180a. As a result, openings 190 with a design width of 60 nm were formed in the insulating layer 180c, the insulating layer 180b, and the insulating layer 180a. Thereafter, the SOC film, the SOG film, and the resist film were removed.

[0514] Subsequently, a titanium nitride film having a thickness of 5 nm was formed as the conductive film 115f by the CVD method. ４ Gas 50 sccm, and NH ３ The deposition gas was 2700 sccm, the substrate temperature was 400° C., and the deposition gas pressure was 667 Pa. Then, a resist film having a thickness of 300 nm was applied as a photoresist 131p.

[0515] Next, as shown in FIGS. 14A to 14C, anisotropic etching was performed on the entire surface of the photoresist 131p using a dry etching process. This formed a resist mask 131. The dry etching process was performed using 200 sccm of oxygen gas as the etching gas. The substrate temperature was 40° C., the etching gas pressure was 3.00 Pa, and the bias power was 0 W. The dry etching process was performed until the top surface of the conductive film 115f was exposed, and was continued for an additional 5 seconds after exposure. In other words, over-etching was performed for 5 seconds, with the conductive film 115f as the end point.

[0516] 15A to 15C, the conductive film 115f was subjected to dry etching using the resist mask 131. Thus, the conductive layer 115 was formed. The dry etching was performed using a chlorine gas of 45 sccm, CF ４ The etching was performed using 55 sccm of hydrogen gas and 55 sccm of oxygen gas as etching gases. The substrate temperature was 40° C., the etching gas pressure was 0.67 Pa, and the bias power was 50 W. The processing time was 15 seconds.

[0517] Next, as shown in FIGS. 16A to 16C, the resist mask 131 was removed. Next, as shown in FIGS. 17A to 17C, a silicon oxide film with a thickness of 300 nm was formed as an insulating layer 133 by CVD. The silicon oxide film was formed using TEOS as a deposition gas. Specifically, a gas in which the flow ratio of ozone gas to TEOS was 8:1 was used as the deposition gas. The substrate temperature was set to 350° C. Thereafter, as shown in FIGS. 18A to 18C, a wet etching process was performed to remove the insulating layer 133.

[0518] 19A to 19C, a hafnium zirconium oxide film having a thickness of 10 nm was formed as the ferroelectric layer 130 by the ALD method. ４ , and ZrCl ４ Water was used as the oxidizing agent, and the substrate temperature was set to 300°C.

[0519] Subsequently, a titanium nitride film having a thickness of 30 nm was formed as the conductive film 120f_1 by the CVD method. ４ Gas 50 sccm, and NH ３ The deposition gas was 2700 sccm, the substrate temperature was 400° C., and the deposition gas pressure was 667 Pa.

[0520] Subsequently, a tungsten film having a thickness of 50 nm was formed as the conductive film 120f_2 by the CVD method. ６ The deposition gases used were 250 sccm of nitrogen gas, 2200 sccm of hydrogen gas, 2000 sccm of argon gas, and 200 sccm of nitrogen gas. The substrate temperature was 400° C., and the deposition gas pressure was 10666 Pa.

[0521] Next, a titanium nitride film with a thickness of 50 nm was formed on the conductive film 120f_2 by a CVD method. After that, the titanium nitride film on the conductive film 120f_2 and the conductive film 120f_2 were subjected to planarization treatment by a CMP method. As a result, the titanium nitride film on the conductive film 120f_2 was removed, and the thickness of the conductive film 120f_2 was reduced to 40 nm.

[0522] Next, an SOC film, an SOG film, and a resist film were formed in this order by coating, after which a resist pattern was formed by photolithography, and the SOG film and the SOC film were processed using the resist pattern.

[0523] Next, based on the resist pattern, dry etching was performed on the conductive film 120f_2, the conductive film 120f_1, and the ferroelectric layer 130. As a result, the conductive layer 120_2 and the conductive layer 120_1 were formed as shown in FIGS. 20A to 20C. As a result, the conductive layer 120 including the conductive layer 120_1 and the conductive layer 120_2 on the conductive layer 120_1 was formed.

[0524] The dry etching process for the conductive film 120f_2 is performed using BCl ３ The dry etching process was performed using 200 sccm of oxygen gas as the etching gas. The processing time was 33 seconds. The etching gas pressure was 0.67 Pa, and the bias power was 50 W. The dry etching process for the conductive film 120f_1 was performed using 200 sccm of oxygen gas as the etching gas. The processing time was 60 seconds. The etching gas pressure was 0.67 Pa, and the bias power was 50 W. The dry etching process for the ferroelectric layer 130 was performed using 200 sccm of oxygen gas as the etching gas. The processing time was 15 seconds. The etching gas pressure was 12.0 Pa, and the bias power was 0 W. Here, in the dry etching process for the conductive film 120f_2, the conductive film 120f_1, and the ferroelectric layer 130, the substrate temperature was 40° C.

[0525] After the conductive layers 120_2 and 120_1 were formed, the SOC film, the SOG film, and the resist film were removed. In this manner, the capacitor 100 was formed.

[0526] Next, 1.5 x 10 −５ The heat treatment was carried out at 400° C. under a vacuum in which the inside pressure was reduced to about Pa. The heat treatment times were 2 minutes, 5 minutes, 10 minutes, 30 minutes, and 60 minutes for Sample C1, Sample C2, Sample C3, Sample C4, and Sample C5, respectively.

[0527] In this manner, samples C1 to C5 were fabricated.

[0528] 38 is a diagram showing the results of the rewrite endurance test for samples C1 to C5. In FIG. 38, the vertical axis represents the remanent polarization 2Pr [μC / cm ２ ] and the horizontal axis indicates the number of cycles [times].

[0529] As shown in FIG. 38, in any of the samples C1 to C5, the number of cycles was 1×10 ８ No dielectric breakdown occurred even after at least 1×10 cycles. ５ Within the first 100 cycles, the remanent polarization 2Pr was largest in samples C5, C4, C3, C2, and C1. Therefore, the longer the heat treatment time after forming the capacitor 100, the larger the remanent polarization 2Pr. In particular, the remanent polarization 2Pr increased significantly when the heat treatment time was set to 60 minutes. From the above, it was confirmed that the heat treatment time after forming the capacitor 100 is preferably set to longer than 30 minutes.

[0530] The above is thought to be because hydrogen originating from water used as an oxidizing agent is mixed into the ferroelectric layer 130 when the ferroelectric layer 130 is formed, and the hydrogen is desorbed by the heat treatment.

[0531] 100: Capacitor, 101: Region, 102: Region, 103: End surface, 105: Upper surface, 110: Conductive layer, 115: Conductive layer, 115f: Conductive film, 115ox: Oxide region, 116: Insulating layer, 120: Conductive layer, 120_1: Conductive layer, 120_2: Conductive layer, 120_3: Conductive layer, 120f: Conductive film, 120f_1: Conductive film, 120f_2: Conductive film, 130: Ferroelectric layer, 131: Resist mask, 131p: Photoresist, 133: Insulating layer, 140: Insulating layer, 150[1,1]: Memory cell, 150[1,2]: Memory cell, 150[2,1]: Memory cell, 150 [2,2]: memory cell, 150: memory cell, 160[1]: memory layer, 160[2]: memory layer, 160[n]: memory layer, 160: memory layer, 180: insulating layer, 180a: insulating layer, 180b: insulating layer, 180c: insulating layer, 190: opening, 200: transistor, 230: semiconductor layer, 240: conductive layer, 240_1: conductive layer, 240_2: conductive layer, 240a: conductive layer, 240a_1: conductive layer, 240a_2: conductive layer, 240b: conductive layer, 240b_1: conductive layer, 240b_2: conductive layer, 244: conductive layer, 244a: conductive layer, 244b: conductive layer, 245 [1]: Conductive layer, 245[2]: Conductive layer, 245: Conductive layer, 247: Conductive layer, 250: Insulating layer, 251: Opening, 260[1]: Conductive layer, 260[2]: Conductive layer, 260: Conductive layer, 260_1: Conductive layer, 260_2: Conductive layer, 270: Opening, 270a: Opening, 270b: Opening, 280: Insulating layer, 280a: Insulating layer, 280b: Insulating layer, 280c: Insulating layer, 283: Insulating layer, 285: Insulating layer, 290: Groove, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulating layer, 316: Conductive layer, 320: insulating layer, 322: insulating layer, 324: insulating layer, 326: insulating layer, 328: conductive layer, 330: conductive layer, 350: insulating layer, 352: insulating layer, 354: insulating layer, 356: conductive layer, 401: curve, 402: curve, 643: conductive layer, 645: conductive layer, 646: conductive layer, 649: insulating layer, 900: semiconductor device, 910: drive circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit,930: layer, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 960: arithmetic unit, 961: substrate, 962: ALU, 962c: ALU controller, 963: instruction decoder, 964: interrupt controller, 965: timing controller, 966: register, 967: register controller, 968: bus interface, 969: cache, 969i: cache interface, 970A: semiconductor device, 970B: semiconductor device, 970C: semiconductor device, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 9 91: interposer, 992: package substrate, 993: electrode, 994: semiconductor device, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network, 7010: storage system,

Claims

a substrate, a first insulating layer, a first conductive layer, a second conductive layer, and a ferroelectric layer; the first insulating layer, the first conductive layer, the second conductive layer, and the ferroelectric layer are provided on the substrate; the first insulating layer has an opening; the first conductive layer has a region along a side surface of the opening of the first insulating layer, an upper end surface of the first conductive layer is lower in height from the substrate than an upper surface of the first insulating layer; the ferroelectric layer has a region in contact with the first conductive layer in the opening, the second conductive layer has a region facing the first conductive layer with the ferroelectric layer interposed therebetween in the opening; the first conductive layer has an oxide region; the oxide region includes a region in contact with the ferroelectric layer, The ferroelectric layer contains oxygen. 　 In claim 1, The oxide region includes an oxide of an element contained in the first conductive layer. 　 In claim 1, A semiconductor device in which the angle of the top surface of the first conductive layer with respect to the top surface of the substrate is greater than 0°. 　 In claim 1, the second conductive layer includes a first layer and a second layer on the first layer; the first layer is provided to fill the opening, A semiconductor device in which the thermal expansion coefficient of the first layer is greater than the thermal expansion coefficient of the second layer. 　 In claim 4, the first layer comprises titanium nitride; The semiconductor device wherein the second layer comprises tungsten. 　 In any one of claims 1 to 5, a second insulating layer, a third insulating layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; the second insulating layer is located on the second conductive layer and on the first insulating layer; the third conductive layer and the fourth conductive layer are located on the second insulating layer; the second insulating layer has a groove portion that overlaps a region between the third conductive layer and the fourth conductive layer and has a region that reaches the second conductive layer; the semiconductor layer has a region in contact with the second conductive layer, a region in contact with the third conductive layer, a region in contact with the fourth conductive layer, and a region along a part of a side surface of the second insulating layer in the groove portion; the third insulating layer is provided on the semiconductor layer so as to have a region located inside the groove; The fifth conductive layer has a region inside the groove that faces the semiconductor layer with the third insulating layer sandwiched therebetween. 　 In claim 6, a fourth insulating layer and a sixth conductive layer; the fourth insulating layer is located on the third to fifth conductive layers; the sixth conductive layer is located on the fourth insulating layer; The sixth conductive layer is electrically connected to the third conductive layer and the fourth conductive layer. 　 In claim 7, the groove and the fifth conductive layer extend in a first direction; the sixth conductive layer extends in a second direction; The second direction is perpendicular to the first direction. In claim 6, The semiconductor device, wherein the semiconductor layer contains indium. 　 forming a first insulating layer on a substrate; forming an opening in the first insulating layer; forming a conductive film so as to cover the opening; A photoresist is applied onto the conductive film; anisotropically etching the photoresist to form a resist mask in the opening; forming a first conductive layer along a side surface of the opening of the first insulating layer by processing the conductive film; removing the resist mask; performing an oxidation treatment on the first conductive layer to form an oxide region in the first conductive layer; forming a ferroelectric layer containing oxygen so as to have a region in contact with the oxide region; forming a second conductive layer on the ferroelectric layer so as to have a region located in the opening; A method for manufacturing a semiconductor device, wherein the first conductive layer is formed so that a height of an upper surface of the first conductive layer from the substrate is lower than a height of an upper surface of the first insulating layer from the substrate. 　 In claim 10, In the oxidation treatment, a second insulating layer containing oxygen is formed so as to have a region in contact with the first conductive layer, and then the second insulating layer is removed. 　 In claim 10, forming a first layer filling the opening and a second layer on the first layer as the second conductive layer; A method for manufacturing a semiconductor device, wherein the first layer has a larger thermal expansion coefficient than the second layer. 　 In claim 12, The first layer is formed to include titanium nitride; The second layer is formed to contain tungsten.

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