Semiconductor device

Abstract

The present invention provides a semiconductor device that suppresses variations in calculation results. The semiconductor device includes a voltage generation circuit, a drive circuit, and an arithmetic cell. The voltage generation circuit has a plurality of first output terminals. The drive circuit has a first selector circuit, a transistor, and a switch. The first selector circuit has a plurality of first input terminals, a plurality of second input terminals, and a second output terminal. The voltage generation circuit generates a plurality of analog potentials by a resistance voltage division method, and gives each of the plurality of analog potentials to the plurality of first input terminals. Due to the fact that digital data is given to each of the plurality of second input terminals, the first selector circuit establishes an electrically conductive state between one of the plurality of first input terminals and the second output terminal in accordance with the digital data, and applies the analog potential of the selected first input terminal to the gate of the transistor. The first transistor generates a first current in an amount corresponding to one of the analog potentials applied to the gate and provides the first current to the arithmetic cell.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, power storage devices, imaging devices, memory devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof.

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that mimic the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brainmorphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network having "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that configures an artificial neural network using an SRAM (Static Random Access Memory).

[0005] As an example of a computing device that configures an artificial neural network, Patent Document 1 discloses a computing device including a multiplication cell that performs multiplication using a current flowing in the subthreshold region of a transistor. Patent Document 1 also discloses a method for adjusting weighting coefficients to correct variations in the computation results.

[0006] JP 2024-65044 A

[0007] M. Kang et al., "IEEE Journal of Solid-State Circuits", 2018, Volume 53, No. 2, pp. 642-655. J. Zhang et al., "IEEE Journal of Solid-State Circuits", 2017, Volume 52, No. 4, pp. 915-924. Takashi Koida, "High-Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / jp / rpd-envene / PV / ja / results / 2019 / oral / T13. pdf>

[0008] An example of an arithmetic device that configures an artificial neural network is an arithmetic device described in Patent Document 1, which performs a product-sum operation by adding analog currents corresponding to the products of weighting coefficients and input data. Because this arithmetic device uses analog currents for calculations, the circuit scale and circuit area can be smaller than those of arithmetic devices configured with digital circuits. Furthermore, by designing this arithmetic device to use a small amount of analog current for calculations, the power consumption of the arithmetic device can be reduced.

[0009] The above-mentioned arithmetic device may have a configuration in which a cell array in which arithmetic cells are arranged in a matrix, each cell multiplying a weighting factor by input data and outputting the result of the multiplication as an analog current, is configured to add up the analog currents output from the arithmetic cells arranged in a column, for example, so that the amount of the added analog current can be treated as the value resulting from a product-sum operation of the weighting factor and the input data, thereby enabling the operation to be performed faster than when a product-sum operation is performed using a digital circuit.

[0010] On the other hand, when using a computing device configured with a cell array in which computation cells that output analog currents are arranged in a matrix, variations may occur in the weighting coefficients or input data input to the computation cells, the current corresponding to the product of the weighting coefficients and input data output from the computation cells, and the computation results output from a circuit that computes an activation function. For example, when an analog current corresponding to a weighting coefficient or input data is generated using a current generating circuit or the like, if there is significant variation in the characteristics of the multiple transistors included in the current generating circuit, the amount of the analog current may deviate from the intended current amount. In this case, since the analog current is input to the computation cell, the result of the computation performed by the computation cell may differ from the expected value. This may result in significant variations in the computation results of the artificial neural network. This may also result in a low accuracy rate of inferences using the artificial neural network. Note that the current generating circuit here may also be referred to as a digital potential-to-analog current conversion circuit (IDAC) or the like in this specification.

[0011] An object of one embodiment of the present invention is to provide a semiconductor device in which variation in calculation results is suppressed, or to provide a semiconductor device in which the accuracy rate of inference using an artificial neural network is increased.

[0012] Another object of one embodiment of the present invention is to provide a semiconductor device with a reduced circuit area, or to provide a semiconductor device with high computing efficiency per area, or to provide a novel semiconductor device.

[0013] Note that the problem of one embodiment of the present invention is not limited to the above problem. The above problem does not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above problem and other problems, and does not necessarily solve all of the above problem and other problems.

[0014] As described above, the amount of analog current generated in a current generating circuit may fluctuate due to variations in the electrical characteristics of each transistor included in the current generating circuit. For this reason, it is desirable for a current generating circuit to have a configuration that relies as little as possible on the electrical characteristics of the transistors in generating the analog current.

[0015] Below, a configuration example of a semiconductor device according to one embodiment of the present invention, which can suppress variations in generated analog current, will be described.

[0016] (1) One embodiment of the present invention is a semiconductor device including a voltage generator circuit, a first driver circuit, and an arithmetic cell, wherein the voltage generator circuit has a plurality of first output terminals, the first driver circuit has a first selector circuit, a first transistor, and a switch, and the first selector circuit has a plurality of first input terminals, a second input terminal, and a second output terminal.

[0017] The first input terminal is electrically connected to the first output terminal, the second output terminal is electrically connected to the gate of the first transistor, one of the source and drain of the first transistor is connected to the first terminal of the switch, and the second terminal of the switch is electrically connected to the arithmetic cell.

[0018] The voltage generation circuit has a function of generating a plurality of analog potentials using a resistive voltage division method and outputting the analog potentials to a first output terminal. The first selector circuit has a function of providing first digital data to a second input terminal and establishing a conductive state between one of the plurality of first input terminals and the second output terminal in accordance with the first digital data. The first transistor has a function of generating a first current of an amount corresponding to the analog potential provided to the gate of the first transistor. The arithmetic cell has a function of maintaining a first potential corresponding to the first current.

[0019] (2) Alternatively, in one aspect of the present invention, in the above (1), the device may further include a second drive circuit and a drive cell. Preferably, the second drive circuit includes a second selector circuit and a second transistor. Preferably, the second selector circuit includes a plurality of third input terminals, a fourth input terminal, and a third output terminal.

[0020] In particular, it is preferable that the third input terminal is electrically connected to each of the first output terminals, and it is preferable that the third output terminal is electrically connected to the gate of the second transistor, and it is preferable that one of the source and drain of the second transistor is connected to each of the calculation cell and the driving cell.

[0021] Preferably, the second selector circuit has a function of providing second digital data to the fourth input terminal and bringing one of the plurality of fourth input terminals into a conductive state in accordance with the second digital data. Preferably, the second transistor has a function of generating a second current whose amount corresponds to an analog potential provided to a gate of the second transistor. Preferably, the drive cell has a function of maintaining a second potential corresponding to the second current.

[0022] (3) Alternatively, in one aspect of the present invention, in the above (2), the arithmetic cell may have a function of outputting, as a third current, a result of multiplying the ratio of the third digital data to the second digital data by the first digital data when the second digital data input to the fourth input terminal changes to the third digital data.

[0023] (4) Alternatively, according to one embodiment of the present invention, in the above-described (3), each of the first transistor and the second transistor may have a channel formation region including an oxide containing indium as an oxide semiconductor.

[0024] As described above, by using a current generating circuit configured as described above in (1) or (2) to generate an analog potential using a resistive voltage division method, and then applying the analog potential to the gate of a transistor to generate an analog current, it is possible to reduce the variation in the analog current compared to conventional current generating circuits.

[0025] According to one embodiment of the present invention, a semiconductor device in which variation in calculation results is suppressed or a semiconductor device in which the accuracy rate of inference using an artificial neural network is increased can be provided.

[0026] According to one embodiment of the present invention, a semiconductor device with a reduced circuit area can be provided. According to one embodiment of the present invention, a semiconductor device with high computing efficiency per area can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0027] Note that the effects of one embodiment of the present invention are not limited to the above-described effects. The above-described effects do not preclude the existence of other effects. Furthermore, the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the above-described effects and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.

[0028] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. FIG. 2 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. FIGS. 3A and 3B are circuit diagrams showing an example of the configuration of a circuit included in the semiconductor device. FIG. 4 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. FIGS. 5A, 5B, and 5C are circuit diagrams showing an example of the configuration of a circuit included in the semiconductor device. FIG. 6A is a circuit diagram showing an example of the configuration of a semiconductor device, and FIG. 6B is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. FIGS. 7A, 7B, and 7C are circuit diagrams showing an example of the configuration of a circuit included in the semiconductor device. FIG. 8 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. FIG. 9 is a block diagram showing an example of the configuration of a semiconductor device. FIGS. 10A, 10B, and 10C are circuit diagrams showing an example of the configuration of a circuit included in the semiconductor device. FIGS. 11A, 11B, 11C, and 11D are circuit diagrams showing an example of the configuration of a circuit included in the semiconductor device. FIG. 12 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. FIG. 13 is a circuit diagram showing an example of the configuration of a semiconductor device. FIG. 14 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. FIG. 15 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. FIG. 16 is a timing chart showing an example of the operation of the semiconductor device. FIGS. 17A and 17B are schematic plan views showing an example of the configuration of a circuit included in a semiconductor device. FIG. 18 is a schematic cross-sectional view showing an example of the configuration of a semiconductor device. FIG. 19 is a schematic cross-sectional view showing an example of the configuration of a transistor included in a semiconductor device. FIGS. 20A and 20B are schematic cross-sectional views showing an example of the configuration of a transistor included in a semiconductor device. FIGS. 21A, 21B, and 21C are schematic cross-sectional views showing an example of the configuration of a transistor included in a semiconductor device. FIG. 22 is a schematic perspective view showing an example of the configuration of a transistor included in a semiconductor device. FIGS. 23A and 23B are schematic cross-sectional views showing an example of the configuration of a capacitive element included in a semiconductor device. FIGS. 24A and 24B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 24C is a cross-sectional view illustrating an indium oxide film. FIGS. 25A, 25B, 25C, and 25D are diagrams illustrating examples of electronic components. FIG. 26 is a diagram illustrating an example of an information processing system. FIG. 27 is a diagram showing an example of space equipment.Fig. 28 is a diagram showing an example of a storage system applicable to a data center. Fig. 29A1, Fig. 29A2, Fig. 29A3, Fig. 29A4, Fig. 29A5, Fig. 29A6, Fig. 29A7 and Fig. 29B1, Fig. 29B2, Fig. 29B3, Fig. 29B4, Fig. 29B5, Fig. 29B6 are circuit diagrams for explaining electrical connections.

[0029] (Additional Notes Related to the Present Specification) In the present specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit. A semiconductor device also refers to any device that can function by utilizing semiconductor characteristics. An example of a semiconductor device is an integrated circuit. Another example of a semiconductor device is a chip equipped with an integrated circuit. Another example of a semiconductor device is an electronic component that houses a chip in a package. For example, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be a semiconductor device, or may include a semiconductor device.

[0030] In this specification, "connection" includes, for example, "electrical connection."

[0031] When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, it includes, for example, "direct connection" and "indirect connection." For example, "A and B are directly connected" refers to a connection between A and B without the intervention of a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, for example, "A and B are indirectly connected" refers to a connection between A and B via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0032] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0033] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 29A1 and 29A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases in which the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 29A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0034] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 29A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 29A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0035] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 29A6 and 29A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 29A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, the connection relationship will be the same as in Figures 29A6 and 29A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0036] Although an example of "indirect connection" has been given above, as an example, the provision of "indirect connection" is included in the provision of "electrical connection," so when "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0037] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 29B1, 29B2, and 29B3. When A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, as shown in FIGS. 29B4 and 29B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 29B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0038] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0039] Note that even when independent components are shown as being connected to each other in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both a wiring and an electrode. Therefore, in this specification, the term "connection" also includes such cases where one conductive film has the functions of multiple components.

[0040] Generally, examples of a "resistance element" include a circuit element having a resistance value higher than 0Ω, wiring having a resistance value higher than 0Ω, etc. Therefore, the "resistance element" described in this specification includes wiring, diodes, or coils having a resistance value. Therefore, the term "resistance element" can sometimes be replaced with the terms "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," or "region having a resistance value" can sometimes be replaced with the term "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, 1 Ω or more and 1×10 ９ It can be made smaller than Ω.

[0041] Generally, examples of "capacitance" include a circuit element having a capacitance value higher than 0 F, a region of wiring having a capacitance value higher than 0 F, and a region between a gate or back gate and a source or drain in a transistor having a capacitance value higher than 0 F. Furthermore, the terms "capacitance element," "parasitic capacitance," or "gate capacitance" may sometimes be replaced with the term "capacitance." Conversely, the term "capacitance" may sometimes be replaced with the terms "capacitance element," "parasitic capacitance," or "gate capacitance."

[0042] Furthermore, a "capacitor" (including a "capacitor" with three or more terminals) includes an insulator and a pair of conductors sandwiching the insulator. Therefore, the term "pair of conductors" in a "capacitor" can be rephrased as "pair of electrodes," "pair of conductive regions," "pair of regions," or "pair of terminals." Furthermore, the terms "one of the pair of terminals" and "the other of the pair of terminals" may be referred to as a first terminal and a second terminal, respectively. The value of the electrostatic capacitance of a capacitor can be, for example, 0.05 fF or more and 10 pF or less. Furthermore, it can be, for example, 1 pF or more and 10 μF or less.

[0043] The switches described in this specification are described as having the function of being turned on or off and controlling whether or not a current flows, or as having the function of selecting and switching the path through which a current flows.

[0044] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0045] In addition, in this specification, the terms "conductive" or "conductive state" used when conductive layers are in direct contact with each other refer to a state in which a current can flow between the conductive layers, for example.

[0046] Furthermore, the switch may have two or more terminals for passing current in addition to the control terminal. For example, an electrical switch, a mechanical switch, or the like may be used. In other words, the switch is not limited to a specific type as long as it has the function of controlling current.

[0047] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these. When a transistor is used as a switch, the "conductive state" or "on state" of the transistor refers to a state in which a current can flow between the source electrode and the drain electrode of the transistor. The "non-conductive state" or "off state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0048] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls the conductive and non-conductive states.

[0049] The selector circuit described herein may be, for example, a circuit having multiple input terminals and one output terminal, selecting one of the multiple input terminals, and establishing a conductive state between the selected input terminal and the one output terminal. In other words, the selector circuit described herein may be a circuit that selects one of the input signals input to each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, the selector circuit described herein may be, for example, a circuit having multiple output terminals and one input terminal, selecting one of the multiple output terminals, and establishing a conductive state between the selected output terminal and the one input terminal. In other words, the selector circuit may be a circuit that selects one of the multiple output terminals and outputs the input signal input to the input terminal to the selected output terminal. In other words, the selector circuit may refer to a multiplexer or a demultiplexer. In particular, when an analog potential or an analog current is input or output, the selector circuit may refer to an analog multiplexer or an analog demultiplexer.

[0050] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls switching between a conductive state and a non-conductive state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of potential applied to the three terminals of the transistor. Therefore, in this specification, the terms "source" and "drain" are sometimes interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source and the drain" and "the other of the source and the drain" are used. In this specification, one of the source and the drain is sometimes referred to as a "first electrode of the transistor" or a "first terminal of the transistor," and the other of the source and the drain is sometimes referred to as a "second electrode of the transistor" or a "second terminal of the transistor." Note that, depending on the structure of a transistor, a backgate may be provided in addition to the three terminals described above. In this case, in this specification, one of the gate or back gate of the transistor may be referred to as a first gate, and the other of the gate or back gate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "back gate" may be interchangeable. Furthermore, in this specification, when a transistor has three or more gates, the respective gates may be referred to as a first gate, a second gate, a third gate, etc.

[0051] For example, an example of a transistor described herein may include a multi-gate transistor with two or more gate electrodes. The multi-gate structure connects the channel formation regions in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the transistor's breakdown voltage (reliability). Alternatively, the multi-gate structure can achieve a flat Id-Vds characteristic when operating in the saturation region of the Id (source-drain current)-Vds (drain-source voltage) characteristic, where the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing the Id-Vds characteristic in this region, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0052] Generally, the threshold voltage of a transistor is a voltage between the subthreshold region (weak inversion region) and the strong inversion region, and can be said to be the voltage at which switching between the subthreshold region and the strong inversion region occurs. In addition, as an example of a method for measuring the threshold voltage, Id is calculated based on the Id (source-drain current) - Vgs (gate-source voltage) characteristics. １／２ -Vgs characteristics are plotted, and Id １／２ Id on the tangent line where the slope of the -Vgs characteristic is maximum １／２ As another example, in the Id-Vgs characteristic where the drain potential is 1.2 V, Id=1.0×10 −１２ A is set as the threshold voltage.

[0053] In this specification, the term "operation in the subthreshold region" refers to a case where the gate-source voltage of the transistor is lower than the threshold voltage, more preferably a case where the drain current of the transistor increases exponentially with the gate-source voltage. This also refers to a case where appropriate potentials are applied to the gate, source, and drain of the transistor so that the transistor operates in the subthreshold region.

[0054] In this specification, the subthreshold region refers to a region in a graph showing the Id-Vgs characteristics of a transistor where Vgs is lower than the threshold voltage. Alternatively, the subthreshold region refers to a region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to a region where Id increases exponentially with increasing Vgs. Alternatively, the subthreshold region includes regions that can be considered as the regions described above.

[0055] In this specification, the source-drain current when a transistor operates in the subthreshold region is referred to as the “subthreshold current.” The subthreshold current increases exponentially with the gate-source voltage, regardless of the drain potential.

[0056] In general, the off-state current of a transistor may refer to a source-drain current that flows when the gate-source voltage Vgs of the transistor is lower than the threshold voltage. Therefore, the off-state current may include a subthreshold current. Note that, in this specification, since a circuit driven by a subthreshold current is described, the off-state current will be described as a current lower than the subthreshold current unless otherwise specified.

[0057] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors connected in series. For example, when a circuit diagram shows one capacitance element, this includes two or more capacitance elements connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors connected in series, with the gates of the transistors connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors connected in series or in parallel, with the gates of the transistors connected to each other.

[0058] In this specification, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and device structure. A terminal, a wiring, etc. can also be referred to as a node.

[0059] Furthermore, in this specification, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0060] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials applied to the two wirings may be different from each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials applied to the two wirings may be different from each other.

[0061] Furthermore, "current" refers to the phenomenon of charge transfer (electrical conduction). For example, the statement "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), the statement "current flows from element A to element B" can be rephrased as "current flows from element B to element A." Furthermore, the statement "current is input to element A" can be rephrased as "current is output from element A."

[0062] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the counter may be omitted in the claims. For example, a component with an ordinal number "first" added in one embodiment of this specification may be a component with a different ordinal number such as "second" or "third" added in other embodiments or claims. Furthermore, for example, a component with an ordinal number "first" added in one embodiment of this specification may be omitted in other embodiments or claims.

[0063] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, etc., and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0064] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B. Similarly, the expression "electrode B below insulating layer A" does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0065] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the orientation in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees. Similarly, the expression "column direction" may be rephrased as "row direction" by rotating the orientation of the drawing by 90 degrees.

[0066] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer". Or, in some cases or depending on the situation, the terms "film" and "layer" can be replaced with other terms without being used. For example, the term "conductive layer" or "conductive film" can be changed to the term "conductor". Or, for example, the term "insulating layer" or "insulating film" can be changed to the term "insulator".

[0067] Furthermore, in this specification, terms such as "electrode," "wiring," and "terminal" do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, terms such as "electrode" or "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where one or more selected from "electrode," "wiring," and "terminal" are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," and "terminal" may be replaced with the term "region" in some cases.

[0068] Furthermore, in this specification, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" or "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, a term such as "signal line" may be changed to the term "power line." Furthermore, a term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, a term such as "signal" may be changed to the term "potential."

[0069] In addition, timing charts may be used in this specification to explain an operation method of a semiconductor device. The timing charts used in this specification illustrate ideal operation examples, and the periods, magnitudes, and timings of signals (e.g., potentials or currents) described in the timing charts are not limited unless otherwise specified. The magnitudes and timings of signals (e.g., potentials or currents) input to each wiring (including a node) in the timing charts described in this specification may be changed depending on the situation. For example, even if two periods are shown at equal intervals in a timing chart, the lengths of the two periods may be different. For example, even if one period is shown as long and the other as short, the lengths of the two periods may be equal, or one period may be short and the other period may be long. For example, to clearly illustrate the timing charts, two or more overlapping signals may be intentionally shifted.

[0070] In this specification, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0071] In this specification, nitrogen-containing metal oxides may also be collectively referred to as metal oxides, and nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0072] In this specification, the term "impurities" in a semiconductor refers to, for example, elements other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0073] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0074] In this specification, unless otherwise specified, the expression "A and B are equal" means that the ratio of one of A and B to the other is 0.9 or more and 1.1 or less. For example, the case where the ratio of B to A is 0.9 or more and 1.1 or less and the ratio of A to B is not 0.9 or more and 1.1 or less is also considered to be "A and B are equal." Furthermore, unless otherwise specified, the expression "A and B are approximately equal" means that the ratio of one of A and B to the other is 0.8 or more and 1.2 or less, is also considered to be "A and B are approximately equal." For example, the case where the ratio of B to A is 0.8 or more and 1.2 or less and the ratio of A to B is not 0.8 or more and 1.2 or less is also considered to be "A and B are approximately equal."

[0075] In this specification, the configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. When multiple configuration examples are shown in one embodiment, the configuration examples can be combined with each other as appropriate.

[0076] In addition, the content described in one embodiment can be applied, combined, or replaced with another content described in that embodiment and at least one of the content described in another embodiment.

[0077] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0078] Furthermore, a figure described in one embodiment can be combined with another portion of that figure and at least one figure described in one or more other embodiments to form even more figures.

[0079] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0080] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to the reference numeral in the drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0081] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0082] Embodiment 1 In this embodiment, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device has the effect of suppressing variations in calculation results and increasing the accuracy rate of inference using an artificial neural network. To achieve these effects, the semiconductor device includes a circuit having excellent input / output characteristics between digital data input from an external device and an analog current converted from the digital data and output.

[0083] 1 is a block diagram illustrating a configuration example of a calculation device that is a semiconductor device according to one embodiment of the present invention. The calculation device, for example, has a function of calculating the sum of products of a plurality of first data items and a plurality of second data items, and a function of calculating a function in which the result of the sum of products is assigned as a variable. The calculation device also has a function of performing calculations on a hierarchical neural network. In this case, for example, the plurality of first data items are treated as weight coefficients (which may be referred to as weight data, connection strengths, etc.), and the plurality of second data items are treated as data to be input to neurons (which may be referred to as input data).

[0084] In addition, in this specification, the first data may be referred to as a multiplier, and the second data may be referred to as a multiplicand. Note that the multiplier and the multiplicand can be interchangeable due to the commutative law of products. For example, the first data may be referred to as a multiplicand, and the second data may be interchangeable as a multiplier.

[0085] The arithmetic device CDVA shown in FIG. 1 includes, as an example, a voltage generating circuit RSTR, a cell array CA, a driving circuit WCD, a driving circuit XCD, a driving circuit WSD, and a driving circuit ITS.

[0086] <<Cell Array CA>> The cell array CA is a circuit that calculates the sum of products of multiple first data and multiple second data. Specifically, the arithmetic cells IM included in the cell array CA have the function of multiplying the first data by the second data. The cell array CA can also calculate the sum of products of the multiple first data and the multiple second data by adding the results of the multiplications performed by the multiple arithmetic cells IM. The arithmetic cells IM included in the cell array CA also have the function of holding a potential corresponding to the first data. Thus, the arithmetic cells IM that have the function of holding first data corresponding to a multiplier in addition to the arithmetic function, the cell array CA including the arithmetic cells IM, or the arithmetic device CDVA including the cell array CA are sometimes referred to as in-memory computing.

[0087] As an example, in the cell array CA, a plurality of calculation cells IM are arranged in a matrix of m rows and n columns (m is an integer equal to or greater than 1, and n is an integer equal to or greater than 1). Therefore, the cell array CA shown in FIG. 1 is assumed to be provided with m×n calculation cells IM.

[0088] 1 indicates the address within the cell array CA where the calculation cell IM is arranged, for example, calculation cell IM[x, y] indicates that it is arranged in the xth row and yth column of the cell array CA. Note that the above can also be applied to other drawings.

[0089] 1, the calculation cell IM arranged in the first row and first column is indicated as calculation cell IM[1,1], the calculation cell IM arranged in the mth row and first column is indicated as calculation cell IM[m,1], the calculation cell IM arranged in the first row and nth column is indicated as calculation cell IM[1,n], and the calculation cell IM arranged in the mth row and nth column is indicated as calculation cell IM[m,n]. Also, calculation cells IM other than calculation cell IM[1,1], calculation cell IM[m,1], calculation cell IM[1,n], and calculation cell IM[m,n] are not shown in FIG.

[0090] In addition, in the cell array CA, as an example, m drive cells IMD are arranged in each row. In particular, in Figure 1, "_" attached to a drive cell IMD indicates the address in the cell array CA where the drive cell IMD is arranged, and for example, drive cell IMD_x indicates that it is arranged in the xth row of the cell array CA. Note that the above can also be used for other drawings.

[0091] 1, the driver cell IMD arranged in the first row is indicated as driver cell IMD_1, and the driver cell IMD arranged in the mth row is indicated as driver cell IMD_m. Also, driver cells IMD other than driver cell IMD_1 and driver cell IMD_m are not shown in FIG.

[0092] In the cell array CA, for example, wirings WCL_1 to WCL_n extend in the column direction, and wirings XCL_1 to XCL_m and wirings WSL_1 to WSL_m extend in the row direction.

[0093] The connection configuration of a computation cell IM[i,j] (not shown) arranged in the i-th row and j-th column (i is an integer between 1 and m, and j is an integer between 1 and n) in the cell array CA will be described. The computation cell IM[i,j] is connected to each of a wiring WCL_j (not shown), a wiring XCL_i (not shown), and a wiring WSL_i (not shown). Furthermore, a driving cell IMD_i (not shown) arranged in the i-th row is connected to each of the wiring XCL_i and the wiring WSL_i.

[0094] The configurations of the computation cell IM[i, j] and the driving cell IMD_i will be described later.

[0095] <<Voltage Generator Circuit RSTR>> The voltage generator circuit RSTR has, for example, a function of generating a plurality of analog potentials and a function of applying the plurality of analog potentials to the wirings VRWL and VRXL.

[0096] A specific configuration example of the voltage generation circuit RSTR is shown in Fig. 2. The voltage generation circuit RSTR in Fig. 2 is a circuit that generates an analog potential (a potential corresponding to a value from "0" to "255") with a resolution of 8 bits by a resistive voltage division method, and includes resistor elements Ra_1 to Ra_255 and terminals VOT_0 to VOT_255.

[0097] 2, the resistor elements Ra_1 to Ra_255 are connected in series, and therefore may be collectively referred to as a resistor string.

[0098] 2, as an example, each of the resistors Ra_1 to Ra_255 is illustrated as a single resistor. One embodiment of the present invention is not limited thereto, and for example, each of the resistors Ra_1 to Ra_255 may be a plurality of resistors instead of a single resistor.

[0099] Terminals VOT_0 to VOT_255 for outputting the generated analog potentials are provided at both ends of the resistor string and at the points where the resistor elements are connected to each other.

[0100] Specifically, a first terminal of the resistor element Ra_255 is connected to the wiring VDHL and the terminal VOT_255, and a second terminal of the resistor element Ra_k+1 (k is an integer between 0 and 254) is connected to the first terminal of the resistor element Ra_k and the terminal VOT_k. Also, a second terminal of the resistor element Ra_1 is connected to the wiring VSLL and the terminal VOT_0.

[0101] Furthermore, the wiring VRWL or the wiring VRXL is connected to each of the terminals VOT_0 to VOT_255. For this reason, in this specification, each of the wiring VRWL and the wiring VRXL is treated as a wiring group including a plurality of wirings.

[0102] The wiring VDHL has a function as a wiring that applies a fixed potential, for example. In particular, in this specification, the fixed potential is a high power supply potential for generating an analog potential according to the resolution in the voltage generation circuit RSTR.

[0103] The wiring VSLL functions as a wiring that applies a fixed potential, for example. In particular, in this specification, the fixed potential is a low power supply potential for generating an analog potential according to the resolution in the voltage generation circuit RSTR.

[0104] By applying a high power supply potential from the wiring VDHL and a low power supply potential from the wiring VSLL, the voltage generation circuit RSTR can output each potential divided into 8 bits to each of the terminals VOT_0 to VOT_255.

[0105] 1 can be applied with the circuit configuration of the voltage generating circuit RSTR shown in FIG. 3A, for example, other than the circuit configuration of the voltage generating circuit RSTR shown in FIG. 2.

[0106] 3A includes, for example, amplifiers GA_0 to GA_255, resistors Ra_1 to Ra_255, and resistors Rb_1 to Rb_255. In other words, the voltage generation circuit RSTR in FIG. 3A can be said to be a circuit in which amplifiers GA_0 to GA_255 and resistors Rb_1 to Rb_255 are further provided in addition to the voltage generation circuit RSTR in FIG.

[0107] Each of the amplifiers GA_0 to GA_255 is illustrated as a voltage follower using a differential amplifier circuit. That is, each of the amplifiers GA_0 to GA_255 has an amplification factor of 1, so that the potential of the input terminal and the potential of the output terminal are equal.

[0108] In the voltage generating circuit RSTR in FIG. 3A, the resistors Rb_1 to Rb_255 are also connected in series as a resistor string, similar to the resistors Ra_1 to Ra_255.

[0109] Furthermore, for example, each of the resistor elements Rb_1 to Rb_255 may be a plurality of resistor elements instead of a single resistor element.

[0110] Next, the connection configuration of the voltage generating circuit RSTR in FIG. 3A will be described.

[0111] A first terminal of the resistor Ra_255 is connected to the wiring VDHL and the input terminal of the amplifier GA_255, a second terminal of the resistor Ra_k+1 is connected to the first terminal of the resistor Ra_k and the input terminal of the amplifier GA_k, and a second terminal of the resistor Ra_1 is connected to the wiring VSLL and the input terminal of the amplifier GA_0.

[0112] A first terminal of the resistor Rb_255 is connected to the wiring VDHL, the output terminal of the amplifier GA_255, and the terminal VOT_255, a second terminal of the resistor Rb_k+1 is connected to the first terminal of the resistor Rb_k, the output terminal of the amplifier GA_k, and the terminal VOT_k, and a second terminal of the resistor Rb_1 is connected to the wiring VSLL, the output terminal of the amplifier GA_0, and the terminal VOT_0.

[0113] 2, the voltage generation circuit RSTR in FIG. 3A includes amplifiers GA_0 to GA_255. Therefore, even if the potential of any one of the terminals VOT_0 to VOT_255 fluctuates, the corresponding amplifier GA quickly charges or discharges the terminal VOT_0 to VOT_255, thereby restoring the fluctuated potential to its original potential. In other words, since the charging and discharging of the wiring VRWL and the wiring VRXL is fast, the input of the power supply voltage from the voltage generation circuit RSTR to the circuits WCDa and XCDa can be stabilized. Note that the circuit WCDa is provided in the driver circuit WCD, and the circuit XCDa is provided in the driver circuit XCD. Details of each circuit will be described later.

[0114] 3A , the number of amplifiers GA may be reduced as long as the potentials of the terminals VOT_0 to VOT_255 can be sufficiently stabilized. For example, in FIG. 3B , the voltage generation circuit RSTR may include 17 amplifiers GA, namely, amplifiers GAD_1 to GAD_17. Note that the amplifier GAD_1 shown in FIG. 3B corresponds to the amplifier GA_0 in the voltage generation circuit RSTR of FIG. 3A , the amplifier GAD_2 shown in FIG. 3B corresponds to the amplifier GA_16 (not shown in FIG. 3A ) in the voltage generation circuit RSTR of FIG. 1 , the amplifier GAD_16 corresponds to the amplifier GAD_240 (not shown in FIG. 3A ) in the voltage generation circuit RSTR of FIG. 3A , and the amplifier GAD_17 in FIG. 3B corresponds to the amplifier GA_255 in the voltage generation circuit RSTR of FIG. 3A . 3B, by reducing the number of amplifiers GA in the voltage generator circuit RSTR of FIG. 3A, the power consumption of the voltage generator circuit RSTR can be reduced, and the circuit area of ​​the voltage generator circuit RSTR can also be reduced.

[0115] <<Driver Circuit WCD>> The driver circuit WCD is connected to the wirings IWL_1 to IWL_n, the wirings WCL_1 to WCL_n, the wiring VRWL, and the wiring SWLA. For example, the driver circuit WCD has a function of converting first data, which is digital data transmitted from the wiring IWL_j, into an analog current and causing the analog current to flow through the wiring WCL_j.

[0116] As will be described in detail later, the analog current flows to a selected one of the calculation cells IM[1,j] to IM[m,j] arranged in the jth column of the cell array CA, and the selected calculation cell IM holds a potential corresponding to the analog current, thereby enabling the selected calculation cell IM to acquire and store first data corresponding to the analog current.

[0117] The driver circuit WCD includes, for example, circuits WCDa_1 to WCDa_n, transistors FW_1 to FW_n, and a circuit SWCA. The circuit SWCA also includes switches SA_1 to SA_n.

[0118] Each of the switches SA_1 to SA_n can be, for example, an electrical switch such as an analog switch or a transistor. Alternatively, each of the switches SA_1 to SA_n can be, for example, a mechanical switch other than an electrical switch.

[0119] Furthermore, when transistors are used as the switches SA_1 to SA_n as electrical switches, the transistors can be OS transistors. OS transistors can have extremely low off-state current, which can prevent an increase in power consumption due to leakage current when the switches SA_1 to SA_n are in an off state. To increase the on-state current of the switches SA_1 to SA_n, it is preferable to use transistors (sometimes referred to as IO transistors) containing indium oxide, a type of oxide semiconductor, in their channel formation regions as the electrical switches used for the switches SA_1 to SA_n.

[0120] Note that an OS transistor and an oxide semiconductor included in the OS transistor will be described later in Embodiment 3. In particular, an oxide containing indium will be described in Embodiment 4.

[0121] Furthermore, when an electrical switch is used for each of the switches SA_1 to SA_n, the electrical switch can be, for example, a transistor including silicon in a channel formation region (sometimes called a Si transistor) other than an OS transistor.

[0122] In this specification, the switches SA_1 to SA_n are described as being electric switches. Each of the switches SA_1 to SA_n has a control terminal, and each of the switches SA_1 to SA_n is turned on when a high-level potential is input to the control terminal, and is turned off when a low-level potential is input to the control terminal.

[0123] An input terminal of the circuit WCDa_j (not shown) is connected to a wiring IWL_j (not shown), and an output terminal of the circuit WCDa_j is connected to a gate of a transistor FW_j (not shown). A power supply input terminal of the circuit WCDa_j is connected to a voltage generating circuit RSTR via a wiring VRWL. In this specification, the power supply input terminal of the circuit WCDa_j may be referred to as a first input terminal, and the input terminal connected to the wiring IWL_j may be referred to as a second input terminal.

[0124] A first terminal of the transistor FW_j is connected to the wiring VEH, a second terminal of the transistor FW_j is connected to the first terminal of the switch SA_j, a second terminal of the switch SA_j is connected to the wiring WCL_j, and a control terminal of the switch SA_j is connected to the wiring SWLA.

[0125] 1, the transistors FW_1 to FW_n are each an n-channel transistor, but one embodiment of the present invention is not limited thereto, and for example, each of the transistors FW_1 to FW_n may be a p-channel transistor.

[0126] For example, the wiring VEH functions as a wiring that applies a fixed potential. Specifically, the fixed potential can be, for example, a high-level potential.

[0127] For example, the wiring SWLA functions as a wiring for transmitting a signal for controlling the on / off switching of each of the switches SA_1 to SA_n.

[0128] Each of the circuits WCDa_1 to WCDa_n functions as a selector circuit. Specifically, the circuit WCDa_j has a function of acquiring digital data input to the wiring IWL_j, selecting a potential according to the value of the digital data from each potential supplied from the voltage generation circuit RSTR, and outputting the selected potential from an output terminal.

[0129] 4 shows an example of the configuration of a selector circuit that can be applied to the circuits WCDa_1 to WCDa_n shown in FIG. 1. The circuit WCDa_j shown in FIG. 4 is an analog multiplexer with a tree structure of pass-transistor logic. Note that, for the purpose of explaining the connection configuration with the circuit WCDa_j, FIG. 4 also shows the voltage generation circuit RSTR and the transistor FW_j described above.

[0130] 4, the circuit WCDa_j includes one or more p-channel transistors and one or more n-channel transistors. Note that the transistors included in the circuit WCDa_j function as switching transistors.

[0131] For example, when the analog multiplexer selects and outputs one of analog potentials with a resolution of H bits (H is an integer equal to or greater than 1), the number of p-channel transistors and n-channel transistors included in the analog multiplexer is Σ2 （ｈ−１） In addition, Σ2 （ｈ−１） is the number of times when the integer h is from 1 to H. （ｈ−１） Therefore, the total number of p-channel transistors and n-channel transistors is Σ2 ｈ In this specification, an analog multiplexer that selects and outputs one of analog potentials with a resolution of H bits is called an H-bit analog multiplexer.

[0132] Specifically, in the case of a 1-bit analog multiplexer, one p-channel transistor and one n-channel transistor are required to select and output one analog potential with a resolution of 1 bit, and in the case of a 3-bit analog multiplexer, 1+2+4=7 p-channel transistors and 1 n-channel transistor are required to select and output one analog potential with a resolution of 3 bits.

[0133] 4 is an analog multiplexer with 8-bit resolution, and is configured to select and output one of the 8-bit analog potentials, so the number of p-channel transistors and the number of n-channel transistors is 1 + 2 + 4 + 8 + 16 + 32 + 64 + 128 = 255. Note that the circuit WCDa_j in FIG. 4 shows only some, but not all, of the transistors.

[0134] Furthermore, one or more p-channel transistors and one or more n-channel transistors included in the circuit WCDa_j in FIG. 4 can be Si transistors. Alternatively, one or more n-channel transistors included in the circuit WCDa_j can be OS transistors. OS transistors can have extremely low off-state current and are therefore suitable as switching transistors included in the circuit WCDa_j. Furthermore, using an IO transistor among OS transistors as one or more n-channel transistors included in the circuit WCDa_j can not only reduce off-state current but also improve on-state characteristics. Therefore, using an IO transistor as the n-channel transistor included in the circuit WCDa_j allows the circuit WCDa_j to function as a selector circuit with excellent input / output characteristics.

[0135] The circuit WCDa_j in FIG. 4 also includes inverters IV[0] to IV[7] for controlling the on and off states of the transistors.

[0136] In addition, in an H-bit analog multiplexer, the number of transistors arranged in the H-h-th bit stage of the H bits is 2 ｈFor example, as shown in FIG. 4, in the case of an analog multiplexer with H=8 bits, there are two transistors arranged at the 8-1=7th bit (when h=1). One of the two transistors is a p-channel transistor, and the other is an n-channel transistor. The gates of the p-channel transistor and the n-channel transistor are connected to a wiring SELa[7] that transmits the value of the H-h=8-1=7th bit as a signal via the input terminal of the circuit WCDa_j and an inverter IV[7].

[0137] For example, in the case of an analog multiplexer with H = 8 bits, the number of transistors arranged at the 0th bit (when h = 8) is 256 (H - h = 8 - 8 = 0th bit). Of the 256 transistors, 128 are p-channel transistors, and the remaining 128 are n-channel transistors. The gates of 64 of the 128 p-channel transistors and 64 of the 128 n-channel transistors are connected to a wiring SELa[0] that transmits the value of the 0th bit as a signal via an input terminal of the circuit WCDa_j. The gates of the remaining 64 of the 128 p-channel transistors and the remaining 64 of the 128 n-channel transistors are connected to a wiring SELa[0] via an input terminal of the circuit WCDa_j and an inverter IV[0].

[0138] In this specification, in binary notation, the LSB (Least Significant Bit) is written as the 0th bit, and the MSB (Most Significant Bit) is written as the Hth bit.

[0139] 4, the wirings SELa[0] to SELa[7] are collectively referred to as wiring IWL_j. That is, the wiring IWL_j is regarded as a group of wirings that collectively includes the wirings SELa[0] to SELa[7]. Therefore, each of the wirings IWL_1 to IWL_n shown in FIG. 1 can also be regarded as a group of wirings SELa[0] to SELa[7] included in each of the circuits WCDa_1 to WCDa_n. Therefore, the potential of each bit transmitted to each of the wirings SELa[0] to SELa[7] can be a signal corresponding to each bit of the digital data transmitted by the wiring IWL_j.

[0140] 4 can be any one of the voltage generator circuits RSTR shown in FIGS. 2 to 3B. As described for the voltage generator circuits RSTR shown in FIGS. 2 to 3B, the voltage generator circuit RSTR shown in FIG. 4 generates 8-bit analog potentials and outputs the respective potentials to the terminals VOT_0 to VOT_255. Each of the terminals VOT_u (where u is an integer between 0 and 255) is connected to the terminal VIT_u of the circuit WCDa_j. In other words, each of the terminals VOT_0 to VOT_255 of the voltage generator circuit RSTR is connected in a one-to-one relationship to either the source or the drain of each of the 255 transistors arranged at the 0th bit in the circuit WCDa_j.

[0141] 4, the on / off state of each of the 255 p-channel transistors and the 255 n-channel transistors included in the circuit WCDa_j is determined by the potentials of the 8-bit digital data transmitted to the wirings SELa_0 to SELa_7. This uniquely determines a current path between any one of the terminals VIT_0 to VIT_255 and the output terminal of the circuit WCDa_j. That is, one of the 8-bit analog potentials generated by the voltage generation circuit RSTR is selected according to the potential of the 8-bit digital data. This converts the 8-bit digital data provided to the wiring IWL_j into an analog potential, and the analog potential is provided to the gate of the transistor FW_j.

[0142] Furthermore, when the analog potential is applied to the transistor FW_j, a current corresponding to the analog potential flows between the source and drain of the transistor FW_j. Note that the fixed potential of the wiring VEH applied to the first terminal of the transistor FW_j and the potentials of the terminals VOT_0 to VOT_255 of the voltage generation circuit RSTR applied to the gate of the transistor FW_j are each an appropriate potential that allows the transistor FW_j to operate in the subthreshold region.

[0143] 2 to 3B, the resistors Ra_1 to Ra_255 may have different resistance values.

[0144] In the driver circuit WCD of Figure 1, by applying the circuit WCDa_j shown in Figure 4 to each of the circuits WCDa_1 to WCDa_n, the input / output characteristics of the value of digital data transmitted to the wiring IWL and the amount of current flowing from the driver circuit WCD to the wiring WCL can be improved.

[0145] Specifically, the input / output characteristics of the WCDa_j in Figure 4 are better than those of the circuit WCDpn_j shown in Figures 10A and 10B (described later). In particular, in the case of the circuit WCDpn_j shown in Figures 10A and 10B, variations in the electrical characteristics of the transistor Tr1 provided in each of the current sources CS1 to CS4 shown in Figures 11A to 11D can cause the amount of current flowing from the drive circuit WCD to the wiring WCL to deviate from the ideal input / output characteristics. This can cause the results calculated by the computing device to differ from the expected values. This can also result in a low accuracy rate for inferences using an artificial neural network.

[0146] 4 to each of the circuits WCDa_1 to WCDa_n in the driver circuit WCD of FIG. 1, the amount of current flowing from the driver circuit WCD to the wiring WCL can be made closer to ideal input / output characteristics, and the result of the calculation performed by the arithmetic unit CDVA can be made as close as possible to an expected value. This also increases the accuracy rate of inference using an artificial neural network.

[0147] Furthermore, the driver circuit WCD shown in FIG. 1 can be modified to have the configuration of the driver circuit WCD shown in FIG. 5A. FIG. 5A shows an example circuit configuration of the driver circuit WCD in which loads LR_1 to LR_n are added to the driver circuit WCD of FIG. 1. Specifically, the second terminal of the transistor FW_1 is connected to the first terminal of the load LR_1 instead of the first terminal of the switch SA_1, and the second terminal of the load LR_1 is connected to the first terminal of the switch SA_1. Furthermore, the second terminal of the transistor FW_n is connected to the first terminal of the load LR_n instead of the first terminal of the switch SA_n, and the second terminal of the load LR_n is connected to the first terminal of the switch SA_n.

[0148] The loads LR_j (not shown) may be, for example, resistors, transistors, diodes, etc. In particular, when diodes are used as the loads LR_j, the first terminals of the loads LR_j are connected as the anodes of the diodes, and the second terminals of the loads LR_j are connected as the cathodes of the diodes, thereby allowing a positive analog current to flow from the wiring VEH to the wiring WCL_j.

[0149] 5A , by providing a load LR_j between the transistor FW_j and the switch SA_j, the slope of the curve in the subthreshold region in the characteristics of the gate-source voltage and source-drain current of the transistor FW_j can be reduced. Reducing the slope of the curve in the subthreshold region can increase the range of the gate-source voltage in the subthreshold region, making it easier to control the amount of current flowing through the transistor FW_j when an analog potential is applied to the gate of the transistor FW_j.

[0150] 1 , the configuration in which loads LR_1 to LR_n are additionally provided may be the configuration in FIG. 5B instead of FIG. 5A . The circuit configuration in FIG. 5B is obtained by switching the connection order of the transistor FW_j and the load LR_j in FIG. 5A . Specifically, the second terminal of the load LR_j is connected to the wiring VEH instead of the first terminal of the switch SA_j, and the first terminal of the transistor FW_j is connected to the first terminal of the switch SA_j. The circuit configuration in FIG. 5B also makes it easier to control the amount of current flowing through the transistor FW_j.

[0151] The driver circuit WCD shown in FIG. 1 can be modified to have the configuration shown in FIG. 5C. FIG. 5C shows an example of a circuit configuration of the driver circuit WCD in which back gates are provided for the transistors FW_1 to FW_n of the driver circuit WCD shown in FIG. 1. In FIG. 5C, wiring (not shown) is preferably connected to the back gates of the transistors FW_1 to FW_n to apply a desired potential in order to control the threshold voltages of the transistors FW_1 to FW_n. Controlling the threshold voltage of the transistor FW_j can also reduce the slope of the curve in the subthreshold region, making it easier to control the amount of current flowing through the transistor FW_j.

[0152] <<Driver Circuit XCD>> The driver circuit XCD is connected to the wirings IXL_1 to IXL_m, the wirings XCL_1 to XCL_m, and the wiring VRXL. For example, the driver circuit XCD has a function of converting second data or reference data, which is digital data transmitted from the wiring IXL_i, into an analog current and causing the analog current to flow through the wiring XCL_i. Note that the reference data is data that serves as a reference for the second data. Although the details will be described later, the ratio of the second data to the reference data essentially becomes the multiplicand for the first data.

[0153] The driver circuit XCD includes, for example, circuits XCDa_1 to XCDa_m and transistors FX_1 to FX_m.

[0154] An input terminal of the circuit XCDa_i (not shown) is connected to a wiring IXL_i (not shown), an output terminal of the circuit XCDa_i is connected to the gate of a transistor FX_i (not shown), and a power supply input terminal of the circuit XCDa_i is connected to the voltage generating circuit RSTR via a wiring VRXL.

[0155] A first terminal of the transistor FX_i is connected to the wiring VEH, and a second terminal of the transistor FX_i is connected to the wiring XCL_i.

[0156] For the wiring VEH, the description of the wiring VEH explained in the configuration example of the driver circuit WCD can be referred to.

[0157] Each of the circuits XCDa_1 to XCDa_m has a function as a selector circuit, similar to the circuits WCDa_1 to WCDa_n. Specifically, the circuit XCDa_i has a function of acquiring digital data input to the wiring IXL_i, selecting a potential according to the value of the digital data from each potential supplied from the voltage generation circuit RSTR, and outputting the selected potential from an output terminal.

[0158] 4, which is described in the configuration example of the driver circuit WCD. Specifically, the circuit XCDa_i can be configured by replacing the circuit WCDa_j with the circuit XCDa_i, the transistor FW_j with the transistor FX_i, and the wiring IWL_j with the wiring IXL_i in FIG. 4. Therefore, for the circuit XCDa_i, the description of the circuit WCDa_j described in the configuration example of the driver circuit WCD can be referred to.

[0159] As a result, in the circuit XCDa_i, 8-bit digital data serving as reference data or second data is transmitted to the wirings SELa_0 to SELa_7 as the wiring IXL_i. The on / off states of the 255 p-channel transistors and the 255 n-channel transistors included in the circuit XCDa_i are determined by the potentials of the transmitted 8-bit digital data. This uniquely determines a current path between any one of the terminals VIT_0 to VIT_255 and the output terminal of the circuit XCDa_i. That is, one of the 8-bit analog potentials generated by the voltage generation circuit RSTR is selected according to the potential of the 8-bit digital data. The 8-bit digital data transmitted to the wiring IXL_i is converted into an analog potential, and the analog potential is applied to the gate of the transistor FX_i.

[0160] Furthermore, by using the same transistor as the transistor FW_j for the transistor FX_i, a subthreshold current corresponding to the analog potential flows between the source and drain of the transistor FX_i. In other words, when digital data serving as reference data or second data is applied to the wiring IXL_i, the driving circuit XCD generates a current corresponding to the digital data and causes the current to flow through the wiring XCL_i.

[0161] In the driver circuit XCD of Figure 1, by applying the circuit XCDa_i shown in Figure 4 to each of the circuits XCDa_1 to XCDa_m, the input / output characteristics of the value of digital data transmitted to the wiring IXL and the amount of current flowing from the driver circuit XCD to the wiring XCL can be improved, as in the above-mentioned driver circuit WCD.

[0162] Specifically, the input / output characteristics can be improved compared to those of the drive circuit XCD shown in Fig. 10C (described later). For an explanation of the input / output characteristics of the drive circuit XCD in Fig. 10C, please refer to the explanation of the input / output characteristics of the drive circuit WCD in Figs. 10A and 10B (described above).

[0163] 4 to each of the circuits XCDa_1 to XCDa_m in the driver circuit XCD of FIG. 1, the input / output characteristics can be improved compared to those of the driver circuit XCD shown in FIG. 10C, and the results of the calculations performed by the arithmetic unit CDVA can be brought as close as possible to the expected values. This also increases the accuracy rate of inferences using an artificial neural network.

[0164] 5A or 5B, a load may be connected in series to the transistor FX_i provided in the drive circuit XCD. Also, as in FIG. 5C, a back gate may be provided to the transistor FX_i provided in the drive circuit XCD. These configurations make it easier to control the amount of current flowing through the transistor FX_i.

[0165] <<Driver Circuit WSD>> The driver circuit WSD shown in FIG. 1 has a function of turning on the write transistor included in the computation cell IM by supplying a predetermined signal to the wiring WSL when writing first data to the computation cell IM. Similarly, it also has a function of turning on the write transistor included in the drive cell IMD. In other words, the driver circuit WSD functions as a write word line driver circuit for the computation cell IM and the drive cell IMD. For example, the driver circuit WSD can turn on the write transistor included in the computation cell IM (transistor M1 described below) and the write transistor included in the drive cell IMD (transistor M1d described below) by supplying a high-level potential as a select signal to the wiring WSL. Furthermore, the driver circuit WSD can turn off the write transistors included in the computation cell IM and the drive cell IMD by supplying a low-level potential as a deselect signal to the wiring WSL. As described above, the drive circuit WSD can select either writing data or retaining data in each of the processing cells IM and the driving cells IMD by transmitting a selection signal or a non-selection signal to the wiring WSL. Note that the data here refers to the first data in the processing cells IM and the second data in the driving cells IMD.

[0166] <<Computation Cells IM and Driver Cells IMD>> Next, a configuration example of the computation cells IM and driver cells IMD included in the cell array CA will be described.

[0167] Fig. 6A is a circuit diagram showing an example configuration of the calculation cell IM[i,j] arranged in the i-th row and j-th column, and the drive cell IMD_i arranged in the i-th row, in the cell array CA of Fig. 1. Note that Fig. 6A also shows the voltage generation circuit RSTR, the drive circuit WCD, the drive circuit XCD, the drive circuit WSD, and the drive circuit ITS in order to explain the connection configuration of the calculation cell IM[i,j] and the drive cell IMD_i.

[0168] As an example, the calculation cell IM[i, j] has the function of holding the first data transmitted from the driving circuit WCD and the function of multiplying the first data by the second data by acquiring the second data transmitted from the driving circuit XCD.

[0169] As an example, the driving cell IMD_i has the function of retaining the reference data transmitted from the driving circuit XCD and the function of keeping the current flowing from the driving circuit XCD (the current corresponding to the reference data or the current corresponding to the second data) constant by using the transistor M3d described later.

[0170] 6A, the calculation cell IM[i,j] includes, for example, a transistor M1, a transistor M3, a transistor M4, and a capacitance element C1, and the driving cell IMD_i includes, for example, a transistor M1d, a transistor M3d, a transistor M4d, and a capacitance element C1d.

[0171] In the operation cell IM, the transistor M1 functions as a switching transistor, particularly a write transistor (sometimes called a hold transistor) for writing a potential corresponding to the first data. The transistor M3 functions as a transistor (sometimes called an amplifying transistor) for outputting a result of multiplication of a multiplier and a multiplicand. The transistor M4 functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M3 due to drain-induced barrier lowering (DIBL).

[0172] In the drive cell IMD, the transistor M1d functions as a switching transistor, particularly a write transistor for writing a potential corresponding to reference data. The transistor M3d functions as an amplifier transistor for passing a current (current corresponding to the reference data or the second data) generated by the drive circuit XCD. The transistor M4d functions as a clamp transistor for preventing a decrease in the threshold voltage of the transistor M3d due to DIBL.

[0173] Note that, for example, OS transistors can be used for each of the transistors M1, M3, M4, M1d, M3d, and M4d. In particular, since the transistors M1 and M1d function as switching transistors or write transistors, it is preferable to use OS transistors that can significantly reduce their off-state current. Furthermore, OS transistors may also be used for the transistors M3, M3d, M4, and M4d. Since the transistors M3 and M3d function as amplifying transistors, it is preferable to use transistors that can increase their on-state current. For example, by using IO transistors, which are a type of OS transistors, for the transistors M3 and M3d, the on-state current of each of the transistors M3 and M3d can be increased. Similarly, since the transistors M4 and M4d function as clamp transistors, it is preferable to use IO transistors that can increase their on-state current.

[0174] Further, in addition to OS transistors, Si transistors can be used as each of the transistors M1, M3, M4, M1d, M3d, and M4d.

[0175] In the calculation cell IM[i,j], the first terminal of the transistor M1 is connected to the first terminal of the capacitor C1 and the gate of the transistor M3, the second terminal of the transistor M1 is connected to the wiring WCL_j, and the gate of the transistor M1 is connected to the wiring WSL_i. The first terminal of the transistor M3 is connected to the first terminal of the transistor M4, and the second terminal of the transistor M3 is connected to the wiring VEL. The second terminal of the transistor M4 is connected to the wiring WCL_j, and the gate of the transistor M4 is connected to the wiring VEB. The second terminal of the capacitor C1 is connected to the wiring XCL_i.

[0176] In the driving cell IMD_i, the first terminal of the transistor M1d is connected to the first terminal of the capacitance element C1d and the gate of the transistor M3d, the second terminal of the transistor M1d is connected to the wiring XCL_i, and the gate of the transistor M1d is connected to the wiring WSL_i. The first terminal of the transistor M3d is connected to the first terminal of the transistor M4d, and the second terminal of the transistor M3d is connected to the wiring VEL. The second terminal of the transistor M4d is connected to the wiring XCL_i, and the gate of the transistor M4d is connected to the wiring VEB. The second terminal of the capacitance element C1d is connected to the wiring XCL_i.

[0177] For example, the wiring VEL functions as a wiring that applies a fixed potential. Specifically, the wiring VEL functions as a wiring that applies the fixed potential to the second terminals of the transistors M3 and M3d. In particular, the fixed potential is a potential at which the transistors M3 and M3d operate in the subthreshold region. Specifically, the potential may be a ground potential, a negative potential, or the like. Depending on the situation, the potential may be a positive potential, or the like. Alternatively, depending on the situation, the wiring VEL may function as a wiring that applies a variable potential such as a pulse potential (sometimes referred to as a pulse signal) or a clock potential (sometimes referred to as a clock signal) instead of a fixed potential.

[0178] For example, the wiring VEB functions as a wiring that applies a fixed potential. Note that the fixed potential can be, for example, a positive potential. As a result, the transistors M4 and M4d, which are clamp transistors, are turned on. Note that, depending on the situation, the fixed potential applied by the wiring VEB can be a ground potential, a negative potential, or the like. For example, the wiring VEB may also function as a wiring that applies a variable potential instead of a fixed potential.

[0179] In the computation cell IM[i,j] shown in FIG. 6A, if the effect of DIBL on the threshold voltage of transistor M3 is small, the computation cell IM[i,j] may be configured without transistor M4, as shown in FIG. 6B. Similarly, if the effect of DIBL on the threshold voltage of transistor M3d is small, the driver cell IM_i may be configured without transistor M4d, as shown in FIG. 6B. In this case, the circuit areas of the computation cell IM[i,j] and the driver cell IMD_i can be reduced, thereby increasing cell density. Furthermore, since there is no need to extend the wiring VEB to the cell array CA, the circuit area of ​​the computation device CDVA can also be reduced. Furthermore, power consumption required to apply a potential to the wiring VEB can be reduced.

[0180] An example of the operation of the computation cell IM[i,j] and the driving cell IMD_i will be described later.

[0181] <<Configuration Example of Driver Circuit ITS>> The driver circuit ITS is connected to the wirings WCL_1 to WCL_n and the wirings OL_1 to OL_n. For example, the driver circuit ITS has a function of calculating a function in which a value corresponding to the sum of analog currents transmitted from the wirings WCL_j is assigned as a variable, and outputting the result of the calculation to the wiring OL_j.

[0182] The driver circuit ITS shown in Fig. 1 can have, for example, the configuration shown in Fig. 7A. Wiring WCL_j and wiring OL_j are also shown in Fig. 7A to show the connection of the driver circuit ITS to peripheral circuits. Wiring SWLB for transmitting a control signal to the switch SB_j is also shown in Fig. 7A.

[0183] 7A can be applied to each of the circuits ITSa_1 to ITSa_n shown in Fig. 1. The switch SB_j shown in Fig. 7A is the switch arranged in the j-th column among the switches SB_1 to SB_n shown in Fig. 1.

[0184] 7A includes a circuit that performs an activation function calculation as a function system (e.g., a nonlinear function system) and an analog-to-digital conversion circuit, as described above. In particular, the circuit that performs the function system calculation preferably has a function of performing the function system calculation using, as an input value, a value corresponding to the amount of input current, and outputting digital data (e.g., a digital potential) corresponding to the result of the calculation.

[0185] 7A includes, for example, a circuit RL and an analog-to-digital converter circuit ATDC. The circuit RL also includes, for example, a terminal RTi and a terminal RTo.

[0186] A second terminal of the switch SB_j is connected to a terminal RTi of the circuit RL via an input terminal of the circuit ITSa_j. A terminal RTo of the circuit RL is connected to an input terminal of the analog-to-digital conversion circuit ATDC, and an output terminal of the analog-to-digital conversion circuit ATDC is connected to a wiring OL_j via an output terminal of the circuit ITSa.

[0187] The circuit RL may be a circuit that performs the calculation of the above-described function system. The function system may be an activation function used in an artificial neural network model. Examples of the activation function include nonlinear functions such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function. In the configuration of FIG. 7A, the circuit RL is preferably configured to output a potential from a terminal RTo.

[0188] The circuit RL may also be a current-voltage conversion circuit.

[0189] When the circuit RL is a current-voltage conversion circuit, it is preferable that the circuit RL is configured to generate an analog potential according to a current input to a terminal RTi of the circuit RL from the wiring WCL_j via the switch SB_j, and output the analog potential to a terminal RTo of the circuit RL.

[0190] The analog-to-digital converter circuit ATDC preferably converts an analog potential supplied from the terminal RTo of the circuit RL into a digital signal and outputs the digital signal to the wiring OL_j.

[0191] 7B shows a configuration example of the drive circuit ITS when the circuit RL is a current-voltage conversion circuit. The circuit RL shown in FIG. 7B includes, as an example, a load LE and an amplifier circuit OP.

[0192] The amplifier circuit OP has an inverting input terminal, a non-inverting input terminal, and an output terminal. For example, an operational amplifier or a differential amplifier circuit can be used as the amplifier circuit OP.

[0193] The inverting input terminal of the amplifier circuit OP is connected to the first terminal of the load LE and the second terminal of the switch SB_j. The non-inverting input terminal of the amplifier circuit OP is connected to the wiring VRL. The output terminal of the amplifier circuit OP is connected to the second terminal of the load LE and the terminal RTo.

[0194] The wiring VRL functions as a wiring that applies a fixed potential, which may be, for example, a ground potential (GND) or a low-level potential.

[0195] In particular, by setting the fixed potential provided by the wiring VRL to ground potential (GND), the inverting input terminal of the amplifier circuit OP becomes a virtual ground, and therefore the analog voltage output to the wiring OL_j can be a voltage based on ground potential (GND).

[0196] 7B, the drive circuit ITS can output to the terminal RTo an analog voltage corresponding to the amount of current flowing from the wiring WCL_j through the switch SB_j to the terminal RTi of the circuit RL. The analog voltage can be converted into a digital signal by the analog-to-digital converter ATDC and output to the wiring OL_j.

[0197] Note that when an analog voltage rather than a digital signal is output from the drive circuit ITS to the wiring OL_j, the circuit ITSa_j does not need to include an analog-digital conversion circuit ATDC, as shown in the drive circuit ITS in FIG. 7C . Also, in FIG. 7C , the circuit RL preferably performs a function calculation using a value corresponding to the amount of current flowing through the terminal RTi as an input value, and outputs the result of the calculation as an analog current to the terminal RTo. Furthermore, by passing the analog current resulting from the calculation output from the terminal RTo, for example, through the wiring XCL of another calculation device CDVA, another calculation can be performed using the result of the calculation. This corresponds to sending the result of the calculation to the next fully connected layer in a multilayer perceptron, a type of artificial neural network. By directly using the analog current resulting from the calculation in the next calculation, analog-to-digital conversion and digital-to-analog current conversion are not necessary, and the conversion circuits for these conversions can be omitted. This makes it possible to reduce the circuit area of ​​the arithmetic unit CDVA, and also to omit the conversion circuit, thereby reducing the power consumption of the arithmetic unit CDVA.

[0198] Next, a specific example of the configuration of the circuit RL included in the circuit ITSa_j in FIG. 7A or 7C will be described.

[0199] FIG. 8 is a circuit diagram showing, as an example, a specific configuration of the circuit RL included in the circuit ITSa_j of FIG. 7A or 7C, and the circuit RL of FIG. 8 has a function of performing the calculation of the ReLU function.

[0200] The circuit RL shown in FIG. 8 includes, as an example, transistors MP1i, MP1o, MP2i, MP2o, MP3i, MP3o, MP4i, MP4o, MN1i, MN1o, MN2i, MN2o, and a current source CNI.

[0201] Each of the n-channel transistors included in the circuit RL can be, for example, a transistor applicable to the n-channel transistor included in the circuit WCDa_j shown in Fig. 4. Each of the p-channel transistors included in the circuit RL can be, for example, a transistor applicable to the p-channel transistor included in the circuit WCDa_j shown in Fig. 4.

[0202] 8, a first current mirror circuit is formed by p-channel transistors MP1i, MP2i, MP1o, and MP2o, a second current mirror circuit is formed by n-channel transistors MN1i, MN2i, MN1o, and MN2o, and a third current mirror circuit is formed by p-channel transistors MP3i, MP4i, MP3o, and MP4o.

[0203] Furthermore, since the circuit RL includes a first current mirror circuit to a third current mirror circuit, the circuit RL is sometimes called a three-stage current mirror circuit.

[0204] The drain of transistor MP1i is connected to terminal RTi, the drain of transistor MP1o is connected to the input terminal of current source CNI and the drain of transistor MN2i. The drain of transistor MN2o is connected to the drain of transistor MP3i. Transistor MP3o is connected to terminal RTo of circuit RL. The output terminal of current source CNI is connected to wiring VGE.

[0205] For example, the wiring VGE functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a low-level potential, a negative potential, or a ground potential. Depending on the situation, the fixed potential applied by the wiring VGE can be a high-level potential, a positive potential, or the like. The wiring VGE may also function as a wiring that applies not only a fixed potential but also a variable potential such as a pulse potential or a clock potential.

[0206] The first current mirror circuit ideally has the function of passing a current between the source and drain of transistor MP2o that is equal to the source-drain current corresponding to the gate-source potential of transistor MP2i. Similarly, the second current mirror circuit ideally has the function of passing a current between the source and drain of transistor MN1o that is equal to the source-drain current corresponding to the gate-source potential of transistor MN1i. Similarly, the third current mirror circuit ideally has the function of passing a current between the source and drain of transistor NP4o that is equal to the source-drain current corresponding to the gate-source potential of transistor MP4i.

[0207] In the first current mirror circuit, transistor MP1i functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2i due to drain-induced barrier lowering. Similarly, transistor MP1o also functions as a clamp transistor to prevent a decrease in the threshold voltage of transistor MP2o due to drain-induced barrier lowering. Therefore, a wiring RSWL1 that applies a predetermined bias potential is connected to the gates of transistor MP1i and transistor MP1o.

[0208] In the second and third current mirror circuits, the transistors MN2i, MN2o, MP3i, and MP3o also function as clamp transistors to prevent a decrease in the threshold voltage of the series-connected transistors due to a drain-induced barrier lowering. In this case, the wirings RSWL2 and RSWL3 each function as wirings that apply a predetermined bias potential. Specifically, the wiring RSWL2 is connected to the gates of the transistors MN2i and MN2o, respectively, and the wiring RSWL3 is connected to the gates of the transistors MP3i and MP3o, respectively.

[0209] The bias potentials applied by the wirings RSWL1 to RSWL3 can be made equal to each other. Therefore, the wirings RSWL1 to RSWL3 can be the same wiring. The ratio of the bias potential applied by one selected from the wirings RSWL1 to RSWL3 to the bias potential applied by the remaining two is preferably 0.9 to 1.1, more preferably 0.95 to 1.05, and even more preferably 0.99 to 1.01.

[0210] Each of the transistors MP1i and MP1o can function as a switching transistor. In this case, the wiring RSWL1 preferably functions as a wiring for controlling the switching between the on state and the off state of each of the transistors MP1i and MP1o. Furthermore, by turning off each of the transistors MP1i and MP1o, the first current mirror circuit can be stopped, thereby reducing power consumption in the circuit RL.

[0211] Similarly, since the transistors MN2i and MN2o each function as a switching transistor, the second current mirror circuit can be stopped at a desired timing. In this case, it is preferable that the wiring RSWL2 function as a wiring for controlling the switching between the on state and the off state of the transistors MN2i and MN2o. Similarly, since the transistors MP3i and MP3o each function as a switching transistor, the third current mirror circuit can be stopped at a desired timing. In this case, it is preferable that the wiring RSWL3 function as a wiring for controlling the switching between the on state and the off state of the transistors MP3i and MP3o.

[0212] Note that the transistors MP1i and MP1o, and the transistors MP3i and MP3o can be simultaneously turned on or off, respectively. Therefore, the wiring RSWL1 and the wiring RSWL3 can be the same wiring.

[0213] In the first current mirror circuit, the source of transistor MP2i and the source of transistor MP2o are each connected to a wiring VDDL. Since the first current mirror circuit is composed of p-channel transistors, it also functions as a current source circuit. Therefore, the wiring VDDL functions as a wiring that provides a high-level potential as a high power supply potential for the first current mirror circuit. In addition, in the first current mirror circuit, the gates of transistor MP2i and transistor MP2o are each connected to a terminal RTi.

[0214] Similarly, the third current mirror circuit also functions as a current source circuit, and therefore the high-level potential provided by the wiring VDDL also functions as a high power supply potential for the third current mirror circuit. In the third current mirror circuit, the drains of the transistors MP3i and MN2o are connected to the gates of the transistors MP4i and MP4o, respectively.

[0215] In the second current mirror circuit, the source of transistor MN1i and the source of transistor MN1o are connected to a wiring VSSL, respectively. Because the second current mirror circuit is configured with n-channel transistors, it also functions as a current sink circuit. Therefore, the wiring VSSL functions as a wiring that provides a low-level potential as the low power supply potential of the second current mirror circuit. In the second current mirror circuit, the drain of transistor MN2i, the drain of transistor MP1o, and the input terminal of current source CNI are connected to the gates of transistors MN1i and MN1o, respectively.

[0216] The current source CNI is, for example, a quantity I ＩＢ The current flows from the drains of the transistors MP1o and MN2i to the wiring VGE.

[0217] When a high-level potential is applied to the wiring SWLB, the high-level potential is applied to the control terminal of the switch SB, and the switch SB_j is turned on. At this time, the wiring WCL_j is supplied with an amount I ＩＬ Therefore, a current of the amount I flows from the wiring VDDL to the wiring WCL_j. ＩＬ Therefore, the amount of the source-drain current of the transistor MP2o is also I ＩＬ This becomes:

[0218] Also, when the current source CNI is operating, I ＩＬ =I ＩＢ +I ＯＬ is established. Note that I ＯＬ is the amount of current flowing between the source and drain of the transistor MN1i. Therefore, the amount of source-drain current of the transistor MN1o is also I ＯＬ This becomes:

[0219] The amount of source-drain current of the transistor MN1o is also I ＯＬTherefore, the amount of source-drain current of the transistor MP4i is also I ＯＬ Therefore, the amount of source-drain current of the transistor MP4o is also I ＯＬ and the terminal RTo is charged with the quantity I ＯＬ A current of flows.

[0220] The circuit RL is I ＩＬ Ga I Ｂ If it is greater than , the difference is the amount I ＯＬ A current of I flows through the terminal RTo. ＩＬ Ga I Ｂ When the following condition is satisfied, the current flowing between the input terminal and the output terminal of the current source CNI is I ＩＬ And also, I ＯＬ = 0. In this case, no current flows from the terminal RTo of the circuit RL. In other words, the circuit RL shown in FIG. 8 can perform the calculation of the ReLU function.

[0221] <Operation Example 1 of Arithmetic Circuit> Next, an operation example of the arithmetic device CDVA of FIG. 1 will be described.

[0222] First, first data, which is digital data, is input from outside the arithmetic device CDVA to the wirings IWL_1 to IWL_n.

[0223] 1, the voltage generator circuit RSTR is the voltage generator circuit RSTR shown in any one of FIGS. 2, 3A, and 3B, and the circuit WCDa_j included in the driver circuit WCD is the driver circuit WCD shown in FIG. 4. In this case, the circuit WCDa_j selects one of the terminals VIT_0 to VIT_255 in accordance with the first data w[i, j], which is digital data transmitted to the wiring IWL_j, and conduction is established between the selected terminal VIT and the output terminal. As a result, a potential output from one of the terminals VOT_0 to VOT_255 of the voltage generator circuit RSTR reaches the output terminal of the circuit WCDa_j, and the potential is applied to the gate of the transistor FW_j. Since a high-level potential is applied as a fixed potential from the wiring VEH to the first terminal of the transistor FW_j, a current according to the potential of the gate of the transistor FW_j, in other words, an analog current of an amount according to the first data w[i, j] transmitted to the wiring IWL_j flows between the source and drain of the transistor FW_j. Here, the amount of analog current according to the first data w is expressed as w[i, j]I Ｗｕｔ Also, I Ｗｕｔ is the amount of current that flows when w[i, j]=1.

[0224] Furthermore, when a high-level potential is applied to the wiring SWLA, the switch SA_j of the circuit SWCA is turned on. At this time, an analog current corresponding to the digital data that flows between the source and drain of the transistor FW_j flows to the wiring WCL_j.

[0225] In addition, in the calculation device CDVA of FIG. 1, as an example, the drive circuit WSD selects the i-th row in the cell array CA, and the calculation cell IM[i, j] receives the amount w[i, j]I corresponding to the first data w[i, j] from the wiring WCL_j. Ｗｕｔ Specifically, when a high-level potential is applied from the driver circuit WSD to the wiring WSL_i to turn on the transistor M1, the gate of the transistor M3 and the first terminal thereof are brought into a conductive state, and the potential of the gate of the transistor M3 is such that the amount of the source-drain current of the transistor M3 is w[i, j]I. ＷｕｔHere, by holding the potential of the gate of the transistor M3 of the processing cell IM[i, j], the amount of the current w[i, j]I flowing between the source and drain of the transistor M3 is determined as follows: Ｗｕｔ As a result, w[i,j] is written as the first data into the calculation cell IM[i,j].

[0226] Furthermore, in the above, the amount w[i,j]I according to the first data is transmitted from the wiring WCL_j to the operation cell IM[i,j]. Ｗｕｔ While the current flows, the driving circuit XCD supplies the wiring XCL_i with a current of an amount r[i]I according to the reference data r[i]. Ｘｕｔ Specifically, when a high-level potential is applied from the drive circuit WSD to the wiring WSL_i to turn on the transistor M1d, the gate of the transistor M3d and the first terminal are brought into a conductive state, and the gate potential of the transistor M3d is maintained when the amount of the source-drain current of the transistor M3d is equal to or greater than r[i]I. Ｘｕｔ As a result, the amount of current flowing between the source and drain of the transistor M3d of the driving cell IMD_i is determined as r[i]I Ｘｕｔ The amount of current to the driving cell IMD_i of the cell array CA is set together with the amount of current to the calculation cell IM[i, j].

[0227] The quantity r[i]I corresponding to the reference data r[i] ＸｕｔThe current is generated by a circuit XCDa_i and a transistor FX_i included in the driver circuit XCD. For example, the circuit XCDa_i included in the driver circuit XCD is the driver circuit XCD shown in FIG. 4 . At this time, the circuit XCDa_i selects one of the terminals VIT_0 to VIT_255 in accordance with reference data r[i], which is digital data transmitted to the wiring IXL_i, and conduction is established between the selected terminal VIT and the output terminal. As a result, a potential output from one of the terminals VOT_0 to VOT_255 of the voltage generation circuit RSTR reaches the output terminal of the circuit XCDa_i, and the potential is applied to the gate of the transistor FX_i. Since a high-level potential is applied as a fixed potential from the wiring VEH to the first terminal of the transistor FX_i, a current corresponding to the potential of the gate of the transistor FX_i flows between the source and drain of the transistor FX_i, in other words, an amount r[i]I corresponding to the reference data r[i] transmitted to the wiring IXL_i. Ｘｕｔ An analog current of I flows. Ｘｕｔ is the amount of current that flows when r[i]=1.

[0228] From the above, the amount of current I flowing through the transistor M3 of the processing cell IM[i, j] is Ｍ３ [i, j] is as shown in the following formula (1.1). In addition, the amount of current I Ｍ３ｄ [i] is as shown in the following formula (1.2).

[0229]

[0230] Also, I Ｗｕｔ is the amount of current in the subthreshold region of the transistor FW_j, and I Ｘｕｔ is the amount of current in the subthreshold region of the transistor FX_i. Ｗｕｔ and I Ｘｕｔ are explained as equal currents, and each is I ｕｔ In this case, w[i, j]I in formula (1.1) Ｗｕｔ is written as in the following formula (1.3), and r[i]I in formula (1.2) Ｘｕｔcan be written as equation (1.4) below.

[0231]

[0232] In addition, V ｇ (w[i,j]) is the gate-source voltage of transistor M3 when calculation cell IM[i,j] holds w[i,j], and V ｔｈ is the threshold voltage of the transistor M3 of the calculation cell IM[i, j]. ｇｍ (r[i]) is the gate-source voltage of the transistor M3d when the driving cell IMD_i holds r[i], and V ｔｈｍ is the threshold voltage of the transistor M3d of the driving cell IMD_i. ａ is V ｇ (w[i,j])=V ｔｈ When w[i, j]I ｕｔ is the amount of current, and J is a correction coefficient determined by temperature, device structure, etc. ａ is V ｇｍ (r[i]) = V ｔｈｍ When r[i]I ｕｔ The current amount is I in equation (1.3). ａ Furthermore, J in equation (1.4) is a correction coefficient determined by temperature, device structure, etc., similar to equation (1.3), and is equal to J in equation (1.3).

[0233] Next, second data x[i], which is digital data, is input to the wiring IXL_i from outside the arithmetic device CDVA. Specifically, the digital data provided to the wiring IXL_i changes from reference data r[i] to second data x[i].

[0234] The quantity x[i]I according to the second data x[i] ｕｔThe current is generated by a circuit XCDa_i and a transistor FX_i included in the driver circuit XCD. For example, the circuit XCDa_i selects one of the terminals VIT_0 to VIT_255 in accordance with the second data x[i], which is digital data transmitted to the wiring IXL_i, and conduction is established between the selected terminal VIT and the output terminal. As a result, a potential output from one of the terminals VOT_0 to VOT_255 of the voltage generation circuit RSTR reaches the output terminal of the circuit XCDa_i, and the potential is applied to the gate of the transistor FX_i. Therefore, a current of an amount x[i]I corresponding to the second data x[i] transmitted to the wiring IXL_i is generated between the source and drain of the transistor FX_i. ｕｔ An analog current of flows.

[0235] The potential of the wiring XCL_i is determined according to the amount of current flowing through the wiring. When the potential of the wiring XCL_i changes, the potential of the gate of the transistor M3d of the driving cell IMD_i also changes due to capacitive coupling in the capacitive element C1d. Here, when the gate-source voltage of the transistor M3d is V ｇｍ (r[i]) to V ｇｍ (x[i]). At this time, the amount of current I flowing between the source and drain of the transistor M3d of the driving cell IMD_i is Ｍ３ｄ [i] changes from equation (1.2) as shown in equation (1.5) below.

[0236]

[0237] Furthermore, when the potential of the wiring XCL_i changes, the potential of the gate of the transistor M3 of the processing cell IM[i, j] also changes due to capacitive coupling in the capacitor C1. Note that the amount of change in the potential of the wiring XCL_i is V ｇｍ (x[i])-V ｇｍ (r[i]), the change in the gate potential of the transistor M3 is also V ｇｍ (x[i])-V ｇｍ (r[i]). At this time, the amount of current I flowing between the source and drain of the transistor M3 is Ｍ３ [i] changes from equation (1.1) as shown in equation (1.6) below.

[0238]

[0239] Here, equation (1.6) can be rewritten as equation (1.7) below by using equations (1.3) to (1.5).

[0240]

[0241] As shown in equation (1.7), the amount of current I flowing between the source and drain of transistor M3 Ｍ３ is proportional to the product of the first data w[i,j] and the second data x[i], and inversely proportional to the reference data r[i]. In particular, by setting the reference data r[i] to 1, the first data w[i,j] and the second data x[i] can be multiplied.

[0242] 1, by setting the reference data r to a positive number other than 0, it is possible to perform division using r[i] as the divisor and w[i,j]x[i] as the dividend. In other words, it is possible to multiply w[i,j] by x[i] / r[i]. In other words, the arithmetic cell IM[i,j] of the arithmetic device CDVA can output, as a current, the result of multiplying the ratio of the second data x[i] to the reference data r[i] by the first data w[i,j].

[0243] When multiplication of w[i,j] and x[i] / r[i] is assumed in the calculation device CDVA, the second data x[i] is a ratio of the reference data r[i], so it can be said that the calculation device CDVA can handle values ​​that can be input as the second data with a higher resolution. Also, when multiplication of w[i,j] / r[i] and x[i] is assumed, the first data w[i,j] is a ratio of the reference data r[i], so it can be said that the calculation device CDVA can handle values ​​that can be input as the first data with a higher resolution.

[0244] In this operation example, for the sake of simplicity, the capacitive coupling coefficient of the capacitive element C1 and the capacitive element C1d is set to 1.

[0245] 1 is the same as the driver circuit ITS shown in FIG. 7A. At this time, a low-level potential is applied to the wiring SWLA to turn off the switches SA_1 to SA_n of the circuit SWCA included in the driver circuit WCD, and a high-level potential is applied to the wiring SWLB to turn on the switches SB_1 to SB_n of the circuit SWCB included in the driver circuit ITS. A quantity I given by equation (1.7) is applied between the arithmetic cell IM[i, j] and the circuit ITSa_j. Ｍ３ A current of [i, j] flows.

[0246] In the above, attention was focused on the calculation cell IM[i, j] in the i-th row of the cell array CA, but here, the calculation cells IM in the 1st row to the Mth row arranged in the j-th column of the cell array CA are also respectively I Ｍ３ [1,j] to I Ｍ３ At this time, the sum of the amounts of current flowing through the operation cells IM[1,j] to IM[m,j] in the j-th column of the cell array CA is input to the circuit ITSa_j. Therefore, the amount of current input to the circuit ITSa_j is expressed as I ＳＵＭ When [j] is set, I ＳＵＭ [j] is as shown in the following equation (1.8).

[0247]

[0248] That is, when r[i] is a positive real number independent of i, the amount of current I flowing through the circuit ITSa_j is ＳＵＭ [j] is determined according to the result of multiplying and accumulating the first data and the second data.

[0249] In the circuit ITSa_j of FIG. 7A, the terminal RTi_j of the circuit RL_j receives the result of the sum of products I ＳＵＭ [j] is input. As a result, the circuit RL_j receives I ＳＵＭ For example, the function I, which is used for the calculation of the circuit ITSa_j, is used as an input value. ＳＵＭ The function with [j] as input value is F(I ＳＵＭ[j]) and the result of the calculation is z, z can be expressed as in equation (1.9) below.

[0250]

[0251] Furthermore, the circuit RL_j outputs the calculation result of the function system as an analog potential to the terminal RTo_j, and inputs it to an analog-to-digital converter (ADC). The analog-to-digital converter converts the analog potential into digital data. The digital data is output to the outside via the wiring OL_j. This allows the arithmetic unit CDVA to perform a product-sum operation and a function operation.

[0252] In particular, the arithmetic unit CDVA is suitable for performing calculations on a fully connected layer neural network. For example, by storing a weight coefficient as first data in the arithmetic cell IM of the cell array CA of the arithmetic unit CDVA and inputting the value of the neuron's input signal as second data to the wiring XCL, a product-sum operation can be performed on the weight coefficient and the neuron's input signal. Furthermore, by configuring the circuit ITSa_j as an operation circuit for an activation function adopted in the fully connected layer neural network, the value of the activation function can be output using the result of the product-sum operation as an input value. This value can then be input to the next hidden layer, output layer, etc.

[0253] When the processing of the fully connected layer is performed by analog calculation using the calculation device CDVA, a subthreshold current flows through the transistor M3 of each of the calculation cells IM[1,1] to IM[m,n] included in the cell array CA, which reduces the power consumption per calculation cell IM and increases the calculation efficiency per area.

[0254] Furthermore, by using the arithmetic unit CDVA, the input / output characteristics of the voltage generation circuit RSTR, the circuit WCDa_j, and the transistor FW_j in the conversion from digital data to analog current are improved, thereby suppressing variations in the analog current generated according to the first data. Similarly, the input / output characteristics of the voltage generation circuit RSTR, the circuit XCDa_i, and the transistor FX_i in the conversion from digital data to analog current are also improved, thereby suppressing variations in the analog current generated according to the reference data and the second data. This suppresses variations in the results of the calculations performed by the arithmetic unit CDVA and increases the accuracy rate of inferences using the artificial neural network.

[0255] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0256] Embodiment 2 In this embodiment, a semiconductor device according to one embodiment of the present invention, which is different from that in Embodiment 1, will be described.

[0257] <Configuration Example 2 of Semiconductor Device> FIG. 9 is a block diagram illustrating a configuration example of an arithmetic device that is a semiconductor device according to one embodiment of the present invention. As an example, the arithmetic device has a function of calculating a sum of products of a plurality of first data and a plurality of second data, similar to the arithmetic device CDVA of FIG. 1 described in Embodiment 1, and a function of calculating a function into which the result of the sum of products is assigned as a variable. Furthermore, the arithmetic device has a function of performing calculations of a hierarchical neural network, similar to the arithmetic device CDVA of FIG. 1. The arithmetic device CDVB of FIG. 9 differs from the arithmetic device CDVA of FIG. 1 in that it can handle not only positive numbers and 0 but also negative numbers as the first data.

[0258] The arithmetic device CDVB shown in FIG. 9 includes, as an example, a cell array CA, a drive circuit WCD, a drive circuit XCD, a drive circuit WSD, and a drive circuit ITS.

[0259] Hereinafter, in the description of the arithmetic device CDVB shown in Fig. 9, the description will be focused on the parts that are different from the arithmetic device CDVA in Fig. 1. Also, for some circuits included in the arithmetic device CDVB in Fig. 9, the description of some circuits included in the arithmetic device CDVA in Fig. 1 can be referred to.

[0260] <<Cell Array CA>> The cell array CA of the arithmetic device CDVB shown in Fig. 9 has arithmetic cells IMp, IMn, and driver cells IMD. In this embodiment, for convenience, arithmetic cells IMp and IMn are collectively referred to as arithmetic cells IM. Like the arithmetic cell IM shown in Fig. 1, the arithmetic cells IMp and IMn in Fig. 9 have the function of multiplying first data by second data, and the driver cell IMD in Fig. 9 has the function of holding reference data, like the driver cell IMD shown in Fig. 1.

[0261] In the cell array CA of the arithmetic device CDVB of Fig. 9, the arithmetic cells IM are arranged in a matrix of m rows and n columns (m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1), similar to the cell array CA of the arithmetic device CDVA of Fig. 1. In other words, when the arithmetic cells IMp and IMn are combined, the arithmetic cells IMp and IMn are arranged in a matrix of m rows and 2n columns. Furthermore, the driving cells IMD in the cell array CA of Fig. 9 are arranged in each row, similar to the driving cells IMD in the cell array CA of Fig. 1.

[0262] As described above, the calculation unit CDVB is different from the calculation unit CDVA in Fig. 1 in that it can perform calculations with the first data as a positive or negative number, or 0. When calculations are performed by the calculation unit CDVB, the first data w input to the calculation unit CDVB is first input to the calculation unit CDVB using two parameters w ｐ And lol ｎ Specifically, when the first data w is positive (w ｐ , w ｎ ) = (w, 0), and when w is negative, (w ｐ , wｎ ) = (0, -w), and when w is 0, (w ｐ , w ｎ ) = (0,0).

[0263] Also, w ｐ is stored in the calculation cell IMp, and w ｎ is stored in the operation cell IMn. That is, in the operation device CDVB of FIG. 9, the first data w is stored in the operation cell IM. ｐ And lol ｎ and are maintained.

[0264] The circuit configurations of the operation cells IMp and IMn will be described later.

[0265] In addition, in the cell array CA of the arithmetic device CDVB, wirings WCLp_1 to WCLp_n and wirings WCLn_1 to WCLn_n extend in the column direction, and wirings XCL_1 to XCL_m, wirings WSLp_1 to WSLp_m, and wirings WSLn_1 to WSLn_m extend in the row direction.

[0266] Note that FIG. 9 shows only wiring WCLp_j (j is an integer greater than or equal to 1 and less than or equal to n), wiring WCLn_j, wiring XCL_1, wiring XCL_m, wiring WSLp_1, wiring WSLp_m, wiring WSLn_1, and wiring WSLn_m.

[0267] 9 includes a circuit WCDpn_j and a circuit SWCA. The circuit SWCA includes a switch SAp_j and a switch SAn_j. Note that the switches SAp_j and SAn_j may be the same as those applicable to the switch SA described in the above embodiment.

[0268] A first terminal of the switch SAp_j and a first terminal of the switch SAn_j are connected to an output terminal of the circuit WCDpn_j. A second terminal of the switch SAp_j is connected to a wiring WCLp_j, and a second terminal of the switch SAn_j is connected to a wiring WCLn_j. A control terminal of the switch SAp_j is connected to a wiring SWLAp, and a control terminal of the switch SAn_j is connected to a wiring SWLAn. An input terminal of the circuit WCDpn_j is connected to a wiring IWL_j.

[0269] 9 can have the configuration shown in FIG. 10A. Note that in FIG. 10A, wirings SWLAp, SWLAn, IWL_j, WCLp_j, and WCLn_j are also shown to show the connection of the driver circuit WCD with peripheral circuits. For convenience, the switches SAp_j and SAn_j are included in the circuit SWCA, and the circuit SWCA is included in the driver circuit WCD.

[0270] The circuit WCDpn_j is ｐ Or w ｎ In the case of the arithmetic device CDVB in FIG. 9, the signal is a current. ｐ Or w ｎ It is preferable that the current generating circuit is a digital potential-to-analog current converting circuit (IDAC). ｐ Or w ｎ is transmitted to the wiring IWL_j as digital data.

[0271] 10A includes a switch SWW, as an example. A first terminal of the switch SWW is connected to a first terminal of the switch SAp_j and a first terminal of the switch SAn_j, and a second terminal of the switch SWW is connected to a wiring VINI1. The wiring VINI1 functions as a wiring that applies an initialization potential to the wiring WCLp_j and the wiring WCLn_j. The initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. Note that the switch SWW is turned on only when the initialization potential is applied to the wiring WCLp_j and the wiring WCLn_j, and is turned off otherwise.

[0272] The switch SWW may be, for example, a switch that can be applied to the switch SA described in the above embodiment.

[0273] 10A includes a plurality of current sources CS. Ｋ In this case, the circuit WCDpn_j has a function of outputting the first data w of 2 Ｋ The circuit WCDpn_j has, for example, one current source CS that outputs information corresponding to the value of the 0th bit as a current, two current sources CS that output information corresponding to the value of the 1st bit as a current, and two current sources CS that output information corresponding to the value of the (K-1)th bit as a current. Ｋ−１ There are individual ones.

[0274] 10A, each current source CS has a terminal T1 and a terminal T2. The terminal T1 of each current source CS is connected to a first terminal of a switch SAp_j and a first terminal of a switch SAn_j included in the circuit SWCA. The terminal T2 of one current source CS is connected to a wiring DW[0], and the terminals T2 of two current sources CS are connected to a wiring DW[1]. Ｋ−１ Each of the terminals T2 of the current sources CS is connected to a wiring DW[K-1].

[0275] In particular, the wirings DW[0] to DW[K-1] can be the wiring IWL_j shown in Fig. 9. That is, the wiring IWL_j can be a wiring group including the wirings DW[0] to DW[K-1].

[0276] The multiple current sources CS included in the circuit WCDpn_j each have the same amount I Ｗｕｔ from terminal T1. In reality, during the manufacturing stage of the arithmetic device CDVB, errors may occur due to variations in the electrical characteristics of the transistors included in each current source CS. This may also cause the result of the calculation in the arithmetic device CDVB to deviate from the expected result. One of the purposes of the arithmetic device CDVB, which is a semiconductor device described in this embodiment, is to solve this problem. Note that the error here is, as an example, the amount I of the constant current output from the terminal of the current source CS. Ｗｕｔ and the output current read from the ideal input / output characteristics.

[0277] The wiring DW[0] to the wiring DW[K-1] receive the quantity I from the connected current source CS. Ｗｕｔ The wiring DW[0] functions as a wiring for transmitting a control signal for outputting a constant current of I. This allows the circuit WCDpn_j to flow a current of an amount corresponding to K-bit data transmitted from the wirings DW[0] to DW[K-1] to the wiring WCLp_j or the wiring WCLn_j. Specifically, for example, when a high-level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] outputs a constant current I Ｗｕｔ flows through the circuit SWCA, and when a low level potential is applied to the wiring DW[0], the current source CS connected to the wiring DW[0] is Ｗｕｔ For example, when a high-level potential is applied to the wiring DW[1], the two current sources CS connected to the wiring DW[1] output a total of 2I Ｗｕｔ When a constant current of 2I flows through the circuit SWCA and a low level potential is applied to the wiring DW[1], the current source CS connected to the wiring DW[1] has a total of 2I ＷｕｔFor example, when a high-level potential is applied to the wiring DW[K-1], the constant current of the second Ｋ−１ The current sources CS are a total of 2 Ｋ−１ I Ｗｕｔ When a constant current of 100 kJ flows through the circuit SWCA and a low-level potential is applied to the wiring DW[K-1], the current source CS connected to the wiring DW[K-1] has a total of 2 Ｋ−１ I Ｗｕｔ It does not output a constant current.

[0278] The current flowing from one current source CS connected to the wiring DW[0] corresponds to the value of the 0th bit, the current flowing from two current sources CS connected to the wiring DW[1] corresponds to the value of the 1st bit, and the amount of current flowing from K current sources CS connected to the wiring DW[K-1] corresponds to the value of the (K-1)th bit. Here, consider the circuit WCDpn_j when K is 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high-level potential is applied to the wiring DW[0] and a low-level potential is applied to the wiring DW[1]. At this time, a constant current I is supplied from the circuit WCDpn_j to the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "1", a low-level potential is applied to the wiring DW[0] and a high-level potential is applied to the wiring DW[1]. At this time, a constant current of 2I flows from the circuit WCDpn_j to the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "1" and the value of the 1st bit is "1", a high-level potential is applied to the wiring DW[0] and the wiring DW[1]. At this time, a constant current of 3I flows from the circuit WCDpn_j to the circuit SWCA. Ｗｕｔ Furthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DW[0] and the wiring DW[1]. At this time, no constant current flows from the circuit WCDa to the circuit SWCA.

[0279] 10A illustrates the circuit WCDpn_j when K is an integer equal to or greater than 3, but when K is 1, it is preferable that the circuit WCDpn_j in FIG. 10A does not include a current source CS connected to the wirings DW[1] to DW[K-1]. When K is 2, it is preferable that the circuit WCDpn_j in FIG. 10A does not include a current source CS connected to the wirings DW[2] to DW[K-1].

[0280] Next, a specific example of the configuration of the current source CS will be described.

[0281] The current source CS1 shown in FIG. 11A is a circuit that can be applied to the current source CS included in the circuit WCDpn_j in FIG. 10A, and the current source CS1 has a transistor Tr1 and a transistor Tr2.

[0282] A first terminal of the transistor Tr1 is connected to the wiring VEH, a second terminal of the transistor Tr1 is connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2, a second terminal of the transistor Tr2 is connected to the back gate of the transistor Tr2 and the terminal T1, and the gate of the transistor Tr2 is connected to the terminal T2, which is also connected to the wiring DW.

[0283] The wiring DW is any one of the wirings DW[0] to DW[K-1] in FIG. 10A.

[0284] The wiring VEH functions as a wiring that applies a fixed potential. The fixed potential can be, for example, a high-level potential.

[0285] When the fixed potential applied by the wiring VEH is set to a high-level potential, the high-level potential is input to the first terminal of the transistor Tr1. The potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. In this case, the first terminal of the transistor Tr1 functions as a drain, and the second terminal of the transistor Tr1 functions as a source. Since the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are connected, the gate-source voltage of the transistor Tr1 is 0 V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (source-drain current) in the subthreshold region flows between the first terminal and the second terminal of the transistor Tr1. When the transistor Tr1 is an OS transistor, the amount of the current is, for example, 1.0×10 −８ A or less, and 1.0 × 10 −１２ A or less is more preferable, and 1.0 × 10 −１５ It is more preferable that the current is equal to or less than 1 A. Furthermore, for example, it is more preferable that the current is in a range in which it increases exponentially with respect to the gate-source voltage. In other words, the transistor Tr1 functions as a current source for supplying a current in the subthreshold region. Note that the current is the above-mentioned I Ｗｕｔ , or I described below Ｘｕｔ It can be said that:

[0286] The transistor Tr2 functions as a switching transistor. When the potential of the first terminal of the transistor Tr2 is higher than the potential of the second terminal of the transistor Tr2, the first terminal of the transistor Tr2 functions as a drain, and the second terminal of the transistor Tr2 functions as a source. The back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are connected to each other, so the back gate-source voltage is 0 V. Therefore, when the threshold voltage of the transistor Tr2 is appropriate, the transistor Tr2 is turned on when a high-level potential is input to the gate of the transistor Tr2, and is turned off when a low-level potential is input to the gate of the transistor Tr2. Specifically, when the transistor Tr2 is on, the current in the subthreshold region described above flows from the second terminal of the transistor Tr1 to the terminal T1. When the transistor Tr2 is off, the current does not flow from the second terminal of the transistor Tr1 to the terminal T1.

[0287] Note that a circuit applicable to the current source CS included in the circuit WCDa of FIG. 10A is not limited to the current source CS1 of FIG. 11A. For example, while the current source CS1 is configured such that the back gate of transistor Tr2 is connected to the second terminal of transistor Tr2, the back gate of transistor Tr2 may be connected to a separate wiring. An example of such a configuration is shown in FIG. 11B. In the current source CS2 shown in FIG. 11B, the back gate of transistor Tr2 is connected to wiring VTHL. By connecting wiring VTHL to an external circuit or the like, the current source CS2 can apply a predetermined potential to wiring VTHL via the external circuit, thereby applying the predetermined potential to the back gate of transistor Tr2. This allows the threshold voltage of transistor Tr2 to be varied. In particular, increasing the threshold voltage of transistor Tr2 can reduce the off-state current of transistor Tr2.

[0288] Further, for example, the current source CS1 has a configuration in which the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are connected, but a configuration in which the voltage is held by a capacitor between the back gate and the second terminal of the transistor Tr2 may be adopted. Such a configuration example is shown in FIG. 11C. The current source CS3 shown in FIG. 11C includes a transistor Tr3 and a capacitor element C6 in addition to the transistor Tr1 and the transistor Tr2. The current source CS3 is different from the current source CS1 in that the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 are connected via the capacitor element C6, and the back gate of the transistor Tr1 and the first terminal of the transistor Tr3 are connected. Also, the current source CS3 has a configuration in which the second terminal of the transistor Tr3 is connected to the wiring VTL and the gate of the transistor Tr3 is connected to the wiring VWL. The current source CS3 can make the connection between the wiring VTL and the back gate of the transistor Tr1 conductive by applying a high-level potential to the wiring VWL to turn on the transistor Tr3. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. Then, by applying a low-level potential to the wiring VWL to turn off the transistor Tr3, the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be held by the capacitor element C6. That is, by determining the potential applied by the wiring VTL to the back gate of the transistor Tr1, the threshold voltage of the transistor Tr1 can be varied, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor element C6.

[0289] Further, for example, as a circuit applicable to the current source CS included in the circuit WCDpn_j of FIG. 10(A), the current source CS4 shown in FIG. 11(D) may be used. The current source CS4 has a configuration in which the back gate of the transistor Tr2 is connected to the wiring VTHL instead of the second terminal of the transistor Tr2 in the current source CS3 of FIG. 11(C). That is, similar to the current source CS2 of FIG. 11(B), the current source CS4 can vary the threshold voltage of the transistor Tr2 according to the potential applied by the wiring VTHL.

[0290] In the current source CS4, when a large current flows between the first and second terminals of the transistor Tr1, it is necessary to increase the on-current of the transistor Tr2 in order to pass the current from the terminal T1 to the outside of the current source CS4. In this case, the current source CS4 applies a high-level potential to the wiring VTHL to lower the threshold voltage of the transistor Tr2 and increase the on-current of the transistor Tr2, thereby allowing the large current flowing between the first and second terminals of the transistor Tr1 to flow from the terminal T1 to the outside of the current source CS4.

[0291] 11A to 11D as the current source CS included in the circuit WCDpn_j of Fig. 10A, the circuit WCDpn_j can output a current corresponding to the K-bit first data. Furthermore, the amount of the current can be, for example, the amount of current in the subthreshold region flowing between the first terminal and the second terminal of the transistor M3p included in the operation cell IMp[i,j] and the transistor M3n included in the operation cell IMn[i,j].

[0292] 10B may be used as the circuit WCDpn_j of Fig. 10A. The circuit WCDpn_j of Fig. 10B has a configuration in which the current source CS of Fig. 11A is connected to each of the wirings DW[0] to DW[K-1]. When the channel width of the transistor Tr1[0] is d[0], the channel width of the transistor Tr1[1] is d[1], and the channel width of the transistor Tr1[K-1] is d[K-1], the ratio of the channel widths is d[0]:d[1]:d[K-1]=1:2:2. Ｋ−１ Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the circuit WCDpn_j shown in FIG. 10B can output a current corresponding to the K-bit first data w, similar to the circuit WCDpn_j in FIG. 10A.

[0293] Note that the transistors Tr1 (including transistors Tr1[0] to Tr1[K-1]), Tr2 (including transistors Tr2[0] to Tr2[K-1]), and Tr3 can be, for example, transistors that can be used as the transistors M1, M3, or M4 described in the above embodiments. For example, OS transistors are preferably used as the transistors Tr1 (transistors Tr1[0] to Tr1[K-1]), Tr2 (transistors Tr2[0] to Tr2[K-1]), and Tr3. In particular, IO transistors can be used as a type of OS transistor.

[0294] In particular, the circuits shown in FIGS. 10A and 10B are sometimes called K-bit current ladder type DACs (Digital to Analog Converters), which are a type of digital potential-analog current conversion circuit.

[0295] 10B may be changed to a CMOS circuit including n-channel transistors and p-channel transistors. For example, the circuit WCDpn_j in FIG. 10A may be changed to a circuit configuration shown in FIG.

[0296] The circuit WCDpn_j shown in Figure 12 has a circuit configuration including n-channel transistors and p-channel transistors, and is an example of a configuration of a K-bit current-type ladder DAC. The circuit WCDpn_j has K current sources CS and a current mirror circuit CRM. The current source CS shown in Figure 12 differs from each of the current sources CS1 to CS4 shown in Figures 11A to 11D in terms of connection configuration.

[0297] Next, each current source CS shown in FIG. 12 will be described.

[0298] A first terminal of the transistor Tr1[0] is electrically connected to the wiring VSSL, a second terminal of the transistor Tr1[0] is connected to the first terminal of the transistor Tr2[0], and a gate of the transistor Tr1[0] is connected to the wiring BIS. Also, a gate of the transistor Tr2[0] is connected to the wiring DW[0].

[0299] Similarly, a first terminal of the transistor Tr1[1] is connected to the wiring VSSL, a second terminal of the transistor Tr1[1] is connected to the first terminal of the transistor Tr2[1], and a gate of the transistor Tr1[1] is connected to the wiring BIS. Also, a gate of the transistor Tr2[1] is connected to the wiring DW[1].

[0300] Similarly, a first terminal of the transistor Tr1[K-1] is connected to the wiring VSSL, a second terminal of the transistor Tr1[K-1] is connected to the first terminal of the transistor Tr2[K-1], and a gate of the transistor Tr1[K-1] is connected to the wiring BIS. Also, a gate of the transistor Tr2[K-1] is connected to the wiring DW[K-1].

[0301] Further, second terminals of the transistors Tr2[0] to Tr2[K-1] are connected to a terminal CTi of a current mirror circuit CRM, which will be described later.

[0302] 12, the channel widths of the transistors Tr1[0] to Tr1[K-1] can be determined by referring to the description of the transistors Tr1[0] to Tr1[K-1] in FIG. 10B.

[0303] 12, the transistors Tr2[0] to Tr2[K-1] function as transistors capable of adjusting the amount of current flowing between the source and drain of each of the transistors Tr1[0] to Tr1[K-1]. Therefore, the wiring BIS functions as a wiring that applies a fixed potential. Note that the fixed potential may be a high-level potential, a positive potential, or the like. Depending on the situation, the fixed potential may also be a low-level potential, a ground potential, a negative potential, or the like.

[0304] For example, the wiring VSSL functions as a wiring that applies a fixed potential. The fixed potential may be, for example, a low-level potential, a ground potential, a negative potential, or the like. Depending on the situation, the fixed potential may be a high-level potential.

[0305] Each current source CS shown in FIG. 12 has the above-described connection configuration, and therefore functions as a current sink circuit that causes a current to flow from the terminal T1 of the current source CS to the wiring VSSL via the transistor Tr1 and the transistor Tr2.

[0306] Next, the current mirror circuit CRM will be described.

[0307] The current mirror circuit CRM has a terminal CTi that functions as an input terminal and a terminal CTo that functions as an output terminal, and has a function of outputting a current to the terminal CTo that is equal to the amount of current flowing through the terminal CTi, for example.

[0308] The current mirror circuit CRM includes a transistor Tr5, a transistor Tr5m, a transistor Tr6, and a transistor Tr6m.

[0309] The first terminal of transistor Tr5 is connected to terminal CTi, the gate of transistor Tr6, and the gate of transistor Tr6m. The second terminal of transistor Tr5 is connected to the first terminal of transistor Tr6. The gate of transistor Tr5 is connected to the gate of transistor Tr5m and the wiring CPE. The second terminal of transistor Tr6 is connected to the wiring VEH. The first terminal of transistor Tr5m is connected to terminal CTo. The second terminal of transistor Tr5m is connected to the first terminal of transistor Tr6m. The second terminal of transistor Tr6m is connected to the wiring VEH.

[0310] For the wiring VEH, the description of the wiring VEH shown in FIG. 10A can be referred to.

[0311] For example, the wiring CPE functions as a wiring that applies a fixed potential. The fixed potential may be a low-level potential, a ground potential, a negative potential, etc. Depending on the situation, the fixed potential may be a high-level potential, etc.

[0312] In the current mirror circuit CRM, the second terminals of the transistors Tr6 and Tr6m are connected such that a potential is applied from the wiring VEH, and the gates of the transistors Tr6 and Tr6m are connected such that a potential of the terminal CTi is applied. Ideally, therefore, equal amounts of current flow between the source and drain of the transistors Tr6 and Tr6m.

[0313] Furthermore, transistor Tr5 functions as a transistor cascode-connected to transistor Tr6. Similarly, transistor Tr5m functions as a transistor cascode-connected to transistor Tr6m. This prevents the potential of terminal CTi from being directly input to the first terminal of transistor Tr6. In other words, this prevents the potential of the first terminal of transistor Tr6 from suddenly fluctuating, thereby stabilizing the operation of the current mirror circuit CRM.

[0314] <<Driver Circuit XCD>> The driver circuit XCD shown in Fig. 9 includes circuits XCDb_1 to XCDb_m. Each of the circuits XCDb_1 to XCDb_m shown in Fig. 9 can have the same configuration as the circuit XCDb_i (i is an integer greater than or equal to 1 and less than or equal to m) shown in Fig. 10C, for example.

[0315] The circuit XCDb_i has a function of supplying a signal of an amount corresponding to the second data x to the wiring XCL_i. Note that in the case of the arithmetic device CDVB of FIG. 9, the signal is a current. That is, like the above-described circuit WCDpn_j, the circuit XCDb_i is preferably a current generating circuit that generates a current of an amount corresponding to x. Furthermore, it is particularly preferable that the current generating circuit be a digital potential-analog current converter (IDAC). Note that x is transmitted to the wiring IXL_i as digital data.

[0316] The circuit XCDb_i shown in FIG. 10C includes, as an example, a switch SWX. A first terminal of the switch SWX is connected to the wiring XCL_i, and a second terminal of the switch SWX is connected to the wiring VINI2. The wiring VINI2 functions as a wiring that applies an initialization potential to the wiring XCL. The initialization potential can be a negative potential, a ground potential (GND), a low-level potential, or a high-level potential. The initialization potential applied by the wiring VINI2 may be equal to the potential applied by the wiring VINI1. Note that the switch SWX is turned on only when the initialization potential is applied to the wiring XCL_i, and is turned off otherwise.

[0317] The switch SWX can be, for example, a switch that can be applied to the switches SA_1 to SA_n described in the above embodiment.

[0318] 10C can be configured to have almost the same configuration as the circuit WCDpn_j in FIG. 10A. Specifically, the circuit XCDb_i has a function of outputting reference data as a current amount and a function of outputting L bits (2 Ｌ and a function of outputting second data x of a value (L is an integer of 1 or more) as a current amount. In this case, the circuit XCDb has a function of outputting second data x of a value (L is an integer of 1 or more) as a current amount. ＬThe circuit XCDb_i has one current source CS that outputs information corresponding to the value of the 0th bit as a current, two current sources CS that output information corresponding to the value of the 1st bit as a current, and two current sources CS that output information corresponding to the value of the (L-1)th bit as a current. Ｌ−１ There are individual ones.

[0319] Incidentally, the reference data output as a current by the circuit XCDb_i can be, for example, information in which the value of the 0th bit is "1" and the values ​​of the 1st and subsequent bits are "0".

[0320] In FIG. 10C, the terminal T2 of one current source CS is connected to the wiring DX[0], and each of the terminals T2 of two current sources CS is connected to the wiring DX[1]. Ｌ−１ Each of the terminals T2 of the current sources CS is connected to the wiring DX[L-1].

[0321] In particular, the wirings DX[0] to DX[L-1] can be wirings in the i-th row among the wirings IXL_1 to IXL_m in FIG. 9. That is, the wiring IXL_i can be a wiring group including the wirings DX[0] to DX[L-1].

[0322] The multiple current sources CS included in the circuit XCDb_i are each supplied with the same constant current I Ｘｕｔ from the terminal T1. The wirings DX[0] to DX[L-1] are connected to the current source CS and output I Ｘｕｔ This allows the circuit XCDb_i to pass, to the wiring XCL_i, an amount of current corresponding to L-bit data transmitted from the wirings DX[0] to DX[L-1].

[0323] Specifically, consider the circuit XCDb_i when L is set to 2. For example, when the value of the 0th bit is "1" and the value of the 1st bit is "0", a high-level potential is applied to the wiring DX[0] and a low-level potential is applied to the wiring DX[1]. At this time, a constant current I is supplied from the circuit XCDb_i to the wiring XCL. ＸｕｔFurthermore, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "1", a low-level potential is applied to the wiring DX[0] and a high-level potential is applied to the wiring DX[1]. At this time, a constant current of 2I flows from the circuit XCDb_i to the wiring XCL_i. Ｘｕｔ Furthermore, for example, when the value of the 0th bit is "1" and the value of the 1st bit is "1", a high-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, a constant current of 3I flows from the circuit XCDb_i to the wiring XCL_i. Ｘｕｔ flows. Also, for example, when the value of the 0th bit is "0" and the value of the 1st bit is "0", a low-level potential is applied to the wiring DX[0] and the wiring DX[1]. At this time, no constant current flows from the circuit XCDb_i to the wiring XCL_i. Note that in this specification and the like, this may be rephrased as a current with zero current amount flows from the circuit XCDb_i to the wiring XCL_i. Also, the current with zero current amount, I, output from the circuit XCDb_i Ｘｕｔ , 2I Ｘｕｔ , 3I Ｘｕｔ etc. can be the second data output by the circuit XCDb_i, and in particular, the amount I of constant current output by the circuit XCDb_i Ｘｕｔ can be the reference data output by the circuit XCDb_i.

[0324] In addition, when an error occurs due to variations in the electrical characteristics of the transistors included in each current source CS of the circuit XCDb_i, the amount of constant current I output from each of the terminals T1 of the multiple current sources CS may be Ｘｕｔ The error is preferably within 10%, more preferably within 5%, and even more preferably within 1%. In this embodiment, the amount of constant current I output from the terminal T1 of each of the multiple current sources CS included in the circuit XCDb is Ｘｕｔ In this embodiment, the amount of constant current I output from the terminal T1 of each of the plurality of current sources CS included in the circuit XCDb_i is Ｘｕｔ The following description will be given assuming that there is no error in the amount of constant current I output from the terminal of the current source CS. Ｘｕｔand the output current read from the ideal input / output characteristics.

[0325] 11A to 11D can be applied as the current source CS of the circuit XCDb_i, similar to the current source CS of the circuit WCDpn_j. In this case, the wiring DW illustrated in FIGS. 11A to 11D can be replaced with the wiring DX. This allows the circuit XCDb_i to pass a current in the subthreshold region to the wiring XCL_i as reference data or L-bit second data.

[0326] <<Drive circuit WSD>> The drive circuit WSD shown in Figure 9, like the drive circuit WSD described in the above embodiment, has the function of turning on the write transistor included in the calculation cell IM provided in the cell array CA by supplying a predetermined signal to each of the wiring WSLp and the wiring WSLn when writing first data to the calculation cell IM.

[0327] Note that in the calculation device CDVB, there are two calculation cells, calculation cell IMp and calculation cell IMn. Similarly, the write transistor included in the driver cell IMD also has the function of turning on. Therefore, the driver circuit WSD shown in FIG. 9 functions as a write word line driver circuit for the calculation cell IMp, calculation cell IMn, and driver cell IMD.

[0328] For example, consider a computation cell IM and a driving cell IMD arranged in the i-th row of a cell array CA. A wiring WSLp_i is connected to computation cells IMp[i,1] to IMp[i,n] and the driving cell IMD_i, and a wiring WSLn_i is connected to computation cells IMn[i,1] to IMn[i,n].

[0329] In other words, the signal transmitted from the driving circuit WSD via the wiring WSLp_i is input to each of the calculation cells IMp[i,1] to IMp[i,n] and the driving cell IMD_i, and the signal transmitted from the driving circuit WSD via the wiring WSLn_i is input to each of the calculation cells IMn[i,1] to IMn[i,n].

[0330] <<Computation Cells IM and Driver Cells IMD>> Next, a configuration example of the computation cells IM and driver cells IMD included in the cell array CA will be described.

[0331] Fig. 13 is a circuit diagram showing an example of the circuit configuration of the calculation cell IM[i,j] arranged in the i-th row and j-th column, and the driving cell IMD_i arranged in the i-th row, in the cell array CA of Fig. 9. Note that calculation cell IM[i,j] is a collective name for calculation cell IMp[i,j] and calculation cell IMn[i,j], and therefore Fig. 9 shows circuit diagrams of each of calculation cell IMp[i,j] and calculation cell IMn[i,j].

[0332] In addition, Figure 13 also illustrates the drive circuits WCD, XCD, WSD, and ITS to show the respective connections between the calculation cells IMp[i,j], IMn[i,j], and the drive cells IMD_i.

[0333] The calculation cell IMp[i, j] is, for example, one of two variables w that represents the first data w transmitted from the drive circuit WCD. ｐ and by acquiring the second data x transmitted from the driving circuit XCD, ｐ Similarly, the calculation cell IMn[i,j] has a function of multiplying the other of the two variables expressing the first data w transmitted from the drive circuit WCD, w ｎ and by acquiring the second data x transmitted from the driving circuit XCD, ｎ and x.

[0334] For the driving cell IMD_i, the description of the driving cell IMD_i in the first embodiment can be referred to.

[0335] For example, the calculation cell IMp[i,j] includes a transistor M1p, a transistor M3p, a transistor M4p, and a capacitance element C1p. For example, the calculation cell IMn[i,j] includes a transistor M1n, a transistor M3n, a transistor M4n, and a capacitance element C1n.

[0336] For the transistors M1p and M1n, the description of the transistor M1 included in the processing cell IM in the first embodiment can be referred to. For the transistors M3p and M3n, the description of the transistor M3 included in the processing cell IM in the first embodiment can be referred to. For the transistors M4p and M4n, the description of the transistor M4 included in the processing cell IM in the first embodiment can be referred to. For the capacitors C1p and C1n, the description of the capacitor C1 included in the processing cell IM in the first embodiment can be referred to.

[0337] Regarding the wirings VEL and VEB shown in FIG. 13, the description of the wirings VEL and VEB in the first embodiment can also be referred to.

[0338] In the calculation cell IMp[i,j], the second terminal of the transistor M1p and the second terminal of the transistor M4p are connected to the wiring WCLp_j, and in the calculation cell IMn[i,j], the second terminal of the transistor M1n and the second terminal of the transistor M4n are connected to the wiring WCLn_j.

[0339] 13, the connection point between the first terminal of the capacitance element C1p, the first terminal of the transistor M1p, and the gate of the transistor M3p is indicated as a node Np, the connection point between the first terminal of the capacitance element C1n, the first terminal of the transistor M1n, and the gate of the transistor M3n is indicated as a node Nn, and the connection point between the first terminal of the capacitance element C1d, the first terminal of the transistor M1d, and the gate of the transistor M3d is indicated as a node Nd.

[0340] For an example of the operation of the calculation cell IMp[i,j], the calculation cell IMn[i,j], and the driving cell IMD_i, please refer to the explanation of the example of the operation of the calculation cell IMn[i,j] and the driving cell IMD_i in the first embodiment.

[0341] 9 is connected to a wiring WCLp_j, a wiring WCLn_j, and a wiring OL_j. The driver circuit ITS has a function of outputting a differential current between a current flowing through the wiring WCLp_j and a current flowing through the wiring WCLn_j, and outputting the differential current or a voltage corresponding to the differential current to the wiring OL_j, for example.

[0342] 9 includes, as an example, a circuit SWCB and circuits ITSpn_1 to ITSpn_n. Of the circuits ITSpn_1 to ITSpn_n, only the circuit ITSpn_j is shown in FIGS. 9 and 13. The circuit SWCB also includes switches SBp_1 to SBp_n and switches SBn_1 to SB_j. Only the switches SBp_j and SBn_j are shown in FIGS. 9 and 13.

[0343] The circuit ITSpn_j also has terminals RTip and RTin that function as input terminals, and a terminal RTo that functions as an output terminal.

[0344] A first terminal of the switch SBp_j is connected to the wiring WCLp_j, a second terminal of the switch SBp_j is connected to the terminal RTip of the circuit ITSpn_j, and a control terminal of the switch SBp_j is connected to the wiring SWLB. Also, a first terminal of the switch SBn_j is connected to the wiring WCLn_j, a second terminal of the switch SBn_j is connected to the terminal RTin of the circuit ITSpn_j, and a control terminal of the switch SBn_j is connected to the wiring SWLB.

[0345] Next, an example of the circuit configuration of the circuit ITSpn_j will be described.

[0346] 14 has a function of obtaining a difference between the currents flowing through the wirings WCLp and WCLn and outputting the difference as an analog current. Note that the circuit ITSpn shown in Fig. 14 is, as an example, a modified version of the circuit RL shown in Fig. 8, and only the differences from the circuit RL in Fig. 8 will be described here.

[0347] Unlike the circuit RL in Fig. 8, the circuit ITSpn in Fig. 14 does not include a current source CNI. Furthermore, the terminal RTip of the circuit ITSpn corresponds to the terminal RTi shown in Fig. 8. Furthermore, the first terminal of the transistor Mp1o, the first terminal of the transistor MN2i, the gate of the transistor MN1i, and the gate of the transistor MN1o are connected to the terminal RTin.

[0348] As will be described in detail later, the terminal RTip is connected to a quantity I corresponding to the result of multiplying and accumulating the positive first data and the second data transmitted to each row in the cell array CA. Ｓｐ The current flows to the wiring WCLp_j. Also, as will be described in detail later, the terminal RTin receives a current I corresponding to the result of multiplying and accumulating the negative first data and the second data transmitted to each row in the cell array CA. Ｓｎ The current flows to the wiring WCLn_j.

[0349] Since the transistors MP1i, MP2i, MP1o, and MP2o each constitute a current mirror circuit, the amount of current I flowing through the terminal RTip Ｓｐ Ideally, the amount of current flowing between the source and drain of the transistor MP2o and the transistor MP1o is equal to the amount of current flowing between the source and drain of the transistor MN2i and the transistor MN1i. Ｓｐ -I Ｓｎ (=I Ｓ The current flow is I Ｓｐ Ga I Ｓｎ In the circuit configuration shown in FIG. Ｓ becomes 0.

[0350] Since the transistors MN1i, MN2i, MN1o, and MN2o also form a current mirror circuit, the amount of current I flowing between the source and drain of the transistors MN2i and MN1i is Ｓ Ideally, the amount of current I flowing between the source and drain of the transistor MN1o and the transistor MN2o isＳ is equal to

[0351] Furthermore, since the transistors MP3i, MP4i, MP3o, and MP4o also form a current mirror circuit, the amount of current I flowing between the source and drain of the transistors MN3i and MN4i is Ｓ Ideally, the amount of current I flowing between the source and drain of the transistor MN3o and the transistor MN4o is Ｓ is equal to

[0352] As a result, the circuit ITSpn in FIG. 14 outputs I Ｓｐ and I Ｓｎ is the differential current I Ｓ This allows the circuit ITSpn to output the result of the product-sum operation by the cell array CA as an analog current.

[0353] Next, an example of the configuration of a circuit that is different from the circuit ITSpn of FIG. 14 and that can be applied to the circuit ITSpn of the arithmetic unit CDVB of FIG. 9 will be described.

[0354] 15 has a function of obtaining a difference between the currents flowing through the terminals RTip and RTin and outputting a value corresponding to the difference as digital data. The circuit ITSpn shown in FIG. 15 is also sometimes called a successive approximation register (SAR) type ADC (analog to digital converter).

[0355] As an example, the circuit ITSpn shown in FIG. 15 includes transistors MP5i, MP6i, MP5o, and MP6o included in a first current mirror circuit, and transistors MP7i, MP8i, MP7o, and MP8o included in a second current mirror circuit.

[0356] 15 includes a first digital potential-analog current converter circuit and a second digital potential-analog current converter circuit. The first digital potential-analog current converter circuit includes transistors Tp1[0] to Tp1[M-1] (M is an integer greater than or equal to 1) and transistors Tp2[0] to Tp2[M-1]. The second digital potential-analog current converter circuit includes transistors Tn1[0] to Tn1[M-1] and transistors Tn2[0] to Tn2[M-1].

[0357] Note that the transistors Tp1[s] (here, s is an integer greater than or equal to 0 and less than or equal to M-1) and the transistor Tp2[s] can be replaced with the transistors Tr1 and Tr2 included in the current source CS shown in FIG. 12. The transistors Tn1[s] and Tn2[s] can also be replaced with the transistors Tr1 and Tr2 included in the current source CS shown in FIG. 12. Therefore, the transistors Tp1[0] to Tp1[M-1] and the transistors Tn1[0] to Tn1[M-1] each function as a transistor that passes a constant current according to the channel width. The transistors Tp2[0] to Tp2[M-1] and the transistors Tn2[0] to Tn2[M-1] each function as a switching transistor.

[0358] Here, when the channel width of the transistors Tp1[0] and Tn1[0] is d[0], the channel width of the transistors Tp1[1] and Tn1[1] is d[1], and the channel width of the transistors Tp1[M-1] and Tn1[M-1] is d[M-1], the ratio of the respective channel widths is d[0]:d[1]:d[M-1]=1:2:2. Ｍ−１ Let's say.

[0359] 15 includes a comparator CPR and a logic circuit LGC. The logic circuit LGC includes a terminal LTi, a terminal LFTp, a terminal LFTn, and a terminal LTo.

[0360] A first terminal of the transistor MP5i is connected to the terminal RTip, the gate of the transistor MP6i, the gate of the transistor MP6o, and the first terminals of the transistors Tp2[0] to Tp2[M-1]. A second terminal of the transistor MP5i is connected to the first terminal of the transistor MP6i, and a gate of the transistor MP5i is connected to the gate of the transistor MP5o and the wiring RSWLp.

[0361] A first terminal of the transistor MP7i is connected to the terminal RTin, the gate of the transistor MP8i, the gate of the transistor MP8o, and the first terminals of the transistors Tn2[0] to Tn2[M-1]. A second terminal of the transistor MP7i is connected to the first terminal of the transistor MP8i, and a gate of the transistor MP7i is connected to the gate of the transistor MP7o and the wiring RSWLn.

[0362] For the wirings RSWLp and RSWLn, the description of the wirings RSWL1 to RSWL3 shown in FIG. 8 can be referred to.

[0363] A first terminal of the transistor MP5o is connected to a first terminal of the comparator CPR, a second terminal of the transistor MP5o is connected to a first terminal of the transistor MP6o, a first terminal of the transistor MP7o is connected to a second terminal of the comparator CPR, and a second terminal of the transistor MP7o is connected to a first terminal of the transistor MP8o. In addition, second terminals of the transistors MP6i, MP6o, MP8i, and MP8o are connected to the wiring VDDL.

[0364] For the wiring VDDL, the description of the wiring VDDL shown in FIG. 8 can be referred to.

[0365] The second terminal of the transistor Tp2[s] is connected to the first terminal of the transistor Tp1[s]. The gates of the transistors Tp2[0] to Tp2[M-1] are connected to the terminal LFTp of the logic circuit LGC. The second terminals of the transistors Tp1[0] to Tp1[M-1] are connected to the wiring VSSL. The gates of the transistors Tp1[0] to Tp1[M-1] are connected to the wiring VFE.

[0366] The second terminal of the transistor Tn2[s] is connected to the first terminal of the transistor Tn1[s]. The gates of the transistors Tn2[0] to Tn2[M-1] are connected to the terminal LFTn of the logic circuit LGC. The second terminals of the transistors Tn1[0] to Tn1[M-1] are connected to the wiring VSSL. The gates of the transistors Tn1[0] to Tn1[M-1] are connected to the wiring VFE.

[0367] For the wiring VSSL, the description of the wiring VSSL shown in Fig. 8 can be referred to. For the wiring VFE, the description of the wiring BIS shown in Fig. 12 can be referred to.

[0368] The output terminal of the comparator CPR is connected to the terminal LTi of the logic circuit LGC, and the terminal LTo of the logic circuit LGC is connected to the terminal RTo. ＦＳｐ The amount of current I input to the second input terminal is ＦＳｎ When is small, the amount of current I input to the first input terminal ＦＳｐ and the amount of current I input to the second input terminal ＦＳｎ When the values ​​are equal to each other, a high level potential is output to the output terminal, or the amount of current I input to the first input terminal is ＦＳｐ The amount of current I input to the second input terminal is ＦＳｎ is large, it has the function of outputting a low level potential to the output terminal.

[0369] The logic circuit LGC has the function of obtaining the comparison result of the comparator CPR from the terminal LTi, and outputting a digital signal Q to each of the terminals LFTp and LFTn according to the comparison result, and the function of outputting digital data to the terminal LTo according to the comparison result.

[0370] By operating the circuit ITSpn of FIG. Ｓｐ and I Ｓｎ The differential current can be output to the terminal RTo as digital data.

[0371] <Operation Example 2 of Arithmetic Circuit> Next, an operation example of the arithmetic device CDVB of FIG. 9 will be described.

[0372] 16 is a timing chart showing an example of an operation method of the arithmetic device CDVB. The timing chart shows changes in potentials of the wirings SWLAp, SWLAn, SWLB, WSLp_i, WSLn_i, XCL_i, the node Np, the node Nn, and the node Nd during and around the periods T01 to T09. The timing chart also shows changes in potentials of the wirings SWLAp, SWLAn, SWLB, WSLp_i, WSLn_i, XCL_i, the node Np, the node Nn, and the node Nd during and around the periods T01 to T09. Ｍ３ｐ and the amount of source-drain current I flowing through the transistor M3n. Ｍ３ｎ and the amount of source-drain current I flowing through the transistor M3d. Ｍ３ｄ The respective variations of and are also shown.

[0373] 16, the types of wiring, nodes, etc. are shown on the left side, and the level of potential is shown on the right side. In particular, "High" shown in the timing chart means a high-level potential on the wiring, and "Low" means a low-level potential on the wiring.

[0374] In this operation example, the drive circuit WCD included in the calculation device CDVB of Figure 9 will be described as being applied to the drive circuit WCD of Figure 10A, and the drive circuit XCD included in the calculation device CDVB of Figure 9 will be described as being applied to the drive circuit XCD of Figure 10C.

[0375] The potentials applied by the wirings VEL, VINI1, and VINI2 are V Ｎ In addition, V Ｎ is a ground potential (GND) or a negative potential. The potential applied by the wiring VEB is a high-level potential, and the transistors M4p, M4n, and M4d each function as a clamp transistor.

[0376] In this operation example, the first data w written to the calculation cell IM[i, j] is a positive number. Therefore, one of the two parameters expressing the first data w is w ｐ = w, and the other is w ｎ =0.

[0377] [Period T01] In the period T01, a low-level potential is applied to the wirings SWLAp, SWLAn, SWLB, WSLp_i, and WSLn_i. The potentials of the node N of the processing cell IM and the node Nd of the driving cell IMD are V Ｎ Also, I Ｍ３ and I Ｍ３ｄ Each of these is set to 0.

[0378] As a result, the switches SAp_j, SAn_j, SBp_j, and SBn_j are turned off, and the transistors M1p, M1n, and M1d are also turned off.

[0379] Furthermore, no digital data is input to either the wiring IWL_j or the wiring IXL_i.

[0380] [Period T02] During period T02, one of the two parameters expressing the first data w is input to the wiring IWL_j. ｐ =w is input as digital data. Also, reference data r is input as digital data to the wiring IXL_i.

[0381] A high-level potential is applied to the wiring SWLAp, so that the switch SAp is in an on state. Note that a low-level potential is continuously applied to the wiring SWLAn from the period T01, so that the switch SAn is in an off state.

[0382] The circuit WCDpn converts the digital data w input to the wiring IWL_j into a current. Here, the amount of the current is expressed as wI ０ In addition, I ０ is the current that flows when w is 1. Then, the amount wI ０ The current flows through the switch SAp to the wiring WCLp_j. The current also flows through the operation cell IMp[i,j].

[0383] The circuit XCDa converts the digital data r input to the wiring IXL_i into a current. The amount of the current is expressed as rI ０ Then, the amount rI according to r ０ The current flows to the wiring XCL_i. The current also flows to the driving cell IMD_i.

[0384] A high-level potential is applied to the wiring WSLp_i from the driving circuit WSD, which turns on the transistor M1p in the processing cell IMp[i,j] and also turns on the transistor M1d in the driving cell IMD_i.

[0385] In addition, in the calculation cell IMp[i, j], the source-drain current of the transistor M3p is expressed as wI ０ flows, the potential of the gate of the transistor M3p is such that the source-drain current of the transistor M3p is wI ０ Here, the potential of the gate of the transistor M3p is set to V ｇｐ It is assumed that the result is (w).

[0386] In addition, in the driving cell IMD_i, the source-drain current of the transistor M3d is rI ０ flows, the potential of the gate of the transistor M3d is such that the source-drain current of the transistor M3d is rI ０ Here, the potential of the gate of the transistor M3d is set to V ｇｍ It shall be (r).

[0387] In the calculation cell IMn[i, j], the node Nn is in a floating state, and therefore the potential of the wiring XCL_i fluctuates due to the capacitance element C1n, and the potential of the node Nn also fluctuates. Ｎ From V ｇｍ (r), the potential of the node Nn changes to V ｇｍ (r)-V Ｎ Only fluctuates.

[0388] During period T03, a low-level potential is applied to the wiring WSLp_i from the driving circuit WSD, which turns off the transistor M1p in the processing cell IMp[i,j] and the transistor M1d in the driving cell IMD_i.

[0389] At this time, the potential of the gate of the transistor M3p is V ｇｐ (w), and the amount of current flowing between the source and drain of the transistor M3p is wI ０ Similarly, the potential of the gate of the transistor M3d is set to V ｇｍ (r), and the amount of current flowing between the source and drain of the transistor M3d is rI ０ It is set so that:

[0390] [Period T04] During period T04, ｐ =w is stopped. A low-level potential is applied to the wiring SWLAp. This stops the conversion of digital data into current in the circuit WCDpn_j. The switch SAp_j is turned off.

[0391] [Period T05] During period T05, the other of the two parameters expressing the first data w is input to the wiring IWL_j. ｎ = 0 is input as digital data. Furthermore, the reference data r continues to be input as digital data to the wiring IXL_i.

[0392] A high-level potential is applied to the wiring SWLAn, so that the switch SAn is in an on state. Note that a low-level potential has been applied to the wiring SWLAp since the period T04, so that the switch SAp is in an off state.

[0393] The digital data input to the wiring IWL_j is ｎ = 0, the circuit WCDpn is, for example, at the potential V Ｎ is output to the output terminal. Ｎ is applied to the wiring WCLn_j via the switch SAn. Ｎ is given to the calculation cell IMn[i,j].

[0394] The wiring XCL_i continues to receive the quantity rI from the driving circuit XCD. ０ Therefore, the potential of the wiring XCL_i is V ｇｍ It remains as (r).

[0395] A high-level potential is applied to the wiring WSLn_i from the driving circuit WSD. This turns on the transistor M1n in the processing cell IMn[i,j]. At this time, the gate of the transistor M3n in the processing cell IMn[i,j] is supplied with the potential V Ｎ In this operation example, the gate-source voltage of the transistor M3n is V Ｎ -V Ｎ =0, the amount of current flowing between the source and drain of the transistor M3n becomes zero.

[0396] [Period T06] During the period T06, a low-level potential is applied to the wiring WSLn_i from the driver circuit WSD, which turns off the transistor M1n in the processing cell IMn[i,j].

[0397] At this time, the potential of the gate of the transistor M3n is V Ｎ , and the amount of current flowing between the source and drain of the transistor M3n is set to 0. In other words, the transistor M3n is set to be in the OFF state.

[0398] [Period T07] During period T07, ｎ Input of .SIGMA.=0 is stopped. A low-level potential is applied to the wiring SWLAn. This stops the conversion of digital data into current in the circuit WCDpn_j. Furthermore, the switch SAn_j is turned off.

[0399] In addition, in the period T07, the input of the reference data r to the wiring IXL_i is stopped. Therefore, the operation of converting digital data into current in the circuit XCDa_i is stopped. Note that in this case, the circuit XCDa_i does not apply a potential V Ｎ It will be explained as giving

[0400] In the calculation cell IMp[i, j], the node Np is in a floating state. Therefore, the potential of the wiring XCL_i fluctuates due to the capacitance element C1p, and the potential of the node Np also fluctuates. Here, the potential of the wiring XCL_i is V ｇｍ (r) to V Ｎ Therefore, the potential of the node Np changes to V ｇｍ (r)-V Ｎ In this example of operation, the potential of the node Np changes by V ｇｐ (w)-V ｇｍ (r) + V Ｎ It shall be as follows.

[0401] In the calculation cell IMn[i, j], the node Nn is in a floating state, and therefore the potential of the wiring XCL_i fluctuates due to the capacitance element C1n, and the potential of the node Nn also fluctuates. ｇｍ (r) to V Ｎ Therefore, the potential of the node Nn changes to V ｇｍ (r)-V Ｎ In this example of operation, the potential of the node Nn changes by 2V. Ｎ -V ｇｍ It shall be (r).

[0402] In addition, in the driving cell IMD_i, the node Nd is in a floating state, and therefore, when the potential of the wiring XCL_i fluctuates due to the capacitance element C1d, the potential of the node Nd also fluctuates.ｇｍ (r) to V Ｎ Therefore, the potential of the node Nd changes to V ｇｍ (r)-V Ｎ In this example of operation, the potential of the node Nn changes by V Ｎ It shall be as follows.

[0403] [Period T08] In the period T07, a high-level potential is applied to the wiring SWLB. As a result, the switches SBp_j and SBn_j are turned on. As a result, a high-level potential is applied from the circuit ITSpn_j to the wiring WCLp_j and the wiring WCLn_j. Therefore, the amount wI set in the periods T02 and T03 is applied between the source and drain of the transistor M3p of the arithmetic cell IMp[i,j]. ０ Furthermore, this current flows from the terminal RTip of the circuit ITSpn_j through the wiring WCLp_j to the wiring VEL of the operation cell IMp[i,j].

[0404] [Period T09] In the period T09, the second data x is input to the wiring IXL_i as digital data. As a result, the circuit XCDa converts the digital data x input to the wiring IXL_i into a current. Note that the amount of the current is expressed as xI ０ Then, the amount xI according to x ０ The current flows to the wiring XCL_i. The current also flows to the driving cell IMD_i.

[0405] At this time, the potential of the wiring XCL_i is V ｇｍ From (r), the amount of current xI flowing through the wiring XCL_i ０ At this time, the potential of the wiring XCL_i is determined by V ｇｍ Let (x).

[0406] In addition, in the period T09, the node Nd in the driving cell IMD_i is in a floating state. Therefore, the potential of the wiring XCL_i fluctuates due to the capacitive coupling of the capacitor C1d, and the potential of the node Nd also fluctuates. Here, the potential of the wiring XCL_i is V Ｎ From V ｇｍ (x), the potential of the node Nd changes to V ｇｍ (x)-VＮ That is, in this operation example, the potential of the node Nd changes by V ｇｍ Let it be (x).

[0407] In addition, in the period T09, the node Np in the calculation cell IMp[i, j] is in a floating state. Therefore, the potential of the wiring XCL_i fluctuates due to the capacitive coupling of the capacitor C1p, and the potential of the node Np also fluctuates. Here, the potential of the wiring XCL_i is V Ｎ From V ｇｍ [x], the potential of the node Np also changes to V ｇｍ (x)-V Ｎ That is, in this example of operation, the potential of the node Np changes by V ｇｐ (w)-V ｇｍ (r) + V ｇｍ Let it be (x).

[0408] At this time, the amount of current flowing between the source and drain of the transistor M3p is expressed as I ０ ×wx / r.

[0409] In addition, in the period T09, the node Nn in the arithmetic cell IMn[i, j] is in a floating state. Therefore, the potential of the wiring XCL_i fluctuates due to the capacitive coupling of the capacitor C1n, and the potential of the node Nn also fluctuates. Here, the potential of the wiring XCL_i is V Ｎ From V ｇｍ (x), the potential of the node Nn also changes to V ｇｍ (x)-V Ｎ In this example of operation, the potential of the node Nn changes by V ｇｍ (x)-V ｇｍ (r) + V Ｎ In this example of operation, V is applied to the gate of the transistor M3n. ｇｍ (x)-V ｇｍ (r) + V Ｎ is applied to the second terminal of the transistor M3n, and V Ｎ When the voltage Vcc is given, the amount of current flowing between the source and drain of the transistor M3n is assumed to be 0.

[0410] In the above description, the explanation was given focusing on the calculation cells IM[i, j] (calculation cells IMp[i, j] and calculation cells IMn[i, j]) of the cell array CA. However, if the calculation cells IM[i, j] are focused on from the first row to the m-th row, the amount of current I ＳＵＭｐ and the amount of current I flowing through the wiring WCLn_j. ＳＵＭｎ With reference to equation (1.8), each of and is expressed as I ＳＵＭｐ =I ０ Σw ｐ [i,j]x[i] / r[i] and I ＳＵＭｎ =I ０ Σw ｎ It can be written as [i, j] x [i] / r [i]. ｐ [i, j] is the value of the digital data held in the calculation cell IMp[i, j], and w ｎ [i, j] is the value of the digital data held in the calculation cell IMn[i, j]. ｐ [i, j] and w ｎ [i, j] are two variables that represent the first data w[i, j] written into the calculation cell IM[i, j].

[0411] Then, in a period T09, the terminal RTip of the circuit ITSpn_j is connected to I ＳＵＭｐ flows, and I flows to the terminal RTin of the circuit ITSpn_j. ＳＵＭｎ flow, the circuit ITSpn_j generates a difference current I ＳＵＭｐ -I ＳＵＭｎ Thus, the circuit ITSpn_j can output the differential current or a potential according to the differential current to the wiring OL_j.

[0412] 9, the arithmetic device CDVB uses one circuit WCDpn_j to provide each of the arithmetic cells IMp[1,j] to IMp[m,j] connected to the wiring WCLp_j with a signal WCDpn_j. ｐ is written to each of the calculation cells IMn[1,j] to IMn[m,j] connected to the wiring WCLn_j. ｎ With this configuration, the amount of differential current I generated in the circuit ITSpn_j is written.ＳＵＭｐ -I ＳＵＭｎ This means that the variation in the results of the sum-of-products operation can be reduced.

[0413] Here, w ｐ and writing w to each of the calculation cells IMn[1,j] to IMn[m,j]. ｎ When there is a difference in the input / output characteristics of the different circuits WCDpn, in other words, when the same digital data is input to both circuits WCDpn, there is a difference in the potentials output, and the amount of differential current I generated in the circuit ITSpn_j is ＳＵＭｐ -I ＳＵＭｎ However, there are cases where the actual current amount deviates from the expected amount.

[0414] Therefore, the w ｐ and writing w to each of the calculation cells IMn[1,j] to IMn[m,j]. ｎ and the amount of differential current I generated in the circuit ITSpn_j by using the same circuit WCDpn. ＳＵＭｐ -I ＳＵＭｎ This allows the results of the product-sum operation to be output more accurately, and the accuracy rate of the artificial neural network's inference can be increased.

[0415] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0416] Embodiment Mode 3 In this embodiment mode, a structural example of the semiconductor device described in the above embodiment mode will be described.

[0417] <Example of Circuit Layout of Semiconductor Device> FIG. 17A is a schematic plan view showing an example of the circuit configuration of an arithmetic cell IM included in the arithmetic device CDVA, which is the semiconductor device described in the above embodiment.

[0418] The schematic plan view of Fig. 17A shows an example of a circuit layer including a calculation cell IM, and the circuit layer includes conductive layers 232, 233, 234, 235, and a semiconductor layer 251. Note that, to clearly show the schematic plan view, Fig. 17A does not show insulating layers included in the circuit layer.

[0419] 17A , each of the transistor M1, the transistor M3, and the transistor M4 includes an island-shaped insulating layer, a semiconductor layer 251 formed on the insulating layer, a conductive layer 232 formed on the semiconductor layer 251, a gate insulating film formed on the semiconductor layer 251, and a conductive layer 233 formed on the gate insulating film. Each of the transistor M1, the transistor M3, and the transistor M4 can have a GL (Gate Last) structure (also referred to as a TGSA (Trench Gate Self Align) or Top Gate Self Align) structure) described later.

[0420] For example, the semiconductor layer 251 is located below the conductive layer 232 and the conductive layer 233. For example, the conductive layer 234 is located above the conductive layer 232 and the conductive layer 233. For example, the conductive layer 235 is located above the conductive layer 234. The order of formation can be as follows: first, the semiconductor layer 251, second, the conductive layer 232, third, the conductive layer 233, fourth, and fifth, the conductive layer 234.

[0421] 17A , for example, a portion of the conductive layer 232 functions as a source or drain of each of the transistors M1, M3, and M4. For example, a portion of the conductive layer 233 functions as a gate of each of the transistors M1, M3, and M4. For example, the conductive layer 234 functions as a wiring for electrically connecting the conductive layer 232 or the conductive layer 233 to the conductive layer 235. For this reason, the conductive layer 234 may be referred to as a contact plug, for example.

[0422] 17A , a part of the conductive layer 233 functions as one of a pair of electrodes of the capacitor C1, for example, and the conductive layer 235 functions as the other of the pair of electrodes of the capacitor C1, for example.

[0423] 17A, a portion of each of the conductive layers 233 and 235 functions as wiring. For example, a portion of the conductive layer 233 is provided as wiring XCL and wiring WSL, extending in the left-right direction of the drawing. For example, a portion of the conductive layer 235 is provided as wiring VEL, wiring WCL, and wiring VEB, extending in the up-down direction of the drawing. For this reason, it is preferable to use a highly conductive material for each of the conductive layers 233 and 235.

[0424] Each of the above-described conductive layers can be formed by, for example, lithography. Specifically, for example, when forming the conductive layer 232, a conductive material to be the conductive layer 232 can be formed by one or more methods selected from a sputtering method, a chemical vapor deposition (CVD) method, a pulsed laser deposition (PLD) method, and an atomic layer deposition (ALD) method, and then a desired pattern can be formed by lithography. Furthermore, conductive layers, semiconductor layers, and insulating layers other than the conductive layer 232 can also be formed by the same methods as above.

[0425] In this specification, the lithography method includes, for example, photolithography, ion beam lithography, X-ray lithography, electron beam lithography, multiphoton lithography, interference lithography, and nanoimprinting.

[0426] Furthermore, an insulating layer can be provided between the conductive layer 233 and the conductive layer 235. In particular, in the region where the capacitor C1 is provided, the insulating layer formed so as to overlap between the conductive layer 233 and the conductive layer 235 is preferably an insulating layer that functions as a dielectric in the capacitor C1.

[0427] 17A, the capacitance element C1 has a parallel plate structure. Furthermore, the capacitance element C1 can be provided in a region where the wiring XCL extends. This makes it easy to ensure the area for the capacitance element C1, thereby reducing the circuit area of ​​the processing cell IM.

[0428] 17A , the width d1 of the conductive layer 235, which functions as the other of the pair of electrodes of the capacitor C1, is shorter than the width d2 of the conductive layer 233, which functions as one of the pair of electrodes of the capacitor C1. When an insulating layer functioning as a dielectric is formed on the conductive layer 233, the insulating layer may be poorly formed at the edge of the conductive layer 233 or in its surrounding area. Specifically, the insulating layer formed at the edge of the conductive layer 233 or in its surrounding area may have poor coverage. In this case, if the width d1 of the conductive layer 235 is longer than the width d2 of the conductive layer 233, the edge of the conductive layer 233 or its surrounding area may come into contact with the area of ​​the conductive layer 235 that overlaps it, resulting in a short circuit. For this reason, it is preferable that the width d1 of the conductive layer 235 be shorter than the width d2 of the conductive layer 233.

[0429] Conversely, if the coverage of the insulating layer formed on the edge of the conductive layer 233 or its surrounding area can be increased, it is preferable to make the width d1 longer than the width d2. Specifically, since the capacitance value of a capacitance element is proportional to the area of ​​the region where one of the pair of electrodes, the dielectric, and the other of the pair of electrodes overlap, it is preferable to increase the area of ​​that region if a higher capacitance value is desired. Therefore, by making the width d1 longer than the width d2, the width of that region can be increased from d1 to d2. As a result, the conductive layer 235 is formed above the edge of the conductive layer 233, which increases the area of ​​the other of the pair of electrodes of the capacitance element C1, thereby increasing the capacitance value of the capacitance element C1.

[0430] 6A, because the transistors M3 and M4 are connected in series, as shown in the schematic plan view of the calculation cell IM in Fig. 17A, the transistors M3 and M4 can be formed so as to share the island-shaped semiconductor layer 251. This makes it possible to reduce the formation area of ​​the calculation cell IM, and as a result, it is possible to increase the cell density of the calculation cell IM and also to reduce the circuit area of ​​the calculation device CDVA.

[0431] Furthermore, a wiring (back-gate wiring) functioning as a back gate electrode may be provided for each of the transistors M1 and M4. Specifically, for example, as shown in FIG. 17B , a conductive layer 231 may be extended as a wiring BGL1, which is a back-gate wiring, below a semiconductor layer 251 including the channel formation regions of the transistors M1 and M4. The conductive layer 231 may also be provided below the semiconductor layer 251 including the channel formation region of the transistor M3. This facilitates routing of the wiring BGL1 and shortens the wiring distance, thereby reducing parasitic resistance and power consumption.

[0432] Note that the schematic plan views of the semiconductor device of one embodiment of the present invention are not limited to those shown in Fig. 17A and Fig. 17B The schematic plan views of the arithmetic circuit of one embodiment of the present invention can be appropriately changed depending on the situation.

[0433] In addition, in the schematic plan views of Figures 17A and 17B, the sizes (including channel lengths and channel widths) of transistors M1, M3, and M4 are shown to be equal to each other, but the sizes of transistors M1, M3, and M4 may be different from each other.

[0434] For example, the channel width of the switching transistor is preferably shorter than the channel width of the amplification transistor. Specifically, in Figures 17A and 17B, the channel width d3 of the transistor M1 is preferably shorter than the channel width d5 ​​of the transistor M3. By shortening the channel width d3 of the transistor M1 that functions as a switching transistor, the off-state current of the transistor M1 can be reduced, and the potential of the gate of the transistor M3 can be held for a long period of time.

[0435] 17A and 17B, the channel length d4 of the transistor M1 is preferably longer than the channel length d6 of the transistor M3. Increasing the channel length d4 of the transistor M1 that functions as a switching transistor can also reduce the off-state current of the transistor M1.

[0436] Furthermore, for example, the channel width of the amplification transistor is preferably longer than the channel width of the switching transistor. Specifically, the channel width d5 ​​of the transistor M3 is preferably shorter than the channel width d3 of the transistor M1. By shortening the channel width d5 ​​of the transistor M3 that functions as an amplification transistor, the on-current of the transistor M3 can be increased.

[0437] Furthermore, for example, it is preferable that the channel length of the amplification transistor be shorter than the channel length of the switching transistor. Specifically, it is preferable that the channel length d6 of the transistor M3 be shorter than the channel length d4 of the transistor M1. By shortening the channel length d6 of the transistor M3 that functions as an amplification transistor, it is possible to increase the on-current of the transistor M3.

[0438] Furthermore, because transistor M4 functions as a clamp transistor, it is preferable that the channel length d10 of transistor M4 be longer than the channel length d6 of transistor M3. By making the channel length d10 of transistor M4 longer than the channel length d6 of transistor M3, DIBL of transistor M3 can be prevented. Furthermore, even if the channel length d10 of transistor M4 is equal to or shorter than the channel length d6 of transistor M3, DIBL of transistor M3 can be prevented in some cases. Furthermore, because transistor M4 prevents a decrease in the amount of current flowing between the source and drain of transistor M3, it is preferable that the channel width d9 of transistor M4 be longer than the channel width d5 ​​of transistor M3. Furthermore, even if the channel width d9 of transistor M4 is equal to or shorter than the channel length d5 ​​of transistor M3, a decrease in the amount of current flowing between the source and drain of transistor M3 can be prevented in some cases.

[0439] <Example of Cross-Sectional Configuration of Semiconductor Device> Fig. 18 is a schematic cross-sectional view showing an example of the configuration of the arithmetic device CDVA described in the above embodiment. In Fig. 18, the arithmetic device CDVA includes, as an example, a circuit layer PHRL and a circuit layer OMAL located above the circuit layer PHRL.

[0440] 18, the transistor M1 is located above the transistors M3 and M4, so note that the cross-sectional view of FIG. 18 differs in configuration from the plan views of FIG. 17A and FIG. 17B.

[0441] The circuit layer PHRL can be formed by, for example, providing circuit elements such as transistors and capacitors on a substrate. The substrate can be a semiconductor substrate (e.g., a single-crystal substrate made of silicon or germanium). Other than semiconductor substrates, examples of usable substrates include an SOI (silicon-on-insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a lamination film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, lamination films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Another example is polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride. Another example is polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or paper. If the manufacturing process of the computing device CDVA includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate.

[0442] In this embodiment, the substrate included in the circuit layer PHRL will be described as a semiconductor substrate having silicon.

[0443] By using a semiconductor substrate made of silicon as the substrate included in the circuit layer PHRL, the transistors included in each of the drive circuits WCD, XCD, ITS, and WSD shown in FIG. 1 can be formed on the semiconductor substrate. In this case, the transistors are Si transistors. Si transistors have high field-effect mobility and can therefore pass large on-currents. This makes it possible to increase the drive speed of each of the drive circuits listed above and widen the signal range.

[0444] The stacked structure of the circuit layer PHRL and the circuit layer OMAL can be fabricated by directly forming the circuit layer OMAL on the circuit layer PHRL. Alternatively, the circuit layer OMAL can be fabricated by forming a substrate on which circuit elements such as transistors and capacitors are provided, and then mounting the substrate on the circuit layer PHRL. When the circuit layer OMAL is formed directly on the circuit layer PHRL, the circuit layer OMAL preferably includes an OS transistor. An IO transistor can be used as the OS transistor. OS transistors can be formed not only on semiconductor substrates but also on insulating substrates, conductive substrates, and even conductive films, insulating films, and semiconductor films. Therefore, they can be easily provided on semiconductor substrates (on the circuit layer PHRL) on which Si transistors are formed.

[0445] Furthermore, when circuit elements such as transistors and capacitors are formed on a substrate as the circuit layer OMAL and the substrate is mounted on the circuit layer PHRL, flip-chip bonding or wire bonding can be used. Alternatively, a first bonding layer may be provided on the circuit layer PHRL side, a second bonding layer may be provided on the substrate of the circuit layer OMAL, and the first and second bonding layers may be bonded together using one or both of a surface activated bonding method and a hydrophilic bonding method, thereby mounting the circuit layer OMAL on the circuit layer PHRL. In particular, bonding in which copper (Cu) is used as the conductor contained in each of the first and second bonding layers and the copper is bonded to each other is called Cu-Cu (copper-copper) direct bonding.

[0446] 18 illustrates a transistor 100 included in the circuit layer PHRL. The transistor 100 is provided over a substrate 101 and includes a conductive layer 131 functioning as a gate, an insulating layer 161 and an insulating layer 111 functioning as gate insulating films, a semiconductor region 171 including part of the substrate 101, and low-resistance regions 172a and 172b functioning as source and drain regions including part of the substrate. The transistor 100 can be a p-channel transistor or an n-channel transistor. The substrate 101 can be, for example, a single crystal silicon substrate.

[0447] 18 is formed by providing an element isolation layer 102 in the substrate 101. The element isolation layer 102 can also be said to be provided to isolate a plurality of transistors formed on the substrate 101. The element isolation layer 102 can be formed by using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, or a mesa isolation method.

[0448] As an example, the transistor 100 shown in FIG. 18 may have a semiconductor region 171 (a part of the substrate 101) in which a channel is formed that has a convex shape, as shown in the cross-sectional schematic diagram of FIG. 19 . FIG. 19 is a cross-sectional schematic diagram of the transistor 100 in the channel width direction. A conductive layer 131 is provided to cover the side and top surfaces of the semiconductor region 171 with an insulating layer 161 interposed therebetween. The conductive layer 131 may be made of a material that adjusts the work function. FIG. 19 also illustrates a conductive layer 136 for connecting the conductive layer 131 to a circuit element or the like located above the transistor 100. The conductive layer 136 also functions as a plug. Such a transistor 100 is also called a fin-type transistor because it utilizes a convex portion of the semiconductor substrate. An insulating layer that contacts the top of the convex portion and functions as a mask for forming the convex portion may be provided. While the case where the convex portion is formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0449] Note that the transistor 100 illustrated in FIGS. 18 and 19 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0450] Between each structure, a wiring layer provided with an interlayer film, wiring, and plugs may be provided. Furthermore, multiple wiring layers may be provided depending on the design. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0451] For example, an insulating layer 112, an insulating layer 181, and an insulating layer 113 are stacked in this order as an interlayer film over the transistor 100. A conductive layer 132 and the like are embedded in the insulating layer 112. A conductive layer 133 and the like are embedded in the insulating layer 181 and the insulating layer 113. The conductive layer 132 and the conductive layer 133 function as contact plugs or wirings.

[0452] The insulating layer serving as an interlayer film may also serve as a planarizing film that covers the underlying unevenness. For example, the top surface of the insulating layer 112 may be planarized by a planarization treatment using a chemical mechanical polishing (CMP) method to improve the planarity.

[0453] 18 , an insulating layer 182, an insulating layer 114, an insulating layer 115, and an insulating layer 116 are stacked in this order over the insulating layer 113 and the conductive layer 133. In addition, a conductive layer 134 is formed in the insulating layer 182, the insulating layer 114, and the insulating layer 115. The conductive layer 134 functions as a contact plug or a wiring.

[0454] An insulating layer 281 is provided on the insulating layer 116. It is preferable that contact plugs or wiring are embedded in the insulating layer 116 and the insulating layer 281 to connect to an upper circuit (for example, a circuit element included in a circuit included in the circuit layer OMAL).

[0455] Next, a configuration example of the arithmetic cells included in the circuit layer OMAL shown in FIG. 18 will be described.

[0456] 18, the transistors M3 and M4 are formed on an insulating layer 281. The transistor M1 is formed on an insulating layer 284. The capacitance element C1 is formed on an insulating layer 287. The insulating layer 287 is located above the insulating layer 284, and the insulating layer 284 is located above the insulating layer 281. Therefore, it can be said that the capacitance element C1 is located above the transistor M1, and the transistor M1 is located above the transistors M3 and M4.

[0457] 18 preferably functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layer 181, the insulating layer 182, the insulating layers 281 to 284, and the insulating layer 287 preferably functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. Therefore, the insulating layer 181, the insulating layer 182, the insulating layers 281 to 284, and the insulating layer 287 preferably functions as a barrier insulating film that suppresses the permeation of impurities such as water and hydrogen. ２ O, NO or NO ２ It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules) (i.e., through which the oxygen is less likely to permeate). Note that for materials that can be applied to the insulating layer 181, the insulating layer 182, the insulating layers 281 to 284, and the insulating layer 287, the description of the insulating layers in the section on constituent materials of transistors can be referred to.

[0458] A conductive layer functioning as a wiring VEL is connected to one of the source electrode or drain electrode of the transistor M3 through a conductive layer 234_1 functioning as a contact plug. The other of the source electrode or drain electrode of the transistor M3 is formed so as to be shared with one of the source electrode or drain electrode of the transistor M4. The other of the source electrode or drain electrode of the transistor M4 is connected to one of the source electrode or drain electrode of the transistor M1 through a conductive layer 234_2, a conductive layer 235_2, and a conductive layer 235_4 functioning as contact plugs. Note that in FIG. 18, as an example, a conductive layer functioning as a wiring WCL is provided between the conductive layer 234_2 and the conductive layer 235_2.

[0459] Moreover, the gate electrode of the transistor M1 extends in the front-to-depth direction of FIG. 18 as a conductive layer having the function of a wiring WSL, for example.

[0460] The other of the source electrode and the drain electrode of the transistor M1 is connected to the gate electrode of the transistor M3 through a conductive layer 235_3, a conductive layer 235_1, and a conductive layer 235_2 which function as a contact plug. In FIG. 18, for example, a conductive layer which serves as one of a pair of electrodes of the capacitor C1 is provided between the conductive layer 235_1 and the conductive layer 235_3.

[0461] A conductive layer that functions as one of a pair of electrodes of the capacitor C1 is formed so as to be embedded in the insulating layer 219 over the insulating layer 287. An insulating layer 441 that functions as a dielectric of the capacitor C1 is provided above the conductive layer that becomes one of the pair of electrodes of the capacitor C1. A conductive layer that functions as a wiring XCL is provided above the insulating layer 441. Note that a region of the conductive layer that functions as the wiring XCL that overlaps with the conductive layer that becomes one of the pair of electrodes of the capacitor C1 functions as the other of the pair of electrodes of the capacitor C1.

[0462] By embedding the conductive layer that functions as one of the pair of electrodes of the capacitor C1 in the insulating layer 219, the upper surface of the conductive layer that functions as one of the pair of electrodes of the capacitor C1 and the upper surface of the insulating layer 219 can be made flush with each other. This allows the insulating layer that functions as a dielectric and the conductive layer that functions as the other of the pair of electrodes of the capacitor C1 to be formed with good flatness on the upper surfaces of the conductive layer that functions as one of the pair of electrodes of the capacitor C1 and the insulating layer 219, which have good flatness. By improving the flatness of both the pair of electrodes of the capacitor C1 and the insulating layer that functions as a dielectric, localized electric field concentration can be suppressed, thereby preventing leakage current between the pair of electrodes of the capacitor C1. Furthermore, one of the pair of electrodes of the capacitor C1 (here, the lower electrode) has a smaller area than the other of the pair of electrodes of the capacitor C1 (here, the upper electrode). This configuration makes it possible to suppress local electric field concentration that may occur in the dielectric film (insulating film sandwiched between a pair of electrodes) of the capacitance element C1, thereby realizing a highly reliable semiconductor device.

[0463] For example, in the computation cell IM[i,j] of Figure 5, by configuring the capacitance element C1 as described above, it is possible to prevent leakage current between the pair of electrodes of the capacitance element C1 that occurs between the gate of the transistor M3 and the wiring XCL. As a result, fluctuations in the potential of the gate of the transistor M3 due to the leakage current can be prevented in the computation cell IM, and the potential can be maintained for a long period of time. Furthermore, local electric field concentration can be suppressed in the dielectric of the capacitance element C1, thereby improving the reliability of the computation cell IM.

[0464] Similarly, in the driver cell IMD_i of Figure 5, by configuring the capacitor C1d as described above, it is possible to prevent leakage current between the pair of electrodes of the capacitor C1d that occurs between the gate of the transistor M3 and the wiring XCL. Therefore, in the driver cell IMD, fluctuations in the potential of the gate of the transistor M3 due to the leakage current can be prevented, and the potential can be maintained for a long period of time. Furthermore, localized electric field concentration on the dielectric of the capacitor C1d can be suppressed, thereby improving the reliability of the driver cell IMD. As a result, the reliability of the driver cell IMD can be improved.

[0465] In addition, in the configuration example of FIG. 18, the conductive layer that functions as the wiring XCL and the conductive layer that functions as the wiring WSL are each extended in the direction of the channel width of each of the transistors M1, M3, and M4.

[0466] 18, a conductive layer functioning as a back gate may be provided below the island-shaped semiconductor layer of each of the transistors M1, M3, and M4. By providing a back gate for each transistor and changing the potential of the back gate, the threshold voltage of the transistor can be changed.

[0467] For example, by providing a back gate to each of the transistors M1, M3, and M4, the influence of an external electric field can be reduced and the transistors can be stably maintained in an off state. Therefore, data written to the capacitance element C1 can be stably held. In this way, providing a back gate stabilizes the operation of the calculation cell IM and improves the reliability of the circuit layer OMAL including the calculation cell IM.

[0468] As the semiconductor layers in which the channels of the transistors M1, M3, and M4 are formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, silicon or germanium can be used as described in Embodiment 1. As another example, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can be used.

[0469] Note that the transistors M1, M3, and M4 are preferably transistors (OS transistors) that use an oxide semiconductor, which is a type of metal oxide, in a semiconductor layer in which a channel is formed. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. Therefore, the power consumption of the arithmetic cell can be reduced. Therefore, the power consumption of the arithmetic device CDVA including the arithmetic cell IM can be reduced.

[0470] 18 can store the first data, and therefore also functions as a storage device. Therefore, the calculation cell or the calculation device CDVA in FIG. 18 can be called an "OS memory."

[0471] Furthermore, the OS transistor operates stably even in a high-temperature environment, and its characteristics fluctuate little. For example, the off-state current hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an environment of room temperature (e.g., 25° C.) or higher and 200° C. or lower. Furthermore, the on-state current hardly decreases even in a high-temperature environment. Therefore, the OS memory operates stably even in a high-temperature environment, and high reliability is achieved.

[0472] In particular, by using an oxide containing indium as the oxide semiconductor, that is, by using each of the transistors M1, M3, and M4 as an IO transistor, the transistors M1, M3, and M4 can be transistors with small off-state current and large on-state current, which may enable the realization of a computing device CDVA that has both high reliability and high operating speed.

[0473] Note that when a back gate is provided in a transistor, it is preferable not to provide a conductive layer near the back gate in order to avoid formation of parasitic capacitance with the back gate.

[0474] <<Transistor Configuration Example 1>> Next, a specific configuration example of a transistor called a GL structure that can be applied to the transistor M1, the transistor M3, and the transistor M4 shown in Fig. 18 will be described. A transistor 200 shown in Fig. 20A and Fig. 20B is an example of a transistor with a GL structure that can be applied to the transistor M1, the transistor M3, and the transistor M4 shown in Fig. 18.

[0475] In particular, FIG. 20A shows a schematic cross-sectional view of the transistor 200 in the channel length direction, and FIG. 20B shows a schematic cross-sectional view of the transistor 200 in the channel width direction.

[0476] 20A and 20B , for example, the transistor 200 includes a semiconductor layer 251a, a semiconductor layer 251b, a conductive layer 231, a conductive layer 232a, a conductive layer 232b, an insulating layer 213, a conductive layer 233, an insulating layer 281, an insulating layer 212, an insulating layer 261, an insulating layer 262, an insulating layer 263, an insulating layer 264, an insulating layer 282, an insulating layer 283, an insulating layer 213, and an insulating layer 214. Note that the transistor 200 does not necessarily include all of the above components. For example, the conductive layer 231 functions as a backgate electrode of the transistor 200, but the transistor 200 may not include the conductive layer 231.

[0477] Materials that can be used for the conductive layer, insulating layer, and semiconductor layer will be described later.

[0478] The conductive layer 231 (conductive layer 231a and conductive layer 231b) and the insulating layer 212 are disposed above a substrate (not shown). In particular, the conductive layer 231 is preferably provided so as to be embedded in the insulating layer 212. Specifically, the conductive layer 231a is preferably provided in contact with the bottom and sidewall of an opening provided in the insulating layer 212. The conductive layer 231b is preferably provided so as to be embedded in a recess formed in the conductive layer 231a. Note that in the transistor 200 shown in FIGS. 20A and 20B , the height of the top surface of the conductive layer 231b is approximately the same as the height of the top surface of the conductive layer 231a and the height of the top surface of the insulating layer 212.

[0479] The insulating layer 212 functions as a planarizing film that flattens steps caused by plugs or the like, similar to the insulating layer 112. Therefore, the insulating layer 212 can be made of a material that functions as a planarizing film, similar to the insulating layer 112. Furthermore, by using a material with a low dielectric constant for the insulating layer 212, the parasitic capacitance between wirings can be reduced.

[0480] For this reason, the insulating layer 212 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Alternatively, the insulating layer 212 can be made of, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, or silicon oxide having vacancies are particularly preferred because they can easily form regions containing oxygen that is released by heating. Alternatively, the insulating layer 212 can be made of, for example, a resin. The material used for the insulating layer 212 may be an appropriate combination of the above-mentioned insulating materials.

[0481] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0482] The semiconductor layer 251 and the conductive layer 233 are disposed in a region overlapping the conductive layer 231. The semiconductor layer 251b is disposed on the semiconductor layer 251a. The conductive layers 232a and 232b are disposed on the semiconductor layer 251b, spaced apart from each other. The insulating layer 213 is disposed on the conductive layers 232a and 232b. In particular, an opening is formed in the insulating layer 213 in a region between the conductive layers 232a and 232b. The conductive layer 233 is disposed in the opening. The insulating layer 264 is disposed between the semiconductor layer 251b, the conductive layers 232a and 232b, and the insulating layer 213 and the conductive layer 233. Here, as shown in FIGS. 20A and 20B , it is preferable that the top surface of the conductive layer 233 substantially coincides with the top surfaces of the insulating layer 264 and the insulating layer 213. Note that hereinafter, the conductive layers 231a and 231b may be collectively referred to as conductive layers 231. The semiconductor layers 251a and 251b may be collectively referred to as semiconductor layers 251. The conductive layers 232a and 232b may be collectively referred to as conductive layers 232.

[0483] 20A , a region 271a may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 232a and in its vicinity. Similarly, a region 271b may be formed as a low-resistance region at the interface between the semiconductor layer 251b and the conductive layer 232b and in its vicinity. In this case, the region 271a functions as one of a source region and a drain region, and the region 271b functions as the other of the source region and the drain region. A channel formation region is formed in a region sandwiched between the region 271a and the region 271b.

[0484] By providing the conductive layer 232a (conductive layer 232b) so as to be in contact with the semiconductor layer 251, the oxygen concentration in the region 271a (region 271b) may be reduced. Furthermore, a metal compound layer containing a metal contained in the conductive layer 232a (conductive layer 232b) and a component of the semiconductor layer 251 may be formed in the region 271a (region 271b). Furthermore, the region 271a (region 271b) may have a high concentration of impurities such as hydrogen, nitrogen, and metal elements. In such cases, the carrier concentration in the region 271a (region 271b) increases, and the region 271a (region 271b) becomes a low-resistance region. That is, the source region and the drain region are n-type regions (low-resistance regions) having a higher carrier concentration than the channel formation region.

[0485] On the other hand, the channel formation region has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0486] The carrier concentration in the channel formation region is 1×10 １８ cm −３ Below, 1 x 10 １７ cm −３ Less than 1 x 10 １６ cm −３ Less than 1 x 10 １５ cm −３ Less than 1 x 10 １４ cm −３ Less than 1 x 10 １３ cm −３ Less than 1 x 10 １２ cm −３ Less than 1 x 10 １１ cm −３ Less than or 1 x 10 １０ cm −３ The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 −９ cm −３ It can be said that:

[0487] Note that when the carrier concentration of the semiconductor layer 251 is reduced, the impurity concentration in the semiconductor layer 251 is reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic. Note that an oxide semiconductor (or a metal oxide) having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor (or a metal oxide).

[0488] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration of the channel formation region in the semiconductor layer 251. In addition, in order to reduce the impurity concentration of the semiconductor layer 251, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that the impurities in the semiconductor layer 251 refer to, for example, elements other than the main components constituting the semiconductor layer 251. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0489] Furthermore, it may be difficult to clearly detect the boundaries between regions in the semiconductor layer 251. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may not necessarily vary stepwise from region to region, but may also vary continuously within each region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in regions closer to the channel formation region.

[0490] In a transistor using an oxide semiconductor for the semiconductor layer 251, impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, and the transistor's electrical characteristics are likely to fluctuate, which may result in poor reliability. Ｏ H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to be normally on. Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V ＯIt is preferable that H be reduced as much as possible. In other words, it is preferable that the carrier concentration of a channel formation region in the oxide semiconductor be reduced and that the channel formation region be i-type (intrinsic) or substantially i-type.

[0491] In response to this problem, an insulating layer containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed. This allows oxygen to be supplied from the insulating layer to the oxide semiconductor, thereby eliminating oxygen vacancies and V Ｏ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 200 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulating layer to the oxide semiconductor diffuses into a conductive layer such as a gate electrode, a source electrode, or a drain electrode, the conductive layer may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0492] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. Ｏ It is also preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions, and to reduce the V Ｏ It is preferable to prevent the amount of H from being excessively reduced. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductive layer 233, the conductive layer 232a, the conductive layer 232b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductive layer 233, the conductive layer 232a, the conductive layer 232b, and the like. Note that hydrogen in the oxide semiconductor is converted into V Ｏ H can be formed, so V Ｏ To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0493] 20A and 20B , the side surfaces of the conductive layers 232a and 232b facing the conductive layer 233 have a substantially perpendicular shape. Note that the transistor 200 shown in FIGS. 20A and 20B is not limited thereto, and the angle formed between the side surface and the bottom surface of the conductive layers 232a and 232b may be 10° to 80°, preferably 30° to 60°. Furthermore, the opposing side surfaces of the conductive layers 232a and 232b may have a plurality of surfaces.

[0494] Note that the transistor 200 has a structure in which two layers, the semiconductor layer 251a and the semiconductor layer 251b, are stacked in the region where a channel is formed (hereinafter also referred to as the channel formation region) and in the vicinity thereof; however, the present invention is not limited to this. For example, the semiconductor layer 251b may have a single-layer structure or a stacked structure of three or more layers. Furthermore, each of the semiconductor layer 251a and the semiconductor layer 251b may have a stacked structure of two or more layers.

[0495] The conductive layer 233 functions as a first gate electrode (sometimes referred to as a top gate electrode or a front gate electrode) of the transistor, and as described above, the conductive layer 232a and the conductive layer 232b function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 233 is formed so as to be embedded in the opening of the insulating layer 213 and in the region sandwiched between the conductive layer 232a and the conductive layer 232b. Here, the conductive layer 233, the conductive layer 232a, and the conductive layer 232b are formed in a self-aligned manner with respect to the opening of the insulating layer 213. That is, in the transistor 200, the first gate electrode can be disposed between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductive layer 233 can be formed without providing a margin for alignment, which reduces the area occupied by the transistor 200. This allows the density of arithmetic cells in the arithmetic device to be increased.

[0496] Note that the transistor 200 can be formed by forming an island-shaped stack of layers over an insulating layer 262, the stack of layers including an insulating layer 263 (described later), a semiconductor layer 251, and a conductive layer that will become the conductive layer 232a and the conductive layer 232b. Next, an insulating layer 282 and an insulating layer 213 (collectively referred to here as an interlayer film) are stacked in this order above the island-shaped stack of layers and above the insulating layer 262. An opening is then formed in the interlayer film that overlaps the island-shaped stack of layers, and an insulating layer 264 and a conductive layer 233 are provided in this order in the opening. In particular, it is preferable to simultaneously form the conductive layer 232a and the conductive layer 232b by forming an opening in the interlayer film. In this specification, a transistor structure in which an opening reaching the island-shaped stack of layers and an interlayer film are formed in the interlayer film, and a conductive layer that will become the first gate electrode of the transistor is provided to fill the opening is referred to as a GL structure. Such a structure may also be called a TGSA structure.

[0497] 20A and 20B , the conductive layer 233 is shown as having a two-layer structure. Here, the conductive layer 233 preferably includes a conductive layer 233a and a conductive layer 233b disposed on the conductive layer 233a. For example, the conductive layer 233a is preferably disposed so as to surround the bottom and side surfaces of the conductive layer 233b. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 233a.

[0498] The conductive layer 233a is preferably made of a conductive material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms, or a conductive material that has a function of suppressing diffusion of oxygen.

[0499] Furthermore, since the conductive layer 233a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 233b caused by oxygen contained in the insulating layer 213, etc. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0500] The conductive layer 233b is preferably a conductive layer with high conductivity. For example, the conductive layer 233b can be formed using a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 233b may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0501] For the conductive layers 232a and 232b, it is preferable to use, for example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layers 232a and 232b. When a conductive material containing metal and nitrogen is used for the conductive layers 232a and 232b, the conductive layers 232a and 232b become conductive layers containing at least metal and nitrogen. For example, a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion can be selected from the materials that can be used for the conductive layers 233a and 233b described above.

[0502] For example, the conductive layers 235a and 235b are preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.

[0503] Furthermore, for example, the conductive layer 235 a and the conductive layer 235 b can have a stacked structure including a plurality of layers. In particular, it is preferable to stack a conductive material having a function of suppressing permeation of impurities such as water and hydrogen and a material with high conductivity.

[0504] The conductive layer 231 may function as a second gate electrode (also referred to as a bottom gate electrode or a back gate electrode). In this case, the potential applied to the conductive layer 231 may be changed independently of the potential applied to the conductive layer 233, thereby reducing the threshold voltage V ｔｈ In particular, by applying a negative potential to the conductive layer 231, the V ｔｈTherefore, when a negative potential is applied to the conductive layer 231, the drain current when the potential applied to the conductive layer 233 is 0 V can be made smaller than when no negative potential is applied.

[0505] The conductive layer 231 is preferably provided to be larger than the channel formation region in the semiconductor layer 251. In particular, as shown in Fig. 20B, the conductive layer 231 preferably extends as a wiring also in a region outside the end portion intersecting with the channel width direction of the semiconductor layer 251. That is, outside the side surface of the semiconductor layer 251 in the channel width direction, the conductive layer 231 and the conductive layer 233 preferably overlap with each other with an insulating layer interposed therebetween.

[0506] 20A , the conductive layer 233 preferably includes a conductive layer 233a provided inside the insulating layer 264 and a conductive layer 233b provided so as to be embedded inside the conductive layer 233a. Although the conductive layer 233 is shown as having a two-layer stacked structure in FIGS. 20A and 20B , the present invention is not limited to this. For example, the conductive layer 233 may have a single-layer structure or a stacked structure of three or more layers.

[0507] 20A and 20B , the transistor 200 preferably includes an insulating layer 211 disposed on a substrate (not shown), an insulating layer 281 disposed on the insulating layer 211, an insulating layer 212 disposed on the insulating layer 281, a conductive layer 231 disposed so as to be embedded in the insulating layer 212, an insulating layer 261 disposed on the insulating layer 212 and the conductive layer 231, an insulating layer 262 disposed on the insulating layer 261, and an insulating layer 263 disposed on the insulating layer 262. A semiconductor layer 251 a is preferably disposed on the insulating layer 263.

[0508] 20A and 20B, an insulating layer 282 is preferably disposed between the insulating layer 262, the insulating layer 263, the semiconductor layer 251a, the semiconductor layer 251b, the conductive layer 232a, and the conductive layer 232b and the insulating layer 213. Here, the insulating layer 282 is preferably in contact with the side surfaces of the insulating layer 264, the top and side surfaces of the conductive layer 232a, the top and side surfaces of the conductive layer 232b, the side surfaces and top surfaces of the semiconductor layer 251a, the semiconductor layer 251b, and the insulating layer 263, and the top surface of the insulating layer 262, as shown in FIG.

[0509] An insulating layer 283 and an insulating layer 214 which function as interlayer films are preferably provided over the transistor 200. Here, the insulating layer 283 is preferably provided in contact with top surfaces of the conductive layer 233, the insulating layer 264, and the insulating layer 213. In this case, the top surface of the insulating layer 213 is preferably planarized.

[0510] It is preferable to provide a conductive layer 235 (conductive layer 235a and conductive layer 235b) that is connected to the transistor 200 and functions as a plug. For this reason, the conductive layer 235 is provided in contact with the sidewalls of the openings of the insulating layer 282, the insulating layer 213, the insulating layer 283, and the insulating layer 214. In particular, a first conductive layer of the conductive layer 235 may be provided in contact with the sidewalls, and a second conductive layer of the conductive layer 235 may be provided on a side surface of the first conductive layer. Here, the height of the top surface of the conductive layer 235 can be made approximately the same as the height of the top surface of the insulating layer 214.

[0511] Specifically, for example, a first conductive layer of the conductive layer 235a is provided in contact with one sidewall of two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 235a is formed in contact with the side surface thereof. Note that the conductive layer 232a is located in part of the bottom of the opening, and the conductive layer 235a is in contact with the conductive layer 232a. Similarly, for example, a first conductive layer of the conductive layer 235b is provided in contact with the other sidewall of two openings of the insulating layer 214, the insulating layer 283, the insulating layer 213, and the insulating layer 282, and a second conductive layer of the conductive layer 235b is formed in contact with the side surface thereof. Note that the conductive layer 232b is located in part of the bottom of the opening, and the conductive layer 235b is in contact with the conductive layer 232b.

[0512] Note that although the transistor 200 shows a structure in which the first conductive layer of the conductive layer 235 and the second conductive layer of the conductive layer 235 are stacked, the present invention is not limited to this. For example, the conductive layer 235 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by assigning ordinal numbers to the order of formation.

[0513] 20B , in a region of the semiconductor layer 251b that does not overlap with the conductive layer 232, in other words, in the channel formation region of the semiconductor layer 251, the side surface of the semiconductor layer 251 is arranged to be covered with the conductive layer 233. This makes it easier for the electric field of the conductive layer 233, which functions as the first gate electrode, to act on the side surface of the semiconductor layer 251, and as a result, the channel formation region of the semiconductor layer 251 can be electrically surrounded by the electric field of the conductive layer 233. This increases the on-state current of the transistor 200 and improves its frequency characteristics.

[0514] For example, the insulating layer 213 preferably has a lower dielectric constant than the insulating layer 262. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layer 213 preferably uses, as a material with a low dielectric constant, one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, and silicon oxide having vacancies.

[0515] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0516] The upper surfaces of the insulating layers 213 may be planarized, so that the insulating layers 213 also function as planarizing films.

[0517] As described above, the insulating layer 213 can be formed using a material similar to that of the insulating layer 212 .

[0518] <<Constituent Materials of Transistor>> Next, the materials that constitute the transistor 200 will be described.

[0519] [Metal Oxide (Oxide Semiconductor)] A metal oxide functioning as an oxide semiconductor including a channel formation region is preferably used for the transistor 200. In particular, indium oxide described in Embodiment 4 is suitable as the metal oxide.

[0520] Note that in the following, not only indium oxide but also various metal oxides that form a channel formation region of the transistor 200 will be described.

[0521] The metal oxide to be used for the channel formation region of the transistor 200 preferably has a band gap of, for example, 2 eV or more, preferably 2.5 eV or more. Specifically, in the case of the transistor 200 in FIGS. 20A and 20B, the semiconductor layer 251 preferably includes a metal oxide that functions as an oxide semiconductor.

[0522] Note that the structure of a metal oxide can be divided into a single crystal structure and other structures (non-single crystal structures). Examples of non-single crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures may be used. However, the use of a crystalline metal oxide, typified by a CAAC structure or an nc structure, is preferable because a highly reliable semiconductor device can be obtained.

[0523] As described in the above embodiment, the metal oxide preferably contains at least indium. In particular, it is preferable that it contains indium and zinc. In addition to these, it is preferable that the element M is contained. The element M can be one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, it is preferable that the element M is one or more selected from aluminum, gallium, yttrium, and tin. It is even more preferable that the element M contains one or both of gallium and tin.

[0524] Examples of the metal oxide include indium oxide (also referred to as In oxide, IO, or indium oxide), gallium oxide (also referred to as Ga oxide or gallium oxide), zinc oxide (also referred to as Zn oxide or zinc oxide), indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide), gallium zinc oxide (Ga—Zn oxide, also referred to as “GZO”), and aluminum zinc oxide. Examples of usable oxides include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as "AZO"), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as "IGZO"), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as "IGZTO"), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as "IGAZO" or "IAGZO"). Alternatively, silicon-containing indium tin oxide, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), and the like can be used.

[0525] As described above, the metal oxide preferably contains indium. Specifically, it is preferable to use indium oxide as the metal oxide. It is particularly preferable to use crystalline indium oxide.

[0526] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, a film with high crystallinity or high film density can be formed. Furthermore, when the metal oxide is formed by ALD, atoms can be deposited layer by layer, which has the advantages of enabling film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. After the metal oxide is formed, it is preferable to perform an impurity removal treatment to remove impurities (typically, impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of impurity removal treatments include plasma treatment, microwave plasma treatment, and heat treatment.

[0527] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0528] 20A and 20B , a conductive layer functioning as a source electrode or a drain electrode, for example, the conductive layer 232 a and the conductive layer 232 b shown in FIG. 20A and 20B , is preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, an alloy containing two or more of the above metal elements, or an alloy combining two or more of the above metal elements. Furthermore, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used for the conductive layer. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. In addition, the conductive layer may be made of a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element (e.g., phosphorus), or a silicide (e.g., nickel silicide).

[0529] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may also be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may also be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0530] For the conductive layer functioning as the second gate electrode, for example, the conductive layer 231 shown in Figures 20A and 20B, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms is preferably used. Alternatively, a conductive material having a function of suppressing the diffusion of oxygen is preferably used. In particular, examples of conductive materials having a function of suppressing the diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide.

[0531] In addition to the above, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.

[0532] The conductive layer functioning as the first gate electrode, for example, the conductive layer 232 shown in Figures 20A and 20B, is preferably a conductive layer having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferably a conductive material having a function of suppressing the diffusion of oxygen. Examples of conductive materials having a function of suppressing the diffusion of oxygen include tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Furthermore, by providing a conductive material containing oxygen as the conductive layer, oxygen desorbed from the conductive material is more easily supplied to the channel formation region.

[0533] The conductive layer functioning as the first gate electrode is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductive layer also functions as a wiring, it is preferable to use a conductive layer with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductive layer may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive material.

[0534] The conductive layer may be formed using, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon. The conductive layer may be formed using, for example, indium gallium zinc oxide containing nitrogen. The use of such a material may allow hydrogen contained in the metal oxide in which the channel is formed to be captured. Alternatively, hydrogen introduced from an outer insulating layer or the like may be captured.

[0535] [Insulating Layer] Examples of the insulating layer 281, the insulating layer 261, the insulating layer 262, the insulating layer 263, the insulating layer 282, and the insulating layer 283 included in the transistor 200 include an insulating oxide, a nitride, an oxynitride, a nitride oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide.

[0536] The insulating layer 281 that can be provided in the transistor preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the semiconductor layers of the transistor M1, the transistor M3, and the transistor M4 from the substrate side. Similarly, the insulating layer 283 that can be provided in the transistor preferably functions as a barrier insulating film that prevents impurities such as water and hydrogen from entering the semiconductor layer of the transistor 200 from above the circuit layer OMAL. Therefore, the insulating layer preferably uses an insulating material that has a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of preventing the diffusion of oxygen (i.e., through which the oxygen is less likely to permeate).

[0537] Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include, for example, insulating layers containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used as a single layer or a stack. Specifically, examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers that suppress the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0538] The second gate insulating film in contact with the metal oxide contained in the channel formation region, for example, the insulating layers 261 to 263 shown in FIGS. 20A and 20B, preferably has oxygen released therefrom by heating. In this specification, oxygen released by heating may be referred to as excess oxygen. For example, silicon oxide or silicon oxynitride is preferably used as appropriate for the second gate insulating film. By providing an insulating layer containing oxygen in contact with the metal oxide, oxygen vacancies in the metal oxide can be reduced, and the reliability of the transistor can be improved.

[0539] Specifically, it is preferable to use an oxide material from which part of oxygen is released by heating as the insulating layer. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted into oxygen atoms by thermal desorption spectrometry (TDS) is 1.0×10 １８ atoms / cm ３ or more, preferably 1.0 × 10 １９ atoms / cm ３More preferably, 2.0×10 １９ atoms / cm ３ or more, or 3.0 x 10 ２０ atoms / cm ３ The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C. or 100° C. to 400° C. In particular, by performing the TDS analysis at a temperature in the range of 100° C. to 700° C., the amount of released oxygen in accordance with the manufacturing process of a transistor can be evaluated.

[0540] Furthermore, the insulating layer included in the transistor may preferably contain an oxide of one or both of aluminum and hafnium, which are insulating materials. Examples of insulating layers containing an oxide of one or both of aluminum and hafnium include aluminum oxide and hafnium oxide. Another example is an oxide containing aluminum and hafnium (hafnium aluminate). When such a material is used to form an insulating layer around a transistor, the insulating layer can function as a layer that suppresses oxygen release and the intrusion of impurities such as hydrogen from the periphery of the transistor into the metal oxide.

[0541] Furthermore, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to an insulating layer included in a transistor. Alternatively, these insulating layers may be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulating layer.

[0542] The insulating layer included in the transistor may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ) or (Ba,Sr)TiO ３ An insulating layer containing a so-called high-k material such as (BST) may be used as a single layer or a laminate.

[0543] 20A and 20B , an insulating layer serving as a first gate insulating film, for example, the insulating layer 264, is preferably disposed in contact with the upper surface of the metal oxide. The insulating layer can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having vacancies. Silicon oxide and silicon oxynitride are particularly preferred because they are stable to heat.

[0544] 18, which illustrates a structural example of an arithmetic device that is a semiconductor device of one embodiment of the present invention, the transistors M1, M3, and M4 each have a GL structure. Note that the structures of the transistors M1, M3, and M4 according to one embodiment of the present invention are not limited thereto. The transistors M1, M3, and M4 according to one embodiment of the present invention may each have the structure of a vertical channel transistor described below, for example.

[0545] 21A to 21C show examples of the configuration of a vertical channel transistor. In a vertical channel transistor, the source electrode and the drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction. In other words, the channel length direction can be said to have a component in the height direction (vertical direction).

[0546] Note that the transistors illustrated in FIGS. 21A to 21C may also be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, or the like, other than vertical channel transistors.

[0547] In this specification, in a vertical channel transistor, one of the source electrode and the drain electrode located at the bottom may be referred to as a bottom electrode, and the other of the source electrode and the drain electrode located at the top may be referred to as an top electrode.

[0548] In particular, Fig. 21A shows a schematic plan view of an example of a transistor 300, which is a vertical channel transistor, and Figs. 21B and 21C show schematic cross-sectional views of the transistor 300. Fig. 21B is a schematic cross-sectional view taken along dashed line A1-A2 in Fig. 21A, and Fig. 21C is a schematic cross-sectional view taken along dashed line A3-A4 in Fig. 21A. Fig. 21B shows an excerpt of the transistor included in the circuit layer OMAL. Fig. 22 shows a schematic perspective view of the transistor 300 shown in Figs. 21A to 21C and the surrounding wiring.

[0549] The transistor 300 shown in FIGS. 21A-21C can be substituted for transistors in a GL structure, such as the transistors M1, M3, and M4 shown in FIG.

[0550] The structure of a transistor 300, which is a vertical channel transistor, will be described with reference to FIGS. 21A to 21C and 22. FIG.

[0551] As an example, the transistor 300 includes a conductive layer 331 that functions as a wiring or an electrode, a conductive layer 332 that functions as a wiring or an electrode, a semiconductor layer 351 that is an active layer of the transistor 300, an insulating layer 361 that functions as a gate insulating film of the transistor 300, a conductive layer 333 that functions as a gate of the transistor 300, and a conductive layer 334 that functions as a wiring.

[0552] The conductive layer 331 is provided above the insulating layer 311, which functions as an interlayer film. The conductive layer 331 extends along the direction of the dashed dotted line A3-A4 in the schematic plan view of Fig. 21A, and thereby functions as a wiring.

[0553] For example, a conductive layer that can be applied to the above-described transistors M1, M3, and M4 can be used for the conductive layer 331. The same applies to conductive layers 332 to 334 described later.

[0554] An insulating layer 312 functioning as an interlayer film and a conductive layer 332 are formed in this order on the insulating layer 311 and the conductive layer 331. The conductive layer 332 extends along the direction of the dashed dotted line A1-A2 in the schematic plan view of Fig. 21A, and thereby functions as a wiring.

[0555] Furthermore, openings reaching the conductive layer 331 are formed in the insulating layer 312 and the conductive layer 332 in regions overlapping with the conductive layer 331. A semiconductor layer 351 is formed on the side surfaces and bottom of the openings. That is, the semiconductor layer 351 is formed on the top surface of the conductive layer 331, the side surfaces of the insulating layer 312, and the side surfaces of the conductive layer 332. The semiconductor layer 351 is also formed on part of the top surface of the conductive layer 332. An insulating layer 361 is provided so as to be in contact with the conductive layer 332, the semiconductor layer 351, and the insulating layer 312 inside and outside the openings. A conductive layer 333 is formed on the top surface and side surfaces of the insulating layer 361 so as to fill the openings.

[0556] An insulating layer 313 functioning as an interlayer film is formed on the top surface of the insulating layer 361 and the top surface of the conductive layer 333. An opening reaching the conductive layer 333 is formed in the insulating layer 313 in a region overlapping with the conductive layer 333. A conductive layer 334 is embedded in the side surface and bottom of the opening. Note that part of the conductive layer 334 may be formed on the top surface of the insulating layer 313. The insulating layer 314 functioning as an interlayer film is formed on the insulating layer 313 and the conductive layer 334.

[0557] The conductive layer 334 extends along the direction of the dotted line A3-A4 in the schematic plan view of FIG. 21A, and thus functions as a wiring.

[0558] For example, an insulating material with a low dielectric constant is preferably used for the insulating layers 311 to 314. By using an insulating material with a low dielectric constant as an interlayer film, parasitic capacitance occurring between wirings can be reduced. For this reason, the insulating layers 311 to 314 can each be made of a material that can be used for the insulating layer 212 or the insulating layer 213 described above.

[0559] The insulating layer 361 has a function as a gate insulating film, and therefore, for example, a material that can be used for the insulating layer 264 can be used for the insulating layer 361 .

[0560] Part of the conductive layer 331 functions as one of the source electrode and the drain electrode of the transistor 300. Part of the conductive layer 332 functions as the other of the source electrode and the drain electrode of the transistor 300. Part or all of the conductive layer 333 functions as a gate electrode of the transistor 300.

[0561] As described above, by forming the insulating layer, the conductive layer, and the semiconductor layer, a vertical channel transistor can be formed in which the channel length direction has a component in the height direction (vertical direction). The channel length of the transistor 300 depends on the film thickness of the insulating layer 312. The thinner the insulating layer 312, the shorter the channel length, and therefore the larger the on-current of the transistor 300 can be. On the other hand, the thicker the insulating layer 312, the longer the channel length, and therefore the smaller the off-current of the transistor 300 can be.

[0562] Furthermore, the wirings connected to the source, drain, or gate of the vertical channel transistor are not formed in the same process but in different processes. As a result, the wirings connected to the source, drain, or gate of the vertical channel transistor have overlapping regions in a plan view. Since the wirings connected to the source, drain, or gate of the vertical channel transistor are provided at different heights, the parasitic capacitance generated in each wiring can be reduced. This allows the driving frequency of the transistor 300 to be increased and the driving speed of the arithmetic unit CDVA, etc. to be increased.

[0563] <<Configuration Example of Capacitor Element>> In FIG. 18, a flat-plate type capacitative element is shown as the capacitative element C1, but the arithmetic device CDVA can be provided with a capacitative element other than a flat-plate type capacitative element.

[0564] 23A and 23B show a capacitive element 400 which is a vertical capacitive element, rather than the flat capacitive element shown in Fig. 18. Note that Fig. 23A shows a schematic cross-sectional view of the capacitive element 400, and Fig. 23B shows a schematic plan view of the capacitive element 400.

[0565] 23A includes, as an example, a portion of conductive layer 431, a portion of conductive layer 432, a portion of conductive layer 433, and insulating layer 441. Note that FIG. 23A excerpts conductive layer 434, insulating layer 411, insulating layer 412, insulating layer 413, and insulating layer 414 as materials formed around capacitor element 400. Also, FIG. 23B is a plan view schematic diagram taken along dashed-dotted line B1-B2 in FIG. 23A , and shows insulating layer 412, conductive layer 432, insulating layer 441, and conductive layer 433. Also, the dashed line in FIG. 23B represents an edge 473 of conductive layer 433 provided on insulating layer 441.

[0566] The conductive layer 431 functions as a wiring for connecting to one of a pair of electrodes of the capacitor 400. For the conductive layer 431, the description of the conductive layer 331 in FIGS.

[0567] Part of the conductive layer 432 functions as one of a pair of electrodes of the capacitor 400, part of the conductive layer 433 functions as the other of the pair of electrodes of the capacitor 400, and the insulating layer 441 functions as a dielectric of the capacitor 400. For example, the conductive layer 431 can be formed using a material that can be used for the conductive layer 331 in FIGS. 21A to 21C and 22. For the conductive layer 432, a material that can be used for the conductive layer 331 or the conductive layer 334 can be used.

[0568] The insulating layer 441 functions as a dielectric of the capacitive element 400. For example, it is preferable to use a material with a high dielectric constant (high-k) for the insulating layer 441. Specifically, as one example, a high dielectric constant material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium zirconium oxide can be used for the insulating layer 441. Alternatively, as another example, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use hafnium oxide having an amorphous structure. Furthermore, as another example, lead zirconate titanate (PZT), strontium titanate (SrTiO ３ ), or (Ba,Sr)TiO ３ By using a high dielectric constant material for the dielectric of the capacitance element C1, the capacitance value can be increased, and the potential written in the capacitance element C1 can be held for a long period of time.

[0569] The capacitive element 400 can be a ferroelectric capacitor by using a material that can have ferroelectricity for the insulating layer 441. Unlike paraelectric materials, materials that can have ferroelectricity maintain their internal dielectric polarization even when no voltage is applied (this is sometimes called remanent polarization).

[0570] Moreover, a conductive layer 434 is formed on the conductive layer 433 .

[0571] The insulating layer 411 functions as a base film for forming the conductive layer 431. The insulating layer 412 functions as an interlayer film for separating the conductive layer 431 and the conductive layer 432. The insulating layer 413 functions as an interlayer film for forming a conductive layer 434, which functions as a wiring, above the conductive layer 433. Note that the insulating layer 413 has openings in regions where the conductive layers 433 and 434 overlap, and the conductive layers 433 and 434 are connected through the openings. The insulating layer 414 is an interlayer film provided above the conductive layer 434. Note that the descriptions of the insulating layers 311 to 314 in FIGS. 21B and 21C can be referred to for the insulating layers 411 to 414, respectively.

[0572] The capacitor 400 shown in FIG. 23A illustrates a configuration in which the upper surface of the conductive layer 431 has a recess. The recess can be formed by forming an opening in the insulating layer 412. Therefore, it can be said that the opening includes the side surface of the insulating layer 412 and the bottom surface of the recess in the conductive layer 431. Therefore, the side surface of the insulating layer 412 may be referred to as the side surface of the opening, and the recess in the conductive layer 431 may be referred to as the bottom of the opening. Furthermore, the side wall of the opening includes the side surface of the insulating layer 412. In particular, FIG. 23A illustrates a first region 471 below the opening and a second region 472 above the opening as the side surface of the insulating layer 412. Furthermore, each of the first region 471 and the second region 472 can be said to be the side surface of the opening. Note that the side wall of the opening may also include the side surface of the recess in the conductive layer 431.

[0573] The conductive layer 431 has a recess at a position overlapping with the opening of the insulating layer 412, which increases the contact area between the conductive layer 431 and the conductive layer 432 compared to when the conductive layer 431 does not have the recess. This reduces the contact resistance between the conductive layer 431 and the conductive layer 432, which will be described later.

[0574] The conductive layer 432 has a region with rounded corners within the recess of the conductive layer 431. By having this region within the recess, electric field concentration in the insulating layer 441 near this region can be suppressed more effectively than, for example, when the recess has a right angle or an acute angle (a corner). Furthermore, the end of the conductive layer 432 is located at a position lower in height from the reference plane than the top surface of the insulating layer 412. In other words, the conductive layer 432 is located in a first region 471 of the opening of the insulating layer 412. Furthermore, the insulating layer 441 is provided on the top surface of the conductive layer 432, a second region 472 of the opening of the insulating layer 412, and the top surface of the insulating layer 412. Furthermore, the conductive layer 433 is provided on the insulating layer 441 so as to fill the opening of the insulating layer 412.

[0575] Since the end of the conductive layer 432 is positioned on the side surface of the opening of the insulating layer 412, electric field concentration in the insulating layer 441 near the end can be suppressed. As described above, suppressing electric field concentration in the insulating layer 441 suppresses dielectric breakdown of the insulating layer 441, and a highly reliable computing device can be provided. Furthermore, since the capacitor 400 has a pair of electrodes provided in the opening of the insulating layer 412, the circuit area of ​​the capacitor 400 in a planar view is smaller than that of a flat capacitor. Therefore, by using the capacitor 400 shown in FIG. 23A as the capacitor included in the circuit, the area of ​​the circuit can be reduced.

[0576] For example, in the arithmetic device CDVA described in the above embodiment, by using the above-described capacitor 400 as the capacitor C1, leakage current between the pair of electrodes of the capacitor C1, which occurs between the gate of the transistor M1 and the wiring XCL, can be prevented. Therefore, in the arithmetic device CDVA, fluctuations in the gate potential of the transistor M1 due to the leakage current can be prevented, and the gate potential of the transistor M1 can be maintained for a long period of time. Furthermore, localized electric field concentration on the dielectric of the capacitor C1 can be suppressed, thereby improving the reliability of the gate of the transistor M1. Furthermore, since the area of ​​the capacitor C1 in a plan view can be reduced, the circuit area of ​​the arithmetic device CDVA can be reduced. This also leads to a reduction in the circuit area of ​​the arithmetic device CDVA.

[0577] The capacitance value of the capacitor 400 is proportional to the area of ​​a region where the conductive layer 432, the insulating layer 441, and the conductive layer 433 overlap each other. This region can be, for example, a region where the conductive layer 432 and the insulating layer 441 are in contact with each other. Therefore, the height d from the bottom of the opening in the insulating layer 412 to the edge of the conductive layer 432 provided on the side surface of the opening is Ｕ The area of ​​the region can be increased by increasing the length d. Ｋ When this is the case, d Ｕ is d Ｋ For example, d Ｕ is d Ｋ In order to obtain the effect of suppressing electric field concentration in the insulating layer 441 at the end portion of the conductive layer 432 or its vicinity, it is preferable that the ratio of d Ｕ is d Ｋ It is preferable that the value is 95% or less or 85% or less of d Ｕ For example, Ｋ It is preferable that the ratio is 80% or more and 85% or less, or 80% or more and 95% or less.

[0578] Furthermore, the capacitance value of the capacitance element 400 is inversely proportional to the distance between the conductive layer 432 and the conductive layer 433, for example, in the schematic plan view of FIG. 23B . Specifically, the capacitance value is inversely proportional to the film thickness of the insulating layer 441. Therefore, in the schematic cross-sectional view of FIG. 23A or the schematic plan view of FIG. 23B , the film thickness of the insulating layer 441 is preferably 100 nm or less, more preferably 50 nm or less, and even more preferably 10 nm or less. Furthermore, to increase the voltage resistance of the capacitance element 400, the film thickness of the insulating layer 441 is preferably 1 nm or more, more preferably 5 nm or more, and even more preferably 10 nm or more. Therefore, the film thickness of the insulating layer 441 is preferably 2 nm or more and 8 nm or less, or 8 nm or more and 12 nm or less, for example.

[0579] Note that this embodiment mode can be appropriately combined with the same or other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with another configuration, structure, method, etc. described in this embodiment mode. Furthermore, for example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0580] Embodiment 4 In this embodiment, indium oxide that can be used as the metal oxide of the channel formation region of the IO transistor according to one embodiment of the present invention described in the above embodiment will be described.

[0581] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0582] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0583] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 24A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 24B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0584] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 24B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 24A (see Non-Patent Document 3). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 24A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 24A.

[0585] 24A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0586] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0587] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0588] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0589] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 24A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0590] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0591] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0592] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0593] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0594] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0595] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0596] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0597] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0598] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0599] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 24C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0600] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0601] Furthermore, as shown in FIG. 24C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the film and is released as water molecules.

[0602] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0603] The table below shows the properties of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in the table below, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, because the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in the table below, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0604]

[0605] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0606] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0607] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0608] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0609] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide f...

Claims

1. A device comprising a voltage generation circuit, a first drive circuit, and an arithmetic cell, wherein the voltage generation circuit has a plurality of first output terminals, the first drive circuit has a first selector circuit, a first transistor, and a switch, the first selector circuit has a plurality of first input terminals, a second input terminal, and a second output terminal, the first input terminal is electrically connected to the first output terminal, the second output terminal is electrically connected to the gate of the first transistor, one of the source and drain of the first transistor is electrically connected to a first terminal of the switch, and the second terminal of the switch is electrically connected to the arithmetic cell, the voltage generation circuit has a function of generating a plurality of analog potentials by a resistive voltage division method and outputting the analog potentials to the first output terminal, and the first selector circuit has a function of providing first digital data to the second input terminal, thereby bringing one of the plurality of first input terminals and the second output terminal into a conductive state in accordance with the first digital data, the first transistor has a function of generating a first current having an amount corresponding to the analog potential applied to a gate of the first transistor, and the arithmetic cell has a function of holding a first potential corresponding to the first current.

2. A semiconductor device according to claim 1, comprising a second drive circuit and a drive cell, wherein the second drive circuit comprises a second selector circuit and a second transistor, wherein the second selector circuit comprises a plurality of third input terminals, a fourth input terminal and a third output terminal, wherein the third input terminals are electrically connected to each of the first output terminals, and the third output terminal is electrically connected to the gate of the second transistor, and one of the source and drain of the second transistor is electrically connected to each of the arithmetic cell and the drive cell, wherein the second selector circuit has a function of bringing one of the plurality of fourth input terminals and the third output terminal into a conductive state in accordance with the second digital data when second digital data is provided to the fourth input terminal, wherein the second transistor has a function of generating a second current of an amount corresponding to the analog potential provided to the gate of the second transistor, and wherein the drive cell has a function of maintaining a second potential corresponding to the second current.

3. A semiconductor device according to claim 2, wherein the arithmetic cell has a function of outputting, as a third current, a result of multiplication of the ratio of the third digital data to the second digital data and the first digital data when the second digital data input to the fourth input terminal changes to third digital data.

4. The semiconductor device according to claim 3, wherein the first transistor and the second transistor each have an oxide containing indium as an oxide semiconductor in a channel formation region.

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