Quantum error correction on quantum hardware systems

Abstract

In a method for implementing quantum error correction, QEC, on a quantum hardware system, a QEC code for encoding logical qubits of a logical quantum circuit in physical qubits is determined, using a subsystem hypergraph product code construction on a first and a second classical error-correction code. The logical quantum circuit is executed on the quantum hardware system, using the determined QEC code. Each of the first and second classical error-correction codes belongs to a family of classical error-correction codes.

Description

QUANTUM ERROR CORRECTION QUANTUM HARDWARE SYSTEMS Cross-Reference to Related

[0001] This application claims priority from US application No.63 / 670,620 filed 12 July 2024 and entitled QUANTUM ERROR CORRECTION ON QUANTUM HARDWARE SYSTEMS which is hereby incorporated herein by reference for all purposes. For purposes of the United States of America, this application claims the benefit under 35 U.S.C. §119 of US application No.63 / 670,620 filed 12 July 2024 and entitled QUANTUM ERROR CORRECTION ON QUANTUM HARDWARE SYSTEMS which is hereby incorporated herein by reference for all purposes. Field

[0002] This disclosure generally relates to methods, devices, and systems for implementing quantum error correction (QEC) on a quantum hardware system. In particular, the disclosure relates to methods and devices for implementing QEC on quantum hardware systems, and to information processing systems. Background

[0003] Quantum computers are prone to physical errors, which can cause incorrect outcomes when executing a logical quantum circuit. The reason is that quantum states are highly vulnerable to errors arising from various sources such as environmental noise, fluctuations in a control system, imperfect gate operations, and decoherence.

[0004] To mitigate this risk, QEC codes can be employed. These codes map a logical quantum circuit, designed to run on ^^ logical qubits onto a physical quantum circuit utilizing ^^ physical qubits, where ^^ is larger than ^^. By distributing quantum information across the additional qubits, redundancy is introduced, allowing the system to identify and correct errors that occur during computation.

[0005] QEC codes can detect and correct errors without measuring the actual quantum information directly, thus preserving the quantum state. Through syndrome measurements and error-correcting procedures, the system can determine which errors occurred and apply the necessary corrections to restore the intended quantum state.

[0006] Implementing QEC is crucial for the development of scalable and reliable quantum computers. Accordingly, there is a need for highly efficient implementation of QEC codes on quantum hardware systems.Summary

[0007] The present disclosure has several aspects, including methods and devices for implementing QEC on a quantum hardware system, and information processing systems.

[0008] A first aspect of the disclosure provides a method for implementing QEC on a quantum hardware system. A QEC code for encoding logical qubits of a logical quantum circuit in physical qubits is determined, using a subsystem hypergraph product code construction on a first and a second classical error-correction code. The logical quantum circuit is executed on the quantum hardware system, using the determined QEC code. Each of the first and second classical error-correction codes belongs to a family of classical error-correction codes. Each classical error-correction code of the family of classical error-correction codes is for encoding logical bits in physical bits. For each code in the family of classical error-correction codes, there is a plurality of physical classical circuits for operating on the physical bits. Each physical classical circuit corresponds to a logical reversible XOR circuit operating on the logical bits. For the family of classical error-correction codes, depth indicators of the physical classical circuits are, as a function of a number of the logical bits encoded by the classical error-correction codes, bounded by a first constant. A depth indicator of a physical classical circuit denotes a depth of the physical classical circuit, wherein permutations of the physical bits are disregarded for determining the depth.

[0009] Using the determined QEC code to execute the logical quantum circuit can result in more efficient execution of the logical quantum circuit. This is a result of a combination of the type of construction used to construct the QEC code from classical codes and the type of classical codes used in the construction.

[0010] Using the subsystem hypergraph product code construction has the advantage that the QEC code has efficient implementations of any logical CNOT circuits for which the first and second classical codes have efficient implementations of corresponding logical reversible XOR circuits. The first and second classical codes have efficient implementations of at least one logical reversible XOR circuit because the depth indicators of the physical circuits that implement the logical reversible XOR circuits for codes in the family of classical error correction codes are bound by a first constant. That is, the depth indicators of the logical reversible XOR circuits do not grow with the size of the classical code, i.e., with the number of logical (or physical) bits. As a result, there is at least one logical CNOT circuit for which the QEC code willhave a low-depth physical operator This enables more efficient execution of logical quantum circuits in QEC code.

[0011] According to an embodiment of the method for implementing QEC on a quantum hardware system, for each code in the family of classical error-correction codes, at least one linear transformation for operating on the logical bits can be expressed as a sum of binary matrices, each binary matrix representing a respective logical reversible XOR circuit in the logical reversible XOR circuits. Herein, the at least one linear transformation for operating on the logical bits is a linear transformation other than a logical reversible XOR circuit. A number of summands in each respective sum of binary matrices, as a function of a number of the logical bits encoded by the classical error-correction codes, is bounded by a second constant. In some embodiments, the at least one linear transformation for operating on the logical bits can be expressed as a sum of at least two of the binary matrices.

[0012] This enables efficient implementation of a wider variety of logical quantum circuits because the determined QEC code has efficient physical operator implementations of a greater number of logical CNOT circuits. In particular, as described above, the first and second classical codes having physical circuits that implement the logical reversible XOR circuits with depth indicators bounded by a first constant means the determined QEC code has an efficient physical operator implementation for at least one first logical CNOT circuit. The first and second classical codes having at least one linear transformation that is expressible as a sum of the binary matrices with a number of summands bounded by a second constant means that the determined QEC code has an efficient physical operator implementation for at least one second logical CNOT circuit, in which the at least one second logical CNOT circuit may be constructed from the at least one first logical CNOT circuit.

[0013] In general, a quantum mechanical operation on one or more qubits is described by a unitary operator. An important class of unitary operators is described by the Pauli group. The single-qubit Pauli group ^^1is the group of Pauli operators that can each act on the qubit. There are 16 PauliUp to a complex phase, there are 3 distinct non-trivial operators, the Pauli ^^,^^, and ^^ operators. The single- qubit Pauli group ^^1is formed by all products of the Pauli ^^,^^, and ^^ operators.

[0014] Accordingthis specification, the term “^^-qubit Pauli group ^^^^” (or simply: “Pauli group”) denotes the group formed by all length ^^ tensorof elements ofthe single-qubit Pauli group ^^1, where ^^ integer greater than 1. The Pauli group is a non-Abelian group, i.e., group elements in general do not commute. The elements of the ^^-qubit Pauli group are denoted as Pauli operators.

[0015] According to this specification, the term “QEC code” can be understood as being defined by specifying a code space. Herein, a code space is a vector subspace of a Hilbert space which is spanned by so-called code words of the QEC code. A code word is a state which encodes some data. A code word corresponds to a logical state of the QEC code. A QEC code is used to protect quantum information that is processed in the computation from errors due to quantum noise, e.g., decoherence.

[0016] A QEC code is in general a mapping of ^^ qubits onto ^^ qubits, where ^^ > ^^.The quantum states on ^^ qubits are elements of a Hilbert space of dimension 2^^. The quantum states on ^^ qubits are elements of a Hilbert space of dimension 2^^. Herein, the ^^ qubits are the “logical qubits” or “encoded qubits” that are to be protected from error, e.g., a threshold amount of error. The ^^ qubits are the “physical qubits”implementing the logical qubits. The additional ^^ − ^^ qubits allow the ^^ logical qubitsto be stored in a redundant fashion so that the encoded information is less susceptible to noise or other disturbances.

[0017] A QEC code with block size ^^, encoded qubits ^^, and distance ^^ is denoted as an “[[^^,^^,^^]] QEC code”, where the distance ^^ is the minimum support of a non- identity logical operator in the code. The distance ^^ sets a bound on the number of errors the QEC code can detect and correct. For example, if there are fewer than ^^−1 ⌊ 2 ⌋ errors, a perfect decoder can identify and correct these errors without changing ^^−1 the intended quantum state. On the other hand, if there are more than ⌊ 2 ⌋ errors, a perfect decoder may be unable to correct all the errors.

[0018] The QEC code can be provided by the user. In particular, the QEC code can be a stabilizer code ^^.

[0019] According to this specification, a “stabilizer code” denotes a QEC code defined by a set ^^ of mutually commuting Hermitian Pauli operators that does not contain the negative of the identity operator, −^^.

[0020] According to this specification, the term “Pauli stabilizers,” S, denotes the commuting Hermitian Pauli operators that define the associated stabilizer code ^^. This collection forms a subgroup of the full Pauli group. In particular, the compositionof two Pauli stabilizers produces another stabilizer. Each Pauli stabilizer is an ^^ qubit gate.

[0021] In the case of a Calderbank-Shor-Steane (CSS) stabilizer code (CSS code), the group S of Pauli stabilizers is determined by binary matrices ^^^^and ^^^^: S= {^^^^^^^^  :  ^^ ∈ RowSpan(^^^^),  ^^ ∈ RowSpan(^^^^)}.

[0022] For more general codes, the group S of Pauli stabilizers is determined by asingle matrix ^^ comprising ^^ − ^^ rows, each of length 2^^:S = {^^^^^^^^  :  (^^|^^) ∈ RowSpan(^^)}.

[0023] More specifically, the code words ^^ ∈ ^^ of the stabilizer code are the ^^ qubitstates (i.e. vectors in the Hilbert space ℋ of dimension 2^^) that are unchanged when any Pauli stabilizer is applied. The code words are therefore the fixed points of the Pauli stabilizers.

[0024] The Pauli stabilizers can be used to detect unwanted errors. For a given code word, a detectable error will transform the code word to a different vector in the Hilbert space ℋ of dimension 2^^that is no longer a fixed point of the Pauli stabilizers. By determining which Pauli stabilizers still fix the vector, the error can be identified and corrected.

[0025] According to this specification, the term “Clifford group” denotes the group of so-called Clifford operators which are unitary operators that preserve the Pauli group under conjugation. This means that the ^^-qubit Clifford group ^^ℓ^^is the set of all operators ^^ that map Pauli operators ^^ in the ^^-qubit Pauli group ^^^^to other Pauli operators in the ^^-qubit Pauli group ^^^^under conjugation: ^^ℓ^^ = {^^: ^^^^^^† ∈ ^^^^ , ∀^^ ∈ ^^^^}.

[0026] The ^^-qubit Clifford group ^^ℓ^^is said to “normalize” the ^^-qubit Pauli group ^^^^. The fact that the Clifford operators map Pauli operators to other Pauli operatorsconjugation makes the Clifford operators easier to to describe. Up to a phase, a Clifford operator ^^ can be described by the images of the 2^^ Pauli operators ^^^^and ^^^^under conjugation by ^^. A Clifford operator can therefore be described by a 2^^ ×(2^^ + 1) matrix (with one column tracking signs) which is much more efficient than ageneral unitary operator which can only be fully described by a 2^^ × 2^^ matrix.

[0027] For example, conjugating the Pauli ^^ operator by the Hadamard gate ^^ givesthe Pauli ^^ operator: ^^^^^^† = ^^.

[0028] Similar relations hold for the other ^^,^^ operators. The Hadamard gate ^^ is an example of a Clifford operator.

[0029] The Clifford group is generated by the Hadamard gate ^^, the phase gate ^^, and the ^^^^^^^^ gate. Herein, a list of gates or operators is said to “generate” a larger collection of gates or operators, if every element of the larger collection can be composed as products of elements from the list of gates. These compositions may be arbitrarily long and may contain repetitions.

[0030] Every element of the Clifford group is uniquely specified (up to a phase) by specifying where the Clifford operator maps a generating set of the Pauli group under conjugation. Advantageously, the Clifford group requires only a single additional gate to form a universal gate set.

[0031] The Hadamard gate ^^, the phase gate ^^, and the ^^^^^^^^ gate generate other Clifford group elements such as the Controlled-^^ gate (denoted as ^^^^ gate) and the SWAP gates.

[0032] According to this specification, the term “logical quantum circuit” denotes a quantum computation. The logical quantum circuit generally comprises a sequence of operations, such as quantum gates, measurements, and initializations of logical qubits to predefined values. Herein, logical quantum gates are basic blocks that operate on a small number of logical qubits.

[0033] In order to implement the logical quantum circuit, the logical qubits are implemented by (a generally larger number of) physical qubits of the quantum hardware system.

[0034] According to the specification, a “physical operator implementation” of a logical operator denotes a physical gate or more generally a sequence of physical gates that implement the logical operator. The physical gates are not necessarily already gates acting on hardware physical qubits of a specific quantum hardware. Rather, the physical gates can act on “physical” (or virtual) qubits of a virtual circuit which is implemented on a physical circuit (i.e., a specific quantum hardware system) at a subsequent stage.

[0035] According to this specification, the “depth” of a physical quantum circuit denotes the number of layers of quantum gates of the physical quantum circuit that are applied sequentially, such that quantum gates within the same layer can be executed in parallel. In other words, it is the length of the longest path from the input to the output of the circuit, counting only those layers where quantum gates areapplied. The depth of a physical quantum reflects the time complexity of executing the physical quantum circuit on quantum hardware system, with lower depth typically indicating faster execution and potentially lower susceptibility to decoherence and other noise.

[0036] According to this specification, the “depth indicator” of a physical classical circuit denotes the depth of the physical classical circuit disregarding permutations of the physical bits of the physical circuit. That is, permutations of the physical bits are not taken into account when determining the depth. Herein, the “depth” of a physical circuit denotes the number of layers of classical gates of the physical classical circuit that are applied sequentially, such that classical gates within the same layer can be executed in parallel. Because permutations are ignored for determining the depth indicator of the physical classical circuit, a permutation does not affect and increase the depth indicator of the physical classical circuit. Physical classical circuits consisting only of permutations have a depth indicator of zero.

[0037] In other words, the depth indicator of the physical classical circuit is a depth up to a permutation, i.e., permutations are excluded. This depth of the physical classical circuit up to a permutation is the relevant quantity because it influences the depths of the circuits in the physical operator implementation for the constructed QEC. In particular, an increase in the number of permutations in the classical physical circuits for the classical error-correction codes used to construct a QEC code does not correspond to an increase in the depth of the physical operator implementations for that code and can therefore be ignored.

[0038] According to the method for implementing QEC on a quantum hardware system, the depth indicators of the physical classical circuits are bounded if considered as a function of the number of the logical bits. This can also be expressed in terms of asymptotic notation. The depth indicator ^^ as a function of the number ^^ of the logical bits of the classical error-correction codes is a function of order zero, i.e., it does not grow with the number of the logical bits (i.e., the size of the classical error- correction code). This can be expressed as: ^^(^^) = ^^(1) .

[0039] Likewise, in some embodiments, the number ^^ of summands in each respective sum of binary matrices, as a function of the number ^^ of the logical bits encoded by the classical error-correction codes is a function of order zero, i.e., it does not grow with the number of the logical bits:^^(^^) = ^^(1) .

[0040] According to this specification, the term “logical reversible XOR gate” denotes a reversible version of the Boolean exclusive OR (XOR) gate. The logical reversibleXOR gate has two binary inputs ^^ and ^^ and provides two binary outputs ^^ and ^^ ⊕^^, where ⊕ denotes bit-wise addition. The truth table of the logical reversible XOR gate can be given as follows: input output ^^ ^^ ^^ ^^ ⊕ ^^0 0 0 0 0 1 0 1 1 0 1 1 1 1 1 0

[0041] The logical reversible XOR gate is the classical analogue of the controlled NOT (CNOT) gate (i.e., controlled bit-flip gate or controlled Pauli-X gate) of quantum circuits.

[0042] According to this specification, the term “logical reversible XOR circuit” denotes a classical circuit that consists of at least one logical reversible XOR gate.

[0043] According to this specification, the term “logical CNOT circuit” denotes a quantum circuit that consists of at least one logical CNOT gate.

[0044] According to this specification, the term “linear transformation” relates to a linear operator of the classical code.

[0045] According to this specification, the term “classical error-correction code” relates to an algorithm for encoding data such that any errors which are introduced can be detected and corrected based on redundancy introduced by the encoding. That is, a classical error-correction code includes redundancy to the original data, allowing the system to identify and correct a limited number of errors without needing to retransmit the data. A classical error-correction code ^^ can be classified by parameters (^^,^^,^^), where ^^ denotes the length of the codewords (i.e., the number of logical bits in each codeword), ^^ denotes the dimension of the code (i.e., the number of physical bits in each codeword), and ^^ denotes the minimum distance between any two distinct codewords (i.e., the smallest number of bit changes needed to transform one codeword into another).

[0046] According to this specification, the term “subsystem hypergraph product code” relates to a QEC code which is generated according to the subsystem hypergraphproduct code construction based on two error-correction codes. According to the subsystem hypergraph product code the QEC codes are associatedwith quantum logical operators ^^ ⊗ ^^ operating on logical qubits. Herein, ^^ is aclassical logical operator of the first classical error-correction code and ^^ is a classical logical operator of the second classical error-correction code.

[0047] According to this specification, the term “subsystem code” (or subsystem QEC code) denotes a QEC code wherein information is encoded in a subsystem of a code space.

[0048] According to this specification, the term “hypergraph” denotes a generalization of a graph in which an edge can join any number of vertices.

[0049] According to this specification, the term “product code” denotes a QEC code which is based on a tensor product of two codes.

[0050] According to an embodiment of the method for implementing QEC on a quantum hardware system, the physical classical circuits correspond to automorphisms of the classical error-correction code. Herein, an automorphism is a permutation of the classical physical bits that preserves the code space of the classical error-correction code, i.e., maps code words to other code words.

[0051] According to an embodiment of the method for implementing QEC on a quantum hardware system, the family of classical error-correction codes is the family of simplex codes. Each classical error-correction code in the family of simplex codes may be specified by a parameter ^^ (the order of the simplex code) and is for encoding^^ logical bits in 2^^ − 1 physical bits. The parameter ^^ is an integer. Classical simplexcodes automatically fulfill the criteria on the depth indicator (i.e., depth indicators of the simplex circuits are, as a function of the number of the logical bits encoded by the simplex codes, bounded by a first constant) and on the number of summands (i.e., a number of summands in each respective sum of binary matrices, as a function of the number of the logical bits encoded by the simplex codes, is bounded by a second constant).

[0052] According to an embodiment of the method for implementing QEC on a quantum hardware system, the physical classical circuits comprise permutations of the physical bits. Permutations are not considered for determining the depth indicator, i.e., physical classical circuits which comprise only permutations have a depth indicator of zero, i.e., have a constant depth indicator and the depth indicator does not depend on the code size.

[0053] According to an embodiment of for implementing QEC on a quantum hardware system, the depth of the physical classical circuits are zero. This is the case for physical classical circuits consisting of permutations.

[0054] According to an embodiment of the method for implementing QEC on a quantum hardware system, the first and second classical error-correction codes belong to two different families of classical error-correction codes.

[0055] According to an embodiment of the method for implementing QEC on a quantum hardware system, the first and second classical error-correction codes belong to the same family of classical error-correction codes. In particular, both classical error-correction codes can be simplex codes.

[0056] According to an embodiment of the method for implementing QEC on a quantum hardware system, the first and second classical error-correction codes are identical. For example, both classical error-correction codes are simplex codes of the same order ^^.

[0057] According to an embodiment of the method for implementing QEC on a quantum hardware system, executing the logical quantum circuit comprises mapping the logical quantum circuit to a physical quantum circuit, and executing the physical quantum circuit. In other embodiments, the logical quantum circuit is transmitted to another entity (e.g., a controller of the quantum hardware device), and the other entity executes the logical quantum circuit.

[0058] According to an embodiment of the method for implementing QEC on a quantum hardware system, mapping the logical quantum circuit to the physical quantum circuit comprises mapping a logical Hadamard gate on each logical qubit in the logical quantum circuit to a physical Hadamard gate implemented on each physical qubit and a permutation of two or more of the logical qubits. In particular, a traversal Hadamard operation and a permutation can be implemented. This implementation of a Hadamard gate using a transversal Hadamard operation and a permutation is available for any subsystem hypergraph product code constructed using identical first and second classical error-correction codes. This implementation is advantageous because transversal gates do not spread errors between qubits.

[0059] The permutation of the two or more of the logical qubits may be implemented by a physical quantum gate (e.g. using a SWAP gate or a physical CNOT circuit that implements the permutation) or by a classical operation (e.g. in software). Implementing the permutation of the two or more logical qubits classically isparticularly advantageous as it enables the logical Hadamard gate more quickly and reliably.

[0060] According to this specification, the term “logical Hadamard gate” denotes agate which maps the logical qubit basis states |0^, |1^ as follows:|0^ | ^| ^ + 10 →, √2 .

[0061] The logical Hadamard gate a rotation about the following unit axis:^̂^+^̂^ √2 , where ^̂^ and ^̂^ are unit axes of a system.

[0062] According to an embodiment of for implementing QEC on a quantum hardware system, determining the QEC code comprises the selection of the QEC code out of a plurality of QEC codes which differ in the first classical error- correction code and / or second classical error-correction code of the subsystem hypergraph product code construction. The selection can be based on the type of application, e.g., based on the logical quantum circuit which is to be run on the quantum hardware device. For example, a user may select the specific QEC code.

[0063] According to an embodiment of the method for implementing QEC on a quantum hardware system, determining the QEC code comprises determining the QEC code based on a predefined selection of the QEC code. The QEC code can be stored in a memory and can be retrieved during physical implementation of the logical quantum circuit.

[0064] According to an embodiment of the method for implementing QEC on a quantum hardware system, determining the QEC code comprises determining the QEC code based on a user input. The user may specify the family of classical error- correction codes for at least one of the first and second classical error-correction code or may select a family member of a pre-defined family of classical error-correction codes.

[0065] According to an embodiment of the method for implementing QEC on a quantum hardware system, the at least one linear transformation comprises all linear transformations for operating on the logical bits. The at least one linear transformation can form the algebra of all binary matrices operating on the logical bits. This enablesefficient implementation of a wider variety logical quantum circuits because the determined QEC code has efficient of all logical CNOT circuits.

[0066] According to an embodiment of the method for implementing QEC on a quantum hardware system, the at least one linear transformation comprises all linear transformations operating on a subset of the logical bits. The at least one linear transformation can form a subalgebra of the algebra of all binary matrices operating on the logical bits. In this case, the QEC code will have efficient physical operator implementations on a subset of the logical qubits. This may allow for, for example, efficient implementation of a logical quantum circuit that has the same number of logical qubits as the subset of logical qubits.

[0067] According to an embodiment of the method for implementing QEC on a quantum hardware system, mapping the logical quantum circuit to a physical quantum circuit comprises replacing a quantum logical operator in the logical quantum circuit with a physical operator implementation for at least implementing at least one logical CNOT circuit operating on control qubit(s) and target qubit(s). The logical CNOT circuit is implemented such that the control qubit(s) are located in a first code block of physical qubits, and the target qubit(s) are located in a second code block of physical qubits. That is, the logical CNOT circuits comprise one or more constituent logical CNOT operators in which the control qubit(s) for the one or more logical constituent CNOT operators are in the first code block and the target qubit(s) of the logical constituent CNOT operators are in the second code block.

[0068] According to the specification, the term “code block” relates to a block comprising one or more logical qubits that an instance of a QEC code operates on. For example, a code block for an instance of the [[7,1,3]]-Steane code may comprise 7 physical qubits and 1 logical qubit, i.e., the 7 physical qubits map to 1 logical qubit. QEC can be performed within a code block. For example, at least one syndrome can be measured by performing measurements on the qubits in a code block. Logical quantum circuits can be divided into many code blocks because of the large number of logical qubits that may be required in a logical quantum circuit. Performing syndrome measurements across smaller blocks of these logical qubits can be more efficient than performing measurements across all of the logical qubits.

[0069] Having control qubits in a first code block and target qubits in a second code block can be particularly useful for distributed quantum computing, i.e., if the quantum hardware system is a modular quantum hardware system.

[0070] According to this specification, the “modular quantum hardware system” relates to a quantum hardware system a plurality of modules or sub-units which can be physically separate entities, e.g., arranged on different chips. The modules are interconnected. For example, inter-modular operations can be performed by entangling physical qubits on different modules, e.g., using photon-mediated entanglement. The first code block can be implemented on one module of the modular quantum hardware system and the second code block can be implemented on another module of the modular quantum hardware system. The implementation with few cross-module CNOTs avoids operations between modules and reduces run- time costs.

[0071] According to an embodiment of the method for implementing QEC on a quantum hardware system, the quantum logical operator comprises a logical CNOT operator within one of the first code block or the second code block. That is, the quantum logical operator may comprise an in-block logical CNOT operator. According to this specification, the term “in-block” denotes a logical operation within one code block and the term “two-block” (i.e., “block-to-block”) denotes logical operations between two code blocks.

[0072] The logical CNOT operator may have control qubit(s) and target qubit(s) in the first block, or control qubit(s) and target qubit(s) in the second code block, or vice versa. Another of the first code block and the second code block comprises an auxiliary code block. That is, mapping the logical quantum circuit to the physical quantum circuit may comprise replacing a logical CNOT operator for operating within a particular code block with a physical operator implementation for implementing at least one logical CNOT circuit between that particular code block and an auxiliary code block.

[0073] According to an embodiment of the method for implementing QEC on a quantum hardware system, the auxiliary code block starts in an all positive or all zero logical state, and the physical operator implementation is for implementing a measurement on the one of the first code block or the second code block (i.e., not on the auxiliary code block), a correction based on a value of the measurement, and the at least one logical CNOT circuit.

[0074] According to an embodiment of the method for implementing QEC on a quantum hardware system, at least two logical CNOT circuits are implemented, andthe physical operator implementation is on the auxiliary code block having an all positive or all zero logical state, the at least two logical CNOT circuits.

[0075] According to an embodiment of the method for implementing QEC on a quantum hardware system, the quantum logical operator comprises a logical diagonal Clifford operator within the first code block or the second code block. The other of the first code block and the second code block comprises an auxiliary code block. That is, a logical in-block diagonal Clifford circuit for operating within a particular code block may be implemented by a physical operator implementation for implementing at least one logical CNOT circuit between that particular code block and an auxiliary code block.

[0076] According to an embodiment of the method for implementing QEC on a quantum hardware system, the physical operator implementation is for implementing, on the auxiliary code block having an all positive or all zero logical state, two iterations of: a measurement on the one of the first code block and the second code block, a correction based on a value of the measurement, and the at least one logical CNOT circuit. The physical operator implementation may implement an in-block diagonal Clifford circuit.

[0077] According to an embodiment of the method for implementing QEC on a quantum hardware system, the physical operator implementation is for implementing, on the auxiliary code block having an all positive or all zero logical state, at least two logical CNOT circuits. The physical operator implementation may implement an in- block diagonal Clifford circuit.

[0078] According to an embodiment of the method for implementing QEC on a quantum hardware system, the quantum logical operator comprises a logical diagonal Clifford operator between the first code block and the second code block. The physical operator implementation is for implementing a logical Hadamard transformation of the at least one logical CNOT circuit, a physical diagonal circuit within the first code block and a physical diagonal circuit within the second code block. The physical operator implementation may implement a two-block diagonal Clifford circuit.

[0079] According to an embodiment of the method for implementing QEC on a quantum hardware system, the quantum logical operator comprises a logical Hadamard operator on a logical qubit within the first code block or the second code block. The physical operator implementation is for implementing two or more logicaldiagonal operators on the logical qubit, by one or more logical Hadamard operators on all logical qubits within the one of the first code block or the second code block. The physical operator implementation may implement an arbitrary Hadamard gate. For example, a Hadamard gate ^^^^acting on a particular qubit ^^ can be implemented using a sequence of all-qubit Hadamard gates and diagonal circuits.

[0080] According to an embodiment of the method for implementing QEC on a quantum hardware system, the quantum hardware system is a modular quantum hardware system. The physical qubits of the first code block are in a first module of the modular quantum hardware system. The physical qubits of the second code block are in a second module of the modular quantum hardware system.

[0081] A second aspect of the disclosure provides a computer program product comprising executable program code configured to, when executed by a computing device, perform the method for implementing QEC on a target quantum hardware system according to the first aspect.

[0082] A third aspect of the disclosure provides a non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method for implementing QEC on a target quantum hardware system according to the first aspect.

[0083] A fourth aspect of the disclosure provides a device for implementing QEC on a quantum hardware system, comprising at least one processor, and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to determine a QEC code for encoding logical qubits of a logical quantum circuit in physical qubits, using a subsystem hypergraph product code construction on a first and a second classical error-correction code. The processor further generates a control signal for controlling the quantum hardware system to execute the logical quantum circuit on the quantum hardware system, using the determined QEC code. Each of the first and second classical error-correction codes belongs to a family of classical error-correction codes. Each classical error-correction code of the family of classical error-correction codes is for encoding logical bits in physical bits. For each code in the family of classical error-correction codes, there is a plurality of physical classical circuits for operating on the physical bits. Each physical classical circuit corresponds to a logical reversible XOR circuit operating on the logical bits. For thefamily of classical error-correction codes, depth indicators of the physical classical circuits are, as a function of a number of logical bits encoded by the classical error-correction codes, bounded by a first constant. The depth indicators of the physical classical circuits denote depths of the physical classical circuits disregarding permutations of the physical bits.

[0084] A fifth aspect of the disclosure provides an information processing system comprising a quantum hardware system, at least one processor communicatively coupled to the quantum hardware system, and at least one tangible computer- readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to determine a QEC code for encoding logical qubits of a logical quantum circuit in physical qubits, using a subsystem hypergraph product code construction on a first and a second classical error-correction code. The processor further generates a control signal for controlling the quantum hardware system to execute the logical quantum circuit on the quantum hardware system, using the determined QEC code. Each of the first and second classical error-correction codes belongs to a family of classical error-correction codes. Each classical error-correction code of the family of classical error-correction codes is for encoding logical bits in physical bits. For each code in the family of classical error- correction codes, there is a plurality of physical classical circuits for operating on the physical bits, wherein each physical classical circuit corresponds to a logical reversible XOR circuit operating on the logical bits. For the family of classical error- correction codes, depth indicators of the physical classical circuits are, as a function of a number of the logical bits encoded by the classical error-correction codes, bounded by a first constant. The depth indicators of the physical classical circuits denote depths of the physical classical circuits disregarding permutations of the physical bits.

[0085] A sixth aspect of the disclosure provides a method for implementing QEC on a quantum hardware system. A logical quantum circuit is executed on the quantum hardware system, using a QEC code for encoding logical qubits of the logical quantum circuit in physical qubits. The QEC code is constructed using a subsystem hypergraph product code construction on a first classical simplex code and a second classical simplex code.

[0086] According to an embodiment of for implementing QEC on a quantum hardware system, the first simplex code is identical to the second classical simplex code.

[0087] According to an embodiment of the method for implementing QEC on a quantum hardware system, the first classical simplex code differs from the second classical simplex code.

[0088] A seventh aspect of the disclosure provides a computer program product comprising executable program code configured to, when executed by a computing device, perform the method for implementing QEC on a quantum hardware system according to the sixth aspect.

[0089] An eighth aspect of the disclosure provides a non-transitory, computer- readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method for implementing QEC on a quantum hardware system according to the sixth aspect.

[0090] A ninth aspect of the disclosure provides a device for implementing QEC on a quantum hardware system, comprising at least one processor, and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to generate a control signal for controlling the quantum hardware system to execute a logical quantum circuit on the quantum hardware system, using a QEC code for encoding logical qubits of the logical quantum circuit in physical qubits. The QEC code is constructed using a subsystem hypergraph product code construction on a first classical simplex code and a second classical simplex code.

[0091] A tenth aspect of the disclosure provides an information processing system comprising a quantum hardware system, at least one processor communicatively coupled to the quantum hardware system, and at least one tangible computer- readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to generate a control signal for controlling the quantum hardware system to execute a logical quantum circuit on the quantum hardware system, using a QEC code for encoding logical qubits of the logical quantum circuit in physical qubits. The QEC code is constructed using asubsystem hypergraph product code on a first classical simplex code and a second classical simplex code.

[0092] An eleventh aspect of the disclosure provides a method including the steps of: determining a QEC code for encoding logical qubits of a logical quantum circuit in physical qubits, using a subsystem hypergraph product code construction on a first and a second classical error-correction code; and estimating a quantity of resources required to execute the logical quantum circuit on a quantum hardware system, using the determined QEC code. Each of the first and second classical error-correction codes belongs to a family of classical error-correction codes, wherein each classical error-correction code of the family of classical error-correction codes is for encoding logical bits in physical bits. For each code in the family of classical error-correction codes: there is a plurality of physical classical circuits for operating on the physical bits, wherein each physical classical circuit corresponds to a logical reversible XOR circuit operating on the logical bits. For the family of classical error-correction codes: depth indicators of the physical classical circuits are, as a function of a number of the logical bits encoded by the classical error-correction codes, bounded by a first constant, wherein the depth indicators of the physical classical circuits denote depths of the physical classical circuits disregarding permutations of the physical bits.

[0093] In some embodiments, the method further comprises designing the quantum hardware system based on the estimated quantity of resources.

[0094] A twelfth aspect of the disclosure provides a method including the steps of estimating a quantity of resources required to execute a logical quantum circuit on a quantum hardware system, using a QEC code for encoding logical qubits of the logical quantum circuit in physical qubits, wherein the QEC code is constructed using a subsystem hypergraph product code construction on a first classical simplex code and a second classical simplex code.

[0095] In some embodiments, the method further comprises designing the quantum hardware system based on the estimated quantity of resources.

[0096] A thirteenth aspect of the disclosure provides a computer program product comprising executable program code configured to, when executed by a computing device, perform the method according to the eleventh aspect or the twelfth aspect.

[0097] A fourteenth aspect of the disclosure provides a non-transitory, computer- readable storage medium comprising executable program code configured to, whenexecuted by a computing device, perform method according to the eleventh aspect or the twelfth aspect.

[0098] A fifteenth aspect of the disclosure provides a device comprising at least one processor; and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor- executable instructions which, when executed by the at least one processor, cause the at least one processor to perform the method according to the eleventh aspect or the twelfth aspect.

[0099] The disclosure relates to all combinations of the above features, even if these are recited in different aspects or different claims. In particular, the devices for implementing QEC on a quantum hardware system may be configured to perform each or a combination of the described embodiments of the respective method for implementing QEC on a quantum hardware system. Brief description of the drawings

[0100] In the following, further aspects and exemplary embodiments will be described with reference to the accompanying drawings. However, the present disclosure is not limited to the described exemplary embodiments and may be modified in various different ways. Consequently, the drawings and description are intended to be illustrative in nature and not limiting. Fig.1 schematically shows a block diagram illustrating an information processing system according to an embodiment of the disclosure; Fig.2 shows a flow diagram illustrating a method for implementing QEC on a quantum hardware system according to an embodiment of the disclosure; Fig.3 schematically illustrates a quantum circuit implementing a state teleportation operation; Fig.4 schematically illustrates a quantum circuit for implementing an in-block CNOT logical operator; Fig.5 schematically illustrates another quantum circuit for implementing an in- block CNOT logical operator; Fig.6 schematically illustrates a quantum circuit implementing a state teleportation operation; Fig.7 schematically illustrates a quantum circuit for implementing an in-block CNOT logical operator;Fig.8 schematically illustrates quantum circuit for implementing an in- block CNOT logical operator; Fig.9 schematically illustrates a quantum circuit implementing a SWAP operation; Fig.10 schematically illustrates a quantum circuit for implementing an in-block CNOT logical operator; Fig.11 schematically illustrates another quantum circuit for implementing an in- block CNOT logical operator; Fig.12 schematically illustrates a quantum circuit implementing a SWAP operation; Fig.13 schematically illustrates another quantum circuit for implementing an in- block CNOT logical operator; Fig.14 schematically illustrates another quantum circuit for implementing an in- block CNOT logical operator; Fig.15 schematically illustrates a quantum circuit for implementing an in-block logical diagonal Clifford operator; Fig.16 schematically illustrates another quantum circuit for implementing an in- block logical diagonal Clifford operator; Fig.17 schematically illustrates another quantum circuit for implementing an in- block logical diagonal Clifford operator; Fig.18 schematically illustrates another quantum circuit for implementing an in- block logical diagonal Clifford operator; Fig.19 schematically illustrates a quantum circuit for implementing a Hadamard gate. Fig.20 schematically illustrates another quantum circuit for implementing a Hadamard gate; Fig.21 shows a flow diagram illustrating a method for implementing QEC on a quantum hardware system according to an embodiment of the disclosure; Fig.22 shows an action of a permutation operating on physical bits; and Fig.23 shows an action of the permutation operating on logical bits.Detailed description

[0101] Figure 1 schematically shows a diagram illustrating an information processing system 100. The information processing system 100 comprises a quantum hardware system 400 with a plurality of interconnected chips or modules 401. The quantum hardware system 400 is a physical device or machine which can be used to implement algorithms (e.g., a quantum computer). The quantum hardware system 400 comprises coupling devices 402 for coupling the modules 401. The coupling devices 402 can comprise optical links or one or more optical networks to connect the modules 401.

[0102] Whereas the quantum hardware system 400 in Figure 1 is a modular quantum hardware system, the specification is not restricted to this case. In other embodiments, the quantum hardware system 400 has only a single chip or module 401.

[0103] The quantum hardware system 400 operates the multiple modules 401 when executing a quantum process and can perform “intra-modular” and “inter-modular” operations. The term “intra-modular operation” relates to operations (e.g. gates) between physical qubits of the same module 401. The term “inter-modular operation” relates to operations (e.g. gates) between physical qubits of different modules 401. In certain applications, it can be advantageous to link multiple modules 401 instead of building ever-larger monolithic quantum supercomputers (i.e., having only a single chip or module). Herein, the modules 401 are separate components with quantum hardware systems. Different modules can be spatially separated.

[0104] The quantum hardware system 400 can be a non-locally connected quantum hardware system, as described in Simmons, “Scalable Fault-Tolerant Quantum Technologies with Silicon Colour Centres”, arXiv:2311.04858, 2023, and in Afzal et al., “Distributed Quantum Computing in Silicon”, arXiv: 2406.01704, which are hereby incorporated by reference in their entirety.

[0105] The modules 401 may comprise a plurality of physical qubits having first and second quantum states that can be used to represent quantum information and which can exist in a quantum superposition.

[0106] Both the modules 401 and the coupling devices 402 comprise hardware components such as optical paths, optical links, optical networks, grating couplers, optical switches, Bell State Analyzers (BSAs) and / or detectors for facilitating optical connection between the physical qubits of the modules 401. Accordingly, the couplingdevices 402 may be configured to optical coupling between the modules 401. In other embodiments, the modules 401 can be coupled non-optically. Similarly, inter-modular connections can be optical or non-optical. In some embodiments, there can be both optical and non-optical connections. Intra-module connections may comprise optical interconnects, microwave interconnects, physical ion transport, and the like. Inter-modular connections (i.e., the coupling devices 402) can comprise optical interconnects, microwave interconnects (with or without microwave to optical transduction), and the like.

[0107] Optical links can be used in connecting the physical qubits of the modules 401 with switches and detectors and can further connect switches and detectors to each other. Similarly, the switches can be controlled to select specific optical links for connecting a physical qubit of the modules 401 to at least one other physical qubit of the modules 401, either of the same module 401 or of another module 401. In some embodiments, by controlling the hardware components in a suitable manner, any pair of physical qubits of the modules 401 may be connected to each other.

[0108] The detectors can be used in generating entanglement between the physical qubits of the modules 401 based on a photon detection pattern of photon states associated with said physical qubits of the modules 401. The entanglement may be generated according to an entanglement protocol, such as the Barrett-Kok protocol.

[0109] The physical qubits of the modules 401 can be matter qubits or photonic qubits. Examples comprise luminescent defects, trapped ions, trapped atoms, neutral atoms, superconducting qubits, quantum dots, quantum wells, nuclear spins within dissolved molecules, trapped atoms coupled to high-finesse cavities, Bose-Einstein condensates, and the like.

[0110] The quantum hardware system 400 may comprise a photon interface (photonic interface). One possible example is a spin-photon interface. Spins generally have long coherence times, so information can be stored for long times. For example, the quantum hardware system 400 may comprise a semiconductor body with luminescent defects which form the physical qubits of the modules 401. The semiconductor body may comprise silicon or similar semiconductor materials. For example, the semiconductor material may include natural silicon, silicon carbide, silicon germanium, isotopically purified paramagnetic silicon, a so-called silicon vacuum or combinations thereof. The semiconductor body may be processed to remove a large fraction of non-paramagnetic isotopes (e.g., silicon-29). The semiconductor body maycomprise enriched or purified silicon that been processed to remove some to nearly all non-zero-nuclear spin as silicon-29. Purified silicon includes material enriched to various levels of silicon-28, such as, 99%, 99.9%, and 99.99%. Purified silicon includes material enriched with silicon-28. Purified silicon includes silicon where spectroscopic linewidths are at least ten to hundred times sharper than in natural silicon. The semiconductor body may also comprise an epilayer of isotopically purified silicon, grown on top of a natural silicon wafer.

[0111] The luminescent defects may comprise luminescence centres or colour centres. The luminescent defects may comprise radiation damage centres. The luminescent defects may comprise T centres, as described in any of US 2022 / 0366290 A1, US 2022 / 0327416 A1, and US 2024 / 0012749 A1, which are hereby incorporated by reference in their entirety.

[0112] The physical qubits of the modules 401 can be connected via a plurality of optical connections. Each optical connection provides a path that connects a pair of physical qubits of the modules 401 and enables performing operations between these physical qubits. Different optical connections may comprise different hardware components, i.e., different routes including switches, detectors, and the like. In particular, the number of switches, detectors, and the like can vary for different optical connections.

[0113] In embodiments where the physical qubits of the modules 401 are associated with T centres, pairs of T centres may be optically connected by means of a telecom photonic interface (i.e., operating in the telecom frequency band, such as the telecom O-band) of the T centre in the silicon substrate. In some embodiments, each T centre can be optically connected to any other T centre, i.e., all-to-all optical connection between the T centres is possible. The optical connection between a pair of T centres may comprise at least one photonic waveguide integrated in the silicon substrate (“on-chip”). In addition or alternatively, the optical connection can also comprise optical fibres or other components which can be external to the silicon substrate (“off- chip”). In particular, the modules 401 can be arranged in different chips and the coupling devices 402 can comprise at least some off-chip hardware components for coupling physical qubits on different modules 401.

[0114] The optical connection may be configured to facilitate entanglement between T centres. The entanglement can be generated and / or distributed by photons which are transmitted over the optical connections connecting the T centres. The quantumhardware system 400 can be configured maximally entangled Bell pairs, using the T centres.

[0115] The quantum hardware system 400 may further include means for generating and applying pulses for manipulating the state of physical qubits of the modules 401. The quantum hardware system 400 may be used for any practical application in quantum sensing, quantum computing or quantum communication.

[0116] Quantum sensing comprises measurements which utilize quantum effects such as entanglement, interference or quantum state squeezing.

[0117] Quantum computing comprises any processing of information based on quantum effects, such as superpositions of physical qubits of the modules 401 and (de-)coherence or entanglement of physical qubits of the modules 401.

[0118] Quantum communication comprises the transmission of classical information or of quantum states between different devices, e.g., between the quantum hardware system 400 and another quantum hardware system based on quantum effects as described above.

[0119] Quantum circuits of the quantum hardware system 400 are designed for carrying out the necessary steps of a given quantum algorithm. Logical quantum circuits can be implemented by physical quantum circuits. Logical quantum circuits comprise a plurality of logical operators, such as gates.

[0120] The information processing system 100 further comprises a device 200 for implementing QEC on the quantum hardware system 400.

[0121] The device 200 for implementing QEC on the quantum hardware system 400 comprises at least one processor 203, and at least one memory 204 (i.e., a tangible computer-readable, or processor-readable storage device) communicatively coupled to the at least one processor 203.

[0122] The processor 203 can be a logic processing unit and can comprise a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller (μC), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a program logic unit (PLU), a network processor (NP) or a combination thereof.

[0123] The memory 204 can comprise at least one of a magnetic hard disk, an optical disc (e.g., compact disc, digital video disc, Blu-ray disc), a solid state disc (SSD), a magneto-optical memory or a hard disc drive (HDD). For example, the memory 204 can comprise a volatile semiconductor or solid state memory, e.g., a random accessmemory (RAM), dynamic RAM (DRAM), RAM (SRAM). The memory 204 can comprise a non-volatile semiconductor or state memory, e.g., a read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), or the like.

[0124] The memory 204 stores processor-executable instructions and / or processor- readable data associated with the operation of the device 200 for implementing QEC on the quantum hardware system 400. The processor-executable instructions and / or processor-readable data can comprise an operating system, peripheral drivers, server instructions, application instructions, calibration instructions, or communication channel instructions.

[0125] The device 200 for implementing QEC on the quantum hardware system 400 further comprises a user interface 205, having at least one of a display, a keyboard, a touch screen, a mouse, buttons, a microphone, loudspeakers and the like. A user may provide or receive information regarding the operation of the information processing system 100 via the user interface 205.

[0126] Although the user interface 205 is illustrated as a component of the device 200 for implementing QEC on the quantum hardware system 400, the user interface 205 can also be an external device of the information processing system 100. For example, the device 200 for implementing QEC on the quantum hardware system 400 can be implemented as a remote server which a user can access via the user interface 205.

[0127] An interface 202 is provided for connecting the processor 203 with the quantum hardware system 400, a cooling device 500 and an actuator device 300. The interface 202 can be any port or link or interface capable of communicating information to another system, e.g., a wired connection or a wireless connection (e.g. wireless LAN, Bluetooth®, ethernet, or the like).

[0128] All of the components of the device 200 for implementing QEC on the quantum hardware system 400 described above can be controlled and / or can communicate over at least one bus 201. The processor 203 may be configured to control the interface 202 and user interface 205 of the device 200 for implementing QEC on the quantum hardware system 400.

[0129] A QEC code is provided to the device 200 for implementing QEC on the quantum hardware system 400. In some embodiments, the QEC code is provided by a user via the user interface 205. In other embodiments, the QEC code is predefined, e.g., stored in the memory 204. The user may in some embodiments select betweena plurality of predefined QEC codes. In cases, the family of classical error- correction codes used to construct the QEC code is predetermined but the member of the family of classical error-correction codes may vary, e.g., depending on the application.

[0130] In addition to the QEC code, a logical quantum circuit for a specific application is provided to the device 200 for implementing QEC on the quantum hardware system 400. In some embodiments, the logical quantum circuit is provided by a user via the user interface 205.

[0131] The logical quantum circuit comprises sequences of operators, such as quantum gates, measurements, and initializations of logical qubits of the logical quantum circuit to predefined values. The quantum gates (or quantum operators) operate on the logical qubits of the logical quantum circuit.

[0132] The QEC code is constructed by a subsystem hypergraph product code construction on a first and a second classical error-correction code. The first and second classical error-correction codes each belong to a family of classical error- correction codes.

[0133] Each classical error-correction code of the family of classical error-correction codes is for encoding logical bits in physical bits. For each code in the family of classical error-correction codes, there is a plurality of physical classical circuits for operating on the physical bits. Each physical classical circuit corresponds to a logical reversible XOR circuit operating on the logical bits. For example, the physical classical circuits may be or comprise permutations of the physical bits.

[0134] In some embodiments, for each code in the family of classical error-correction codes, at least one linear transformation for operating on the logical bits can be expressed as a sum of binary matrices, each binary matrix representing a respective logical reversible XOR circuit in the logical reversible XOR circuits. The linear transformations may comprise all linear transformations for operating on the logical bits. That is, the at least one linear transformation can form the algebra of all binary matrices operating on the logical bits. In other cases, the linear transformations only comprise a subalgebra of the full algebra of all binary matrices operating on the logical bits.

[0135] For the family of classical error-correction codes, the depths indicators of the physical classical circuits are, as a function of a number of the logical bits encoded by the classical error-correction codes, bounded by a first constant. That is, the depthindicators of the physical classical the classical error-correction codes in the family do not scale with the size of For example, the depth indicators of the physical classical circuits are zero. That is, the physical classical circuits may only comprise permutations which are ignored in determining the depth indicator.

[0136] In some embodiments, a number of summands in each respective sum of binary matrices, as a function of a number of the logical bits encoded by the classical error-correction codes, is bounded by a second constant. That is, the number of terms that are summed in the each respective sum of binary matrices for the classical error-correction codes in the family does not scale with the size of the codes.

[0137] A particular example of a family of classical error-correction codes satisfying the above conditions is the family of simplex codes. Classical error-correction codes in the family of simplex codes are specified by a parameter ^^ and is for encoding ^^logical bits in 2^^ − 1 physical bits, wherein the parameter ^^ is an integer. For asimplex code, every invertible linear operator on the ^^ logical bits may beimplemented by a permutation of the ^^ classical bits.

[0138] The first and second classical error-correction codes can belong to two different families of classical error-correction codes or can belong to the same family of classical error-correction codes. In embodiments in which the first and second classical error-correction codes belong to two different families of classical error- correction codes, each of the two families satisfy the above conditions. In an example, the first and second classical error-correction codes are identical.

[0139] The device 200 for implementing QEC on the quantum hardware system 400 implements the logical quantum circuit in a virtual quantum circuit. In particular, the logical qubits of the logical quantum circuit are mapped to physical qubits of the virtual quantum circuit according to the QEC code. The number of physical qubits of the virtual quantum is in general larger than the number of logical qubits of the logical quantum circuit. The physical qubits of the virtual quantum circuit are not yet mapped to hardware physical qubits in the modules 401 of the quantum hardware system 400.

[0140] Implementing the logical quantum circuit in the virtual quantum circuit comprises, in particular, finding physical operator implementations of logical gates of the logical quantum circuit in the virtual quantum circuit. For example, for a QEC code constructed by the subsystem hypergraph product code construction based on two identical classical error-correction codes, a logical Hadamard gate on each logical qubit in the logical quantum circuit (or in a code block) can be mapped to a physicalHadamard gate implemented on each qubit (in the code block) and a permutation of two or more of the logical

[0141] The device 200 for implementing QEC on the quantum hardware system 400 may determine a physical implementation for each logical gate of the logical quantum circuit.

[0142] The memory 204 stores processor-executable instructions. When executed by the processor 203, the instructions cause the processor 203 to implement QEC on the quantum hardware system 400, as explained in the following.

[0143] The logical gates in the logical quantum circuit are substituted with physical gates mapped to by the selected QEC code. Accordingly, a virtual quantum circuit is determined for the logical quantum circuit, based on the QEC code and the determined at least one physical operator implementation.

[0144] The virtual quantum circuit is mapped to a physical quantum circuit. In particular, each physical qubit in the virtual quantum circuit is mapped to a corresponding hardware physical qubit in the modules 401 of the quantum hardware system 400. The mapping may depend on properties of the virtual circuit such as link quality.

[0145] The physical quantum circuit is then executed on the quantum hardware system 400. In this way, the logical quantum circuit is executed on the quantum hardware system, using the QEC code and the at least one determined physical operator implementation.

[0146] The information processing system 100 can control the quantum hardware system 400 to implement a specific quantum algorithm. For example, the algorithm can be obtained from a user, e.g., via the user interface 205 of the device 200 for implementing QEC on the quantum hardware system 400. The processor 203 generates a control signal to control the quantum hardware system 400 to execute the logical quantum circuit.

[0147] The cooling device 500 may maintain the quantum hardware system 400 at a predefined operating temperature of the quantum hardware system 400. The operating temperature may be a cryogenic temperature, e.g., in a range from about 1 mK to 77 K, or more particularly in a range from about 1.5 K to 4 K. In some embodiments, the cooling device 500 may be omitted. The quantum hardware system 400 may, optionally, also be kept at constant air pressure, e.g., a stable vacuum.

[0148] The actuator device 300 can a plurality of actuators. For example, the actuator device 300 can comprise an to apply a time-invariant electric field, a time-varying electric field, or a pulsed electric field to the quantum hardware system 400.

[0149] Figure 2 shows a flow diagram illustrating a method for implementing QEC on a quantum hardware system. The quantum hardware system can in some embodiments be the quantum hardware system 400 described in Figure 1 above. In turn, the quantum hardware system 400 of Figure 1 may be configured to carry out the following method.

[0150] In step S101, a logical quantum circuit is determined. The logical quantum circuit can be predetermined or the logical quantum circuit can be obtained. In some embodiments, a user can submit the logical quantum circuit to a job handler of a Quantum as a Service (QaaS) platform. The logical quantum circuit can be provided in any computer-readable form, e.g., in Open Quantum Assembly Language (OpenQASM), in Q#, in Quantum Intermediate Representation (QIR), or in a graph- based format such as a directed acyclic graph (DAG) with metadata. The metadata can provide a mapping between logical quantum gates of the logical quantum circuit and corresponding nodes in the graph.

[0151] In addition, a QEC code for encoding logical qubits of the logical quantum circuit in physical qubits is determined. A user may submit the QEC code. In some embodiments, the user may select between a plurality of predefined QEC codes.

[0152] The QEC code is constructed using a subsystem hypergraph product code construction on two classical error-correction codes. Each of the two classical error- correction codes belongs to a family of classical error-correction codes. Both classical error-correction codes can belong to different families of classical error-correction codes or to the same family of classical error-correction codes. In particular, they can be identical, i.e., the same member of one family of classical error-correction codes.

[0153] Each classical error-correction code of the family of classical error-correction codes is for encoding logical bits in physical bits.

[0154] The family of classical error-correction codes has certain properties which make implementation of the corresponding QEC code more efficient.

[0155] In particular, each classical error-correction code in the family of classical error-correction codes is associated with a plurality of physical classical circuits foroperating on the physical bits. The classical circuits correspond to respective logical reversible XOR circuits operating on the logical bits. The depth indicators of the physical classical circuits are, as a function of a number of the logical bits encoded by the classical error-correction codes, bounded by a first constant.

[0156] In some embodiments, for each code in the family of classical error-correction codes, at least one linear transformation, that is different to the logical reversible XOR circuits, for operating on at least some of the logical bits can be expressed as a sum of binary matrices, for example of at least two binary matrices. The linear transformations may comprise all linear transformations for operating on the logical bits or only a subset (forming a subalgebra) of all linear transformations operating on the logical bits.

[0157] Each binary matrix represents a respective logical reversible XOR circuit in the logical reversible XOR circuits. The number of summands in each respective sum of binary matrices, as a function of a number of the logical bits encoded by the classical error-correction codes, is bounded by a second constant.

[0158] In the following, the subsystem hypergraph product code construction is described in more detail. The subsystem hypergraph product code construction can be used to generate a quantum low-density parity-check (QLDPC) code. QLDPC codes are a class of QEC codes that are inspired by classical low-density parity- check (LDPC) codes. QLDPC codes are defined by sparse parity-check matrices, meaning that each row and column of the matrix contains only a small number of non- zero entries. This sparsity leads to efficient encoding and decoding algorithms. The parity-check matrix can be represented as a bipartite Tanner graph, where one set of nodes represents qubits and the other set represents parity checks. The edges indicate which qubits participate in each parity check. The QLDPC code can be implemented using the stabilizer formalism.

[0159] According to this specification, the term “parity-check matrix” (denoted by ^^) denotes a matrix used in linear error-correcting codes to verify whether a givencodeword is valid. For a (^^, ^^) linear block code (with ^^ being the length of eachcodeword and ^^ being the number of information bits in each codeword), the paritycheck matrix ^^ is an ^^ × ^^ matrix, where ^^ ≥ ^^ − ^^ and a codeword ^^ is valid, if andonly if ^^ ⋅ ^^^^ = 0 .

[0160] Closely connected to parity-check are generator matrices. Accordingto this specification, the term “generator denotes a matrix ^^ associated with aclassical or quantum code which is used to encode information bits (or logical qubits)into codewords (or physical qubits). For a classical (^^, ^^) linear block code, thegenerator matrix is of dimension ^^ × ^^, where ^^ is the number of information bits, ^^ ≥^^, and ^^ is the length of the codewords. For some information vector ^^, the corresponding codeword ^^ is obtained by the following formula: ^^ = ^^ ⋅ ^^ .

[0161] The sparse nature of QLDPC codes results in lower overhead in terms of the number of physical qubits required for encoding logical qubits, compared to other types of QEC codes. Decoding algorithms for QLDPC codes, such as belief propagation or iterative decoding, are computationally efficient and can be implemented in a scalable manner.

[0162] Subsystem hypergraph product code constructions are described in Li et al., “A Numerical Study of Bravyi-Bacon-Shor and Subsystem Hypergraph Product Codes”, 2020 IEEE International Conference on Quantum Computing and Engineering (QCE), 2020, pp.109-119, which is hereby incorporated by reference in its entirety.

[0163] In the subsystem hypergraph product code construction, the QLDPC code is generated based on two classical simplex codes C1 and C2 with parity-check matrices H1and H2and corresponding generator matrices G1and G2, respectively.

[0164] The subsystem hypergraph product code construction involves gauge operators. The ^^ gauge operators ^^^^and the ^^ gauge operators ^^^^(which correspond to stabilizer generators plus some logical operators) of the subsystem hypergraph product codes are given by: ^^^^ = [^^1 ⊗ ^^] ,^^^^ = [^^ ⊗ ^^2] ,where the symbol “⊗” denotes the Kronecker product. The ^^ gauge operators ^^^^ andthe ^^ gauge operators ^^^^are sufficient to define the code.

[0165] For example, for ^^1 = (1 1 0),for the choice ^^1 = ^^2, and with^^ = (1 0,the ^^ gauge operator ^^^^ and the ^^ ^^^^ are:^^^^ = ^^1 ⊗ ^^ = 0 1 0 0 00 1 0 1 0 0) , .

[0166] So ^^^^ contains the two rows of ^^1 ⊗ ^^.In particular, the firstthird positions whichcorresponds to the Pauli operator ^^1 ⋅ ^^3.

[0167] Then, the ^^ stabilizer generators ^^^^and the ^^ stabilizer generators ^^^^of the subsystem hypergraph product codes are given by: ^^^^ = [^^1 ⊗ ^^2] ,  ^^^^ = [^^1 ⊗ ^^2] .

[0168] In the following, the classical error-correction codes ^^1and ^^2have theparameters (^^1,^^1, ^^1) and (^^2, ^^2,^^2), respectively, where ^^^^ for ^^ = 1,2 denotes thelength of the codewords, which is the number of symbols in each codeword. Further,^^^^ for ^^ = 1, 2 denotes the dimension of the code, representing the number ofinformation symbols (logical bits) in each codeword, or equivalently, the number ofindependent information bits that can be encoded, and ^^^^ for ^^ = 1,2 denotes theminimum Hamming distance between any two distinct codewords, which is the smallest number of symbol changes needed to transform one codeword into another. The parameter ^^^^determines the error-detecting and error-correcting capabilities of the code.

[0169] The resultant QEC code has the following code parameters. The number of physical qubits is given by: ^^ = ^^1 ⋅ ^^2 ,the number of logical qubits is^^ = ^^1 ⋅ ^^2,the number of gauge qubits is given by ^^ = (^^1 − ^^1) ⋅ (^^2 − ^^2),and the quantum minimum distance is given by ^^ = min(^^1,^^2).

[0170] The subsystem code is denoted with the notation ^^[^^,^^,^^,^^] and thestabilizer code is denoted with the notation ^^[[^^, ^^ + ^^, ^^]].

[0171] For example, there is a product code of ^^[9, 4, 1, 2]obtained using a single classical simplex i.e., ^^1 = ^^2, whose parity-checkmatrix is expressed as an element in ^^2^^ for the cyclic group: ^^ = Cyclic(3),with polynomial ℎ(^^) = 1 + ^^ + ^^2.

[0172] The gauge generators ^^^^and ^^^^can be constructed, where in addition so- called overcompletion may be performed, e.g., the rows of the parity-check matrix H1 can be repeated three times. In this case, the gauge generators ^^^^and ^^^^are given by the following matrices: 11 1 0 0 0 0 0 0é1 1 1 0 0 0 0 0 0ù ê1 1 1 0 0 0 0 0ú ê00 0 0 1 1 1 0ú ^^ê0 0= 0 0 0 1ú ^^ê1 1 0 0 0ú , ê0 0 0 1 1 1 0 0 0ú ê0 0 0 0 0 0 1 1 1ú ê0 0 0 0 0 0 1 1 1ú ë0 0 0 0 0 0 1 1 1û1 0 0 1 0 0 1 0 0é0 1 0 0 1 0 0 1 0ù ê0 0 1 0 0 1 0ú ê0 11 0 0 1 0 0ú ^^ =ê1 0 00 1 0ú ^^ê0 1 0 0 1 0ú , ê0 0 1 0 0 1 0 0 1ú ê1 0 0 1 0 0 1 0 0ú ê0 1 0 0 1 0 0 1 0ú ë0 0 1 0 0 1 0 0 1û

[0173] In step S102, physical operator implementations of the logical gates of the logical quantum circuit are determined. The logical gates comprise Clifford gates and non-Clifford gates (such as a T-gate). The physical operator implementation act on physical qubits of a virtual circuit. The physical operator implementations may be retrieved from memory, for example. It can be the case that for at least one of the logical gates in the logical quantum circuit there is no known efficient implementation. In some embodiments, this at least one logical gate can then first be mapped to at least one other logical gate with a known efficient implementation. Examples are given below. The efficient physical implementation of these logical gates is then used to implement the original logical gates.

[0174] In other embodiments, the mapping from logical gates to logical gates with more efficient physical can be skipped. For example, the logical gate is directly mapped to a physical implementation which is based on a logical gate with an efficient implementation, without, however, explicitly constructing the logical gate with the efficient implementation. For example, mappings of all possible logical gates to their physical operator implementations can be stored.

[0175] In step S103, a virtual quantum circuit is provided, which comprises the physical qubits and sequences of operations and measurements, based on the logical quantum circuit and the QEC code. Herein, the operations are based on the physical operator implementations of the logical gates of the logical quantum circuit. That is, step S103 may involve replacing the logical operations in the logical quantum circuit with their respective physical implementations, in the determined QEC code.

[0176] For example, logical quantum state preparations, logical quantum gates, and logical circuit measurements in the logical quantum circuit are replaced by physical quantum state preparations, physical quantum gates, and physical circuit measurements. Moreover, stabilizer measurements are introduced that extract information about the locations of errors without disturbing the protected logical information.

[0177] The virtual circuit can be generated by replacing each logical gate in the logical quantum circuit with its physical operator implementation for the QEC code (e.g. as determined in step S103), and adding one or more stabilizer measurements.

[0178] In step S104, the logical quantum circuit is executed on the quantum hardware system, using the QEC code and the determined physical operator implementations. In order to implement the logical quantum circuit, the corresponding virtual quantum circuit is mapped to the hardware of the quantum hardware system 400. In particular, each physical qubit in the virtual quantum circuit is mapped to a corresponding hardware physical qubit in the quantum hardware system 400.

[0179] The virtual quantum circuit is thereby mapped to a physical quantum circuit executed on the quantum hardware system 400. The mapping may be based on hardware considerations, i.e., based on the characterization of the quantum hardware system 400.

[0180] The quantum hardware system 400 compiles the physical quantum circuit to obtain an executable i.e., converts it into machine code that is readable by acontroller of the quantum hardware The executable is then output to a controller of the quantum hardware system 400 for execution.

[0181] At run-time, the physical quantum circuit is executed by the quantum hardware system 400. Hardware physical qubits are prepared in initial states and physical quantum gates and measurements are performed on the hardware physical qubits to perform computations. For example, the state of the corresponding logical qubits are changed. Further, stabilizer measurements can be carried out to extract information about the locations of errors to use in QEC.

[0182] The information extracted from the hardware physical qubits is referred to as a syndrome. A codeword is any quantum state that is fixed by ideal stabilizer measurements. Any non-destructive stabilizer measurement used to extract a syndrome therefore does not disturb a codeword, and hence the set of all codewords constitute a subspace in which one can reliably store quantum information protected from error.

[0183] A decoder can process the measured syndromes to identify errors that occurred. Based on the syndrome, the error can be detected and it can be determined which qubit or qubits are affected by the error. Recovery operations can be determined.

[0184] The recovery operations can be carried out, e.g., by implementing additional physical gates to correct the error.

[0185] In some embodiments, step S104 may be omitted. The method may, for example, end after step S103 has been performed. In some embodiments, the virtual quantum circuit provided in S103 may be used to estimate a quantity of resources required to execute the logical quantum circuit using the QEC code on the quantum hardware system. The resources may be resources of the quantum hardware system. The resources may include, for example, one or more of: time, physical qubits, physical gates, a particular type of physical gate, a particular type of quantum state etc. Time may be expressed in, for example, seconds, clock cycles, and / or a circuit depth. The quantity of a particular type of quantum state may be, for example, a quantity of entangled states, a quantity of magic states (e.g. T states) etc. An estimated quantity may be expressed as a rate e.g. the quantity of the particular type of quantum state per unit of time.

[0186] In some embodiments, estimating the quantity of resources may involve estimating the quantity of resources based on a property of the quantum hardwaresystem (e.g. quantum hardware system . For example, the estimate may depend on one or more of: a quantity of physical of the particular quantum hardware system, a physical gate fidelity for the particular quantum hardware system, a physical gate duration for the particular quantum hardware system, a connectivity of the particular quantum hardware system etc.

[0187] Such resource estimations may advantageously be used for designing (e.g. adjusting a design of) a quantum hardware system. For example, estimating that a quantity of time required to execute the logical quantum circuit using the QEC on a particular quantum hardware system that is longer than the expected uptime of particular quantum hardware system may indicate that the clock cycle time of the particular quantum hardware system is too long, necessitating redesign. As another example, a quantity of physical qubits allocated to generating entanglement in the particular quantum hardware may be adjusted in response to estimating that the entanglement rate required to execute a logical quantum circuit on a particular quantum hardware system exceeds the achievable entanglement rate of the particular quantum hardware system.

[0188] As explained, the logical quantum circuit is mapped to a virtual quantum circuit. Each quantum logical operator in the logical quantum circuit can be replaced by a physical operator implementation.

[0189] At least some quantum logical operators in the logical quantum circuit can be replaced by a physical operator implementation for implementing at least one logical CNOT circuit. Herein, the at least one logical CNOT circuits are implemented such that the control qubits are located in a first code block of physical qubits, and the target qubits are located in a second code block of physical qubits. These logical CNOT circuits can be called logical “B-circuits”. According to this specification, the term logical “B-circuit” denotes therefore a CNOT circuit such that the control qubits are located in a first code block of physical qubits, and the target qubits are located in a second code block of physical qubits.

[0190] That is, according to the present disclosure, particular logical B-circuits, and particular combinations of logical B-circuits, can be used to implement some logical operators in the subsystem hypergraph product codes described herein. This is advantageous because the logical B-circuits may be implemented by physical B- circuits. Physical B-circuits do not propagate errors within a code block, preserving the distance of the subsystem hypergraph product code. In addition, although thephysical B-circuits involve implementing gates between code blocks, they involve a reduced number of entangling gates between code blocks whilst still implementing the desired logical operation. This means that the physical B-circuits reduce the propagation of errors from one code block to another. Since the subsystem hypergraph product codes described herein have physical operator implementations that do not propagate errors within a code block and reduce error propagation between code blocks, encoding logical quantum circuits encoded with these subsystem hypergraph product codes can reduce propagation of errors in the circuit during circuit execution. This can be used to enable more reliable quantum computation.

[0191] The term “CNOT gate” denotes a gate that acts on two qubits, namely a control qubit and a target qubit. The CNOT gate inverts the state of (i.e. performs the NOT operation on) the target qubit when the control qubit is in the |1^ state and leaves the target qubit unchanged when the control qubit is in the |0^ state. A physical CNOT gate operates on physical qubits. A logical CNOT gate operates on logical qubits.

[0192] To illustrate how logical operators in the subsystem hypergraph product code codes described herein may be implemented using logical B-circuits (and thus physical B-circuits), further details are provided. For ease, this is described with respect to embodiments in which it is possible to express all linear transformations for operating on all logical bits in the classical error correction codes used to construct the subsystem hypergraph product code as respective sums of binary matrices, in which each binary matrix represents a logical reversible XOR circuit. Each logical reversible XOR circuit corresponds to a physical classical circuit for operating on physical bits, and the number of summands in each respective sum of binary matrices is bounded by a second constant. In other embodiments, it may only be possible to express some (e.g. at least one) linear transformations for operating on (some or all of) the logical bits as respective sums of the binary matrices. In such embodiments, only some implementations of logical CNOT circuits may be available for the QEC code.

[0193] In addition, in some embodiments it may only be possible to express the linear transformations for operating on a subset of the logical bits in the classical error correction codes as respective sums of the binary matrices. As a result, in someembodiments, the mappings described may only be valid for a subset of the logical qubits.

[0194] The two classical error-correction codes used to construct the subsystemhypergraph product code as described herein have parameters (^^1, ^^1, ^^1) and(^^2, ^^2, ^^2), respectively, where ^^^^ is the number of physical bits, ^^^^ is the number oflogical bits, and ^^^^is the minimum distance. As mentioned above, in some embodiments it is possible to express all linear transformations for operating on logical bits in the classical error correction codes as respective sums of binary matrices. That is, for each of the two classical error-correction codes, the full algebraof linear transformations on ^^^^ logical qubits may be generated by sums of ^^^^ × ^^^^binary matrices. The size of these sums for a code in a classical code family is bounded by a constant ^^^^, i.e., the required number of summands to construct a given linear transformation is at most ^^1in the first classical error correction code and at most ^^2in the second error correction code. In addition, the depth indicators of the physical classical circuits that implement the reversible logical XOR circuits for a code in the classical code family are, as a function of a number of the logical bits encoded by the classical code, bounded by a first constant ^^^^.

[0195] For the corresponding subsystem hypergraph product code, any element ofthe full algebra may be generated by a sum of ^^ × ^^ binary matrices, for:^^ = ^^1 ⋅ ^^2 ,in which the number of summands is no larger than: (2 ⋅ (^^1 + ^^2) + 1) ⋅ ^^1^^2 ⋅ ^^^^^^(^^21, ^^22) ≤ (2 ⋅ (^^1 + ^^2) + 1) ⋅ ^^1 ⋅ ^^2 ⋅ ^^ .1) ⋅ ^^ ⋅ ^^2 scales as ^^(1), and the expression (2 ⋅ (^^1 + ^^2) +^^1 ⋅ ^^2 ⋅ ^^as ^^(^^).

[0197] In other words, the number of summands to express a given element of the fullalgebra in terms of ^^ × ^^ binary matrices scales as no worse than ^^(^^), i.e. in theworst case, scales linearly with the number of logical qubits, ^^. This means that it is possible to implement any logical CNOT circuit (i.e., any logical CNOT on any logical qubit) in the subsystem hypergraph product code described herein using a respective combination of one or more physical B-circuits that implement logical B-circuits, in which the number of physical B-circuits scales no worse than linearly with the number of logical qubits of the code. This, in turn, means that the depths of the physical operator implementations for logical CNOT circuits within a block in the subsystemhypergraph product code described no worse than linearly with the number of logical qubits. For logical CNOT between code blocks, the depths of the physical operator implementations in the subsystem hypergraph product code described herein scale no worse than linearly with the number of logical qubits and with the square of the number of code blocks. As a result, the subsystem hypergraph product code described herein may be used to efficiently implement a logical CNOT circuit. In addition, this code also has efficient implementations of other logical operators, which is described in more detail below.

[0198] A Clifford circuit is a circuit which can be expressed in terms of any generating set for the Clifford group. An arbitrary Clifford circuit has a physical implementation involving a combination of a diagonal circuit, a CNOT circuit, a Hadamard transformed diagonal circuit, and an arbitrary Hadamard transformation.

[0199] Clifford gates and a non-Clifford gate (e.g., a T gate) form a universal gate set. Implementations of non-Clifford gates are known (e.g., by magic state distillation and state injection). Therefore, by having a physical implementation for any arbitrary Clifford circuit, some of the subsystem hypergraph product codes described herein allow efficient logical operator implementations for a universal gate set.

[0200] In the following, specific physical implementations of logical quantum gates are explained. Many of the implementations are based on the above described B-circuits.

[0201] In the subsystem hypergraph product code where the first and second classical error-correction codes are identical, a logical Hadamard gate on each logical qubit in the logical quantum circuit can be mapped to a physical Hadamard gate implemented on each physical qubit and a permutation of two or more of the logical qubits. The permutation may involve applying a SWAP gate. For example, the permutation can be implemented by applying pulses to physical qubits to implement a SWAP gate. Alternatively, the permutation may involve applying a logical CNOT circuit. The permutation may, alternatively, be implemented in software, e.g., by keeping track of the physical qubits and by relabeling the physical qubits (i.e., ordering indices associated with the physical qubits) in software.

[0202] This gate implementation is advantageous because it is automatically fault- tolerant. If an error occurs on one physical qubit, implementing the gate will not propagate the error to a different physical qubit because implementing the gate does not involve any inter-qubit interactions.

[0203] In the subsystem hypergraph code described herein, an in-block CNOT logical operator can be acting on logical qubits. The in-block CNOT logical operator is a CNOT logical operator within a first code block, and there is a second code block which is an auxiliary code block.

[0204] Figures 3 to 5 show quantum circuits for explaining an implementation of an in- block CNOT logical operator.

[0205] In Figure 3, a first quantum state in a first code block is initially an arbitrary k- logical qubit state |^^^, encoded in ^^-physical qubits, and a second quantum state in a second code block is initially an auxiliary all zero logical state |0^.

[0206] Herein, an auxiliary state (or system) is used to assist in a quantum algorithm, e.g., by providing extra work space.

[0207] A logical CNOT circuit acts on the first and second quantum states. Although only a single CNOT gate is illustrated in Figure 3, it represents a CNOT circuit that comprises one or more CNOT gates. The logical CNOT circuit is a B-circuit because the control qubits (the qubits of the first quantum state |^^^) are located in the first code block and the target qubits (the second quantum state |0^) are located in the second code block.

[0208] An ^^-measurement is performed on the first quantum state and a ^^^^-operation (a Pauli correction) is performed on the second quantum state, where ^^ in ^^^^denotes the result of the measurement. The quantum circuit implements a SWAP operation, where the first quantum state|^^^from the first code block is in the end located in the second code block.

[0209] In Figure 4, a logical in-block CNOT circuit ^^ is applied at the end on the second quantum state to obtain the state ^^|^^^.

[0210] In Figure 5, a specific implementation of the logical in-block CNOT circuit ^^ is shown. A first quantum state in a first code block is initially an arbitrary ^^-logical qubit state |^^^ and a second quantum state in a second code block (an auxiliary code block) is initially an auxiliary all zero state |0^. A logical B-circuit implementation of the CNOT circuit ^^ is applied, an ^^-measurement is performed on the first quantum state and a ^^^^^^^^−1-operation is performed on the second quantum state to obtain the state ^^|^^^.

[0211] The physical implementation comprises therefore a (destructive) measurement on the first code block, a correction based on a value of the measurement (a Paulicorrection), and a physical circuit that a logical CNOT circuit which is a logical B-circuit. The logical B-circuit may implemented using one or more physical B-circuits. As such, a logical in-block CNOT circuit may be implemented on the logical state |^^^ by implementing one or more physical B-circuits that implement a logical B- circuit, implementing a measurement on the first code block and a correction based on a value of the measurement.

[0212] Figures 6 to 8 show quantum circuits for explaining another implementation of an in-block CNOT logical operator.

[0213] In Figure 6, a first quantum state in a first code block is initially an ^^-logical qubit state |^^^ encoded in ^^-physical qubits, and a second quantum state in a second code block is initially an auxiliary all plus logical state |+^. A logical CNOT circuit (implemented as a B-circuit) acts on the first and second quantum states. A ^^- measurement is performed on the first quantum state and an ^^^^-operation (a Pauli correction) is performed on the second quantum state, where ^^ in ^^^^denotes the result of the measurement. The quantum circuit implements a SWAP operation, where the first quantum state |^^^ from the first code block is in the end located in the second code block.

[0214] In Figure 7, a logical in-block CNOT circuit ^^ is applied at the end on the second quantum state to obtain the state ^^|^^^.

[0215] In Figure 8, a specific implementation of the logical in-block CNOT circuit ^^ is shown. A first quantum state in a first code block is initially an arbitrary ^^-logical qubit state|^^^and a second quantum state in a second code block is initially an auxiliary all plus logical state|+^. A logical B-circuit implementation of the CNOT circuit ^^−1is applied, a ^^-measurement is performed on the first quantum state and a ^^^^^^^^−1- operation is performed on the second quantum state to obtain the state ^^|^^^.

[0216] The physical implementation of the logical CNOT circuit ^^ comprises thereforea (destructive) measurement on the first code block, a correction based on a value of the measurement (a Pauli correction, indicated by the ^^^^^^^^−1-operation), and a logical CNOT circuit which is a logical B-circuit. The logical B-circuit may be implemented using one or more physical B-circuits.

[0217] Figures 5 and 8 thus show two different ways of implementing a logical CNOT^^ in the subsystem hypergraph product code described herein. In bothimplementations, the physical operator implementation involves an auxiliary code block initially in an all zero or an all positive logical state, one or more physical B-circuits that implement a logical B-circuit the first code block and an auxiliary code block, a measurement on the first block and a correction based on a value of the measurement. In both examples, the implementation results in the logical CNOT circuit being implemented on the auxiliary code block. To implement the logical CNOT circuit on the first code block, a permutation of one or more logical qubits may be performed to swap the state ^^|^^^ to the first code block. The permutation may be implemented by applying, for example, a physical SWAP gate, a permutation in software or one or more logical B-circuits etc.

[0218] Figures 9 to 11 show quantum circuits for explaining another implementation of an in-block CNOT logical operator.

[0219] In Figure 9, a first quantum state in a first code block is initially an arbitrary ^^- logical qubit state|^^^and a second quantum state in a second code block is initially an auxiliary all zero logical state|0^. A logical CNOT circuit (implemented as a logical B-circuit) acts on the first and second quantum states. Another logical CNOT circuit gate (implemented as a logical B-circuit) acts on the first and second quantum states, with control qubits and target qubits inverted. The quantum circuit implements a SWAP operation, where the first quantum state|^^^from the first code block is in the end located in the second code block.

[0220] In Figure 10, an in-block logical CNOT circuit ^^ is applied at the end on the second quantum state to obtain the state ^^|^^^.

[0221] In Figure 11, a specific implementation of an in-block logical CNOT circuit ^^ is shown. A first quantum state in a first code block is initially an arbitrary ^^-logical qubit state |^^^ and a second quantum state in a second code block is initially an auxiliary all zero logical state |0^. A logical B-circuit implementation of the logical CNOT circuit ^^ is applied and another logical B-circuit implementation of the logical CNOT circuit ^^−1is applied, with control qubits and target qubits inverted. In the end, the second quantum state in the second code block is in the state ^^|^^^.

[0222] The in-block logical CNOT circuit ^^ may thus be implemented by two logical CNOT circuits which are logical B-circuits acting between the two code blocks. Each of the logical B-circuits may be implemented by one or more physical B-circuits.

[0223] Figures 12 to 14 show quantum circuits for explaining another implementation of a logical in-block CNOT logical operator.

[0224] In Figure 12, a first quantum state in a first code block is initially an arbitrary ^^- logical qubit state |^^^ and a second quantum state in a second code block is initiallyan auxiliary all plus logical state|+^. A CNOT circuit (implemented as a B- circuit) acts on the first and second quantum states. Another logical CNOT circuit (implemented as a B-circuit) acts on the first and second quantum states, with control qubits and target qubits inverted. The quantum circuit implements a SWAP operation, where the first quantum state|^^^from the first code block is in the end located in the second code block.

[0225] In Figure 13, a logical in-block CNOT circuit ^^ is applied at the end on the second quantum state to obtain the state ^^|^^^.

[0226] In Figure 14, a specific implementation of a logical in-block CNOT circuit ^^ is shown. A first quantum state in a first code block is initially an arbitrary ^^-logical qubit state |^^^ and a second quantum state in a second code block is initially an auxiliary all plus logical state |+^. A logical B-circuit implementation of the logical CNOT circuit ^^−1is applied and another logical B-circuit implementation of the logical CNOT circuit ^^ is applied, with control qubits and target qubits inverted. In the end, the second quantum state in the second code block is in the state ^^|^^^.

[0227] The physical implementation comprises therefore two logical CNOT circuits which are logical B-circuits acting between the two code blocks. Each of the logical B- circuits may be implemented by one or more physical B-circuits.

[0228] Figures 11 and 14 thus show two different ways of implementing a logicalCNOT ^^ in the subsystem hypergraph product code described herein. In bothimplementations, the physical operator implementation involves an auxiliary code block initially in an all zero or an all positive logical state and two logical B-circuits between the first code block and the auxiliary code block. The logical B-circuits may be implemented by performing one or more physical B-circuits between the code blocks. In both examples, the implementation results in the logical CNOT circuit being implemented on the auxiliary code block. To implement the logical CNOT circuit on the first code block, a permutation of one or more logical qubits may be performed to swap the state ^^|^^^ to the first code block. The permutation may be implemented by applying, for example, a physical SWAP gate, a permutation in software or one or more logical B-circuits etc.

[0229] The implementations of Figures 11 and 14 have the advantage of being non- destructive because no measurement is involved.

[0230] In the subsystem hypergraph product code described herein, a two-blockCNOT logical operator can be implemented, acting on logical qubits. A two-blockCNOT logical circuit comprises any logical circuit of CNOT circuits involving two code blocks. Any logical two-block CNOT logical operator can be implemented using up to two arbitrary logical B-circuits and two parallelizable in-block logical CNOT circuits (e.g., constructed as explained above), with a permutation. The permutation can be performed classically. As mentioned above, the logical B-circuits may be implemented using physical B-circuits.

[0231] In the subsystem hypergraph product code described herein, a logical diagonal Clifford operator can be implemented. The logical diagonal Clifford operator may be an in-block logical diagonal Clifford operator. That is, the logical diagonal Clifford operator may be within a first code block and a second code block may comprise an auxiliary code block.

[0232] A logical diagonal Clifford operator is a Clifford operator ^^ which, modulo Pauli operators, can be expressed as ^^ = ( ^^ ^^0 ^^),where I is the identity matrix and ^^ ∈ ^^^^(2) is a symmetric matrix with diagonal andoff-diagonal entries. The matrix ^^ determines the S and CZ gates comprising the logical diagonal Clifford operator. A diagonal physical quantum circuit can implement the diagonal Clifford operator. Every Clifford operator can be implemented using physical quantum circuits which implement diagonal Clifford operators, transversal Hadamard gates and CNOT circuits.

[0233] In the subsystem hypergraph product code described herein, an in-block logical diagonal Clifford circuit can be implemented. According to this specification, an “in-block logical diagonal circuit” denotes a diagonal Clifford circuit applied within one code block. Every diagonal circuit ^^ decomposes as: ^^ = ( ^^ ^^ ^^ 0^^−10 ^^) = (^^ ^^ ^^ ^^^^−^^) (^^) (^^^^) (^^), with matricesthird matrices in the last expression correspond to logical CNOT operators, and the second and fourth correspond to S gates. This decomposition can be used to implement injection- based logical evolution.

[0234] According to this specification, an “S gate” (also known as phase gate)denotes a gate which maps the logical qubit basis states |0^, |1^ as follows:|0^ → |0^ ,|1^ → ^^|1^ .

[0235] In the subsystem hypergraph code described herein, an in-block logical diagonal Clifford operator can in some embodiments be implemented by a sequence of depth ^^(1) physical diagonal circuits. The logical diagonal circuits that can be implemented using one or more of these physical diagonal quantum circuits depends on the QEC code. For example, the quantum code constructed using a subsystem hypergraph product of two identical copies of the [3,2,2] classical simplex code has 9 physical qubits, 4 logical qubits, and the logical diagonal Clifford operator ^^1 ⋅ ^^3 ⋅ ^^4 ⋅ ^^^^{1,3} ⋅ ^^^^{2,3} ⋅ ^^^^{3,4}is implemented by the depth 1 physical diagonal circuit ^^1 ⋅ ^^6 ⋅ ^^8 ⋅ ^^^^{2,7} ⋅ ^^^^{3,4} ⋅ ^^^^{5,9} .

[0236] Figures 15 and 16 show quantum circuits for explaining another implementation of an in-block logical diagonal Clifford operator.

[0237] In Figure 15, a first quantum state in a first code block is initially an arbitrary ^^- logical qubit state|^^^and a second quantum state in a second code block is initially an auxiliary logical state ^^|+^, where ^^ denotes an S gate and |+^ is an all positive logical state. The ^^|+^state is the result of applying an S gate to the all plus codeword. This is also known as a magic state for injecting the S gate. A logical CNOT gate (implemented as a B-circuit) is applied, a ^^-measurement is performed on the second quantum state and a ^^^^-operation is performed on the second quantum state to obtain the state ^^|^^^.

[0238] In Figure 16, a first quantum state in a first code block is initially an arbitrary ^^- logical qubit state |^^^ and a second quantum state in a second code block is initially an auxiliary logical state ^^|+^, where ^^ denotes an S gate and |+^ is an all positive logical state. A logical B-circuit implementation of the CNOT circuit ^^−1is applied, a ^^-measurement is performed on the second quantum state and a ^^^^^^^^−1-operation is performed on the second quantum state to obtain the state ^^^^^^−1|^^^.

[0239] An in-block diagonal logical diagonal Clifford operator can be implemented in the subsystem hypergraph product code described herein by up to two logical CNOT circuits and up to two logical S circuits. Each of the logical CNOT circuits may be implemented using one or more B-circuits as described above. Based on the circuits in Figures 15 and 16, each of the logical S circuits may be implemented by a round of conjugated direct injection of an ^^|+^state, each comprising a measurement, acorrection based on a value of the (a Pauli correction), and one B- circuit.

[0240] Since Figures 15 and 16 respectively show the implementation of a logical ^^ operator and a logical ^^^^^^−1operator on the logical state |^^^, and these operators are also diagonal Clifford operators, Figures 15 and 16 also illustrate implementations of in-block logical diagonal Clifford operators.

[0241] Figures 17 and 18 show quantum circuits for explaining another implementation of an in-block logical diagonal Clifford operator.

[0242] In Figure 17, a first quantum state in a first code block is initially an arbitrary ^^- logical qubit state|^^^and a second quantum state in a second code block is initially an auxiliary logical qubit state ^^|+^, where ^^ denotes an S gate and |+^ is an all positive logical state. A logical CNOT gate (implemented as a logical B-circuit) is applied and a logical controlled Z (CZ) circuit is applied to obtain the state ^^|^^^ in the first code block and ^^|+^ in the second code block.

[0243] In Figure 18, a first quantum state in a first code block is initially an arbitrary ^^- logical qubit state |^^^ and a second quantum state in a second code block is initially an auxiliary logical state ^^|+^, where ^^ denotes an S gate and |+^ is an all positive logical state. A B-circuit implementation of the CNOT circuit ^^−1is applied, and a CZ circuit ^^^^^^−1is applied (with control and target inverted) to obtain the state ^^^^^^−1|^^^ in the first code block and ^^|+^ in the second code block.

[0244] Based on the circuit in Figure 18, a logical S circuit may be implemented by around of conjugated catalytic injection of an ^^|+^ state, which uses one block logicalCNOT circuit and one Hadamard conjugated block logical CNOT circuit (the CZ circuit), but does not require consuming the ^^|+^state. Herein, “catalytic” means that no measurement is involved, i.e., the ^^|+^state remains intact.

[0245] In the subsystem hypergraph product code described herein, two-block diagonal circuits can be implemented. A logical diagonal Clifford operator between the first code block and the second code block can be implemented, which comprises implementing a logical Hadamard transformation of at least one logical CNOT circuit (of a logical B-circuit), a physical diagonal circuit within the first code block and a physical diagonal circuit within the second code block.

[0246] In the subsystem hypergraph product code described herein, arbitrary Hadamard gates can be implemented.

[0247] Figures 19 and 20 show quantum for explaining an implementation of arbitrary Hadamard gates.

[0248] In Figure 19, a quantum state is initially an arbitrary ^^-logical qubit state |^^^. A sequence of three logical ^^^^gates is applied, where ^^^^is a S gate acting on a specific qubit ^^ of the ^^ qubits. Between two logical ^^^^operations, a logical all qubit Hadamard gate H is applied, i.e., the logical ^^^^gates are interleaved by two rounds of logical Hadamard gates H. The logical all qubit Hadamard and the logical S gate may be implemented using the respective physical operator implementations described above. The result of the quantum circuit is the state ^^^^|^^^.

[0249] In Figure 20, a quantum state is initially an ^^-logical qubit state |^^^. Asequence of three logical ^^^^^^^^gates is applied, is a controlled Z (CZ) gate acting on the specific logical qubits ^^ and ^^ of the ^^ logical qubits. Between two operations, a logical all qubit Hadamard gate H is applied, i.e., the logical ^^^^^^^^gates are interleaved by two rounds of logical all qubit Hadamard gates ^^. The result of the quantum circuit is the state SWAPij^^^^^^^^|^^^, where SWAPijdenotes the SWAP gate acting on the specific qubits ^^ and ^^ ^^ qubits. The logical all qubit Hadamardmay be implemented using the physical operator implementation described above. The logical ^^^^^^^^gate may be implemented as an in-block logical diagonal Clifford operator, described above.

[0250] In general, any Hadamard gate ^^^^acting on a particular logical qubit can be implemented using a sequence of all-qubit Hadamard gates and diagonal circuits. The particular sequence depends on the targeted qubit or qubits.

[0251] Figure 21 shows a flow diagram of a method for implementing QEC on a quantum hardware system.

[0252] In step S201, a logical quantum circuit is determined. The logical quantum circuit can be predetermined or can be retrieved from a user or a remote device, e.g., a remote server.

[0253] Further, a QEC code is determined for encoding logical qubits of the logical quantum circuit in physical qubits. Herein, determining the QEC code can comprise receiving the QEC code or constructing the QEC code.

[0254] The QEC code is constructed using a subsystem hypergraph product code construction on a first classical simplex code and a second classical simplex code. The first classical simplex code can be identical to the second classical simplex code.It is also possible to select different the first classical simplex code differs from the second classical simplex code.

[0255] In step S202, the logical quantum circuit is executed on the quantum hardware system, using the QEC code.

[0256] In the following, simplex codes are described in more detail. Simplex codes are classical codes with a large automorphism group. Simplex codes are the dual of Hamming codes. Their code parameters saturate the Hamming bound. An individual simplex code can be identified by specifying a single parameter, namely the order, ^^, of the simplex code, where ^^ is a positive integer greater than or equal to 2. The length of each codeword (i.e., the number of physical bits) is given by: ^^ = 2^^ − 1.

[0257] The size ^^ grows exponentially in size as a function of the order ^^ of the simplex code. The order ^^ of the simplex code is a parameter which is associated with the number of physical bits of the simplex codes.

[0258] The length of each information word (i.e., the number of logical bits) to be encoded is: ^^ = ^^,and the minimum distance of the code is given by: ^^ = 2^^−1.

[0259] Simplex codes can be written as: ^^(^^, ^^, ^^) = ^^(2^^ − 1, ^^, 2^^−1).

[0260] Simplex codes are cyclic codes. According to this specification, the term “cyclic code” denotes a type of linear error-correcting code in which, if a codeword is cyclically shifted (i.e., its logical bits are rotated), the result is still a codeword.Formally, if ^^ = (^^0, ^^1, ... , ^^^^−1) is a codeword in an n-length cyclic code, then(^^^^−1, ^^0, ^^1, ... , ^^^^−2) must also be a codeword in the same code. Cyclic codes areparticularly useful because they can be efficiently implemented and decoded.

[0261] The parity-check matrix and the generator matrix of simplex codes can be described by a polynomial or an element of the group algebra ^^2^^ for the cyclic groupG of order 2^^ − 1. The parity-check matrix of the simplex codes is the binary lift fromits group algebra polynomial.

[0262] For example, a simplex code with order ^^ = 3 can be expressed as anelement in ^^2^^ for the cyclic group ^^ = Cyclic(7), with the polynomial:ℎ(^^) = 1 + ^^ + ^^3.

[0263] In fact, this polynomial is not unique.

[0264] In a particular example, the order simplex code can be given by ^^ = 3,which implies that the number of physical bits is equal to ^^ = 7, the number of logicalbits is equal to ^^ = 3 and the distance of the code is given by ^^ = 4, i.e., the simplexcode can be denoted as ^^(7, 3, 4).

[0265] This simplex code has an automorphism group of order 168, and is isomorphicto GL3(2), the group of 3 × 3 invertible matrices over the field of size 2 (i.e., binarymatrices). The parity-check matrix for this code that corresponds to the choice of ℎ(^^) above is given by: 11 0 1 0 0 0é0 1 1 0 1 0 0ù 0ú 1ú ú . 0ú 1ú 1û

[0266] The generator0^^ = [ 0 1 1 1 0 1 0] 00 1 1 1 0 1

[0267] The parity-check matrix and the generator matrix for the simplex code^^(7, 3, 4) are not unique.

[0268] Every codeword of the ^^(7, 3, 4) simplex code can be described by a sum ofbasis codewords ^^1, ^^2, ^^3 which can be defined as follows:^^1^^1 0 1 1 1 0 0, where T denotes

[0269] Now, for example, the code vector ^^ = (1 0 0 0 1 0 1)^^can be expressed as: ^^ = 1 ⋅ ^^1 + 0 ⋅ ^^2 + 1 ⋅ ^^3 ,

[0270] In general, a code3 ^^ = ∑^^^^ ⋅ ^^^^, ^^=1 where ^^^^denote the logical bit values. For the specific code vector above, the logicalbit values are given by (^^1, ^^2, ^^3) = (1, 0, 1).

[0271] Figure 22 shows the action of a linear transformation, namely the permutation ^^ operating on the seven physical bits ^^1 to ^^7. Figure 22 therefore shows a physical classical circuit. The permutation ^^ permutes bits ^^2 and ^^4 and ^^5and ^^6. The total action of the permutation ^^ on the physical bits ^^1 to ^^7 is given by:^^1 ↦ ^^1^^2 ↦ ^^4^^3 ↦ ^^3^^4 ↦ ^^2^^5 ↦ ^^6^^6 ↦ ^^5^^7 ↦ ^^7

[0272] The action of the linear transformation ^^ on the basis codewords ^^1,^^2,^^3is as follows: ^^ ^^1 = ^^ 1 0 1 1 1 0 0) ^^) = (1 1 1 0 0 1 0)^() (( ^ = ^^2 .^^ ^^ ^^ ..^^ = ( 1 1 0) , 00 1which represents a logical reversible XOR circuit.

[0274] Figure 23 illustrates the action on the three logical bits ^^1 to ^^3, corresponding to the permutation ^^ defined above. Figure 23 therefore shows a logical classical circuit. The matrix corresponds to a logical reversible XOR gate which is the classical analogue of a CNOT gate. The graphical notation for the CNOT gate has been used.

[0275] In general, each linear transformation maps basis codewords to other codewords, which can be expressed as a linear combination of basis codewords. By linearity, the linear transformation preserves the full code space and therefore induces a logical operator. The logical operator is determined by its action on the basis codewords.

[0276] For all logical XOR circuits corresponding to any choice of invertible matrix ^^ in the general linear group ^^ ∈ ^^^^3(2) ,there is a corresponding physical ^^^^ of depth ^^ = 0, up topermutation.

[0277] According to this specification, the termlinear group”, ^^^^^^(2), ofdegree ^^ for the field with two elements denotes the set of ^^ × ^^ invertible matriceswith binary entries. The “algebra of all linear transformations”, ^^^^(2), of degree ^^ forthe field with two elements denotes the set of all ^^ × ^^ matrices with binary entries. Inparticular, ^^^^(2), contains all non-invertible matrices.

[0278] The depth indicators ^^ of the physical classical circuits associated with a logical reversible XOR circuit does not depend on the parameter ^^ of the simplex codes.

[0279] In particular, the depth indicators (i.e., ^^ = 0) of the physical classical circuitsare, as a function of a number of the logical bits encoded by the classical error- correction codes (i.e., simplex codes), bounded by a first constant (e.g., 1). In otherwords, the depth indicator ^^ of the classical circuit associated with each logicalreversible XOR circuit does not scale with the parameter ^^.

[0280] The invertible matrices ^^ corresponding to the logical reversible XOR circuits are generators which generate all classical logical operators (linear transformations) operating on the logical bits. That is, each arbitrary (not necessarily invertible) matrix in ^^^^3(2)can be written as the sum of at most two invertible binary matrices. The number of summands in the sum of invertible binary matrices is therefore constant and does not depend on the parameter ^^ of the simplex codes. In particular, the number of summands (i.e., 2) in each respective sum of binary matrices, as a function of a number of the logical bits encoded by the classical error-correction codes, is bounded by a second constant (e.g., 2).

[0281] For the classical simplex codes, the obtained linear transformations form thealgebra of all binary matrices operating on the logical bits ^^^^(2), i.e., all ^^ × ^^ binarymatrices, where ^^ is the number of logical bits. For other families of classical error- correction codes it can occur that the obtained linear transformations form only a subalgebra of the algebra of all binary matrices in ^^^^(2), operating on the logical bits.For example, for ^^ = 3, it may happen that only binary matrices in ^^3(2) of the form^^ ^^ 0^^ ^^,are generated, for arbitrary binary values ^^, ^^,^^. These matrices form a ^^2(2)subalgebra of ^^′3(2), i.e. ^^× ^^′ binary with ^^′ = 2.

[0282] In summary, the invention provides methods, devices, and systems for implementing QEC on a quantum hardware system in an efficient manner. Physical classical circuits correspond to logical reversible XOR circuits. Further, the depth indicators of the physical classical circuits are bounded by a constant. That is, the depth indicator does not grow with the number of logical bits. These properties guarantee that corresponding QEC codes can be implemented in an efficient way.

[0283] The devices, apparatuses and systems described in the present disclosure may comprise electronic components and circuits known to those skilled in the art. Therefore, details of the circuitry and its components have not be explained in any greater extent than that considered necessary for the understanding and appreciation of the underlying concepts of the present disclosure.

[0284] Where reference is made to a component, such as a device, component, software module or the like, the reference to that component is intended to include as equivalents any component being functionally equivalent, i.e., performing the same function, even though the component is not necessarily structurally equivalent to the component that performs in the exemplary embodiments.

[0285] In the above description, embodiments have been described with reference to specific details, e.g., parts of a method, components, materials, and the like. A person skilled in the art will understand that embodiments may be implemented without one or more of these specific details.

[0286] All of the US patents, US patent application publications, US patent applications, foreign patents, foreign patent applications, and non-patent publications referred to in this specification, or referred to on any application data sheet, are incorporated by reference in their entireties for all purposes herein.

[0287] A person skilled in the art may understand that certain method steps may be described or depicted in a particular order of occurrence while such specificity with respect to sequence is not actually required.

[0288] Phrases like “an embodiment” and “another embodiment” are used in the sense that particular features described in connection with the embodiment are included in at least one embodiment. Those phrases do not necessarily all refer to the same embodiment. Terms such as "first", "second", “third”, and so on, are used todistinguish between the elements by these terms. These terms do not necessarily imply any temporal or other of such elements.

[0289] As used herein, the singular forms "a," "one," and "the " are also intended to encompass the plural forms unless the context indicates otherwise. In addition, it is understood that the expressions "includes" and / or "including" when used in this specification relates to the presence of features, numbers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more features, numbers, steps, operations, elements and / or combinations thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.

[0290] Terms such as “horizontal”, “vertical”, “upper”, “lower”, “above”, “below”, “forward” and “backward” refer to particular orientations of components and / or events in time and / or space. The skilled person understands that may therefore depend on the specific orientation and may change if the components and / or events are oriented differently.

[0291] In this specification, the present disclosure has been described with reference to the accompanying drawings, in which exemplary embodiments are shown. However, the present disclosure is not limited to the described exemplary embodiments described and may be modified in various different ways. Consequently, the drawings and description are intended to be illustrative in nature and not limiting. Identical reference numbers denote identical elements in the specification.

[0292] As used herein, the terms "about," "approximately," or "substantially" refer to a value, amount, or property that is close to the specified value, amount, or property. The value, amount, or property is such that a desired function or result is still achieved. According to an example, an amount may be less than 10%, 5%, 1%, or 0.1% of the specified amount, respectively.

[0293] Even if the disclosure has been described and illustrated with reference to illustrative embodiments, various modifications may be made without departing from the scope of the present disclosure as defined in the claims. Such modifications may comprise replacement of features, components and / or method steps with equivalent features, components and / or method steps; mixing of features, components and / or method steps from different embodiments; and / or omitting or combining features, components and / or method steps from described embodiments. All suchmodifications and variations are intended be included herein within the scope of this disclosure and protected by the claims.

Claims

WHAT IS CLAIMED IS:

1. A method for implementing quantum error correction, QEC, on a quantum hardware system, wherein the method includes the steps of: determining a QEC code for encoding logical qubits of a logical quantum circuit in physical qubits, using a subsystem hypergraph product code construction on a first and a second classical error-correction code; and executing the logical quantum circuit on the quantum hardware system, using the determined QEC code; wherein each of the first and second classical error-correction codes belongs to a family of classical error-correction codes, wherein each classical error- correction code of the family of classical error-correction codes is for encoding logical bits in physical bits; wherein, for each code in the family of classical error-correction codes: there is a plurality of physical classical circuits for operating on the physical bits, wherein each physical classical circuit corresponds to a logical reversible XOR circuit operating on the logical bits, and such that, for the family of classical error-correction codes: depth indicators of the physical classical circuits are, as a function of a number of the logical bits encoded by the classical error-correction codes, bounded by a first constant, wherein the depth indicators of the physical classical circuits denote depths of the physical classical circuits disregarding permutations of the physical bits.

2. The method of claim 1, wherein, for each code in the family of classical error- correction codes: at least one linear transformation for operating on the logical bits can be expressed as a sum of binary matrices, each binary matrix representing a respective logical reversible XOR circuit in the logical reversible XOR circuits, andwherein, for the family of classical error-correction codes: a number of summands in each respective sum of binary matrices, as a function of a number of the logical bits encoded by the classical error- correction codes, is bounded by a second constant.

3. The method of claim 1 or 2, wherein the family of classical error-correction codes is the family of simplex codes.

4. The method of any of the preceding claims, wherein the physical classical circuits comprise permutations of the physical bits.

5. The method of any of the preceding claims, wherein the depth indicators of the physical classical circuits are zero.

6. The method of any of the preceding claims, wherein the first and second classical error-correction codes belong to two different families of classical error- correction codes.

7. The method of any of the preceding claims, wherein the first and second classical error-correction codes belong to the same family of classical error- correction codes.

8. The method of claim 7, wherein the first and second classical error-correction codes are identical.

9. The method of any of the preceding claims, wherein determining the QEC code comprises the step of: selecting the QEC code out of a plurality of QEC codes which differ in the first classical error-correction code and / or second classical error-correction code of the subsystem hypergraph product code construction.

10. The method of any of the preceding wherein determining the QEC code comprises determining the QEC based on a predefined selection of the QEC code.

11. The method of any of the preceding claims, wherein determining the QEC code comprises determining the QEC code based on a user input.

12. The method of any of the preceding claims, wherein the at least one linear transformation comprises all linear transformations for operating on the logical bits.

13. The method of any of the preceding claims, wherein the at least one linear transformation comprises all linear transformations operating on a subset of the logical bits.

14. The method of any of the preceding claims, wherein executing the logical quantum circuit comprises mapping the logical quantum circuit to a physical quantum circuit, and executing the physical quantum circuit.

15. The method of claim 14 when depending on claim 8, wherein mapping the logical quantum circuit to the physical quantum circuit comprises mapping a logical Hadamard gate on each of the logical qubits in the logical quantum circuit to: a physical Hadamard gate implemented on each of the physical qubits and a permutation of two or more of the logical qubits.

16. The method of claim 14, wherein mapping the logical quantum circuit to a physical quantum circuit comprises replacing a quantum logical operator in the logical quantum circuit with a physical operator implementation for implementing at least one logical CNOT circuit operating on a logical control qubit and a logical target qubit, wherein the logical CNOT circuits are implemented such that the logical control qubit is implemented in a first code block of physical qubits, and the target qubit is implemented in a second code block of physical qubits.

17. The method of claim 16, wherein logical operator comprises a logical CNOT operator within one of first code block or the second code block, and wherein another of the first code block and the second code block comprises an auxiliary code block.

18. The method of claim 17, wherein the auxiliary code block is initiated in an all positive or all zero logical state, and wherein the physical operator implementation is for implementing a measurement on the one of the first code block or the second code block, a correction based on a value of the measurement, and the at least one logical CNOT circuit.

19. The method of claim 17 or 18, wherein the physical operator implementation is for implementing, on the auxiliary code block having an all positive or all zero logical state, at least two logical CNOT circuits.

20. The method of any of claims 16 to 19, wherein the quantum logical operator comprises a logical diagonal Clifford operator within one of the first code block or the second code block, and wherein the other of the first code block and the second code block comprises an auxiliary code block.

21. The method of claim 20, wherein the physical operator implementation is for implementing, on the auxiliary code block having an all positive or all zero logical state, two iterations of: a measurement on the one of the first code block and the second code block, a correction based on a value of the measurement, and the at least one logical CNOT circuit.

22. The method of claim 20, wherein the physical operator implementation is for implementing, on the auxiliary code block having an all positive or all zero logical state, at least two logical CNOT circuits.

23. The method of any of claims 16 to 22, wherein the quantum logical operator comprises a logical diagonal Clifford operator between the first code block and the second code block, wherein the physical operator implementation is for implementing a logical Hadamard transformation of the at least one logicalCNOT circuit, a physical diagonal within the first code block and a physical diagonal circuit within the code block.

24. The method of any of claims 16 to 23, wherein the quantum logical operator comprises a logical Hadamard operator on a logical qubit within one of the first code block or the second code block, wherein the physical operator implementation is for implementing two or more logical diagonal operators acting on the logical qubit, interleaved by one or more logical Hadamard operators acting on all logical qubits within the one of the first code block or the second code block.

25. The method of any of claims 16 to 24, wherein the quantum hardware system is a modular quantum hardware system, wherein the physical qubits of the first code block are in a first module of the modular quantum hardware system, and wherein the physical qubits of the second code block are in a second module of the modular quantum hardware system.

26. A computer program product comprising executable program code configured to, when executed by a computing device, perform the method according to any of claims 1 to 25.

27. A non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method according to any of claims 1 to 25.

28. A device for implementing quantum error correction, QEC, on a quantum hardware system, comprising: at least one processor; and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to:determine a QEC code for qubits of a logical quantum circuit in physical qubits, using a subsystem hypergraph product code construction on a first and a second classical error-correction code; and generate a control signal for controlling the quantum hardware system to execute the logical quantum circuit on the quantum hardware system, using the determined QEC code; wherein each of the first and second classical error-correction codes belongs to a family of classical error-correction codes, wherein each classical error- correction code of the family of classical error-correction codes is for encoding logical bits in physical bits; wherein, for each code in the family of classical error-correction codes: there is a plurality of physical classical circuits for operating on the physical bits, wherein each physical classical circuit corresponds to a logical reversible XOR circuit operating on the logical bits; such that, for the family of classical error-correction codes: depth indicators of the physical classical circuits are, as a function of a number of the logical bits encoded by the classical error-correction codes, bounded by a first constant, wherein the depth indicators of the physical classical circuits denote depths of the physical classical circuits disregarding permutations of the physical bits.

29. An information processing system comprising: a quantum hardware system; at least one processor communicatively coupled to the quantum hardware system; at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executableinstructions which, when executed the at least one processor, cause the at least one processor to: determine a quantum error correction, QEC, code for encoding logical qubits of a logical quantum circuit in physical qubits, using a subsystem hypergraph product code construction on a first and a second classical error-correction code; and generate a control signal for controlling the quantum hardware system to execute the logical quantum circuit on the quantum hardware system, using the determined QEC code; wherein each of the first and second classical error-correction codes belongs to a family of classical error-correction codes, wherein each classical error- correction code of the family of classical error-correction codes is for encoding logical bits in physical bits; wherein, for each code in the family of classical error-correction codes: there is a plurality of physical classical circuits for operating on the physical bits, wherein each physical classical circuit corresponds to a logical reversible XOR circuit operating on the logical bits; such that, for the family of classical error-correction codes: depth indicators of the physical classical circuits are, as a function of a number of the logical bits encoded by the classical error-correction codes, bounded by a first constant, wherein the depth indicators of the physical classical circuits denote depths of the physical classical circuits disregarding permutations of the physical bits.

30. A method for implementing quantum error correction, QEC, on a quantum hardware system, wherein the method includes: executing a logical quantum circuit on the quantum hardware system, using a QEC code for encoding logical qubits of the logical quantum circuit in physicalqubits, wherein the QEC code is using a subsystem hypergraph product code construction on a first simplex code and a second classical simplex code.

31. The method of claim 30, wherein the first classical simplex code is identical to the second classical simplex code.

32. The method of claim 30, wherein the first classical simplex code differs from the second classical simplex code.

33. A device for implementing quantum error correction, QEC, on a quantum hardware system, comprising: at least one processor; and at least one tangible computer-readable storage device communicatively coupled to the at least one processor and which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to: generate a control signal for controlling the quantum hardware system to execute a logical quantum circuit on the quantum hardware system, using a QEC code for encoding logical qubits of the logical quantum circuit in physical qubits, wherein the QEC code is constructed using a subsystem hypergraph product code construction on a first classical simplex code and a second classical simplex code.

34. An information processing system comprising: a quantum hardware system; at least one processor communicatively coupled to the quantum hardware system; andat least one tangible computer- storage device communicatively coupled to the at least one processor which stores processor-executable instructions which, when executed by the at least one processor, cause the at least one processor to: generate a control signal for controlling the quantum hardware system to execute a logical quantum circuit on the quantum hardware system, using a quantum error correction, QEC, code for encoding logical qubits of the logical quantum circuit in physical qubits, wherein the QEC code is constructed using a subsystem hypergraph product code construction on a first classical simplex code and a second classical simplex code.

35. A method including the steps of: determining a QEC code for encoding logical qubits of a logical quantum circuit in physical qubits, using a subsystem hypergraph product code construction on a first and a second classical error-correction code; and estimating a quantity of resources required to execute the logical quantum circuit on a quantum hardware system, using the determined QEC code; wherein each of the first and second classical error-correction codes belongs to a family of classical error-correction codes, wherein each classical error- correction code of the family of classical error-correction codes is for encoding logical bits in physical bits; wherein, for each code in the family of classical error-correction codes: there is a plurality of physical classical circuits for operating on the physical bits, wherein each physical classical circuit corresponds to a logical reversible XOR circuit operating on the logical bits, and such that, for the family of classical error-correction codes: depth indicators of the physical classical circuits are, as a function of a number of the logical bits encoded by the classical error-correction codes,bounded by a first constant, the depth indicators of the physical classical circuits denote the physical classical circuits disregarding permutations of the physical bits.

36. A method including the steps of: estimating a quantity of resources required to execute a logical quantum circuit on a quantum hardware system, using a QEC code for encoding logical qubits of the logical quantum circuit in physical qubits, wherein the QEC code is constructed using a subsystem hypergraph product code construction on a first classical simplex code and a second classical simplex code.

37. A non-transitory, computer-readable storage medium comprising executable program code configured to, when executed by a computing device, perform the method according to claim 35 or claim 36.

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