Method for manufacturing wiring board, and wiring board

Abstract

A method for manufacturing a wiring board includes, in the stated order: a step of forming a resist layer 3 on a metal layer 20 provided on a support 1; a step of forming a pattern, including an opening 3A through which the metal layer 20 is exposed, on the resist layer 3 by exposure and development of the resist layer 3; a step of forming a copper plating layer 21 on the metal layer 20 exposed within the opening 3A by electrolytic plating; a step of removing the resist layer 3; a step of filling at least a part of an opening void 21A opening at a surface of the copper plating layer 21; and a step of removing an exposed part of the metal layer 20 by etching.

Description

Method for manufacturing wiring board, and wiring board

[0001] The present disclosure relates to a method for manufacturing a wiring board, and a wiring board.

[0002] Wiring boards that constitute electronic devices are required to have fine-width wiring to meet the demands for smaller, lighter, and faster electronic devices. Semi-additive (SAP) and modified semi-additive (MSAP) methods are widely used to form fine-width wiring (see Patent Document 1). These methods generally include a step of forming a copper plating layer on a metal layer by electroplating.

[0003] Japanese Patent Application Laid-Open No. 2004-6773

[0004] Such a wiring board is usually manufactured by forming a resist layer on a metal layer as a seed layer provided on a support, forming a pattern in the resist layer by exposure and development, forming a copper plating layer on the metal layer by electrolytic plating, peeling the resist layer from the metal layer, and removing the metal layer by etching.

[0005] When a copper plating layer is formed by electrolytic plating on a metal layer serving as a seed layer, voids may form in the copper plating layer near the interface between the metal layer and the copper plating layer. If such voids are open voids that open on the surface of the copper plating layer, the etchant penetrates the open voids, causing them to expand and extend along the interface between the metal layer and the copper plating layer. As a result, the connection stability of the copper plating layer to the metal layer is reduced, which may cause the copper plating layer to collapse or peel off. In particular, when forming wiring with a very small width, the reduced connection stability of the copper plating layer to the metal layer is a major problem.

[0006] Therefore, an object of the present disclosure is to provide a method for manufacturing a wiring board that can improve the connection stability of a copper plating layer to a metal layer, and the wiring board.

[0007] [1] A method for manufacturing a wiring board according to the present disclosure includes, in this order, a step of forming a resist layer on a metal layer provided on a support, a step of exposing and developing the resist layer to form a pattern in the resist layer, the pattern including openings that expose the metal layer, a step of forming a copper plating layer by electrolytic plating on the metal layer exposed in the openings, a step of removing the resist layer, a step of filling at least a portion of the opening voids that open from the surface of the copper plating layer, and a step of removing the exposed portions of the metal layer by etching.

[0008] In this method for manufacturing a wiring board, since at least a portion of the open voids is filled before the metal layer exposed by removing the resist layer is removed by etching, it is possible to prevent the etching solution from penetrating into the open voids when removing the metal layer by etching, thereby preventing the open voids from increasing due to the penetration of the etching solution, and improving the connection stability of the copper plating layer to the metal layer.

[0009] [2] In the method for manufacturing a wiring board according to [1], the step of filling the open voids may include sealing the openings of the open voids in the surface of the copper plating layer. In this method for manufacturing a wiring board, sealing the openings of the open voids in the surface of the copper plating layer can further prevent the etching solution from penetrating into the open voids when removing the metal layer by etching.

[0010] [3] In the method for manufacturing a wiring board according to [1] or [2], the copper plating layer may be heated to 150° C. or higher and 210° C. or lower in the step of filling the open void. In this method for manufacturing a wiring board, by heating the copper plating layer to 150° C. or higher and 210° C. or lower, it is possible to form a thick copper oxide on the surface of the copper plating layer while suppressing thermal deformation of the copper plating layer and excessive growth of an oxide film. This makes it possible to fill at least a portion of the open void.

[0011] [4] In the method for manufacturing a wiring board according to [3], the step of filling the open voids may involve heating the copper plating layer in an oxygen-containing atmosphere. In this method for manufacturing a wiring board, heating the copper plating layer in an oxygen-containing atmosphere allows thick copper oxide to be formed on the surface of the copper plating layer, and the copper oxide formed on the surface of the copper plating layer can fill at least a portion of the open voids.

[0012] [5] A wiring board according to the present disclosure includes a support, a metal layer provided on the support, and wiring having a copper plating layer formed on the metal layer, wherein copper oxide is formed on the surface of the copper plating layer, and at least a portion of voids formed in the copper plating layer are filled with copper oxide.

[0013] In this wiring board, copper oxide is formed on the surface of the copper plating layer, and at least a portion of the voids formed in the copper plating layer are filled with copper oxide, thereby improving the connection stability of the copper plating layer to the metal layer.

[0014] [6] In the wiring board according to [5], the thickness of the copper oxide may be 300 nm or less. In this wiring board, the thickness of the copper oxide formed on the surface of the copper plating layer is 300 nm or less, which allows for the copper plating layer to be finer and the reliability to be improved.

[0015] [7] In the wiring board according to [5] or [6], the voids may include open voids that open from the surface of the copper plating layer, and the length of the open voids from the surface of the copper plating layer may be ⅓ or less of the width of the copper plating layer. In this wiring board, the length of the open voids from the surface of the copper plating layer is ⅓ or less of the width of the copper plating layer, which further improves the connection stability of the copper plating layer to the metal layer.

[0016] [8] In the wiring board according to any one of [5] to [7], the wiring may include a linear portion, and the linear portion may have a width of 5 μm to 20 μm. In this wiring board, although the width of the linear portion of the wiring is as fine as 5 μm to 20 μm, at least a portion of the voids formed in the copper plating layer are filled with copper oxide, thereby improving the connection stability of the copper plating layer to the metal layer.

[0017] According to the present disclosure, the connection stability of the copper plating layer to the metal layer can be improved.

[0018] 1(a), 1(b), 1(c), 1(d), 1(e), and 1(f) are schematic cross-sectional views showing an example of a method for manufacturing a wiring substrate. A schematic cross-sectional view showing a state in which a resist layer has been peeled off from a metal layer. A schematic cross-sectional view showing a state in which an exposed portion of the metal layer has been removed by etching without filling an open void. A schematic cross-sectional view showing a state in which a resist layer has been peeled off from a metal layer. A schematic cross-sectional view showing a state in which an exposed portion of the metal layer has been removed by etching. A schematic cross-sectional view showing another example in which an exposed portion of the metal layer has been removed by etching. FIG. 7(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 1, and FIG. 7(b) is an enlarged cross-sectional photograph at a higher magnification than FIG. 7(a). FIG. 8(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 2, and FIG. 8(b) is an enlarged cross-sectional photograph at a higher magnification than FIG. 8(a). Fig. 9(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 3, and Fig. 9(b) is an enlarged cross-sectional photograph at a higher magnification than Fig. 9(a). Fig. 10(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 4, and Fig. 10(b) is an enlarged cross-sectional photograph at a higher magnification than Fig. 10(a). Fig. 11(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 5, and Fig. 11(b) is an enlarged cross-sectional photograph at a higher magnification than Fig. 11(a). Fig. 12(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 6, and Fig. 12(b) is an enlarged cross-sectional photograph at a higher magnification than Fig. 12(a).

[0019] The present invention is not limited to the following examples.

[0020] Fig. 1 is a schematic cross-sectional view showing an example of a method for manufacturing a wiring board. The method shown in Fig. 1 includes a step of forming a metal layer 20 on one main surface of a plate-shaped support 1 (see Fig. 1(a)), a step of forming a resist layer 3 on the metal layer 20 (see Fig. 1(b)), a step of exposing and developing the resist layer 3 to form a pattern in the resist layer 3 including openings 3A through which the metal layer 20 is exposed (see Fig. 1(c)), a step of pretreating the surface of the metal layer 20 exposed in the openings 3A by contacting it with a pretreatment solution at a predetermined pretreatment temperature, and a step of plating copper on the metal layer 20 by electrolytic plating. The method includes, in this order, a step of forming a copper plating layer 21 (see FIG. 1(d)), a step of removing the resist layer 3 to expose a portion of the metal layer 20 that is not covered with the copper plating layer 21 (see FIG. 1(e)), a step of filling at least a portion of an opening void 21A (see FIG. 2) that opens from the surface of the copper plating layer 21, and a step of removing the exposed portion of the metal layer 20 by etching to form a wiring board 10 that has wiring 2 having the metal layer 20 and the copper plating layer 21 and a support 1 (see FIG. 1(f)).

[0021] The outermost layer of the support 1 on the side where the metal layer 20 is provided is usually mainly composed of an insulating layer. The insulating layer provided as the outermost layer of the support 1 may be, for example, an insulating resin layer such as a build-up layer. The support 1 may include wiring connected to the wiring 2. The support 1 may include an insulating substrate which is a laminate formed from a plurality of prepregs.

[0022] The metal layer 20 functions as a seed layer for electrolytic plating. The metal layer 20 may be, for example, a metal plating layer formed by electroless plating, a metal foil such as copper foil, a layer formed by vapor deposition such as sputtering, or a metal sintered layer. The metal sintered layer is formed by heating a coating film containing metal particles to sinter the metal particles. The metal constituting the metal layer 20 may include, for example, at least one metal selected from the group consisting of copper, gold, silver, tungsten, molybdenum, tin, cobalt, chromium, iron, and zinc. The metal layer 20 may be a single layer or may be composed of two or more layers. The thickness of the metal layer 20 may be, for example, 0.1 to 2.0 μm.

[0023] The resist layer 3 can be formed of a photosensitive resist material that is commonly used to form wiring. The thickness of the resist layer 3 may be, for example, 10 to 50 μm. The resist material for forming the resist layer 3 may be, for example, a photosensitive resin composition containing a binder polymer, a photopolymerizable compound having an ethylenically unsaturated bond, and a photopolymerization initiator.

[0024] To form the resist layer 3, a resist film containing a photosensitive resin composition may be laminated on the metal layer 20, or a photosensitive resin composition containing a solvent may be applied to the metal layer 20 and the solvent may be removed from the coating.

[0025] In the step of forming a pattern in the resist layer 3 (see FIG. 1(c)), a portion of the resist layer 3 is exposed to light and the exposed resist layer 3 is developed to form the resist layer 3 having a pattern including openings 3A. The exposure and development can be performed by a conventional method known to those skilled in the art. By exposure through a photomask, a fine pattern including openings 3A that expose the metal layer 20 is formed. The developer for development may be an alkaline aqueous solution such as an aqueous sodium carbonate solution.

[0026] In the pretreatment step, the surface of the metal layer 20 exposed in the opening 3A is pretreated by contact with a pretreatment liquid having a predetermined pretreatment temperature. For example, the surface of the metal layer 20 can be pretreated by immersing an intermediate structure including the support 1, the metal layer 20, and the patterned resist layer 3 in a pretreatment liquid adjusted to a predetermined pretreatment temperature. The pretreatment temperature may be set appropriately depending on the type of pretreatment liquid, etc., and may be, for example, within a range of 20 to 50°C. The immersion time in the pretreatment liquid may be, for example, 1 to 8 minutes.

[0027] In the step of forming a copper plating layer 21 (see FIG. 1(d)), a copper plating layer 21 filling the opening 3A is formed on the surface of the pretreated metal layer 20 by electrolytic plating.

[0028] In the step of removing the resist layer 3 (see FIG. 1( e )), the resist layer 3 is peeled off from the metal layer 20 .

[0029] 2 is a schematic cross-sectional view showing a state in which the resist layer has been peeled off from the metal layer. As shown in FIG. 2, when a copper plating layer 21 is formed on the surface of a metal layer 20 by electrolytic plating, voids may be formed in the copper plating layer 21 near the interface between the metal layer 20 and the copper plating layer 21. Such voids include open voids 21A that open to the surface of the copper plating layer 21.

[0030] 3 is a schematic cross-sectional view showing the state in which the exposed portion of the metal layer 20 is removed by etching without filling the open voids. As shown in FIG. 3 , if the next step of removing the exposed portion of the metal layer 20 by etching (see FIG. 1( f)) is performed without filling at least a portion of the open voids 21A, the open voids 21A will expand and extend along the interface between the metal layer 20 and the copper plating layer 21 due to penetration of the etching solution. As a result, the connection stability of the copper plating layer 21 to the metal layer 20 will decrease, which may cause the copper plating layer 21 to collapse or the copper plating layer 22 to peel off. The narrower the width of the copper plating layer 21, the more likely the copper plating layer 21 will collapse or the copper plating layer 22 to peel off.

[0031] 4 is a schematic cross-sectional view showing a state in which the resist layer has been peeled off from the metal layer. As shown in FIG. 4, in the step of filling at least a portion of the open void 21A, the open void 21A is filled at least in part so that the etching solution does not penetrate into the open void 21A and increase the size of the open void 21A in the subsequent step of removing the exposed portion of the metal layer 20 by etching (see FIG. 1( f)). In this step, the open void 21A may be filled entirely, or only in part. Alternatively, the opening of the open void 21A on the surface of the copper plating layer 21 may be blocked.

[0032] In this process, for example, the copper plating layer 21 may be heated to 150°C or higher and 210°C or lower, preferably 160°C or higher and 200°C or lower, and more preferably 170°C or higher and 190°C or lower, to at least partially fill the open voids 21A. The copper plating layer 21 may be heated for, for example, 5 minutes or higher and 200 minutes or lower, preferably 20 minutes or higher and 120 minutes or lower, and more preferably 30 minutes or higher and 60 minutes or lower. The copper plating layer 21 may also be heated in an oxygen-containing atmosphere. This results in a thick copper oxide 21B being formed on the surface of the copper plating layer 21, and the copper oxide 21B formed on the surface of the copper plating layer 21 at least partially fills the open voids 21A. The thickness T1 of the copper oxide 21B formed on the surface of the plating layer 21 is, for example, 10 nm or higher and 300 nm or lower, preferably 20 nm or higher and 200 nm or lower, and more preferably 20 nm or higher and 100 nm or lower. In this step, other means may be used as long as they can fill at least a part of the open void 21A.

[0033] 5 is a schematic cross-sectional view showing the state in which the exposed portions of the metal layer have been removed by etching. As shown in FIG. 5, in the step of removing the exposed portions of the metal layer 20 by etching (see FIG. 1( f )), the portions of the metal layer 20 exposed by the peeling of the resist layer 3 are removed by etching (wet etching). The etching solution may be, for example, a mixed solution of hydrogen peroxide, sulfuric acid, copper sulfate, iron sulfate, etc. As a result, wiring 2 is formed, which is composed of the metal layer 20 remaining on the support 1 and the metal plating layer 21.

[0034] The electrolytic plating layer 21 may include linear portions, and the width of these linear portions may be 2 μm or more and 20 μm or less. Furthermore, as shown in FIG. 1 , the wiring 2 may include linear portions 2 a, and the width w of these linear portions 2 a may be 2 μm or more and 20 μm or less. In other words, the line / space (L / S) of the wiring 2 may be 2 μm / 2 μm to 20 μm / 20 μm. The linear portions 2 a are portions that extend linearly.

[0035] The wiring board 10 manufactured by the above steps includes a support 1, a metal layer 20 provided on the support 1, and wiring 2 having a copper plating layer 21 formed on the metal layer 20. Copper oxide 21B is formed on the surface of the copper plating layer 21, and at least a portion of voids formed in the copper plating layer 21 near the interface between the metal layer 20 and the copper plating layer 21 is filled with the copper oxide 21B formed on the surface of the copper plating layer 21. The thickness T2 of the copper oxide 21B formed on the surface of the plating layer 21 is, for example, 0 nm or more and 300 nm or less, preferably 0 nm or more and 200 nm or less, and more preferably 0 nm or more and 100 nm or less. A thickness T2 of 0 nm of the copper oxide 21B formed on the surface of the plating layer 21 means that no copper oxide 21B is formed on the surface of the plating layer 21, or that the copper oxide 21B formed on the surface of the plating layer 21 has been completely removed by etching.

[0036] 6 is a schematic cross-sectional view showing another example of the state in which the exposed portion of the metal layer has been removed by etching. As shown in FIG. 6 , when an open void 21A remains in the copper plating layer 21, the length L of the open void 21A from the surface of the copper plating layer 21 is 1 / 3 or less, preferably 1 / 5 or less, and more preferably 1 / 10 or less of the width W of the copper plating layer 21. The length L of the open void 21A from the surface of the copper plating layer 21 is the linear distance from the start point to the end point of the open void 21A in a direction perpendicular to the direction in which the wiring 2 extends. The width W of the copper plating layer 21 is the width of the linear portion of the electrolytic plating layer 21.

[0037] As described above, in the method for manufacturing a wiring board according to this embodiment, since at least a portion of the open void 21A is filled before the metal layer 20 exposed by the removal of the resist layer 3 is removed by etching, it is possible to prevent the etchant from penetrating into the open void 21A when removing the metal layer 20 by etching. This makes it possible to prevent the open void 21A from increasing due to the penetration of the etchant, thereby improving the connection stability of the copper plating layer 21 to the metal layer 20.

[0038] Furthermore, by closing the openings of the open voids on the surface of the copper plating layer, it is possible to further prevent the etching solution from penetrating into the open voids 21A when removing the metal layer 20 by etching.

[0039] Furthermore, by heating the copper plating layer 21 to 150°C or higher, preferably 160°C or higher, and more preferably 170°C or higher, a thick copper oxide 21B can be formed on the surface of the copper plating layer 21. This allows at least a portion of the open void 21A to be filled. On the other hand, by heating the copper plating layer 21 to 210°C or lower, preferably 200°C or lower, and more preferably 190°C or lower, it is possible to suppress thermal deformation of the copper plating layer 21 and excessive growth of an oxide film.

[0040] Furthermore, by heating the copper plating layer 21 in an atmosphere containing oxygen, a thick copper oxide 21B can be formed on the surface of the copper plating layer 21, and the copper oxide 21B formed on the surface of the copper plating layer 21 can fill at least a portion of the open void 21A.

[0041] In the wiring board 10 according to this embodiment, copper oxide 21B is formed on the surface of the copper plating layer 21, and at least a portion of the voids formed in the copper plating layer 21 are filled with copper oxide 21B, thereby improving the connection stability of the copper plating layer 21 to the metal layer 20.

[0042] Furthermore, by setting the thickness T2 of the copper oxide 21B formed on the surface of the copper plating layer 21 to 300 nm or less, preferably 200 nm or less, and more preferably 100 nm or less, the copper plating layer 21 can be made finer and its reliability improved.

[0043] Furthermore, by making the length L of the opening void 21A from the surface of the copper plating layer 21 1 / 3 or less, preferably 1 / 5 or less, and more preferably 1 / 10 or less of the width W of the copper plating layer 21, the connection stability of the copper plating layer 21 to the metal layer 20 can be further improved.

[0044] Furthermore, although the width w of the linear portion 2a of the wiring 2 is fine, at 5 μm or more and 20 μm or less, at least a portion of the voids formed in the copper plating layer 21 is filled with copper oxide 21B, thereby improving the connection stability of the copper plating layer 21 to the metal layer 20.

[0045] The present invention is not limited to the following examples.

[0046] A copper seed layer was formed by electroless plating on an insulating material (ABF GL102de, manufactured by Ajinomoto Fine-Techno Co., Ltd.) for forming an insulating resin layer, which served as a support. Next, a resist film (RY-A003-06, manufactured by Resonac Co., Ltd.) was laminated on the prepared support at 110°C using a roll laminator, producing a support in which the resist film was laminated on the support. This was then left to stand at 5°C for one day. Next, an i-line stepper (manufactured by Ushio Inc.) was used to apply 172 mJ / cm ２ The resist film was exposed under the conditions of AF-16 μm and left for 30 minutes. Next, the resist film was developed using a spray developer with a 1 wt % aqueous sodium carbonate solution at 30° C. and 2 MD.

[0047] Next, as a pretreatment, the laminate with the exposed and developed resist film was immersed in a commercially available acid cleaner at 30 ° C for 3 minutes, and then immersed in a 10% aqueous sulfuric acid solution at room temperature for 1 minute. Next, the pretreated laminate was immersed in an electroplating solution (CPL1913860, manufactured by Tama Chemicals Co., Ltd.) and electroplated on the seed layer at 2 ASD for 12 minutes. Next, the resist film was removed by spraying a stripper (R101 and R100S, manufactured by Mitsubishi Gas Chemical Trading Co., Ltd.) at 60 ° C for 1 minute.

[0048] Next, the laminates of Reference Examples 2 to 6 from which the resist film had been removed were heated under the conditions shown in Table 1. The laminate of Reference Example 1 was not heated. Cross-sectional photographs of the lamination areas of Reference Examples 1 to 6 are shown in Figures 7 to 12. Figure 7(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 1, and Figure 7(b) is an enlarged cross-sectional photograph at a higher magnification than Figure 7(a). Figure 8(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 2, and Figure 8(b) is an enlarged cross-sectional photograph at a higher magnification than Figure 8(a). Figure 9(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 3, and Figure 9(b) is an enlarged cross-sectional photograph at a higher magnification than Figure 9(a). Figure 10(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 4, and Figure 10(b) is an enlarged cross-sectional photograph at a higher magnification than Figure 10(a). Fig. 11(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 5, and Fig. 11(b) is an enlarged cross-sectional photograph at a higher magnification than Fig. 11(a). Fig. 12(a) is an enlarged cross-sectional photograph of the laminate of Reference Example 6, and Fig. 12(b) is an enlarged cross-sectional photograph at a higher magnification than Fig. 12(a).

[0049]

[0050] As shown in Table 1 and Figure 7, in Reference Example 1, in which no heating was performed after removing the resist layer, open voids were observed on the surface of the copper plating layer. As shown in Table 1, Figures 8 and 9, in Reference Example 2, in which heating was performed at 130°C for 30 minutes, and Reference Example 3, in which heating was performed at 150°C for 30 minutes, copper oxide was formed on the surface of the copper plating layer, but open voids were observed on the surface of the copper plating layer. In contrast, as shown in Table 1 and Figures 10 to 12, in Reference Example 4, in which heating was performed at 180°C for 30 minutes, Reference Example 5, in which heating was performed at 200°C for 30 minutes, and Reference Example 6, in which heating was performed at 200°C for 60 minutes, thick copper oxide was formed on the surface of the copper plating layer, and open voids were not observed on the surface of the copper plating layer. This is presumably because the open voids on the surface of the copper plating layer were filled with copper oxide.

[0051] From these results, it is inferred that by heating the copper plating layer at a temperature higher than 150°C, a thick copper oxide is formed on the surface of the copper plating layer, and open voids that open on the surface of the copper plating layer are filled with copper oxide.

[0052] 1...support, 2...wiring, 2a...linear portion, 3...resist layer, 20...metal layer, 21...copper plating layer, 21A...open void, 21B...copper oxide, 10...wiring substrate.

Claims

1. A method for manufacturing a wiring board, comprising the steps of: forming a resist layer on a metal layer provided on a support; exposing and developing the resist layer to form a pattern in the resist layer, the pattern including openings that expose the metal layer; forming a copper plating layer by electrolytic plating on the metal layer exposed in the openings; removing the resist layer; filling at least a portion of the opening voids that open from the surface of the copper plating layer; and removing the exposed portions of the metal layer by etching, in this order.

2. The method for manufacturing a wiring board according to claim 1, wherein the step of filling the open voids comprises sealing the openings of the open voids on the surface of the copper plating layer.

3. The method for manufacturing a wiring board according to claim 1 or 2, wherein the step of filling the open voids involves heating the copper plating layer to a temperature of 150°C or higher and 210°C or lower.

4. The method for manufacturing a wiring board according to claim 3, wherein the step of filling the open voids comprises heating the copper plating layer in an atmosphere containing oxygen.

5. A wiring board comprising: a support; a metal layer provided on the support; and wiring having a copper plating layer formed on the metal layer, wherein copper oxide is formed on the surface of the copper plating layer, and at least a portion of voids formed in the copper plating layer are filled with the copper oxide.

6. The wiring board according to claim 5, wherein the thickness of the copper oxide is 300 nm or less.

7. The wiring board according to claim 5 or 6, wherein the voids include open voids that open from the surface of the copper plating layer, and the length of the open voids from the surface of the copper plating layer is 1 / 3 or less of the width of the copper plating layer.

8. The wiring board according to claim 5 or 6, wherein the wiring includes a linear portion, and the width of the linear portion is 5 μm or more and 20 μm or less.

Images