Amplifier circuit and electronic apparatus

Abstract

Distortion in the output of an amplifier circuit is reduced while improving driving efficiency.　An amplifier circuit according to the present invention includes: a ΔΣ modulator for outputting a digital input by reducing the bit rate thereof; a PWM unit for generating a pulse width modulation (PWM) signal on the basis of the digital output of the ΔΣ modulator; a driver for generating an analog drive signal on the basis of the PWM signal; and a digital feedback unit for applying digital feedback on the basis of the result of a ΔΣAD conversion of the drive signal. The digital feedback unit may include a ΔΣ analog to digital converter (ADC) that performs AD conversion by oversampling the drive signal.

Description

Amplification circuits and electronic devices

[0001] The present technology relates to an amplifier circuit and an electronic device. More particularly, the present technology relates to an amplifier circuit and an electronic device that can operate as a class D amplifier.

[0002] A class D amplifier is sometimes used to drive electronic devices more efficiently. For example, a technology using a highly efficient class D amplifier as a power amplifier for driving an electroacoustic transducer such as a speaker or a headphone has been disclosed (see, for example, Patent Document 1).

[0003] JP 2022-62988 A

[0004] However, in the above-mentioned conventional technology, analog feedback is used to reduce distortion in the class D amplifier, which may lead to increased power consumption.

[0005] This technology was developed in light of these circumstances, and aims to achieve low distortion in the output of amplifier circuits while improving drive efficiency.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an amplifier circuit including a ΔΣ modulator that converts a digital input into a low-bit signal and outputs it, a PWM unit that generates a PWM (Pulse Width Modulation) signal based on the digital output of the ΔΣ modulator, a driver that generates an analog drive signal based on the PWM signal, and a digital feedback unit that applies digital feedback based on a result of ΔΣAD (Analog to Digital) conversion of the drive signal. This brings about the effect of reducing distortion in a class-D amplifier based on digital feedback.

[0007] In addition, in the first aspect, the digital feedback unit may include a ΔΣ ADC (Analog to Digital Converter) that oversamples and AD converts the drive signal, a decimation filter that reduces the rate of an ADC output from the ΔΣ ADC, and a first undersampling unit that undersamples a filter output from the decimation filter, and applies digital feedback based on the output of the first undersampling unit. This brings about the effect of achieving high accuracy in ΔΣ AD conversion while realizing digital feedback to a stage preceding the ΔΣ modulator.

[0008] In the first aspect, the decimation filter may thin out the ADC output in synchronization with the PWM, thereby reducing noise generated in accordance with the PWM cycle.

[0009] In addition, in the first aspect, the digital feedback unit may include a calculation unit that calculates a feedback gain for the output of the first undersampling unit, a subtractor that subtracts the output of the calculation unit from the digital input, and an integrator that integrates the output of the subtractor and inputs the result to the ΔΣ modulator. This provides the effect of reducing high-frequency noise due to the PWM carrier wave and ΔΣ modulation while applying digital feedback to low-frequency signal components.

[0010] In addition, in a first aspect, the digital feedback unit may include a first calculation unit that generates a calculation result of a first feedback gain based on the output of the first undersampling unit, a first subtractor that subtracts the output of the first calculation unit from the digital input, a first integrator that integrates the output of the first subtractor, a second calculation unit that generates a calculation result of a second feedback gain based on the output of the first undersampling unit, a second subtractor that subtracts the output of the second calculation unit from the output of the first integrator, and a second integrator that integrates the output of the second subtractor and inputs it to the ΔΣ modulator. This provides the effect of ensuring the effectiveness of digital feedback on low-frequency signal components while suppressing operational instability due to digital feedback.

[0011] In the first aspect, the digital feedback unit may further include an attenuation unit that attenuates high-frequency components including quantization noise output from the ΔΣ modulator, thereby achieving digital feedback to low-frequency signal components while suppressing operational instability due to delays in digital feedback.

[0012] In addition, in a first aspect, the attenuation unit may include an oversampling unit that oversamples the digital output of the ΔΣ modulator, a dummy filter that reduces the rate of the output of the oversampling unit based on the dummy operation of the decimation filter, a second undersampling unit that undersamples the dummy output of the dummy filter, a first high-pass filter that passes high-frequency components of the output of the second undersampling unit, and a third subtractor that subtracts the output of the first high-pass filter from the output of the first undersampling unit. This achieves high accuracy in ΔΣ AD conversion, realizes digital feedback to low-frequency signal components, and suppresses operational instability due to delays in the digital feedback.

[0013] In the first aspect, the decimation filter and the dummy filter may be a CIC (Cascaded Integrator Comb) filter, thereby achieving anti-aliasing in undersampling.

[0014] In the first aspect, the digital feedback unit may further include a compensation unit that extracts high-frequency signal components from the digital input input to the ΔΣ modulator and compensates for the high-frequency signal components attenuated by the attenuation unit. This makes it possible to compensate for the loss of high-frequency signal components in the attenuation unit, thereby stabilizing the digital feedback.

[0015] In the first aspect, the compensation unit may include a delay unit that delays the digital input input to the ΔΣ modulator, a second high-pass filter that passes high-frequency components of the output of the delay unit, and an adder that adds the output of the second high-pass filter to the output of the third subtractor, thereby extracting high-frequency signal components from the digital input and compensating for the loss of the high-frequency signal components.

[0016] A second aspect of the present invention is an electronic device comprising a load and an amplifier circuit for driving the load, the amplifier circuit including a ΔΣ modulator for converting a digital input into a low-bit signal and outputting the low-bit signal, a PWM unit for generating a PWM (Pulse Width Modulation) signal based on the digital output of the ΔΣ modulator, a driver for generating an analog drive signal based on the PWM signal, and a digital feedback unit for applying digital feedback based on the result of ΔΣAD (Analog to Digital) conversion of the drive signal. This provides the effect of realizing low distortion in the output of the amplifier circuit while improving the efficiency of driving the electronic device.

[0017] In the second aspect, the load may be a speaker, thereby achieving low distortion in the output of the amplifier circuit while improving the efficiency of driving the speaker.

[0018] FIG. 1 is a block diagram showing a configuration example of an amplifier circuit according to a first embodiment; FIG. 2 is a diagram showing signal waveforms of each part of the amplifier circuit according to the first embodiment; FIG. 3 is a diagram showing an enlarged view of signal waveforms of each part of the amplifier circuit according to the first embodiment; FIG. 4 is a diagram showing a further enlarged view of signal waveforms of each part of the amplifier circuit according to the first embodiment; FIG. 5 is a block diagram showing a configuration example of an amplifier circuit according to a second embodiment; FIG. 6 is a block diagram showing a configuration example of an amplifier circuit according to a third embodiment; and FIG. 7 is a diagram showing an example of an electronic device to which an amplifier circuit according to a fourth embodiment is applied.

[0019] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which digital feedback is applied based on the result of ΔΣ AD (Analog to Digital) conversion of a drive signal, high-frequency components including quantization noise are attenuated in the digital feedback loop, and high-frequency signal components lost during this process are compensated for) 2. Second embodiment (an example in which digital feedback is applied based on the result of ΔΣ AD conversion of a drive signal, without attenuating high-frequency components including quantization noise and compensating for high-frequency signal components in the digital feedback loop) 3. Third embodiment (an example in which digital feedback is applied based on the result of ΔΣ AD conversion of a drive signal, and one stage of digital feedback gain is applied, without attenuating high-frequency components including quantization noise and compensating for high-frequency signal components in the digital feedback loop) 4. Fourth embodiment (an example in which an amplifier circuit that applies digital feedback based on the result of ΔΣ AD conversion of a drive signal is applied to an electronic device)

[0020] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an amplifier circuit according to a first embodiment.

[0021] In the figure, the amplifier circuit AM1 can operate as a class D amplifier that drives the speaker SP. In this case, the amplifier circuit AM1 can apply digital feedback based on the result of ΔΣAD (Analog to Digital) conversion of the drive signal SD that drives the speaker SP. The amplifier circuit AM1 also attenuates high-frequency components, including quantization noise, in the digital feedback loop and compensates for the high-frequency signal components that are lost during this process, thereby suppressing an increase in noise in the digital feedback loop and ensuring the stability of the digital feedback loop.

[0022] The amplifier circuit AM1 includes an arithmetic unit 111, a ΔΣ modulator 101, a PWM unit 116, a driver 117, and a digital feedback unit 121.

[0023] The calculation unit 111 multiplies the digital input DIN by a coefficient b1 and outputs the result to the subtractor 112. At this time, the PWM frequency of the digital input DIN can be set to fm.

[0024] The ΔΣ modulator 101 reduces the bit depth of the digital input DIN, which has been subjected to digital feedback via the digital feedback unit 121, to generate a digital output Do. At this time, the ΔΣ modulator 101 can reduce the gradation of the digital input DIN and output it to the PWM unit 116. For example, the ΔΣ modulator 101 may convert the 256-level digital input DIN into an 8-level digital output and output it to the PWM unit 116. Here, the ΔΣ modulator 101 can perform noise shaping by operating as a low-pass filter for the signal input and as a high-pass filter for quantization noise. At this time, the ΔΣ modulator 101 can operate as an error feedback type. The ΔΣ modulator 101 includes an adder 102, a quantizer 103, a subtractor 104, and a loop filter 105.

[0025] Adder 102 adds the output of integrator 115 and the output of loop filter 105 and outputs the result to quantizer 103 and subtractor 104. Quantizer 103 reduces the gradation of the output of adder 102 and feeds it back to subtractor 104, while also outputting the result to oversampling unit 132 and PWM unit 116. Subtractor 104 subtracts the output of adder 102 from the output of quantizer 103 and outputs the result to loop filter 105.

[0026] The loop filter 105 integrates the output of the subtractor 104 and outputs the integrated value to the adder 102. At this time, the loop filter 105 can suppress quantization noise at low frequencies within the signal band and increase quantization noise at high frequencies outside the signal band.

[0027] The PWM unit 116 generates a PWM (Pulse Width Modulation) signal based on the digital output Do of the ΔΣ modulator. At this time, the PWM clock frequency of the PWM unit 116 can be set to fc.

[0028] The driver 117 generates an analog drive signal SD based on the PWM signal generated by the PWM unit 116 and outputs the analog drive signal SD to the speaker SP.

[0029] The digital feedback unit 121 applies digital feedback based on the ΔΣ AD conversion result of the drive signal SD. The digital feedback unit 121 includes a ΔΣ ADC 122, a decimation filter 123, and an undersampling unit 124. The digital feedback unit 121 also includes calculation units 125 and 126, integrators 113 and 115, and subtractors 112 and 114. The digital feedback unit 121 also includes a high-frequency attenuation unit 131 and a high-frequency compensation unit 141.

[0030] The ΔΣ ADC 122 oversamples the drive signal SD and performs AD conversion. The rate of change of the ADC output ADO of the ΔΣ ADC 122 from low level to high level depends on the rate of change of the analog input. In this case, the ΔΣ ADC 122 can operate as a continuous-time ΔΣ ADC. The ΔΣ ADC 122 performs oversampling to reduce quantization noise. Here, the ΔΣ ADC 122 can move the quantization noise to a high-frequency band by oversampling and improve the S / N ratio by noise shaping. In this case, the ADC frequency of the ΔΣ ADC 122 can be set to fa. The ADC frequency fa can be given by N×fm (N is a real number greater than 1). Furthermore, the PWM clock frequency fc can be given by 2×fa.

[0031] The decimation filter 123 reduces the rate of the ADC output ADO of the ΔΣ ADC 122. At this time, the decimation filter 123 can thin out the ADC output ADO in synchronization with the PWM period of the PWM unit 116. The decimation filter 123 may be a CIC (Cascaded Integrator Comb) filter.

[0032] The undersampling unit 124 undersamples the filter output FO of the decimation filter 123 and outputs the result to the subtractor 136. At this time, the undersampling unit 124 can reduce the frequency of the filter output FO of the decimation filter 123 to 1 / N. This allows the ΔΣ ADC 122 to oversample the drive signal SD while aligning the frequency of the digital input DIN with the frequency of the digital feedback signal superimposed on the digital input DIN.

[0033] The calculation unit 125 generates a calculation result of the feedback gain af1 based on the output of the undersampling unit 124. At this time, the calculation unit 125 can attenuate high-frequency components including quantization noise from the output of the undersampling unit 124 and multiply the signal with the high-frequency signal components compensated for by the feedback gain af1. The subtractor 112 subtracts the output of the calculation unit 125 from the output of the calculation unit 111. The integrator 113 integrates the output of the subtractor 112.

[0034] The calculation unit 126 generates a calculation result of the feedback gain af2 based on the output of the undersampling unit 124. At this time, the calculation unit 126 can attenuate high-frequency components including quantization noise from the output of the undersampling unit 124 and multiply the signal with the high-frequency signal components compensated for by the feedback gain af2. The subtractor 114 subtracts the output of the calculation unit 126 from the output of the integrator 113. The integrator 115 integrates the output of the subtractor 114.

[0035] Increasing the feedback gain af1 makes the correction more effective, but it also increases the cutoff frequency of the low-pass filter (the 0 dB frequency in an open loop), reducing the stability of the feedback. In this case, by calculating and integrating the feedback gains af1 and af2 in two stages in the feedback loop, it is theoretically possible to increase the low-frequency gain without increasing the cutoff frequency.

[0036] The high-frequency attenuation unit 131 attenuates high-frequency components, including quantization noise, output from the ΔΣ modulator 101. At this time, the high-frequency attenuation unit 131 can achieve digital feedback to low-frequency signal components while suppressing operational instability caused by delays in digital feedback via the ΔΣ ADC 122. The high-frequency attenuation unit 131 includes an oversampling unit 132, a dummy filter 133, an undersampling unit 134, a high-pass filter 135, and a subtractor 136.

[0037] The oversampling unit 132 oversamples the digital output Do of the ΔΣ modulator 101. At this time, the oversampling unit 132 can increase the frequency of the digital output Do by N times and output it to the dummy filter 133. This makes it possible to align the frequency of the input to the dummy filter 133 with the frequency of the input to the decimation filter 123.

[0038] The dummy filter 133 reduces the rate of the output of the oversampling unit 132 based on the dummy operation of the decimation filter 123. The dummy filter 133 can predict the delay of the decimation filter 123 and simulate the operation of the decimation filter 123. The dummy filter 133 may be a CIC filter.

[0039] The undersampling unit 134 undersamples the dummy output of the dummy filter 133. At this time, the undersampling unit 134 can reduce the frequency of the dummy output of the dummy filter 133 to 1 / N. This makes it possible to align the frequencies of the inputs to the subtractor 136.

[0040] High-pass filter 135 passes the high-frequency components of the output of undersampling unit 134 and outputs the result to subtractor 136. Subtractor 136 subtracts the output of high-pass filter 135 from the output of undersampling unit 124 and outputs the result to adder 146.

[0041] The high-frequency compensation unit 141 extracts high-frequency signal components from the digital input DIN of the ΔΣ modulator 101 and compensates for the high-frequency signal components attenuated by the high-frequency attenuation unit 131. This makes it possible to compensate for the loss of high-frequency signal components in the high-frequency attenuation unit 131 and stabilize the digital feedback. The digital input DIN on which the digital feedback signal is superimposed may be the output of the integrator 115. The high-frequency compensation unit 141 includes a delay circuit 142, a high-pass filter 145, and an adder 146.

[0042] Delay circuit 142 delays digital input DIN, which is the output of integrator 115 with a digital feedback signal superimposed thereon. High-pass filter 145 passes high-frequency components of the output of delay circuit 142. Adder 146 adds the output of high-pass filter 145 to the output of subtractor 136 and outputs the result to calculation units 125 and 126.

[0043] FIG. 2 shows signal waveforms at various parts of the amplifier circuit according to the first embodiment, FIG. 3 shows enlarged views of signal waveforms at various parts of the amplifier circuit according to the first embodiment, and FIG. 4 shows further enlarged views of signal waveforms at various parts of the amplifier circuit according to the first embodiment. In the figures, the vertical axis represents signal level and the horizontal axis represents time. Also, FIGS. 2 to 4 show simulated waveforms. Furthermore, FIG. 4 shows a simulated waveform where the signal level is near 0.

[0044] In the figure, "a" indicates the input waveform of the ΔΣ modulator 101. "b" indicates the output waveform of the ΔΣ modulator 101. "c" indicates the output waveform of the PWM unit 116. "d" indicates the output waveform of the ΔΣ ADC 122. "e" indicates the output waveform of the decimation filter 123. "f" indicates the output waveform of the subtractor 136.

[0045] In the figure, the feedback processing of the amplifier circuit AM1 is performed in the digital domain based on AD conversion processing of the drive signal SD that has been oversampled by the ΔΣ ADC 122.

[0046] In this way, in the first embodiment described above, digital feedback is applied based on the ADC output ADO obtained by ΔΣ AD converting the drive signal SD, and high-frequency components including quantization noise are attenuated in the digital feedback loop, while the high-frequency signal components lost during this process are compensated for. This makes it possible to reduce quantization noise in a class-D amplifier while suppressing operational instability caused by delays in digital feedback, and also to reduce distortion of the drive signal SD based on digital feedback.

[0047] 2. Second Embodiment In the first embodiment described above, digital feedback is applied based on the ADC output ADO obtained by ΔΣ AD converting the drive signal SD, and high-frequency components including quantization noise are attenuated in the digital feedback loop, while high-frequency signal components lost during this process are compensated for. In this second embodiment, digital feedback is applied based on the ADC output ADO obtained by ΔΣ AD converting the drive signal SD, without attenuating high-frequency components including quantization noise or compensating for high-frequency signal components in the digital feedback loop.

[0048] FIG. 5 is a block diagram showing an example of the configuration of an amplifier circuit according to the second embodiment.

[0049] In the figure, this amplifier circuit AM2 includes a digital feedback section 221 instead of the digital feedback section 121 of the first embodiment described above. The digital feedback section 221 is obtained by removing the high-frequency attenuation section 131 and the high-frequency compensation section 141 from the digital feedback section 121 of the first embodiment described above. Other configurations of the amplifier circuit AM2 of the second embodiment are similar to the configuration of the amplifier circuit AM1 of the first embodiment described above.

[0050] At this time, the undersampling unit 124 undersamples the filter output FO of the decimation filter 123 and outputs the undersampled output to the calculation units 125 and 126 .

[0051] In this way, in the second embodiment described above, digital feedback is applied based on the ADC output ADO obtained by ΔΣ AD converting the drive signal SD, without attenuating high-frequency components including quantization noise and compensating for high-frequency signal components in the digital feedback loop. This makes it possible to reduce distortion of the drive signal SD based on digital feedback while suppressing an increase in the circuit size of the class-D amplifier.

[0052] 3. Third Embodiment In the second embodiment described above, the feedback gains af1 and af2 are calculated and integrated in two stages on the feedback loop, and input to the ΔΣ modulator 101. In this third embodiment, the feedback gain af1 for one stage is calculated and integrated on the feedback loop, and input to the ΔΣ modulator 101.

[0053] FIG. 6 is a block diagram showing an example of the configuration of an amplifier circuit according to the third embodiment.

[0054] In the figure, the amplifier circuit AM3 is obtained by removing the arithmetic unit 126, the subtractor 114, and the integrator 115 from the amplifier circuit AM2 of the second embodiment described above. The remaining configuration of the amplifier circuit AM3 of the third embodiment is the same as the configuration of the amplifier circuit AM2 of the second embodiment described above.

[0055] At this time, the undersampling unit 124 undersamples the filter output FO of the decimation filter 123 and outputs the undersampled output to the calculation unit 125. Furthermore, the integrator 113 integrates the output of the subtractor 112 and inputs the integrated output to the ΔΣ modulator 101.

[0056] In this way, in the third embodiment described above, the feedback gain af1 for one stage is calculated and integrated on the feedback loop, and input to the ΔΣ modulator 101. This makes it possible to reduce distortion of the drive signal SD based on digital feedback while suppressing an increase in the circuit size of the class D amplifier.

[0057] 4. Fourth Embodiment In the first embodiment described above, digital feedback is applied based on the ADC output ADO obtained by ΔΣ AD converting the drive signal SD, and high-frequency components including quantization noise are attenuated in the digital feedback loop, while high-frequency signal components lost during this process are compensated for. In this fourth embodiment, an amplifier circuit that applies digital feedback based on the ADC output ADO obtained by ΔΣ AD converting the drive signal SD is applied to a wireless earphone.

[0058] FIG. 7 is a diagram illustrating an example of an electronic device to which the amplifier circuit according to the fourth embodiment is applied.

[0059] In the figure, the electronic device includes a smartphone 401 and wireless earphones 402 and 403. The wireless earphones 402 and 403 can achieve true wireless stereo (TWS) based on wireless communication with the smartphone 401 using Bluetooth Low Energy (BLE).

[0060] The smartphone 401 transmits audio data to be played back by the wireless earphones 402 and 403 to the wireless earphones 402 and 403. The type of audio data to be played back by the wireless earphones 402 and 403, the volume, playback start and playback stop can be specified on the smartphone 401.

[0061] The wireless earphones 402 and 403 play back the acoustic data transmitted from the smartphone 401. The wireless earphones 402 and 403 may be equipped with any of the amplifier circuits AM1 to AM3 of the first to third embodiments described above. In this case, the wireless earphones 402 and 403 can perform class D amplification on the acoustic data transmitted from the smartphone 401 and drive the speaker SP.

[0062] In this way, in the fourth embodiment described above, an amplifier circuit that applies digital feedback based on the ADC output ADO that has been subjected to ΔΣ AD conversion of the drive signal SD is applied to the wireless earphones 402 and 403. This makes it possible to improve the efficiency of driving the wireless earphones 402 and 403 while suppressing degradation in the sound quality of the wireless earphones 402 and 403.

[0063] In the above-described fourth embodiment, an example has been shown in which an amplifier circuit that applies digital feedback based on an ADC output ADO obtained by ΔΣ AD converting a drive signal SD is applied to the wireless earphones 402 and 403. In addition to this, an amplifier circuit that applies digital feedback based on an ADC output ADO obtained by ΔΣ AD converting a drive signal SD may be applied to headphones, a personal computer, a voice guidance device, or the like, or may be applied to a power amplifier used to drive a speaker attached to an audio device, or the like.

[0064] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0065] The present technology may also be configured as follows: (1) An amplifier circuit comprising: a ΔΣ modulator that converts a digital input into a low-bit signal and outputs it; a PWM unit that generates a PWM (Pulse Width Modulation) signal based on the digital output of the ΔΣ modulator; a driver that generates an analog drive signal based on the PWM signal; and a digital feedback unit that applies digital feedback based on a result of ΔΣ AD (Analog to Digital) conversion of the drive signal. (2) The digital feedback unit comprises: a ΔΣ ADC (Analog to Digital Converter) that oversamples the drive signal and performs AD conversion; a decimation filter that reduces the rate of an ADC output of the ΔΣ ADC; and a first undersampling unit that undersamples a filter output of the decimation filter, and applies digital feedback based on an output of the first undersampling unit. (3) The amplifier circuit according to (2), wherein the decimation filter thins out the ADC output in synchronization with the PWM. (4) The amplifier circuit according to (2) or (3), wherein the digital feedback unit comprises: a calculation unit that calculates a feedback gain on the output of the first undersampling unit, a subtractor that subtracts the output of the calculation unit from the digital input, and an integrator that integrates the output of the subtractor and inputs the result to the ΔΣ modulator. (5) The amplifier circuit according to (2) or (3), wherein the digital feedback unit comprises: a first calculation unit that generates a calculation result of a first feedback gain based on the output of the first undersampling unit, a first subtractor that subtracts the output of the first calculation unit from the digital input, a first integrator that integrates the output of the first subtractor, a second calculation unit that generates a calculation result of a second feedback gain based on the output of the first undersampling unit, a second subtractor that subtracts the output of the second calculation unit from the output of the first integrator, and a second integrator that integrates the output of the second subtractor and inputs the result to the ΔΣ modulator.(6) The amplifier circuit according to any one of (1) to (5), wherein the digital feedback unit further comprises an attenuation unit that attenuates high-frequency components including quantization noise output from the ΔΣ modulator. (7) The amplifier circuit according to (6), wherein the attenuation unit comprises: an oversampling unit that oversamples the digital output of the ΔΣ modulator; a dummy filter that lowers the rate of the output of the oversampling unit based on a dummy operation of the decimation filter; a second undersampling unit that undersamples the dummy output of the dummy filter; a first high-pass filter that passes high-frequency components of the output of the second undersampling unit; and a third subtractor that subtracts the output of the first high-pass filter from the output of the first undersampling unit. (8) The amplifier circuit according to (7), wherein the decimation filter and the dummy filter are CIC (Cascaded Integrator Comb) filters. (9) The amplifier circuit according to any one of (6) to (8), wherein the digital feedback unit further comprises a compensation unit that extracts high-frequency signal components from the digital input input to the ΔΣ modulator and compensates for the high-frequency signal components attenuated by the attenuation unit. (10) The amplifier circuit according to (9), wherein the compensation unit comprises: a delay unit that delays the digital input input to the ΔΣ modulator, a second high-pass filter that passes high-frequency components of the output of the delay unit, and an adder unit that adds the output of the second high-pass filter to the output of the third subtractor. (11) An electronic device comprising: a load; and an amplifier circuit that drives the load, wherein the amplifier circuit comprises: a ΔΣ modulator that converts the digital input into a low-bit signal and outputs it; a PWM unit that generates a PWM (Pulse Width Modulation) signal based on the digital output of the ΔΣ modulator; a driver that generates an analog drive signal based on the PWM signal; and a digital feedback unit that applies digital feedback based on a result of ΔΣ AD (Analog to Digital) conversion of the drive signal. (12) The electronic device according to (11), wherein the load is a speaker.

[0066] AM1 Amplifier circuit SP Speaker 101 ΔΣ modulator 102, 146 Adder 103 Quantizer 104, 112, 114, 136 Subtractor 105 Loop filter 111, 125, 126 Arithmetic unit 113, 115 Integrator 116 PWM unit 117 Driver 121 Digital feedback unit 122 ΔΣ ADC 123 Decimation filter 124, 134 Undersampling unit 131 High frequency attenuation unit 133 Dummy filter 132 Oversampling unit 135, 145 High pass filter 141 High frequency compensation unit 142 Delay circuit

Claims

1. An amplifier circuit comprising: a ΔΣ modulator that converts a digital input into a low-bit signal and outputs it; a PWM unit that generates a PWM (Pulse Width Modulation) signal based on the digital output of the ΔΣ modulator; a driver that generates an analog drive signal based on the PWM signal; and a digital feedback unit that applies digital feedback based on the ΔΣAD (Analog to Digital) conversion result of the drive signal.

2. The amplifier circuit of claim 1, wherein the digital feedback section comprises a ΔΣ ADC (Analog to Digital Converter) that oversamples and AD converts the drive signal, a decimation filter that reduces the rate of the ADC output of the ΔΣ ADC, and a first undersampling section that undersamples the filter output of the decimation filter, and applies digital feedback based on the output of the first undersampling section.

3. The amplifier circuit according to claim 2, wherein the decimation filter thins out the ADC output in synchronization with the PWM.

4. The amplifier circuit according to claim 2, wherein the digital feedback section comprises: a calculation section that calculates a feedback gain on the output of the first undersampling section; a subtractor that subtracts the output of the calculation section from the digital input; and an integrator that integrates the output of the subtractor and inputs it to the ΔΣ modulator.

5. The amplifier circuit of claim 2, wherein the digital feedback section comprises: a first calculation section that generates a calculation result of a first feedback gain based on the output of the first undersampling section; a first subtractor that subtracts the output of the first calculation section from the digital input; a first integrator that integrates the output of the first subtractor; a second calculation section that generates a calculation result of a second feedback gain based on the output of the first undersampling section; a second subtractor that subtracts the output of the second calculation section from the output of the first integrator; and a second integrator that integrates the output of the second subtractor and inputs it to the ΔΣ modulator.

6. The amplifier circuit according to claim 2, wherein the digital feedback section further comprises an attenuation section that attenuates high frequency components including quantization noise output from the ΔΣ modulator.

7. The amplifier circuit of claim 6, wherein the attenuation unit comprises: an oversampling unit that oversamples the digital output of the ΔΣ modulator; a dummy filter that reduces the rate of the output of the oversampling unit based on the dummy operation of the decimation filter; a second undersampling unit that undersamples the dummy output of the dummy filter; a first high-pass filter that passes high-frequency components of the output of the second undersampling unit; and a third subtractor that subtracts the output of the first high-pass filter from the output of the first undersampling unit.

8. The amplifier circuit according to claim 7, wherein the decimation filter and the dummy filter are CIC (Cascaded Integrator Comb) filters.

9. The amplifier circuit according to claim 7, wherein the digital feedback section further comprises a compensation section that extracts high-frequency signal components from the digital input input to the ΔΣ modulator and compensates for the high-frequency signal components attenuated by the attenuation section.

10. The amplifier circuit according to claim 9, wherein the compensation unit comprises: a delay unit that delays the digital input input to the ΔΣ modulator; a second high-pass filter that passes high-frequency components of the output of the delay unit; and an adder unit that adds the output of the second high-pass filter to the output of the third subtractor.

11. An electronic device comprising: a load; and an amplifier circuit for driving the load, wherein the amplifier circuit comprises: a ΔΣ modulator for converting a digital input into a low-bit signal and outputting it; a PWM unit for generating a PWM (Pulse Width Modulation) signal based on the digital output of the ΔΣ modulator; a driver for generating an analog drive signal based on the PWM signal; and a digital feedback unit for applying digital feedback based on the result of ΔΣAD (Analog to Digital) conversion of the drive signal.

12. The electronic device according to claim 11, wherein the load is a speaker.

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