Semiconductor device

Abstract

A semiconductor device (10) comprises: a semiconductor layer (20) including a first surface (20S); an IGBT region (21); a diode region (22); anode regions (25A) provided in the diode region (22); an insulating layer (30) provided on the first surface (20S) so as to cover the IGBT region (21) while exposing the diode region (22); a first electrode layer (40) including a first electrode section (41) provided on the insulating layer (30) correspondingly with respect to the IGBT region (21), and a second electrode section (42) that and is provided correspondingly with respect to the diode region (22) on the first surface (20S) and set apart from the first surface (20S); and an electroconductive protective layer (90) that is provided between the second electrode section (42) and the first surface (20S) and electrically connects the second electrode section (42) and the anode regions (25A). The protective layer (90) is constituted by electroconductive polysilicon.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Patent Document 1 discloses a semiconductor device including a reverse conducting-insulating gate bipolar transistor (RC-IGBT).

[0003] JP 2018-120990 A

[0004] [Summary] There is a demand for improved electrical characteristics of semiconductor devices.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer including a first surface, an IGBT region provided on the first surface, a diode region provided on the first surface, an anode region provided in the diode region of the first surface, an insulating layer provided on the first surface to cover the IGBT region while exposing the diode region, a first electrode layer including a first electrode portion provided on the insulating layer corresponding to the IGBT region, and a second electrode portion provided on the first surface corresponding to the diode region and spaced apart from the first surface, and a conductive protective layer provided between the second electrode portion and the first surface and electrically connecting the second electrode portion and the anode region, the protective layer being made of conductive polysilicon.

[0006] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to a first embodiment. FIG. 2 is a schematic plan view showing the arrangement of an IGBT region and a diode region in the semiconductor device shown in FIG. 1. FIG. 3 is a schematic plan view enlarging a region F3 in FIG. 1. FIG. 4 is a schematic plan view showing a trench structure and a contact structure in a region F4 in FIG. 2. FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. 3. FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process of an exemplary semiconductor device according to a first embodiment. FIG. 7 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to the process shown in FIG. 6. FIG. 8 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to the process shown in FIG. 7. FIG. 9 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to the process shown in FIG. 8. FIG. 10 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to the process shown in FIG. 9. FIG. 11 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to the process shown in FIG. 10. FIG. 12 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to the process shown in FIG. 11. FIG. 13 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to the process shown in FIG. 12. FIG. 14 is a schematic cross-sectional view illustrating a manufacturing process of the semiconductor device subsequent to the process shown in FIG. 13. FIG. 15 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device subsequent to that shown in FIG. 14 . FIG. 16 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device subsequent to that shown in FIG. 15 . FIG. 17 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device subsequent to that shown in FIG. 16 . FIG. 18 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device subsequent to that shown in FIG. 17 . FIG. 19 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device subsequent to that shown in FIG. 18 . FIG. 20 is a schematic cross-sectional view of a portion of a semiconductor device of a comparative example. FIG. 21 is a schematic cross-sectional view of a portion of a semiconductor device of the first embodiment. FIG. 22 is a graph showing impurity concentrations in the anode regions of a semiconductor device of a comparative example and a semiconductor device of the first embodiment. FIG. 23 is a graph showing current-voltage characteristics of a semiconductor device of a comparative example and a semiconductor device of the first embodiment. FIG. 24 is a schematic plan view of an exemplary semiconductor device according to a second embodiment. FIG. 25 is a schematic cross-sectional view of the semiconductor device taken along line F25-F25 in FIG. 24 . FIG. 26 is a schematic cross-sectional view of an enlarged portion of the semiconductor device of FIG. 25 . FIG. 27 is a schematic cross-sectional view of a semiconductor device of a modified example. FIG. 28 is a schematic cross-sectional view of a semiconductor device of a modified example. FIG. 29 is a schematic cross-sectional view of a semiconductor device according to a modified example.

[0007] DETAILED DESCRIPTION Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The terms "first," "second," "third," etc. used in this disclosure are merely used to label and are not necessarily intended to assign any order to their objects. The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" if the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length) of A are equal to the dimensions (width, length) of B" or "the dimensions (width, length) of A and the dimensions (width, length) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length) of A and the dimensions (width, length) of B is, for example, within 10% of the dimensions (width, length) of A.

[0011] First Embodiment Overall Planar Structure of Semiconductor Device The planar structure of a semiconductor device 10 according to a first embodiment will be described with reference to Figures 1 and 2. Figure 1 schematically illustrates the planar structure of an exemplary semiconductor device 10 according to the first embodiment. Figure 2 schematically illustrates the layout of an IGBT (Insulated Gate Bipolar Transistor) region 21 and a diode region 22, which will be described later, in the semiconductor device 10 shown in Figure 1. In Figure 2, the diode region 22 is dotted to facilitate understanding of the drawing.

[0012] 1, the semiconductor device 10 has a flat plate shape with the Z direction as its thickness direction. The semiconductor device 10 has a rectangular shape when viewed from the Z direction. Here, the term "plan view" used in this specification refers to viewing the semiconductor device 10 from the Z direction, unless explicitly stated otherwise. Furthermore, two mutually orthogonal directions orthogonal to the Z direction are referred to as the "X direction" and the "Y direction."

[0013] The semiconductor device 10 includes an IGBT region 21 in which an IGBT 21A (see FIG. 5) is provided, and a diode region 22 in which a diode 22A (see FIG. 5) is provided. The diode 22A may be a freewheeling diode (FWD) connected in anti-parallel to the IGBT 21A. Both the IGBT 21A and the diode 22A are provided on the same chip. In this way, the semiconductor device 10 constitutes an RC (reverse conducting)-IGBT chip.

[0014] The semiconductor device 10 includes a semiconductor layer 20. The semiconductor layer 20 may include a semiconductor substrate and an epitaxial layer. Therefore, the semiconductor layer 20 may be referred to as, for example, a "chip" or a "semiconductor chip." The semiconductor layer 20 may be made of a material containing Si. Therefore, a Si substrate may be used as the semiconductor substrate in the semiconductor layer 20. In this case, the epitaxial layer may be a Si epitaxial layer epitaxially grown from the Si substrate. The semiconductor layer 20 includes a first surface 20S and a second surface 20R (see FIG. 5 ) opposite to the first surface 20S.

[0015] The semiconductor device 10 includes an insulating layer 30 and a first electrode layer 40 provided on the first surface 20S. The first electrode layer 40 can be arranged so as to overlap at least both the IGBT region 21 and the diode region 22 in a plan view.

[0016] The insulating layer 30 is made of silicon oxide (SiO ２ ), silicon nitride (SiN), silicon oxynitride (SiON), and aluminum oxide (Al ２ O ３ The insulating layer 30 may be composed of a single insulating layer, or may have a laminated structure of a plurality of different insulating layers.

[0017] The first electrode layer 40 may include at least one of aluminum (Al), copper (Cu), an aluminum alloy, a copper alloy, tungsten (W), molybdenum (Mo), nickel (Ni), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The first electrode layer 40 may be composed of a single metal layer or may have a stacked structure of multiple different metal layers. In the first embodiment, the first electrode layer 40 is composed of a single metal layer. In the first embodiment, the first electrode layer 40 is composed of aluminum silicon copper (AlSiCu) as an aluminum alloy. In one example, the first electrode layer 40 may have a thickness of 3 μm or more and 6 μm or less. The thickness of the first electrode layer 40 can be changed as desired.

[0018] The first electrode layer 40 includes a first pad electrode 40P and a gate pad electrode 40G. The first pad electrode 40P and the gate pad electrode 40G are arranged spaced apart from each other in a plan view.

[0019] The first pad electrode 40P is arranged to overlap both the IGBT region 21 and the diode region 22 in a plan view. In the example shown in Fig. 1 , the first pad electrode 40P is provided to overlap the entire IGBT region 21 and the entire diode region 22. The first pad electrode 40P is provided on most of the first surface 20S of the semiconductor layer 20.

[0020] The gate pad electrode 40G is arranged in a region different from both the IGBT region 21 and the diode region 22 in a plan view. The gate pad electrode 40G is arranged at a position spaced apart from the first pad electrode 40P in the X direction.

[0021] The semiconductor device 10 may further include a gate wiring 50 electrically connected to the gate pad electrode 40G. The gate wiring 50 is disposed above the semiconductor layer 20 and below the first pad electrode 40P. The gate wiring 50 may be insulated from both the semiconductor layer 20 and the first pad electrode 40P by the insulating layer 30. Therefore, it can be said that the gate wiring 50 is embedded in the insulating layer 30. In one example, the gate wiring 50 may be made of conductive polysilicon. In another example, the gate wiring 50 may be made of another metal material.

[0022] The gate wiring 50 may include a plurality of gate fingers 51. In the example of FIG. 1 , the gate wiring 50 includes five gate fingers 51. Each gate finger 51 may extend in the X direction. The number of gate fingers 51 may be set appropriately depending on the desired characteristics of the semiconductor device 10.

[0023] As shown in FIG. 2 , the semiconductor device 10 may include a plurality of IGBT regions 21 and a plurality of diode regions 22. The plurality of IGBT regions 21 and the plurality of diode regions 22 may be arranged in an array without overlapping each other in a plan view. The plurality of IGBT regions 21 may be arranged spaced apart from each other in the X direction and the Y direction. The plurality of diode regions 22 may be arranged spaced apart from each other in the X direction and the Y direction. In the example shown in FIG. 2 , both the IGBT regions 21 and the diode regions 22 are rectangular in a plan view. Here, in the present disclosure, the X direction corresponds to the "first direction."

[0024] Each IGBT region 21 may be arranged adjacent to some of the multiple diode regions 22. In one example, some of the multiple IGBT regions 21 may be arranged alternately with some of the multiple diode regions 22 in the X direction. In the example of FIG. 2, four IGBT regions 21 and three diode regions 22 are arranged alternately in the X direction. A subregion 20A including such alternately arranged IGBT regions 21 and diode regions 22 may be arranged adjacent to the gate finger 51 shown in FIG. 1. The semiconductor device 10 may include multiple subregions 20A arranged spaced apart from each other. In the example shown in FIG. 2, the multiple subregions 20A are arranged spaced apart from each other in the Y direction. The multiple subregions 20A and the multiple gate fingers 51 may be arranged alternately in the Y direction. The number of IGBT regions 21 and diode regions 22 included in a subregion 20A and the number of subregions 20A are appropriately set depending on the desired characteristics of the semiconductor device 10.

[0025] 2 , the area of ​​the IGBT region 21 in a plan view is larger than the area of ​​the diode region 22 in a plan view. The areas of the IGBT region 21 in a plan view and the diode region 22 in a plan view are set appropriately depending on the desired characteristics of the semiconductor device 10.

[0026] 1 and 2 for the sake of simplicity, a boundary region 23 can be provided between the adjacent IGBT region 21 and diode region 22. The boundary region 23 will be described later with reference to FIGS.

[0027] [Detailed Structure of a Portion of the Semiconductor Device] The detailed planar structure and cross-sectional structure of a portion of the semiconductor device 10 will be described with reference to FIGS. 3 to 5. FIG. 3 schematically illustrates an enlarged planar structure of region F3 in FIG. 1. FIG. 4 schematically illustrates an enlarged planar structure of region F4 in FIG. 2. Regions F3 and F4 are located at the same position in a plan view. FIG. 5 schematically illustrates a cross-sectional structure of the semiconductor device 10 taken along line F5-F5 in FIG. 4. FIG. 3 also schematically illustrates the first electrode layer 40, the electrode structure, and a protective layer 90, which will be described later. The protective layer 90 is indicated by dots.

[0028] As shown in FIG. 4 , the semiconductor device 10 may include a plurality of trench structures 70 provided in the semiconductor layer 20. In the example shown in FIG. 4 , each trench structure 70 extends in the Y direction in a plan view. The plurality of trench structures 70 are arranged spaced apart from one another in the X direction across the IGBT region 21, the boundary region 23, and the diode region 22. In the example shown in FIG. 4 , the pitch PT of the plurality of trench structures 70 in the X direction is constant. Note that the pitch PT of the plurality of trench structures 70 can be changed as desired. In one example, the pitch PT of the plurality of trench structures 70 may be different in the IGBT region 21, the boundary region 23, and the diode region 22.

[0029] As shown in FIG. 5 , the semiconductor device 10 includes a first region 20P containing n-type impurities and a second region 20Q containing p-type impurities. Therefore, the first region 20P is an n-type region, and the second region 20Q is a p-type region. The second region 20Q is provided on the first region 20P. The first region 20P includes a semiconductor substrate and a portion of the epitaxial layer of the semiconductor layer 20. The second region 20Q includes the epitaxial layer of the semiconductor layer 20. In this disclosure, n-type is also referred to as the first conductivity type, and p-type is also referred to as the second conductivity type. The n-type impurities may be, for example, phosphorus (P) or arsenic (As). The p-type impurities may be, for example, boron (B) or aluminum (Al).

[0030] 5, in the IGBT region 21, the semiconductor layer 20 may further include an n-type emitter region 24 adjacent to the second region 20Q. The emitter region 24 includes a part of the first surface 20S of the semiconductor layer 20. That is, in the IGBT region 21, the emitter region 24 is provided in a surface layer portion closer to the first surface 20S of the semiconductor layer 20. In one example, the n-type impurity concentration of the emitter region 24 is 1×10 １９ cm －３ 1x10 or more ２０ cm －３ It can be as follows:

[0031] In the IGBT region 21, the second region 20Q may include a base region 25B. The base region 25B is adjacent to both the emitter region 24 and the first region 20P. That is, the base region 25B is sandwiched between the emitter region 24 and the first region 20P in the Z direction. In one example, the p-type impurity concentration of the base region 25B is 1×10 １５ cm －３ 1x10 or more １８ cm －３ It can be as follows:

[0032] In the IGBT region 21, the semiconductor layer 20 may further include a p-type collector region 26C adjacent to the first region 20P. The collector region 26C includes a part of the second surface 20R of the semiconductor layer 20. That is, in the IGBT region 21, the collector region 26C is provided in a surface layer portion closer to the second surface 20R of the semiconductor layer 20. In one example, the p-type impurity concentration of the collector region 26C is 1×10 １５ cm －３ 1x10 or more １８ cm －３ It can be as follows:

[0033] In the IGBT region 21, the first region 20P may include a buffer region 27 adjacent to the collector region 26C, a drift region 28 provided on the buffer region 27, and a carrier storage region 29 adjacent to the drift region 28. The carrier storage region 29 is sandwiched between the base region 25B and the drift region 28 in the Z direction. In one example, the n-type impurity concentration of the buffer region 27 is 1×10１５ cm －３ 1x10 or more １７ cm －３ In one example, the n-type impurity concentration of the drift region 28 can be 1×10 １３ cm －３ 1x10 or more １５ cm －３ The drift region 28 has a lower n-type impurity concentration than the buffer region 27. The carrier storage region 29 has a higher n-type impurity concentration than the drift region 28. In one example, the n-type impurity concentration of the carrier storage region 29 is 1×10 １５ cm －３ 1x10 or more １７ cm －３ Preferably, the carrier storage region 29 has a lower n-type impurity concentration than the emitter region 24.

[0034] The provision of the carrier storage region 29 suppresses the discharge of carriers (holes) into the base region 25B, thereby promoting the accumulation of carriers (holes) in the region immediately below the trench structure 70 in the IGBT region 21. Therefore, the carrier storage region 29 can reduce the on-resistance and on-voltage of the IGBT 21A.

[0035] In the IGBT region 21, the multiple trench structures 70 may include multiple gate trench structures 70G and multiple emitter trench structures 70E. In one example, the gate trench structures 70G and the emitter trench structures 70E may be arranged alternately in the X direction in the IGBT region 21. Note that the number and arrangement of the gate trench structures 70G and the emitter trench structures 70E may be changed as appropriate depending on the desired characteristics of the IGBT 21A.

[0036] Each gate trench structure 70G includes a gate trench 71G, a gate insulating layer 72G, and a gate electrode 73G. The gate trench 71G has an opening in the first surface 20S of the semiconductor layer 20 and extends to penetrate the base region 25B. Therefore, the gate trench 71G also penetrates the emitter region 24. The gate trench 71G penetrates the carrier storage region 29 and reaches the drift region 28.

[0037] The multiple gate trenches 71G may be arranged at intervals of 1 μm to 10 μm in the X direction. Each gate trench 71G may have a width (dimension in the X direction) of 0.5 μm to 3 μm inclusive. Each gate trench 71G may have a depth (dimension in the Z direction) of 1 μm to 10 μm inclusive.

[0038] The gate trench 71G includes sidewalls and a bottom wall. The sidewalls extend from the first surface 20S of the semiconductor layer 20 toward the bottom wall. The bottom wall forms the end of the gate trench 71G on the second surface 20R side of the semiconductor layer 20. In the example shown in FIG. 5 , the sidewalls extend along the Z direction. The bottom wall has a curved shape that convexly extends toward the second surface 20R of the semiconductor layer 20.

[0039] The sidewalls may have a tapered shape in which the opening width (dimension in the X direction) narrows from the first surface 20S of the semiconductor layer 20 toward the bottom wall. The bottom wall may be a flat surface perpendicular to the Z direction. In this case, the corners between the bottom wall and the sidewalls may be curved and convex outward.

[0040] The gate insulating layer 72G is provided in the gate trench 71G. The gate insulating layer 72G may be formed by, for example, thermal oxidation. In this case, the boundary portion of the semiconductor layer 20 with the outer surface of the gate insulating layer 72G may form the sidewall and bottom wall of the gate trench 71G. The gate insulating layer 72G may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The gate insulating layer 72G is integrated with the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20. Therefore, it can be said that the insulating layer 30 includes the gate insulating layer 72G.

[0041] The gate insulating layer 72G is provided in a layered form on the sidewalls and bottom wall of the gate trench 71G. As a result, a recess space is formed in the gate trench 71G by the gate insulating layer 72G. A gate electrode 73G is buried in this recess space. Therefore, it can be said that the gate electrode 73G is buried in the gate insulating layer 72G within the gate trench 71G.

[0042] The gate electrode 73G is configured to receive a gate potential. That is, the gate electrode 73G may be electrically connected to the gate pad electrode 40G (see FIG. 1). In one example, although not shown, the gate electrode 73G is connected to a gate contact at one end of the gate trench 71G in the Y direction. The gate contact is connected to the gate finger 51 (see FIG. 1). As a result, the gate electrode 73G is electrically connected to the gate pad electrode 40G via the gate contact and the gate finger 51. The upper end surface of the gate electrode 73G may be located closer to the bottom wall of the gate trench 71G than the first surface 20S of the semiconductor layer 20. The gate electrode 73G is made of, for example, conductive polysilicon.

[0043] Each emitter trench structure 70E includes an emitter trench 71E, an emitter insulating layer 72E, and a field plate electrode 73E. Like the gate trench 71G, the emitter trench 71E penetrates the emitter region 24, the base region 25B, and the carrier storage region 29 and reaches the drift region 28.

[0044] The multiple emitter trenches 71E may be arranged at intervals of 1 μm or more and 10 μm or less in the X direction. Each emitter trench 71E may have a width (dimension in the X direction) of 0.5 μm or more and 3 μm or less. Each emitter trench 71E may have a depth (dimension in the Z direction) of 1 μm or more and 10 μm or less. The shape of the emitter trench 71E shown in FIG. 5 may be the same as the shape of the gate trench 71G. In the first embodiment, the size and pitch of the emitter trench 71E may be the same as those of the gate trench 71G. In another example, the size and pitch of the emitter trench 71E may be different from those of the gate trench 71G.

[0045] The emitter insulating layer 72E is provided in the emitter trench 71E. When the emitter insulating layer 72E is formed by, for example, thermal oxidation, the boundary portion of the semiconductor layer 20 with the outer surface of the emitter insulating layer 72E may form the sidewalls and bottom wall of the emitter trench 71E. The emitter insulating layer 72E may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In other words, the emitter insulating layer 72E may be made of the same material as the gate insulating layer 72G. The emitter insulating layer 72E is integrated with the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20. Therefore, it can be said that the insulating layer 30 includes the emitter insulating layer 72E.

[0046] The emitter insulating layer 72E is provided in a layered form on the sidewalls and bottom wall of the emitter trench 71E. This forms a recess space within the emitter trench 71E due to the emitter insulating layer 72E. A field plate electrode 73E is embedded in this recess space. Therefore, it can be said that the field plate electrode 73E is embedded in the emitter insulating layer 72E within the emitter trench 71E.

[0047] The field plate electrode 73E is configured to be applied with an emitter potential. That is, the field plate electrode 73E may be electrically connected to the first pad electrode 40P (see FIG. 1). In one example, although not shown, the field plate electrode 73E is connected to an emitter contact at one end of the emitter trench 71E in the Y direction. The emitter contact is connected to the first pad electrode 40P. As a result, the field plate electrode 73E is electrically connected to the first pad electrode 40P via the emitter contact. The upper end surface of the field plate electrode 73E may be located closer to the bottom wall of the emitter trench 71E than the first surface 20S of the semiconductor layer 20. The field plate electrode 73E is made of, for example, conductive polysilicon. In this way, the field plate electrode 73E may be made of the same material as the gate electrode 73G. In one example, the width WE of the field plate electrode 73E (see FIG. 3) may be equal to the width WG of the gate electrode 73G (see FIG. 3).

[0048] The semiconductor device 10 includes a plurality of contact structures 80 that electrically connect the first pad electrode 40P and the second region 20Q in the IGBT region 21. The contact structures 80 are arranged on both sides of the gate trench structure 70G in the X direction and spaced apart from the gate trench structure 70G in the X direction.

[0049] The contact structure 80 includes a contact hole 81, an emitter contact 82, and a p-type base contact region 83. The contact hole 81 has an opening in the first surface 20S of the semiconductor layer 20 and extends in the Z direction toward the second surface 20R. The contact hole 81 also penetrates the insulating layer 30 in the Z direction. The contact hole 81 includes a sidewall and a bottom wall. The sidewall extends from the upper surface 30S of the insulating layer 30 toward the bottom wall. The sidewall includes a first sidewall formed by the insulating layer 30 and a second sidewall formed by the semiconductor layer 20. In the example shown in FIG. 5 , the sidewall has a tapered shape in which the opening width (dimension in the X direction) narrows from the upper surface 30S of the insulating layer 30 toward the bottom wall. The bottom wall has a curved shape that convexly curves toward the base region 25B.

[0050] The side walls may extend along the Z direction. The bottom wall may be a flat surface perpendicular to the Z direction. In this case, the corners between the bottom wall and the side walls may be curved and convex outward.

[0051] The emitter contact 82 is buried in the contact hole 81. The emitter contact 82 is in contact with the emitter region 24. The emitter contact 82 may have, for example, a stacked structure of a first conductive layer 82A and a second conductive layer 82B. The first conductive layer 82A may include at least one of titanium, titanium nitride, tantalum (Ta), and tantalum nitride (TaN). The second conductive layer 82B is provided on the first conductive layer 82A. The second conductive layer 82B may include at least one of tungsten (W), molybdenum, nickel, aluminum, copper, an aluminum alloy, and a copper alloy.

[0052] The base contact region 83 is provided in the base region 25B. The base contact region 83 is provided on the bottom wall of the contact hole 81. In other words, the base contact region 83 is exposed at the bottom wall of the contact hole 81. Therefore, the emitter contact 82 is in contact with the base contact region 83 at the bottom wall of the contact hole 81. The p-type impurity concentration of the base contact region 83 may be higher than the p-type impurity concentration of the base region 25B. In one example, the p-type impurity concentration of the base contact region 83 is 1×10 １９ cm －３ 1x10 or more ２０ cm －３ It can be as follows:

[0053] The semiconductor device 10 may further include a second electrode layer 60 provided on the second surface 20R of the semiconductor layer 20. The second electrode layer 60 is electrically connected to the collector region 26C in the IGBT region 21. The second electrode layer 60 forms ohmic contact with the collector region 26C. The second electrode layer 60 may include at least one of titanium (Ti), nickel (Ni), palladium (Pd), gold (Au), silver (Ag), and aluminum (Al). In this manner, the structure between the first pad electrode 40P and the second electrode layer 60 in the IGBT region 21 allows the IGBT 21A to be configured in the IGBT region 21. Therefore, it can be said that the first pad electrode 40P configures the emitter of the IGBT 21A, and the second electrode layer 60 configures the collector of the IGBT 21A.

[0054] (Diode Region) In the diode region 22, the second region 20Q may include a p-type anode region 25A instead of the base region 25B of the IGBT region 21. Furthermore, the diode region 22 does not include the emitter region 24. Therefore, the anode region 25A includes a part of the first surface 20S of the semiconductor layer 20. That is, in the diode region 22, the anode region 25A is provided in a surface layer portion closer to the first surface 20S of the semiconductor layer 20. Furthermore, the anode region 25A is adjacent to the first region 20P. In one example, the p-type impurity concentration of the anode region 25A is 1×10 １５ cm －３ 1x10 or more １８ cm －３ In one example, the p-type impurity concentration of the anode region 25A may be equal to the p-type impurity concentration of the base region 25B. In another example, the p-type impurity concentration of the anode region 25A may be different from the p-type impurity concentration of the base region 25B.

[0055] In the diode region 22, the semiconductor layer 20 may further include a p-type cathode region 26K adjacent to the first region 20P, instead of the collector region 26C of the IGBT region 21. The cathode region 26K includes a part of the second surface 20R of the semiconductor layer 20. That is, in the diode region 22, the cathode region 26K is provided in a surface layer portion closer to the second surface 20R of the semiconductor layer 20. The cathode region 26K is adjacent to the collector region 26C in a direction perpendicular to the Z direction. In one example, the n-type impurity concentration of the cathode region 26K is 1×10 １９ cm －３ 1x10 or more ２０ cm －３ That is, the n-type impurity concentration of the cathode region 26K may be higher than the p-type impurity concentration of the collector region 26C.

[0056] In the diode region 22, the first region 20P may include a buffer region 27 and a drift region 28, similar to the IGBT region 21. On the other hand, in the diode region 22, the first region 20P does not include a carrier storage region 29. In the diode region 22, the buffer region 27 is adjacent to the cathode region 26K.

[0057] In the diode region 22, the plurality of trench structures 70 may include a plurality of diode trench structures 70D. Note that the number of diode trench structures 70D can be changed as appropriate depending on the desired characteristics of the diode 22A.

[0058] Each diode trench structure 70D includes a diode trench 71D, a diode insulating layer 72D, and a diode electrode 73D. The diode trench 71D has an opening in the first surface 20S of the semiconductor layer 20 and extends through the anode region 25A. The diode trench 71D reaches the drift region 28.

[0059] The multiple diode trenches 71D may be arranged at intervals of 1 μm or more and 10 μm or less in the X direction. Each diode trench 71D may have a width (dimension in the X direction) of 0.5 μm or more and 3 μm or less. Each diode trench 71D may have a depth (dimension in the Z direction) of 1 μm or more and 10 μm or less. The shape of the diode trench 71D shown in FIG. 5 may be the same as the shape of the gate trench 71G. In the first embodiment, the size of the diode trench 71D may be the same as the size of the gate trench 71G. The pitch of the diode trench 71D is 1 / 2 the pitch of the gate trench 71G. The size of the diode trench 71D may be different from that of the gate trench 71G. The pitch of the diode trench 71D may be different from 1 / 2 the pitch of the gate trench 71G.

[0060] The diode insulating layer 72D is provided in the diode trench 71D. When the diode insulating layer 72D is formed by, for example, thermal oxidation, the boundary portion of the semiconductor layer 20 with the outer surface of the diode insulating layer 72D may form the sidewall and bottom wall of the diode trench 71D. The diode insulating layer 72D may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In other words, the diode insulating layer 72D may be made of the same material as the gate insulating layer 72G.

[0061] The diode insulating layer 72D is provided in a layered form on the sidewalls and bottom wall of the diode trench 71D. As a result, a recess space is formed in the diode trench 71D by the diode insulating layer 72D. A diode electrode 73D is embedded in this recess space. Therefore, it can be said that the diode electrode 73D is embedded in the diode insulating layer 72D within the diode trench 71D.

[0062] The diode electrode 73D is configured to be applied with a potential different from the gate potential, for example, an anode potential. In the first embodiment, the anode potential is the same as the emitter potential. That is, the diode electrode 73D may be electrically connected to the first pad electrode 40P (see FIG. 1). The upper end surface of the diode electrode 73D may be located closer to the bottom wall of the diode trench 71D than the first surface 20S of the semiconductor layer 20. The diode electrode 73D may be made of, for example, conductive polysilicon. In this manner, the diode electrode 73D may be made of the same material as the gate electrode 73G. In one example, the width WD of the diode electrode 73D (see FIG. 3) may be equal to the width WG of the gate electrode 73G (see FIG. 3). In one example, the width WD of the diode electrode 73D may be equal to the width WE of the field plate electrode 73E (see FIG. 3).

[0063] The second electrode layer 60 is electrically connected to the cathode region 26K in the diode region 22. The second electrode layer 60 forms ohmic contact with the cathode region 26K. In this manner, a diode 22A can be configured in the diode region 22 by the structure between the first pad electrode 40P and the second electrode layer 60 in the diode region 22. For this reason, it can be said that the first pad electrode 40P configures the anode of the diode 22A, and the second electrode layer 60 configures the cathode of the diode 22A. In this manner, the first pad electrode 40P electrically connects the emitter of the IGBT 21A to the anode of the diode 22A. The second electrode layer 60 electrically connects the collector of the IGBT 21A to the cathode of the diode 22A.

[0064] (Boundary Region) In the boundary region 23, the second region 20Q may include a p-type boundary well region 25W. On the other hand, the emitter region 24 is not provided in the boundary region 23. Therefore, the boundary well region 25W includes a part of the first surface 20S of the semiconductor layer 20. That is, in the boundary region 23, the boundary well region 25W is provided in a surface layer portion closer to the first surface 20S of the semiconductor layer 20. Furthermore, the boundary well region 25W is adjacent to the first region 20P. In one example, the p-type impurity concentration of the boundary well region 25W is 1×10１５ cm －３ 1x10 or more １８ cm －３ The following may be true: In one example, the p-type impurity concentration of the boundary well region 25W may be equal to the p-type impurity concentration of the base region 25B. In another example, the p-type impurity concentration of the boundary well region 25W may be different from the p-type impurity concentration of the base region 25B. In one example, the p-type impurity concentration of the boundary well region 25W may be equal to the p-type impurity concentration of the anode region 25A. In another example, the p-type impurity concentration of the boundary well region 25W may be different from the p-type impurity concentration of the anode region 25A.

[0065] Both the p-type cathode region 26K and the n-type collector region 26C adjacent to the first region 20P are arranged in the boundary region 23. That is, the boundary between the cathode region 26K and the collector region 26C is located in the boundary region 23.

[0066] In the boundary region 23, the first region 20P may include a buffer region 27 and a drift region 28, similar to the IGBT region 21. On the other hand, in the boundary region 23, the first region 20P does not include a carrier storage region 29. In the boundary region 23, the buffer region 27 is adjacent to both the cathode region 26K and the collector region 26C.

[0067] In the boundary region 23, the plurality of trench structures 70 may include a boundary trench structure 70B. The boundary trench structure 70B includes a boundary trench 71B, a boundary insulating layer 72B, and a boundary electrode 73B.

[0068] The boundary trench 71B has an opening in the first surface 20S of the semiconductor layer 20 and extends to penetrate the boundary well region 25W. The boundary trench 71B reaches the drift region 28.

[0069] The boundary trench 71B may have a width (dimension in the X direction) of 0.5 μm or more and 3 μm or less. The boundary trench 71B may have a depth (dimension in the Z direction) of 1 μm or more and 10 μm or less. The shape of the boundary trench 71B shown in FIG. 5 may be the same as the shape of the gate trench 71G. In the first embodiment, the size of the boundary trench 71B may be the same as the gate trench 71G. The size of the boundary trench 71B may be different from that of the gate trench 71G.

[0070] The boundary insulating layer 72B is provided in the boundary trench 71B. When the boundary insulating layer 72B is formed by, for example, thermal oxidation, the boundary portion of the semiconductor layer 20 with the outer surface of the boundary insulating layer 72B may form the sidewall and bottom wall of the boundary trench 71B. The boundary insulating layer 72B may contain at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. In other words, the boundary insulating layer 72B may be made of the same material as the gate insulating layer 72G. The boundary insulating layer 72B is integrated with the insulating layer 30 provided on the first surface 20S of the semiconductor layer 20. Therefore, it can be said that the insulating layer 30 includes the boundary insulating layer 72B.

[0071] The boundary insulating layer 72B is provided in a layered form on the sidewalls and bottom wall of the boundary trench 71B. As a result, a recess space is formed in the boundary trench 71B by the boundary insulating layer 72B. A boundary electrode 73B is buried in this recess space. Therefore, it can be said that the boundary electrode 73B is buried in the boundary insulating layer 72B within the boundary trench 71B.

[0072] The boundary electrode 73B is configured to be applied with an emitter potential. That is, the boundary electrode 73B may be electrically connected to the first pad electrode 40P (see FIG. 1). In one example, although not shown, the boundary electrode 73B is connected to a boundary contact at one end of the boundary trench 71B in the Y direction. The boundary contact is connected to the first pad electrode 40P. As a result, the boundary electrode 73B is electrically connected to the first pad electrode 40P via the boundary contact. The upper end surface of the boundary electrode 73B may be located closer to the bottom wall of the boundary trench 71B than the first surface 20S of the semiconductor layer 20. The boundary electrode 73B may be made of, for example, conductive polysilicon. In this way, the boundary electrode 73B may be made of the same material as the gate electrode 73G. In one example, the width WB of the boundary electrode 73B (see FIG. 3) may be equal to the width WG of the gate electrode 73G (see FIG. 3). In one example, the width WB of the boundary electrode 73B may be equal to the width WE of the field plate electrode 73E (see FIG. 3 ). In one example, the width WB of the boundary electrode 73B may be equal to the width WD of the diode electrode 73D (see FIG. 3 ).

[0073] (Insulating Layer, Protective Layer, and First Electrode Layer) The insulating layer 30 provided on the first surface 20S of the semiconductor layer 20 includes a first insulating layer 31 in contact with the first surface 20S and a second insulating layer 32 stacked on the first insulating layer 31. In one example, the first insulating layer 31 and the second insulating layer 32 may be made of the same material. As another example, the first insulating layer 31 and the second insulating layer 32 may be made of different materials.

[0074] The first insulating layer 31 has a thickness thinner than the second insulating layer 32. The thickness of the first insulating layer 31 may be equal to the thickness of each of the gate insulating layer 72G, the emitter insulating layer 72E, the diode insulating layer 72D, and the boundary insulating layer 72B, for example. The first insulating layer 31 may be integrated with the gate insulating layer 72G and the emitter insulating layer 72E. The second insulating layer 32 covers the gate electrode 73G and the field plate electrode 73E.

[0075] The insulating layer 30 may include a diode opening 33. The diode opening 33 exposes the diode region 22. The diode opening 33 may also expose the boundary region 23. In other words, the insulating layer 30 is provided in the IGBT region 21. In one example, a side surface 33A of the insulating layer 30 constituting the diode opening 33 may be inclined toward the diode region 22 from the upper surface 30S of the insulating layer 30 toward the first surface 20S of the semiconductor layer 20. The diode opening 33 may expose the entire diode region 22 in the Y direction. The diode opening 33 may expose the entire diode region 22 in the X direction. The diode opening 33 may also expose the entire boundary region 23 in the Y direction. The side surface 33A of the insulating layer 30 may be located in the boundary region 23, for example. That is, a portion of the insulating layer 30 in the X direction may be provided in the boundary region 23. 5 , the side surface 33A of the insulating layer 30 is located at the end of the boundary region 23 closer to the IGBT region 21. More specifically, the side surface 33A of the insulating layer 30 is located closer to the IGBT region 21 than the center in the X direction of the boundary well region 25W adjacent to the IGBT region 21.

[0076] The first pad electrode 40P in the first electrode layer 40 may include a first electrode portion 41 provided corresponding to the IGBT region 21, a second electrode portion 42 provided corresponding to the diode region 22, and a third electrode portion 43 provided corresponding to the boundary region 23. The first electrode portion 41 is provided on the insulating layer 30. The first electrode portion 41 is in contact with the upper surface 30S of the insulating layer 30. The second electrode portion 42 is provided within the diode opening 33. The second electrode portion 42 is provided spaced apart from the first surface 20S of the semiconductor layer 20. The third electrode portion 43 is provided within the diode opening 33. The third electrode portion 43 is provided spaced apart from the first surface 20S of the semiconductor layer 20. The third electrode portion 43 includes an inclined portion that is inclined along a side surface 33A of the insulating layer 30 that constitutes the diode opening 33.

[0077] The semiconductor device 10 includes a conductive protective layer 90 provided in the diode region 22. The protective layer 90 is provided between the second electrode portion 42 of the first electrode layer 40 and the first surface 20S of the semiconductor layer 20. The protective layer 90 electrically connects the second electrode portion 42 and the anode region 25A. In one example, the protective layer 90 may be in contact with both the second electrode portion 42 and the anode region 25A. In one example, the protective layer 90 may be provided over the entire diode region 22 in a plan view. In one example, a plurality of protective layers 90 may be provided corresponding to the plurality of diode regions 22 (see FIG. 1 ).

[0078] The protective layer 90 is provided between the third electrode portion 43 of the first electrode layer 40 and the first surface 20S of the semiconductor layer 20. The protective layer 90 electrically connects the third electrode portion 43 and the boundary well region 25W. As described above, the protective layer 90 may be provided at least partially in the boundary region 23, extending from the diode region 22 across the boundary between the diode region 22 and the boundary region 23. That is, the protective layer 90 may be provided continuously across both the diode region 22 and the boundary region 23. In one example, the protective layer 90 may be in contact with both the third electrode portion 43 and the boundary well region 25W. In one example, the protective layer 90 may extend from the diode region 22 to a region closer to the IGBT region 21 than the boundary electrode 73B. In one example, the protective layer 90 may be provided across most of the boundary region 23 in the X direction. 5 , the protective layer 90 may be provided so as to contact the boundary well region 25W closer to the IGBT region 21 than the boundary trench structure 70B in the boundary region 23. In this way, the protective layer 90 is electrically connected to the boundary well region 25W closer to the IGBT region 21 than the boundary trench structure 70B. In one example, the protective layer 90 may be provided across the entire boundary region 23 in the Y direction.

[0079] The multiple protective layers 90 may be spaced apart from one another. The multiple protective layers 90 may be arranged spaced apart in the X direction in correspondence with the multiple diode regions 22 and boundary regions 23 in one subregion 20A (see FIG. 1 ).

[0080] The protective layer 90 may be provided along the first surface 20S of the semiconductor layer 20 and the diode trench structure 70D. That is, the protective layer 90 includes a portion that extends from the first surface 20S of the semiconductor layer 20 toward the second surface 20R at a position corresponding to the diode trench structure 70D. The protective layer 90 includes multiple recesses 91 corresponding to the diode trench structure 70D. The protective layer 90 extends into the diode trench 71D at a position corresponding to the diode trench structure 70D, thereby contacting the diode electrode 73D. Therefore, it can be said that the protective layer 90 is in contact with both the second electrode portion 42 and the diode electrode 73D. In one example, the protective layer 90 may be integrated with the diode electrode 73D. That is, the protective layer 90 and the diode electrode 73D may be provided integrally. Note that, in another example, the protective layer 90 and the diode electrode 73D may be provided separately. In this case, the protective layer 90 is connected to the diode electrode 73D.

[0081] The protective layer 90 may be provided along the first surface 20S of the semiconductor layer 20 and the boundary trench structure 70B. That is, the protective layer 90 includes a portion that extends from the first surface 20S of the semiconductor layer 20 toward the second surface 20R at a position corresponding to the boundary trench structure 70B. The protective layer 90 includes multiple recesses 92 corresponding to the boundary trench structure 70B. The protective layer 90 extends into the boundary trench 71B at a position corresponding to the boundary trench structure 70B, thereby contacting the boundary electrode 73B. Therefore, it can be said that the protective layer 90 is in contact with both the third electrode portion 43 and the boundary electrode 73B. In one example, the protective layer 90 may be integrated with the boundary electrode 73B. That is, the protective layer 90 and the boundary electrode 73B may be provided integrally. Note that in another example, the protective layer 90 and the boundary electrode 73B may be provided separately. In this case, the protective layer 90 is connected to the boundary electrode 73B.

[0082] The protective layer 90 is provided in the diode opening 33 of the insulating layer 30. The protective layer 90 includes a side surface 93 that contacts the insulating layer 30 that constitutes the diode opening 33. In other words, the protective layer 90 is provided over the entire diode opening 33 in a plan view.

[0083] The thickness TP of the protective layer 90 may be thinner than the thickness T2 of the second electrode portion 42. The thickness TP of the protective layer 90 may be thinner than the thickness T1 of the first electrode portion 41. The thickness TP of the protective layer 90 may be thinner than the thickness T3 of the third electrode portion 43. The thickness TP of the protective layer 90 may be 1 / 10 or less of the thickness T2 of the second electrode portion 42. The thickness TP of the protective layer 90 may be 1 / 10 or less of the thickness T1 of the first electrode portion 41. The thickness TP of the protective layer 90 may be 1 / 10 or less of the thickness T3 of the third electrode portion 43.

[0084] The thickness TP of the protective layer 90 may be thinner than the thickness T4 of the insulating layer 30. The thickness TP of the protective layer 90 may be thinner than the thickness of the second insulating layer 32. The thickness TP of the protective layer 90 may be equal to or greater than the thickness of the first insulating layer 31.

[0085] The thickness TP of the protective layer 90 may be thinner than the width WD of the diode electrode 73D (see FIG. 3). The thickness TP of the protective layer 90 may be thinner than the width WG of the gate electrode 73G (see FIG. 3). The thickness TP of the protective layer 90 may be thinner than the width WE of the field plate electrode 73E (see FIG. 3). The thickness TP of the protective layer 90 may be thinner than the width WB of the boundary electrode 73B (see FIG. 3). The thickness TP of the protective layer 90 may be equal to or less than half the width WD of the diode electrode 73D. The thickness TP of the protective layer 90 may be equal to or less than half the width WG of the gate electrode 73G. The thickness TP of the protective layer 90 may be equal to or less than half the width WE of the field plate electrode 73E. The thickness TP of the protective layer 90 may be equal to or less than half the width WB of the boundary electrode 73B.

[0086] Because the thickness TP of the protective layer 90 is thus small, the second electrode portion 42 extends into the diode trench 71D at the recess 91 of the protective layer 90 corresponding to the diode region 22. Furthermore, the third electrode portion 43 extends into the boundary trench 71B at the recess 92 of the protective layer 90 corresponding to the boundary region 23.

[0087] The protective layer 90 is made of conductive polysilicon. That is, the protective layer 90 may be made of the same material as the diode electrode 73D. The protective layer 90 may be made of the same material as the gate electrode 73G. The protective layer 90 may be made of the same material as the field plate electrode 73E. The protective layer 90 may be made of the same material as the boundary electrode 73B. The protective layer 90 is made of polysilicon doped with impurities. The impurity concentration of the protective layer 90 is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ It can be as follows:

[0088] [Method of Manufacturing Semiconductor Device] An example of a method of manufacturing the semiconductor device 10 will be described with reference to Figures 6 to 19. Figures 6 to 19 show cross-sectional structures at the same cross-sectional position as that shown in Figure 5. For ease of understanding, in Figures 6 to 19, components similar to those in Figure 5 are denoted by the same reference numerals.

[0089] 6, in the method for manufacturing the semiconductor device 10, a semiconductor wafer 800 is prepared as a base for the semiconductor layer 20. The semiconductor wafer 800 may be an n-type single crystal silicon substrate. In one example, the n-type impurity concentration of the semiconductor wafer 800 is 1×10 １３ cm －３ 1x10 or more １５ cm －３ The semiconductor wafer 800 can be described as follows. The semiconductor wafer 800 includes a first surface 801 and a second surface 802 opposite to the first surface 801. Here, the first surface 801 corresponds to the first surface 20S of the semiconductor layer 20. In the semiconductor wafer 800, a plurality of IGBT regions 21, a plurality of boundary regions 23, and a plurality of diode regions 22 are formed by the steps described below. In this way, it can be said that the method for manufacturing the semiconductor device 10 includes forming the semiconductor layer 20 including the first surface 20S in which the IGBT regions 21 and the diode regions 22 are provided.

[0090] As shown in FIG. 7 , the method for manufacturing the semiconductor device 10 includes forming a gate trench 71G, an emitter trench 71E, a diode trench 71D, and a boundary trench 71B. These trenches 71G, 71E, 71D, and 71B are formed on a first surface 801 of a semiconductor wafer 800. In this process, a mask (not shown) is first formed on the first surface 801 of the semiconductor wafer 800. The mask may be, for example, a hard mask or a resist mask. The mask exposes regions of the first surface 801 of the semiconductor wafer 800 where the gate trench 71G, emitter trench 71E, diode trench 71D, and boundary trench 71B are to be formed, while covering the remaining regions. Subsequently, the regions exposed by the mask are etched to form the gate trench 71G, emitter trench 71E, diode trench 71D, and boundary trench 71B. The gate trench 71G, emitter trench 71E, diode trench 71D, and boundary trench 71B each have an opening in a first surface 801 of the semiconductor wafer 800. The gate trench 71G and emitter trench 71E are formed in the IGBT region 21. The diode trench 71D is formed in the diode region 22. The boundary trench 71B is formed in the boundary region 23. After these trenches 71G, 71E, 71D, and 71B are formed, the mask is removed.

[0091] As shown in FIG. 8 , the manufacturing method for the semiconductor device 10 includes forming a first insulating layer 810. The first insulating layer 810 is an insulating layer that constitutes the first insulating layer 31. The first insulating layer 810 is formed on the first surface 801 of the semiconductor wafer 800 and on the gate trench 71G, the emitter trench 71E, the diode trench 71D, and the boundary trench 71B. Therefore, the first insulating layer 810 includes a gate insulating layer 72G, an emitter insulating layer 72E, a diode insulating layer 72D, and a boundary insulating layer 72B. In other words, the manufacturing method for the semiconductor device 10 can be said to include forming a gate insulating layer 72G in the gate trench 71G and forming an emitter insulating layer 72E in the emitter trench 71E. The manufacturing method for the semiconductor device 10 can be said to include forming a diode insulating layer 72D in the diode trench 71D. The manufacturing method for the semiconductor device 10 can be said to include forming a boundary insulating layer 72B in the boundary trench 71B. In this way, the gate insulating layer 72G, the emitter insulating layer 72E, the diode insulating layer 72D, and the boundary insulating layer 72B are formed in a common process, and therefore the thicknesses of the gate insulating layer 72G, the emitter insulating layer 72E, the diode insulating layer 72D, and the boundary insulating layer 72B are all equal to one another.

[0092] The first insulating layer 810 can be formed by, for example, a chemical vapor deposition (CVD) method, an oxidation treatment method (for example, a thermal oxidation method), etc. The first insulating layer 810 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0093] Next, the manufacturing method for the semiconductor device 10 includes removing the first insulating layer 810 formed on the first surface 801 of the semiconductor wafer 800 corresponding to the diode region 22. In this step, the first insulating layer 810 formed on the upper ends of the plurality of diode trenches 71D is also removed. As a result, the first surface 801 in the diode region 22 and the upper ends of each diode trench 71D are exposed.

[0094] In addition, the manufacturing method of the semiconductor device 10 includes removing the first insulating layer 810 formed on the first surface 801 of the semiconductor wafer 800 corresponding to the boundary region 23. In this step, the first insulating layer 810 formed on the upper ends of the plurality of boundary trenches 71B is also removed. As a result, the first surface 801 in the boundary region 23 and the upper ends of each boundary trench 71B are exposed.

[0095] 9 , the method for manufacturing the semiconductor device 10 includes forming a first metal layer 820. The first metal layer 820 is formed on the first insulating layer 810. The first metal layer 820 is formed on the first surface 801 of the semiconductor wafer 800 in the diode region 22 and the boundary region 23. The first metal layer 820 is formed in the gate trench 71G, the emitter trench 71E, the diode trench 71D, and the boundary trench 71B. More specifically, the first metal layer 820 is embedded in the gate insulating layer 72G in the gate trench 71G. The first metal layer 820 is embedded in the emitter insulating layer 72E in the emitter trench 71E. The first metal layer 820 is embedded in the diode insulating layer 72D in the diode trench 71D. The first metal layer 820 is embedded in the boundary insulating layer 72B in the boundary trench 71B. As described above, the first metal layer 820 includes the gate electrode 73G, the field plate electrode 73E, the diode electrode 73D, and the boundary electrode 73B. The first metal layer 820 is formed of, for example, conductive polysilicon. The impurity concentration of the first metal layer 820 is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The first metal layer 820 may be formed by a CVD method.

[0096] As shown in FIG. 10 , the manufacturing method for the semiconductor device 10 includes forming a conductive protective layer 90. In this process, the first metal layer 820 formed on the first surface 801 of the semiconductor wafer 800 in the IGBT region 21 is removed. In the IGBT region 21, the first metal layer 820 may be removed, for example, to a depth below the first surface 801. That is, in the IGBT region 21, the upper surface of the first metal layer 820 is located below the first surface 801. This results in the formation of a gate electrode 73G and a field plate electrode 73E. Additionally, the first metal layer 820 formed on the first surface 801 of the semiconductor wafer 800 in the boundary region 23 and the diode region 22 is thinned. The thinned first metal layer 820 constitutes the protective layer 90. Furthermore, the portion of the first metal layer 820 embedded in the diode trench 71D constitutes the diode electrode 73D. The portion of the first metal layer 820 embedded in the boundary trench 71B constitutes the boundary electrode 73B. That is, the protective layer 90 is formed integrally with the gate electrode 73G, the field plate electrode 73E, the diode electrode 73D, and the boundary electrode 73B. In order to clearly distinguish the protective layer 90 from the first metal layer 820 (see FIG. 9), the protective layer 90 is hatched differently from the first metal layer 820 (see FIG. 9) in FIG.

[0097] Here, the manufacturing method of the semiconductor device 10 may include adjusting the thickness of the first metal layer 820 formed in the boundary region 23 and the diode region 22. In this step, the thickness of the first metal layer 820 (the thickness of the protective layer 90) may be adjusted by, for example, etching.

[0098] As shown in FIG. 11 , the method for manufacturing the semiconductor device 10 includes forming an emitter region 24, a base region 25B, and a carrier storage region 29 in the IGBT region 21. The method for manufacturing the semiconductor device 10 also includes forming an anode region 25A in the diode region 22. The method for manufacturing the semiconductor device 10 also includes forming a boundary well region 25W in the boundary region 23. The order in which these impurity regions are formed is arbitrary. The emitter region 24, the base region 25B, and the carrier storage region 29 in the IGBT region 21 are formed by implanting n-type or p-type impurities through a mask (not shown) having a predetermined pattern. Meanwhile, the anode region 25A and the boundary well region 25W in the boundary region 23 and the diode region 22 are formed by implanting p-type impurities through a protective layer 90. That is, in this process, the protective layer 90 is used as a mask. In this process, the portion of the semiconductor wafer 800 into which the n-type or p-type impurities are not implanted may include the drift region 28. Both the anode region 25A and the boundary well region 25W include a portion of the first surface 801 of the semiconductor wafer 800. Therefore, the protective layer 90 contacts both the anode region 25A and the boundary well region 25W. As a result, the protective layer 90 is electrically connected to both the anode region 25A and the boundary well region 25W. Furthermore, the first metal layer 820 corresponding to the boundary region 23 and the diode region 22 serves as the protective layer 90, and therefore the protective layer 90 is connected to the diode electrode 73D. Furthermore, the protective layer 90 is connected to the boundary electrode 73B.

[0099] Thus, forming the anode region 25A is performed after forming the protective layer 90. In other words, forming the protective layer 90 is performed before forming the anode region 25A. Similarly, forming the border well region 25W is performed after forming the protective layer 90. In other words, forming the protective layer 90 is performed before forming the border well region 25W.

[0100] As shown in FIG. 12 , the manufacturing method of the semiconductor device 10 includes forming a second insulating layer 830. The second insulating layer 830 is an insulating layer that constitutes the second insulating layer 32. The second insulating layer 830 is formed to cover the upper surfaces of the gate electrode 73G and the field plate electrode 73E and the upper surface of the first insulating layer 810 in the IGBT region 21. Therefore, the second insulating layer 830 extends into the upper ends of the gate trench 71G and the emitter trench 71E. The second insulating layer 830 is also formed on the protective layer 90 in the boundary region 23 and the diode region 22. In one example, the second insulating layer 830 may be formed by a CVD method. The second insulating layer 830 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0101] As shown in FIGS. 13 to 15 , the method for manufacturing the semiconductor device 10 includes forming a contact structure 80. As shown in FIG. 13 , forming the contact structure 80 includes forming a plurality of contact holes 81. In this step, a mask 900 is formed on a second insulating layer 830. The mask 900 exposes regions of the second insulating layer 830 where the plurality of contact holes 81 are to be formed, while covering the remaining regions. The mask 900 may be, for example, a resist mask or a hard mask. Then, the second insulating layer 830 is etched using the mask 900, thereby selectively removing the second insulating layer 830, the first insulating layer 810, and the semiconductor wafer 800. As a result, the plurality of contact holes 81 are formed.

[0102] Each of the multiple contact holes 81 penetrates the second insulating layer 830 and the first insulating layer 810 to expose the semiconductor wafer 800 between the gate trench 71G and the emitter trench 71E. Each contact hole 81 is formed to reach the emitter region 24. Note that each contact hole 81 may penetrate the emitter region 24 to reach the base region 25B.

[0103] 13 , forming the contact structure 80 includes forming base contact regions 83 through each contact hole 81. In this step, ion implantation is performed to implant p-type impurities into the semiconductor wafer 800. The p-type impurities are implanted into the semiconductor wafer 800 using a mask 900. As a result, the p-type impurities are implanted into portions of the semiconductor wafer 800 exposed by the contact holes 81, thereby simultaneously forming multiple base contact regions 83. Each base contact region 83 is formed in the base region 25B. The base contact region 83 is connected to the contact hole 81. After each base contact region 83 is formed, the mask 900 is removed.

[0104] 14 and 15 , forming the contact structure 80 includes forming an emitter contact 82 in each contact hole 81. In this process, as shown in FIG. 14 , first, forming the contact structure 80 includes forming a second metal layer 840. The second metal layer 840 is formed on the second insulating layer 830 and along the sidewalls and bottom walls of the contact holes 81. The second metal layer 840 may be formed by at least one of a sputtering method or a CVD method. The second metal layer 840 may include at least one of titanium, titanium nitride, tantalum, and tantalum nitride.

[0105] Next, forming the contact structure 80 includes forming a third metal layer 850. The third metal layer 850 is formed on the second metal layer 840 and is filled in the contact hole 81. The third metal layer 850 may be formed by at least one of a sputtering method, a CVD method, and a plating method. The third metal layer 850 may also include at least one of tungsten, molybdenum, nickel, aluminum, copper, an aluminum alloy, and a copper alloy.

[0106] 15 , forming the contact structure 80 includes removing a portion of each of the second metal layer 840 and the third metal layer 850. In one example, both the second metal layer 840 and the third metal layer 850 may be removed by etching (e.g., dry etching, wet etching, etc.). The second metal layer 840 and the third metal layer 850 are removed until the second insulating layer 830 is exposed. Through the above steps, the contact structure 80 is formed.

[0107] 16 and 17 , the method for manufacturing the semiconductor device 10 includes forming the diode opening 33. The formation of the diode opening 33 may be performed after the formation of the protective layer 90.

[0108] 16 , a resist mask 910 is formed on the second insulating layer 830. The resist mask 910 is formed so as to cover the portion of the second insulating layer 830 corresponding to the IGBT region 21, while exposing the portions corresponding to the boundary region 23 and the diode region 22.

[0109] Next, as shown in FIG. 17 , the second insulating layer 830 and the first insulating layer 810 exposed from the resist mask 910 are removed by etching. The etching may be anisotropic etching. The anisotropic etching is dry etching (specifically, RIE (Reactive Ion Etching)). As a result, the diode opening 33 is formed. The protective layer 90 is exposed through the diode opening 33. In other words, in this process, the first surface 801 of the semiconductor wafer 800 is covered by the protective layer 90 in the diode region 22 and the boundary region 23 and is not exposed. The anode region 25A and the boundary well region 25W are also covered by the protective layer 90 and are not exposed. After the diode opening 33 is formed, the resist mask 910 is removed. Through the above processes, the insulating layer 30 is formed to cover the IGBT region 21 and expose the diode region 22.

[0110] As shown in FIG. 18 , the manufacturing method of the semiconductor device 10 includes forming a first electrode layer 40 over both the IGBT region 21 and the diode region 22. The first electrode layer 40 includes forming a fourth metal layer 860 on the insulating layer 30 and the protective layer 90. The fourth metal layer 860 is a metal layer that constitutes the first electrode layer 40. The fourth metal layer 860 is provided in portions corresponding to the IGBT region 21, the diode region 22, and the boundary region 23. Therefore, forming the first electrode layer 40 includes forming a first electrode portion 41 on the insulating layer 30 corresponding to the IGBT region 21 and forming a second electrode portion 42 on the protective layer 90 corresponding to the diode region 22. Furthermore, forming the first electrode layer 40 includes forming a third electrode portion 43 on the protective layer 90 corresponding to the boundary region 23. Both the second electrode portion 42 and the third electrode portion 43 are in contact with the protective layer 90. In this way, the protective layer 90 electrically connects the second electrode portion 42 and the anode region 25A. The protective layer 90 also electrically connects the third electrode portion 43 and the boundary well region 25W.

[0111] In the first embodiment, the fourth metal layer 860 is composed of a single metal layer. The fourth metal layer 860 may be composed of aluminum silicon copper (AlSiCu). The fourth metal layer 860 is then patterned using, for example, lithography and etching to form the first pad electrode 40P and the gate pad electrode 40G.

[0112] As shown in FIG. 19, the method for manufacturing the semiconductor device 10 includes thinning the semiconductor wafer 800, forming the buffer region 27, the collector region 26C, and the cathode region 26K, and forming the second electrode layer 60.

[0113] Thinning the semiconductor wafer 800 is performed by grinding or etching the second surface 802 of the semiconductor wafer 800. Next, the buffer region 27, the collector region 26C, and the cathode region 26K may be formed by implanting n-type or p-type impurities into the second surface 802 of the semiconductor wafer 800. The buffer region 27, the collector region 26C, and the cathode region 26K may be formed in any order. The cathode region 26K may be formed by implanting n-type impurities through a first mask (not shown) having a predetermined pattern. The buffer region 27 may be formed by implanting n-type impurities through a second mask (not shown) having a predetermined pattern. The anode region 25A may be formed by implanting p-type impurities through a third mask (not shown) having a predetermined pattern. Through the above steps, the semiconductor layer 20 is formed.

[0114] In forming the second electrode layer 60, the second electrode layer 60 is formed on the second surface 802 of the thinned semiconductor wafer 800. The second electrode layer 60 can be formed by at least one of a sputtering method and a CVD method. The semiconductor wafer 800 is then divided into individual pieces by dicing. Through the above steps, the semiconductor device 10 is manufactured.

[0115] [Operation of First Embodiment] The operation of the semiconductor device 10 of the first embodiment will be described with reference to FIGS. 20 to 23. FIG. 20 shows the concentration distribution of p-type impurities in the anode region 25A of the semiconductor device 10X of the comparative example. FIG. 21 shows the concentration distribution of p-type impurities in the anode region 25A of the semiconductor device 10 of the first embodiment. FIGS. 20 and 21 show simulation results when p-type impurities are implanted into the anode region 25A, with darker dots indicating higher p-type impurity concentrations. FIG. 22 shows the concentration profiles of p-type impurities in the anode region 25A of the semiconductor device 10X of the comparative example and the semiconductor device 10 of the first embodiment. The solid line in FIG. 22 shows the concentration profile of p-type impurities in the anode region 25A of the semiconductor device 10 of the first embodiment. The dashed line in FIG. 22 shows the concentration profile of p-type impurities in the anode region 25A of the semiconductor device 10X of the comparative example.

[0116] Fig. 23 shows the current-voltage characteristics of the diode 22A of the semiconductor device 10X of the comparative example and the semiconductor device 10 of the first embodiment. The solid line in Fig. 23 shows the current-voltage characteristics of the diode 22A of the semiconductor device 10 of the first embodiment. The dashed line in Fig. 23 shows the current-voltage characteristics of the diode 22A of the semiconductor device 10X of the comparative example.

[0117] Here, the semiconductor device 10X of the comparative example has a configuration in which the protective layer 90 is omitted from the semiconductor device 10 of the first embodiment. Therefore, in the semiconductor device 10X of the comparative example, the first pad electrode 40P is in contact with the first surface 20S of the semiconductor layer 20.

[0118] As shown in Figures 20 and 21, it can be seen that the anode region 25A of the semiconductor device 10 of the first embodiment has a region with a high p-type impurity concentration that extends close to the drift region 28, compared to the anode region 25A of the semiconductor device 10X of the comparative example.

[0119] As shown in FIG. 22, the anode region 25A of the semiconductor device 10 of the first embodiment has a higher p-type impurity concentration throughout the entire anode region 25A in the Z direction compared to the anode region 25A of the semiconductor device 10X of the comparative example.

[0120] From the results shown in Figures 20 to 22, since the anode region 25A of the semiconductor device 10 of the first embodiment has a higher p-type impurity concentration than the anode region 25A of the semiconductor device 10X of the comparative example, the forward current at the same forward voltage is larger in the diode 22A of the semiconductor device 10 of the first embodiment than in the diode 22A of the semiconductor device 10X of the comparative example.

[0121] Furthermore, in the semiconductor device 10X of the comparative example, when the diode opening 33 is formed in the insulating layer 30 by, for example, dry etching, the insulating layer 30 is removed so as to expose the first surface 801 of the semiconductor wafer 800, which may damage the semiconductor wafer 800. As a result, crystal defects may be formed in the semiconductor wafer 800, which may cause leakage current.

[0122] In this regard, in the semiconductor device 10 of the first embodiment, the first surface 801 of the semiconductor wafer 800 is covered with the protective layer 90 when the diode opening 33 is formed. This makes it possible to prevent damage to the semiconductor wafer 800 when the diode opening 33 is formed. This prevents crystal defects from being formed in the semiconductor layer made of the semiconductor wafer 800, thereby suppressing the generation of leakage current.

[0123] Effects of the First Embodiment According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes a semiconductor layer 20 including a first surface 20S, an IGBT region 21 provided in the first surface 20S, a diode region 22 provided in the first surface 20S, a base region 25B provided in the IGBT region 21 of the first surface 20S, an anode region 25A provided in the diode region 22 of the first surface 20S, an insulating layer 30 provided on the first surface 20S to cover the IGBT region 21 while exposing the diode region 22, a first electrode layer 40 including a first electrode portion 41 provided on the insulating layer 30 corresponding to the IGBT region 21, and a second electrode portion 42 provided on the first surface 20S corresponding to the diode region 22 and spaced apart from the first surface 20S, and a conductive protective layer 90 provided between the second electrode portion 42 and the first surface 20S and electrically connecting the second electrode portion 42 and the anode region 25A. The protective layer 90 is made of conductive polysilicon.

[0124] With this configuration, the protective layer 90 is omitted, and compared to the comparative example structure in which the second electrode portion 42 and the anode region 25A are in contact with each other, the impurity concentration of the anode region 25A has a concentration distribution in which the impurity concentration increases even in the region of the anode region 25A closer to the second surface 20R. This improves the current-voltage characteristics in the diode region 22 compared to the comparative example structure. Therefore, the electrical characteristics of the semiconductor device 10 can be improved.

[0125] (1-2) The protective layer 90 is provided over the entire diode region 22 in a plan view. With this configuration, compared to the comparative example in which the protective layer 90 is omitted and the second electrode portion 42 and the anode region 25A are in contact with each other, the overall impurity concentration of the anode region 25A becomes higher even in the region closer to the second surface 20R of the anode region 25A. This allows for further improvement in the electrical characteristics of the semiconductor device 10.

[0126] (1-3) The semiconductor device 10 includes a diode trench 71D having an opening in the first surface 20S in the diode region 22 and extending to penetrate the anode region 25A, a diode insulating layer 72D provided in the diode trench 71D, and a diode electrode 73D embedded in the diode insulating layer 72D within the diode trench 71D. The protective layer 90 is connected to the diode electrode 73D.

[0127] According to this configuration, the first electrode layer 40 and the diode electrode 73D are electrically connected via the protective layer 90, so that the potential of the first electrode layer 40 can be applied to the diode electrode 73D. This allows the semiconductor layer 20 to be depleted, thereby improving the breakdown voltage of the semiconductor device 10.

[0128] (1-4) The protective layer 90 is in contact with both the anode region 25A and the second electrode portion 42. This configuration eliminates the need for a dedicated contact structure for connecting the anode region 25A and the second electrode portion 42, thereby simplifying the configuration of the semiconductor device 10.

[0129] (1-5) The protective layer 90 is integrated with the diode electrode 73D. This configuration can suppress an increase in electrical resistance at the connection point between the protective layer 90 and the diode electrode 73D, compared to a configuration in which the protective layer 90 and the diode electrode 73D are provided separately and then connected to each other. In addition, the protective layer 90 and the diode electrode 73D can be formed in a common process. This can simplify the manufacturing method of the semiconductor device 10.

[0130] (1-6) The thickness TP of the protective layer 90 is thinner than the thickness T2 of the second electrode portion 42. With this configuration, an increase in electrical resistance in the current path from the anode region 25A to the second electrode portion 42 can be suppressed.

[0131] (1-7) The thickness TP of the protective layer 90 is equal to or less than 1 / 10 of the thickness T2 of the second electrode portion 42. With this configuration, an increase in electrical resistance in the current path from the anode region 25A to the second electrode portion 42 can be further suppressed.

[0132] (1-8) The thickness TP of the protective layer 90 is thinner than the thickness T4 of the insulating layer 30. With this configuration, an increase in electrical resistance in the current path from the anode region 25A to the second electrode portion 42 can be suppressed.

[0133] (1-9) The impurity concentration of the protective layer 90 is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ According to this configuration, the electrical resistance of the protective layer 90 can be reduced.

[0134] (1-10) The insulating layer 30 includes a diode opening 33 that exposes the diode region 22. The protective layer 90 includes a side surface 93 that contacts the insulating layer 30 that forms the diode opening 33.

[0135] According to this configuration, the protective layer 90 is provided to cover the entire diode region 22 exposed by the insulating layer 30. As a result, the overall impurity concentration of the anode region 25A becomes higher up to the region of the anode region 25A closer to the second surface 20R, thereby further improving the electrical characteristics of the semiconductor device 10.

[0136] (1-11) A plurality of IGBT regions 21 and a plurality of diode regions 22 are provided. The plurality of IGBT regions 21 and the plurality of diode regions 22 are arranged alternately one by one in the X direction. A plurality of protective layers 90 are provided corresponding to the plurality of diode regions 22. The plurality of protective layers 90 are provided spaced apart from one another.

[0137] According to this configuration, the protective layer 90 is provided corresponding to the plurality of diode regions 22, which can improve the current-voltage characteristics in each diode region 22. Therefore, the electrical characteristics of the semiconductor device 10 can be improved.

[0138] (1-12) The semiconductor device 10 includes a base region 25B provided in the IGBT region 21 of the first surface 20S, a gate trench 71G having an opening in the first surface 20S in the IGBT region 21 and extending through the base region 25B, a gate insulating layer 72G provided in the gate trench 71G, and a gate electrode 73G embedded in the gate insulating layer 72G within the gate trench 71G. The protective layer 90 and the gate electrode 73G are made of the same material. This configuration allows the protective layer 90 and the gate electrode 73G to be formed in a common process. This simplifies the manufacturing method of the semiconductor device 10.

[0139] (1-13) The semiconductor device 10 includes a boundary region 23 provided between the IGBT region 21 and the diode region 22, and a boundary well region 25W provided in the boundary region 23 of the first surface 20S. The insulating layer 30 exposes the boundary region 23. The first electrode layer 40 includes a third electrode portion 43 provided on the first surface 20S corresponding to the boundary region 23 and spaced apart from the first surface 20S. The protective layer 90 is provided between the first surface 20S of the semiconductor layer 20 and the third electrode portion 43 in the boundary region 23. The protective layer 90 electrically connects the third electrode portion 43 and the boundary well region 25W. The semiconductor device 10 further includes a boundary trench 71B having an opening in the first surface 20S in the boundary region 23 and extending to penetrate the boundary well region 25W, a boundary insulating layer 72B provided in the boundary trench 71B, and a boundary electrode 73B embedded in the boundary insulating layer 72B within the boundary trench 71B. Both the protective layer 90 and the boundary electrode 73B are made of the same material.

[0140] According to this configuration, an electron injection promotion structure is provided in the boundary region 23. This restricts the migration path of holes flowing into the base region 25B in the boundary region 23, thereby promoting the accumulation of holes in the region directly below the base region 25B. Furthermore, compared to the comparative example in which the protective layer 90 is omitted and the third electrode portion 43 and the boundary well region 25W are in contact with each other, the impurity concentration in the boundary well region 25W has a concentration distribution that increases even in the region closer to the second surface 20R of the boundary well region 25W. This enhances the effect of promoting the accumulation of holes in the region directly below the base region 25B. Additionally, since the protective layer 90 and the boundary electrode 73B can be formed in a common process, the manufacturing method of the semiconductor device 10 can be simplified.

[0141] (1-14) The protective layer 90 and the boundary electrode 73B are integrated. This configuration allows the protective layer 90 and the boundary electrode 73B to be formed in a common process, thereby simplifying the manufacturing method of the semiconductor device 10.

[0142] (1-15) The thickness TP of the protective layer 90 is smaller than the width WD of the diode electrode 73 D. This configuration can suppress an increase in electrical resistance in the current path from the anode region 25 A to the second electrode portion 42.

[0143] (1-16) The thickness TP of the protective layer 90 is smaller than the width WG of the gate electrode 73 G. With this configuration, an increase in electrical resistance in the current path from the anode region 25 A to the second electrode portion 42 can be suppressed.

[0144] (1-17) The thickness TP of the protective layer 90 is smaller than the width WB of the boundary electrode 73 B. With this configuration, an increase in electrical resistance in the current path from the anode region 25 A to the second electrode portion 42 can be suppressed.

[0145] (1-18) A method for manufacturing a semiconductor device 10 includes forming a semiconductor wafer 800 including a first surface 801 on which an IGBT region 21 and a diode region 22 are provided, forming an insulating layer 30 on the first surface 801 so as to cover the IGBT region 21 while exposing the diode region 22, forming a conductive protective layer 90 on the first surface 801 in the diode region 22, forming an anode region 25A in the diode region 22 of the first surface 801, and forming a first electrode layer 40 over both the IGBT region 21 and the diode region 22. Forming the first electrode layer 40 includes forming a first electrode portion 41 on the insulating layer 30 corresponding to the IGBT region 21, and forming a second electrode portion 42 on the protective layer 90 corresponding to the diode region 22. The protective layer 90 electrically connects the second electrode portion 42 and the anode region 25A and is made of conductive polysilicon.

[0146] With this configuration, the protective layer 90 is omitted, and compared to a comparative structure in which the second electrode portion 42 and the anode region 25A are in contact with each other, the impurity concentration of the anode region 25A becomes higher even in the region closer to the second surface 20R of the anode region 25A. This improves the current-voltage characteristics in the diode region 22 compared to the comparative structure. Therefore, the electrical characteristics of the semiconductor device 10 can be improved.

[0147] (1-19) The method for manufacturing the semiconductor device 10 includes forming a diode opening 33 in the insulating layer 30, exposing the diode region 22. Forming the diode opening 33 in the insulating layer 30 is performed after forming the protective layer 90.

[0148] According to this configuration, when the diode opening 33 is formed, the first surface 801 of the semiconductor wafer 800 is covered with the protective layer 90. This makes it possible to prevent damage to the semiconductor wafer 800 when the diode opening 33 is formed. This prevents crystal defects from being formed in the semiconductor layer made of the semiconductor wafer 800, thereby suppressing the occurrence of leakage current.

[0149] (1-20) The protective layer 90 is formed before the anode region 25A is formed. With this configuration, the protective layer 90 can be used as a mask for ion implantation when forming the anode region 25A. This eliminates the need to form a dedicated mask for ion implantation when forming the anode region 25A, thereby simplifying the manufacturing method for the semiconductor device 10.

[0150] (1-21) The protective layer 90 is formed integrally with the gate electrode 73G, the field plate electrode 73E, the diode electrode 73D, and the boundary electrode 73B. With this configuration, the process for forming the protective layer 90 can be simplified compared to when the protective layer 90 is formed in a separate process from the gate electrode 73G, the field plate electrode 73E, the diode electrode 73D, and the boundary electrode 73B.

[0151] Second Embodiment A semiconductor device 100 according to a second embodiment will be described with reference to Fig. 24 to Fig. 26. Fig. 24 schematically shows the planar structure of the semiconductor device 10 according to the second embodiment. Fig. 25 schematically shows the cross-sectional structure of the semiconductor device 10 taken along line F25-F25 in Fig. 24. Fig. 26 schematically shows the cross-sectional structure of an enlarged portion of Fig. 25.

[0152] 24 , in the second embodiment, a diode chip is configured as the semiconductor device 100. The semiconductor device 100 includes an active region 101 and a peripheral region 102 that surrounds the active region 101 in a plan view. The active region 101 is a region that configures the diode.

[0153] As shown in FIG. 25 , the semiconductor device 100 includes an n-type semiconductor layer 110. The semiconductor layer 110 includes a first surface 110S and a second surface 110R opposite to the first surface 110S. The semiconductor layer 110 is made of, for example, a material containing Si. A Si substrate or a SiC substrate may be used for the semiconductor layer 110. When a Si substrate is used for the semiconductor layer 110, the semiconductor layer 110 includes a Si substrate and a Si epitaxial layer epitaxially grown on the Si substrate. When a SiC substrate is used for the semiconductor layer 110, the semiconductor layer 110 includes a SiC substrate and a SiC epitaxial layer epitaxially grown on the SiC substrate. The Si substrate (SiC substrate) includes the second surface 110R, and the Si epitaxial layer (SiC epitaxial layer) includes the first surface 110S.

[0154] The semiconductor layer 110 includes a cathode region 111 , a drift region 112 provided on the cathode region 111 , and a buffer region 113 provided between the cathode region 111 and the drift region 112 .

[0155] Both the cathode region 111 and the buffer region 113 have a higher n-type impurity concentration than the drift region 112. The cathode region 111 has a higher n-type impurity concentration than the buffer region 113. The n-type impurity concentration of the cathode region 111 is, for example, 1×10 １８ cm －３ 5x10 or more ２０ cm －３ The n-type impurity concentration of the buffer region 113 can be set to, for example, 5×10 １５ cm －３ 1x10 or more １７ cm －３ The n-type impurity concentration of the drift region 112 can be set to, for example, 5×10 １２ cm －３ 5x10 or more １４ cm －３ The thickness of the buffer region 113 can be, for example, 0.3 μm or more and 600 μm or less, and the thickness of the drift region 112 can be, for example, 30 μm or more and 300 μm or less.

[0156] In the active region 101, the semiconductor layer 110 includes a p-type anode region 114. The anode region 114 may be an impurity diffusion layer selectively provided in the surface layer portion of the drift region 112. As a result, a pn junction is formed between the anode region 114 and the drift region 112 in the semiconductor layer 110. The p-type impurity concentration of the anode region 114 is, for example, 1×10 １５ cm －３ 1x10 or more ２０ cm －３ The thickness of the anode region 114 can be, for example, 1 μm or more and 3 μm or less. Here, the anode region 114 is an example of a "semiconductor region of the second conductivity type."

[0157] In the peripheral region 102, the semiconductor layer 110 includes a p-type well region 115, a p-type field limiting ring (FLR) region 116, and an n-type channel stop region 117. The well region 115, the FLR region 116, and the channel stop region 117 are each provided in a surface layer portion of the semiconductor layer 110. The well region 115, the FLR region 116, and the channel stop region 117 each include a portion of a first surface 110S of the semiconductor layer 110.

[0158] The well region 115 is annular in plan view, surrounding the anode region 114. The well region 115 is disposed so as to cover the entire peripheral portion 114A of the anode region 114 from below. The outer periphery of the well region 115 is located outward from the outer periphery of the anode region 114 in plan view. The well region 115 has a higher p-type impurity concentration than the anode region 114. The p-type impurity concentration of the well region 115 is, for example, 1×10 １５ cm －３ 1x10 or more ２０ cm －３ It can be as follows:

[0159] The FLR region 116 has an annular shape surrounding the well region 115 in a plan view. A plurality of FLR regions 116 are provided, spaced apart from each other in a direction perpendicular to the Z direction. The FLR region 116 has a higher p-type impurity concentration than the anode region 114. The FLR region 116 has, for example, the same p-type impurity concentration as the well region 115.

[0160] The channel stop region 117 is provided outward from the FLR region 116. The channel stop region 117 may be provided so as to extend from the peripheral region 102 to an end face 118 of the semiconductor layer 110. The channel stop region 117 has a higher n-type impurity concentration than the drift region 112. The n-type impurity concentration of the channel stop region 117 is, for example, 1×10 １７ cm －３ 1x10 or more ２２ cm －３ The thickness of the channel stop region 117 can be set to, for example, 2 μm or more and 3 μm or less.

[0161] The semiconductor device 100 includes an insulating layer 120 provided on the semiconductor layer 110. The insulating layer 120 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide. The thickness of the insulating layer 120 may be, for example, 0.5 μm or more and 5 μm or less.

[0162] The insulating layer 120 includes a first contact hole 121 and a second contact hole 122. The first contact hole 121 is provided so as to selectively expose the anode region 114. The first contact hole 121 may have a tapered shape such that the opening area decreases from its opening end toward the first surface 110S of the semiconductor layer 110. The first contact hole 121 is slightly smaller than the anode region 114 in a plan view. Therefore, the peripheral portion 114A of the anode region 114 is covered with the insulating layer 120. The insulating layer 120 is also provided so as to expose a portion of the channel stop region 117.

[0163] The second contact holes 122 are provided so as to selectively expose the FLR regions 116. A plurality of second contact holes 122 are provided in accordance with the number of FLR regions 116. Each second contact hole 122 may have a tapered shape such that the opening area decreases from the opening end toward the first surface 110S of the semiconductor layer 110.

[0164] The semiconductor device 100 includes a first electrode layer 130 provided on the semiconductor layer 110 and the insulating layer 120. The first electrode layer 130 includes an anode electrode 131, a field plate electrode 132, and an EQR (Equipotential Ring) electrode 133.

[0165] The anode electrode 131 is provided in the first contact hole 121 of the insulating layer 120. The anode electrode 131 is electrically connected to the anode region 114. The anode electrode 131 includes an overlapping portion 131A that extends from the first contact hole 121 onto the insulating layer 120. The overlapping portion 131A faces the peripheral portion 114A of the anode region 114 and the well region 115, with the insulating layer 120 sandwiched between them. The outer periphery of the overlapping portion 131A may be located between the outer periphery of the anode region 114 and the outer periphery of the well region 115.

[0166] The field plate electrodes 132 are provided individually for the multiple FLR regions 116. That is, a plurality of field plate electrodes 132 are provided corresponding to the number of FLR regions 116. The multiple field plate electrodes 132 are electrically connected to the corresponding multiple FLR regions 116. Of the multiple field plate electrodes 132, the field plate electrode 132 located at the outermost periphery includes an extraction portion 132A that is extracted outward on the insulating layer 120.

[0167] The EQR electrode 133 is provided on the insulating layer 120 and extends outward from the insulating layer 120. As a result, the EQR electrode 133 is electrically connected to the channel stop region 117 exposed from the insulating layer 120.

[0168] The semiconductor device 100 includes a surface protection layer 140 that covers the first electrode layer 130. The surface protection layer 140 is provided so as to cover the active region 101 and the peripheral region 102. The surface protection layer 140 includes an opening 141 that exposes a portion of the anode electrode 131 as a pad. The surface protection layer 140 is made of, for example, polyimide (PI).

[0169] The semiconductor device 100 includes a second electrode layer 150. The second electrode layer 150 is provided on a second surface 110R of the semiconductor layer 110. The second electrode layer 150 is electrically connected to the cathode region 111.

[0170] 26 , the semiconductor device 100 includes a conductive protective layer 160 electrically connected to the anode region 114. The protective layer 160 is made of conductive polysilicon. The protective layer 160 is in contact with the anode region 114. The protective layer 160 is provided over the entire anode region 114 in a plan view.

[0171] The anode electrode 131 serving as the first electrode layer 130 is provided on the protective layer 160. The anode electrode 131 is electrically connected to the anode region 114 via the protective layer 160. The anode electrode 131 may be in contact with the entire surface of the protective layer 160 in a plan view.

[0172] The thickness TP of the protective layer 160 may be thinner than the thickness TA of the anode electrode 131. The thickness TP of the protective layer 160 may be thinner than the thickness T4 (see FIG. 25 ) of the insulating layer 120. The thickness TP of the protective layer 160 may be thinner than the thickness T5 (see FIG. 25 ) of the surface protective layer 140. The thickness TP of the protective layer 160 may be 1 / 10 or less of the thickness TA of the anode electrode 131.

[0173] [Effects of Second Embodiment] The semiconductor device 10 of the second embodiment has the following effects. (2-1) The semiconductor device 100 includes an n-type semiconductor layer 110 including a first surface 110S, a p-type anode region 114 partially provided on the first surface 110S, an insulating layer 120 provided on the first surface 110S so as to expose the anode region 114, a conductive protective layer 160 provided on the first surface 110S and electrically connected to the anode region 114, and a first electrode layer 130 provided on the protective layer 160. The protective layer 160 is made of conductive polysilicon.

[0174] With this configuration, the protective layer 160 is omitted, and compared to a comparative structure in which the first electrode layer 130 and the anode region 114 are in contact with each other, the impurity concentration of the anode region 114 becomes higher even in the region closer to the second surface 110R of the anode region 114. This improves the current-voltage characteristics of the semiconductor device 100 compared to the comparative structure. Therefore, the electrical characteristics of the semiconductor device 100 can be improved.

[0175] (2-2) The thickness TP of the protective layer 160 is smaller than the thickness TA of the anode electrode 131. With this configuration, an increase in electrical resistance in the current path from the anode electrode 131 to the anode region 114 can be suppressed.

[0176] (2-3) The thickness TP of the protective layer 160 is equal to or less than 1 / 10 of the thickness TA of the anode electrode 131. With this configuration, an increase in electrical resistance in the current path from the anode electrode 131 to the anode region 114 can be further suppressed.

[0177] <Modifications> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other to the extent that no technical contradiction occurs.

[0178] (Modifications to the Configuration of the Semiconductor Device) In the first embodiment, the protective layer 90 may be provided in some of the plurality of diode regions 22. That is, the semiconductor device 10 may include diode regions 22 in which the protective layer 90 is provided and diode regions 22 in which the protective layer 90 is not provided. Similarly, the protective layer 90 may be provided in some of the plurality of boundary regions 23. That is, the semiconductor device 10 may include boundary regions 23 in which the protective layer 90 is provided and boundary regions 23 in which the protective layer 90 is not provided.

[0179] In the first embodiment, the protective layer 90 may be provided partially on the diode region 22. Similarly, the protective layer 90 may be provided partially on the boundary region 23.

[0180] In the first embodiment, another conductive layer may be interposed between the protective layer 90 and the second electrode portion 42 of the first electrode layer 40. That is, it is sufficient that the protective layer 90 and the second electrode portion 42 are electrically connected. Similarly, another conductive layer may be interposed between the protective layer 90 and the third electrode portion 43 of the first electrode layer 40. That is, it is sufficient that the protective layer 90 and the third electrode portion 43 are electrically connected.

[0181] In the first embodiment, another conductive layer may be interposed between the protective layer 90 and the anode region 25A. That is, it is sufficient that the protective layer 90 and the anode region 25A are electrically connected. Similarly, another conductive layer may be interposed between the protective layer 90 and the boundary well region 25W. That is, it is sufficient that the protective layer 90 and the boundary well region 25W are electrically connected.

[0182] In the first embodiment, another conductive layer may be interposed between the protective layer 90 and the diode electrode 73D. That is, it is sufficient that the protective layer 90 and the diode electrode 73D are electrically connected. Similarly, another conductive layer may be interposed between the protective layer 90 and the boundary electrode 73B. That is, it is sufficient that the protective layer 90 and the boundary electrode 73B are electrically connected.

[0183] In the first embodiment, the protective layer 90 and the diode electrode 73D may be provided separately. Similarly, the protective layer 90 and the boundary electrode 73B may be provided separately. In the first embodiment, the protective layer 90 and the diode electrode 73D may be made of different materials. Similarly, the protective layer 90 and the boundary electrode 73B may be made of different materials.

[0184] In the first embodiment, the relationship between the thickness TP of the protective layer 90 and the width WD of the diode electrode 73D can be changed as desired. For example, the thickness TP of the protective layer 90 may be equal to the width WD of the diode electrode 73D. For example, the thickness TP of the protective layer 90 may be greater than the width WD of the diode electrode 73D.

[0185] In the first embodiment, the relationship between the thickness TP of the protective layer 90 and the width WB of the boundary electrode 73B can be changed as desired. For example, the thickness TP of the protective layer 90 may be equal to the width WB of the boundary electrode 73B. For example, the thickness TP of the protective layer 90 may be greater than the width WB of the boundary electrode 73B.

[0186] In the first embodiment, the relationship between the thickness TP of the protective layer 90 and the width WG of the gate electrode 73G can be changed as desired. For example, the thickness TP of the protective layer 90 may be equal to the width WG of the gate electrode 73G. For example, the thickness TP of the protective layer 90 may be greater than the width WG of the gate electrode 73G.

[0187] In the first embodiment, the relationship between the thickness TP of the protective layer 90 and the thickness T2 of the second electrode portion 42 can be changed as desired. In one example, the thickness TP of the protective layer 90 may be thicker than 1 / 10 of the thickness T2 of the second electrode portion 42. In one example, the thickness TP of the protective layer 90 may be equal to the thickness T2 of the second electrode portion 42. In another example, the thickness TP of the protective layer 90 may be thicker than the thickness T2 of the second electrode portion 42.

[0188] In the first embodiment, the relationship between the thickness TP of the protective layer 90 and the thickness T4 of the insulating layer 30 can be changed as desired. In one example, the thickness TP of the protective layer 90 may be equal to the thickness T4 of the insulating layer 30. In another example, the thickness TP of the protective layer 90 may be greater than the thickness T4 of the insulating layer 30.

[0189] In each embodiment, the impurity concentration of the protective layer 90, 160 is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The present invention is not limited to the following and can be modified as desired. In the first embodiment, the side surface 93 of the protective layer 90 and the insulating layer 30 that constitutes the diode opening 33 may be spaced apart from each other. In this case, the second electrode portion 42 may be interposed between the side surface 93 of the protective layer 90 and the insulating layer 30 that constitutes the diode opening 33.

[0190] In the first embodiment, the formation range of the protective layer 90 in the X direction can be changed as desired. For example, the protective layer 90 may be provided over the entire boundary region 23 in the X direction. For another example, the protective layer 90 may be provided partially in the IGBT region 21 in the X direction as long as it is electrically insulated from the gate trench structure 70G. In this case, the protective layer 90 may be electrically connected to the field plate electrode 73E. For another example, the protective layer 90 may be provided closer to the diode region 22 than the boundary well region 25W, which is closer to the IGBT region 21 than the boundary trench structure 70B, in the boundary region 23. For another example, the protective layer 90 may be provided at a position closer to the diode region 22 than the boundary trench structure 70B in the X direction and spaced apart from the boundary trench structure 70B. For another example, the protective layer 90 does not need to be provided in the boundary region 23.

[0191] In the first embodiment, the width WG of the gate electrode 73G, the width WE of the field plate electrode 73E, the width WD of the diode electrode 73D, and the width WB of the boundary electrode 73B can be changed as desired. For example, at least one of the width WG of the gate electrode 73G, the width WE of the field plate electrode 73E, the width WD of the diode electrode 73D, and the width WB of the boundary electrode 73B may be different from the others.

[0192] In the first embodiment, a portion of the second insulating layer 32 may be provided on the protective layer 90. That is, the protective layer 90 may include a portion that is located closer to the IGBT region 21 in the X direction than the side surface 33A of the diode opening 33 of the insulating layer 30.

[0193] In the first embodiment, the emitter trench structure 70E may be changed to a gate trench structure 70G. In the first embodiment, the diode trench structure 70D may be omitted.

[0194] In the first embodiment, the boundary trench structure 70B may be omitted. In the first embodiment, the boundary well region 25W may be omitted. In the first embodiment, the boundary region 23 may be omitted, as shown in FIG. 27 . In this case, the IGBT region 21 and the diode region 22 are provided adjacent to each other. The protective layer 90 is provided, for example, up to a position in the diode region 22 adjacent to the IGBT region 21.

[0195] In the first embodiment, the area in which the protective layer 90 is provided can be changed as desired. In one example, as shown in FIG. 28 , the protective layer 90 may be provided in the diode region 22 but not in the boundary region 23. In this case, the diode opening 33 of the insulating layer 30 exposes the diode region 22. Meanwhile, the insulating layer 30 covers the boundary region 23. The first insulating layer 31 of the insulating layer 30 is also provided in the boundary region 23.

[0196] In the first embodiment, the configuration of the first electrode layer 40 can be changed as desired. For example, as shown in FIG. 29 , the first electrode layer 40 may have a stacked structure of a first conductive layer 44, a second conductive layer 45, and a third conductive layer 46. The first conductive layer 44 is a conductive layer in contact with the insulating layer 30 and the protective layer 90. The first conductive layer 44 may be made of, for example, aluminum silicon copper (AlSiCu). The second conductive layer 45 is provided on the first conductive layer 44. The second conductive layer 45 may be made of, for example, titanium nitride. The third conductive layer 46 is provided on the second conductive layer 45. The third conductive layer 46 may be made of, for example, aluminum. The second conductive layer 45 may be made of titanium. The thickness of the second conductive layer 45 is thinner than both the first conductive layer 44 and the third conductive layer 46. Here, the thickness TP of the protective layer 90 may be thicker than the thickness of the second conductive layer 45. The thickness TP of the protective layer 90 may be thinner than the thickness of the first conductive layer 44. The thickness TP of the protective layer 90 may be thinner than the thickness of the third conductive layer 46.

[0197] In the second embodiment, another conductive layer may be interposed between the protective layer 160 and the anode region 114. In other words, it is sufficient that the protective layer 160 is electrically connected to the anode region 114.

[0198] In the second embodiment, another conductive layer may be interposed between the protective layer 160 and the anode electrode 131. In other words, it is sufficient that the protective layer 160 is electrically connected to the anode electrode 131.

[0199] In the second embodiment, the configuration of the peripheral region 102 of the semiconductor device 100 can be changed as desired. For example, at least one of the field plate electrode 132 and the EQR electrode 133 may be omitted. For example, at least one of the well region 115, the FLR region 116, and the channel stop region 117 may be omitted.

[0200] (Modification of the semiconductor device manufacturing method) In the first embodiment, the protective layer 90 may be formed separately from the boundary electrode 73B. Furthermore, the protective layer 90 may be formed separately from the diode electrode 73D. Furthermore, the protective layer 90 may be formed separately from the gate electrode 73G. Furthermore, the protective layer 90 may be formed separately from the field plate electrode 73E. In this way, the protective layer 90 may be formed in a separate process from the boundary electrode 73B and the diode electrode 73D, for example, after the boundary electrode 73B and the diode electrode 73D are formed. In this case, the thickness TP of the protective layer 90 may be set to a desired thickness when the protective layer 90 is formed.

[0201] In the first embodiment, the protective layer 90 may be formed after the anode region 25A is formed. Alternatively, the protective layer 90 may be formed after the boundary well region 25W is formed. One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically inconsistent.

[0202] The term "on" as used in this disclosure includes the meanings of "on" and "above," unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" is intended to mean that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0203] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0204] <Supplementary Notes> The technical ideas that can be understood from this disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the supplementary notes are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each supplementary note should not be limited to the components indicated by the reference numerals.

[0205] [Supplementary Note 1] A semiconductor layer (20) including a first surface (20S), an IGBT region (21) provided in the first surface (20S), a diode region (22) provided in the first surface (20S), an anode region (25A) provided in the diode region (22) of the first surface (20S), an insulating layer (30) provided on the first surface (20S) to cover the IGBT region (21) while exposing the diode region (22), a first electrode layer (40) including: a first electrode portion (41) provided on the insulating layer (30) corresponding to the IGBT region (21), and a second electrode portion (42) provided on the first surface (20S) corresponding to the diode region (22) and spaced apart from the first surface (20S); a conductive protective layer (90) provided between the second electrode portion (42) and the first surface (20S) and electrically connecting the second electrode portion (42) and the anode region (25A), wherein the protective layer (90) is made of conductive polysilicon.

[0206] [Supplementary Note 2] The semiconductor device according to Supplementary Note 1, wherein the protective layer (90) is provided over the entire diode region (22) in a plan view.

[0207] [Supplementary Note 3] The semiconductor device according to Supplementary Note 1 or 2, comprising: a diode trench (71D) having an opening in the first surface (20S) in the diode region (22) and extending to penetrate the anode region (25A); a diode insulating layer (72D) provided in the diode trench (71D); and a diode electrode (73D) embedded in the diode insulating layer (72D) in the diode trench (71D), wherein the protective layer (90) is connected to the diode electrode (73D).

[0208] [Supplementary Note 4] The semiconductor device according to Supplementary Note 3, wherein the protective layer (90) is in contact with both the anode region (25A) and the second electrode portion (42).

[0209] [Supplementary Note 5] The semiconductor device according to Supplementary Note 4, wherein the protective layer (90) is integrated with the diode electrode (73D).

[0210] [Supplementary Note 6] The semiconductor device according to any one of Supplementary Notes 3 to 5, wherein the protective layer (90) and the diode electrode (73D) are made of the same material.

[0211] [Supplementary Note 7] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein a thickness (TP) of the protective layer (90) is thinner than a thickness (T2) of the second electrode portion (42).

[0212] [Supplementary Note 8] The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein the thickness (TP) of the protective layer (90) is 1 / 10 or less of the thickness (T2) of the second electrode portion (42).

[0213] [Supplementary Note 9] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein the thickness (TP) of the protective layer (90) is thinner than the thickness (T4) of the insulating layer (30).

[0214] [Supplementary Note 10] The impurity concentration of the protective layer (90) is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The semiconductor device according to any one of appendices 1 to 9,

[0215] [Supplementary Note 11] The semiconductor device according to any one of Supplementary Notes 1 to 10, wherein the insulating layer (30) includes a diode opening (33) that exposes the diode region (22), and the protective layer (90) includes a side surface (93) that contacts the insulating layer (30) and that constitutes the diode opening (33).

[0216] [Supplementary Note 12] The semiconductor device according to any one of Supplementary Notes 1 to 11, wherein a plurality of the IGBT regions (21) and a plurality of the diode regions (22) are provided, the plurality of the IGBT regions (21) and the plurality of the diode regions (22) are arranged alternately one by one in a first direction (X), a plurality of the protective layers (90) are provided corresponding to the plurality of the diode regions (22), and the plurality of the protective layers (90) are provided at a distance from each other.

[0217] [Supplementary Note 13] The semiconductor device according to any one of Supplementary Notes 1 to 12, comprising: a base region (25B) provided in the IGBT region (21) of the first surface (20S); a gate trench (71G) having an opening in the first surface (20S) in the IGBT region (21) and extending to penetrate the base region (25B); a gate insulating layer (72G) provided in the gate trench (71G); and a gate electrode (73G) embedded in the gate insulating layer (72G) within the gate trench (71G), wherein the protective layer (90) and the gate electrode (73G) are made of the same material.

[0218] [Supplementary Note 14] The semiconductor device according to any one of Supplementary Notes 1 to 13, comprising: a boundary region (23) provided between the IGBT region (21) and the diode region (22); and a boundary well region (25W) provided in the boundary region (23) of the first surface (20S), wherein the insulating layer (30) exposes the boundary region (23), the first electrode layer (40) includes a third electrode portion (43) provided on the first surface (20S) corresponding to the boundary region (23) and spaced apart from the first surface (20S), and the protective layer (90) is provided between the boundary region (23) and the third electrode portion (43) in the boundary region (23), and electrically connects the third electrode portion (43) and the boundary well region (25W).

[0219] [Supplementary Note 15] The semiconductor device according to Supplementary Note 14, comprising: a boundary trench (71B) having an opening in the first surface (20S) in the boundary region (23) and extending to penetrate the boundary well region (25W); a boundary insulating layer (72B) provided in the boundary trench (71B); and a boundary electrode (73B) embedded in the boundary insulating layer (72B) within the boundary trench (71B), wherein both the protective layer (90) and the boundary electrode (73B) are made of the same material.

[0220] [Supplementary Note 16] The semiconductor device according to Supplementary Note 15, wherein the protective layer (90) and the boundary electrode (73B) are integrated.

[0221] [Supplementary Note 17] The semiconductor device according to any one of Supplementary Notes 3 to 6, wherein the thickness (TP) of the protective layer (90) is smaller than the width (WD) of the diode electrode (73D).

[0222] [Supplementary Note 18] The semiconductor device according to Supplementary Note 13, wherein the thickness (TP) of the protective layer (90) is smaller than the width (WG) of the gate electrode (73G).

[0223] [Appendix 19] A semiconductor device (100) including: a first conductivity type semiconductor layer (110) including a first surface (110S); a second conductivity type semiconductor region (114) partially provided on the first surface (110S); an insulating layer (120) provided on the first surface (110S) so as to expose the semiconductor region (114); a conductive protective layer (160) provided on the first surface (110S) and electrically connected to the semiconductor region (114); and a first electrode layer (130) provided on the protective layer (160), wherein the protective layer (160) is made of conductive polysilicon.

[0224] [Supplementary Note 20] The semiconductor device according to Supplementary Note 19, wherein the semiconductor layer (110) includes a second surface (110R) opposite to the first surface (110S), and includes a second electrode layer (150) provided on the second surface (110R).

[0225] [Supplementary Note 21] The semiconductor device according to Supplementary Note 15 or 16, wherein the thickness (TP) of the protective layer (90) is smaller than the width (WB) of the boundary electrode (73B).

[0226] [Supplementary Note 22] The semiconductor device includes: forming a semiconductor layer (800) including a first surface (801) provided with an IGBT region (21) and a diode region (22); forming an insulating layer (30) on the first surface (801) so as to cover the IGBT region (21) while exposing the diode region (22); forming a conductive protective layer (90) on the first surface (801) in the diode region (22); forming an anode region (25A) in the diode region (22) of the first surface (801); and forming a first electrode layer (40) over both the IGBT region (21) and the diode region (22), wherein forming the first electrode layer (40) includes: forming a first electrode portion (41) on the insulating layer (30) corresponding to the IGBT region (21); forming a second electrode portion (42) on the protective layer (90) in correspondence with the diode region (22), wherein the protective layer (90) electrically connects the second electrode portion (42) and the anode region (25A) and is made of conductive polysilicon.

[0227] [Supplementary Note 23] The method for manufacturing a semiconductor device according to Supplementary Note 22, further comprising forming a diode opening (33) in the insulating layer (30) that exposes the diode region (22), wherein forming the diode opening (33) in the insulating layer (30) is performed after forming the protective layer (90).

[0228] [Supplementary Note 24] The method for manufacturing a semiconductor device according to Supplementary Note 22 or 23, wherein forming the protective layer (90) is performed before forming the anode region (25A).

[0229] [Supplementary Note 25] A method for manufacturing a semiconductor device according to any one of Supplementary Notes 22 to 24, comprising: forming a diode trench (71D) having an opening in the first surface (801) in the diode region (22); forming a diode insulating layer (72D) in the diode trench (71D); and forming a diode electrode (73D) in the diode insulating layer (72D) within the diode trench (71D), wherein the protective layer (90) is connected to the diode electrode (73D).

[0230] [Supplementary Note 26] The method for manufacturing a semiconductor device according to Supplementary Note 25, wherein the protective layer (90) and the diode electrode (73D) are integrally formed.

[0231] [Supplementary Note 27] The semiconductor device (10) includes a boundary region (23) provided between the IGBT region (21) and the diode region (22), and includes forming a boundary well region (25W) in the boundary region (23) of the first surface (801), the insulating layer (30) is formed so as to expose the boundary region (23), and forming the first electrode layer (40) includes forming a third electrode portion (43) on the first surface (801) corresponding to the boundary region (23) and spaced apart from the first surface (801), and forming the protective layer (90) includes forming the protective layer (90) in the boundary region (23) between the boundary region (23) and the third electrode portion (43) so as to electrically connect the third electrode portion (43) and the boundary region (23).

[0232] [Supplementary Note 28] A method for manufacturing a semiconductor device according to Supplementary Note 27, comprising: forming a boundary trench (71B) having an opening in the first surface (801) in the boundary region (23); forming a boundary insulating layer (72B) in the boundary trench (71B); and forming a boundary electrode (73B) in the boundary insulating layer (72B) within the boundary trench (71B), wherein the protective layer (90) is connected to the boundary electrode (73B).

[0233] [Supplementary Note 29] The method for manufacturing a semiconductor device according to Supplementary Note 28, wherein the protective layer (90) and the boundary electrode (73B) are integrally formed.

[0234] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims.

[0235] 10...semiconductor device, 20...semiconductor layer, 20S...first surface, 20R...second surface, 20A...sub-region, 20P...first region, 20Q...second region, 21...IGBT region, 21A...IGBT, 22...diode region, 22A...diode, 23...boundary region, 24...emitter region, 25B...base region, 25A...anode region, 25W...boundary well region, 26C...collector region, 26K... Cathode region, 27...buffer region, 28...drift region, 29...carrier storage region, 30...insulating layer, 30S...upper surface, 31...first insulating layer, 32...second insulating layer, 33...diode opening, 33A...side surface, 40...first electrode layer, 40P...first pad electrode, 40G...gate pad electrode, 41...first electrode portion, 42...second electrode portion, 43...third electrode portion, 44...first conductive layer, 45...third 2 conductive layer, 46... third conductive layer, 50... gate wiring, 51... gate finger, 60... second electrode layer, 70... trench structure, 70G... gate trench structure, 71G... gate trench, 72G... gate insulating layer, 73G... gate electrode, 70E... emitter trench structure, 71E... emitter trench, 72E... emitter insulating layer, 73E... field plate electrode, 70D... diode trench structure, 71D... diode trench, 72D... diode insulating layer, 73D... diode electrode, 70B... boundary trench structure, 71B... boundary trench, 72B... boundary insulating layer, 73B... boundary electrode, 80... contact structure, 81... contact hole, 82... emitter contact, 82A... first conductive layer, 82B... second conductive layer, 83... base contact region, 90... protective layer, 91,92...recess, 93...side surface, 100...semiconductor device, 101...active region, 102...peripheral region, 110...semiconductor layer, 110S...first surface, 110R...second surface, 111...cathode region, 112...drift region, 113...buffer region, 114...anode region, 114A...periphery, 115...well region, 116...FLR region, 117...channel stop region, 118...end surface, 120...insulating layer, 121...first contact hole, 122...second contact hole, 130...first electrode layer, 131...anode electrode, 131A...overlap portion, 132...field plate electrode, 132A...drawing portion, 133...EQR electrode, 140...surface protection layer , 141...opening, 150...second electrode layer, 160...protective layer, 800...semiconductor wafer, 801...first surface, 802...second surface, 810...first insulating layer, 820...first metal layer, 830...second insulating layer, 840...second metal layer, 850...third metal layer, 860...fourth metal layer, 900...mask, 910...resist mask, PT...trench structure pitch, T1...thickness of first electrode portion, T2...thickness of second electrode portion, T3...thickness of third electrode portion, T4...thickness of insulating layer, T5...thickness of surface protective layer, TA...thickness of anode electrode, TP...thickness of protective layer, WB...width of boundary electrode, WD...width of diode electrode, WE...width of field plate electrode, WG...width of gate electrode,

Claims

1. A semiconductor device comprising: a semiconductor layer including a first surface; an IGBT region provided on the first surface; a diode region provided on the first surface; an anode region provided in the diode region of the first surface; an insulating layer provided on the first surface to cover the IGBT region while exposing the diode region; a first electrode layer including: a first electrode portion provided on the insulating layer corresponding to the IGBT region; and a second electrode portion provided on the first surface corresponding to the diode region and spaced apart from the first surface; and a conductive protective layer provided between the second electrode portion and the first surface, electrically connecting the second electrode portion and the anode region, wherein the protective layer is made of conductive polysilicon.

2. The semiconductor device according to claim 1, wherein the protective layer is provided over the entire diode region in a plan view.

3. The semiconductor device according to claim 1 or 2, comprising: a diode trench having an opening in the first surface in the diode region and extending to penetrate the anode region; a diode insulating layer provided in the diode trench; and a diode electrode embedded in the diode insulating layer within the diode trench, wherein the protective layer is connected to the diode electrode.

4. The semiconductor device according to claim 3, wherein the protective layer is in contact with both the anode region and the second electrode portion.

5. The semiconductor device according to claim 4, wherein the protective layer is integrated with the diode electrode.

6. The semiconductor device according to any one of claims 3 to 5, wherein the protective layer and the diode electrode are made of the same material.

7. The semiconductor device according to any one of claims 1 to 6, wherein the thickness of the protective layer is thinner than the thickness of the second electrode portion.

8. The semiconductor device according to any one of claims 1 to 7, wherein the thickness of the protective layer is 1 / 10 or less of the thickness of the second electrode portion.

9. The semiconductor device according to any one of claims 1 to 8, wherein the thickness of the protective layer is thinner than the thickness of the insulating layer.

10. The impurity concentration of the protective layer is 1×10 １９ cm －３ 1x10 or more ２１ cm －３ The semiconductor device according to any one of claims 1 to 9, wherein:

11. The semiconductor device according to any one of claims 1 to 10, wherein the insulating layer includes a diode opening that exposes the diode region, and the protective layer includes a side surface that contacts the insulating layer and forms the diode opening.

12. The semiconductor device according to any one of claims 1 to 11, wherein a plurality of the IGBT regions and a plurality of the diode regions are provided, the plurality of the IGBT regions and the plurality of the diode regions are arranged alternately one by one in a first direction, a plurality of the protective layers are provided corresponding to the plurality of the diode regions, and the plurality of the protective layers are provided spaced apart from each other.

13. A semiconductor device according to any one of claims 1 to 12, comprising: a base region provided in the IGBT region of the first surface; a gate trench having an opening in the first surface in the IGBT region and extending to penetrate the base region; a gate insulating layer provided in the gate trench; and a gate electrode embedded in the gate insulating layer within the gate trench, wherein the protective layer and the gate electrode are made of the same material.

14. A semiconductor device as claimed in any one of claims 1 to 13, comprising: a boundary region provided between the IGBT region and the diode region; and a boundary well region provided in the boundary region of the first surface; wherein the insulating layer exposes the boundary region; the first electrode layer includes a third electrode portion on the first surface corresponding to the boundary region and spaced apart from the first surface; and the protective layer is provided in the boundary region between the boundary region and the third electrode portion, electrically connecting the third electrode portion and the boundary well region.

15. The semiconductor device of claim 14, comprising: a boundary trench having an opening in the first surface in the boundary region and extending through the boundary well region; a boundary insulating layer provided in the boundary trench; and a boundary electrode embedded in the boundary insulating layer within the boundary trench, wherein both the protective layer and the boundary electrode are made of the same material.

16. The semiconductor device according to claim 15, wherein the protective layer and the boundary electrode are integrated.

17. The semiconductor device according to any one of claims 3 to 6, wherein the thickness of the protective layer is thinner than the width of the diode electrode.

18. The semiconductor device according to claim 13, wherein the thickness of the protection layer is thinner than the width of the gate electrode.

19. A semiconductor device comprising: a semiconductor layer of a first conductivity type including a first surface; a semiconductor region of a second conductivity type partially provided on the first surface; an insulating layer provided on the first surface so as to expose the semiconductor region; a conductive protective layer provided on the first surface and electrically connected to the semiconductor region; and a first electrode layer provided on the protective layer, wherein the protective layer is made of conductive polysilicon.

20. The semiconductor device according to claim 19, wherein the semiconductor layer includes a second surface opposite to the first surface, and a second electrode layer provided on the second surface.

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