Image display device

Abstract

The present disclosure relates to an image display device. An image display device, according to one embodiment of the present disclosure, comprises: a panel; a signal processing device for signal-processing an input image and outputting an image signal; and a timing controller for driving the panel on the basis of the image signal from the signal processing device, wherein the signal processing device outputs a data enable signal divided into an active period and a blank period, and when a data bit of the image signal is varied, varies the length of the active period or the length of the blank period. Accordingly, gradation representation during image display can be enhanced.

Description

Video display device

[0001] The present disclosure relates to an image display device, and more particularly, to an image display device capable of improving gradation expression when displaying an image.

[0002] A video display device is a device that displays images.

[0003] Recently, with the increase in image resolution, etc., the display resolution or peak luminance of the image displayed on the image display device is increasing.

[0004] Accordingly, when transmitting a processed video signal from a video display device, an upward shift of data bits is required.

[0005] Meanwhile, there is a problem that there is a limitation on the upward expansion of data bits of the video signal due to limitations in transmission frequency, etc.

[0006] The problem of the present disclosure is to provide a video display device capable of improving the gradation expressiveness when displaying a video.

[0007] Another problem of the present disclosure is to provide a display device capable of improving the gradation expressiveness during display of an image by varying a data enable signal based on an image display mode.

[0008] Another problem of the present disclosure is to provide a video display device capable of improving the gradation expressiveness when displaying a video by varying the data bits of a video signal based on the frequency of a vertical synchronization signal.

[0009] Another problem of the present disclosure is to provide a video display device capable of improving the gradation expressiveness when displaying a video without changing the transmission lane of the video signal.

[0010] An image display device according to one embodiment of the present disclosure for solving the above problem includes a panel, a signal processing device for processing an input image and outputting an image signal, and a timing controller for driving the panel based on the image signal from the signal processing device, wherein the signal processing device outputs a data enable signal divided into an active period and a blank period, and varies the length of the active period or the length of the blank period when the data bit of the image signal varies.

[0011] Meanwhile, the signal processing device outputs a first data enable signal corresponding to a first active period and a first blank period when the image display mode is a normal mode, and outputs a second data enable signal corresponding to a second active period and a second blank period when the image display mode is a game mode, and the length of the second active period may be greater than the length of the first active period, and the length of the second blank period may be less than the length of the first blank period.

[0012] Meanwhile, the signal processing device outputs a first data enable signal corresponding to a first active period and a first blank period for displaying an image at a first level of peak luminance on the panel, and outputs a second data enable signal corresponding to a second active period and a second blank period for displaying an image at a second level of peak luminance greater than the first level on the panel, wherein the length of the second active period may be greater than the length of the first active period, and the length of the second blank period may be less than the length of the first blank period.

[0013] Meanwhile, the signal processing device outputs a first data enable signal corresponding to the frequency of the first vertical synchronization signal, and when the data bit of the image signal is any one of the first bit, the second bit, the third bit, the fourth bit, and the fifth bit, the length of the active period or the length of the blank period corresponding to the corresponding bit can be set.

[0014] Meanwhile, the signal processing device may set the length of the active period or the length of the blank period to which the data bits of the image signal correspond to any one of the first number of bits when the vertical synchronization signal frequency corresponds to the frequency of the first vertical synchronization signal, and may set the length of the active period or the length of the blank period to which the data bits of the image signal correspond to any one of the second number of bits smaller than the first number when the vertical synchronization signal frequency corresponds to the frequency of the second vertical synchronization signal higher than the frequency of the first vertical synchronization signal.

[0015] Meanwhile, the signal processing device outputs a second data enable signal corresponding to the frequency of the second vertical synchronization signal, and when the data bit of the image signal is any one of the first bit, the second bit, and the third bit, the length of the active period or the length of the blank period corresponding to the corresponding bit can be set.

[0016] Meanwhile, the signal processing device can control the length of the blank period of the data enable signal to become shorter as the frequency of the vertical synchronization signal increases.

[0017] Meanwhile, the signal processing device can control the length of the active period of the data enable signal to increase or the length of the blank period to decrease as the data bit of the image signal increases.

[0018] Meanwhile, the signal processing device can vary the length of the active interval or the length of the blank interval when in data enable variable mode.

[0019] Meanwhile, the signal processing device can fix the length of the active period and the length of the blank period when in data enable fixed mode.

[0020] Meanwhile, the signal processing device can output an image signal including R, G, and B data in response to the length of the active section of the data enable signal.

[0021] Meanwhile, the signal processing device can control the data bits of the R, G, and B data to increase as the length of the active section of the data enable signal increases.

[0022] According to another embodiment of the present disclosure, an image display device includes a panel, a signal processing device that processes an input image to output an image signal, and a timing controller that drives the panel based on the image signal from the signal processing device, wherein the signal processing device outputs a first data enable signal corresponding to a first active period and a first blank period when the image display mode is a normal mode, and outputs a second data enable signal corresponding to a second active period and a second blank period when the image display mode is a game mode, wherein a length of the second active period is greater than a length of the first active period, and a length of the second blank period is less than a length of the first blank period.

[0023] Meanwhile, the signal processing device can control the data bits of the R, G, B data output in the game mode to be larger than the data bits of the R, G, B data output in the normal mode.

[0024] Meanwhile, the signal processing device outputs a second data enable signal corresponding to a second active period and a second blank period when the image display mode is a game mode and the vertical synchronization signal frequency corresponds to a frequency of the first vertical synchronization signal, and outputs a third data enable signal corresponding to a third active period and a third blank period when the image display mode is a game mode and the vertical synchronization signal frequency corresponds to a frequency of the second vertical synchronization signal greater than the frequency of the first vertical synchronization signal, and the length of the third active period may be greater than the length of the second active period, and the length of the third blank period may be less than the length of the second blank period.

[0025] According to another embodiment of the present disclosure, an image display device includes a panel, a signal processing device that processes an input image to output an image signal, and a timing controller that drives the panel based on the image signal from the signal processing device, wherein the signal processing device outputs a data enable signal divided into an active period and a blank period, and in the case of a data enable variable mode, varies the length of the active period or the length of the blank period, and in the case of a data enable fixed mode, fixes the length of the active period and the length of the blank period.

[0026] Meanwhile, the signal processing device is in a data enable variable mode, and when the image display mode is a normal mode, outputs a first data enable signal corresponding to a first active period and a first blank period, and when the image display mode is in a data enable variable mode, outputs a second data enable signal corresponding to a second active period and a second blank period, and a length of the second active period may be greater than a length of the first active period, and a length of the second blank period may be less than a length of the first blank period.

[0027] Meanwhile, the signal processing device, when in the data enable variable mode, outputs a first data enable signal corresponding to the frequency of the first vertical synchronization signal, and when the data bit of the image signal is any one of the first bit, the second bit, the third bit, the fourth bit, and the fifth bit, can set the length of the active period or the length of the blank period corresponding to the corresponding bit.

[0028] According to one embodiment of the present disclosure, a video display device includes a panel, a signal processing device that processes an input image and outputs an image signal, and a timing controller that drives the panel based on the image signal from the signal processing device, wherein the signal processing device outputs a data enable signal divided into an active period and a blank period, and varies the length of the active period or the length of the blank period when the data bit of the image signal varies. Accordingly, it is possible to improve the gradation expressivity during image display. In particular, it is possible to improve the gradation expressivity during image display without varying the transmission lane of the image signal.

[0029] Meanwhile, the signal processing device outputs a first data enable signal corresponding to a first active period and a first blank period when the image display mode is a normal mode, and outputs a second data enable signal corresponding to a second active period and a second blank period when the image display mode is a game mode, wherein the length of the second active period may be greater than the length of the first active period, and the length of the second blank period may be less than the length of the first blank period. Accordingly, by varying the data enable signal based on the image display mode, it is possible to improve the gradation expressiveness during image display.

[0030] Meanwhile, the signal processing device outputs a first data enable signal corresponding to a first active period and a first blank period for displaying an image with a first level of peak luminance on the panel, and outputs a second data enable signal corresponding to a second active period and a second blank period for displaying an image with a second level of peak luminance greater than the first level on the panel, wherein the length of the second active period may be greater than the length of the first active period, and the length of the second blank period may be less than the length of the first blank period. Accordingly, by varying the data enable signal, it is possible to improve the gradation expressiveness during image display.

[0031] Meanwhile, the signal processing device outputs a first data enable signal corresponding to the frequency of the first vertical synchronization signal, and when the data bit of the image signal is any one of the first bit, the second bit, the third bit, the fourth bit, and the fifth bit, the length of the active period or the length of the blank period corresponding to the corresponding bit can be set. Accordingly, by varying the data enable signal based on the vertical synchronization signal frequency, it is possible to improve the gradation expressiveness when displaying an image.

[0032] Meanwhile, the signal processing device may set the length of the active period or the length of the blank period, in which the data bits of the image signal correspond to any one of the first number of bits when the vertical synchronization signal frequency corresponds to the frequency of the first vertical synchronization signal, and may set the length of the active period or the length of the blank period, in which the data bits of the image signal correspond to any one of the second number of bits smaller than the first number when the vertical synchronization signal frequency corresponds to the frequency of the second vertical synchronization signal higher than the frequency of the first vertical synchronization signal. Accordingly, by varying the data enable signal based on the vertical synchronization signal frequency, it is possible to improve the gradation expressiveness when displaying an image.

[0033] Meanwhile, the signal processing device outputs a second data enable signal corresponding to the frequency of the second vertical synchronization signal, and, when the data bit of the image signal is any one of the first bit, the second bit, and the third bit, can set the length of the active period or the length of the blank period corresponding to the corresponding bit. Accordingly, by varying the data enable signal based on the vertical synchronization signal frequency, it is possible to improve the gradation expressiveness when displaying an image.

[0034] Meanwhile, the signal processing device can control the blank interval length of the data enable signal to become shorter as the frequency of the vertical synchronization signal increases. Accordingly, by varying the data enable signal based on the vertical synchronization signal frequency, it is possible to improve the gradation expressiveness during image display.

[0035] Meanwhile, the signal processing device can control the length of the active period of the data enable signal to increase or the length of the blank period to decrease as the data bits of the image signal increase. Accordingly, by varying the data enable signal, the gradation expressiveness during image display can be improved.

[0036] Meanwhile, the signal processing device can vary the length of the active interval or the length of the blank interval when in the data enable variable mode. Accordingly, by varying the data enable signal according to the data enable variable mode, it is possible to improve the gradation expressiveness during image display.

[0037] Meanwhile, the signal processing device can fix the length of the active interval and the length of the blank interval when in data enable fixed mode. Accordingly, it can operate in data enable fixed mode.

[0038] Meanwhile, the signal processing device can output an image signal including R, G, and B data in response to the length of the active section of the data enable signal. Accordingly, the gradation expressiveness during image display can be improved.

[0039] Meanwhile, the signal processing device can control the data bits of the R, G, and B data to increase as the length of the active section of the data enable signal increases. Accordingly, the gradation expressiveness during image display can be improved.

[0040] According to another embodiment of the present disclosure, a video display device includes a panel, a signal processing device that processes an input image and outputs an image signal, and a timing controller that drives the panel based on the image signal from the signal processing device, wherein the signal processing device outputs a first data enable signal corresponding to a first active period and a first blank period when the image display mode is a normal mode, and outputs a second data enable signal corresponding to a second active period and a second blank period when the image display mode is a game mode, wherein the length of the second active period is greater than the length of the first active period, and the length of the second blank period is less than the length of the first blank period. Accordingly, by varying the data enable signal based on the image display mode, it is possible to improve the gradation expressivity during image display. In particular, it is possible to improve the gradation expressivity during image display without varying a transmission lane of the image signal.

[0041] Meanwhile, the signal processing device can control the data bits of the R, G, B data output in the game mode to be larger than the data bits of the R, G, B data output in the normal mode. Accordingly, the gradation expressiveness in the game mode can be improved compared to the normal mode.

[0042] Meanwhile, the signal processing device outputs a second data enable signal corresponding to a second active period and a second blank period when the image display mode is a game mode and the vertical synchronization signal frequency corresponds to a frequency of the first vertical synchronization signal, and outputs a third data enable signal corresponding to a third active period and a third blank period when the image display mode is a game mode and the vertical synchronization signal frequency corresponds to a frequency of the second vertical synchronization signal greater than the frequency of the first vertical synchronization signal, and the length of the third active period may be greater than the length of the second active period, and the length of the third blank period may be less than the length of the second blank period. Accordingly, by varying the data enable signal based on the image display mode, it is possible to improve the gradation expressiveness during image display.

[0043] According to another embodiment of the present disclosure, a video display device includes a panel, a signal processing device that processes an input image to output a video signal, and a timing controller that drives the panel based on the video signal from the signal processing device, wherein the signal processing device outputs a data enable signal divided into an active period and a blank period, and in the case of a data enable variable mode, the length of the active period or the length of the blank period is varied, and in the case of a data enable fixed mode, the length of the active period and the length of the blank period are fixed. Accordingly, it is possible to improve the gradation expressiveness when displaying an image based on the data enable variable mode. In particular, it is possible to improve the gradation expressiveness when displaying an image without varying a transmission lane of an image signal.

[0044] Meanwhile, the signal processing device is in a data enable variable mode, and when the image display mode is a normal mode, outputs a first data enable signal corresponding to a first active period and a first blank period, and when the data enable variable mode and when the image display mode is a game mode, outputs a second data enable signal corresponding to a second active period and a second blank period, and the length of the second active period may be greater than the length of the first active period, and the length of the second blank period may be less than the length of the first blank period. Accordingly, the gradation expressiveness during image display can be improved based on the data enable variable mode.

[0045] Meanwhile, the signal processing device, in the case of the data enable variable mode, outputs a first data enable signal corresponding to the frequency of the first vertical synchronization signal, and, when the data bit of the image signal is any one of the first bit, the second bit, the third bit, the fourth bit, and the fifth bit, can set the length of the active period or the length of the blank period corresponding to the corresponding bit. Accordingly, it is possible to improve the gradation expressiveness when displaying an image based on the data enable variable mode.

[0046] FIG. 1 is a drawing illustrating an image display device according to one embodiment of the present disclosure.

[0047] Figure 2 is an example of an internal block diagram of the video display device of Figure 1.

[0048] Figure 3 is an example of an internal block diagram of the signal processing device of Figure 2.

[0049] Figure 4a is a drawing illustrating a control method of the remote control device of Figure 2.

[0050] Figure 4b is an internal block diagram of the remote control device of Figure 2.

[0051] Figure 5 is an example of an internal block diagram of the display of Figure 2.

[0052] FIGS. 6A and 6B are drawings for reference in the description of the organic light-emitting panel of FIG. 5.

[0053] FIG. 7 is an example of an internal block diagram of a video display device according to one embodiment of the present disclosure.

[0054] FIG. 8 is an example of an internal block diagram of a signal processing device according to one embodiment of the present disclosure.

[0055] FIGS. 9A to 9C are drawings for reference in explaining the operation of a video display device related to the present disclosure.

[0056] FIG. 10a is a flowchart showing an example of an operation method of an image display device according to an embodiment of the present disclosure.

[0057] FIG. 10b is a flowchart showing another example of an operating method of an image display device according to an embodiment of the present disclosure.

[0058] FIG. 10c is a flowchart showing another example of an operating method of an image display device according to an embodiment of the present disclosure.

[0059] FIG. 10d is a flowchart showing another example of an operating method of an image display device according to an embodiment of the present disclosure.

[0060] Figures 11a to 14b are drawings referenced in the description of Figures 10a to 10d.

[0061] Hereinafter, the present disclosure will be described in more detail with reference to the drawings.

[0062] The suffixes "module" and "part" used in the following description are given solely for the convenience of writing this specification and do not impart any particularly significant meaning or role to the components themselves. Therefore, the terms "module" and "part" may be used interchangeably.

[0063] FIG. 1 is a drawing illustrating an image display device according to one embodiment of the present disclosure.

[0064] Referring to the drawing, the image display device (100) may include a display (180).

[0065] The image display device (100) can receive image signals from various external devices, process them, and display them on a display (180).

[0066] The various external devices may be, for example, a computer (PC), a mobile terminal (600) such as a smart phone, a set-top box (STB), a game console (GSB), a server (SVR), etc.

[0067] Meanwhile, the display (180) may be implemented as any one of various panels. For example, the display (180) may be any one of self-luminous panels such as an organic light-emitting panel (OLED panel), an inorganic light-emitting panel (LED panel), and a micro LED panel.

[0068] In this disclosure, the display (180) is described mainly with an organic light-emitting panel (OLED panel).

[0069] Meanwhile, organic light-emitting panels (OLED panels) have the advantages of faster panel response speed, superior color reproduction, and superior color reproducibility compared to liquid crystal display panels.

[0070] Accordingly, when the display (180) is equipped with an organic light-emitting panel, it is preferable that the signal processing unit (170 in FIG. 2) in the image display device (100) performs image quality processing corresponding to the organic light-emitting panel.

[0071] Meanwhile, the display (180) may be equipped with a panel and a timing controller, and an image can be displayed on the panel through signal processing of the timing controller.

[0072] Meanwhile, in the timing controller, when outputting a video signal to the panel, if memory is used, the video signal can be output to the panel using data stored in the memory.

[0073] Meanwhile, in order to slim down the timing controller, if the timing controller does not use or is not equipped with memory, the amount of signal processing in the timing controller increases, and in particular, when the resolution of the image increases, the amount of signal processing becomes more severe.

[0074] Accordingly, in accordance with the trend of slimming down timing controllers, the present disclosure proposes a method for accurately and quickly performing signal processing for a panel in a timing controller when memory is not used or is hardly used.

[0075] To this end, the present disclosure proposes a method of signal processing a received image and, in addition to outputting the signal-processed first frame image data, additionally outputting second image frame data downscaled based on the received image.

[0076] An image display device (100) according to one embodiment of the present disclosure may include a signal processing device (170) that outputs first image frame data (ImgL) with a delay compared to second image frame data (ImgS), a timing controller (232) that performs signal processing based on an image signal output from the signal processing device (170), and a panel (210) that displays an image based on a signal from the timing controller (232). Accordingly, the timing controller (232) can accurately and quickly perform signal processing on the panel (210).

[0077] Meanwhile, a signal processing device (170) in a video display device (100) according to one embodiment of the present disclosure includes an input interface (IIP) for receiving a video signal from the outside, a first video processing unit (1010) for generating first video frame data (ImgL) based on the video signal, a second video processing unit (1020) for generating second video frame data (ImgS) scaled down from the first video frame data (ImgL) based on the video signal, and an output interface (OIP) for receiving the first video frame data (ImgL) from the first video processing unit (1010) and the second video frame data (ImgS) from the second video processing unit (1020), and outputting the first video frame data (ImgL) and the second video frame data (ImgS), wherein the first video frame data (ImgL) output from the output interface (OIP) is output with a delay compared to the second video frame data (ImgS). Accordingly, it is possible to output a signal so that accurate and rapid signal processing is possible in the timing controller. Meanwhile, the timing controller can accurately and rapidly perform signal processing on the delayed output first image frame data (ImgL) based on the second image frame data (ImgS). In particular, the timing controller can accurately and rapidly perform signal processing for reducing power consumption.

[0078] Meanwhile, a signal processing device (170) in a video display device (100) according to another embodiment of the invention includes an input interface (IIP) for receiving a video signal from the outside, a first video processing unit (1010) for generating first video frame data (ImgL) based on the video signal, a second video processing unit (1020) for generating video frame data based on the video signal, a data enable signal (DE) divided into an active period (HA) and a blank period (HB), and an output interface (OIP) for outputting a data signal of the first video frame data (ImgL) and a data signal of the second video frame data (ImgS), and when only the data signal of the first video frame data (ImgL) is output, the output interface (OIP) sets the active period (HA) of the first data enable signal (DE) to a first length (Wa) and outputs the data signal of the first video frame data (ImgL) and the data signal of the second video frame data (ImgS) together. In this case, the active period (HA) of the second data enable signal (DE) is set to a second length (Wb) that is greater than the first length (Wa). Accordingly, a signal can be output so that accurate and rapid signal processing is possible in the timing controller.

[0079] Meanwhile, the video display device (100) of FIG. 1 can be a TV, monitor, tablet PC, mobile terminal, vehicle display device, etc.

[0080] Figure 2 is an example of an internal block diagram of the video display device of Figure 1.

[0081] Referring to FIG. 2, an image display device (100) according to an embodiment of the present disclosure may include an image receiving unit (105), an external device interface unit (130), a storage unit (140), a user input interface unit (150), a sensor unit (not shown), a signal processing unit (170), a display (180), and an audio output unit (185).

[0082] The video receiving unit (105) may include a tuner unit (110), a demodulation unit (120), a network interface unit (130), and an external device interface unit (130).

[0083] Meanwhile, unlike the drawing, the video receiving unit (105) may include only a tuner unit (110), a demodulator unit (120), and an external device interface unit (130). That is, it may not include a network interface unit (130).

[0084] The tuner unit (110) selects an RF broadcast signal corresponding to a channel selected by the user or all pre-stored channels among RF (Radio Frequency) broadcast signals received through an antenna (not shown). In addition, it converts the selected RF broadcast signal into an intermediate frequency signal or a baseband video or audio signal.

[0085] For example, if the selected RF broadcast signal is a digital broadcast signal, it is converted into a digital IF signal (DIF), and if it is an analog broadcast signal, it is converted into an analog baseband video or audio signal (CVBS / SIF). That is, the tuner unit (110) can process a digital broadcast signal or an analog broadcast signal. The analog baseband video or audio signal (CVBS / SIF) output from the tuner unit (110) can be directly input to the signal processing device (170).

[0086] Meanwhile, the tuner unit (110) may be equipped with multiple tuners to receive broadcast signals of multiple channels. Alternatively, a single tuner that simultaneously receives broadcast signals of multiple channels is also possible.

[0087] The demodulation unit (120) receives the digital IF signal (DIF) converted from the tuner unit (110) and performs a demodulation operation.

[0088] The demodulator (120) can output a stream signal (TS) after performing demodulation and channel decoding. At this time, the stream signal may be a signal in which a video signal, an audio signal, or a data signal is multiplexed.

[0089] The stream signal output from the demodulator (120) can be input to the signal processing device (170). The signal processing device (170) performs demultiplexing, image / audio signal processing, etc., and then outputs an image to the display (180) and outputs an audio to the audio output device (185).

[0090] The external device interface unit (130) can transmit or receive data to or from a connected external device (not shown), for example, a set-top box (50). To this end, the external device interface unit (130) may include an A / V input / output unit (not shown).

[0091] The external device interface unit (130) can be connected to external devices such as a DVD (Digital Versatile Disk), Blu-ray, game device, camera, camcorder, computer (laptop), set-top box, etc., via wired / wireless connection, and can also perform input / output operations with the external devices.

[0092] The A / V input / output unit can receive video and audio signals from an external device. Meanwhile, the wireless communication unit (not shown) can perform short-range wireless communication with other electronic devices.

[0093] Through this wireless communication unit (not shown), the external device interface unit (130) can exchange data with an adjacent mobile terminal (600). In particular, the external device interface unit (130) can receive device information, running application information, application images, etc. from the mobile terminal (600) in mirroring mode.

[0094] The network interface unit (135) provides an interface for connecting the video display device (100) to a wired / wireless network, including the Internet. For example, the network interface unit (135) can receive content or data provided by the Internet, a content provider, or a network operator via a network.

[0095] Meanwhile, the network interface unit (135) may include a wireless communication unit (not shown).

[0096] The storage unit (140) may store programs for each signal processing and control within the signal processing device (170), and may also store signal-processed image, voice, or data signals.

[0097] In addition, the storage unit (140) may also perform a function for temporary storage of video, audio, or data signals input to the external device interface unit (130). In addition, the storage unit (140) may store information regarding a specific broadcast channel through a channel memory function such as a channel map.

[0098] Although the storage unit (140) of FIG. 2 illustrates an embodiment in which the storage unit (140) is provided separately from the signal processing device (170), the scope of the present disclosure is not limited thereto. The storage unit (140) may be included within the signal processing device (170).

[0099] The user input interface unit (150) transmits a signal input by the user to the signal processing device (170) or transmits a signal from the signal processing device (170) to the user.

[0100] For example, a user input signal such as power on / off, channel selection, screen setting, etc. may be transmitted / received from a remote control device (200), a user input signal input from a local key (not shown) such as a power key, a channel key, a volume key, a setting value, etc. may be transmitted to a signal processing device (170), a user input signal input from a sensor unit (not shown) that senses a user's gesture may be transmitted to the signal processing device (170), or a signal from the signal processing device (170) may be transmitted to a sensor unit (not shown).

[0101] The signal processing device (170) can demultiplex an input stream or process demultiplexed signals through a tuner unit (110), a demodulator unit (120), a network interface unit (135), or an external device interface unit (130) to generate and output a signal for video or audio output.

[0102] For example, the signal processing device (170) can receive a broadcast signal or an HDMI signal received from the image receiving unit (105), perform signal processing based on the received broadcast signal or HDMI signal, and output a signal-processed image signal.

[0103] An image signal processed by a signal processing device (170) may be input to a display (180) and displayed as an image corresponding to the image signal. In addition, an image signal processed by a signal processing device (170) may be input to an external output device through an external device interface unit (130).

[0104] The voice signal processed in the signal processing device (170) can be output as sound to the audio output unit (185). In addition, the voice signal processed in the signal processing device (170) can be input to an external output device through the external device interface unit (130).

[0105] Although not illustrated in FIG. 2, the signal processing device (170) may include a demultiplexing unit, an image processing unit, etc. That is, the signal processing device (170) may perform various signal processing operations and, accordingly, may be implemented in the form of a system on chip (SOC). This will be described later with reference to FIG. 3.

[0106] In addition, the signal processing device (170) can control the overall operation within the video display device (100). For example, the signal processing device (170) can control the tuner unit (110) to select (tune) an RF broadcast corresponding to a channel selected by a user or a pre-stored channel.

[0107] In addition, the signal processing device (170) can control the image display device (100) by a user command or internal program input through the user input interface unit (150).

[0108] Meanwhile, the signal processing device (170) can control the display (180) to display an image. At this time, the image displayed on the display (180) may be a still image or a moving image, and may be a 2D image or a 3D image.

[0109] Meanwhile, the signal processing device (170) can cause a predetermined object to be displayed within an image displayed on the display (180). For example, the object can be at least one of a connected web screen (newspaper, magazine, etc.), an EPG (Electronic Program Guide), various menus, widgets, icons, still images, videos, and text.

[0110] Meanwhile, the signal processing device (170) can recognize the user's location based on an image captured from a camera (not shown). For example, the distance (z-axis coordinate) between the user and the image display device (100) can be determined. In addition, the x-axis coordinate and y-axis coordinate within the display (180) corresponding to the user's location can be determined.

[0111] The display (180) generates a driving signal by converting a video signal, data signal, OSD signal, control signal, etc. processed by the signal processing device (170) or a video signal, data signal, control signal, etc. received from the external device interface unit (130).

[0112] Meanwhile, the display (180) is configured as a touch screen and can be used as an input device in addition to an output device.

[0113] The audio output unit (185) receives a signal processed by the signal processing device (170) and outputs it as voice.

[0114] A camera unit (not shown) photographs a user. The camera unit (not shown) may be implemented with a single camera, but is not limited thereto, and may also be implemented with multiple cameras. Image information captured by the camera unit (not shown) may be input to a signal processing device (170).

[0115] The signal processing device (170) can detect the user's gesture based on an image captured from a shooting unit (not shown) or a signal detected from a sensor unit (not shown), or a combination thereof.

[0116] The power supply unit (190) supplies power to the entire video display device (100).

[0117] In particular, the power supply unit (190) can supply power to a signal processing unit (170) that can be implemented in the form of a system on chip (SOC), a display (180) for displaying images, and an audio output unit (185) for audio output.

[0118] Specifically, the power supply (190) may be equipped with a converter that converts the level of the input voltage.

[0119] For example, the power supply (190) may have an ac / dc converter and a dc / dc converter when the input voltage is an alternating voltage.

[0120] As another example, the power supply (190) may have a dc / dc converter when the input voltage is a direct current voltage.

[0121] The remote control device (200) transmits user input to the user input interface unit (150). To this end, the remote control device (200) may use Bluetooth, RF (Radio Frequency) communication, IR (Infrared) communication, UWB (Ultra Wideband), ZigBee, etc. In addition, the remote control device (200) may receive video, audio, or data signals output from the user input interface unit (150) and display or output the same as audio on the remote control device (200).

[0122] Meanwhile, the above-described video display device (100) may be a digital broadcast receiver capable of receiving fixed or mobile digital broadcasts.

[0123] Meanwhile, the block diagram of the image display device (100) illustrated in FIG. 2 is a block diagram for one embodiment of the present disclosure. Each component of the block diagram may be integrated, added, or omitted depending on the specifications of the image display device (100) actually implemented. That is, two or more components may be combined into one component, or one component may be subdivided into two or more components, as needed. In addition, the functions performed by each block are intended to explain the embodiment of the present disclosure, and the specific operations or devices thereof do not limit the scope of the present disclosure.

[0124] Figure 3 is an example of an internal block diagram of the signal processing device of Figure 2.

[0125] Referring to the drawings, a signal processing device (170) according to an embodiment of the present disclosure may include a demultiplexing unit (310), an image processing unit (320), a processor (330), and an audio processing unit (370). In addition, a data processing unit (not shown) may be further included.

[0126] The demultiplexer (310) demultiplexes the input stream. For example, when MPEG-2 TS is input, it can be demultiplexed to separate it into video, audio, and data signals, respectively. Here, the stream signal input to the demultiplexer (310) may be a stream signal output from the tuner (110), the demodulator (120), or the external device interface (130).

[0127] The image processing unit (320) can perform signal processing on an input image. For example, the image processing unit (320) can perform image processing on an image signal demultiplexed from the demultiplexing unit (310).

[0128] To this end, the image processing unit (320) may include an image decoder (325), a scaler (335), an image quality processing unit (635), an image encoder (not shown), a graphics processing unit (340), a frame rate conversion unit (350), and a formatter (360).

[0129] The video decoder (325) decodes the demultiplexed video signal, and the scaler (335) scales the resolution of the decoded video signal so that it can be output on the display (180).

[0130] The video decoder (325) can be equipped with decoders of various standards. For example, it can be equipped with an MPEG-2, H.264 decoder, a 3D video decoder for color images and depth images, a decoder for multi-view images, etc.

[0131] The scaler (335) can scale an input video signal that has been decoded by a video decoder (325), etc.

[0132] For example, the scaler (335) can upscale when the size or resolution of the input image signal is small, and downscale when the size or resolution of the input image signal is large.

[0133] The image quality processing unit (635) can perform image quality processing on an input image signal for which image decoding has been completed in the image decoder (325), etc.

[0134] For example, the image quality processing unit (635) may perform noise removal processing of an input image signal, expand the resolution of the gradation of an input image signal, perform image resolution enhancement, perform signal processing based on high dynamic range (HDR), vary the frame rate, or perform image quality processing corresponding to panel characteristics, particularly the panel.

[0135] The graphic processing unit (340) generates an OSD signal based on user input or on its own. For example, based on a user input signal, a signal for displaying various information in the form of graphics or text on the screen of the display (180) may be generated. The generated OSD signal may include various data such as the user interface screen of the image display device (100), various menu screens, widgets, and icons. In addition, the generated OSD signal may include a 2D object or a 3D object.

[0136] In addition, the graphic processing unit (340) can generate a pointer that can be displayed on the display based on a pointing signal input from the remote control device (200). In particular, such a pointer can be generated by the pointing signal processing unit, and the graphic processing unit (240) can include such a pointing signal processing unit (not shown). Of course, the pointing signal processing unit (not shown) can also be provided separately rather than being included within the graphic processing unit (240).

[0137] The frame rate converter (FRC) (350) can convert the frame rate of an input video. Meanwhile, the frame rate converter (350) can also output the video as is without a separate frame rate conversion.

[0138] Meanwhile, the formatter (360) can change the format of an input video signal into a video signal for display on a display and output it.

[0139] In particular, the formatter (360) can change the format of the video signal to correspond to the display panel.

[0140] Meanwhile, the formatter (360) can also change the format of the video signal.

[0141] The processor (330) can control the overall operation within the image display device (100) or the signal processing device (170).

[0142] For example, the processor (330) can control the tuner (110) to select (tuning) an RF broadcast corresponding to a channel selected by the user or a pre-stored channel.

[0143] In addition, the processor (330) can control the image display device (100) by a user command or internal program input through the user input interface unit (150).

[0144] Additionally, the processor (330) can perform data transmission control with the network interface unit (135) or the external device interface unit (130).

[0145] Additionally, the processor (330) can control the operation of the demultiplexing unit (310), the image processing unit (320), etc., within the signal processing device (170).

[0146] Meanwhile, the audio processing unit (370) within the signal processing device (170) can perform audio processing of the demultiplexed audio signal. To this end, the audio processing unit (370) can be equipped with various decoders.

[0147] Additionally, the audio processing unit (370) within the signal processing device (170) can process bass, treble, volume control, etc.

[0148] A data processing unit (not shown) within a signal processing device (170) can perform data processing on a demultiplexed data signal. For example, if the demultiplexed data signal is an encoded data signal, it can be decoded. The encoded data signal may be electronic program guide information (EPG) information that includes broadcast information such as the start time and end time of a broadcast program broadcast on each channel.

[0149] Meanwhile, the block diagram of the signal processing device (170) illustrated in FIG. 3 is a block diagram for one embodiment of the present disclosure. Each component of the block diagram may be integrated, added, or omitted depending on the specifications of the signal processing device (170) actually implemented.

[0150] In particular, the frame rate conversion unit (350) and formatter (360) may be provided separately from the image processing unit (320).

[0151] Meanwhile, a signal processing device (170) according to an embodiment of the present disclosure may further include a neural network processor (333) for learning processing, etc.

[0152] Figure 4a is a drawing illustrating a control method of the remote control device of Figure 2.

[0153] As shown in (a) of FIG. 4a, a pointer (205) corresponding to a remote control device (200) is displayed on the display (180).

[0154] The user can move or rotate the remote control device (200) up and down, left and right ((b) of FIG. 4a), and forward and backward ((c) of FIG. 4a). The pointer (205) displayed on the display (180) of the video display device corresponds to the movement of the remote control device (200). As shown in the drawing, the pointer (205) moves and is displayed according to the movement in 3D space, so the remote control device (200) can be called a space remote control or a 3D pointing device.

[0155] Figure 4a (b) illustrates that when a user moves the remote control device (200) to the left, the pointer (205) displayed on the display (180) of the video display device also moves to the left in response.

[0156] Information about the movement of the remote control device (200) detected by the sensor of the remote control device (200) is transmitted to the image display device. The image display device can calculate the coordinates of the pointer (205) from the information about the movement of the remote control device (200). The image display device can display the pointer (205) to correspond to the calculated coordinates.

[0157] FIG. 4A (c) illustrates a case where, while pressing a specific button within the remote control device (200), the user moves the remote control device (200) away from the display (180). As a result, the selection area within the display (180) corresponding to the pointer (205) may be zoomed in and displayed in an enlarged manner. Conversely, when the user moves the remote control device (200) closer to the display (180), the selection area within the display (180) corresponding to the pointer (205) may be zoomed out and displayed in a reduced manner. Meanwhile, when the remote control device (200) moves away from the display (180), the selection area may be zoomed out, and when the remote control device (200) moves closer to the display (180), the selection area may be zoomed in.

[0158] Meanwhile, when a specific button within the remote control device (200) is pressed, recognition of up, down, left, and right movements may be excluded. That is, when the remote control device (200) moves away from or toward the display (180), up, down, left, and right movements may not be recognized, and only forward and backward movements may be recognized. When a specific button within the remote control device (200) is not pressed, only the pointer (205) moves in accordance with the up, down, left, and right movements of the remote control device (200).

[0159] Meanwhile, the movement speed or movement direction of the pointer (205) can correspond to the movement speed or movement direction of the remote control device (200).

[0160] Figure 4b is an internal block diagram of the remote control device of Figure 2.

[0161] Referring to the drawing, the remote control device (200) may include a wireless communication unit (425), a user input unit (435), a sensor unit (440), an output unit (450), a power supply unit (460), a storage unit (470), and a control unit (480).

[0162] The wireless communication unit (425) transmits and receives signals with any one of the image display devices according to the embodiments of the present disclosure described above. Among the image display devices according to the embodiments of the present disclosure, one image display device (100) will be described as an example.

[0163] In this embodiment, the remote control device (200) may be equipped with an RF module (421) capable of transmitting and receiving signals with the image display device (100) in accordance with RF communication standards. In addition, the remote control device (200) may be equipped with an IR module (423) capable of transmitting and receiving signals with the image display device (100) in accordance with IR communication standards.

[0164] In this embodiment, the remote control device (200) transmits a signal containing information about the movement of the remote control device (200) to the image display device (100) through the RF module (421).

[0165] In addition, the remote control device (200) can receive a signal transmitted by the image display device (100) through the RF module (421). In addition, the remote control device (200) can transmit commands for power on / off, channel change, volume change, etc. to the image display device (100) through the IR module (423) as needed.

[0166] The user input unit (435) may be configured as a keypad, a button, a touch pad, or a touch screen. The user can input a command related to the image display device (100) to the remote control device (200) by operating the user input unit (435). If the user input unit (435) has a hard key button, the user can input a command related to the image display device (100) to the remote control device (200) by pushing the hard key button. If the user input unit (435) has a touch screen, the user can input a command related to the image display device (100) to the remote control device (200) by touching a soft key of the touch screen. In addition, the user input unit (435) may be equipped with various types of input means that the user can operate, such as a scroll key or a jog key, and the present embodiment does not limit the scope of the present disclosure.

[0167] The sensor unit (440) may be equipped with a gyro sensor (441) or an acceleration sensor (443). The gyro sensor (441) may sense information regarding the movement of the remote control device (200).

[0168] For example, a gyro sensor (441) can sense information about the operation of a remote control device (200) based on the x, y, and z axes. An acceleration sensor (443) can sense information about the movement speed of the remote control device (200). Meanwhile, a distance measuring sensor can be further provided, thereby sensing the distance to the display (180).

[0169] The output unit (450) can output a video or audio signal corresponding to the operation of the user input unit (435) or to a signal transmitted from the video display device (100). Through the output unit (450), the user can recognize whether the user input unit (435) is being operated or whether the video display device (100) is being controlled.

[0170] For example, the output unit (450) may be equipped with an LED module (451) that lights up when the user input unit (435) is operated or a signal is transmitted and received with the image display device (100) through the wireless communication unit (425), a vibration module (453) that generates vibration, an audio output module (455) that outputs audio, or a display module (457) that outputs audio.

[0171] The power supply unit (460) supplies power to the remote control device (200). The power supply unit (460) can reduce power waste by stopping the power supply when the remote control device (200) is not moved for a predetermined period of time. The power supply unit (460) can resume the power supply when a predetermined key provided on the remote control device (200) is operated.

[0172] The storage unit (470) can store various types of programs, application data, etc. required for the control or operation of the remote control device (200). If the remote control device (200) wirelessly transmits and receives signals through the image display device (100) and the RF module (421), the remote control device (200) and the image display device (100) transmit and receive signals through a predetermined frequency band. The control unit (480) of the remote control device (200) can store and refer to information regarding the frequency band through which signals can be wirelessly transmitted and received between the remote control device (200) and the paired image display device (100), etc., in the storage unit (470).

[0173] The control unit (480) controls all matters related to the control of the remote control device (200). The control unit (480) can transmit a signal corresponding to a predetermined key operation of the user input unit (435) or a signal corresponding to the movement of the remote control device (200) sensed by the sensor unit (440) to the image display device (100) via the wireless communication unit (425).

[0174] The user input interface unit (150) of the video display device (100) may be equipped with a wireless communication unit (151) capable of wirelessly transmitting and receiving signals with a remote control device (200), and a coordinate value calculation unit (415) capable of calculating the coordinate value of a pointer corresponding to the operation of the remote control device (200).

[0175] The user input interface unit (150) can wirelessly transmit and receive signals to and from the remote control device (200) via the RF module (412). In addition, the user input interface unit (150) can receive signals transmitted by the remote control device (200) according to the IR communication standard via the IR module (413).

[0176] The coordinate value calculation unit (415) can calculate the coordinate values ​​(x, y) of the pointer (205) to be displayed on the display (170) by correcting hand shake or error from a signal corresponding to the operation of the remote control device (200) received through the wireless communication unit (151).

[0177] A transmission signal of a remote control device (200) input to a video display device (100) through a user input interface unit (150) is transmitted to a signal processing device (170) of the video display device (100). The signal processing device (170) can determine information about the operation and key operation of the remote control device (200) from the signal transmitted from the remote control device (200) and control the video display device (100) in response thereto.

[0178] As another example, the remote control device (200) can calculate pointer coordinate values ​​corresponding to the operation and output them to the user input interface unit (150) of the image display device (100). In this case, the user input interface unit (150) of the image display device (100) can transmit information about the received pointer coordinate values ​​to the signal processing device (170) without a separate hand shake or error correction process.

[0179] In addition, as another example, the coordinate value calculation unit (415) may be provided inside the signal processing device (170) rather than the user input interface unit (150), unlike in the drawing.

[0180] Figure 5 is an example of an internal block diagram of the display of Figure 2.

[0181] Referring to the drawing, the display (180) based on an organic light-emitting panel may include an organic light-emitting panel (210), a first interface unit (230), a second interface unit (231), a timing controller (232), a gate driver unit (234), a data driver unit (236), a memory (240), a processor (270), a power supply unit (290), a current detector unit (510), etc.

[0182] The display (180) receives a video signal (Vd), a first DC voltage (V1), and a second DC voltage (V2), and can display a predetermined image based on the video signal (Vd).

[0183] Meanwhile, the first interface unit (230) within the display (180) can receive a video signal (Vd) and a first DC voltage (V1) from the signal processing device (170).

[0184] Here, the first DC voltage (V1) can be used for the operation of the power supply (290) and the timing controller (232) within the display (180).

[0185] Next, the second interface unit (231) can receive a second DC voltage (V2) from an external power supply unit (190). Meanwhile, the second DC voltage (V2) can be input to a data driving unit (236) within the display (180).

[0186] The timing controller (232) can output a data driving signal (Sda) and a gate driving signal (Sga) based on a video signal (Vd).

[0187] For example, when the first interface unit (230) converts an input image signal (Vd) and outputs a converted image signal (va1), the timing controller (232) can output a data driving signal (Sda) and a gate driving signal (Sga) based on the converted image signal (va1).

[0188] The timing controller (232) can receive, in addition to the video signal (Vd) from the signal processing device (170), a control signal, a vertical synchronization signal (Vsync), etc.

[0189] In addition, the timing controller (232) can output a gate drive signal (Sga) for the operation of the gate drive unit (234) and a data drive signal (Sda) for the operation of the data drive unit (236) based on a control signal, a vertical synchronization signal (Vsync), etc., in addition to a video signal (Vd).

[0190] The data driving signal (Sda) at this time may be a data driving signal for driving RGBW subpixels when the panel (210) has RGBW subpixels.

[0191] Meanwhile, the timing controller (232) can further output a control signal (Cs) to the gate driver (234).

[0192] The gate driving unit (234) and the data driving unit (236) supply a scan signal and an image signal to the organic light-emitting panel (210) through the gate line (GL) and the data line (DL), respectively, in accordance with the gate driving signal (Sga) and the data driving signal (Sda) from the timing controller (232). Accordingly, the organic light-emitting panel (210) displays a predetermined image.

[0193] Meanwhile, the organic light-emitting panel (210) may include an organic light-emitting layer, and in order to display an image, a plurality of gate lines (GL) and data lines (DL) may be arranged in a matrix form to cross each pixel corresponding to the organic light-emitting layer.

[0194] Meanwhile, the data driving unit (236) can output a data signal to the organic light-emitting panel (210) based on the second DC voltage (V2) from the second interface unit (231).

[0195] The power supply unit (290) can supply various power sources to the gate driver unit (234), the data driver unit (236), the timing controller (232), etc.

[0196] The current detection unit (510) can detect the current flowing in the subpixel of the organic light-emitting panel (210). The detected current can be input to a processor (270) or the like for cumulative current calculation.

[0197] The processor (270) can perform various controls within the display (180). For example, it can control the gate driver (234), the data driver (236), the timing controller (232), etc.

[0198] Meanwhile, the processor (270) can receive information on current flowing in the subpixel of the organic light-emitting panel (210) from the current detection unit (510).

[0199] FIGS. 6A and 6B are drawings for reference in the description of the organic light-emitting panel of FIG. 5.

[0200] First, FIG. 6a is a drawing showing pixels within an organic light-emitting panel (210).

[0201] Referring to the drawing, the organic light-emitting panel (210) may have a plurality of scan lines (Scan 1 to Scan n) and a plurality of data lines (R1, G1, B1, W1 to Rm, Gm, Bm, Wm) intersecting therewith.

[0202] Meanwhile, a pixel (subpixel) is defined in the intersection area of ​​the scan line and the data line within the organic light-emitting panel (210). In the drawing, a pixel having RGBW subpixels (SR1, SG1, SB1, SW1) is illustrated.

[0203] FIG. 6b illustrates the circuit of one sub-pixel within the pixel of the organic light-emitting panel of FIG. 6a.

[0204] Referring to the drawing, the organic light-emitting sub-pixel circuit (CRTm) may be an active type and include a scan switching element (SW1), a storage capacitor (Cst), a driving switching element (SW2), and an organic light-emitting layer (OLED).

[0205] The scan switching element (SW1) is turned on according to an input scan signal (Vdscan) by connecting a scan line to the gate terminal. When turned on, the input data signal (Vdata) is transmitted to the gate terminal of the driving switching element (SW2) or one end of the storage capacitor (Cst).

[0206] The storage capacitor (Cst) is formed between the gate terminal and the source terminal of the driving switching element (SW2), and stores a predetermined difference between the data signal level transmitted to one end of the storage capacitor (Cst) and the DC voltage (Vdd) level transmitted to the other end of the storage capacitor (Cst).

[0207] For example, if the data signal has different levels according to the PAM (Plus Amplitude Modulation) method, the power level stored in the storage capacitor (Cst) changes depending on the level difference of the data signal (Vdata).

[0208] As another example, when the data signal has different pulse widths according to the Pulse Width Modulation (PWM) method, the power level stored in the storage capacitor (Cst) changes depending on the difference in the pulse width of the data signal (Vdata).

[0209] The driving switching element (SW2) is turned on according to the power level stored in the storage capacitor (Cst). When the driving switching element (SW2) is turned on, a driving current (IOLED) proportional to the stored power level flows to the organic light-emitting layer (OLED). Accordingly, the organic light-emitting layer (OLED) performs a light-emitting operation.

[0210] The organic light-emitting layer (OLED) includes an RGBW emission layer (EML) corresponding to a subpixel, and may include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), and may also include a hole blocking layer.

[0211] Meanwhile, subpixels all emit white light from the organic light-emitting diode (OLED), but separate color filters are provided for green, red, and blue subpixels to implement the colors. That is, green, red, and blue subpixels each additionally have green, red, and blue color filters. On the other hand, white subpixels emit white light, so separate color filters are not required.

[0212] Meanwhile, in the drawing, a case in which a p-type MOSFET is used as the scan switching element (SW1) and the driving switching element (SW2) is exemplified, but an n-type MOSFET, or other switching elements such as a JFET, IGBT, or SIC may also be used.

[0213] Meanwhile, a pixel can continue to emit light in an organic light-emitting layer (OLED) after a scan signal is applied during a unit display period, specifically during a unit frame.

[0214] FIG. 7 is an example of an internal block diagram of a power supply unit according to an embodiment of the present disclosure.

[0215] Referring to the drawings, an image display device (100) according to an embodiment of the present disclosure includes a panel (210), a signal processing device (170) that processes an input image to output an image signal, and a timing controller (232) that drives the panel (210) based on an image signal from the signal processing device (170).

[0216] The signal processing device (170) can transmit an image signal based on R, G, B data to the timing controller (232) based on a predetermined transmission data format.

[0217] To this end, the signal processing device (170) may be equipped with a data output unit (1018) that outputs an image signal based on R, G, B data based on a predetermined transmission data format.

[0218] The transmission data format at this time may be Vx1 format, as shown in the drawing, but is not limited to this and various modifications are possible.

[0219] Meanwhile, the timing controller (232) can output an image signal based on R, G, B data and a timing clock (Timing CLK) signal based on a signal received from the signal processing device (170).

[0220] Meanwhile, the timing controller (232) can transmit current information output from the timing controller (232) or current information flowing through the panel (210) to the signal processing device (170) via I2C communication.

[0221] Meanwhile, the panel (210) and the timing controller (232) may be provided within the display (180).

[0222] Meanwhile, the image display device (100) according to the embodiment of the present disclosure includes a power supply unit (190) that supplies a display driving voltage (EVDD) to the display (180).

[0223] For example, the power supply unit (190) may include an AC / DC converter (not shown) that converts input AC voltage into DC voltage, and a DC / DC converter (not shown) that converts the level of the DC voltage from the AC / DC converter to output a display driving voltage (EVDD).

[0224] Meanwhile, if the display (180) is an organic light-emitting panel, the display driving voltage (EVDD) may be a pixel driving voltage of an organic light-emitting pixel.

[0225] Meanwhile, the power supply unit (190) may further include a second dc / dc converter (not shown) that converts the level of the direct current voltage from the ac / dc converter and outputs a gate driving voltage (VDD).

[0226] The gate driving voltage (VDD) at this time may be lower than the display driving voltage (EVDD) and may be input to the timing controller (232) or the driving driver (235).

[0227] For example, the voltage level of the display driving voltage (EVDD) may be approximately 24 V, and the gate driving voltage (VDD) may be approximately 12 V.

[0228] Meanwhile, the display (180) may further include a driving driver (235) that drives the panel (210) based on an image signal based on R, G, B data and a timing clock (Timing CLK) signal from a timing controller (232).

[0229] The driving driver (235) may include a gate driving unit (234) and a data driving unit (236) of FIG. 5.

[0230] Meanwhile, a signal processing device (170) according to one embodiment of the present disclosure outputs a data enable signal (DE) when transmitting an image signal based on R, G, B data.

[0231] The data enable signal (DE) is divided into an active period (HA) and a blank period (HB), and the signal processing device (170) can output a zero signal including R, G, and B data in the image signal to the timing controller (232) in response to the length of the active period (HA).

[0232] Meanwhile, when transmitting a video signal based on R, G, B data, an increase in the data bit of the R, G, B data is required due to an increase in the frequency of the vertical synchronization signal (Vsync) or an increase in peak luminance.

[0233] Accordingly, in this disclosure, a method is proposed to improve the gradation expressiveness when displaying an image by enabling upward transmission of data bits without expanding the transmission lane between a signal processing device (170) and a timing controller (232).

[0234] To this end, a signal processing device (170) according to one embodiment of the present disclosure outputs a data enable signal (DE) divided into an active period (HA) and a blank period (HB), and varies the length of the active period (HA) or the length of the blank period (HB) when the data bit of the image signal varies. Accordingly, it is possible to improve the gradation expressiveness during image display. In particular, it is possible to improve the gradation expressiveness during image display without varying the transmission lane of the image signal.

[0235] In particular, a signal processing device (170) according to one embodiment of the present disclosure varies the length of an active period (HA) or a blank period (HB) within a data enable signal (DE) when an upward movement of a data bit is required.

[0236] For example, the signal processing device (170) can output a first data enable signal (DE) corresponding to the first active period (HA) and the first blank period (HB) when the image display mode is the normal mode, and can output a second data enable signal (DE) corresponding to the second active period (HA) and the second blank period (HB) when the image display mode is the game mode.

[0237] At this time, the length of the second active section (HA) may be greater than the length of the first active section (HA), and the length of the second blank section (HB) may be less than the length of the first blank section (HB). Accordingly, by varying the data enable signal (DE) based on the image display mode, it is possible to improve the gradation expressiveness during image display.

[0238] As another example, the signal processing device (170) may output a first data enable signal (DE) corresponding to a first active period (HA) and a first blank period (HB) for displaying an image at a first level of peak luminance on the panel (210), and may output a second data enable signal (DE) corresponding to a second active period (HA) and a second blank period (HB) for displaying an image at a second level of peak luminance greater than the first level on the panel (210).

[0239] At this time, the length of the second active section (HA) may be greater than the length of the first active section (HA), and the length of the second blank section (HB) may be less than the length of the first blank section (HB). Accordingly, by varying the data enable signal (DE), the gradation expressiveness during image display can be improved.

[0240] As another example, the signal processing device (170) may output a first data enable signal (DE) corresponding to a first active period (HA) and a first blank period (HB) when the peak luminance level of the R, G, B data to be output to the timing controller (232) is a first level, and may output a second data enable signal (DE) corresponding to a second active period (HA) and a second blank period (HB) when the peak luminance level of the R, G, B data to be output to the timing controller (232) is a second level greater than the first level. Accordingly, by varying the data enable signal (DE), it is possible to improve the gradation expressiveness when displaying an image.

[0241] Meanwhile, the signal processing device (170) can control the length of the active period (HA) of the data enable signal (DE) to increase or the length of the blank period (HB) to decrease as the frequency of the vertical synchronization signal increases. Accordingly, by varying the data enable signal (DE) based on the vertical synchronization signal frequency, it is possible to improve the gradation expressiveness during image display.

[0242] Meanwhile, the signal processing device (170) can control the length of the active section (HA) of the data enable signal (DE) to increase or the length of the blank section (HB) to decrease as the data bit of the image signal increases. Accordingly, by varying the data enable signal (DE), it is possible to improve the gradation expressiveness when displaying an image.

[0243] Meanwhile, the signal processing device (170) can control to perform a data enable variable mode when an upward movement of data bits is required, and can control to perform a data enable fixed mode when an upward movement of data bits is not required.

[0244] For example, the signal processing device (170) can vary the length of the active interval (HA) or the length of the blank interval (HB) in the case of the data enable variable mode. Accordingly, by varying the data enable signal (DE) according to the data enable variable mode, it is possible to improve the gradation expressiveness when displaying an image.

[0245] Meanwhile, the signal processing device (170) can control the data bits of R, G, and B data to increase as the length of the active section (HA) of the data enable signal (DE) increases in the data enable variable mode. Accordingly, the gradation expressiveness during image display can be improved.

[0246] Meanwhile, the signal processing device (170) can fix the length of the active interval (HA) and the length of the blank interval (HB) when in data enable fixed mode. Accordingly, it can operate in data enable fixed mode.

[0247] FIG. 8 is an example of an internal block diagram of a signal processing device according to one embodiment of the present disclosure.

[0248] Referring to the drawing, a signal processing device (170) according to an embodiment of the present disclosure may include an input interface (IIP) that receives an image signal from the outside, an image processing unit (1010) that generates image frame data (ImgL) based on the image signal, and an output interface (OIP) that outputs image frame data (ImgL) based on R, G, B data.

[0249] Accordingly, the timing controller (232) can output R, G, B data and a clock signal, etc. for driving the panel (210), based on the received R, G, B data-based image frame data (ImgL).

[0250] Meanwhile, the output interface (OIP) of FIG. 8 can correspond to the data output unit (1018) of FIG. 7.

[0251] Meanwhile, the input interface (IIP) can receive video signals from a computer (PC), a mobile terminal (600), a set-top box (STB), a game console (GSB), a server (SVR), etc. of FIG. 1.

[0252] Meanwhile, the signal processing device (170) according to the embodiment of the present disclosure may further include a preprocessing unit (515) that performs signal processing such as noise reduction, noise removal, and HDR signal processing on an image signal from an input interface (IIP).

[0253] Meanwhile, the preprocessing unit (515) performs signal processing on the image signal from the input interface (IIP).

[0254] For example, the preprocessing unit (515) can perform signal processing such as noise removal without separate decoding processing when the received image signal is a decoded image signal.

[0255] As another example, if the received video signal is a video signal encoded according to a video compression standard, the preprocessing unit (515) may perform decoding in accordance with the video compression standard after signal processing such as noise removal.

[0256] Meanwhile, the preprocessing unit (515) can perform HDR signal processing when the received image signal is an HDR image signal. To this end, the preprocessing unit (515) may be equipped with an HDR processing unit (705).

[0257] Meanwhile, the HDR processing unit (705) can receive a video signal and perform high dynamic range (HDR) processing on the input video signal.

[0258] For example, the HDR processing unit (705) can convert a standard dynamic range (SDR) video signal into an HDR video signal.

[0259] As another example, the HDR processing unit (705) can receive a video signal and perform grayscale processing for a high dynamic range on the input video signal.

[0260] Meanwhile, the HDR processing unit (705) can bypass grayscale conversion when the input image signal is an SDR image signal, and perform grayscale conversion when the input image signal is an HDR image signal.

[0261] Meanwhile, a signal processing device (170) according to one embodiment of the present disclosure may further include a memory (540) that stores frame data for image processing of the image processing unit (1010). Alternatively, the memory (540) may be provided within the image processing unit (1010), as shown in the drawing.

[0262] That is, the image processing unit (1010) in the signal processing device (170) according to one embodiment of the present disclosure may include a memory (540) that stores frame data for image processing.

[0263] The image processing unit (1010) can generate and output image frame data (ImgL) based on the image signal processed in the preprocessing unit (515).

[0264] To this end, the image processing unit (1010) may include a scaler (335) that performs scaling of the image signal to match the resolution of the panel, etc., a frame rate converter (350) that operates to vary the frame rate, and an image processing unit (635a) that performs image quality processing.

[0265] Meanwhile, the image processing unit (1010) may further include a memory (540) that stores frame data for frame rate variation in the frame rate converter (350).

[0266] Meanwhile, the image quality processing unit (635a) can perform image quality processing on the image frame data (ImgL).

[0267] For example, the image quality processing unit (635a) can perform signal processing such as noise reduction, three-dimensional effect enhancement signal processing, brightness amplification, and brightness expansion.

[0268] Meanwhile, the output interface (OIP) can receive image frame data (ImgL) from the image quality processing unit (635a).

[0269] Meanwhile, the output interface (OIP) can output image frame data (ImgL) based on R, G, B data.

[0270] Meanwhile, the output interface (OIP) may include a first output terminal (PNa) for transmitting a vertical synchronization signal (Vsync), a second output terminal (PNb) for transmitting a horizontal synchronization signal (Hsync), a third output terminal (PNc) for transmitting a video data signal (Vdata) based on R, G, B data, and a fourth output terminal (PNd) for transmitting a data enable signal (DE).

[0271] Meanwhile, the data enable signal (DE) can be divided into an active period (HA) and a blank period (HB).

[0272] The timing controller (232) can receive an image data signal (Vdata) output from the third output terminal (PNc) in response to the active period (HA) of the data enable signal (DE).

[0273] Meanwhile, the output interface (OIP) within the signal processing device (170) can vary the length of the active interval (HA) or the length of the blank interval (HB) when the data bit of the image signal varies. Accordingly, the gradation expressiveness during image display can be improved. In particular, the gradation expressiveness during image display can be improved without varying the transmission lane of the image signal.

[0274] For example, the output interface (OIP) within the signal processing device (170) can output a first data enable signal (DE) corresponding to the first active period (HA) and the first blank period (HB) when the image display mode is the normal mode, and can output a second data enable signal (DE) corresponding to the second active period (HA) and the second blank period (HB) when the image display mode is the game mode.

[0275] At this time, the length of the second active section (HA) may be greater than the length of the first active section (HA), and the length of the second blank section (HB) may be less than the length of the first blank section (HB). Accordingly, by varying the data enable signal (DE) based on the image display mode, it is possible to improve the gradation expressiveness during image display.

[0276] As another example, the output interface (OIP) within the signal processing device (170) may output a first data enable signal (DE) corresponding to a first active period (HA) and a first blank period (HB) for displaying an image at a first level of peak luminance on the panel (210), and may output a second data enable signal (DE) corresponding to a second active period (HA) and a second blank period (HB) for displaying an image at a second level of peak luminance greater than the first level on the panel (210).

[0277] At this time, the length of the second active section (HA) may be greater than the length of the first active section (HA), and the length of the second blank section (HB) may be less than the length of the first blank section (HB). Accordingly, by varying the data enable signal (DE), the gradation expressiveness during image display can be improved.

[0278] As another example, the output interface (OIP) within the signal processing device (170) may output a first data enable signal (DE) corresponding to a first active period (HA) and a first blank period (HB) when the peak luminance level of R, G, B data to be output to the timing controller (232) is a first level, and may output a second data enable signal (DE) corresponding to a second active period (HA) and a second blank period (HB) when the peak luminance level of R, G, B data to be output to the timing controller (232) is a second level greater than the first level. Accordingly, by varying the data enable signal (DE), it is possible to improve the gradation expressiveness during image display.

[0279] Meanwhile, the output interface (OIP) within the signal processing device (170) can be controlled so that as the frequency of the vertical synchronization signal increases, the length of the active period (HA) of the data enable signal (DE) increases or the length of the blank period (HB) decreases. Accordingly, by varying the data enable signal (DE) based on the vertical synchronization signal frequency, it is possible to improve the gradation expressiveness during image display.

[0280] Meanwhile, the output interface (OIP) within the signal processing device (170) can be controlled so that as the data bit of the image signal increases, the length of the active period (HA) of the data enable signal (DE) increases or the length of the blank period (HB) decreases. Accordingly, by varying the data enable signal (DE), the gradation expressiveness during image display can be improved.

[0281] Meanwhile, the output interface (OIP) within the signal processing device (170) can be controlled to perform a data enable variable mode when an upward movement of data bits is required, and to perform a data enable fixed mode when an upward movement of data bits is not required.

[0282] For example, the output interface (OIP) within the signal processing device (170) can vary the length of the active interval (HA) or the length of the blank interval (HB) in the case of the data enable variable mode. Accordingly, by varying the data enable signal (DE) according to the data enable variable mode, it is possible to improve the gradation expressiveness during image display.

[0283] Meanwhile, the output interface (OIP) within the signal processing device (170) can be controlled so that, in the data enable variable mode, the data bits of the R, G, and B data increase as the length of the active period (HA) of the data enable signal (DE) increases. Accordingly, the gradation expressiveness during image display can be improved.

[0284] Meanwhile, the output interface (OIP) within the signal processing device (170) can fix the length of the active interval (HA) and the length of the blank interval (HB) in the case of data enable fixed mode. Accordingly, it can operate in the data enable fixed mode.

[0285] FIGS. 9A to 9C are drawings for reference in explaining the operation of a video display device related to the present disclosure.

[0286] Figure 9a illustrates various peak luminances displayed on the display.

[0287] Referring to the drawing, (a) of FIG. 9a exemplifies that the displayable peak luminance of the display or the peak luminance of the image signal is 500 nit.

[0288] Meanwhile, when the displayable peak luminance of the display or the peak luminance of the image signal is 500 nit, the transmission bits of the R, G, B data transmitted from the signal processing device (170) to the timing controller (232) may be 10 bits.

[0289] Meanwhile, if the transmission bit is 10 bits, the luminance difference (ΔLa) of 1 gray level can be approximately 0.5 nit.

[0290] Figure 9a (b) illustrates that the displayable peak luminance of the display or the peak luminance of the image signal is 3000 nit.

[0291] Meanwhile, when the displayable peak luminance of the display or the peak luminance of the image signal is 3000 nit, the transmission bits of the R, G, B data transmitted from the signal processing device (170) to the timing controller (232) may be 10 to 12 bits.

[0292] Meanwhile, when the transmission bit is 10 bits, the luminance difference (ΔLb) of one gray level can be approximately 3 nits, when the transmission bit is 11 bits, the luminance difference (ΔLc) of one gray level can be approximately 1.5 nits, and when the transmission bit is 12 bits, the luminance difference (ΔLd) of one gray level can be approximately 0.75 nits.

[0293] According to this, as the transmission bit increases, the luminance difference of one gray level becomes smaller.

[0294] For example, if the data transmission format is Vx1 format, the transmission lane is 16 lanes, the frequency of the vertical synchronization signal is 120 Hz, and a video signal with a resolution of 4K (3840x2160) is transmitted in 5 byte mode, the maximum transmission bit can be 12 bits.

[0295] As another example, if the data transmission format is Vx1 format, the transmission lane is 16 lanes, the frequency of the vertical synchronization signal is 144 Hz, which is greater than 120 Hz, and a video signal with a resolution of 4K (3840x2160) is transmitted in 4 byte mode, the maximum transmission bit can be 10 bits.

[0296] Figure 9b illustrates 4 byte mode and 5 byte mode of Vx1 format.

[0297] Referring to the drawing, according to the 4 byte mode of the Vx1 format, R, G, B data can be allocated within 8*4= 32 bits.

[0298] That is, approximately 10 bits of data can be allocated to each R, G, B data by 32 / 3.

[0299] In the drawing, R[2]~R[9] are placed in Byte0, G[2]~G[9] are placed in Byte1, B[2]~B[9] are placed in Byte2, and R[0],R[1],G[0],G[1],B[0],B[1] are placed in Byte3.

[0300] That is, in the drawing, 10-bit R, G, B data is exemplified by R[0]~R[9], G[0]~G[9], B[0]~B[9] in 4-byte mode.

[0301] Meanwhile, according to the 5 byte mode of the Vx1 format, R, G, B data can be allocated within 8*5= 40 bits.

[0302] That is, up to 13 bits of data can be allocated to each R, G, B data by 40 / 3.

[0303] In the drawing, R[4]~R

[0011] are placed in Byte0, G[4]~G

[0011] are placed in Byte1, B[4]~B

[0011] are placed in Byte2, R[2],R[3],G[2],G[3],B[2],B[3] are placed in Byte3, and R[0],R[1],G[0],G[1],B[0],B[1] are placed in Byte4.

[0304] That is, in the drawing, 12-bit R, G, B data is exemplified by R[0]~R

[0011] , G[0]~G

[0011] , B[0]~B

[0011] in 5-byte mode.

[0305] Meanwhile, by using unallocated bits within some bytes in the drawing, it is possible to express up to R

[0012] , G

[0012] , B

[0012] , and accordingly, up to 13 bits of R, G, B data can be transmitted in 5 byte mode.

[0306] However, in 5 byte mode, the maximum 13-bit R, G, B data transmission is possible only when the vertical synchronization signal frequency is 120 Hz, and cannot be applied when the vertical synchronization signal frequency is 144 Hz. This is described with reference to Fig. 9c.

[0307] Figure 9c illustrates 4-byte mode and 5-byte mode when the frequency of the vertical synchronization signal is 120 Hz and 144 Hz, respectively.

[0308] In the 4-byte mode in the drawing, the data transmission bits can correspond to 10 bits, and in the 5-byte mode, the data transmission bits can correspond to 12 bits.

[0309] Referring to the drawing, the frequency of the vertical synchronization signal is 120 Hz, and in 4 byte mode, the pixel clock is 74.25 MHz, the operating frequency of Vx1 is 2.97 GHz, the active period, blank period, and total period of Horizontal can be 240, 35, and 275 clocks, respectively, and the active period, blank period, and total period of Vertical can be 2160, 90, and 2250 clocks, respectively.

[0310] Next, when the frequency of the vertical synchronization signal is 120Hz and in 5 byte mode, the pixel clock is 74.25MHz, the operating frequency of Vx1 is 3.712GHz which is higher than 2.97GHz, the active period, blank period, and total period of Horizontal can be 240, 35, and 275 clocks, respectively, and the active period, blank period, and total period of Vertical can be 2160, 90, and 2250 clocks, respectively.

[0311] Next, if the frequency of the vertical synchronization signal is 144 Hz and in 4 byte mode, the pixel clock is 89.1 MHz, the operating frequency of Vx1 is 3.564 GHz, the active period, blank period, and total period of Horizontal can be 240, 35, and 275 clocks, respectively, and the active period, blank period, and total period of Vertical can be 2160, 90, and 2250 clocks, respectively.

[0312] Next, when the frequency of the vertical synchronization signal is 144 Hz and in 5 byte mode, the pixel clock is 89.1 MHz, the operating frequency of Vx1 is 4.455 GHz, which is higher than 3.564 GHz, the active period, blank period, and total period of Horizontal can be 240, 35, and 275 clocks, respectively, and the active period, blank period, and total period of Vertical can be 2160, 90, and 2250 clocks, respectively.

[0313] Meanwhile, the upper limit of the operating frequency of the Vx1 transmission format according to the standard may be 4 GHz. Accordingly, when the frequency of the vertical synchronization signal is 144 Hz, 4-byte mode is possible, but 5-byte mode may not be possible.

[0314] Therefore, if the frequency of the vertical synchronization signal is 144 Hz, 5 Byte mode may only be possible in 4 byte mode.

[0315] That is, if the frequency of the vertical synchronization signal is 144 Hz, the data transmission bits can only be 10 bits, not 12 bits.

[0316] In such cases, there is a problem of deterioration in gradation expressivity as the peak luminance of the display increases or the peak luminance of the image signal increases.

[0317] Accordingly, in this disclosure, a method for improving the gradation expressivity of image display without changing the transmission lane of the image signal is proposed. This is described with reference to FIG. 10a and below.

[0318] FIG. 10a is a flowchart showing an example of an operation method of an image display device according to an embodiment of the present disclosure.

[0319] Referring to the drawing, a signal processing device (170) according to one embodiment of the present disclosure determines whether data bit variation is required when transmitting an image signal including R, G, and B data to a timing controller (232) (S1010), and if so, varies the length of an active period (HA) or a blank period (HB) of a data enable signal (DE) (S1020).

[0320] Meanwhile, the signal processing device (170) may determine that data bit variation is necessary when the peak luminance of the image signal is variable and is greater than the reference peak luminance (e.g., xxxx nit).

[0321] Meanwhile, the signal processing device (170) can determine that data bit variation is required when the frequency of the vertical synchronization signal of the image signal varies and increases.

[0322] Specifically, when the frequency of the vertical synchronization signal of the video signal varies from 60 Hz to 120 Hz or from 120 Hz to 1440 Hz, it can be determined that data bit variation is required.

[0323] Meanwhile, the signal processing device (170) may determine that data bit variation is required when the image display mode changes from normal mode to game mode.

[0324] Meanwhile, the signal processing device (170) can enter a data enable variable mode and vary the length of the active interval (HA) or the blank interval (HB) within the data enable signal (DE) when data bit variation is required. Accordingly, by varying the data enable signal (DE) according to the data enable variable mode, it is possible to improve the gradation expressiveness during image display.

[0325] Meanwhile, if the signal processing device (170) determines in step 1010 (S1010) that data bit variation is not necessary, it can enter a data enable fixed mode and fix the length of the active interval (HA) and the length of the blank interval (HB). Accordingly, it can operate in the data enable fixed mode.

[0326] For example, if it is determined that data bit variation is not necessary, the signal processing device (170) may enter a data enable fixed mode and control the 4 byte mode or 5 byte mode of 120Hx to be performed, or the 4 byte mode of 144Hx to be performed, as shown in FIG. 9c.

[0327] FIG. 10b is a flowchart showing another example of an operating method of an image display device according to an embodiment of the present disclosure.

[0328] Referring to the drawing, a signal processing device (170) according to one embodiment of the present disclosure can determine whether the image display mode is a normal mode (S1042), and if so, output a first data enable signal (DE) corresponding to the first active period (HA) and the first blank period (HB) (S1045).

[0329] Next, the signal processing device (170) determines whether the image display mode is a game mode if it is not a normal mode (S1047), and if so, outputs a second data enable signal (DE) corresponding to the second active period (HA) and the second blank period (HB) (S1049).

[0330] At this time, the length of the second active section (HA) may be greater than the length of the first active section (HA), and the length of the second blank section (HB) may be less than the length of the first blank section (HB). Accordingly, by varying the data enable signal (DE) based on the image display mode, it is possible to improve the gradation expressiveness during image display.

[0331] Meanwhile, the signal processing device (170) can control the data bits of the R, G, B data output in the game mode to be larger than the data bits of the R, G, B data output in the normal mode. Accordingly, the gradation expressiveness in the game mode can be improved compared to the normal mode.

[0332] Meanwhile, the signal processing device (170) can output a second data enable signal (DE) corresponding to the second active period (HA) and the second blank period (HB) when the image display mode is a game mode and the vertical synchronization signal frequency corresponds to the frequency of the first vertical synchronization signal.

[0333] Meanwhile, when the video display mode is a game mode and the vertical synchronization signal frequency corresponds to a frequency of a second vertical synchronization signal greater than the frequency of the first vertical synchronization signal, a third data enable signal (DE) corresponding to the third active period (HA) and the third blank period (HB) can be output.

[0334] At this time, the length of the third active section (HA) may be greater than the length of the second active section (HA), and the length of the third blank section (HB) may be less than the length of the second blank section (HB). Accordingly, by varying the data enable signal (DE) based on the image display mode, it is possible to improve the gradation expressiveness during image display.

[0335] FIG. 10c is a flowchart showing another example of an operating method of an image display device according to an embodiment of the present disclosure.

[0336] Referring to the drawing, a signal processing device (170) according to one embodiment of the present disclosure, when transmitting an image signal including R, G, B data to a timing controller (232), determines whether the frequency of a vertical synchronization signal of the image signal is the frequency of a first vertical synchronization signal (S1052), and if so, sets the length of an active period (HA) or a blank period (HB) in which a data bit of the image signal corresponds to one of a first number of bits (S1054).

[0337] And, the signal processing device (170) according to one embodiment of the present disclosure can output a first data enable signal (DE) corresponding to the length of the active section (HA) or the length of the blank section (HB) set in step 1054 (S1055).

[0338] That is, the signal processing device (170) outputs a first data enable signal (DE) corresponding to the frequency of the first vertical synchronization signal, and when the data bit of the image signal is any one of the first bit, the second bit, the third bit, the fourth bit, and the fifth bit, the length of the active period (HA) or the length of the blank period (HB) corresponding to the corresponding bit can be set.

[0339] The frequency of the first vertical synchronization signal at this time may be 120 Hz, the first number of bits may be 5 bits, and the first bit, the second bit, the third bit, the fourth bit, and the fifth bit may be 10 bits, 11 bits, 12 bits, 13 bits, and 14 bits, respectively.

[0340] That is, the signal processing device (170) according to one embodiment of the present disclosure can output the first data enable signal (DE) by varying the length of the active period (HA) or the length of the blank period (HB) when the frequency of the vertical synchronization signal of the image signal is 120 Hz.

[0341] At this time, the first data enable signal (DE) may be a data enable signal corresponding to any one of 10 bits, 11 bits, 12 bits, 13 bits, and 14 bits.

[0342] Accordingly, by varying the data enable signal (DE) based on the vertical synchronization signal frequency, it is possible to improve the gradation expression when displaying an image.

[0343] Meanwhile, in step 1052 (S1052), the signal processing device (170) determines whether the frequency of the second vertical synchronization signal is higher than the frequency of the first vertical synchronization signal if it is not the frequency of the first vertical synchronization signal (S1053), and if so, sets the length of the active interval (HA) or the length of the blank interval (HB) corresponding to any one of the second number of bits smaller than the first number (S1057).

[0344] And, the signal processing device (170) according to one embodiment of the present disclosure can output a second data enable signal (DE) corresponding to the length of the active section (HA) or the length of the blank section (HB) set in step 1057 (S1059).

[0345] That is, the signal processing device (170) outputs a second data enable signal (DE) corresponding to the frequency of the second vertical synchronization signal, and when the data bit of the image signal is any one of the first bit, the second bit, and the third bit, the length of the active period (HA) or the length of the blank period (HB) corresponding to the corresponding bit can be set.

[0346] The frequency of the second vertical synchronization signal at this time may be 144 Hz, the second number of bits may be 3 bits, and the first bit, the second bit, and the third bit may be 10 bits, 11 bits, and 12 bits, respectively.

[0347] That is, the signal processing device (170) according to one embodiment of the present disclosure can output the second data enable signal (DE) by varying the length of the active period (HA) or the length of the blank period (HB) when the frequency of the vertical synchronization signal of the image signal is 144 Hz.

[0348] At this time, the second data enable signal (DE) may be a data enable signal corresponding to any one of 10 bits, 11 bits, and 12 bits.

[0349] Accordingly, by varying the data enable signal (DE) based on the vertical synchronization signal frequency, it is possible to improve the gradation expression when displaying an image.

[0350] FIG. 10d is a flowchart showing another example of an operating method of an image display device according to an embodiment of the present disclosure.

[0351] Referring to the drawing, a signal processing device (170) according to one embodiment of the present disclosure determines whether a data enable variable mode is required for data bit variation (S1005), and if so, determines whether data bit variation is required when transmitting an image signal including R, G, B data to a timing controller (232) (S1010), and if so, varies the length of an active period (HA) or a blank period (HB) of a data enable signal (DE) (S1020).

[0352] For example, the signal processing device (170) may determine that a data enable variable mode and data bit variable are required when the peak luminance of the image signal is variable and is greater than or equal to a reference peak luminance (e.g., xxxx nit).

[0353] Meanwhile, the signal processing device (170) may determine that a data enable variable mode and data bit variable mode are required when the frequency of the vertical synchronization signal of the image signal increases variably.

[0354] Meanwhile, the signal processing device (170) may determine that a data enable variable mode and a data bit variable mode are required when the image display mode is changed from a normal mode to a game mode.

[0355] Meanwhile, the signal processing device (170) can vary the length of the active period (HA) or the blank period (HB) within the data enable signal (DE) when the data enable variable mode and data bit variable are required. Accordingly, by varying the data enable signal (DE) according to the data enable variable mode, it is possible to improve the gradation expressiveness during image display.

[0356] Meanwhile, the signal processing device (170), in step 1005 (S1005), determines whether it is in data enable fixed mode if it is not in data enable variable mode (S1025), and if so, enters data enable fixed mode and can fix the length of the active section (HA) and the length of the blank section (HB) (S1028). Accordingly, it is possible to operate in data enable fixed mode.

[0357] For example, if it is determined that data bit variation is not necessary, the signal processing device (170) may enter a data enable fixed mode and control the 4 byte mode or 5 byte mode of 120Hx to be performed, or the 4 byte mode of 144Hx to be performed, as shown in FIG. 9c.

[0358] Figures 11a to 14b are drawings referenced in the description of Figures 10a to 10d.

[0359] First, FIGS. 11a and 11b illustrate examples of various transmission bits when the vertical synchronization signal frequency of the video signal is the frequency of the first vertical synchronization signal.

[0360] Figure 11a illustrates a plurality of transmission bits when the frequency of the first vertical synchronization signal is 120 Hz.

[0361] Referring to the drawing, the signal processing device (170) can control the transmission of data as one of 10 bits, 11 bits, 12 bits, 13 bits, and 14 bits when the frequency of the first vertical synchronization signal is 120 Hz.

[0362] For example, in the case where the signal processing device (170) sets the data transmission bit of the image signal to 10 bits, the pixel clock can be 89.1 MHz, the horizontal active section, blank section, and total section can be set to 240, 90, and 330 clocks, respectively, and the vertical active section, blank section, and total section can be set to 2160, 90, and 2250 clocks, respectively.

[0363] Meanwhile, in the case where the data transmission bit of the image signal is set to 11 bits, the signal processing device (170) may set the pixel clock to 89.1 MHz, the horizontal active section, blank section, and total section to 248, 82, and 330 clocks, respectively, and the vertical active section, blank section, and total section to 2160, 90, and 2250 clocks, respectively.

[0364] Meanwhile, in the case where the signal processing device (170) sets the data transmission bit of the image signal to 12 bits, the pixel clock can be 89.1 MHz, the horizontal active section, blank section, and total section can be set to 272, 58, and 330 clocks, respectively, and the vertical active section, blank section, and total section can be set to 2160, 90, and 2250 clocks, respectively.

[0365] Meanwhile, in the case where the signal processing device (170) sets the data transmission bit of the image signal to 13 bits, the pixel clock can be 89.1 MHz, the horizontal active section, blank section, and total section can be set to 296, 34, and 330 clocks, respectively, and the vertical active section, blank section, and total section can be set to 2160, 90, and 2250 clocks, respectively.

[0366] Meanwhile, in the case where the signal processing device (170) sets the data transmission bit of the image signal to 14 bits, the pixel clock can be 89.1 MHz, the horizontal active section, blank section, and total section can be set to 320, 10, and 330 clocks, respectively, and the vertical active section, blank section, and total section can be set to 2160, 90, and 2250 clocks, respectively.

[0367] That is, the signal processing device (170) can control the length of the active section (HA) of the data enable signal (DE) to increase or the length of the blank section (HB) to decrease as the data bit of the image signal increases.

[0368] For example, the signal processing device (170) can control the horizontal active period to increase by 8 clocks or 24 clocks and the blank period to decrease by 8 clocks or 24 clocks as the data bit of the image signal increases by 1 bit.

[0369] Meanwhile, unlike the drawing, the signal processing device (170) may set the pixel clock to 89.1 MHz, the horizontal active section, blank section, and total section to 328, 2, and 330 clocks, respectively, when the data transmission bit of the image signal is set to 15 bits, and the vertical active section, blank section, and total section may be set to 2160, 90, and 2250 clocks, respectively.

[0370] Figure 11b is a drawing referenced in the description of Figure 11a.

[0371] Referring to the drawing, when the frequency of the first vertical synchronization signal is 120 Hz, the signal processing device (170) can output a plurality of data enable signals (DEm) in which the horizontal active section or blank section is variable.

[0372] For example, when the signal processing device (170) sets the data transmission bit of the image signal to 10 bits, the horizontal active section, blank section, and total section can output a data enable signal (DE1) corresponding to 240, 90, and 330 clocks, respectively.

[0373] Accordingly, the timing controller (232) can extract R, G, B data from the image signal during a period of 240 clocks within the data enable signal (DE1).

[0374] As another example, when the signal processing device (170) sets the data transmission bit of the image signal to 11 bits, the active section, blank section, and total section of Horizontal can output a data enable signal (DE2) corresponding to 248, 82, and 330 clocks, respectively.

[0375] Accordingly, the timing controller (232) can extract R, G, B data from the image signal during a period of 248 clocks within the data enable signal (DE2).

[0376] As another example, when the signal processing device (170) sets the data transmission bit of the image signal to 12 bits, the horizontal active section, blank section, and total section can output a data enable signal (DE3) corresponding to 272, 58, and 330 clocks, respectively.

[0377] Accordingly, the timing controller (232) can extract R, G, B data from the image signal during a period of 272 clocks within the data enable signal (DE3).

[0378] As another example, when the signal processing device (170) sets the data transmission bit of the image signal to 13 bits, the active section, blank section, and total section of the horizontal can output a data enable signal (DE4) corresponding to 296, 34, and 330 clocks, respectively.

[0379] Accordingly, the timing controller (232) can extract R, G, B data from the image signal during a period of 296 clocks within the data enable signal (DE4).

[0380] As another example, when the signal processing device (170) sets the data transmission bit of the image signal to 14 bits, the active section, blank section, and total section of the horizontal can output a data enable signal (DE5) corresponding to 320, 10, and 330 clocks, respectively.

[0381] Accordingly, the timing controller (232) can extract R, G, B data from the image signal during a period of 320 clocks within the data enable signal (DE5).

[0382] Next, FIGS. 12a and 12b illustrate examples of various transmission bits when the vertical synchronization signal frequency of the video signal is the frequency of the second vertical synchronization signal.

[0383] Figure 12a illustrates multiple transmission bits when the frequency of the second vertical synchronization signal is 144 Hz.

[0384] Referring to the drawing, the signal processing device (170) can control the transmission of data as one of 10 bits, 11 bits, and 12 bits when the frequency of the second vertical synchronization signal is 144 Hz.

[0385] For example, in the case where the signal processing device (170) sets the data transmission bit of the image signal to 10 bits, the pixel clock can be 89.1 MHz, the horizontal active section, blank section, and total section can be set to 240, 35, and 275 clocks, respectively, and the vertical active section, blank section, and total section can be set to 2160, 90, and 2250 clocks, respectively.

[0386] Meanwhile, in the case where the data transmission bit of the image signal is set to 11 bits, the signal processing device (170) may set the pixel clock to 89.1 MHz, the horizontal active section, blank section, and total section to 248, 27, and 275 clocks, respectively, and the vertical active section, blank section, and total section to 2160, 90, and 2250 clocks, respectively.

[0387] Meanwhile, in the case where the signal processing device (170) sets the data transmission bit of the image signal to 12 bits, the pixel clock can be 89.1 MHz, the horizontal active section, blank section, and total section can be set to 272, 3, and 275 clocks, respectively, and the vertical active section, blank section, and total section can be set to 2160, 90, and 2250 clocks, respectively.

[0388] That is, the signal processing device (170) can control the length of the active section (HA) of the data enable signal (DE) to increase or the length of the blank section (HB) to decrease as the data bit of the image signal increases.

[0389] For example, the signal processing device (170) can control the horizontal active period to increase by 8 clocks or 24 clocks and the blank period to decrease by 8 clocks or 24 clocks as the data bit of the image signal increases by 1 bit.

[0390] Figure 12b is a drawing referenced in the description of Figure 12a.

[0391] Referring to the drawing, when the frequency of the second vertical synchronization signal is 144 Hz, the signal processing device (170) can output a plurality of data enable signals (DEn) in which the horizontal active section or blank section is variable.

[0392] For example, when the signal processing device (170) sets the data transmission bit of the image signal to 10 bits, the horizontal active section, blank section, and total section can output a data enable signal (DE1) corresponding to 240, 35, and 275 clocks, respectively.

[0393] Accordingly, the timing controller (232) can extract R, G, B data from the image signal during a period of 240 clocks within the data enable signal (DE1).

[0394] As another example, when the signal processing device (170) sets the data transmission bit of the image signal to 11 bits, the active section, blank section, and total section of Horizontal can output a data enable signal (DE2) corresponding to 248, 27, and 275 clocks, respectively.

[0395] Accordingly, the timing controller (232) can extract R, G, B data from the image signal during a period of 248 clocks within the data enable signal (DE2).

[0396] As another example, when the signal processing device (170) sets the data transmission bit of the image signal to 12 bits, the active section, blank section, and total section of Horizontal can output a data enable signal (DE3) corresponding to 272, 3, and 275 clocks, respectively.

[0397] Figure 13a illustrates a data format of 10 to 11 bit data transmission bits.

[0398] Referring to the drawing, the signal processing device (170) can transmit 10-bit R, G, B data by Rn[0] to Rn[9], Gn[0] to Gn[9], Bn[0] to Bn[9] in 4-byte mode when transmitting a 10-bit image signal.

[0399] That is, the signal processing device (170) can control so that Rn[2] to Rn[9] are placed in Byte0 among 4 bytes, Gn[2] to Gn[9] are placed in Byte1, Bn[2] to Bn[9] are placed in Byte2, and Rn[0], Rn[1], Gn[0], Gn[1], Bn[0], Bn[1] are placed in Byte3.

[0400] At this time, the data enable signal may be a clock of 240 clocks in the active section of Horizontal.

[0401] Next, the signal processing device (170) can transmit 10-bit R, G, B data by Rn[0]~Rn

[0010] , Gn[0]~Gn

[0010] , Bn[0]~Bn

[0010] in 4-byte mode when transmitting an 11-bit image signal.

[0402] That is, the signal processing device (170) can control so that Rn[3] to Rn

[0010] are placed in Byte0 among 4 bytes, Gn[3] to Gn

[0010] are placed in Byte1, Bn[3] to Bn

[0010] are placed in Byte2, and Rn[1], Rn[2], Gn[1], Gn[2], Bn[1], Bn[2] are placed in Byte3.

[0403] Meanwhile, the signal processing device (170) can control Rn[0] and Gn[0] to be further placed in Byte3.

[0404] Meanwhile, the signal processing device (170) can extend the active period of the data enable signal from 240 clocks to 248 clocks.

[0405] Accordingly, the signal processing device (170) can control R0[0] to R0

[0239] to be placed in Byte0 to Byte3 during a period of 240 clocks to 248 clocks.

[0406] Ultimately, due to the variation of the active section of the data enable signal, the gradation expression during image display can be improved without variation of the transmission lane of the image signal.

[0407] Figure 13b illustrates the data format of 12-bit data transmission bits.

[0408] Referring to the drawing, the signal processing device (170) can transmit 12-bit R, G, B data by Rn[0]~Rn

[0011] , Gn[0]~Gn

[0011] , Bn[0]~Bn

[0011] in 4-byte mode when transmitting a 12-bit image signal.

[0409] That is, the signal processing device (170) can control so that Rn[4] to Rn

[0011] are placed in Byte0 among 4 bytes, Gn[4] to Gn

[0011] are placed in Byte1, Bn[4] to Bn

[0011] are placed in Byte2, and Rn[2], Rn[3], Gn[2], Gn[3], Bn[2], Bn[3] are placed in Byte3.

[0410] Meanwhile, the signal processing device (170) can control Rn[1] and Gn[1] to be further placed in Byte3.

[0411] Meanwhile, the signal processing device (170) can extend the active period of the data enable signal from 240 clocks to 272 clocks.

[0412] Accordingly, the signal processing device (170) can control R1[0] to R1

[0239] to be placed in Byte0 to Byte3 during a period of 240 to 248 clocks.

[0413] Meanwhile, the signal processing device (170) can control B0[0] to B0

[0239] to be placed in Byte0 to Byte3 during a period of 249 clocks to 256 clocks.

[0414] Meanwhile, the signal processing device (170) can control G0[0] to G0

[0239] to be placed in Byte0 to Byte3 during a period of 257 to 264 clocks.

[0415] Meanwhile, the signal processing device (170) can control R0[0] to R0

[0239] to be placed in Byte0 to Byte3 during a period of 265 clocks to 272 clocks.

[0416] Accordingly, the signal processing device (170) can control R0[0] to R0

[0239] to be placed in Byte0 to Byte3 during a 12-bit data transmission bit using a period of 240 clocks to 272 clocks.

[0417] Ultimately, due to the variation of the active section of the data enable signal, the gradation expression during image display can be improved without variation of the transmission lane of the image signal.

[0418] Figure 14a illustrates an example of image display in normal mode.

[0419] Referring to the drawing, the signal processing device (170) can output a first data enable signal (DE) corresponding to the first active period (HA) and the first blank period (HB) when the image display mode is the normal mode.

[0420] Accordingly, the timing controller (232) can extract R, G, B data within the image signal based on the first data enable signal (DE) and control the display of the first image (1405) based on the R, G, B data.

[0421] At this time, the normal mode may be a broadcast display mode. That is, the first image (1405) may be a broadcast image.

[0422] Figure 14b illustrates an example of a video display in game mode.

[0423] Referring to the drawing, the signal processing device (170) can output a second data enable signal (DE) corresponding to the second active period (HA) and the second blank period (HB) when the image display mode is a game mode.

[0424] At this time, it is preferable that the length of the second active section (HA) is greater than the length of the first active section (HA), and the length of the second blank section (HB) is less than the length of the first blank section (HB).

[0425] Accordingly, the timing controller (232) can extract R, G, B data within the image signal based on the second data enable signal (DE) and control to display the second image (1415), which is a game image, based on the R, G, B data.

[0426] Accordingly, it is possible to improve the gradation expression when displaying an image without changing the transmission lane of the image signal.

[0427] Although the preferred embodiments of the present disclosure have been illustrated and described above, the present disclosure is not limited to the specific embodiments described above, and various modifications may be made by a person skilled in the art to which the present invention pertains without departing from the gist of the present disclosure as claimed in the claims, and such modifications should not be understood individually from the technical idea or prospect of the present disclosure.

[0428] The present disclosure is applicable to an image display device, and more specifically, to an image display device capable of improving gradation expression when displaying an image.

Claims

1. Panel; A signal processing device that processes an input image and outputs an image signal; A timing controller for driving the panel based on a video signal from the signal processing device; The above signal processing device, It outputs a data enable signal that is divided into an active section and a blank section. A video display device that varies the length of the active section or the length of the blank section when the data bit of the video signal is varied.

2. In paragraph 1, The above signal processing device, When the video display mode is normal mode, a first data enable signal corresponding to the first active period and the first blank period is output, When the above video display mode is a game mode, a second data enable signal corresponding to the second active period and the second blank period is output, A video display device wherein the length of the second active section is greater than the length of the first active section, and the length of the second blank section is less than the length of the first blank section.

3. In paragraph 1, The above signal processing device, In order to display an image of a first level of peak brightness on the above panel, a first data enable signal corresponding to a first active period and a first blank period is output, In order to display an image of a second level of peak brightness greater than the first level on the above panel, a second data enable signal corresponding to the second active period and the second blank period is output, A video display device wherein the length of the second active section is greater than the length of the first active section, and the length of the second blank section is less than the length of the first blank section.

4. In paragraph 1, The above signal processing device, Outputs a first data enable signal corresponding to the frequency of the first vertical synchronization signal, A video display device that sets the length of the active interval or the length of the blank interval corresponding to the data bit of the video signal, when the data bit of the video signal is any one of the first bit, the second bit, the third bit, the fourth bit, and the fifth bit.

5. In paragraph 1, The above signal processing device, When the vertical synchronization signal frequency corresponds to the frequency of the first vertical synchronization signal, the data bits of the video signal set the length of the active period or the length of the blank period corresponding to any one of the first number of bits, A video display device in which, when the vertical synchronization signal frequency corresponds to a frequency of a second vertical synchronization signal higher than a frequency of a first vertical synchronization signal, the data bits of the video signal set the length of the active period or the length of the blank period corresponding to any one of a second number of bits smaller than the first number.

6. In paragraph 1, The above signal processing device, Outputs a second data enable signal corresponding to the frequency of the second vertical synchronization signal, A video display device that sets the length of the active interval or the length of the blank interval corresponding to the data bit of the video signal, when the data bit of the video signal is any one of the first bit, the second bit, and the third bit.

7. In paragraph 1, The above signal processing device, A video display device that controls the length of the blank section of the data enable signal to become shorter as the frequency of the vertical synchronization signal increases.

8. In paragraph 1, The above signal processing device, A video display device that controls the length of the active section of the data enable signal to increase or the length of the blank section to decrease as the data bit of the video signal increases.

9. In paragraph 1, The above signal processing device, A video display device in which the length of the active section or the length of the blank section is varied when the data enable variable mode is used.

10. In paragraph 9, The above signal processing device, A video display device in which the length of the active section and the length of the blank section are fixed when the data enable fixed mode is used.

11. In paragraph 1, The above signal processing device, A video display device that outputs the video signal including R, G, and B data corresponding to the length of the active section of the data enable signal.

12. In paragraph 11, The above signal processing device, A video display device that controls the data bits of the R, G, B data to increase as the length of the active section of the data enable signal increases.

13. Panel; A signal processing device that processes an input image and outputs an image signal; A timing controller for driving the panel based on a video signal from the signal processing device; The above signal processing device, When the video display mode is normal mode, a first data enable signal corresponding to the first active period and the first blank period is output, When the above video display mode is a game mode, a second data enable signal corresponding to the second active period and the second blank period is output, An image display device wherein the length of the second active section is greater than the length of the first active section, and the length of the second blank section is less than the length of the first blank section.

14. In paragraph 13, The above signal processing device, A video display device that controls the data bits of R, G, B data output in the game mode to be larger than the data bits of R, G, B data output in the normal mode.

15. In paragraph 13, The above signal processing device, When the above image display mode is a game mode and the vertical synchronization signal frequency corresponds to the frequency of the first vertical synchronization signal, the second data enable signal corresponding to the second active period and the second blank period is output, When the above image display mode is a game mode and the vertical synchronization signal frequency corresponds to a frequency of a second vertical synchronization signal greater than the frequency of the first vertical synchronization signal, a third data enable signal corresponding to a third active period and a third blank period is output, A video display device wherein the length of the third active section is greater than the length of the second active section, and the length of the third blank section is less than the length of the second blank section.

16. Panel; A signal processing device that processes an input image and outputs an image signal; A timing controller for driving the panel based on a video signal from the signal processing device; The above signal processing device, It outputs a data enable signal that is divided into an active section and a blank section. In case of data enable variable mode, the length of the active section or the length of the blank section is variable, A video display device that fixes the length of the active section and the length of the blank section when in data enable fixed mode.

17. In paragraph 16, The above signal processing device, The above data enable variable mode is, when the image display mode is normal mode, a first data enable signal corresponding to the first active period and the first blank period is output, The above data enable variable mode is, and when the image display mode is a game mode, a second data enable signal corresponding to the second active period and the second blank period is output, A video display device wherein the length of the second active section is greater than the length of the first active section, and the length of the second blank section is less than the length of the first blank section.

18. In paragraph 17, The above signal processing device, If the above data enable variable mode, Outputs a first data enable signal corresponding to the frequency of the first vertical synchronization signal, A video display device that sets the length of the active interval or the length of the blank interval corresponding to the data bit of the video signal, when the data bit of the video signal is any one of the first bit, the second bit, the third bit, the fourth bit, and the fifth bit.

Images