Display panel and electronic device equipped with same

Abstract

Provided are a display panel and an electronic device equipped with same, the display panel comprising: first and second initialization voltage lines alternating along a first direction in a display area, extending in a second direction crossing the first direction; and first horizontal initialization voltage lines extending in the first direction and electrically connected to the first initialization voltage lines.

Description

Display panel and electronic device having the same

[0001] Embodiments of the present invention relate to a display panel and an electronic device having the same, and more particularly, to a display panel capable of displaying high-quality images and an electronic device having the same.

[0002] Display panels are used in a variety of electronic devices. To increase resolution and display high-quality images, pixel sizes are shrinking, necessitating the placement of various electronic components in a narrow area.

[0003] Conventional display panels and electronic devices equipped with them have the problem of being unable to display high-quality images due to interference between various electronic elements placed in a narrow area.

[0004] The present invention aims to address various issues, including those described above, by providing a display panel capable of displaying high-quality images and an electronic device comprising the same. However, these tasks are exemplary and should not be construed as limiting the scope of the present invention.

[0005] According to one aspect of the present invention, a display panel is provided, which includes first initialization voltage lines and second initialization voltage lines that are alternately arranged along a first direction within a display area and extend in a second direction intersecting the first direction, and first horizontal initialization voltage lines that extend in the first direction and are electrically connected to the first initialization voltage lines.

[0006] Connecting electrodes may be further provided between the first initialization voltage lines and the first horizontal initialization voltage lines to electrically connect the first initialization voltage lines and the first horizontal initialization voltage lines.

[0007] The above first initialization voltage lines may be located above the first horizontal initialization voltage lines.

[0008] Each of the above connecting electrodes can be electrically connected to a dummy semiconductor layer located below a corresponding one of the first horizontal initialization voltage lines.

[0009] It may further include second horizontal initialization voltage lines extending in the first direction and electrically connected to the second initialization voltage lines.

[0010] The first horizontal initialization voltage lines and the second horizontal initialization voltage lines may be arranged alternately along the second direction.

[0011] Connecting electrodes may be further provided between the second initialization voltage lines and the second horizontal initialization voltage lines to electrically connect the second initialization voltage lines and the second horizontal initialization voltage lines.

[0012] The above second initialization voltage lines may be located above the second horizontal initialization voltage lines.

[0013] Each of the above connecting electrodes can be electrically connected to a semiconductor layer of an initialization transistor located below a corresponding one of the second horizontal initialization voltage lines.

[0014] The above initialization transistor can be electrically connected to a pixel electrode of a light-emitting diode.

[0015] The display area may further include reference voltage lines arranged along the first direction and extending in the second direction, and horizontal reference voltage lines extending in the first direction and electrically connected to the reference voltage lines.

[0016] The first horizontal initialization voltage lines and the second horizontal initialization voltage lines are arranged alternately along the second direction, and each of the horizontal reference voltage lines can be arranged between the first horizontal initialization voltage line and the second horizontal initialization voltage line that are adjacent to each other.

[0017] Connection electrodes may be further provided between the above-mentioned reference voltage lines and the above-mentioned horizontal reference voltage lines to electrically connect the above-mentioned reference voltage lines and the above-mentioned horizontal reference voltage lines.

[0018] The above reference voltage lines may be located above the above horizontal reference voltage lines.

[0019] Each of the above connecting electrodes can be electrically connected to a semiconductor layer of an initialization transistor located below a corresponding one of the above horizontal reference voltage lines.

[0020] The above initialization transistor can be electrically connected to the other end of a data write transistor connected to a data line.

[0021] According to another aspect of the present invention, an electronic device is provided, comprising a display panel and a lower cover having an opening forming an exterior and exposing a portion of the display panel, wherein the display panel has first initialization voltage lines and second initialization voltage lines alternately arranged along a first direction within a display area and extending in a second direction intersecting the first direction, and first horizontal initialization voltage lines extending in the first direction and electrically connected to the first initialization voltage lines.

[0022] Connecting electrodes may be further provided between the first initialization voltage lines and the first horizontal initialization voltage lines to electrically connect the first initialization voltage lines and the first horizontal initialization voltage lines.

[0023] The above first initialization voltage lines may be located above the first horizontal initialization voltage lines.

[0024] Each of the above connecting electrodes can be electrically connected to a dummy semiconductor layer located below a corresponding one of the first horizontal initialization voltage lines.

[0025] It may further include second horizontal initialization voltage lines extending in the first direction and electrically connected to the second initialization voltage lines.

[0026] The first horizontal initialization voltage lines and the second horizontal initialization voltage lines may be arranged alternately along the second direction.

[0027] Connecting electrodes may be further provided between the second initialization voltage lines and the second horizontal initialization voltage lines to electrically connect the second initialization voltage lines and the second horizontal initialization voltage lines.

[0028] The above second initialization voltage lines may be located above the second horizontal initialization voltage lines.

[0029] Each of the above connecting electrodes can be electrically connected to a semiconductor layer of an initialization transistor located below a corresponding one of the second horizontal initialization voltage lines.

[0030] The above initialization transistor can be electrically connected to a pixel electrode of a light-emitting diode.

[0031] The display area may further include reference voltage lines arranged along the first direction and extending in the second direction, and horizontal reference voltage lines extending in the first direction and electrically connected to the reference voltage lines.

[0032] The first horizontal initialization voltage lines and the second horizontal initialization voltage lines are arranged alternately along the second direction, and each of the horizontal reference voltage lines can be arranged between the first horizontal initialization voltage line and the second horizontal initialization voltage line that are adjacent to each other.

[0033] Connection electrodes may be further provided between the above-mentioned reference voltage lines and the above-mentioned horizontal reference voltage lines to electrically connect the above-mentioned reference voltage lines and the above-mentioned horizontal reference voltage lines.

[0034] The above reference voltage lines may be located above the above horizontal reference voltage lines.

[0035] Each of the above connecting electrodes can be electrically connected to a semiconductor layer of an initialization transistor located below a corresponding one of the above horizontal reference voltage lines.

[0036] The above initialization transistor can be electrically connected to the other end of a data write transistor connected to a data line.

[0037] Other aspects, features and advantages other than those described above will become apparent from the following detailed description, claims and drawings for carrying out the invention.

[0038] According to one embodiment of the present invention, as described above, a display panel capable of displaying high-quality images and an electronic device including the same can be implemented. Of course, the scope of the present invention is not limited by these effects.

[0039] FIG. 1 is a perspective view schematically illustrating an electronic device according to one embodiment of the present invention.

[0040] Figure 2 is an exploded perspective view schematically illustrating the electronic device of Figure 1.

[0041] FIG. 3 is a block diagram schematically illustrating the electronic device of FIG. 1.

[0042] FIG. 4 is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0043] Figure 5 is a side view schematically illustrating the display panel of Figure 4.

[0044] Figure 6 is a plan view schematically illustrating the display panel of Figure 4.

[0045] Figure 7 is a conceptual diagram schematically enlarged to illustrate part A of the display panel of Figure 6.

[0046] FIG. 8 is a conceptual diagram schematically enlarged to illustrate a portion of a display panel according to one embodiment of the present invention.

[0047] Fig. 9 is an equivalent circuit diagram of one pixel arranged in the display area of ​​the display panel of Fig. 6.

[0048] Fig. 10 is a layout diagram schematically showing the locations of transistors, capacitors, etc. in pixels arranged in the display area of ​​the display panel of Fig. 6.

[0049] Fig. 11 is a cross-sectional view schematically illustrating a cross-section taken along line B-B' of Fig. 6.

[0050] Figures 12 to 20 are schematic layout diagrams showing components such as transistors and capacitors of the display panel illustrated in Figure 10, layer by layer.

[0051] Fig. 21 is a schematic diagram illustrating pixel electrodes of the display panel illustrated in Fig. 10.

[0052] Fig. 22 is a cross-sectional view schematically illustrating a cross-section taken along line C-C' of Fig. 21.

[0053] FIG. 23 is a cross-sectional view schematically illustrating a cross-section of a display panel according to one embodiment of the present invention.

[0054] Figure 24 is a plan view showing the voltage layer of Figure 20.

[0055] FIG. 25 is a plan view schematically illustrating a voltage layer included in a display panel according to one embodiment of the present invention.

[0056] FIG. 26 is a schematic layout diagram illustrating a semiconductor layer included in a display panel according to one embodiment of the present invention.

[0057] Fig. 27 is a layout diagram schematically showing the positional relationship between the semiconductor layer and the initialization voltage lines of Fig. 26.

[0058] FIG. 28 is a schematic diagram illustrating first horizontal initialization voltage lines, second horizontal initialization voltage lines, and horizontal reference voltage lines included in a display panel according to one embodiment of the present invention.

[0059] Figure 29 is a schematic diagram illustrating connection electrodes that can be electrically connected to the components of Figure 28.

[0060] FIG. 30 is a schematic diagram illustrating first initialization voltage lines, second initialization voltage lines, and reference voltage lines that can be electrically connected to the components of FIG. 28.

[0061] FIG. 31 is a schematic diagram illustrating the connection relationship between the first horizontal initialization voltage lines and the second horizontal initialization voltage lines of FIG. 28 and the first initialization voltage lines and the second initialization voltage lines of FIG. 30.

[0062] Fig. 32 is a schematic diagram showing the connection relationship between the horizontal reference voltage lines of Fig. 28 and the reference voltage lines of Fig. 30.

[0063] Figure 33 is a conceptual diagram schematically illustrating the positional relationship and connection relationship between the first horizontal initialization voltage lines, the second horizontal initialization voltage lines, and the horizontal reference voltage lines, and the first initialization voltage lines, the second initialization voltage lines, and the reference voltage lines.

[0064] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0065] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same drawing reference numerals, and redundant descriptions thereof will be omitted.

[0066] In the following examples, when various components such as layers, films, regions, and plates are said to be "on" other components, this includes not only cases where they are "directly on" other components, but also cases where other components are interposed between them. Furthermore, for convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and therefore, the present invention is not necessarily limited to what is shown.

[0067] In the following examples, the x-axis, y-axis, and z-axis are not limited to three axes on an orthogonal coordinate system, and can be interpreted in a broad sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may also refer to different directions that are not orthogonal to each other.

[0068] In the examples below, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0069] In the following examples, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0070] In this specification, “A and / or B” refers to the case where it is A, or B, or both A and B. And, “at least one of A and B” refers to the case where it is A, or B, or both A and B.

[0071] In the following examples, when it is said that a film, region, or component is connected, it includes not only cases where the films, regions, or components are directly connected, but also cases where other films, regions, or components are interposed between the films, regions, or components and thus indirectly connected. For example, when it is said in this specification that a film, region, or component is electrically connected, it includes not only cases where the films, regions, or components are directly electrically connected, but also cases where other films, regions, or components are interposed between them and thus indirectly electrically connected.

[0072] FIG. 1 is a perspective view schematically illustrating an electronic device (1) according to one embodiment of the present invention, FIG. 2 is an exploded perspective view schematically illustrating the electronic device (1) of FIG. 1, and FIG. 3 is a block diagram schematically illustrating the electronic device (1) of FIG. 1.

[0073] Referring to FIGS. 1 and 2, an electronic device (1) according to an embodiment of the present invention is a device that displays a moving image or a still image, and may be a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, or an Ultra Mobile PC (UMPC), and may be various products such as a television, a laptop, a monitor, a billboard, or an Internet of Things (IOT). Alternatively, the electronic device (1) according to an embodiment of the present invention may be a wearable device such as a smart watch, a watch phone, a glasses-type display, or a head mounted display (HMD). Alternatively, the electronic device (1) according to one embodiment of the present invention may be a dashboard of a vehicle, a CID (Center Information Display) placed on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, or a display placed on the back of a front seat as entertainment for the rear seats of a vehicle.

[0074] In FIGS. 1 and 2, for convenience of explanation, an electronic device (1) according to an embodiment of the present invention is illustrated as a smart phone. This electronic device (1) may include a cover window (70), a display panel (10), a data driver (20), a display circuit board (30), a component (40), a bracket (60), a main circuit board (50), a battery (80), and / or a lower cover (90).

[0075] In the plan view of this specification, “left,” “right,” “upper,” and “lower” indicate directions when looking at the display panel (10) from a direction perpendicular to the display panel (10). For example, “left” indicates the -x direction, “right” indicates the +x direction, “upper” indicates the +y direction, and “lower” indicates the -y direction.

[0076] The electronic device (1) may appear to have a roughly rectangular shape in a plan view. For example, the electronic device (1) may appear to have a roughly rectangular shape having a short side in the x-axis direction and a long side in the y-axis direction in the xy plane as illustrated in FIG. 1. At this time, the corner where the short side in the x-axis direction and the long side in the y-axis direction meet may form a right angle, or may have a round shape with a predetermined curvature. Of course, the electronic device (1) may have a polygonal shape other than a rectangular shape in the plan view, or may have an elliptical shape or an irregular shape, etc.

[0077] A cover window (70) may be placed on the upper part of the display panel (10) to cover the upper surface of the display panel (10). This cover window (70) may have the function of protecting the upper surface of the display panel (10).

[0078] The cover window (70) may include a transparent cover portion (DA70) corresponding to the display panel (10) and a light-blocking cover portion (NDA70) surrounding the transparent cover portion (DA70). The light-blocking cover portion (NDA70) may include an opaque material (e.g., a colored opaque material) that blocks light. The light-blocking cover portion (NDA70) may include a pattern that can be shown to a user when an image is not displayed.

[0079] A display panel (10) may be arranged under a cover window (70). The display panel (10) may overlap a transparent cover portion (DA70) of the cover window (70). The display panel (10) includes a display area (DA). The display area (DA) is an area where an image is displayed, and the display area (DA) may include an area (hereinafter, a component area) that transmits light emitted from a component (40) arranged under the display panel (10). The component may include a sensor or camera that uses visible light, infrared rays, or sound.

[0080] The display panel (10) may be a light-emitting display panel including a light-emitting diode. The light-emitting diode may be an organic light-emitting diode including an organic light-emitting layer, or an inorganic light-emitting diode including an inorganic material. In the case of an inorganic light-emitting diode, it may include a PN diode including inorganic semiconductor-based materials. When a voltage is applied in the forward direction to a PN junction diode, holes and electrons are injected, and energy generated by the recombination of the holes and electrons is converted into light energy to emit light of a predetermined color. Such an inorganic light-emitting diode may have a width of several micrometers to several hundred micrometers. The inorganic light-emitting diode may be referred to as a micro LED.

[0081] The display panel (10) may be a rigid display panel that is rigid and does not bend easily, or a flexible display panel that is flexible and can be easily bent, folded, or rolled. For example, the display panel (10) may be a foldable display panel that can be folded and unfolded, a curved display panel with a curved display surface, a bent display panel with an area other than the display surface bent, a rollable display panel that can be rolled and unfolded, or a stretchable display panel that can be stretched.

[0082] The display panel (10) may be a transparent display panel that is implemented transparently so that objects or backgrounds placed on the lower surface of the display panel (10) can be viewed from the upper surface of the display panel (10). Alternatively, the display panel (10) may be a reflective display panel that can reflect objects or backgrounds on the upper surface of the display panel (10).

[0083] The data driver (20) may be mounted on the display panel (10) in the form of an integrated circuit (IC). Of course, the present invention is not limited thereto, and for example, the data driver (20) may be mounted on a display circuit board (30).

[0084] A display circuit board (30) may be attached to one side of the display panel (10). The display circuit board (30) may be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that is hard and does not bend easily, or a composite printed circuit board including both a rigid printed circuit board and a flexible printed circuit board. A touch sensor driver may be mounted on the display circuit board (30). The touch sensor driver may be formed as an integrated circuit. The touch sensor driver may be electrically connected to touch electrodes of a touch screen layer of the display panel (10) through the display circuit board (30).

[0085] The touch screen layer of the display panel (10) can detect a user's touch input using at least one of various touch methods, such as a resistive film method or an electrostatic capacitance method. When the touch screen layer of the display panel (10) detects a user's touch input using an electrostatic capacitance method, the touch sensor driving unit applies driving signals to the driving electrodes among the touch electrodes, and detects voltages charged in mutual capacitances (hereinafter referred to as "mutual capacitances") between the driving electrodes and the sensing electrodes through the sensing electrodes among the touch electrodes, thereby determining whether a user's touch has occurred.

[0086] A user's touch may include a contact touch and a proximity touch. A contact touch means that a user's finger or an object such as a pen directly contacts the cover window (70) placed on the touch screen layer. A proximity touch means that a user's finger or an object such as a pen is positioned close to the cover window (70), such as hovering. The touch sensor driver transmits sensor data to the main processor (510) according to the detected voltages, and the main processor (510) can calculate the touch coordinates where the touch input occurred by analyzing the sensor data.

[0087] A control unit for supplying driving voltages for driving pixels, gate drivers and / or data drivers (20) of the display panel (10) may be placed on the display circuit board (30).

[0088] A bracket (60) for supporting the display panel (10) may be arranged at the bottom of the display panel (10). The bracket (60) may include plastic, metal, or both plastic and metal. The bracket (60) may include a first camera hole (CMH1) into which a camera device (531) is inserted, a battery hole (BH) into which a battery (80) is arranged, a cable hole (CAH) through which a cable connected to the display circuit board (30) passes, and a component hole (CPH) corresponding to the components (40). The component hole (CPH) may overlap with the components (40) of the main circuit board (50) when viewed in the third direction (z-axis direction). For reference, the display area (DA) of the display panel (10) may overlap with the components (40) of the main circuit board (50) when viewed in the third direction (z-axis direction). Of course, the bracket (60) may not have the component hole (CPH) as needed.

[0089] The component (40) included in the electronic device (1) may include a first component (41), a second component (42), a third component (43), and a fourth component (44) that overlap the display panel (10). Each of the first component (41), the second component (42), the third component (43), and the fourth component (44) may include at least one of a proximity sensor, an illumination sensor, an iris sensor, a facial recognition sensor, and a camera (or an image sensor). The proximity sensor using infrared rays may detect an object positioned close to the upper surface of the electronic device (1), and the illumination sensor may detect the brightness of light incident on the upper surface of the electronic device (1). In addition, the iris sensor may photograph the iris of a person positioned on the upper surface of the electronic device (1), and the camera may obtain image data for an object placed on the upper surface of the electronic device (1). Of course, the component (40) is not limited to a proximity sensor, a light sensor, an iris sensor, a facial recognition sensor, and / or a camera, and may include other sensors.

[0090] A main circuit board (50) and a battery (80) may be placed at the bottom of the bracket (60). The main circuit board (50) may be a printed circuit board or a flexible printed circuit board.

[0091] The main circuit board (50) may include a main processor (510), a camera device (531), a main connector (55), and components (40). The main processor (510) may be formed as an integrated circuit. If necessary, the electronic device (1) may include a camera device (531) disposed on the upper surface of the main circuit board (50) as well as a camera device disposed on the lower surface of the main circuit board (50). Each of the main processor (510) and the main connector (55) may be disposed on either the upper surface or the lower surface of the main circuit board (50). The main circuit board (50) may be electrically connected to the display circuit board (30) via the main connector (55), etc.

[0092] The main processor (510) can control all functions of the electronic device (1). For example, the main processor (510) can output digital video data to the data driver (20) through the display circuit board (30) so that the display panel (10) can display an image. The main processor (510) can receive detection data from the touch sensor driver. The main processor (510) can determine whether a user touches the screen based on the detection data and execute an operation corresponding to the user's direct touch or proximity touch. The main processor (510) can be an application processor, a central processing unit, or a system chip formed of an integrated circuit.

[0093] The camera device (531) processes image frames, such as still images or moving images, obtained by an image sensor in camera mode and outputs them to the main processor (510). The camera device (531) may include at least one of a camera sensor (e.g., CCD or CMOS), a photo sensor (or image sensor), and a laser sensor.

[0094] A cable passing through the cable hole (CAH) of the bracket (60) can be connected to the main connector (55), and the main circuit board (50) can be electrically connected to the display circuit board (30) through this cable.

[0095] The electronic device (1) may be represented by a block diagram as illustrated in FIG. 3. In addition to the main processor (510), the electronic device (1) may be represented as including a wireless communication unit (520), an input unit (530), a sensor unit (540), an output unit (550), an interface unit (560), a memory (570), and / or a power supply unit (580) as illustrated in FIG. 3.

[0096] The wireless communication unit (520) may include at least one of a broadcast reception module (521), a mobile communication module (522), a wireless Internet module (523), a short-range communication module (524), and a location information module (525).

[0097] The broadcast reception module (521) receives broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include a satellite channel or a terrestrial channel.

[0098] The mobile communication module (522) transmits and receives wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network constructed according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc.). The wireless signal may include various types of data according to voice call signals, video call call signals, or text / multimedia message transmission and reception.

[0099] The wireless Internet module (523) refers to a module for wireless Internet access. The wireless Internet module (523) may be configured to transmit and receive wireless signals in a communication network according to wireless Internet technologies. The wireless Internet technologies may be, for example, WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, and / or DLNA (Digital Living Network Alliance).

[0100] The short-range communication module (524) is for short-range communication, and can support short-range communication using at least one of Bluetooth™, RFID (Radio Frequency Identification), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee, NFC (Near Field Communication), Wi-Fi (Wireless-Fidelity), Wi-Fi Direct, and Wireless USB (Wireless Universal Serial Bus) technologies. The short-range communication module (524) can support wireless communication between an electronic device (1) and a wireless communication system, between the electronic device (1) and another electronic device, or between the electronic device (1) and a network where another electronic device (or an external server) is located through a short-range wireless communication network (Wireless Area Network). The short-range wireless communication network may be a Wireless Personal Area Network. The other electronic device may be a wearable device capable of exchanging (or linking) data with the electronic device (1).

[0101] The location information module (525) is a module for obtaining the location of the electronic device (1) and may include a GPS (Global Positioning System) module or a WiFi (Wireless Fidelity) module.

[0102] The input unit (530) may include a video input unit such as a camera device (531) for inputting a video signal, an audio input unit such as a microphone (532) for inputting an audio signal, and an input device (533) for receiving information from a user. The camera device (531) processes image frames such as still images or moving images obtained by an image sensor in a video call mode or a shooting mode. The processed image frames may be displayed on a display panel (10) or stored in a memory (570). The microphone (532) processes an external audio signal into electrical voice data. The processed voice data may be utilized in various ways depending on the function being performed (or the application being executed) in the electronic device (1).

[0103] The main processor (510) can control the operation of the electronic device (1) to correspond to information input through the input device (533). The input device (533) can include a mechanical input means or a touch input means, such as a button, a dome switch, a jog wheel, a jog switch, etc., located on the rear or side of the electronic device (1). The touch input means can be formed of a touch screen layer of the display panel (10).

[0104] The sensor unit (540) may include one or more sensors that sense at least one of information within the electronic device (1), information about the surrounding environment surrounding the electronic device (1), and user information, and generate a sensing signal corresponding thereto. The main processor (510) may control the driving or operation of the electronic device (1) based on the sensing signal, or perform data processing, functions, or operations related to an application installed in the electronic device (1). The sensor unit (540) may be a proximity sensor, an illumination sensor, or a facial recognition sensor, as described above with respect to the component (40). Of course, the sensor unit (540) may include an acceleration sensor, a magnetic sensor, a G-sensor, a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor (IR sensor), a fingerprint recognition sensor, an ultrasonic sensor, an optical sensor, and / or a battery gauge. In addition, the sensor unit (540) may include an environmental sensor or a chemical sensor. The environmental sensor may be, for example, a barometer, a hygrometer, a thermometer, a radiation detection sensor, a heat detection sensor, and / or a gas detection sensor. The chemical sensor may be, for example, an electronic nose, a healthcare sensor, and / or a biometric sensor.

[0105] The output unit (550) is for generating output related to vision, hearing, or tactile sensations, and may include at least one of a display panel (10), an audio output unit (551), a haptic module (552), and an optical output unit (553).

[0106] The display panel (10) displays (outputs) information processed in the electronic device (1). For example, the display panel (10) may display execution screen information of an application running in the electronic device (1), display a UI (User Interface) according to the execution screen information, or display GUI (Graphical User Interface) information. The display panel (10) may include a display layer that displays an image and a touch screen layer that detects a user's touch input. Accordingly, the display panel (10) may function as one of the input devices (533) that provides an input interface between the electronic device (1) and the user, and at the same time, function as one of the output units (550) that provides an output interface between the electronic device (1) and the user.

[0107] The audio output unit (551) can output audio data received from the wireless communication unit (520) or stored in the memory (570) in a call signal reception mode, a call mode, a recording mode, a voice recognition mode, and / or a broadcast reception mode. The audio output unit (551) can also output audio signals related to functions performed in the electronic device (1) (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit (551) can include a receiver and a speaker. At least one of the receiver and the speaker can be a sound generating device attached to the lower portion of the display panel (10) and vibrating the display panel (10) to output audio. The sound generating device can be a piezoelectric element or piezoelectric actuator that contracts and expands according to an electric signal, or an exciter that generates magnetic force using a voice coil to vibrate the display panel (10).

[0108] The haptic module (552) generates various tactile effects that can be felt by the user. The haptic module (552) can provide vibrations to the user as tactile effects. The haptic module (552) can not only deliver tactile effects through direct contact, but can also be implemented so that the user can feel the tactile effects through the kinesthetic senses of the fingers or arms.

[0109] The light output unit (553) outputs a signal to notify the occurrence of an event using light from a light source. Examples of events occurring in the electronic device (1) may include receiving a message, receiving a call signal, receiving a missed call, an alarm, receiving a schedule reminder, receiving an email, and / or receiving information through an application. The signal output by the light output unit (553) is implemented by the electronic device (1) emitting light of a single color or multiple colors from the front or rear. The signal output may be terminated when the electronic device (1) detects the user's confirmation of an event.

[0110] The interface unit (560) serves as a passage for various types of external devices connected to the electronic device (1). The interface unit (560) may include at least one of a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio I / O (Input / Output) port, a video I / O (Input / Output) port, and an earphone port. When an external device is connected to the interface unit (560), the electronic device (1) may perform appropriate control related to the connected external device.

[0111] The memory (570) stores data that supports various functions of the electronic device (1). The memory (570) can store a plurality of applications (application programs) running on the electronic device (1), data and / or commands for the operation of the electronic device (1). At least some of the plurality of applications can be downloaded from an external server via wireless communication. The memory (570) can store applications for the operation of the main processor (510), and can also temporarily store input / output data, such as a phone book, messages, still images and / or moving images. In addition, the memory (570) can store haptic data for various patterns of vibration provided to the haptic module (552) and audio data regarding various sounds provided to the audio output unit (551).

[0112] The memory (570) may include at least one type of storage medium among a flash memory type, a hard disk type, an SSD (Solid State Disk type), an SDD (Silicon Disk Drive type), a multimedia card micro type, a card type memory (e.g., SD or XD memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, and an optical disk.

[0113] The power supply unit (580) receives external power and / or internal power under the control of the main processor (510) and supplies power to each component included in the electronic device (1). The power supply unit (580) may include a battery (80). In addition, the power supply unit (580) may be provided with a connection port, which may be an example of an interface unit (560) to which an external charger that supplies power for charging the battery is electrically connected. Alternatively, the power supply unit (580) may enable the battery (80) to be charged wirelessly. As illustrated in FIG. 2, the battery (80) may be arranged so as not to overlap the main circuit board (50) in the third direction (z direction). The battery (80) may overlap the battery hole (BH) of the bracket (60).

[0114] The lower cover (90) as illustrated in FIG. 2 forms the outer appearance of the electronic device (1) and may have an opening that exposes a portion of the display panel (10). The lower cover (90) has an open surface corresponding to the display panel (10) and may be fastened to the display panel (10). The lower cover (90) may be positioned on the opposite side of the cover window (70) with the display panel (10) interposed therebetween. The lower cover (90) may be positioned below the main circuit board (50) and the battery (80). The lower cover (90) may be fastened to and fixed by a bracket (60). The lower cover (90) may form the lower appearance of the electronic device (1). The lower cover (90) may include plastic, metal, or both plastic and metal.

[0115] A second camera hole (CMH2) that exposes the lower surface of the camera device (531) may be formed in the lower cover (90). The position of the camera device (531) and the positions of the first camera hole (CMH1) and the second camera hole (CMH2) corresponding to the camera device (531) are not limited to those illustrated in FIGS. 1 and 2 and may be varied in various ways.

[0116] Fig. 4 is a plan view schematically illustrating a display panel (10) according to one embodiment of the present invention, and Fig. 5 is a side view schematically illustrating the display panel of Fig. 4. The electronic device (1) described above may include a display panel (10) such as that illustrated in Figs. 4 and 5.

[0117] The display panel (10) may include a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) is a portion that displays an image, and a plurality of pixels may be arranged. The display area (DA) may have various shapes, such as a circle, an oval, a polygon, or a shape of a specific shape. In Fig. 4, the display area (DA) is illustrated as having a roughly rectangular shape with rounded corners.

[0118] The peripheral area (PA) may be located outside the display area (DA). The peripheral area (PA) may include a first peripheral area (PA1) arranged to surround at least a portion of the display area (DA), and a second peripheral area (PA2) located at the lower end of the display area (DA) and extending in a first direction (x-axis direction). A width of the second peripheral area (PA2) in the first direction (x-axis direction) may be narrower than a width of the display area (DA). This structure allows at least a portion of the second peripheral area (PA2) to be easily bent.

[0119] The shape of the plane of the display panel (10) illustrated in FIG. 4 may be substantially the same as the shape of the substrate (100) included in the display panel (10). When the display panel (10) includes a display area (DA) and a peripheral area (PA) outside the display area (DA), it can be said that the substrate (100) includes the display area (DA) and a peripheral area (PA) outside the display area (DA). Hereinafter, for convenience, the substrate (100) is described as having the display area (DA) and the peripheral area (PA).

[0120] The display panel (10) may include a main region (MR), a bending region (BR) outside the main region (MR), and a sub-region (SR) spaced apart from the main region (MR) with the bending region (BR) therebetween. The main region (MR) may be arranged on one side of the bending region (BR), and the sub-region (SR) may be arranged on the other side of the bending region (BR). The display panel (10) may be bent in the bending region (BR), as illustrated in FIG. 5, and at least a portion of the sub-region (SR) may overlap the main region (MR) when viewed in the third direction (z-axis direction). Although FIG. 5 illustrates the display panel (10) being bent, the present invention is not limited thereto. For example, the display panel (10) may be a foldable display panel, in which case the display panel (10) may be bent within the display region (DA) about a bending axis crossing the display region (DA). Of course, if necessary, the display panel (10) may not be bent. The sub-region (SR) may be a non-display region.

[0121] A data driver (20) may be placed in a sub-region (SR) of a display panel (10). The data driver (20) may be placed in the display panel (10) in the form of an integrated circuit (IC). For example, the data driver (20) may be a data driving integrated circuit that generates a data signal.

[0122] A display circuit board (30) may be attached to an end of a sub-area (SR) of a display panel (10). The display circuit board (30) may be electrically connected to a data driver (20) or the like through a pad of the sub-area (SR) of the display panel (10).

[0123] Fig. 6 is a plan view schematically illustrating the display panel (10) of Fig. 4. As illustrated in Fig. 6, the display panel (10) may include a substrate (100). Various components constituting the display panel (10) may be arranged on the substrate (100).

[0124] The substrate (100) may include glass, ceramic, metal, or a polymer resin. The substrate (100) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate (100) may have a multilayer structure including two layers including such polymer resins and an inorganic layer interposed between the layers. Alternatively, the substrate (100) may have a structure in which layers including such polymer resins and inorganic layers are alternately laminated. The inorganic layer may include, for example, silicon oxide, silicon nitride or silicon oxynitride.

[0125] Pixels are arranged in a display area (DA), and the display area (DA) can provide an image using light emitted from the pixels. Each pixel can include a light-emitting diode (LED), and the light-emitting diode (LED) can be electrically connected to a pixel circuit (PC). The pixel circuit (PC) and the light-emitting diode (LED) can be arranged in the display area (DA). In Fig. 6, for convenience, the pixel circuit (PC) and the light-emitting diode (LED) are illustrated as being positioned side by side, but in reality, the pixel circuit (PC) and the light-emitting diode (LED) can overlap at least partly. For example, the light-emitting diode (LED) can be arranged on the pixel circuit (PC).

[0126] A gate driving circuit, a pad (14), a first power supply wiring (15), and a second power supply wiring (16) may be arranged in the peripheral area (PA). The gate driving circuit may include, for example, a first scan driving circuit (11), a second scan driving circuit (12), and / or a light emission control driving circuit (13).

[0127] The first scan driving circuit (11) can provide a scan signal to the pixel circuit (PC) through the gate line (SL). The second scan driving circuit (12) can be arranged on the opposite side of the first scan driving circuit (11) with the display area (DA) interposed therebetween. Some of the pixel circuits (PC) arranged in the display area (DA) can be electrically connected to the first scan driving circuit (11), and the rest can be connected to the second scan driving circuit (12). Of course, the second scan driving circuit (12) can be omitted in some cases.

[0128] The light emission control driving circuit (13) may be arranged on one side of the display area (DA) like the first scan driving circuit (11). The light emission control driving circuit (13) may provide a light emission control signal to the pixel (P) through the light emission control line (EL). In Fig. 6, the light emission control driving circuit (13) is illustrated as being arranged only on one side of the display area (DA), but the present invention is not limited thereto. For example, the display panel (10) may have light emission control driving circuits (13) arranged on one side and the other side of the display area (DA). Alternatively, the first scan driving circuit (11) may be arranged on one side of the display area (DA), and the light emission control driving circuit (13) may be arranged on the other side.

[0129] The pad (14) may be placed in the second peripheral area (PA2) of the substrate (100). The pad (14) is exposed without being covered by an insulating layer, and may be electrically connected to the display circuit board (30). The pad (34) of the display circuit board (30) may be electrically connected to the pad (14) of the display panel (10).

[0130] The display circuit board (30) transmits a signal or power from the control unit to the display panel (10). The control signal generated by the control unit can be transmitted to each gate driving circuit through the display circuit board (30). In addition, the control unit can provide a first power voltage (ELVDD) and a second power voltage (ELVSS) to the first power supply wire (15) and the second power supply wire (16). The first power voltage (ELVDD, hereinafter referred to as driving voltage) is provided to each pixel circuit (PC) through a driving voltage line (PL) connected to the first power supply wire (15), and the second power voltage (ELVSS, hereinafter referred to as common voltage) can be provided to a common electrode of a light emitting diode (LED) connected to the second power supply wire (16). The first power supply wire (15) can extend in a first direction (x-axis direction). The second power supply wiring (16) has a loop shape with one side open, so that it can partially surround the display area (DA).

[0131] The data signal of the data driver (20) can be transmitted to the pixel circuit (PC) through the data line (DL) electrically connected to the input line (IL) via the input line (IL).

[0132] Fig. 7 is a conceptual diagram schematically enlarging part A of the display panel (10) of Fig. 6. As illustrated in Fig. 7, a data line (DL) extending along the second direction (y-axis direction) is arranged in the display area (DA), and an input line (IL) is arranged in the peripheral area (PA). The input line (IL) can transmit a data signal of the data driver (20) to the data line (DL). In FIG. 7, for convenience of illustration, the data lines (DL) include a first data line (DL1), a second data line (DL2), a third data line (DL3), a fourth data line (DL4), a fifth data line (DL5), and a sixth data line (DL6), and the input lines (IL) include a first input line (IL1), a second input line (IL2), a third input line (IL3), a fourth input line (IL4), a fifth input line (IL5), and a sixth input line (IL6). However, the number of data lines (DL) and the number of input lines (IL) may be varied.

[0133] Some of the data lines (DL) may be directly connected to the corresponding input lines (IL), while other of the data lines (DL) may be electrically connected to the corresponding input lines (IL) via data transfer lines (DTL).

[0134] The first data line (DL1), the third data line (DL3), and the fifth data line (DL5) can receive data signals from the first input line (IL1), the third input line (IL3), and the fifth input line (IL5). The first data line (DL1), the third data line (DL3), and the fifth data line (DL5) can be electrically connected to the first input line (IL1), the third input line (IL3), and the fifth input line (IL5). Each of the first data line (DL1), the third data line (DL3), and the fifth data line (DL5) can be integral with a corresponding one of the first input line (IL1), the third input line (IL3), and the fifth input line (IL5). Alternatively, each of the first data line (DL1), the third data line (DL3), and the fifth data line (DL5) may be electrically connected to a corresponding one of the first input line (IL1), the third input line (IL3), and the fifth input line (IL5) through the first contact hole (CNT1), as illustrated in FIG. 7.

[0135] The second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) can be electrically connected to the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) through the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3). That is, the second input line (IL2) can be electrically connected to the second data line (DL2) through the first data transmission line (DTL1), the fourth input line (IL4) can be electrically connected to the fourth data line (DL4) through the second data transmission line (DTL2), and the sixth input line (IL6) can be electrically connected to the sixth data line (DL6) through the third data transmission line (DTL3).

[0136] Most of each of the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3) may be located within the display area (DA). One end of each of the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3) may be electrically connected to a corresponding one of the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) through a second contact hole (CNT2). The other end of each of the first data transmission line (DTL1), the second data transmission line (DTL2), and the third data transmission line (DTL3) may be electrically connected to a corresponding one of the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) through a third contact hole (CNT3). For reference, in Fig. 7, the second contact hole (CNT2) and the third contact hole (CNT3) are illustrated as being located in the peripheral area (PA), but the present invention is not limited thereto. For example, the second contact hole (CNT2) and / or the third contact hole (CNT3) may be located within the display area (DA).

[0137] The first data transmission line (DTL1) may include a first horizontal connection line (DHL1), a first vertical connection line (DVL1), and a first additional vertical connection line (DVL1'), the second data transmission line (DTL2) may include a second horizontal connection line (DHL2), a second vertical connection line (DVL2), and a second additional vertical connection line (DVL2'), and the third data transmission line (DTL3) may include a third horizontal connection line (DHL3), a third vertical connection line (DVL3), and a third additional vertical connection line (DVL3'). The first horizontal connection line (DHL1), the second horizontal connection line (DHL2), and the third horizontal connection line (DHL3) may extend approximately in the first direction (x-axis direction). The first vertical connection line (DVL1), the second vertical connection line (DVL2), the third vertical connection line (DVL3), the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3') extend approximately in the second direction (y-axis direction) and can be substantially parallel to the data line (DL).

[0138] Each of the second input line (IL2), the fourth input line (IL4), and the sixth input line (IL6) is electrically connected to a corresponding one of the first vertical connection line (DVL1), the second vertical connection line (DVL2), and the third vertical connection line (DVL3) through a second contact hole (CNT2), and each of the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) can be electrically connected to a corresponding one of the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3') through a third contact hole (CNT3). Each of the first horizontal connecting line (DHL1), the second horizontal connecting line (DHL2), and the third horizontal connecting line (DHL3) is electrically connected to a corresponding one of the first vertical connecting line (DVL1), the second vertical connecting line (DVL2), and the third vertical connecting line (DVL3) through the first connecting contact hole (DHL-CNT1), and can be electrically connected to a corresponding one of the first additional vertical connecting line (DVL1'), the second additional vertical connecting line (DVL2'), and the third additional vertical connecting line (DVL3') through the second connecting contact hole (DHL-CNT2).

[0139] The first vertical connection line (DVL1), the second vertical connection line (DVL2), the third vertical connection line (DVL3), the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3') may be arranged on the same first layer, and the first horizontal connection line (DHL1), the second horizontal connection line (DHL2), and the third horizontal connection line (DHL3) may be arranged on a second layer different from the first layer. For reference, when certain components are arranged on the same layer, it means that the components can be formed simultaneously with the same material through the same mask process.

[0140] In FIG. 7, as described above, the first data transmission line (DTL1) includes a first horizontal connection line (DHL1), a first vertical connection line (DVL1), and a first additional vertical connection line (DVL1'), the second data transmission line (DTL2) includes a second horizontal connection line (DHL2), a second vertical connection line (DVL2), and a second additional vertical connection line (DVL2'), and the third data transmission line (DTL3) includes a third horizontal connection line (DHL3), a third vertical connection line (DVL3), and a third additional vertical connection line (DVL3'). However, the present invention is not limited thereto.

[0141] For example, as illustrated in FIG. 8, which is a conceptual diagram schematically enlarged to illustrate a portion of a display panel (10) according to one embodiment of the present invention, a first data transmission line (DTL1) may include a first horizontal connection line (DHL1) and a first vertical connection line (DVL1), a second data transmission line (DTL2) may include a second horizontal connection line (DHL2) and a second vertical connection line (DVL2), and a third data transmission line (DTL3) may include a third horizontal connection line (DHL3) and a third vertical connection line (DVL3). In this case, each of the first horizontal connection line (DHL1), the second horizontal connection line (DHL2), and the third horizontal connection line (DHL3) may be electrically connected to a corresponding one of the first vertical connection line (DVL1), the second vertical connection line (DVL2), and the third vertical connection line (DVL3) through the first connection contact hole (DHL-CNT1), and may be electrically connected to a corresponding one of the second data line (DL2), the fourth data line (DL4), and the sixth data line (DL6) through the second connection contact hole (DHL-CNT2).

[0142] Fig. 9 is an equivalent circuit diagram of a pixel arranged in a display area (DA) of a display panel (10) of Fig. 6. As illustrated in Fig. 9, a pixel circuit (PC) connected to a light emitting diode (LED) may include a plurality of transistors and a plurality of capacitors. For example, the pixel circuit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a storage capacitor (Cst), and a hold capacitor (Chd).

[0143] The first transistor (T1) is a driving transistor that outputs a driving current corresponding to a data signal, and the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be switching transistors that transmit signals through on / off. The first terminal (first electrode) of each of the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be either a source region or a drain region, and the second terminal (second electrode) may be the other one.

[0144] At least one of the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), and the sixth transistor (T6) may be a PMOS (p-channel MOSFET), and the others may be NMOS (n-channel MOSFETs). For example, the fifth transistor (T5) may be a PMOS, and the first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), and the sixth transistor (T6) may be NMOS. Alternatively, the fifth transistor (T5) and the sixth transistor (T6) may be PMOS, and the first transistor (T1), the second transistor (T2), the third transistor (T3), and the fourth transistor (T4) may be NMOS. Alternatively, all transistors may be NMOS or all transistors may be PMOS.

[0145] At least one of the transistors may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and the rest may be transistors having oxide semiconductor layers. For example, the fifth transistor (T5) may include a semiconductor layer made of polycrystalline silicon having high reliability, and each of the remaining transistors may include an oxide semiconductor layer having the characteristics of high carrier mobility and low leakage current. Hereinafter, a case will be described where the fifth transistor (T5) is a PMOS including a silicon semiconductor layer, and the remaining transistors are NMOS including oxide semiconductor layers.

[0146] The pixel circuit (PC) can be electrically connected to gate lines that transmit signals to the gate electrodes of each of the transistors. For example, the pixel circuit (PC) can be connected to a scan line (GWL) that transmits a scan signal (GW), an initialization gate line (GBL) that transmits an initialization signal (GB), a reference gate line (GRL) that transmits a reference signal (GR), a first emission control line (EML) that transmits a first emission control signal (EM), a second emission control line (EMBL) that transmits a second emission control signal (EMB), and a data line (DL) that transmits a data signal (DATA). In addition, the pixel circuit (PC) can be connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), a reference voltage line (VRL) that transmits a reference voltage (VREF), and an initialization voltage line (VL) that transmits an initialization voltage (VINT).

[0147] A first transistor (T1), which is a driving transistor, may be electrically connected between a driving voltage line (PL) and a second node (N2). The first transistor (T1) may include a first gate electrode (G1) connected to the first node (N1), a first terminal electrically connected to the driving voltage line (PL), and a second terminal connected to a second node (N2). The first terminal may be a drain region (D) and the second terminal may be a source region (S). The first terminal of the first transistor (T1) may be electrically connected to the driving voltage line (PL) via a fifth transistor (T5), and the second terminal of the first transistor (T1) may be electrically connected to a pixel electrode of a light-emitting diode (LED) via a sixth transistor (T6). The first transistor (T1) can receive a data signal (DATA) according to the switching operation of the second transistor (T2) and control the amount of driving current (Id) flowing to the light-emitting diode (LED).

[0148] A second transistor (T2), which is a data write transistor, may be electrically connected between a data line (DL) and a first node (N1). The second transistor (T2) may include a gate electrode connected to a scan line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) is turned on by a scan signal (GW) transmitted to the scan line (GWL), electrically connecting the data line (DL) and the first node (N1), and transmitting a data signal (DATA) from the data line (DL) to the first node (N1).

[0149] A third transistor (T3), which is a first initialization transistor, may be electrically connected between a first node (N1) and a reference voltage line (VRL). The third transistor (T3) may include a gate electrode connected to the reference gate line (GRL), a first terminal connected to the first node (N1), and a second terminal connected to the reference voltage line (VRL). The third transistor (T3) may be turned on by a reference signal (GR) transmitted to the reference gate line (GRL), and may transmit a reference voltage (VREF) from the reference voltage line (VRL) to the first node (N1).

[0150] The fourth transistor (T4), which is a second initialization transistor, may be electrically connected between the first transistor (T1) and the initialization voltage line (VL). Specifically, the fourth transistor (T4) may be electrically connected between the sixth transistor (T6) described later and the initialization voltage line (VL). The fourth transistor (T4) may include a gate electrode connected to the initialization gate line (GBL), a first terminal connected to the second terminal of the sixth transistor (T6) and a light-emitting diode (LED), and a second terminal connected to the initialization voltage line (VL). The fourth transistor (T4) may be turned on by the initialization signal (GB) transmitted to the initialization gate line (GBL), and may transmit the initialization voltage (VINT) from the initialization voltage line (VL) to the pixel electrode of the light-emitting diode (LED). That is, the fourth transistor (T4) can initialize the potential of the pixel electrode of the light-emitting diode (LED) to the initialization voltage (VINT).

[0151] A fifth transistor (T5), which is a light-emitting control transistor, may be electrically connected between a driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate electrode connected to the first light-emitting control line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to a first light-emitting control signal (EM) from the first light-emitting control line (EML).

[0152] A sixth transistor (T6), which is a motion control transistor, may be connected between the first transistor (T1) and a light emitting diode (LED). The sixth transistor (T6) may include a gate electrode connected to a second light emitting control line (EMBL), a first terminal connected to a second node (N2), and a second terminal connected to the light emitting diode (LED). The sixth transistor (T6) may be turned on by a second light emitting control signal (EMB) from the second light emitting control line (EMBL), thereby electrically connecting the second node (N2) and a pixel electrode of the light emitting diode (LED).

[0153] For reference, in Fig. 9, the fifth transistor (T5) is illustrated as operating in response to the first emission control signal (EM) and the sixth transistor (T6) is illustrated as operating in response to the second emission control signal (EMB), but the present invention is not limited thereto. For example, the fifth transistor (T5) and the sixth transistor (T6) may operate in response to the same emission control signal.

[0154] For reference, the reference signal (GR) can be substantially synchronized with the scan signal (GW) of the pixel circuit (PC) located in the previous row. The initialization signal (GB) can be substantially synchronized with the scan signal (GW). Alternatively, the initialization signal (GB) can be substantially synchronized with the scan signal (GW) or the reference signal (GR) of the pixel circuit (PC) located in the next row.

[0155] The storage capacitor (Cst) may be electrically connected between the first node (N1) and the second node (N2). That is, the pixel circuit (PC) included in the display panel according to the present embodiment may be a source follower type circuit in which the storage capacitor (Cst) is connected between the first node (N1) and the second node (N2). The first storage electrode (CEs1) of the storage capacitor (Cst) may be connected to the first node (N1), and the second storage electrode (CEs2) may be connected to the second node (N2). The storage capacitor (Cst) may store a threshold voltage of the first transistor (T1) and a voltage corresponding to a data signal (DATA).

[0156] A hold capacitor (Chd) may be connected between a driving voltage line (PL) and a second node (N2). A first hold electrode (CEh1) of the hold capacitor (Chd) may be electrically connected to the driving voltage line (PL), and a second hold electrode (CEh2) may be electrically connected to a second node (N2). The hold capacitor (Chd) may allow the voltage of the second node (N2) of the first transistor (T1) to remain constant and not fluctuate when a peripheral signal fluctuates.

[0157] A light emitting diode (LED) includes a pixel electrode electrically connected to a second node (N2) via a sixth transistor (T6) and a common electrode above the pixel electrode, and the common electrode can be supplied with a common voltage (ELVSS). The common electrode can be integral with a plurality of light emitting diodes (LEDs).

[0158] Although FIG. 9 illustrates the pixel circuit (PC) as including six transistors and two capacitors, the present invention is not limited thereto. For example, the pixel circuit (PC) may include five transistors and two capacitors. It may also include seven transistors and one or two capacitors.

[0159] FIG. 10 is a layout diagram schematically showing the positions of transistors, capacitors, etc., in pixels arranged in the display area of ​​the display panel of FIG. 6. For convenience of explanation, FIG. 10 illustrates two pixel circuits, for example, a first pixel circuit (PC1) and a second pixel circuit (PC2), arranged in the same row along a first direction (x-axis direction). However, the present invention is not limited thereto. In addition, although FIG. 10 illustrates the first pixel circuit (PC1) and the second pixel circuit (PC2) as being approximately mirror-symmetrical with respect to an imaginary line (IML) extending between them in the second direction (y-axis direction), the present invention is not limited thereto. The display panel (10) may include a plurality of pixel circuits arranged to form rows in the first direction (x-axis direction) and columns in the second direction (y-axis direction).

[0160] As illustrated in FIG. 10, each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include transistors and capacitors. For example, each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include the first transistor (T1) to the sixth transistor (T6), the storage capacitor (Cst), and the hold capacitor (Chd) described above with reference to FIG. 9.

[0161] Gate lines electrically connected to the first pixel circuit (PC1) and the second pixel circuit (PC2), such as a scan line (GWL), an initialization gate line (GBL), a reference gate line (GRL), a first emission control line (EML), and a second emission control line (EMBL), may extend approximately in the first direction (x-axis direction). In addition, a horizontal connection line (DHL, see FIG. 18) may also extend approximately in the first direction (x-axis direction).

[0162] The first pixel circuit (PC1) may be electrically connected to a data line (DL) passing through the first pixel circuit (PC1), and the second pixel circuit (PC2) may be electrically connected to a data line (DL) passing through the second pixel circuit (PC2). The data line (DL) may extend approximately along the second direction (y-axis direction). The data line (DL) electrically connected to the first pixel circuit (PC1) and the data line (DL) electrically connected to the second pixel circuit (PC2) may be symmetrical with respect to the aforementioned virtual line (IML).

[0163] The first pixel circuit (PC1) may be electrically connected to a voltage line passing through the first pixel circuit (PC1), such as a reference voltage line (VRL) and an initialization voltage line (VL). The second pixel circuit (PC2) may be electrically connected to a voltage line passing through the second pixel circuit (PC2), such as a reference voltage line (VRL) and an initialization voltage line (VL). The reference voltage line (VRL) and the initialization voltage line (VL) electrically connected to the first pixel circuit (PC1) may be symmetrical with respect to the reference voltage line (VRL) and the initialization voltage line (VL) electrically connected to the second pixel circuit (PC2) with respect to the aforementioned imaginary line (IML). The reference voltage line (VRL) and the initialization voltage line (VL) may each extend approximately along the second direction (y-axis direction). For convenience, the initialization voltage line (VL) passing through the first pixel circuit (PC1) may be referred to as the first initialization voltage line (VL1), and the initialization voltage line (VL) passing through the second pixel circuit (PC2) may be referred to as the second initialization voltage line (VL2). That is, the first initialization voltage lines (VL1) and the second initialization voltage lines (VL2) extending in the second direction (y-axis direction) may be arranged alternately along the first direction (x-axis direction).

[0164] The vertical connection line (DVL) may also extend along the second direction (y-axis direction). The vertical connection line (DVL) may correspond to a portion of the data transmission line (DTL) described with reference to FIG. 7 or 8, for example, any one of the first vertical connection line (DVL1), the second vertical connection line (DVL2), the third vertical connection line (DVL3), the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3'). In this case, the vertical connection line (DVL) may be electrically connected to a data line (DL) of a pixel circuit arranged in a different column from the first pixel circuit (PC1) and the second pixel circuit (PC2) illustrated in FIG. 10, so as to transmit a data signal to pixel circuits arranged in a different column. Alternatively, if the first pixel circuit (PC1) or the second pixel circuit (PC2) is not located near a corner of the display area (DA) as shown in FIG. 7 or FIG. 8, but rather in the center of the display area (DA), the vertical connection line (DVL) may be a dummy line to which no electrical signal is applied, or may be a dummy line to which a constant electrical signal is applied as needed.

[0165] For reference, the horizontal connection line (DHL) to be described later may correspond to a portion of the data transmission line (DTL) described with reference to FIG. 7 or FIG. 8, for example, one of the first horizontal connection line (DHL1), the second horizontal connection line (DHL2), or the third horizontal connection line (DHL3). In this case, the horizontal connection line (DHL) is electrically connected to the data line (DL) of the pixel circuit arranged in a different column from the first pixel circuit (PC1) and the second pixel circuit (PC2) illustrated in FIG. 10, together with the vertical connection line (DVL), so as to transmit a data signal to the pixel circuits arranged in a different column. Alternatively, if the first pixel circuit (PC1) or the second pixel circuit (PC2) is not located near a corner of the display area (DA) as shown in FIG. 7 or FIG. 8, but rather in the center of the display area (DA), the horizontal connection line (DHL) may be a dummy line to which no electrical signal is applied, or may be a dummy line to which a constant electrical signal is applied as needed.

[0166] Fig. 11 is a cross-sectional view schematically illustrating a cross-section taken along line B-B' of Fig. 6. As illustrated in Fig. 11, the display panel (10) may include a circuit layer including transistors and capacitors arranged on a substrate (100), and a display element layer arranged on the circuit layer and including a light-emitting diode (LED). The circuit layer may include the transistors and capacitors described above with reference to Figs. 9 and 10. Fig. 11 illustrates a first transistor (T1), a fifth transistor (T5), a storage capacitor (Cst), and a hold capacitor (Chd).

[0167] A lower metal layer (1110) may be disposed on the substrate (100). The lower metal layer (1110) may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). For example, the lower metal layer (1110) may have a single-layer structure including molybdenum, a double-layer structure in which a molybdenum layer and a titanium layer are stacked, or a triple-layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0168] The lower metal layer (1110) may have a voltage level of a constant voltage. For example, the lower metal layer (1110) may have the same voltage level as the driving voltage line (PL) described above with reference to FIG. 9. That is, the driving voltage (ELVDD) may be applied to the lower metal layer (1110). To this end, the lower metal layer (1110) may be electrically connected to a portion of the driving voltage line (PL) or the first power supply line (15), for example, in the peripheral area (PA). The lower metal layer (1110) may at least partially shield light traveling to the fifth semiconductor layer (A5) of the fifth transistor (T5) and protect the fifth transistor (T5) from electrostatic discharge (ESD).

[0169] A buffer layer (101) may be disposed on the lower metal layer (1110) to cover the lower metal layer (1110). The buffer layer (101) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. This buffer layer (101) may have a single-layer structure or a multi-layer structure.

[0170] A silicon semiconductor layer may be arranged on the buffer layer (101). In FIG. 11, the fifth transistor (T5) is illustrated as including a silicon semiconductor layer. That is, FIG. 11 illustrates that the fifth semiconductor layer (A5) included in the fifth transistor (T5) is positioned on the buffer layer (101). The fifth semiconductor layer (A5) may include a channel region (C5) and conductive regions (S5, D5) arranged on both sides of the channel region (C5) and doped with impurities or subjected to plasma treatment to be conductive. One of the conductive regions (S5, D5) of the fifth semiconductor layer (A5) may be a source region and the other may be a drain region.

[0171] A first gate insulating layer (103) may be disposed on the fifth semiconductor layer (A5) to cover the fifth semiconductor layer (A5). The first gate insulating layer (103) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. This first gate insulating layer (103) may have a single-layer structure or a multi-layer structure.

[0172] A fifth gate electrode (G5) may be disposed on the first gate insulating layer (103). This fifth gate electrode (G5) may overlap with the channel region (C5) of the fifth semiconductor layer (A5). In addition to the fifth gate electrode (G5), a sub-layer of the first storage electrode (CEs1) of the storage capacitor (Cst) and the first hold electrode (CEh1) of the hold capacitor (Chd), for example, a first lower hold electrode (CEh1a), may be disposed on the first gate insulating layer (103).

[0173] The fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) may include the same material. The fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. For example, the fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) may have a single-layer structure including molybdenum, or a multi-layer structure of molybdenum / aluminum / molybdenum.

[0174] A second gate insulating layer (105) may be disposed on the fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) to cover them. The second gate insulating layer (105) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The second gate insulating layer (105) may have a single-layer structure or a multi-layer structure. If necessary, the second gate insulating layer (105) may include a different material from the first gate insulating layer (103). For example, the first gate insulating layer (103) may include silicon oxide, and the second gate insulating layer (105) may include silicon nitride.

[0175] A conductive layer (1410, hereinafter referred to as a fifth conductive layer for convenience) may be disposed on the second gate insulating layer (105). The fifth conductive layer (1410) may overlap the first storage electrode (CEs1) of the storage capacitor (Cst) and the first lower hold electrode (CEh1a) of the hold capacitor (Chd). The fifth conductive layer (1410) may include the second storage electrode (CEs2) of the storage capacitor (Cst) and the second hold electrode (CEh2) of the hold capacitor (Chd). That is, a part of the fifth conductive layer (1410) may be the second storage electrode (CEs2) of the capacitor (Cst), and another part of the fifth conductive layer (1410) may be the second hold electrode (CEh2) of the hold capacitor (Chd). In this way, the second storage electrode (CEs2) of the storage capacitor (Cst) and the second hold electrode (CEh2) of the hold capacitor (Chd) can be integral.

[0176] This fifth conductive layer (1410) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including these materials. For example, the fifth conductive layer (1410) may have a single-layer structure including molybdenum, or a multi-layer structure of molybdenum / aluminum / molybdenum.

[0177] A first interlayer insulating layer (107) may be disposed on the fifth conductive layer (1410) to cover the fifth conductive layer (1410). The first interlayer insulating layer (107) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. This first interlayer insulating layer (107) may have a single-layer structure or a multi-layer structure. For example, the first interlayer insulating layer (107) may have a laminated structure of a layer including silicon oxide and a layer including silicon nitride.

[0178] A first semiconductor layer (A1) of a first transistor (T1) and a first upper hold electrode (CEh1b) of a hold capacitor (Chd) may be disposed on a first interlayer insulating layer (107). The first semiconductor layer (A1) of the first transistor (T1) and the first upper hold electrode (CEh1b) of the hold capacitor (Chd) may both include the same material. Specifically, the first semiconductor layer (A1) of the first transistor (T1) and the first upper hold electrode (CEh1b) of the hold capacitor (Chd) may include an oxide semiconductor. The oxide semiconductor may be an oxide semiconductor including at least one element selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor may include ITZO (InSnZnO) or IGZO (InGaZnO).

[0179] The first semiconductor layer (A1) may include a channel region (C1) and conductive regions (S1, D1) arranged on both sides of the channel region (C1). One of the conductive regions (S1, D1) may be a source region and the other may be a drain region. This first semiconductor layer (A1) may be arranged on a different layer from the fifth semiconductor layer (A5) described above. The vertical distance from the substrate (100) to the first semiconductor layer (A1) may be greater than the vertical distance from the substrate (100) to the fifth semiconductor layer (A5).

[0180] The first upper hold electrode (CEh1b) of the hold capacitor (Chd) may overlap the fifth conductive layer (1410) and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) under the fifth conductive layer (1410). The first upper hold electrode (CEh1b) of the hold capacitor (Chd) may be electrically connected to the first lower hold electrode (CEh1a).

[0181] A third gate insulating layer (109) may be disposed on the first semiconductor layer (A1) and the first upper hold electrode (CEh1b) of the hold capacitor (Chd) to cover them. The third gate insulating layer (109) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride. The third gate insulating layer (109) may have a single-layer structure or a multi-layer structure. For example, the third gate insulating layer (109) may have a single-layer structure including silicon oxide.

[0182] Although FIG. 11 illustrates that the third gate insulating layer (109) passes through the side surface of the first semiconductor layer (A1) and contacts the upper surface of the first interlayer insulating layer (107), the present invention is not limited thereto. For example, the third gate insulating layer (109) may have substantially the same pattern and / or the same width as the first gate electrode (G1) to be described later. That is, after forming an insulating layer for forming the third gate insulating layer (109) and forming a conductive layer for forming the first gate electrode (G1) on this insulating layer, the insulating layer and the conductive layer may be simultaneously patterned into the same shape to form the third gate insulating layer (109) and the first gate electrode (G1). In this case, the third gate insulating layer (109) may not contact the upper surface of the first interlayer insulating layer (107).

[0183] A first gate electrode (G1) may be disposed on the third gate insulating layer (109). The first gate electrode (G1) may overlap the channel region (C1) of the first semiconductor layer (A1). The first gate electrode (G1) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. For example, the first gate electrode (G1) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0184] A second interlayer insulating layer (111) may be disposed on the first gate electrode (G1) to cover the first gate electrode (G1). The second interlayer insulating layer (111) may be an inorganic insulating layer including an inorganic insulator such as silicon oxide, silicon nitride, and / or silicon oxynitride. This second interlayer insulating layer (111) may have a single-layer structure or a multi-layer structure. For example, the second interlayer insulating layer (111) may have a laminated structure of a layer including silicon oxide and a layer including silicon oxynitride.

[0185] A first connection electrode (1710), a second connection electrode (1720), and a third connection electrode (1730) may be arranged on the second interlayer insulating layer (111). The first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730) may include the same material. That is, the first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730) may be formed simultaneously from the same material. The first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. For example, the first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0186] A first organic insulating layer (113) may be arranged on the first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730) to cover them. The first organic insulating layer (113) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0187] A data line (DL) and an initialization voltage line (VL) may be arranged on the first organic insulating layer (113). The data line (DL) and the initialization voltage line (VL) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. For example, the data line (DL) and the initialization voltage line (VL) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0188] A second organic insulating layer (115) may be arranged on the data line (DL) and the initialization voltage line (VL) to cover them. The second organic insulating layer (115) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0189] A voltage layer (1900) may be disposed on the second organic insulating layer (115). The voltage layer (1900) may have a voltage level of a driving voltage line (PL). The voltage layer (1900) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials. For example, the voltage layer (1900) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0190] A third organic insulating layer (117) may be disposed on the voltage layer (1900) to cover the voltage layer (1900). The third organic insulating layer (117) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0191] A light-emitting diode (LED) may be placed on the third organic insulating layer (117). The light-emitting diode (LED) may include a pixel electrode (210), an intermediate layer (220), and a common electrode (230) on the third organic insulating layer (117).

[0192] The pixel electrode (210) may be a (semi)transparent electrode or a reflective electrode. For example, the pixel electrode (210) may include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr or a compound thereof, and a transparent or translucent electrode layer positioned on the reflective layer. The transparent or translucent electrode layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO). x : It may include at least one selected from the group including ZnO or ZnO2), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode (210) may have a three-layer structure of ITO / Ag / ITO.

[0193] A pixel definition film (119) may be disposed on the third organic insulating layer (117). The pixel definition film (119) may cover the edge of the pixel electrode (210) and increase the distance between the pixel electrode (210) and the common electrode (230) above, thereby preventing arcs from occurring at the edge of the pixel electrode (210). That is, the pixel definition film (119) may have an opening to expose the central portion of the pixel electrode (210). The pixel definition film (119) may be formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by a method such as spin coating.

[0194] At least a portion of an intermediate layer (220) including an emission layer of a light emitting diode (LED) may be disposed within an opening formed in a pixel defining layer (119). An emission area of ​​the light emitting diode (LED) may be defined by this opening. This intermediate layer (220) may include an emission layer. The emission layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emission layer may be a low-molecular organic material or a high-molecular organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be further selectively disposed below and above the emission layer.

[0195] Alternatively, the intermediate layer (220) may include a first stack including a light-emitting layer and a functional layer, a second stack including a light-emitting layer and a functional layer, and a charge generation layer between the first stack and the second stack. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. In the case of a tandem light-emitting diode (LED) having a plurality of light-emitting layers by the negative charge generation layer and the positive charge generation layer, the light-emitting efficiency can be further increased.

[0196] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0197] The light-emitting layer may have a patterned shape corresponding to the pixel electrode (210). Layers other than the light-emitting layer included in the intermediate layer may be modified in various ways, such as being integral with a plurality of pixel electrodes (210).

[0198] The common electrode (230) may be a transparent electrode or a reflective electrode. For example, the common electrode (230) may be a transparent or semitransparent electrode, and may include a metal thin film with a small work function, such as Li, Ca, Al, Ag, Mg, or a compound thereof (e.g., LiF). In addition, the common electrode (230) may further include a TCO (transparent conductive oxide) film, such as ITO, IZO, ZnO, ZnO2, or In2O3, positioned on the metal thin film.

[0199] The common electrode (230) may be formed as a single body over the entire display area (DA) to cover the display area (DA), and may be arranged on the upper portion of the intermediate layer (220) and the pixel definition film (119). That is, each of the pixel electrodes (210) is arranged to correspond to each light-emitting diode (LED), and the common electrode (230) may be formed as a single body to correspond to a plurality of light-emitting diodes (LEDs). The plurality of light-emitting diodes (LEDs) may share the common electrode (230), and the stacked structure of the pixel electrode (210), the intermediate layer (220), and the common electrode (230) may correspond to a light-emitting diode (LED).

[0200] If necessary, an encapsulation layer may be disposed on the light emitting diode (LED). The encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer therebetween.

[0201] Figures 12 to 20 are layout diagrams schematically illustrating components such as transistors and capacitors of the display panel (10) illustrated in Figure 10, layer by layer. For convenience of explanation, the first pixel circuit (PC1) is described as being located in the i-th row and j-th column, and the second pixel circuit (PC2) is described as being located in the i-th row and j+1-th column.

[0202] As illustrated in Fig. 12, a lower metal layer (1110) may be disposed on a substrate (100). The lower metal layer (1110) may include a first portion (1111) extending along a second direction (y-axis direction), and a second portion (1112) and a third portion (1113) connected to the first portion (1111) and extending approximately along the first direction (x-axis direction).

[0203] The first part (1111) of the lower metal layer (1110) may be positioned on an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The second part (1112) and the third part (1113) of the lower metal layer (1110) may be positioned on opposite sides with the first part (1111) therebetween. The second part (1112) and the third part (1113) may extend overall along the first direction (e.g., the x-direction), but may be locally bent. The lower metal layer (1110) may include a metallic material as described above.

[0204] A buffer layer (101) may be formed on the lower metal layer (1110) illustrated in Fig. 12, and a silicon semiconductor layer (1210) may be formed on the buffer layer (101) as illustrated in Fig. 13. The silicon semiconductor layer (1210) may include silicon, for example, polysilicon.

[0205] As illustrated in FIG. 13, the silicon semiconductor layer (1210) may have an isolated shape but may have a shape extending approximately along the first direction (x-axis direction). The silicon semiconductor layer (1210) may intersect an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The silicon semiconductor layer (1210) may include a fifth semiconductor layer (A5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). In other words, the fifth semiconductor layer (A5) of the first pixel circuit (PC1) and the fifth semiconductor layer (A5) of the second pixel circuit (PC2) may be integral.

[0206] The silicon semiconductor layer (1210) may overlap with the lower metal layer (1110). For example, the silicon semiconductor layer (1210) may overlap with the third portion (1113) of the lower metal layer (1110). Accordingly, the fifth semiconductor layer (A5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may overlap with the third portion (1113) of the lower metal layer (1110).

[0207] A first gate insulating layer (103) may be formed on the structure illustrated in Fig. 13, and a gate line and a conductive layer as illustrated in Fig. 14 may be formed on the first gate insulating layer (103). Fig. 14 illustrates that a first emission control line (EML), a first conductive layer (1310), a second conductive layer (1320), a third conductive layer (1330), and a fourth conductive layer (1340) are formed on the first gate insulating layer (103).

[0208] As illustrated in FIG. 14, the first emission control line (EML), the first conductive layer (1310), the second conductive layer (1320), the third conductive layer (1330), and the fourth conductive layer (1340) can be arranged spaced apart from each other. The first emission control line (EML), the first conductive layer (1310), the second conductive layer (1320), the third conductive layer (1330), and the fourth conductive layer (1340) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials.

[0209] The first emission control line (EML) can extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The first emission control line (EML) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0210] The first emission control line (EML) may include a fifth gate electrode (G5) of each of the fifth transistors (T5) of the first pixel circuit (PC1) and the second pixel circuit (PC2). A portion of the first emission control line (EML) may protrude to overlap with a fifth semiconductor layer (A5) of the fifth transistor (T5), and a portion of the protruding first emission control line (EML) may correspond to the fifth gate electrode (G5) of the fifth transistor (T5). The fifth semiconductor layer (A5) of the fifth transistor (T5) may include a channel region (C5) overlapping with the fifth gate electrode (G5), and conductive regions (S5, D5) disposed on both sides of the channel region (C5) and being conductive by being doped with impurities or subjected to plasma treatment. One of the conductive regions (S5, D5) may be a source region, and the other may be a drain region. The source region and drain region may correspond to the source electrode and the drain electrode, respectively. The positions of the source region and drain region may be swapped depending on the properties of the transistor.

[0211] The first conductive layer (1310) and the third conductive layer (1330) may each have an isolated shape. The second conductive layer (1320) may also have an isolated shape, but may be integral with the adjacent first pixel circuit (PC1) and second pixel circuit (PC2). The fourth conductive layer (1340) may also have an isolated shape, but may be integral with the first pixel circuit (PC1) and the pixel circuit located in the j-1th column, and may also be integral with the second pixel circuit (PC2) and the pixel circuit located in the j+2th column. In the first pixel circuit (PC1) and the second pixel circuit (PC2), the first conductive layer (1310), the second conductive layer (1320), the third conductive layer (1330), and the fourth conductive layer (1340) may be symmetrical with respect to the aforementioned virtual line (IML).

[0212] The second conductive layer (1320) may have an isolated shape and may have a shape extending approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The second conductive layer (1320) may intersect an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The second conductive layer (1320) may include a stem portion extending along the first direction (x-axis direction) and a branch portion branching from the stem portion and protruding along the second direction (y-axis direction). The branch portion of the first pixel circuit (PC1) and the branch portion of the second pixel circuit (PC2) may be substantially symmetrical with respect to the imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0213] The second conductive layer (1320) may include a first lower hold electrode (CEh1a) which is a sublayer of the first hold electrode (CEh1) of the hold capacitor (Chd). The first lower hold electrode (CEh1a) of the hold capacitor (Chd) of the first pixel circuit (PC1) may be integral with the first lower hold electrode (CEh1a) of the hold capacitor (Chd) of the second pixel circuit (PC2).

[0214] The third conductive layer (1330) located in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include a first storage electrode (CEs1) of the storage capacitor (Cst).

[0215] A second gate insulating layer (105) may be formed on the structure illustrated in FIG. 14, and a gate line and a conductive layer as illustrated in FIG. 15 may be formed on the second gate insulating layer (105). FIG. 15 illustrates that an initialization gate line (GBL), a reference gate line (GRL), and a fifth conductive layer (1410) are formed on the second gate insulating layer (105).

[0216] An initialization gate line (GBL), a reference gate line (GRL), and a fifth conductive layer (1410) are arranged to be spaced apart from each other. The initialization gate line (GBL), the reference gate line (GRL), and the fifth conductive layer (1410) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials.

[0217] Each of the initialization gate line (GBL) and the reference gate line (GRL) may extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). Each of the initialization gate line (GBL) and the reference gate line (GRL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0218] The fifth conductive layer (1410) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The fifth conductive layer (1410) disposed in the first pixel circuit (PC1) and the fifth conductive layer (1410) disposed in the second pixel circuit (PC2) may be spaced apart from each other and may be substantially symmetrical with respect to the aforementioned virtual line (IML). The fifth conductive layer (1410) may overlap the third conductive layer (1330) of the first pixel circuit (PC1), the third conductive layer (1330) of the second pixel circuit (PC2), and the second conductive layer (1320) passing through the first pixel circuit (PC1) and the second pixel circuit (PC2). This fifth conductive layer (1410) may include a second hold electrode (CEh2) of the hold capacitor (Chd) and a second storage electrode (CEs2) of the storage capacitor (Cst). That is, the second hold electrode (CEh2) of the hold capacitor (Chd) and the second storage electrode (CEs2) of the storage capacitor (Cst) may be integral.

[0219] A first interlayer insulating layer (107) can be formed on the structure illustrated in Fig. 15, and semiconductor patterns such as those illustrated in Fig. 16 can be formed on the first interlayer insulating layer (107). Fig. 16 illustrates that a first oxide semiconductor pattern (1510), a second oxide semiconductor pattern (1520), a third oxide semiconductor pattern (1530), and a fourth oxide semiconductor pattern (1540) are formed on the first interlayer insulating layer (107).

[0220] As illustrated in FIG. 16, the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may be arranged to be spaced apart from each other. The first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may each include ITZO (InSnZnO), IGZO (InGaZnO), or the like.

[0221] The first oxide semiconductor pattern (1510) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The first oxide semiconductor pattern (1510) may include a first semiconductor layer (A1), a fourth semiconductor layer (A4), and a sixth semiconductor layer (A6). That is, the first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) of the first pixel circuit (PC1) may be integral, and the first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) of the second pixel circuit (PC2) may be integral. This first oxide semiconductor pattern (1510) may have a shape that is folded several times.

[0222] The first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) included in the first oxide semiconductor pattern (1510) may overlap with the fifth conductive layer (1410) and the initialization gate line (GBL) described above with reference to FIG. 15, and the fourth conductive layer (1340) described with reference to FIG. 14, respectively. That is, the portion overlapping with the fifth conductive layer (1410) of the first oxide semiconductor pattern (1510) may be the first semiconductor layer (A1), the portion overlapping with the initialization gate line (GBL) of the first oxide semiconductor pattern (1510) may be the fourth semiconductor layer (A4), and the portion overlapping with the fourth conductive layer (1340) of the first oxide semiconductor pattern (1510) may be the sixth semiconductor layer (A6).

[0223] For reference, in the plan view, the shape of the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) and the shape of the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) may be different from each other. The first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) may be arranged in the same row as the first pixel circuit (PC), but may extend in the direction of a pixel circuit of an adjacent column, for example, a pixel circuit arranged in the i-th row and the j-1-th column, so as to be integral with the first oxide semiconductor pattern of the pixel circuit arranged in the j-1-th column.

[0224] The second oxide semiconductor pattern (1520) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The second oxide semiconductor pattern (1520) may be bent to have an approximate "L" shape. The second oxide semiconductor pattern (1520) of the first pixel circuit (PC1) and the second oxide semiconductor pattern (1520) of the second pixel circuit (PC2) may be symmetrical with respect to the aforementioned imaginary line (IML).

[0225] The second oxide semiconductor pattern (1520) may include a second semiconductor layer (A2) of the second transistor (T2) and a third semiconductor layer (A3) of the third transistor (T3). That is, the second semiconductor layer (A2) of the second transistor (T2) and the third semiconductor layer (A3) of the third transistor (T3) may be connected integrally. The second semiconductor layer (A2) and the third semiconductor layer (A3) included in the second oxide semiconductor pattern (1520) may overlap with the reference gate line (GRL) described above with reference to FIG. 15 and the first conductive layer (1310) described with reference to FIG. 14, respectively. That is, the portion overlapping with the reference gate line (GRL) of the second oxide semiconductor pattern (1520) may be the third semiconductor layer (A3), and the portion overlapping with the first conductive layer (1310) of the second oxide semiconductor pattern (1520) may be the second semiconductor layer (A2).

[0226] The third oxide semiconductor pattern (1530) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The third oxide semiconductor pattern (1530) of the first pixel circuit (PC1) and the third oxide semiconductor pattern (1530) of the second pixel circuit (PC2) may be symmetrical with respect to the aforementioned virtual line (IML).

[0227] The third oxide semiconductor pattern (1530) may overlap with the fifth conductive layer (1410) described with reference to FIG. 15 and the second conductive layer (1320) described with reference to FIG. 14. The third oxide semiconductor pattern (1530) may include a first upper hold electrode (CEh1b), which is a sublayer of the first hold electrode (CEh1) of the hold capacitor (Chd).

[0228] The fourth oxide semiconductor pattern (1540) may be arranged on the first pixel circuit (PC1). The fourth oxide semiconductor pattern (1540) may be arranged at a position corresponding to one end of the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2), and may correspond to a type of dummy electrode.

[0229] Each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may include at least a partially conductive region. For example, at least a portion of each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may be treated with a plasma or the like to make the treated portion conductive. The third oxide semiconductor pattern (1530) including the first upper hold electrode (CEh1b) may have an entire conductive region to form a hold capacitor (Chd).

[0230] After forming a third gate insulating layer (109) on the structure illustrated in FIG. 16 and forming a contact hole (CNT) as illustrated in FIG. 17 in the third gate insulating layer (109), a second emission control line (EMBL), a horizontal reference voltage line (VRHL), a horizontal initialization voltage line (VHL), a first electrode layer (1610), a second electrode layer (1620), a third electrode layer (1630), and a fourth electrode layer (1640) as illustrated in FIG. 17 can be formed on the third gate insulating layer (109). The horizontal initialization voltage line (VHL), the second emission control line (EMBL), the horizontal reference voltage line (VRHL), the first electrode layer (1610), the second electrode layer (1620), the third electrode layer (1630), and the fourth electrode layer (1640) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials.

[0231] The horizontal initialization voltage line (VHL) may extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). Depending on the position of the first pixel circuit (PC1) within the display area (DA), the horizontal initialization voltage line (VHL) may be electrically connected to the initialization voltage line (VL) described later with reference to FIG. 19.

[0232] The horizontal reference voltage line (VRHL) may extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The horizontal reference voltage line (VRHL) may be electrically connected to a reference voltage line (VRL) which will be described later with reference to FIG. 19.

[0233] For reference, in the case of pixel circuits located in the i-th row as illustrated in FIG. 17, and pixel circuits located in the i-2-th row and the i+2-th row (not illustrated), a horizontal reference voltage line (VRHL) extended in the first direction (x-axis direction) may pass. In addition, in the case of pixel circuits located in the i-1-th row and the i+1-th row, a horizontal initialization voltage line (VHL) extended in the first direction (x-axis direction) may pass. That is, horizontal reference voltage lines (VRHL) and horizontal initialization voltage lines (VHL) extended in the first direction (x-axis direction) may be alternately positioned in the second direction (y-axis direction).

[0234] The second emission control line (EMBL) can extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The second emission control line (EMBL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0235] The first electrode layer (1610) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) has an isolated shape and may include the first gate electrode (G1) of the first transistor (T1). That is, the first electrode layer (1610) corresponds to the first gate electrode (G1), and the portion overlapping the first electrode layer (1610) of the first oxide semiconductor pattern (1510) becomes a channel region (C1), and both sides of the channel region (C1) may be conductive regions (S1, D1) doped with impurities or processed with plasma to be conductive. One of the conductive regions (S1, D1) may be a source region and the other may be a drain region. The source region and the drain region may correspond to the source electrode and the drain electrode. Of course, the positions of the source region and the drain region may be switched depending on the properties of the transistor.

[0236] The second electrode layer (1620) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include a third gate electrode (G3) of a third transistor (T3). The second electrode layer (1620) of the first pixel circuit (PC1) may be integral with the second electrode layer of a pixel circuit arranged in the same row as the first pixel circuit (PC) but in an adjacent column, for example, a pixel circuit arranged in the i-th row and the j-1-th column. This second electrode layer (1620) may have an isolated shape and may include a third gate electrode (G3) of the third transistor (T3). That is, a part of the second electrode layer (1620) corresponds to the third gate electrode (G3), and a part of the second oxide semiconductor pattern (1520) overlapping with the second electrode layer (1620) becomes a channel region (C3), and both sides of this channel region (C3) may be conductive regions (S3, D3) doped with impurities or treated with plasma to become conductive. One of the conductive regions (S3, D3) may be a source region and the other may be a drain region. The source region and the drain region may correspond to the source electrode and the drain electrode. Of course, the positions of the source region and the drain region may be switched depending on the properties of the transistor.

[0237] The second electrode layer (1620) may be electrically connected to a reference gate line (GRL) disposed on the lower side of the third semiconductor layer (A3) through a contact hole (CNT). At this time, a part of the second electrode layer (1620) and a part of the reference gate line (GRL) may overlap each other with the channel region (C3) of the third transistor (T3) therebetween. A part of the reference gate line (GRL) overlapping the channel region (C3) of the third transistor (T3) may correspond to the lower gate electrode of the third transistor (T3), and the switching performance of the third transistor (T3) may be improved through such a dual gate structure.

[0238] The third electrode layer (1630) may extend approximately along the first direction (x-axis direction) and may have an integral yet isolated shape with respect to the first pixel circuit (PC1) and the second pixel circuit (PC2). The third electrode layer (1630) may intersect the aforementioned virtual line (IML). This third electrode layer (1630) may include the second gate electrode (G2) of the second transistor (T2). That is, a part of the third electrode layer (1630) corresponds to the second gate electrode (G2), and a portion overlapping the third electrode layer (1630) of the second oxide semiconductor pattern (1520) becomes a channel region (C2), and both sides of this channel region (C2) may be conductive regions (S2, D2) that are doped with impurities or processed with plasma to be conductive. One of the challenge regions (S2, D2) may be a source region and the other may be a drain region. The source and drain regions may correspond to the source and drain electrodes. Of course, the positions of the source and drain regions may be interchanged depending on the characteristics of the transistor.

[0239] This third electrode layer (1630) is electrically connected to a scan line (GWL) to be described later with reference to FIG. 18. In addition, the third electrode layer (1630) may be electrically connected to a first conductive layer (1310) disposed under the second semiconductor layer (A2) through a contact hole (CNT). The third electrode layer (1630) and the first conductive layer (1310) may overlap each other with the channel region (C2) of the second transistor (T2) interposed therebetween. The first conductive layer (1310) may correspond to a lower gate electrode of the second transistor (T2), and the switching performance of the second transistor (T2) may be improved through such a double gate structure.

[0240] The fourth electrode layer (1640) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include a fourth gate electrode (G4) of a fourth transistor (T4). The fourth electrode layer (1640) of the first pixel circuit (PC1) may be formed integrally with the fourth electrode layer of a pixel circuit arranged in the same row as the first pixel circuit (PC) but in an adjacent column, for example, a pixel circuit arranged in the i-th row and the j-1-th column. This fourth electrode layer (1640) may have an isolated shape and may include a fourth gate electrode (G4) of the fourth transistor (T4). That is, a part of the fourth electrode layer (1640) corresponds to the fourth gate electrode (G4), and a portion overlapping the fourth electrode layer (1640) of the first oxide semiconductor pattern (1510) becomes a channel region (C4), and both sides of this channel region (C4) may be conductive regions (S4, D4) doped with impurities or treated with plasma to become conductive. One of the conductive regions (S4, D4) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. Of course, the positions of the source region and the drain region may be switched depending on the properties of the transistor.

[0241] The fourth electrode layer (1640) may be electrically connected to an initialization gate line (GBL) disposed on the lower side of the fourth semiconductor layer (A4) through a contact hole (CNT). A portion of the fourth electrode layer (1640) and a portion of the initialization gate line (GBL) may overlap each other with the channel region (C4) of the fourth transistor (T4) interposed therebetween. A portion of the initialization gate line (GBL) overlapping the channel region (C4) of the fourth transistor (T4) may correspond to the lower gate electrode of the fourth transistor (T4), and the switching performance of the fourth transistor (T4) may be improved through such a dual gate structure.

[0242] The second emission control line (EMBL) may include the sixth gate electrode (G6) of the sixth transistor (T6). That is, a part of the second emission control line (EMBL) corresponds to the sixth gate electrode (G6), and a portion of the first oxide semiconductor pattern (1510) overlapping with the second emission control line (EMBL) becomes a channel region (C6), and both sides of the channel region (C6) may be conductive regions (S6, D6) doped with impurities or processed with plasma to be conductive. One of the conductive regions (S6, D6) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode. The positions of the source region and the drain region may be exchanged depending on the properties of the transistor.

[0243] The second emission control line (EMBL) can be electrically connected to the fourth conductive layer (1340) disposed under the sixth semiconductor layer (A6) through a contact hole (CNT). A portion of the second emission control line (EMBL) and the fourth conductive layer (1340) can overlap each other with the channel region (C6) of the sixth transistor (T6) interposed therebetween. The fourth conductive layer (1340) can correspond to the lower gate electrode of the sixth transistor (T6), and the switching performance of the fourth transistor (T4) can be improved through such a dual gate structure.

[0244] After forming a second interlayer insulating layer (111) on the structure illustrated in FIG. 17 and forming a contact hole (CNT') as illustrated in FIG. 18 in the second interlayer insulating layer (111), a scan line (GWL), a first connection electrode (1710), a second connection electrode (1720), a third connection electrode (1730), a fourth connection electrode (1740), a fifth connection electrode (1750), a sixth connection electrode (1760), a seventh connection electrode (1770), an eighth connection electrode (1780), and a horizontal connection line (DHL) as illustrated in FIG. 18 can be formed on the second interlayer insulating layer (111). The scan line (GWL), the first connection electrode (1710), the second connection electrode (1720), the third connection electrode (1730), the fourth connection electrode (1740), the fifth connection electrode (1750), the sixth connection electrode (1760), the seventh connection electrode (1770), the eighth connection electrode (1780), and the horizontal connection line (DHL) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may have a single-layer structure or a multi-layer structure including such materials.

[0245] The scan line (GWL) can extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The scan line (GWL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0246] The first connection electrode (1710) has an isolated shape that is integral with the first pixel circuit (PC1) and the second pixel circuit (PC2), and can extend approximately along the first direction (x-axis direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The first connection electrode (1710) can intersect an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0247] This first connection electrode (1710) is electrically connected to the second conductive layer (1320) through a contact hole (CNT') and can also be electrically connected to the third oxide semiconductor pattern (1530) through the contact hole (CNT'). In addition, the first connection electrode (1710) can be electrically connected to the fifth semiconductor layer (A5) of the fifth transistor (T5) through the contact hole (CNT') (located in the -y direction). Since the first connection electrode (1710) is electrically connected to a voltage layer (1900, FIG. 20) to be described later, the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b) can be electrically connected to the voltage layer (1900), and the fifth transistor (T5, FIG. 16) can be electrically connected to the voltage layer (1900).

[0248] The second connection electrode (1720) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The second connection electrode (1720) may be electrically connected to the first semiconductor layer (A1) of the first transistor (T1) through a contact hole (CNT') and may be electrically connected to the fifth semiconductor layer (A5) of the fifth transistor (T5) through the contact hole (CNT'). Accordingly, the second connection electrode (1720) may electrically connect the first transistor (T1) and the fifth transistor (T5).

[0249] The third connection electrode (1730) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The third connection electrode (1730) may correspond to the first node (N1) in the pixel circuit of FIG. 9. The third connection electrode (1730) may be electrically connected to the first electrode layer (1610) corresponding to the first gate electrode (G1) of the first transistor (T1) through a contact hole (CNT'), may be electrically connected to the third semiconductor layer (A3) through the contact hole (CNT'), and may be electrically connected to the third conductive layer (1330) through the contact hole (CNT'). Accordingly, the third connection electrode (1730) can electrically connect the first gate electrode (G1) of the first transistor (T1), the third transistor (T3), and the first storage electrode (CEs1).

[0250] The fourth connection electrode (1740) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The fourth connection electrode (1740) may correspond to the second node (N2) in the pixel circuit of FIG. 9. The fourth connection electrode (1740) may be electrically connected to the fifth conductive layer (1410) including the second storage electrode (CEs2) and the second hold electrode (CEh2) through a contact hole (CNT'), and may be electrically connected to the first oxide semiconductor pattern (1510) through the contact hole (CNT'). The connection point of the fourth connection electrode (1740) and the first oxide semiconductor pattern (1510) may be located between an area corresponding to the first semiconductor layer (A1) and an area corresponding to the sixth semiconductor layer (A6, FIG. 15) among the first oxide semiconductor pattern (1510). Through this, the fourth connection electrode (1740) may electrically connect the second storage electrode (CEs2), the second hold electrode (CEh2), the first transistor (T1), and the sixth transistor (T6).

[0251] The fifth connection electrode (1750) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) has an isolated shape, but may be integral with the first pixel circuit (PC1) and the pixel circuit positioned in the j-1th column, and may also be integral with the second pixel circuit (PC2) and the pixel circuit positioned in the j+2th column. The fifth connection electrode (1750) may be electrically connected to the third semiconductor layer (A3) through a contact hole (CNT'). The fifth connection electrode (1750) may be electrically connected to a reference voltage line (VRL, FIG. 19) to be described later, and may transmit a reference voltage (VREF) to the third transistor (T3).

[0252] The sixth connection electrode (1760) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The sixth connection electrode (1760) may be electrically connected to the second semiconductor layer (A2) through a contact hole (CNT'). The sixth connection electrode (1760) may be electrically connected to a data line (DL, FIG. 19) to be described later, and may transmit a data signal (DATA) to the second transistor (T2).

[0253] The seventh connection electrode (1770) located in the second pixel circuit (PC2) may have an isolated shape. In the second pixel circuit (PC2), the seventh connection electrode (1770) may be electrically connected to the fourth semiconductor layer (A4) of the fourth transistor (T4) through a contact hole (CNT'). The seventh connection electrode (1770) may be electrically connected to a second initialization voltage line (VL2, FIG. 19) to be described later, and may transmit the initialization voltage (VINT) to the fourth transistor (T4). For reference, the fourth transistor (T4) located in the first pixel circuit (PC1) located in the j-th column is electrically connected to the fourth transistor of the pixel circuit located in the j-1-th column (adjacent in the -x direction), as illustrated in FIG. 16. Accordingly, the fourth transistor (T4) located in the first pixel circuit (PC1) can be electrically connected to the initialization voltage line (not shown) passing through the pixel circuit located in the j-1th column (adjacent in the -x direction), rather than the first initialization voltage line (VL1, FIG. 19) passing through the first pixel circuit (PC1).

[0254] The dummy connection electrode (1770') located in the first pixel circuit (PC1) may have an isolated shape. The dummy connection electrode (1770') may be electrically connected to the fourth oxide semiconductor pattern (1540), which is also a dummy pattern, through a contact hole (CNT').

[0255] The eighth connection electrode (1780) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The eighth connection electrode (1780) may be electrically connected to the first oxide semiconductor pattern (1510) through a contact hole (CNT'). The connection point of the eighth connection electrode (1780) and the first oxide semiconductor pattern (1510) may be positioned between an area corresponding to the sixth semiconductor layer (A6) and an area corresponding to the fourth semiconductor layer (A4) among the first oxide semiconductor pattern (1510). Through this, the eighth connection electrode (1780) may be electrically connected to the sixth semiconductor layer (A6) and the fourth semiconductor layer (A4), that is, to the fourth transistor (T4) and the sixth transistor (T6). As described below, the eighth connection electrode (1780) is electrically connected to the pixel electrode of the light emitting diode (LED), so the eighth connection electrode (1780) can electrically connect the fourth transistor (T4) and the sixth transistor (T6) to the pixel electrode.

[0256] The horizontal connection line (DHL) extending approximately in the first direction (x-axis direction) may correspond to a portion of the data transmission line (DTL) described with reference to FIG. 7 or FIG. 8, for example, one of the first horizontal connection line (DHL1), the second horizontal connection line (DHL2), or the third horizontal connection line (DHL3). As illustrated in FIG. 18, the horizontal connection line (DHL) has a portion protruding in the second direction (y-axis direction), and if it is necessary to be electrically connected to the vertical connection line (DVL), the protruding portion may be electrically connected to the vertical connection line (DVL).

[0257] In this way, a first organic insulating layer (113) is formed on the structure described with reference to FIG. 18, and first via contact holes (VCNT1) are formed in the first organic insulating layer (113), and then, as shown in FIG. 19, a data line (DL), a vertical connection line (DVL), an initialization voltage line (VL), a reference voltage line (VRL), a ninth connection electrode (1810), and a tenth connection electrode (1820) can be formed on the first organic insulating layer (113).

[0258] Each of the data line (DL), the vertical connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) may extend along the second direction (y-axis direction). The data line (DL), the vertical connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) passing through the first pixel circuit (PC1), and the data line (DL), the vertical connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) passing through the second pixel circuit (PC2) may be substantially symmetrical with respect to an imaginary line (IML).

[0259] The data line (DL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) is electrically connected to the sixth connection electrode (1760) described with reference to FIG. 18 through the first via contact hole (VCNT1), thereby providing a data signal to the second transistor (T2).

[0260] The vertical connection line (DVL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may correspond to a portion of the data transmission line (DTL) described with reference to FIG. 7 or 8, for example, any one of the first vertical connection line (DVL1), the second vertical connection line (DVL2), the third vertical connection line (DVL3), the first additional vertical connection line (DVL1'), the second additional vertical connection line (DVL2'), and the third additional vertical connection line (DVL3'). The vertical connection line (DVL) has a portion protruding in the first direction (x-axis direction), and thus, when it is necessary to be electrically connected to the horizontal connection line (DHL) located below, the vertical connection line (DVL) may be electrically connected to the horizontal connection line (DHL) through a via contact hole formed in the first organic insulating layer (113) at the protruding portion.

[0261] The second initialization voltage line (VL2) passing through the second pixel circuit (PC2) is electrically connected to the seventh connection electrode (1770) at the bottom through the first via contact hole (VCNT1), and the seventh connection electrode (1770) is electrically connected to the first oxide semiconductor pattern (1510) at the bottom through the contact hole (CNT') to provide an initialization voltage to the fourth transistor (T4) of the second pixel circuit (PC2). In addition, FIG. 18 illustrates a pixel circuit located in the +y direction of the first pixel circuit (PC1), a pixel circuit located in the +y direction of the second pixel circuit (PC2), and a seventh connection electrode (1770) having a substantially similar shape located in each of the first pixel circuit (PC1) and the second pixel circuit (PC2). Among these, the seventh connection electrode (1770) located in the pixel circuit located in the +y direction of the second pixel circuit (PC2) is electrically connected to the first oxide semiconductor pattern (1510) below through a contact hole (CNT') and is also electrically connected to the protrusion of the horizontal initialization voltage line (VHL) below through another contact hole (CNT'). Accordingly, the horizontal initialization voltage lines (VHL) extending in the first direction (x-axis direction) and the second initialization voltage lines (VL2) extending in the second direction (y-axis direction) are electrically connected to each other to form a mesh structure overall, so that the initialization voltage (VINT) supplied by the second initialization voltage lines (VL2) in the display area (DA) can be maintained approximately uniformly. This will be described later.

[0262] Of course, the horizontal initialization voltage line (VHL) located in a row other than the i-1th row as illustrated in FIG. 17, for example, the i+1th row, can be electrically connected to the first initialization voltage line (VL1). In this way, the horizontal initialization voltage lines (VHL) extending in the first direction (x-axis direction) and the first initialization voltage lines (VL1) extending in the second direction (y-axis direction) are electrically connected to each other to form a mesh structure overall, thereby allowing the initialization voltage (VINT) supplied by the first initialization voltage lines (VL1) in the display area (DA) to be maintained approximately uniformly. This will be described later.

[0263] The first initialization voltage line (VL1) passing through the first pixel circuit (PC1) can be electrically connected to the dummy connection electrode (1770') through the first via contact hole (VCNT1). As described above with reference to FIG. 18, the fourth transistor (T4) located in the first pixel circuit (PC1) located in the j-th column is electrically connected to the fourth transistor of the pixel circuit located in the j-1-th column (adjacent in the -x direction) as illustrated in FIG. 16. Therefore, the fourth transistor (T4) located in the first pixel circuit (PC1) can be electrically connected to the initialization voltage line (not illustrated) passing through the pixel circuit located in the j-1-th column (adjacent in the -x direction), rather than the first initialization voltage line (VL1, FIG. 19) passing through the first pixel circuit (PC1).

[0264] The reference voltage line (VRL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) is electrically connected to the fifth connection electrode (1750) described above with reference to FIG. 18 through the first via contact hole (VCNT1), and the fifth connection electrode (1750) is electrically connected to the second oxide semiconductor pattern (1520) through the contact hole (CNT') to provide a reference voltage to the third transistor (T3). In addition, FIG. 18 illustrates that the fifth connection electrodes (1750) are positioned at the upper left, upper right, lower left, and lower right, respectively. In the case of the fifth connection electrodes (1750) positioned at the lower left and lower right, respectively, they are electrically connected to the horizontal reference voltage line (VRHL) through the contact hole (CNT'). Accordingly, the horizontal reference voltage lines (VRHL) extending in the first direction (x-axis direction) and the reference voltage lines (VRL) extending in the second direction (y-axis direction) are electrically connected to each other to form an overall mesh structure, thereby allowing the reference voltage (VREF) to be maintained approximately uniformly in the display area (DA). This will be described later.

[0265] For reference, the first pixel circuit (PC1) located in the j-th column can share a reference voltage line (VRL) with the pixel circuit located in the j-1th column adjacent in the -x direction, and the second pixel circuit (PC2) located in the j+1th column can share a reference voltage line (VRL) with the pixel circuit located in the j+2nd column adjacent in the +x direction.

[0266] The ninth connection electrode (1810) and the tenth connection electrode (1820) may each have an isolated shape. The ninth connection electrode (1810) located in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may be electrically connected to the first connection electrode (1710) described above with reference to FIG. 18 through the first via contact hole (VCNT1). The first connection electrode (1710) and the ninth connection electrode (1810) may electrically connect the voltage layer (1900) and the hold capacitor (Chd) described below. The tenth connection electrode (1820) located in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may be electrically connected to the eighth connection electrode (1780) described above with reference to FIG. 18 through the first via contact hole (VCNT1). The eighth connecting electrode (1780) and the tenth connecting electrode (1820) can electrically connect the pixel electrode of the light emitting diode (LED) to the fourth transistor (T4) and the sixth transistor (T6).

[0267] A second organic insulating layer (115) can be formed on the structure described with reference to FIG. 19, and second via contact holes (VCNT2) can be formed on the second organic insulating layer (115). And, as illustrated in FIG. 20, a voltage layer (1900) and an eleventh connection electrode (1955) can be formed on the second organic insulating layer (115).

[0268] As illustrated in FIG. 19, the voltage layer (1900) may include main parts (1910) that are spaced apart from each other and bridge parts (1920, 1930) connecting the main parts (1910). The main parts (1910) and the bridge parts (1920, 1930) may be integral, and the voltage layer (1900) may have a mesh structure as a whole to reduce the self-resistance of the voltage layer (1900). The connection structure of the main parts (1910) and the bridge parts (1920, 1930) may have a mesh shape on a plane. The voltage layer (1900) may include the driving voltage line (PL) described above with reference to FIG. 9. That is, the voltage layer (1900) may have the function of the driving voltage line (PL) described above with reference to FIG. 9.

[0269] The main parts (1910) may overlap with the voltage line or signal line therebelow. One of the main parts (1910) may be located on an imaginary line (IML) and may overlap with the data line (DL) and the vertical connection line (DVL) passing through the first pixel circuit (PC1) and the second pixel circuit (PC2), respectively. Another of the main parts (1910) may overlap with the reference voltage line (VRL) passing through the first pixel circuit (PC1). Still another of the main parts (1910) may overlap with the reference voltage line (VRL) passing through the second pixel circuit (PC2). The main parts (1910) may overlap with the light-emitting area (EA, FIG. 22) of the light-emitting diode (LED) to be described later.

[0270] The bridge portions (1920, 1930) may extend along a first diagonal direction (OB1) between a first direction (x-axis direction) and a second direction (y-axis direction), or may extend along a second diagonal direction (OB2) intersecting the first diagonal direction (OB1). Each of the bridge portions (1920, 1930) may connect adjacent main portions (1910). For example, among the bridge portions (1920, 1930), the first bridge portion (1920) may extend along the first diagonal direction (OB1) to connect two adjacent main portions (1910). Among the bridge portions (1920, 1930), the second bridge portion (1930) may extend along the second diagonal direction (OB2) to connect two adjacent main portions (1910).

[0271] The second bridge portion (1930) passing through the first pixel circuit (PC1) can be electrically connected to the ninth connection electrode (1810) located at the lower portion of the first pixel circuit (PC1) through the second via contact hole (VCNT2). The ninth connection electrode (1810) is electrically connected to the first connection electrode (1710) located at the first pixel circuit (PC1), and the first connection electrode (1710) can be electrically connected to the second conductive layer (1320) including the first lower hold electrode (CEh1a), the third oxide semiconductor pattern (1530) including the first upper hold electrode (CEh1b), and the fifth semiconductor layer (A5) of the fifth transistor (T5). The first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b) are the first hold electrode (CEh1) of the hold capacitor (Chd). Therefore, the driving voltage of the voltage layer (1900) can be transmitted to the fifth transistor (T5) of the first pixel circuit (PC1) and the first hold electrode (CEh1) of the hold capacitor (Chd).

[0272] The first bridge portion (1920) passing through the second pixel circuit (PC2) can be electrically connected to the ninth connection electrode (1810) located at the lower portion of the second pixel circuit (PC2) through the second via contact hole (VCNT2). The ninth connection electrode (1810) is electrically connected to the first connection electrode (1710) located at the second pixel circuit (PC2), and the first connection electrode (1710) can be electrically connected to the second conductive layer (1320) including the first lower hold electrode (CEh1a), the third oxide semiconductor pattern (1530) including the first upper hold electrode (CEh1b), and the fifth semiconductor layer (A5) of the fifth transistor (T5). The first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b) are the first hold electrode (CEh1) of the hold capacitor (Chd). Therefore, the driving voltage of the voltage layer (1900) can be transmitted to the fifth transistor (T5) of the second pixel circuit (PC2) and the first hold electrode (CEh1) of the hold capacitor (Chd).

[0273] The 11th connection electrode (1955) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. Each of the 11th connection electrodes (1955) may be electrically connected to the 10th connection electrode (1820) positioned at the lower portion of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) through the second via contact hole (VCNT2).

[0274] A third organic insulating layer (117) may be formed on a structure such as that illustrated in FIG. 20, and third via contact holes (VCNT3) may be formed in the third organic insulating layer (117). In addition, pixel electrodes (210) of a light-emitting diode (LED), which will be described later with reference to FIG. 21, may be arranged on the third organic insulating layer (117). Each pixel electrode (210) may be electrically connected to an 11th connection electrode (1955) of a corresponding pixel circuit through the third via contact hole (VCNT3).

[0275] Although the main portion (1910) is illustrated as having a circular shape in FIG. 20, the present invention is not limited thereto. For example, the main portion (1910) may have an oval shape, or a polygonal shape such as a square, pentagon, hexagon, or octagon.

[0276] Fig. 21 is a schematic layout diagram of pixel electrodes (210) of the display panel (10) illustrated in Fig. 10, and Fig. 22 is a schematic cross-sectional diagram taken along the line C-C' of Fig. 21. For reference, as illustrated in Fig. 21, the pixel electrode (210) may overlap with the initialization voltage line (VL), but for convenience of illustration, the initialization voltage line (VL) is omitted in Fig. 21. In addition, since the light-emitting diode includes the pixel electrode (210), the position of the pixel electrode (210) can be referred to as the position of the light-emitting diode.

[0277] As illustrated in FIG. 21, light emitting diodes (LEDs) may be arranged to be spaced apart from each other. FIG. 21 illustrates that a second light emitting diode (LED2) overlapping a first pixel circuit (PC1) and a second pixel circuit (PC2) is electrically connected to the first pixel circuit (PC1) located in the i-th row and the j-th column. In this way, the second light emitting diode (LED2) may be located on an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2), but as illustrated in FIG. 21, the pixel electrode (210) of the second light emitting diode (LED2) may have a protrusion protruding in the -x direction and may be electrically connected to the first pixel circuit (PC1) through a third via contact hole (VCNT3) located below the protrusion. Other light emitting diodes also have a pixel electrode (210) with a protrusion that can be electrically connected to a corresponding pixel circuit through a third via contact hole (VCNT3) underneath the protrusion.

[0278] Four third light-emitting diodes (LED3) can be arranged around the second light-emitting diode (LED2). In Fig. 21, the third light-emitting diodes (LED3) are shown as being positioned at the four corners of a square-shaped dotted line indicating the boundary of the set of the first pixel circuit (PC1) and the second pixel circuit (PC2). That is, in FIG. 21, the third light-emitting diode (LED3) located at the lower right is electrically connected to the second pixel circuit (PC2) located at the i-th row and the j+1-th column, the third light-emitting diode (LED3) located at the upper right is electrically connected to the pixel circuit located at the i-1-th row and the j+1-th column adjacent to the second pixel circuit (PC2) in the +y direction, the third light-emitting diode (LED3) located at the lower left is electrically connected to the pixel circuit located at the i-th row and the j-1-th column adjacent to the first pixel circuit (PC1) in the -x direction, and the third light-emitting diode (LED3) located at the upper left is electrically connected to the pixel circuit located at the i-1-th row and the j-1-th column.

[0279] For reference, the first light-emitting diode (LED1, see FIG. 26) may be electrically connected to a pixel circuit located at the (i-1)th row and the (j)th column adjacent to the first pixel circuit (PC1) in the +y direction. In addition, the first light-emitting diodes (LED1) may be electrically connected to a pixel circuit located at the (i-1)th row and the (j+2)th column adjacent to the second pixel circuit (PC2) in the +x direction, a pixel circuit located at the (i-1)th row and the (j-2)th column, and a pixel circuit located at the (i+1)th row and the (j)th column adjacent to the first pixel circuit (PC1) in the -y direction. In the case of the first light-emitting diode (LED1), similarly to the second light-emitting diode (LED2), four third light-emitting diodes (LED3) may be arranged around the first light-emitting diode (LED1) in the center.

[0280] In this way, the pixel circuits arranged in the +x direction in the i-th row may be a set of pixel circuits for the first light-emitting diode (LED1), pixel circuits for the third light-emitting diode (LED3), pixel circuits for the second light-emitting diode (LED2), and pixel circuits for the third light-emitting diode (LED3) that are repeated. And, the pixel circuits arranged in the y-axis direction in the j-th column may be a set of pixel circuits for the first light-emitting diode (LED1) and pixel circuits for the second light-emitting diode (LED2), and the pixel circuits arranged in the second direction (y-axis direction) in each of the j-1-th column and the j+1-th column may be pixel circuits for the third light-emitting diode (LED3).

[0281] For example, the first light-emitting diode may be a diode that emits red light, the second light-emitting diode (LED2) may be a diode that emits blue light, and the third light-emitting diode (LED3) may be a diode that emits green light.

[0282] As illustrated in FIGS. 21 and 22, each of the light emitting diodes (LEDs) can overlap with a corresponding one of the main portions (1910) of the voltage layer (1900). The light emitting area (EA) of each of the light emitting diodes (LEDs) can overlap with a corresponding one of the main portions (1910) of the voltage layer (1900).

[0283] The main portion (1910) of the voltage layer (1900) may be positioned between the pixel electrode (210) and the wires that provide signals, as illustrated in FIG. 22, and located below the pixel electrode (210) and the main portion (1910). The wires that provide signals may be, for example, data lines (DL) and vertical connection lines (DVL). The main portion (1910) may prevent or minimize parasitic capacitance from occurring between each of the data lines (DL) and / or the vertical connection lines (DVL) and the pixel electrode (210), thereby preventing or minimizing deterioration of display quality due to parasitic capacitance.

[0284] This voltage layer (1900) may correspond to the driving voltage line (PL) described above with reference to FIG. 9, and accordingly, the voltage layer (1900) may have a voltage level (e.g., constant voltage) of the driving voltage (ELVDD). However, the present invention is not limited thereto. For example, the voltage layer (1900) may have the same voltage level (e.g., constant voltage) as the common voltage (ELVSS), and in this case, the configuration corresponding to the driving voltage line may be arranged in the same layer as the data line (DL), etc.

[0285] The width (W1) of the main portion (1910) may be larger than the width of the light-emitting area (EA) of each light-emitting diode (LED), as illustrated in FIG. 22. The light-emitting area (EA) of the light-emitting diode (LED) may be defined by an opening (119OP) of a pixel definition film (119) covering an edge of a pixel electrode (210), and in this case, the width (W1) or area of ​​the main portion (1910) may be larger than the width or area of ​​the opening (119OP) overlapping the main portion (1910). Of course, the present invention is not limited thereto, and as illustrated in FIG. 23, which is a cross-sectional view schematically illustrating a cross-section of a display panel according to an embodiment of the present invention, the width (W1) of the main portion (1910) may be smaller than the width of the light-emitting area (EA) of the light-emitting diode (LED). That is, the width (W1) or area of ​​the main portion (1910) may be smaller than the width or area of ​​the opening (119OP) overlapping the pixel electrode (210).

[0286] As illustrated in FIG. 22, if the width (W1) of the main portion (1910) is greater than the width of the light-emitting area (EA), the portion of the pixel electrode (210) corresponding to the light-emitting area (EA) can be maintained in a relatively flat state. On the other hand, as illustrated in FIG. 23, if the width (W1) of the main portion (1910) is less than the width of the light-emitting area (EA), a portion of the upper surface of the third organic insulating layer (117) disposed below the pixel electrode (210) corresponding to the light-emitting area (EA) may not be flat in the light-emitting area (EA). For example, a first vertical distance (H1) between a portion of the pixel electrode (210) corresponding to the center of the light-emitting area (EA) and the substrate (100) may be greater than a second vertical distance (H2) between a portion of the pixel electrode (210) corresponding to the edge of the light-emitting area (EA) and the substrate (100). In the case of the structure illustrated in Fig. 22, sufficient brightness can be secured in the front direction (e.g., z-axis direction), and in the case of the structure illustrated in Fig. 23, brightness can be increased in an oblique direction other than the front direction (e.g., z-axis direction).

[0287] Fig. 24 is a plan view illustrating the voltage layer (1900) of Fig. 20. As illustrated in Fig. 24, the main parts (1910) may be arranged to be spaced apart from each other. As described above, the main parts (1910) may be arranged at the four corners of the rectangular shape (VSQ) indicated by the dotted lines that represent the edges of the set of the first pixel circuit (PC1) and the second pixel circuit (PC2) and at the center of such a rectangular shape (VSQ).

[0288] The sizes of the main parts (1910) may be different from each other. In Fig. 24, the size (or width) of the main part (1910) located at the center of the rectangular shape (VSQ) indicated by the dotted line is illustrated as being larger than the size (or width) of each of the main parts (1910) located at the vertices. However, the present invention is not limited thereto, and the size (or width) of the main part (1910) located at the center of the rectangular shape (VSQ) indicated by the dotted line may be smaller than the size (or width) of each of the main parts (1910) located at the vertices.

[0289] As illustrated in FIGS. 20 and 24, the first bridge portion (1920) and the second bridge portion (1930) connecting the main portions (1910) of the voltage layer (1900) extend along the first diagonal direction (OB1) and the second diagonal direction (OB2). Accordingly, the main portion (1910) located at the center of the rectangular shape (VSQ) indicated by the dotted line can be directly connected to the main portions (1910) located at the four corners.

[0290] FIG. 25 is a plan view schematically illustrating a voltage layer (1900) included in a display panel (10) according to one embodiment of the present invention. As illustrated in FIG. 25, a first bridge portion (1920) may extend in a first direction (x-axis direction) and a second bridge portion (1930) may extend in a second direction (y-axis direction). In this case, among the main portions (1910) located at the four vertices of a dotted line in a rectangular shape indicating the boundary of a set of a first pixel circuit (PC1) and a second pixel circuit (PC2), two main portions (1910) adjacent along the first direction (x-axis direction) may be connected to each other through the first bridge portion (1920) extending in the first direction (x-axis direction).

[0291] The main part (1910) located at the center of the dotted line in the shape of a rectangle indicating the boundary of the set of the first pixel circuit (PC1) and the second pixel circuit (PC2) can be connected to the first bridge part (1920) connecting the two main parts (1910) located at the vertices of the rectangle indicating the boundary of the set of the first pixel circuit (PC1) and the second pixel circuit (PC2) through the second bridge part (1930) extending in the second direction (y-axis direction). That is, the main part (1910) located at the center of the rectangle indicating the boundary of the set of the first pixel circuit (PC1) and the second pixel circuit (PC2) can be connected to the main parts (1910) located at the four vertices of the rectangle indicated by the dotted line through the first bridge parts (1920) through the second bridge parts (1930) extending in the +y direction and the -y direction.

[0292] In this way, in the case of the display panel (10) according to the present embodiment and the electronic device including the same, the occurrence of parasitic capacitance between the wiring providing the data signal and the pixel electrode (210) can be prevented or minimized through the shielding structure of the main part (1910) of the voltage layer (1900). In addition, since the switching transistors have a dual gate structure located below and above the semiconductor layer, the switching performance can be improved. In addition, by using oxide transistors, the display panel (10) and electronic device capable of high-speed driving, fast response speed, and providing high-quality images can be implemented.

[0293] FIG. 26 is a layout diagram schematically illustrating semiconductor layers (1510, 1520, 1530, 1540) included in a display panel (10) and an electronic device including the same according to one embodiment of the present invention, and FIG. 27 is a layout diagram schematically illustrating the positional relationship between the semiconductor layers (1510, 1520, 1530, 1540) and initialization voltage lines (VL) of FIG. 26. For reference, in FIGS. 26 and 27, the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3) represent an area of ​​a pixel circuit to which the first light-emitting diode (LED1) is electrically connected, an area of ​​a pixel circuit to which the second light-emitting diode (LED2) is electrically connected, and an area of ​​a pixel circuit to which the third light-emitting diode (LED3) is electrically connected.

[0294] As described above, and as illustrated in FIGS. 26 and 27, the pixel circuits arranged in the +x direction in the i-th row may be a set of pixel circuits for the first light-emitting diode (LED1), pixel circuits for the third light-emitting diode (LED3), pixel circuits for the second light-emitting diode (LED2), and pixel circuits for the third light-emitting diode (LED3) that are repeated. This also applies to the i+1-th row and other rows. And the pixel circuits arranged in the y-axis direction in each of the j-2-th column, the j-th column, and the j+2-th column may be a set of pixel circuits for the first light-emitting diode (LED1) and the second light-emitting diode (LED2), and the pixel circuits arranged in the second direction (y-axis direction) in each of the j-1-th column and the j+1-th column may be pixel circuits for the third light-emitting diode (LED3).

[0295] Initialization voltage lines (VL) extending approximately in the second direction (y-axis direction) within the display area may be arranged to be spaced apart from each other in the first direction (x-axis direction). For convenience, it may be said that the initialization voltage lines (VL) include first initialization voltage lines (VL1) and second initialization voltage lines (VL2), and that the first initialization voltage lines (VL1) and the second initialization voltage lines (VL2) are arranged alternately along the first direction (x-axis direction). At this time, along each of the first initialization voltage lines (VL1), a pixel circuit for a first light-emitting diode (LED1) and a pixel circuit for a second light-emitting diode (LED2), that is, a first color pixel circuit and a second color pixel circuit, may be arranged alternately along the second direction (y-axis direction). And along each of the second initialization voltage lines (VL2), pixel circuits for the third light-emitting diode (LED3), i.e., third color pixel circuits, can be arranged along the second direction (y-axis direction).

[0296] At this time, the first oxide semiconductor pattern (1510) included in each of the second color pixel circuits, which are pixel circuits for the second light-emitting diode (LED2), can be electrically connected to the first oxide semiconductor pattern (1510) included in the third color pixel circuit, which is the pixel circuit for the third light-emitting diode (LED3) located in the -x direction. Since a part of the first oxide semiconductor pattern (1510) constitutes a fourth transistor (T4) which is an initialization transistor, the fourth transistor (T4) included in each of the second color pixel circuits can be electrically connected to the fourth transistor (T4) included in any one of the third color pixel circuits that is adjacent in the first direction (x-axis direction). In FIG. 26 and FIG. 27, the first oxide semiconductor pattern (1510) included in each of the second color pixel circuits, which are pixel circuits for the second light-emitting diode (LED2), is illustrated as being integral with the first oxide semiconductor pattern (1510) included in the third color pixel circuit, which is the pixel circuit for the third light-emitting diode (LED3) located in the -x direction. For reference, the first oxide semiconductor pattern (1510) included in each of the first color pixel circuits, which are pixel circuits for the first light-emitting diode (LED1), may have an isolated shape within the area of ​​the first color pixel circuit.

[0297] As described above, an intermediate layer (220) including a light-emitting layer is positioned between the pixel electrode (210) and the common electrode (230) of the light-emitting diode (LED). The materials and thicknesses of the light-emitting layers in the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3), which emit light of different colors, may be different from each other. Accordingly, parasitic capacitances between the pixel electrodes (210) and the common electrode (230) in the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3) and threshold voltages for light emission may be different.

[0298] The pixel electrodes (210) of the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3) can be initialized with an initialization voltage (VINT) from an initialization voltage line (VL) by the fourth transistor (T4), which is a second initialization transistor. Since the parasitic capacitances and threshold voltages for light emission between the pixel electrodes (210) of the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3) and the common electrode (230) are different, ideally, the initialization voltages applied to the pixel electrodes (210) of the first light-emitting diode (LED1), the second light-emitting diode (LED2), and the third light-emitting diode (LED3) need to be different from each other. To this end, it is necessary to separately arrange the initialization voltage line for the first light-emitting diode (LED1), the initialization voltage line for the second light-emitting diode (LED2), and the initialization voltage line for the third light-emitting diode (LED3) within the display area (DA). However, in a high-resolution display panel (10) and an electronic device including the same, it is not easy to separately arrange the initialization voltage line for the first light-emitting diode (LED1), the initialization voltage line for the second light-emitting diode (LED2), and the initialization voltage line for the third light-emitting diode (LED3).

[0299] As described above, in the case of the display panel (10) according to the present embodiment and the electronic device including the same, the pixel circuit for the first light-emitting diode (LED1) and the pixel circuit for the second light-emitting diode (LED2), i.e., the first color pixel circuit and the second color pixel circuit, are alternately arranged along the second direction (y-axis direction) along each of the first initialization voltage lines (VL1). However, the pixel circuit for the first light-emitting diode (LED1) is electrically connected to the first initialization voltage line (VL1), whereas the pixel circuit for the second light-emitting diode (LED2) is electrically connected to the second initialization voltage line (VL2) rather than the first initialization voltage line (VL1). Accordingly, the initialization voltage (VINT) may be applied to the first light-emitting diode (LED1) by the first initialization voltage line (VL1), and the initialization voltage (VINT) may be applied to the second light-emitting diode (LED2) and the third light-emitting diode (LED3) by the second initialization voltage line (VL2). The signal of the initialization voltage (VINT) applied to the first initialization voltage line (VL1) may be different from the signal of the initialization voltage (VINT) applied to the second initialization voltage line (VL2). That is, the potential of the initialization voltage (VINT) applied to the first initialization voltage line (VL1) may be different from the potential of the initialization voltage (VINT) applied to the second initialization voltage line (VL2).

[0300] The optimal initialization voltage (VINT) for the first light-emitting diode (LED1) and the optimal initialization voltage (VINT) for the second light-emitting diode (LED2) may be different from each other. In this case, the optimal initialization voltage (VINT) for the second light-emitting diode (LED2) is not completely identical to the optimal initialization voltage (VINT) for the third light-emitting diode (LED3), but may be closer to the optimal initialization voltage (VINT) for the third light-emitting diode (LED3) than to the optimal initialization voltage (VINT) for the first light-emitting diode (LED1). In the case of the display panel (10) according to the present embodiment and the electronic device including the same, even if the pixel circuits for the first light-emitting diode (LED1) and the pixel circuits for the second light-emitting diode (LED2), i.e., the first color pixel circuit and the second color pixel circuit, are alternately arranged along the second direction (y-axis direction) along each of the first initialization voltage lines (VL1), only the first color pixel circuit is electrically connected to the first initialization voltage line (VL1) and the second color pixel circuit is electrically connected to the second initialization voltage line (VL2) to which the third color pixel circuit is electrically connected, the display panel (10) capable of displaying a high-quality image and the electronic device including the same can be implemented.

[0301] That the first color pixel circuit is electrically connected to the first initialization voltage line (VL1) means that one end of the fourth transistor (T4), which is a second initialization transistor included in the first color pixel circuit, is electrically connected to the first initialization voltage line (VL1). That the second color pixel circuit and the third color pixel circuit are electrically connected to the second initialization voltage line (VL2) means that one end of the fourth transistor (T4), which is a second initialization transistor included in the second color pixel circuit, and one end of the fourth transistor (T4), which is a second initialization transistor included in the third color pixel circuit, are electrically connected to the second initialization voltage line (VL2). Of course, the other end of the fourth transistor (T4) included in the first color pixel circuit may be electrically connected to the pixel electrode of the first light-emitting diode (LED1), which is an element emitting first color light, the other end of the fourth transistor (T4) included in the second color pixel circuit may be electrically connected to the pixel electrode of the second light-emitting diode (LED2), which is an element emitting second color light, and the other end of the fourth transistor (T4) included in the third color pixel circuit may be electrically connected to the pixel electrode of the third light-emitting diode (LED3), which is an element emitting third color light.

[0302] Fig. 28 is a schematic diagram illustrating first horizontal initialization voltage lines (VHL1), second horizontal initialization voltage lines (VHL2), and horizontal reference voltage lines (VRHL), and Fig. 29 is a schematic diagram illustrating connection electrodes (1750a, 1770a, 1770'a) that can be electrically connected to the components of Fig. 28. Fig. 30 is a schematic diagram illustrating first initialization voltage lines (VL1), second initialization voltage lines (VL2), and reference voltage lines (VRL) that can be electrically connected to the components of Fig. 28. FIG. 31 is a schematic diagram illustrating a connection relationship between the first horizontal initialization voltage lines (VHL1) and the second horizontal initialization voltage lines (VHL2) of FIG. 28 and the first initialization voltage lines (VL1) and the second initialization voltage lines (VL2) of FIG. 30, and FIG. 32 is a schematic diagram illustrating a connection relationship between the horizontal reference voltage lines (VRHL) of FIG. 28 and the reference voltage lines (VRL) of FIG. 30. FIG. 33 is a conceptual diagram schematically illustrating a positional relationship and a connection relationship between the first horizontal initialization voltage lines (VHL1), the second horizontal initialization voltage lines (VHL2) and the horizontal reference voltage lines (VRHL) and the first initialization voltage lines (VL1), the second initialization voltage lines (VL2) and the reference voltage lines (VRL).

[0303] As described above, FIG. 17 illustrates a first pixel circuit (PC1) located in the i-th row and j-th column, a second pixel circuit (PC2) located in the i-th row and j+1-th column, a part of a pixel circuit located in the i-1-th row and j-th column, and a part of a pixel circuit located in the i-1-th row and j+1-th column, and a horizontal initialization voltage line (VHL) extending in the first direction (x-axis direction) and passing through the pixel circuits of the i-1-th row, and a horizontal reference voltage line (VRHL) extending in the first direction (x-axis direction) and passing through the pixel circuits of the i-th row.

[0304] The horizontal initialization voltage lines (VHL) provided in the display panel (10) may include first horizontal initialization voltage lines (VHL1) and second horizontal initialization voltage lines (VHL2). The horizontal initialization voltage line (VHL) extending in the first direction (x-axis direction) and passing through the pixel circuits of the i-1th row as shown in FIG. 17 is electrically connected to the second initialization voltage line (VL2) as described above, and in that sense, the horizontal initialization voltage line (VHL) passing through the pixel circuits of the i-1th row may be referred to as the second horizontal initialization voltage line (VHL2). In addition, the horizontal initialization voltage line (VHL) extending in the first direction (x-axis direction) and passing through the pixel circuits of the i+1th row as shown in FIG. 28 may be referred to as the first horizontal initialization voltage line (VHL1). This is because the horizontal initialization voltage line (VHL) passing through the pixel circuits of the i+1th row is electrically connected to the first initialization voltage line (VL1).

[0305] For reference, the first initialization voltage line (VL1) is positioned not only in the i+1-th row, but also in the i+5-th row, the i+9-th row, the i+13-th row, etc., and the first initialization voltage line (VL1) may be positioned in the i-3-th row, the i-7-th row, the i-11-th row, etc. In addition, the second initialization voltage line (VL2) is positioned not only in the i-1-th row, but also in the i+3-th row, the i+7-th row, the i+11-th row, etc., and the second initialization voltage line (VL2) may be positioned in the i-5-th row, the i-9-th row, the i-13-th row, etc. In this way, the first horizontal initialization voltage lines (VHL1) and the second horizontal initialization voltage lines (VHL2) may be positioned alternately along the second direction (y-axis direction). This structure is schematically illustrated in FIG. 33, which is a conceptual diagram.

[0306] As described above, FIG. 17 illustrates a horizontal reference voltage line (VRHL) extending in the first direction (x-axis direction) and passing through the pixel circuits of the i-th row. This horizontal reference voltage line (VRHL) is electrically connected to the reference voltage line (VRL) extending in the second direction (y-axis direction) as described above. As illustrated in FIG. 28, the horizontal reference voltage line (VRHL) may be arranged not only in the i-th row but also in the i+2-th row. In addition to the i-th and i+2-th rows, horizontal reference voltage lines (VRHL) may be positioned in the i+4-th row, the i+6-th row, the i+8-th row, etc., and horizontal reference voltage lines (VRHL) may be arranged in the i-2-th row, the i-4-th row, the i-6-th row, etc. That is, each of the horizontal reference voltage lines (VRHL) can be positioned between the first horizontal initialization voltage line (VHL1) and the second horizontal initialization voltage line (VHL2), which are adjacent to each other. This structure is schematically illustrated in the conceptual diagram of Fig. 33.

[0307] Through this configuration, in the display area (DA), the first horizontal initialization voltage lines (VHL1) and the first initialization voltage lines (VL1) are electrically connected to each other to form a mesh structure, thereby preventing or minimizing voltage drops in the first initialization voltage lines (VL1), the second horizontal initialization voltage lines (VHL2) and the second initialization voltage lines (VL2) are electrically connected to each other to form a mesh structure, thereby preventing or minimizing voltage drops in the second initialization voltage lines (VL2), and the horizontal reference voltage lines (VRHL1) and the reference voltage lines (VRL) are electrically connected to each other to form a mesh structure, thereby preventing or minimizing voltage drops in the reference voltage lines (VRL).

[0308] For reference, as illustrated in FIG. 19, in the first pixel circuit (PC1), the first initialization voltage line (VL1) is positioned adjacent to the data line (DL), and in the second pixel circuit (PC2), the second initialization voltage line (VL2) is positioned adjacent to the data line (DL). Accordingly, the initialization voltage (VINT) in the first initialization voltage line (VL1) and / or the initialization voltage (VINT) in the second initialization voltage line (VL2) may be affected by the data signal transmitted by the data line (DL), and thus their potentials may vary. However, in the case of the display panel (10) according to the present embodiment and the electronic device including the same, the first horizontal initialization voltage lines (VHL1) and the first initialization voltage lines (VL1) are electrically connected to each other to form a mesh structure, so that the first initialization voltage line (VL1) can be prevented or minimized from being influenced by the adjacent data line (DL), and similarly, the second horizontal initialization voltage lines (VHL2) and the second initialization voltage lines (VL2) are electrically connected to each other to form a mesh structure, so that the second initialization voltage line (VL2) can be prevented or minimized from being influenced by the adjacent data line (DL).

[0309] In order to electrically connect the first initialization voltage line (VL1) and the first horizontal initialization voltage line (VHL1) located below it, a connection electrode (1770'a) may be positioned between them, as illustrated in FIG. 29. The connection electrode (1770'a) illustrated in FIG. 29 is a modified version of the dummy connection electrode (1770') illustrated in FIG. 18. As illustrated in FIG. 29, dummy connection electrodes (1770') are arranged in the j-2th column, j-th column, j+2th column, etc. of the i-2th row, i-th row, i+2th row, i+4th row, etc., but connection electrodes (1770'a) that are modified dummy connection electrodes (1770') are arranged in the j-2th column, j-th column, j+2nd column, etc. of the i+1th row, i+5th row, i+9th row, i+13th row, etc., which are rows where the first horizontal initialization voltage line (VHL1) is located.

[0310] Unlike the dummy connection electrode (1770') having one contact hole (CNT'), the connection electrode (1770'a) has two contact holes (CNT'). Just as the dummy connection electrode (1770') is electrically connected to the lower dummy semiconductor layer (1540) through the contact hole (CNT'), the connection electrode (1770'a) can be electrically connected to the lower dummy semiconductor layer (1540) through one of the two contact holes (CNT'). In addition, the connection electrode (1770'a) can be electrically connected to the first horizontal initialization voltage line (VHL1) located below through the other of the two contact holes (CNT'). The first initialization voltage line (VL1) is electrically connected to the connection electrode (1770'a) located at the bottom through the first via contact hole (VCNT1), so that as a result, the connection electrode (1770'a) can electrically connect the first initialization voltage line (VL1) and the first horizontal initialization voltage line (VHL1).

[0311] In order to electrically connect the second initialization voltage line (VL2) and the second horizontal initialization voltage line (VHL2) located below it, a connection electrode (1770a) may be located between them as illustrated in FIG. 29. For reference, the connection electrode (1770a) illustrated in FIG. 29 is also illustrated in the pixel circuit located in the +y direction of the second pixel circuit (PC2) illustrated in FIG. 18. This connection electrode (1770a) is a modified version of the seventh connection electrode (1770) illustrated in FIGS. 18 and 29. As illustrated in FIG. 29, the 7th connection electrode (1770) is arranged in the j-3th column, the j-1th column, the j+1th column, etc. of the i-th row, the i+1th row, the i+2th row, etc., but the connection electrode (1770a) is arranged in the j-3th column, the j-1th column, the j+1th column, etc. of the i-1th row, the i+3th row, the i+7th row, the i+11th row, etc., which are the rows where the second horizontal initialization voltage line (VHL2) is located.

[0312] Unlike the seventh connection electrode (1770) having one contact hole (CNT'), the connection electrode (1770a) has two contact holes (CNT'). Just as the seventh connection electrode (1770) is electrically connected to the first oxide semiconductor pattern (1510) underneath through the contact hole (CNT') and is electrically connected to the semiconductor layer of the fourth transistor (T4), which is the second initialization transistor, the connection electrode (1770a) may be electrically connected to the first oxide semiconductor pattern (1510) underneath through one of the two contact holes (CNT') and is electrically connected to the semiconductor layer of the fourth transistor (T4), which is the second initialization transistor. As described above, the fourth transistor (T4) is electrically connected to the pixel electrode (210) of the light-emitting diode. And the connecting electrode (1770a) can be electrically connected to the second horizontal initialization voltage line (VHL2) located at the bottom through the other one of the two contact holes (CNT'). Since the second initialization voltage line (VL2) is electrically connected to the connecting electrode (1770a) located at the bottom through the first via contact hole (VCNT1), as a result, the connecting electrode (1770a) can electrically connect the second initialization voltage line (VL2) and the second horizontal initialization voltage line (VHL2).

[0313] In order to electrically connect the reference voltage line (VRL) and the horizontal reference voltage line (VRHL) located below it, a connection electrode (1750a) may be located between them as illustrated in FIG. 29. The connection electrode (1750a) illustrated in FIG. 29 corresponds to the connection electrode located at the lower left of the first pixel circuit (PC1) and the lower right of the second pixel circuit (PC2) illustrated in FIG. 18. This connection electrode (1750a) is a modified version of the fifth connection electrode (1750), which is a connection electrode located at the upper left of the first pixel circuit (PC1) and the upper right of the second pixel circuit (PC2) illustrated in FIG. 18. For reference, the fifth connection electrode (1750) is also illustrated in FIG. 29. As illustrated in FIG. 29, a fifth connection electrode (1750) is placed at the boundary between the i-1th row and the ith row, the boundary between the i+1th row and the i+2th row, etc., but a connection electrode (1750a) is placed at the boundary between the ith row and the i+1th row, the boundary between the i+2nd row and the i+3rd row, etc.

[0314] Unlike the fifth connection electrode (1750) having two contact holes (CNT'), the connection electrode (1750a) has three contact holes (CNT'). Just as the fifth connection electrode (1750) is electrically connected to the second oxide semiconductor patterns (1520) of two adjacent pixel circuits through the two contact holes (CNT') and is electrically connected to the semiconductor layers of the third transistors (T3), which are the first initialization transistors of the two pixel circuits, the connection electrode (1750a) can be electrically connected to the lower second oxide semiconductor pattern (1520) through two of the three contact holes (CNT') and be electrically connected to the semiconductor layers of the third transistors (T3), which are the first initialization transistors. As described above, the third transistor (T3) is electrically connected to the other end of the second transistor (T2), which is a data writing transistor that is electrically connected to the data line (DL). In addition, the connection electrode (1750a) can be electrically connected to the horizontal reference voltage line (VRHL) located below through the remaining one of the three contact holes (CNT'). Since the reference voltage line (VRL) is electrically connected to the connection electrode (1750a) located below through the first via contact hole (VCNT1), as a result, the connection electrode (1750a) can electrically connect the reference voltage line (VRL) and the horizontal reference voltage line (VRHL).

[0315] Fig. 33 is a conceptual diagram schematically illustrating the positional relationship and connection relationship of the first horizontal initialization voltage lines (VHL1), the second horizontal initialization voltage lines (VHL2), and the horizontal reference voltage lines (VRHL) as described above, and the first initialization voltage lines (VL1), the second initialization voltage lines (VL2), and the reference voltage lines (VRL). In the peripheral area (PA) outside the display area (DA), the first initialization voltage supply line (PVL1), the second initialization voltage supply line (PVL2), and the reference voltage supply line (PVRL) extending in the first direction (x-axis direction) may be arranged. Specifically, as illustrated in FIG. 33, a first initialization voltage supply line (PVL1), a second initialization voltage supply line (PVL2), and a reference voltage supply line (PVRL) may be arranged in the +y direction and the -y direction of the display area (DA), respectively. The first initialization voltage line (VL1) may be connected to two first initialization voltage supply lines (PVL1) and positioned between the first initialization voltage supply lines (PVL1), the second initialization voltage line (VL2) may be connected to two second initialization voltage supply lines (PVL2) and positioned between the second initialization voltage supply lines (PVL2), and the reference voltage line (VRL) may be connected to two reference voltage supply lines (PVRL) and positioned between the reference voltage supply lines (PVRL).

[0316] Although the structure of the display panel (10) has been mainly described so far, the present invention is not limited thereto. An electronic device equipped with such a display panel (10) is also considered to fall within the scope of the present invention.

[0317] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

[0318] A display panel capable of displaying high-quality images and an electronic device including the same can be implemented.

Claims

1. First initialization voltage lines and second initialization voltage lines are arranged alternately along a first direction within the display area and extend in a second direction intersecting the first direction; and First horizontal initialization voltage lines extending in the first direction and electrically connected to the first initialization voltage lines; A display panel having a .

2. In paragraph 1, A display panel further comprising connecting electrodes interposed between the first initialization voltage lines and the first horizontal initialization voltage lines to electrically connect the first initialization voltage lines and the first horizontal initialization voltage lines.

3. In paragraph 2, A display panel wherein the first initialization voltage lines are located above the first horizontal initialization voltage lines.

4. In paragraph 2, A display panel, wherein each of the above connecting electrodes is electrically connected to a dummy semiconductor layer located below a corresponding one of the first horizontal initialization voltage lines.

5. In paragraph 1, A display panel further comprising second horizontal initialization voltage lines extending in the first direction and electrically connected to the second initialization voltage lines.

6. In paragraph 5, A display panel in which the first horizontal initialization voltage lines and the second horizontal initialization voltage lines are arranged alternately along the second direction.

7. In paragraph 5, A display panel further comprising connecting electrodes interposed between the second initialization voltage lines and the second horizontal initialization voltage lines to electrically connect the second initialization voltage lines and the second horizontal initialization voltage lines.

8. In paragraph 7, The display panel, wherein the second initialization voltage lines are located above the second horizontal initialization voltage lines.

9. In paragraph 7, A display panel, wherein each of the above connecting electrodes is electrically connected to a semiconductor layer of an initialization transistor located below a corresponding one of the second horizontal initialization voltage lines.

10. In paragraph 9, The above initialization transistor is electrically connected to the pixel electrode of the light-emitting diode, the display panel.

11. In paragraph 5, Reference voltage lines arranged along the first direction within the display area and extending in the second direction; and Horizontal reference voltage lines extending in the first direction and electrically connected to the reference voltage lines; A display panel that has more features.

12. In paragraph 11, A display panel wherein the first horizontal initialization voltage lines and the second horizontal initialization voltage lines are arranged alternately along the second direction, and each of the horizontal reference voltage lines is arranged between the first horizontal initialization voltage line and the second horizontal initialization voltage line that are adjacent to each other.

13. In paragraph 11, A display panel further comprising connecting electrodes interposed between the reference voltage lines and the horizontal reference voltage lines to electrically connect the reference voltage lines and the horizontal reference voltage lines.

14. In paragraph 13, A display panel wherein the above reference voltage lines are located above the above horizontal reference voltage lines.

15. In paragraph 13, A display panel, wherein each of the above connecting electrodes is electrically connected to a semiconductor layer of an initialization transistor located below a corresponding one of the above horizontal reference voltage lines.

16. In paragraph 15, The above initialization transistor is electrically connected to the other end of the data writing transistor connected to the data line, the display panel.

17. Display panel; and A lower cover forming an exterior and having an opening exposing a portion of the display panel; Includes, The above display panel, First initialization voltage lines and second initialization voltage lines are arranged alternately along a first direction within the display area and extend in a second direction intersecting the first direction; and First horizontal initialization voltage lines extending in the first direction and electrically connected to the first initialization voltage lines; An electronic device having.

18. In paragraph 17, An electronic device further comprising connecting electrodes interposed between the first initialization voltage lines and the first horizontal initialization voltage lines to electrically connect the first initialization voltage lines and the first horizontal initialization voltage lines.

19. In paragraph 18, An electronic device wherein the first initialization voltage lines are located above the first horizontal initialization voltage lines.

20. In paragraph 18, An electronic device wherein each of the above connecting electrodes is electrically connected to a dummy semiconductor layer located below a corresponding one of the first horizontal initialization voltage lines.

Images