Method for executing process, electronic device supporting same, and storage medium

Abstract

An electronic device is disclosed. The electronic device comprises a memory comprising a plurality of memory areas respectively corresponding to a plurality of layers, and at least one processor, wherein the at least one processor is configured to: execute a first process comprising security data, on an application layer having a lower exception level than a kernel layer from among the plurality of layers; while the first process is executed, identify a first event for context switching from the first process to a second process; on the basis of identifying the first event, acquire information associated with a first memory address corresponding to the first process on the kernel layer; store the information associated with the first memory address in a first memory area corresponding to a layer having a higher exception level than the kernel layer; and execute the second process on the basis of the context switching.

Description

Methods of executing processes, electronic devices supporting them, and storage media

[0001] The present disclosure relates to a method for executing a process, an electronic device supporting the same, and a storage medium.

[0002] Recently, processors in electronic devices in embedded systems are evolving into multicore processors to improve performance. These multicore processors can be broadly categorized into symmetric multicore and asymmetric multicore. Asymmetric multicore processors (AMPs) offer higher performance and efficiency than symmetric multicore processors, and their use is rapidly increasing.

[0003] An asymmetric multicore processor may have multiple cores (e.g., 4, 8, or 16 cores) on a single chip. The asymmetric multicore processor may have cores with different characteristics, i.e., cores of a type with high performance and low energy efficiency (e.g., big cores) and cores of a type with low performance and high energy efficiency (e.g., little cores).

[0004] The above asymmetric multi-core processor can perform process scheduling to assign processes to be executed to cores by considering the performance of each core.

[0005] Additionally, in an asymmetric multi-core environment, electronic devices can support virtual operating systems (e.g., virtual machines) by applying virtualization technology to efficiently use hardware resources.

[0006] An electronic device according to one embodiment of the present disclosure may include a memory including a plurality of memory areas corresponding to each of a plurality of layers, and at least one processor.

[0007] According to one embodiment, the at least one processor can execute a first process including secure data on an application layer having an exception level lower than a kernel layer among the plurality of layers.

[0008] In one embodiment, the at least one processor may identify a first event for context switching from the first process to the second process while the first process is executing.

[0009] According to one embodiment, the at least one processor may obtain information associated with a first memory address corresponding to the first process on the kernel layer based on identifying the first event.

[0010] According to one embodiment, the at least one processor may store information associated with the first memory address in a first memory area corresponding to a layer having a higher exception level than the kernel layer.

[0011] In one embodiment, the at least one processor may execute the second process based on the context switching.

[0012] According to one embodiment, the method may include executing a first process including secure data on an application layer having an exception level lower than a kernel layer among a plurality of layers.

[0013] In one embodiment, the method may include an operation of identifying a first event for context switching from the first process to a second process while the first process is executing.

[0014] According to one embodiment, the method may include an operation of obtaining information associated with a first memory address corresponding to the first process on the kernel layer based on verifying the first event.

[0015] According to one embodiment, the method may include storing information associated with the first memory address in a first memory area corresponding to a layer having a higher exception level than the kernel layer.

[0016] According to one embodiment, the method may include executing the second process based on the context switching.

[0017] According to one embodiment, a storage medium storing computer-executable instructions, wherein the instructions, when executed by at least one processor of an electronic device, cause the electronic device to perform at least one operation.

[0018] In one embodiment, the at least one operation may include executing a first process including secure data on an application layer having an exception level lower than a kernel layer among the plurality of layers.

[0019] In one embodiment, the at least one operation may include an operation of identifying a first event for a context switch from the first process to a second process while the first process is executing.

[0020] In one embodiment, the at least one operation may include obtaining information associated with a first memory address corresponding to the first process on the kernel layer based on identifying the first event.

[0021] In one embodiment, the at least one operation may include storing information associated with the first memory address in a first memory area corresponding to a layer having a higher exception level than the kernel layer.

[0022] In one embodiment, the at least one operation may include executing the second process based on the context switching.

[0023] FIG. 1 is a block diagram of an electronic device within a network environment according to one embodiment.

[0024] FIGS. 2A and 2B are block diagrams of electronic device configurations according to one embodiment.

[0025] FIG. 3A and FIG. 3B are diagrams illustrating a method for performing context switching according to one embodiment.

[0026] FIG. 4 is a diagram for explaining the architecture of multiple layers according to one embodiment.

[0027] Figure 5 is a flowchart illustrating a method for protecting information associated with a process of an electronic device.

[0028] FIG. 6 is a flowchart illustrating a method for protecting information associated with a process based on operations between multiple layers of an electronic device.

[0029] Figure 7 is a flowchart illustrating a method for restoring information associated with a process of an electronic device.

[0030] FIG. 8 is a flowchart illustrating a method for restoring information associated with a process based on operations between multiple layers of an electronic device.

[0031] FIG. 9 is a flowchart illustrating a method for protecting information associated with a process based on identification information of the process of an electronic device.

[0032] FIG. 1 is a block diagram of an electronic device (101) within a network environment (100) according to one embodiment. Referring to FIG. 1 , in the network environment (100), the electronic device (101) may communicate with the electronic device (102) via a first network (198) (e.g., a short-range wireless communication network), or may communicate with at least one of the electronic device (104) or the server (108) via a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) via the server (108). According to one embodiment, the electronic device (101) may include a processor (120), a memory (130), an input module (150), an audio output module (155), a display module (160), an audio module (170), a sensor module (176), an interface (177), a connection terminal (178), a haptic module (179), a camera module (180), a power management module (188), a battery (189), a communication module (190), a subscriber identification module (196), or an antenna module (197). In some embodiments, the electronic device (101) may omit at least one of these components (e.g., the connection terminal (178)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (176), the camera module (180), or the antenna module (197)) may be integrated into one component (e.g., the display module (160)).

[0033] The processor (120) may, for example, execute software (e.g., a program (140)) to control at least one other component (e.g., a hardware or software component) of the electronic device (101) connected to the processor (120) and perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operations, the processor (120) may store commands or data received from other components (e.g., a sensor module (176) or a communication module (190)) in a volatile memory (132), process the commands or data stored in the volatile memory (132), and store result data in a non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., a central processing unit or an application processor) or an auxiliary processor (123) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together with the main processor (121). For example, when the electronic device (101) includes the main processor (121) and the auxiliary processor (123), the auxiliary processor (123) may be configured to use less power than the main processor (121) or to be specialized for a given function. The auxiliary processor (123) may be implemented separately from the main processor (121) or as a part thereof.

[0034] The auxiliary processor (123) may control at least a portion of functions or states associated with at least one component (e.g., a display module (160), a sensor module (176), or a communication module (190)) of the electronic device (101), for example, on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (123) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (180) or a communication module (190)). In one embodiment, the auxiliary processor (123) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (101) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (108)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0035] The memory (130) can store various data used by at least one component (e.g., processor (120) or sensor module (176)) of the electronic device (101). The data can include, for example, software (e.g., program (140)) and input data or output data for commands related thereto. The memory (130) can include volatile memory (132) or non-volatile memory (134).

[0036] The program (140) may be stored as software in the memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0037] The input module (150) can receive commands or data to be used in a component of the electronic device (101) (e.g., a processor (120)) from an external source (e.g., a user) of the electronic device (101). The input module (150) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0038] The audio output module (155) can output audio signals to the outside of the electronic device (101). The audio output module (155) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. In one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0039] The display module (160) can visually provide information to an external party (e.g., a user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0040] The audio module (170) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150), output sound through the sound output module (155), or an external electronic device (e.g., electronic device (102)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (101).

[0041] The sensor module (176) can detect the operating status (e.g., power or temperature) of the electronic device (101) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (176) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0042] The interface (177) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (101) with an external electronic device (e.g., the electronic device (102)). In one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0043] The connection terminal (178) may include a connector through which the electronic device (101) may be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0044] The haptic module (179) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (179) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0045] The camera module (180) can capture still images and videos. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0046] The power management module (188) can manage power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0047] A battery (189) may power at least one component of the electronic device (101). In one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0048] The communication module (190) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may operate independently from the processor (120) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (194) (e.g., a local area network (LAN) communication module, or a power line communication module). Among these communication modules, the corresponding communication module can communicate with an external electronic device (104) via a first network (198) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (199) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules can be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (192) can verify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) by using subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (196).

[0049] The wireless communication module (192) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (192) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (192) can support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), an external electronic device (e.g., the electronic device (104)), or a network system (e.g., the second network (199)). According to one embodiment, the wireless communication module (192) can support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0050] The antenna module (197) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). In one embodiment, the antenna module (197) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). In one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (198) or the second network (199), may be selected from the plurality of antennas, for example, by the communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device via the at least one selected antenna. In some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (197).

[0051] According to various embodiments, the antenna module (197) may form a mmWave antenna module. In one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high-frequency band.

[0052] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0053] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) via a server (108) connected to a second network (199). Each of the external electronic devices (102 or 104) may be the same or a different type of device as the electronic device (101). According to one embodiment, all or part of the operations executed in the electronic device (101) may be executed in one or more of the external electronic devices (102, 104, or 108). For example, when the electronic device (101) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (101) may, instead of or in addition to executing the function or service itself, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (101) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In another embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (104) or the server (108) may be included in the second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0054] In the detailed description below, reference numerals in the drawings may be used interchangeably or omitted for components that can be easily understood through the preceding embodiments, and their detailed descriptions may also be omitted. An electronic device according to an embodiment disclosed in this document may be implemented by selectively combining components of different embodiments, and components of one embodiment may be replaced by components of another embodiment. For example, it should be noted that the present invention is not limited to specific drawings or embodiments.

[0055] FIGS. 2A and 2B are block diagrams of electronic device configurations according to one embodiment.

[0056] Referring to FIG. 2A, in one embodiment, an electronic device (e.g., electronic device (101) of FIG. 1) may include a memory (220) (e.g., memory (130) of FIG. 1) and / or a processor (210) (e.g., processor (120) of FIG. 1).

[0057] The memory (220) can store various data used by at least one component of the electronic device (101). The data can include, for example, software (e.g., the program (140) of FIG. 1) and input data or output data for commands related thereto. The memory (220) can include volatile memory (e.g., the volatile memory (132) of FIG. 1) or nonvolatile memory (e.g., the nonvolatile memory (134) of FIG. 1).

[0058] In one embodiment, the memory (220) may include a plurality of memory areas corresponding to each of the plurality of layers. In one embodiment, information stored in each memory area may be separated by a memory protection operation of the memory management unit (MMU) (211).

[0059] In one embodiment, the program may be stored as software in memory (220) and may include, for example, an operating system (e.g., operating system (142) of FIG. 1), middleware (e.g., middleware (144) of FIG. 1), or an application (e.g., application (146) of FIG. 1).

[0060] In one embodiment, the processor (210) may have at least a portion of the same or similar configuration as the processor (120) of FIG. 1. In one embodiment, the processor (210) may include one or more processors.

[0061] In one embodiment, the processor (210) may perform at least one operation to protect information associated with the process based on executing instructions stored in memory (220).

[0062] Referring to FIG. 2B, in one embodiment, the processor (210) may include an MMU (211) and a central processing unit (CPU) (213). The MMU (211) may convert a virtual address corresponding to at least one process executed by the CPU (213) into a physical address. In one embodiment, the operation of converting a virtual address into a physical address performed by the MMU (211) may include an operation of mapping a virtual address corresponding to a process to a physical address included in a memory (220).

[0063] In one embodiment, the MMU (211) may implement an operating system based on multiple layers by managing memory areas corresponding to each of the multiple layers. In one embodiment, the MMU (211) may perform memory protection by blocking access to a memory area corresponding to a layer with relatively high privileges when the CPU (213) processes data in a memory area corresponding to a layer with relatively low privileges.

[0064] According to one embodiment, a processor (210) may set at least one page table entry (PTE) corresponding to a layer having a lower exception level than the hypervisor layer based on page table information stored in a memory area corresponding to the hypervisor layer. The processor (210) may cause a lower layer to perform a specific operation by accessing data stored in a memory area corresponding to the lower layer without recognizing whether a layer having a higher exception level than the lower layer exists based on providing an application programming interface (API) for performing a specific operation to the lower layer.

[0065] According to one embodiment, the processor (210) may execute a first process including secure data on an application layer having a lower exception level than a kernel layer among the plurality of layers. In one embodiment, the plurality of layers may include software configured to access memory areas of different security levels. For example, the plurality of layers may include an application layer, a middle layer, a kernel layer, a hypervisor layer, a security monitor layer, or a hardware layer, and the specific names of the layers may change depending on the implementation. In one embodiment, the kernel layer may have a relatively higher exception level than the application layer. For example, the exception level of the application layer may correspond to exception level (EL) 0 (zero). The exception level of the kernel layer may correspond to EL 1. In one embodiment, the hypervisor layer may have a relatively higher exception level than the kernel layer. For example, the exception level of the hypervisor layer may correspond to EL 2. In one embodiment, the security monitor layer may have a relatively higher exception level than the hypervisor layer. For example, the exception level of the security monitor layer may correspond to EL 3. In one embodiment, the hardware layer may include a processor (210) and / or memory (220). The hardware layer may provide resources for running an operating system based on multiple layers. In one embodiment, the processor (210) may execute a first process including security data on the application layer. The first process may be, for example, a process requiring a relatively high security level. The security data may include, for example, information associated with a process control block (PCB).Information associated with the PCB may include, but is not limited to, information associated with the page table base register (PTBR). Security data may also include, for example, information associated with registers. The information associated with registers may include, for example, at least one of information associated with the stack pointer (SP), information associated with the program counter (PC), or information associated with the current program status register (CPSR).

[0066] According to one embodiment, the processor (210) may identify a first event for context switching from the first process to the second process while the first process is executing. For example, the processor (210) may identify the occurrence of an interrupt or system call for execution of the second process. The context switching will be described with reference to FIGS. 3A and 3B .

[0067] According to one embodiment, the processor (210) may, based on the confirmation of the first event, determine whether the identification information of the first process corresponds to first information associated with at least one process including security data. The first information may, for example, include a list of identification information of at least one process requiring a relatively high security level. In one embodiment, the processor (210) may also perform a protection operation of the state information of the process according to one embodiment of the present disclosure based on the occurrence of an event for context switching, regardless of whether the identification information of the first process corresponds to the first information. The identification information of the process may include, for example, a process identifier (PID), but is not limited thereto.

[0068] In one embodiment, the processor (210) may store state information of the first process in the first PCB corresponding to the first process based on the confirmation of the first event. The processor (210) may protect the state information of the first process stored in the first PCB based on the protection of the address of the first PCB.

[0069] According to one embodiment, the processor (210) may obtain information associated with a first memory address corresponding to a first process on the kernel layer based on confirming a first event. For example, the processor (210) may confirm pointer information of a first PCB corresponding to the first process based on confirming an event for context switching.

[0070] According to one embodiment, the processor (210) may store information associated with the first memory address in a first memory area corresponding to a layer having a higher exception level than the kernel layer. The layer having a higher exception level than the kernel layer may be referred to as a “privileged layer.” In one embodiment, the layer having a higher exception level than the kernel layer may include a hardware layer. The first memory area may include at least a portion of a memory area corresponding to the hardware layer. The layer having a higher exception level than the kernel layer may be a layer corresponding to EL 2 or a layer corresponding to EL 3, depending on the implementation. Based on storing pointer information of the first PCB in the privileged layer, the processor (210) may reduce the risk of increased security information leakage by storing PCB information in the memory area corresponding to EL 2. By storing pointer information of the first PCB in the privileged layer, the processor (210) may enhance the security of PCB information corresponding to a process requiring a relatively high level of security.

[0071] According to one embodiment, the processor (210) may change a memory address corresponding to a first process stored in a memory area associated with a kernel layer to a first value based on storing information associated with a first memory address in a first memory area. For example, the processor (210) may change pointer information of a first PCB stored in a memory area corresponding to the kernel layer to a garbage value. The processor (210) may maintain backward compatibility based on changing the pointer information of the first PCB stored in a memory area corresponding to the kernel layer to a garbage value.

[0072] According to one embodiment, the processor (210) may store information associated with a first memory address in a first memory area based on confirmation that the identification information of the first process corresponds to the first information. For example, the processor (210) may store pointer information of a first PCB corresponding to the first process in a memory area corresponding to a privilege layer.

[0073] According to one embodiment, the processor (210) may store the state information of the first process in a memory area corresponding to a hypervisor layer having a higher exception level than the kernel layer based on confirming that the identification information of the first process does not correspond to the first information. The processor (210) may store the state information of the first process in a memory area corresponding to the hypervisor layer based on confirming that the security level for the first process is relatively low.

[0074] According to one embodiment, the processor (210) may execute the second process based on the context switching. According to one embodiment, the processor (210) may execute the second process until an event for executing the first process is confirmed.

[0075] According to one embodiment, the processor (210) may identify a second event for context switching from the second process to the first process while the second process is running. The processor (210) may, for example, identify a scheduling event for the first process.

[0076] According to one embodiment, the processor (210) may store state information of the second process in a memory area corresponding to a hypervisor layer having a higher exception level than the kernel layer. In one embodiment, the second process may be a process requiring a relatively lower security level than the first process. The processor (210) may store state information of the second process in a memory area corresponding to EL 2. The state information of the second process may include a context corresponding to the second process. In one embodiment, when the security level for the second process corresponds to the security level for the second process, the processor (210) may store pointer information of the second PCB corresponding to the second process in a memory area corresponding to the hardware layer.

[0077] According to one embodiment, a processor (210) may obtain information associated with a first memory address stored in a first memory area. The processor (210) may obtain pointer information of a first PCB stored in a memory area corresponding to a hardware layer.

[0078] According to one embodiment, the processor (210) may acquire status information of the first process based on information associated with the acquired first memory address. For example, the processor (210) may acquire the context of the first process based on pointer information of the acquired first PCB.

[0079] According to one embodiment, a processor (210) may execute a first process based on status information of the first process. The processor (210) may perform context switching from a second process to the first process based on the context of the first process.

[0080] FIG. 3A and FIG. 3B are diagrams illustrating a method for performing context switching according to one embodiment.

[0081] Referring to FIG. 3A, a processor (210) according to one embodiment may execute a first process (301) in operation 311. The first process (301) may be, for example, a process requiring a relatively high security level. In one embodiment, while the first process (301) is executed, the second process (303) may remain in an idle state. In one embodiment, although only the first process (301) and the second process (303) are illustrated in FIGS. 3A and 3B, the processor (210) may perform scheduling for a plurality of processes.

[0082] In one embodiment, the processor (210) may store the context of the first process (301) in the first PCB based on identifying an event for context switching at operation 313. The processor (210) may store state information of the first process (301) in the first PCB corresponding to the first process (301). In one embodiment, the processor (210) may store the memory address of the first PCB in a memory area corresponding to the privilege layer while the second process (303) is executed based on the security level for the first process (301) being relatively high.

[0083] In one embodiment, the processor (210) may obtain the context of the second process (303) from the second PCB at operation 315. The processor (210) may obtain state information of the second process (303) based on checking the stored memory address of the second PCB.

[0084] In one embodiment, the processor (210) may perform context switching by executing a second process (303) at operation 317.

[0085] In one embodiment, the processor (210) may, at operation 319, store the context of the second process in the second PCB based on identifying an event for context switching from the second process (303) to the first process (301) while the second process (303) is executing.

[0086] In one embodiment, the processor (210) may obtain the context of the first process from the first PCB at operation 321. The processor (210) may obtain the context of the first process based on obtaining a memory address of the first PCB stored in a memory area corresponding to the privilege layer.

[0087] In one embodiment, the processor (210) may execute a first process (301) at operation 323. The processor (210) may perform context switching based on executing the first process (301).

[0088] Referring to FIG. 3b, a processor (210) according to one embodiment can execute different processes depending on the time interval.

[0089] In one embodiment, the processor (210) may execute a first process during a time interval t1 to t2. Based on the confirmation of a context switching event at time t2, the processor (210) may store the context of the first process in the first PCB. By storing the memory address of the first PCB in a memory area corresponding to the privilege layer, the processor (210) may protect the PCB information of a process requiring a relatively high level of security while another process is being executed.

[0090] In one embodiment, the processor (210) may acquire the context of the second process at time t3. The processor (210) may acquire the context of the second process based on acquiring the memory address of the second PCB corresponding to the second process.

[0091] In one embodiment, the processor (210) may perform a context switch by executing a second process. The processor (210) may execute the second process during a time interval t3 to t4. Based on the confirmation of a context switch event at time t4, the processor (210) may store the context of the second process in the second PCB. For example, the processor (210) may store the memory address of the second PCB in a memory area corresponding to the hypervisor.

[0092] In one embodiment, the processor (210) may acquire the context of the first process at time t5. The processor (210) may acquire the context of the first process based on acquiring the memory address of the first PCB stored in the memory area corresponding to the privilege layer. The processor (210) may execute the first process based on the acquired context of the first process. The processor (210) may enhance the security of the PCB information of the first process by storing the PCB information of the first process in the memory area corresponding to the privilege layer while the first process is not loaded into the memory (e.g., the memory (220) of FIG. 2).

[0093] FIG. 4 is a diagram for explaining the architecture of multiple layers according to one embodiment.

[0094] Referring to FIG. 4, an electronic device (e.g., the electronic device (101) of FIG. 2A) according to one embodiment may implement an operating system based on a plurality of layers based on managing memory areas corresponding to each of the plurality of layers. In one embodiment, the electronic device may perform memory protection by blocking access to a memory area corresponding to a layer having relatively high authority when a CPU (e.g., the CPU (213) of FIG. 2B) of the electronic device processes data of a memory area corresponding to a layer having relatively low authority.

[0095] An electronic device according to one embodiment may set at least one PTE corresponding to a layer having a lower exception level than the hypervisor layer based on page table information stored in a memory area corresponding to the hypervisor layer. The electronic device may cause the lower layer to perform a specific operation by accessing data stored in a memory area corresponding to the lower layer without recognizing whether a layer having a higher exception level than the lower layer exists, based on providing an API for performing a specific operation to the lower layer.

[0096] An electronic device according to one embodiment may execute a process on an application layer having a lower exception level than a kernel layer among the plurality of layers. For example, the electronic device may execute a first process on a first container having a lower exception level than a first VM kernel. In one embodiment, the plurality of layers may include software configured to access memory areas of different security levels. For example, the plurality of layers may include an application layer, a middle layer, a kernel layer, a hypervisor layer, a security monitor layer, or a hardware layer, and the specific names of the layers may change depending on the implementation. In one embodiment, the kernel layer may have a relatively higher exception level than the application layer. For example, the exception level of the application layer may correspond to EL 0. The exception level of the kernel layer may correspond to EL 1. In one embodiment, the hypervisor layer may have a relatively higher exception level than the kernel layer. For example, the exception level of the hypervisor layer may correspond to EL 2. In one embodiment, the security monitor layer may have a relatively higher exception level than the hypervisor layer. For example, the exception level of the security monitor layer may correspond to EL 3. In one embodiment, the hardware layer may include a processor (210) and / or memory (220). The hardware layer may provide resources for running an operating system based on multiple layers. In one embodiment, the processor (210) may execute a first process including secure data on a first container. The first process may be, for example, a process requiring a relatively high security level.

[0097] In one embodiment, the electronic device may store PCB information of the first process in a memory area corresponding to a privilege layer (e.g., a hardware layer) based on identifying an event for context switching from a first VM kernel to a second VM kernel. In one embodiment, the electronic device may enhance security by storing pointer information of the first PCB corresponding to the first process in a memory area corresponding to the privilege layer. The electronic device may perform context switching based on executing the second process on the second VM kernel.

[0098] Figure 5 is a flowchart illustrating a method for protecting information associated with a process of an electronic device.

[0099] In the following embodiments, the operations may be performed sequentially, but are not necessarily sequential. For example, the order of the operations may be changed, and at least two operations may be performed in parallel. Depending on the implementation, certain operations may be omitted.

[0100] According to FIG. 5, in one embodiment, in operation 501, an electronic device (e.g., the electronic device (200) of FIG. 2A (e.g., the processor (210))) may execute a first process including secure data on an application layer having a lower exception level than a kernel layer among a plurality of layers. In one embodiment, the secure data may include information associated with a page table base register (PTBR). The secure data may also include at least one of information associated with a stack pointer (SP), information associated with a program counter (PC), or information associated with a current program status register (CPSR).

[0101] In one embodiment, at operation 503, the electronic device may identify a first event for context switching from the first process to the second process while the first process is executing.

[0102] According to one embodiment, in operation 505, the electronic device may obtain information associated with a first memory address corresponding to a first process on the kernel layer.

[0103] In one embodiment, in operation 507, the electronic device may store information associated with a first memory address in a first memory area corresponding to a layer having an exception level higher than the kernel layer. In one embodiment, the layer having an exception level higher than the kernel layer may include a hardware layer.

[0104] According to one embodiment, at operation 509, the electronic device may execute a second process based on context switching.

[0105] In one embodiment, the electronic device can enhance the security of security information of a process requiring a relatively high security level by storing PCB information corresponding to the first process in a memory area corresponding to a layer (e.g., a privilege layer) having a higher exception level than the kernel layer.

[0106] FIG. 6 is a flowchart illustrating a method for protecting information associated with a process based on operations between multiple layers of an electronic device.

[0107] In the following embodiments, the operations may be performed sequentially, but are not necessarily sequential. For example, the order of the operations may be changed, and at least two operations may be performed in parallel. Depending on the implementation, certain operations may be omitted.

[0108] In one embodiment, the description that the layers (610, 620, 630, 640, 650) illustrated in FIG. 6 perform a specific operation may be understood as performing the specific operation based on an electronic device (e.g., the electronic device (101) of FIG. 2A) accessing a memory area allocated for the corresponding layer. In one embodiment, although FIG. 6 illustrates a first layer having a relatively low exception level providing specific information to a second layer having a relatively high exception level, the first layer may not be aware of the existence of the second layer because the first layer performs the specific operation based on an API provided from the second layer.

[0109] Referring to FIG. 6, in one embodiment, the application layer (610) may execute a first process including secure data in operation 601. The application layer (610) may confirm a first event in operation 603. The application layer (610) may store state information of the first process in the first PCB in operation 605.

[0110] In one embodiment, the kernel layer (620) may, at operation 607, obtain information associated with a first memory address corresponding to a first process. The kernel layer (620) may obtain information associated with a first memory address of a first PCB corresponding to the first process. The kernel layer (620) may, at operation 609, provide information associated with the first memory address to the hypervisor layer (630).

[0111] In one embodiment, the hypervisor layer (630) may store information associated with a first memory address in a first memory area corresponding to the hardware layer (650) at operation 611. The electronic device may enhance security of critical information of a process while the process is not loaded into memory, for example, by storing the memory address of a PCB corresponding to the process in the memory area corresponding to the hardware layer (650).

[0112] In one embodiment, the hypervisor layer (630) may, at operation 613, change the memory address corresponding to the first process to a first value. In one embodiment, although operation 613 is illustrated in FIG. 6 as being performed after operation 611, the present invention is not limited thereto, and operation 613 may be performed before operation 611.

[0113] In one embodiment, the kernel layer (620) may, at operation 615, provide a context for the second process. In one embodiment, the application layer (610) may, at operation 617, execute the second process.

[0114] Figure 7 is a flowchart illustrating a method for restoring information associated with a process of an electronic device.

[0115] In the following embodiments, the operations may be performed sequentially, but are not necessarily sequential. For example, the order of the operations may be changed, and at least two operations may be performed in parallel. Depending on the implementation, certain operations may be omitted.

[0116] According to FIG. 7, in one embodiment, at operation 701, an electronic device (e.g., the electronic device (200) of FIG. 2A (e.g., the processor (210))) may identify a second event for context switching from a second process to a first process while the second process is executing.

[0117] According to one embodiment, in operation 703, the electronic device may store state information of the second process in a memory area corresponding to a hypervisor layer having a higher exception level than the kernel layer.

[0118] According to one embodiment, in operation 705, the electronic device may obtain information associated with a first memory address stored in a first memory area.

[0119] According to one embodiment, in operation 707, the electronic device may obtain status information of the first process.

[0120] According to one embodiment, at operation 709, the electronic device may execute a first process.

[0121] In one embodiment, the electronic device can enhance the security of information associated with a first process requiring a relatively high level of security by storing information associated with a memory address of a first PCB corresponding to the first process in a memory area corresponding to a hardware layer during a time period when the first process is not loaded into a physical memory.

[0122] FIG. 8 is a flowchart illustrating a method for restoring information associated with a process based on operations between multiple layers of an electronic device.

[0123] In the following embodiments, the operations may be performed sequentially, but are not necessarily sequential. For example, the order of the operations may be changed, and at least two operations may be performed in parallel. Depending on the implementation, certain operations may be omitted.

[0124] Referring to FIG. 8, in one embodiment, the application layer (610) may execute a second process in operation 801. The application layer (610) may identify a second event in operation 803. The application layer (610) may provide status information of the second process in operation 805.

[0125] In one embodiment, the kernel layer (620) may, at operation 807, obtain information associated with a second memory address corresponding to a second process. The kernel layer (620), at operation 809, may store the information associated with the second memory address in a memory area corresponding to the hypervisor layer (630).

[0126] In one embodiment, the hypervisor layer (630) may provide identification information of the first process at operation 811. The identification information of the first process may include, for example, a process identifier (PID), but is not limited thereto. In one embodiment, the hardware layer (650) may provide information associated with a first memory address at operation 813. The electronic device may enhance security of critical information of the first process by, for example, storing the memory address of the first PCB corresponding to the first process in a memory area corresponding to the hardware layer (650) while the first process is not loaded into memory.

[0127] In one embodiment, the hypervisor layer (630) may provide information associated with a first memory address at operation 815. The kernel layer (620) may obtain state information stored in the first PCB of the first process based on obtaining the information associated with the first memory address at operation 817. The kernel layer (620) may provide state information of the first process at operation 819.

[0128] In one embodiment, the application layer (640) may execute a first process at operation 821.

[0129] FIG. 9 is a flowchart illustrating a method for protecting information associated with a process based on identification information of the process of an electronic device.

[0130] In the following embodiments, the operations may be performed sequentially, but are not necessarily sequential. For example, the order of the operations may be changed, and at least two operations may be performed in parallel. Depending on the implementation, certain operations may be omitted.

[0131] According to FIG. 9, in one embodiment, at operation 901, an electronic device (e.g., electronic device (200) of FIG. 2A (e.g., processor (210))) may execute a first process including secure data on an application layer having a lower exception level than a kernel layer among a plurality of layers. In one embodiment, at least a portion of operation 901 may correspond to operation 501.

[0132] In one embodiment, at operation 903, the electronic device may identify a first event for context switching from the first process to the second process while the first process is executing. In one embodiment, at least a portion of operation 903 may correspond to operation 503.

[0133] According to one embodiment, in operation 905, the electronic device may determine whether the identification information of the first process corresponds to first information associated with at least one process including secure data based on the determination of the first event. Based on the determination that the identification information of the first process corresponds to the first information (operation 905: Yes), the electronic device may store information associated with the first memory address in the first memory area in operation 907. Based on the determination that the identification information of the first process does not correspond to the first information (operation 905: No), the electronic device may store state information of the first process in the memory area corresponding to the hypervisor layer having a higher exception level than the kernel layer in operation 909.

[0134] An electronic device according to one embodiment may store PCB address information of a process in a memory area corresponding to a hardware layer based on determining whether the identification information of a first process corresponds to information of a process requiring a relatively high level of security. By storing the PCB address information of the process in a memory area corresponding to the hardware layer, the electronic device may enhance the security of information associated with the process.

[0135] An electronic device according to one embodiment of the present disclosure may include a memory including a plurality of memory areas corresponding to each of a plurality of layers, and at least one processor.

[0136] According to one embodiment, the at least one processor may be configured to execute a first process including secure data on an application layer having an exception level lower than a kernel layer among the plurality of layers.

[0137] In one embodiment, the at least one processor may be configured to identify a first event for a context switch from the first process to the second process while the first process is executing.

[0138] According to one embodiment, the at least one processor may be configured to obtain information associated with a first memory address corresponding to the first process on the kernel layer based on identifying the first event.

[0139] According to one embodiment, the at least one processor may be configured to store information associated with the first memory address in a first memory area corresponding to a layer having a higher exception level than the kernel layer.

[0140] In one embodiment, the at least one processor may be configured to execute the second process based on the context switching.

[0141] In one embodiment, the at least one processor may be further configured to check for a second event for context switching from the second process to the first process while the second process is executing.

[0142] According to one embodiment, the at least one processor may be further configured to store state information of the second process in a memory area corresponding to a hypervisor layer having a higher exception level than the kernel layer.

[0143] According to one embodiment, the at least one processor may be further configured to obtain information associated with the first memory address stored in the first memory area.

[0144] According to one embodiment, the at least one processor may be further configured to obtain state information of the first process based on information associated with the obtained first memory address.

[0145] According to one embodiment, the at least one processor may be further configured to execute the first process based on state information of the first process.

[0146] In one embodiment, the layer having a higher exception level than the kernel layer may include a hardware layer.

[0147] In one embodiment, the at least one processor may be further configured to store state information of the first process in a first PCB (process control block) corresponding to the first process based on identifying the first event.

[0148] In one embodiment, the at least one processor may be further configured to determine, based on the identification of the first event, whether the identification information of the first process corresponds to first information associated with at least one process including security data.

[0149] According to one embodiment, the at least one processor may be further configured to store information associated with the first memory address in the first memory area based on verifying that the identification information of the first process corresponds to the first information.

[0150] According to one embodiment, the at least one processor may be further configured to store state information of the first process in a memory area corresponding to a hypervisor layer having a higher exception level than the kernel layer, based on determining that the identification information of the first process does not correspond to the first information.

[0151] According to one embodiment, the security data may include information associated with a page table base register (PTBR).

[0152] According to one embodiment, the security data may include at least one of information associated with a stack pointer (SP), information associated with a program counter (PC), or information associated with a current program status register (CPSR).

[0153] According to one embodiment, the at least one processor may be further configured to change a memory address corresponding to the first process stored in a memory area associated with the kernel layer to a first value based on storing information associated with the first memory address in the first memory area.

[0154] According to one embodiment, the at least one processor may be further configured to set at least one page table entry (PTE) corresponding to a layer having a lower exception level than the hypervisor layer, based on page table information stored in a memory area corresponding to the hypervisor layer.

[0155] A method according to one embodiment of the present disclosure may include executing a first process including secure data on an application layer having an exception level lower than a kernel layer among a plurality of layers.

[0156] In one embodiment, the method may include an operation of identifying a first event for context switching from the first process to a second process while the first process is executing.

[0157] According to one embodiment, the method may include an operation of obtaining information associated with a first memory address corresponding to the first process on the kernel layer based on verifying the first event.

[0158] According to one embodiment, the method may include storing information associated with the first memory address in a first memory area corresponding to a layer having a higher exception level than the kernel layer.

[0159] According to one embodiment, the method may include executing the second process based on the context switching.

[0160] In one embodiment, the method may further include an operation of identifying a second event for context switching from the second process to the first process while the second process is running.

[0161] According to one embodiment, the method may further include storing state information of the second process in a memory area corresponding to a hypervisor layer having a higher exception level than the kernel layer.

[0162] According to one embodiment, the method may further include an operation of obtaining information associated with the first memory address stored in the first memory area.

[0163] According to one embodiment, the method may further include an operation of obtaining status information of the first process based on information associated with the obtained first memory address.

[0164] According to one embodiment, the method may further include an operation of executing the first process based on the status information of the first process.

[0165] In one embodiment, the layer having a higher exception level than the kernel layer may include a hardware layer.

[0166] According to one embodiment, the method may further include an operation of storing state information of the first process in a first PCB (process control block) corresponding to the first process based on verifying the first event.

[0167] According to one embodiment, the method may further include an operation of determining, based on the determination of the first event, whether the identification information of the first process corresponds to first information associated with at least one process including security data.

[0168] According to one embodiment, the method may further include an operation of storing information associated with the first memory address in the first memory area based on verifying that the identification information of the first process corresponds to the first information.

[0169] According to one embodiment, the method may further include storing state information of the first process in a memory area corresponding to a hypervisor layer having a higher exception level than the kernel layer, based on determining that the identification information of the first process does not correspond to the first information.

[0170] According to one embodiment, the security data may include information associated with a page table base register (PTBR).

[0171] According to one embodiment, the method may further include an operation of changing a memory address corresponding to the first process stored in a memory area associated with the kernel layer to a first value based on storing information associated with the first memory address in the first memory area.

[0172] According to one embodiment, the method may further include an operation of setting at least one page table entry (PTE) corresponding to a layer having a lower exception level than the hypervisor layer, based on page table information stored in a memory area corresponding to the hypervisor layer.

[0173] In a storage medium storing computer-executable instructions according to one embodiment of the present disclosure, the instructions, when executed by at least one processor of an electronic device, can cause the electronic device to perform at least one operation.

[0174] In one embodiment, the at least one operation may include executing a first process including secure data on an application layer having an exception level lower than a kernel layer among the plurality of layers.

[0175] In one embodiment, the at least one operation may include an operation of identifying a first event for a context switch from the first process to a second process while the first process is executing.

[0176] In one embodiment, the at least one operation may include obtaining information associated with a first memory address corresponding to the first process on the kernel layer based on identifying the first event.

[0177] In one embodiment, the at least one operation may include storing information associated with the first memory address in a first memory area corresponding to a layer having a higher exception level than the kernel layer.

[0178] In one embodiment, the at least one operation may include executing the second process based on the context switching.

[0179] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects that are not mentioned will be clearly understood by a person having ordinary skill in the art to which the present disclosure pertains.

[0180] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to the embodiments of this document are not limited to the aforementioned devices.

[0181] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0182] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0183] Various embodiments of the present document may be implemented as software (e.g., a program (140)) including one or more instructions stored in a storage medium (e.g., an internal memory (136) or an external memory (138)) readable by a machine (e.g., an electronic device (101)). For example, a processor (e.g., a processor (120)) of the machine (e.g., an electronic device (101)) may call at least one instruction among the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0184] According to one embodiment, the method according to various embodiments disclosed in this document may be provided as included in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0185] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

In electronic devices, A memory including a plurality of memory areas corresponding to each of a plurality of layers and storing computer-executable instructions; and comprising one or more processors connected to communicate with said memory; The above instructions, when individually or collectively executed by the one or more processors, cause the electronic device to: On an application layer having an exception level lower than the kernel layer among the above multiple layers, a first process including secure data is executed, While the first process is running, a first event for context switching from the first process to the second process is identified, Based on the confirmation of the first event, information associated with the first memory address corresponding to the first process is obtained on the kernel layer, Store information associated with the first memory address in a first memory area corresponding to a layer having an exception level higher than the kernel layer, and An electronic device characterized in that it includes instructions set to execute the second process based on the context switching. In the first paragraph, The above instructions, when individually or collectively executed by the one or more processors, cause the electronic device to: While the second process is running, a second event for context switching from the second process to the first process is checked, Store the state information of the second process in a memory area corresponding to a hypervisor layer having an exception level higher than the kernel layer, Obtain information associated with the first memory address stored in the first memory area, Based on the information associated with the first memory address obtained above, status information of the first process is obtained, and An electronic device characterized in that it further includes instructions set to execute the first process based on the status information of the first process. In the first paragraph, An electronic device, characterized in that a layer having an exception level higher than the kernel layer includes a hardware layer. In the first paragraph, The above instructions, when executed individually or collectively by one or more processors, cause the electronic device to: An electronic device characterized in that it further includes an instruction set to store state information of the first process in a first PCB (process control block) corresponding to the first process based on confirming the first event. In the first paragraph, The above instructions, when individually or collectively executed by the one or more processors, cause the electronic device to: Based on the confirmation of the first event, it is confirmed whether the identification information of the first process corresponds to first information associated with at least one process including security data, and An electronic device characterized in that it further includes instructions set to store information associated with the first memory address in the first memory area based on confirmation that the identification information of the first process corresponds to the first information. In paragraph 5, The above instructions, when individually or collectively executed by the one or more processors, cause the electronic device to: An electronic device characterized in that it further includes an instruction set to store state information of the first process in a memory area corresponding to a hypervisor layer having a higher exception level than the kernel layer, based on confirmation that the identification information of the first process does not correspond to the first information. In the first paragraph, An electronic device, characterized in that the above security data includes information associated with a PTBR (page table base register). In the first paragraph, An electronic device, characterized in that the security data includes at least one of information associated with a stack pointer (SP), information associated with a program counter (PC), or information associated with a current program status register (CPSR). In the first paragraph, The above instructions, when individually or collectively executed by the one or more processors, cause the electronic device to: An electronic device characterized in that it further includes an instruction set to change a memory address corresponding to the first process stored in a memory area associated with the kernel layer to a first value based on storing information associated with the first memory address in the first memory area. In the first paragraph, The above instructions, when executed by the at least one processor, cause the electronic device to: An electronic device characterized in that it further includes an instruction set to set at least one PTE (page table entry) corresponding to a layer having a lower exception level than the hypervisor layer based on page table information stored in a memory area corresponding to the hypervisor layer. In terms of method, An operation of executing a first process containing secure data on an application layer having an exception level lower than the kernel layer among multiple layers; An operation of checking a first event for context switching from the first process to the second process while the first process is running; An operation of obtaining information associated with a first memory address corresponding to the first process on the kernel layer based on confirming the first event; An operation of storing information associated with the first memory address in a first memory area corresponding to a layer having an exception level higher than the kernel layer; and A method characterized by including an operation of executing the second process based on the context switching. In paragraph 11, An operation of checking a second event for context switching from the second process to the first process while the second process is running; An operation of storing state information of the second process in a memory area corresponding to a hypervisor layer having an exception level higher than the kernel layer; An operation of obtaining information associated with the first memory address stored in the first memory area; An operation of acquiring status information of the first process based on information associated with the acquired first memory address; and A method characterized in that it further includes an operation of executing the first process based on the status information of the first process. In paragraph 11, An operation of checking whether the identification information of the first process corresponds to first information associated with at least one process including security data based on the confirmation of the first event; and A method characterized in that it further includes an operation of storing information associated with the first memory address in the first memory area based on confirming that the identification information of the first process corresponds to the first information. In paragraph 11, A method characterized in that it further includes an operation of changing a memory address corresponding to the first process stored in a memory area associated with the kernel layer to a first value based on storing information associated with the first memory address in the first memory area. In a non-transitory storage medium storing computer-executable instructions, the instructions, when individually or collectively executed by one or more processors of an electronic device, cause the electronic device to perform at least one operation, At least one of the above actions, An operation of executing a first process containing secure data on an application layer having an exception level lower than the kernel layer among multiple layers; An operation of checking a first event for context switching from the first process to the second process while the first process is running; An operation of obtaining information associated with a first memory address corresponding to the first process on the kernel layer based on confirming the first event; An operation of storing information associated with the first memory address in a first memory area corresponding to a layer having an exception level higher than the kernel layer; and A non-transitory storage medium characterized by including an operation of executing the second process based on the context switching.

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