Adaptive power grid design

Abstract

Methods, systems, and apparatus, including computational instructions / programs encoded on a computer-readable medium, are disclosed for implementing adaptive power grid design procedures for designing power grids of a semiconductor device. A system generates a design of a power grid in a semiconductor device at least by identifying: i) a power switch in the design of the power grid, and ii) a first metal wire within a region associated with the power switch. For each end of the first metal wire, the system determines whether the end is extendable based on an extension rule and in response to determining that the end is extendable, the system modifies the design by adding an extension to the end of the first metal wire and adding a first via to connect the extension with another metal layer.

Description

ADAPTIVE POWER GRID DESIGNBACKGROUND

[0001] This specification generally relates to power grid planning in semiconductor devices.

[0002] A power grid structure is used in semiconductor devices in a wide range of applications. The power grid structure can control an electricity flow, such as routing the electricity flow and creating switches that turn the electricity flow on and off. As chip area keeps shrinking in modem semiconductor technology, the narrower metal pitch and smaller via size can become a major performance bottleneck of semiconductor devices. Furthermore, smaller chip sizes can also cause an increase in resistance of the semiconductor device, thereby inducing thermal issues and reliability' issues.SUMMARY

[0003] This specification describes power grid design systems, methods, and procedures for local optimization in electric current hotspots to alleviate the above-mentioned issues. In particular, inside power switch regions of a power grid, the described methods can extend an existing metal wire or adding new metal wire on an empty metal track. Outside the power switch regions of the power grid, the described method can form a continuous metal wire byconnecting discrete metal wires in different metal pillars. Vias can be added to connect the metal extension or the newly added metal wire to another metal layer, thereby reducing a resistance between adjacent metal layers. In addition, the described methods can be used to relocate critical cells to make them closer to power switches. Thus, a voltage drop from a power switch to a critical cell can be reduced.

[0004] One aspect of the subject matter described in this specification can be embodied in a computer-implemented method for generating a design of a power grid in a semiconductor device. The method includes identifying a powder switch in the design of the pow er grid and identifying a first metal wire within a region associated with the power switch. The first metal wire includes one or more ends. The method further includes, for each end of the one or more ends of the first metal wire: determining whether the end is extendable based on an extension rule; and in response to determining that the end is extendable, modifying the design by adding an extension to the end of the first metal wire and adding a first via to connect the extension with another metal layer.

[0005] In some implementations, the first metal wire extends in a first direction in a first metal layer of the power grid. The extension rule includes determining that the end is extendable in response to determining that an extendable margin of the end is larger than a sum of a minimum end-to-end space requirement of the first metal layer and a metal pitch requirement of an adjacent upper metal layer of the first metal layer. The extendable margin of the end is a distance along the first direction between the end and an end of a second metal wire on a same metal track as the first metal wire.

[0006] In some implementations, the method further includes determining a length of the extension of the end. The length of the extension equals the extendable margin minus the minimum end-end space requirement of the first metal layer. In some implementations, adding the first via includes adding the first via to connect the extension of the first metal wire with a third metal wire. The third metal wire is in the adjacent upper metal layer of the first metal layer and extends in a second direction perpendicular to the first direction.

[0007] In some implementations, the method further includes: identifying an empty metal track in a second metal layer of the power grid within the region; modifying the design by adding a fourth metal wire on the empty metal track; and adding a second via to connect the fourth metal wire with a fifth metal wire. The fifth metal wire is in an adjacent upper metal layer of the second metal layer. In some implementations, the method is performed in a floorplan stage of a power grid planning process.

[0008] Another aspect of this specification features a computer-implemented method for generating a design of a power grid in a semiconductor device. The method includes identifying two or more metal wires on a same metal track in a first metal layer in the design of the power grid. The two or more metal wires each belong to a separate metal pillar extending through the first metal layer. The method further includes determining whether the two or more metal wires are extendable based on an extension rule and in response to determining that the two or more metal wires are extendable, modifying the design by adding at least one extension on the same metal track to connect the two or more metal wires and adding a via to connect the at least one extension with a second metal wire.

[0009] In some implementations, the second metal wire is in an adjacent upper metal layer of the first metal layer. In some implementations, the extension rule includes determining that the two or more metal wires are extendable in response to determining that: the two or more metal wires are in a region with a functional cell density lower than a threshold; and a cell pin obstacle is absent from spaces between the two or more metal wires.In some implementations, the method is performed before a routing stage of a power grid planning process.

[0010] In some implementations, the extension rule includes determining that the two or more metal wires are extendable in response to determining that the two or more metal wires are in a region with a routing density lower than a threshold. In some implementations, the method is performed in a routing stage of a power grid planning process.

[0011] Another aspect of this specification features a computer-implemented method for generating a design of a power grid in a semiconductor device. The method includes identifying one or more critical cells in the design of the power grid based on at least one of: switching activities of the one or more critical cells, driving information of the one or more critical cells, or types of the one or more critical cells. The method further includes performing a location modification for the one or more critical cells based on at least one of keep out zones associated with the one or more critical cells, distances between the one or more critical cells and power switches, functional cell densities of regions associated with the one or more critical cells, or routing densities of the regions associated with the one or more critical cells.

[0012] In some implementations, the location modification includes, for each critical cell of the one or more critical cells, modifying a location of the critical cell to reduce a distance between the critical cell and a power switch until a keep out zone of the critical cell is in contact with either a keep out zone of another critical cell or the power switch. In some implementations, the method further includes determining a priority for each of the one or more critical cells. The location modification is performed in an order based on the priority for each of the one or more critical cells. In some implementations, the method is performed in a placement stage of a power grid planning process.

[0013] Another aspect of this specification features a power grid design system including at least one processor and at least one memory coupled to the at least one processor and storing programming instructions for execution by the at least one processor to cause the power grid design system to perform operations. The operations include identifying a power switch in a design of a power grid and identifying a first metal wire within a region associated with the power switch. The first metal wire includes one or more ends. The operations further include, for each end of the one or more ends of the first metal wire: determining whether the end is extendable based on an extension rule; and in response to determining that the end is extendable, modifying the design by adding an extension to the end of the first metal wire and adding a via to connect the extension with another metal layer.

[0014] In some implementations, the first metal wire extends in a first direction in a first metal layer of the power grid. The extension rule includes determining that the end is extendable in response to determining that an extendable margin of the end is larger than a sum of a minimum end-end space requirement of the first metal layer and a metal pitch requirement of an adjacent upper metal layer of the first metal layer. The extendable margin of the end is a distance along the first direction between the end and an end of a second metal wire on a same metal track as the first metal wire.

[0015] In some implementations, the operations further include determining a length of the extension of the end. The length of the extension equals the extendable margin minus the minimum end-end space requirement of the first metal layer. In some implementations, adding the via includes adding the via to connect the extension of the first metal wire with a third metal wire. The third metal wire is in the adjacent upper metal layer of the first metal layer and extends in a second direction perpendicular to the first direction.

[0016] Other implementations of this and other aspects include corresponding sy stems, apparatus, and computer programs, configured to perform the actions of the methods, encoded on computer storage devices. A system of one or more computers can be so configured by virtue of software, firmware, hardware, or a combination of them installed on the system that in operation causes the system to perform the actions. One or more computer programs can be so configured by virtue of having instructions that, when executed by a data processing apparatus, cause the apparatus to perform the actions.

[0017] The subject matter described in this specification can be implemented in particular embodiments to realize one or more of the following advantages.

[0018] The techniques described in this specification allow vias to be added to metal wires connected to a power switch of a semiconductor device. The modified metal wires can have reduced resistance while still satisfying technical requirements (such as a pitch requirement and a minimum end-to-end space requirement) on each metal layer. Power consumption of the semiconductor device can be reduced. In addition, discrete metal wires in different metal pillars can be connected together to form a continuous part, thereby creating multiple current paths and reducing circuit resistance without causing interferences to existing placement of functional cells and metal routing. Moreover, power design methods described in the specification can place critical cells closer to power switches to reduce voltage drops, thereby solving or mitigating reliability issues and functional failures that occur to the semiconductor device.

[0019] The details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other potential features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figs. 1A-1C illustrate an example semiconductor device having a power grid.

[0021] Figs. 2A-2B illustrate an example power grid design procedure for power switches.

[0022] Figs. 3A-3D illustrate an example power grid design procedure for metal pillars.

[0023] Figs. 4A-4B illustrate an example power grid design procedure for critical cell placement.

[0024] Fig. 5 illustrates a flow chart of an example powder grid design process.

[0025] Fig. 6 illustrates a flow- chart of an example power grid design procedure for pow er switches.

[0026] Fig. 7 illustrates a flow chart of an example power grid design procedure for critical cell placement.

[0027] Like reference numbers and designations in the various drawings indicate like elements.DETAILED DESCRIPTION

[0028] Figs. 1A-1C illustrate an example semiconductor device 100 having a power grid. Fig. 1A illustrates a top view of the semiconductor device 100. Figs. 1B-1C illustrate a perspective view and a side view of a cell of the semiconductor device 100, respectively. It is noted that X, Y, and Z axes (also referred to as X, Y, and Z directions) are included in Figs. 1 A-1C to further illustrate the spatial relationship of various components in the semiconductor device 100. A substrate (e.g., substrate 102) of the semiconductor device can include two lateral surfaces extending laterally in the X-Y plane: a top surface on the front side of the substrate on which a component of the semiconductor device can be formed, and a bottom surface on the backside opposite to the front side of the substrate. The Z direction is perpendicular to both the X and Y directions. As used in the present disclosure, whether one component (e.g., a layer or a device) is "on." ‘‘above,’’ or ‘‘below” another component (e.g., a layer or a device) of the semiconductor device is determined relative to the substrate of the semiconductor device in the Z direction (the vertical direction perpendicular to the X-Yplane, e.g., the thickness direction of the substrate) when the substrate is positioned in the lowest plane of the semiconductor device in the Z direction. The same notion for describing the spatial relationships is applied throughout the present disclosure.

[0029] The semiconductor device 100 can have the substrate 102 (as shown in Figs. 1B- 1C) on which various circuits 104 (such as combinational logic 104a, sequential logic 104b, and power switches 104c as shown in Fig. IB) are formed. Each of these circuits 104 can be referred to as a cell and can include transistors formed using suitable techniques such as complementary metal-oxide-semiconductor (CMOS), field effect transistor (FET) techniques, fin field effect transistor (FinFET) techniques, and gate-all-around (GAA) transistors, etc. In some implementations, the transistors of the cells 104 are arranged in an array and have gates 110 and source / drain contacts 112. The gates 110 and the contacts 112 can extend in a first horizontal direction (e.g., the X direction). In some instances, the gates 110 are made of a conductive material such as metal or polysilicon. As shown in Fig. 1A, the semiconductor device 100 have a plurality of cell placement rows, and each cell 104 may occupy one or more rows along the X direction. Each cell placement row can extend, for example, in a second horizontal direction (e.g., the Y direction) perpendicular to the first horizontal direction.

[0030] The power grid 106 of the semiconductor device 100 is coupled to the cells 104 and is configured to transmit power to the cells 104. For example, the power can be provided by an external power source coupled to the cells 104 by the power grid 106. The power grid 106 can include a plurality of metal layers 108 spaced along a vertical direction (e.g., the Z direction) perpendicular to both the first horizontal direction (e.g., the X direction) and the second horizontal direction (e.g., the Y direction). For example, as shown in Figs. 1A-1C, the metal layers 108 can include a first metal layer 108-1 coupled to the cell 104, a second metal layer 108-2 being above and coupled to the first metal layer 108-1, and a third metal layer 108-3 being above and coupled to the second metal layer 108-2. The first metal layer 108-1 and the third metal layer 108-3 can extend in the Y direction. The second metal layer 108-2 can extend in the X direction.

[0031] The power grid 106 further includes vias 114 connecting adjacent metal layers and / or connecting a metal layer (e g., the first metal layer 108-1) to the cell 104. As shown in Figs. 1B-1C, the vias 114 extend in the Z direction. It is understood that while three metal layers are shown in Figs. 1A-1C, this example is merely for illustration purpose. In practice, the semiconductor device 100 can have any suitable number of metal layers in the power grid

[0032] Figs. 2A-2B illustrate an example power grid design procedure for power switches. The power grid design procedure for power switches can include methods for designing metal wires coupled to a power switch. Fig. 2A shows a power switch 104c and metal wires in a power grid coupled to the power switch 104c. In this example, the power grid includes three metal layers. The metal wires include metal wires 202-1 in the first metal layer, metal wires 202-2 in the second metal layer, and metal wires 202-3 in the third metal layer. The metal wires can be within a region associated with the power switch 104c. For example, the region associated with the power switch 104c can be a cross section of the power switch 104c in the X-Y plane. The metal wires can be within the cross section in the X-Y plane. In the example of Fig. 2A, the power switch 104c is in a rectangular shape in the X-Y plane, thus the region associated with the power switch 104c is a rectangle determined by four sides of the power switch along the X direction and the Y direction. For example, a size of the region can be determined by a size of the power switch along the X direction and a size of the power switch along the Y direction.

[0033] The specification provides power grid design methods that can be used to extend a metal wire within the region associated with the power switch 104c. Such a power grid design procedure for the power switch can be performed by a power grid design system implemented by one or more computers in one or more locations, and which is generally referred to as the system in this specification. In some implementations, the system can include at least one processor and at least one memory coupled to the at least one processor and storing programming instructions for execution by the at least one processor to cause the powder grid design system to perform the power grid design procedure for the powder switch. In another example, the system can also perform the power grid design procedure for the power switch to add a new metal wire on an empty metal track within the region associated with power switch 104c. By extending the existing metal wire or adding the new metal wire and then adding vias to connect an extension of the existing metal wire or the newly added metal wire to a metal layer at a different level, the resistance betw een different metal layers can be reduced, thereby mitigating or solve the reliability issue or thermal issue caused by high resistance of the power grid.

[0034] In some implementations, the power grid design procedure uses an extension rule. In this specification, an extension rule specifies a set of conditions regarding a metal wire, based on which the system can determine that the metal wire is extendable. For example, the procedure can include identifying a power switch in a design of the power grid. The design of the power grid may be provided by an existing industry power grid design tool. The systemcan identify a first metal wire within a region associated with the power switch. The first metal wire can include one or more ends. The first metal wire can be in any appropriate metal layer. For example, the system can scan each metal layer and identify metal wires in each metal layer that has at least one end. For each end of the identified first metal wire, the system can determine whether the end is extendable based on the extension rule. In response to determining that the end is extendable, the system can modify the design by adding an extension to the end of the first metal wire and adding a first via to connect the extension with another metal layer.

[0035] In some implementations, the extension rule can be associated with parameters including, but not limited to, locations of the one or more ends of the first metal wire, locations of metal wires that are adjacent to the first metal wire and are in the same metal layer as the first metal wire, parameters of the design of the power grid, or any combination thereof. An example extension rule is described as below. The system can determine a metal layer (e.g., x-th metal layer Mxof the power grid) where the first metal wire is located. For each end of the first metal wire, the system can determine an extendable margin of the end (referred to as MxEM), a minimum end-to-end space requirement of the x-th metal layer (referred to as MXS), and a metal pitch requirement of the (x+l)-th metal layer (referred to as Mx+iP). The extendable margin of the end (MXEM) refers to a distance between the end and an end of a second metal wire. The second metal wire is adjacent to the first metal wire and is on a same metal track as the first metal wire, and the distance is measured along a direction of the metal track. As shown in Fig. 2A, metal wires 204-2 are adjacent to the metal wires 202-2 and are in the same metal layer (e.g., the second metal layer) as the metal wares 202-2. Metal wires 204-3 are adjacent to the metal wires 202-3 and are in the same metal layer (e.g., the third metal layer) as the metal wires 202-3. M2EM1. M2EM2, ..., M2EM10 represent extendable margin of ends of some of the metal wires 202-2, and M3EM1, M3EM2, ..., M3EM4 represent extendable margin of ends of the metal wires 202-3. In some implementations, MXS and Mx+iP can be determined based on the power grid design requirements on the x-th metal layer and the (x+l)-th metal layer.

[0036] The system can determine that the end is extendable in response to determining that MxEM > MxS + Mx+iP. In addition, the system can determine a length (referred to as MxEX) of an extension to be added to the end: MxEX = MxEM - MxS. This extension rule allows the extension added to the end of the first metal wire to overlap with a metal wire in the (x+l)-th metal layer. Thus, one or more vias can be added to connect the extension to the overlapping metal wire in the (x+l)-th metal layer. In some implementations, the overlappingmetal wire in the (x+l)-th metal layer extends in a direction perpendicular to the direction of the first metal wire. In addition, this extension rule can also allow the extended first metal wire to still satisfy the minimum end-to-end space requirement of the x-th metal layer. As shown in Fig. 2B, extensions 206-2 are added to some extendable metal wires 202-2, and extensions 206-3 are added to some extendable metal wires 202-3. A length of one of the extensions 206-2 is M2EX5, and a length of one of the extensions 206-3 is M3EX.

[0037] In some implementations, the power grid design procedure for power switches includes adding a new metal wire on an empty metal track of the power grid. The system can first identify an empty metal track in a metal layer of the pow er grid within the region associated with the power switch 104c. For example, as shown in Fig. 2A, a metal track (referred to as M3T) in the third metal layer is empty and is within the region associated with the power switch 104c. The system can modify the power grid design by adding a new metal wire (e.g., metal wire 208 as shown in Fig. 2B) on the empty metal track M3T. A length (referred to as MxL) of the new' metal wire can be determined based on a direction of the empty metal track and a size of the power switch 104c. For example, if the empty metal track MxT extends along the X direction, then MxL is equal to a size of the power switch 104c along the X direction. Otherwise, if the empty metal track MXT extends along the Y direction, then MxL is equal to a size of the power switch 104c along the Y direction. After adding the new metal wire on the empty metal track, the system can add one or more vias to connect the new metal wire with another metal wire. The other metal wire is in an adjacent upper metal layer of the new metal layer and overlaps with the new metal layer.

[0038] Figs. 3A-3D illustrate an example power grid design procedure for metal pillars. Fig. 3A show s a top view' of a pow er grid 300a. The power grid 300a includes metal wires 301 in a first metal layer (e.g., Mi) and metal wires 302 in a second metal layer (e.g.. M2). The power grid 300a can be coupled to power switches 104c. The metal wires 302 include metal wires 302a, 302b, and 302c that are on a same metal track extending in the Y direction. In some implementations, the metal wires 302 can be outside of the pow er sw itch regions. The metal wires 302a, 302b, and 302c may belong to separate metal pillars extending through the metal layer M2. A metal pillar refers to a structure that includes metal wires in different metal layers and vias in between these metal wires. The metal wires and vias are stacked along the vertical direction (e.g., the Z direction) and carry a single current path. In other words, the metal pillar that extends through the x-th metal layer Mxonly includes one metal wire in the metal layer Mx. As shown in Fig. 3 A, although metal wire 302a and metal wire 302b are on the same metal track, they belong to separate metal pillars and thus are isolatedfrom each other in the metal layer M2. Adding an extension connecting metal wire 302a and metal wire 302b may reduce the resistance of the power grid. For example, if a metal wire 303 in the third metal layer M3 is located between the metal wires 302a and 302b, a via can be added to connect the extension (between the metal wire 302a and the metal wire 302b) with the metal wire 303, thereby reducing the resistance between the metal wires 302a-302b and the metal wire 303.

[0039] The power grid design procedure for metal pillars can include identifying two or more metal wires on a same metal track in a metal layer Mxin the design of the power grid. The two or more metal wires each belong to a separate metal pillar extending through the metal layer Mx. The system that performs the power grid design procedure for metal pillars can determine whether the two or more metal wires are extendable based on an extension rule. In response to determining that the two or more metal wires are extendable, the system can modify the design by adding at least one extension on the same metal track to connect the two or more metal wires and adding a via to connect the at least one extension with another metal wire. The other metal wire is in an adjacent upper metal layer (e.g., Mx+i) of the metal layer Mx.

[0040] In some implementations, the extension rule for the power grid design procedure for metal pillars can be based on a functional cell densify as shown in Fig. 3B. A cross section (in the X-Y plane) of a power grid 300b can be divided into multiple regions or tiles. Each region can include a number of functional cells such as sequential cells and combinational cells. A functional cell densify of a region refers to a number of functional cells in the region divided by a size of the region. As shown in Fig. 3B, a region 304 and a region 306 has the same size. Compared to the region 306, there are more functional cells within the region 304. Thus, the region 304 has a higher functional cell densify than the region 306.

[0041] A functional cell densify based extension rule is described as below. The system can determine that the tw o or more metal wires are extendable in response to determining that the two or more metal wires are in a region with a functional cell densify lower than a threshold and that a cell pin obstacle is absent from spaces betw een the two or more metal wires. If a region has a higher functional cell densify, the system may need to reserve empty metal tracks for cell routing instead of adding extensions on the metal tracks. In addition, a cell pin obstacle between the metal wires may block the extension connecting the metal wires.

[0042] In some other implementations, the extension rule for the power grid design procedure for metal pillars can be based on a routing density. A routing density of a region can be defined as a number of occupied metal tracks in this region divided by a number of metal tracks in this region. As shown in Fig. 3C, a region 308 and a region 310 have the same size and are in the same metal layer. The region 308 and the region 310 both have five metal tracks, which can be determined by technology assumption of this metal layer. All five metal tracks in region 308 are occupied by five metal wires as shown in Fig. 3C. Thus, a routing density of the region 308 is 100%. Region 310 has two empty metal tracks. Thus, a routing density of the region 310 is 60%. According to a routing density based extension rule, the system can determine that the two or more metal wires are extendable in response to determining that the two or more metal wires are in a region with a routing density lower than a threshold.

[0043] Fig. 3D illustrates a power grid 300d generated by applying a power grid design procedure for metal pillars to the power grid 300a. As shown in Fig. 3D, the system determines that the metal wires 302 in regions 312 are extendable based on an extension rule (e.g., a functional cell density based extension rule or a routing density based extension rule). Compared to the power grid 300a of Fig. 3 A, in each region 312, metal wires 302 on a same metal track are connected by extensions and form a continuous metal wire 314. The continuous metal wires 314 can overlap with metal wires 303 in an adjacent upper metal layer (e.g., the third metal layer Ms). The system can then add vias to connect the metal wires 314 and the metal wires 303, thereby reducing resistance of the power grid 300d.

[0044] Figs. 4A-4B illustrate an example power grid design procedure for critical cell placement. A voltage drop is caused by a current flowing through a resistor, and thus is also referred to as an IR drop. An IR drop critical cell (also referred to as critical cell) is a functional cell that is prone to have higher voltage drop across it. When a functional cell is away from a power switch, a resistance between the functional cell and the power switch can be increased because the path is longer. The voltage from the power switch may undergo a larger drop when it reaches the functional cell, thereby causing reliability issues or functional failures. Thus, it can be important in power grid design to place critical cells closer to power switches to reduce the voltage drop.

[0045] In some implementations, the power grid design procedure for critical cell placement includes identify ing one or more critical cells in the design of the power grid. The system can identity’ critical cells based on factors including, but not limited to, switching activities of the one or more critical cells, driving information of the one or more criticalcells, types of the one or more critical cells, or any combination thereof. The system can perform a location modification for the one or more critical cells. In some implementations, the location modification can be based on factors including, but not limited to, keep out zones associated with the one or more critical cells, distances between the one or more critical cells and power switches, functional cell densities of regions associated with the one or more critical cells, routing densities of the regions associated with the one or more critical cells, or any combination thereof. A keep out zone (as shown in Figs. 4A-4B) of a critical cell is an area surrounding the critical cell, which blocks other cells to be placed abutted to the critical cell. In some implementations, the keep out zone of the critical cell can be determined based on requirements of the power grid and / or technology assumption.

[0046] In some implementations, the location modification can be performed for each critical cell of the one or more critical cells. For example, the system can modify a location of the critical cell to reduce a distance between the critical cell and a power switch until a keep out zone of the critical cell is in contact with either a keep out zone of another critical cell or the power switch. Any suitable distance metrics (e.g., Manhattan distance) can be used in the critical cell placement.

[0047] In some implementations, the power grid design procedure for critical cell placement can also include determining a priority' for each of the one or more critical cells. The system can perform the location modification in an order determined based on the priority for each of the one or more critical cells. For example, the priority can be based on a cost function calculated for each of the one or more critical cells. An example of the cost function can be a voltage drop across the critical cell multiplied by a Manhattan distance between the critical cell and the closest power switch. The system can move a group (e.g., 10%) of critical cells in the power grid that has the highest cost function.

[0048] In the example of Fig. 4A, two critical cells 401 and 402 are identified by the system according to the power grid design procedure for critical cell placement. The critical cells 401 and 402 are coupled to the same power switch 403 in an initial power grid design illustrated by Fig. 4A. Distance 405 represents the Manhattan distance between the critical cell 401 and the power switch 403, and distance 406 represents the Manhattan distance between the critical cell 402 and the power switch 403. As shown in Fig. 4A, the critical cells 401 and 402 can have a keep out zone issue, as their keep out zones overlap with each other.

[0049] Fig. 4B illustrates new locations of the critical cells 401 and 402 determined based on the power grid design procedure for critical cell placement. As shown in Fig. 4B, the critical cell 401 is moved along the Y direction towards the power switch 403 until the keepout zone of the critical cell 401 is in contact with the power switch 403 and the keep out zone of the critical cell 402. The critical cell 402 is moved along both the X direction and the Y direction towards another power switch 404 and is coupled to the power switch 404. As a result, the distances 405 and 406 between the critical cells 401 and 402 and adjacent power switches are shorter than those in Fig. 4A.

[0050] Fig. 5 illustrates a flow chart of an example power grid design process 500 (also referred to as a power grid planning process) including the power grid design procedures described above. The power grid design process 500 includes various stages such as a floorplan stage 502, a placement stage 504, a clock tree synthesis (CTS) stage 506, a global routing stage 508, and a detailed routing stage 510. In the floorplan stage 502, the system can position large pre-designed blocks (e.g.. static random-access memories (SRAMs), read-only memories (ROMs), IP blocks) onto a floorplan of a semiconductor device and design a power grid to ensure adequate power supply to various parts of the device. The placement stage 504 can include a global placement including initial rough placement of standard cells (e.g., logic gates and flip-flops) on the device and a detailed placement including fine-tuning cell positions to optimize timing, power, and congestion of the device. In the CTS stage 506, the system can insert clock buffers to drive the clock signal throughout the device and balance the clock tree to minimize skew. In some implementations, the system may optimize the clock tree to meet timing requirements of the device while minimizing pow er consumption and area of the device. In the global routing stage 508, the system can determine approximate paths for signal wires between functional cells while considering congestion and timing constraints of the device. The detailed routing stage 510 can include assignment of specific metal layers and metal tracks for each wire segment to ensure signal integrity and minimizing delay of signal transmission.

[0051] The power grid design procedures described in this disclosure, such as the power grid design procedure for powder switches (e.g., as described with reference to Figs. 2A-2B), the pow er grid design procedure for metal pillars (e.g., as described with reference to Figs. 3A-3D), and the power grid design procedure for critical cell placement (e.g., as described with reference to Figs. 4A-4B), can be performed in any suitable pow er grid design stages. For example, the power grid design procedure for power switches can be performed in the floorplan stage 502. As show n in Fig. 5, at operation 512 of the floorplan stage 502, a baseline power grid including power switches on N metal layers can be provided. At operation 514 of the floorplan stage 502, the system can check whether an extension rule (e.g., as described with reference to Figs. 2A-2B) can be applied to any power switches onmetal layer Mx. At operation 516, if the extension rule applies, the system can perform the power grid design procedure for power switches (e.g.. extending an existing metal wire or adding a new metal wire on an empty metal track and adding connecting vias accordingly) in the metal layer Mx. Operations 514 and 516 can be iterated for each layer (e.g., 1 < x < N).

[0052] The power grid design procedure for critical cell placement can be performed in the placement stage 504. After the iteration of operation 514, the power grid design process 500 proceeds to the placement stage 504. At operation 518 of the placement stage 504. the system can check whether there are any critical cells in the power grid. At operation 520 of the placement stage 504, the system can apply the power grid design procedure for critical cell placement to the identified critical cells (for example, to reduce distances between each critical cell and an adjacent power switch).

[0053] The power grid design procedure for metal pillars can be performed in the CTS stage 506, or the detailed routing stage 510, or both. For example, the power grid design process 500 can proceed from the operation 518 to operation 522 of the CTS stage 506. At operation 522, the clock tree of the device can be optimized by. for example, a machine learning based optimization method. At operation 524 of the CTS stage 506, the system can check whether a functional cell density based extension rule (e.g., as described with reference to Fig. 3B) can be applied to metal pillars in metal layer Mx. At operation 526, if the above extension rule applies, the sy stem can perform the power grid design procedure for metal pillars in the metal layer Mx. Operations 524 and 526 can be iterated for each layer (e.g.. 1 < x < N). After the iteration of operation 524, the power grid design process 500 can proceed to the global routing stage 508.

[0054] In some implementations, the system can also perform the power grid design procedure for metal pillars in the detailed routing stage 510. For example, at operation 528 of the detailed routing stage 510, the system can check whether a routing density based extension rule (e.g., as described with reference to Fig. 3C) can be applied to metal pillars in metal layer Mx. At operation 530, if the above extension rule applies, the system can perform the power grid design procedure for metal pillars in the metal layer Mx. Similarly, operations 528 and 530 can also be iterated for each layer (e.g., 1 < x < N). After the iteration, the power grid design process 500 can proceed to operation 532, where the design of the power grid can be stored in a database.

[0055] Fig. 6 illustrates a flow chart 600 of an example power grid design procedure for power switches. The power grid design procedure for power switches illustrated by the flow chart 600 can be performed by a power grid design system described in the disclosure. Thepower grid design procedure for power switches can be used to generate or modify a design of a power grid in a semiconductor device.

[0056] At operation 602, the system can identify a power switch (e.g., power swtich 104c of Fig. 2A) in the design of the power grid.

[0057] At operation 604, the system can identify' a first metal wire (e.g., some of the metal wires 202-2 and metal wires 204-3 of Fig. 2A) within a region associated with the power switch. The first metal wire can include one or more ends.

[0058] Operation 606 can be performed for each end of the one or more ends of the first metal wire. Operation 606 can include operations 608 and 610. At operation 608, the system can determine whether the end is extendable based on an extension rule. At operation 610, in response to determining that the end is extendable, the system can modify the design by adding an extension (e.g., as described with reference to Fig. 2B) to the end of the first metal wire and adding a first via to connect the extension with another metal layer.

[0059] In some implementations, the first metal wire extends in a first direction (e.g., the X direction) in a first metal layer (e.g., metal layer M2) of the power grid. The extension rule can include determining that the end is extendable in response to determining that an extendable margin (e.g., M2EM) of the end is larger than a sum of a minimum end-to-end space requirement (e.g., M2S) of the first metal layer and a metal pitch requirement (e.g., M 3P) of an adjacent upper metal layer of the first metal layer. The extendable margin of the end can be a distance along the first direction between the end and an end of a second metal wire on a same metal track as the first metal wire.

[0060] In some implementations, the power grid design procedure for power switches further includes determining a length (e.g., M2EX) of the extension of the end. The length of the extension equals the extendable margin minus the minimum end-end space requirement of the first metal layer.

[0061] In some implementations, adding the first via includes adding the first via to connect the extension of the first metal wire with a third metal wire. The third metal wire is in the adjacent upper metal layer of the first metal layer and extends in a second direction (e.g.. the Y direction) perpendicular to the first direction.

[0062] In some implementations, the power grid design procedure for power switches further includes identifying an empty metal track (e.g., M3T of Fig. 2B) in a second metal layer (e.g., M3) of the power grid within the region. The system can modify the design by adding a fourth metal wire on the empty metal track and add a second via to connect thefourth metal wire with a fifth metal wire. The fifth metal wire is in an adjacent upper metal layer (e.g., M4) of the second metal layer.

[0063] In some implementations, the power grid design procedure for power switches can be performed in a floorplan stage (e.g., operations 514 and 516 in the floorplan stage 502 of Fig. 5) of a power grid planning process.

[0064] Fig. 7 illustrates a flow chart 700 of an example power grid design procedure for critical cell placement. The power grid design procedure for critical cell placement illustrated by the flow chart 700 can be performed by a power grid design system described in the disclosure. The power grid design procedure for critical cell placement can be used to generate or modify a design of a power grid in a semiconductor device.

[0065] At operation 702. the system can identify one or more critical cells (e.g., critical cells 401 and 402 of Figs. 4A-4B) in the design of the power grid based on at least one of: switching activities of the one or more critical cells, driving information of the one or more critical cells, or ty pes of the one or more critical cells.

[0066] At operation 704. the system can perform a location modification (e.g., as described with reference to Fig. 4B) for the one or more critical cells based on at least one of: keep out zones (as shown in Figs. 4A-4B) associated with the one or more critical cells, distances (e.g., Manhattan distances 405 and 406 of Figs. 4A-4B) between the one or more critical cells and power switches (e.g., power sw itches 403 and 404 of Figs. 4A-4B), functional cell densities of regions associated with the one or more critical cells, or routing densities of the regions associated with the one or more critical cells.

[0067] Embodiments of the subject matter and the functional operations described in this specification can be implemented in digital electronic circuitry, in tangibly-embodied computer software or firmware, in computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible non transitory program carrier for execution by, or to control the operation of. data processing apparatus.

[0068] Alternatively or in addition, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. The computer storagemedium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them.

[0069] The term '‘computing system” encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0070] A computer program (which may also be referred to or described as a program, software, a software application, a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0071] A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub programs, or portions of code. A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication netw ork.

[0072] The processes and logic flows described in this specification can be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or a GPGPU (General purpose graphics processing unit).

[0073] Computers suitable for the execution of a computer program include, by way of example, can be based on general or special purpose microprocessors or both, or any other kind of central processing unit. Generally, a central processing unit will receive instructions and data from a read only memory or a random access memory or both. Some elements of a computer are a central processing unit for performing or executing instructions and one ormore memory' devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices. Moreover, a computer can be embedded in another device, e.g., a mobile telephone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a Global Positioning System (GPS) receiver, or a portable storage device, e.g., a universal serial bus (USB) flash drive, to name just a few.

[0074] Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disks, e.g., internal hard disks or removable disks; magneto optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0075] To provide for interaction with a user, embodiments of the subject matter described in this specification can be implemented on a computer having a display device, e.g., LCD (liquid crystal display) monitor, for displaying information to the user and a keyboard and a pointing device, e.g., a mouse or a trackball, by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user's client device in response to requests received from the web browser.

[0076] Embodiments of the subject matter described in this specification can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN’’), e.g., the Internet.

[0077] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0078] In addition to the embodiments described above, the following embodiments are also innovative:

[0079] Embodiment 1 is a computer-implemented method for generating a design of a power grid in a semiconductor device, the method comprising:

[0080] identifying a power switch in the design of the power grid;

[0081] identifying a first metal wire within a region associated with the power switch, wherein the first metal wire comprises one or more ends; and

[0082] for each end of the one or more ends of the first metal wire:

[0083] determining whether the end is extendable based on an extension rule; and

[0084] in response to determining that the end is extendable, modifying the design byadding an extension to the end of the first metal wire and adding a first via to connect the extension with another metal layer.

[0085] Embodiment 2 is the method of embodiment 1 , wherein the first metal wire extends in a first direction in a first metal layer of the power grid, and wherein the extension rule comprises:

[0086] determining that the end is extendable in response to determining that an extendable margin of the end is larger than a sum of a minimum end-to-end space requirement of the first metal layer and a metal pitch requirement of an adjacent upper metal layer of the first metal layer, wherein the extendable margin of the end is a distance along the first direction between the end and an end of a second metal wire on a same metal track as the first metal wire.

[0087] Embodiment 3 is the method of any one of embodiments 1-2, further comprising determining a length of the extension of the end, wherein the length of the extension equals the extendable margin minus the minimum end-end space requirement of the first metal layer.

[0088] Embodiment 4 is the method of any one of embodiments 1-3, wherein adding the first via comprises:

[0089] adding the first via to connect the extension of the first metal wire with a third metal wire, wherein the third metal wire is in the adjacent upper metal layer of the first metal layer and extends in a second direction perpendicular to the first direction.

[0090] Embodiment 5 is the method of any one of embodiments 1-4, further comprising:

[0091] identifying an empty metal track in a second metal layer of the power grid within the region;

[0092] modifying the design by adding a fourth metal wire on the empty metal track; and

[0093] adding a second via to connect the fourth metal wire with a fifth metal wire, wherein the fifth metal wire is in an adjacent upper metal layer of the second metal layer.

[0094] Embodiment 6 is the method of any one of embodiments 1-5, wherein the method is performed in a floorplan stage of a power grid planning process.

[0095] Embodiment 7 is a computer-implemented method for generating a design of a power grid in a semiconductor device, the method comprising:

[0096] identifying two or more metal wires on a same metal track in a first metal layer in the design of the power grid, wherein the two or more metal wires each belong to a separate metal pillar extending through the first metal layer;

[0097] determining whether the two or more metal wires are extendable based on an extension rule; and

[0098] in response to determining that the two or more metal wires are extendable, modifying the design by adding at least one extension on the same metal track to connect the two or more metal wires and adding a via to connect the at least one extension with a second metal wire.

[0099] Embodiment 8 is the method of embodiment 7, wherein the second metal wire is in an adjacent upper metal layer of the first metal layer.

[0100] Embodiment 9 is the method of any one of embodiments 7-8, wherein the extension rule comprises:

[0101] determining that the two or more metal wires are extendable in response to determining that:

[0102] the two or more metal wires are in a region with a functional cell densify lower than a threshold: and

[0103] a cell pin obstacle is absent from spaces between the two or more metal wires.

[0104] Embodiment 10 is the method of any one of embodiments 7-9, wherein the method is performed before a routing stage of a power grid planning process.

[0105] Embodiment 11 is the method of any one of embodiments 7-10, wherein the extension rule comprises:

[0106] determining that the two or more metal wires are extendable in response to determining that the two or more metal wires are in a region with a routing density lower than a threshold.

[0107] Embodiment 12 is the method of any one of embodiments 7-11, wherein the method is performed in a routing stage of a power grid planning process.

[0108] Embodiment 13 is a computer-implemented method for generating a design of a power grid in a semiconductor device, the method comprising:

[0109] identifying one or more critical cells in the design of the power grid based on at least one of: switching activities of the one or more critical cells, driving information of the one or more critical cells, or types of the one or more critical cells; and

[0110] performing a location modification for the one or more critical cells based on at least one of: keep out zones associated with the one or more critical cells, distances between the one or more critical cells and power switches, functional cell densities of regions associated with the one or more critical cells, or routing densities of the regions associated with the one or more critical cells.

[0111] Embodiment 14 is the method of embodiment 13, wherein the location modification comprises, for each critical cell of the one or more critical cells:

[0112] modifying a location of the critical cell to reduce a distance between the critical cell and a power switch until a keep out zone of the critical cell is in contact with either a keep out zone of another critical cell or the power switch.

[0113] Embodiment 15 is the method of any one of embodiments 13-14, further comprising:

[0114] determining a priority for each of the one or more critical cells, wherein the location modification is performed in an order based on the priority for each of the one or more critical cells.

[0115] Embodiment 16 is the method of any one of embodiments 13-15, wherein the method is performed in a placement stage of a power grid planning process.

[0116] Embodiment 17 is A power grid design system comprising:

[0117] at least one processor; and

[0118] at least one memory coupled to the at least one processor and storing programming instructions for execution by the at least one processor to cause the power grid design system to perform operations comprising:

[0119] identifying a power switch in a design of a power grid;

[0120] identifying a first metal wire within a region associated with the power switch, wherein the first metal wire comprises one or more ends; and

[0121] for each end of the one or more ends of the first metal wire:

[0122] determining whether the end is extendable based on an extension rule; and

[0123] in response to determining that the end is extendable, modifying the design by adding an extension to the end of the first metal wire and adding a via to connect the extension with another metal layer.

[0124] Embodiment 18 is the power grid design system of embodiment 17, wherein the first metal wire extends in a first direction in a first metal layer of the power grid, and wherein the extension rule comprises:

[0125] determining that the end is extendable in response to determining that an extendable margin of the end is larger than a sum of a minimum end-end space requirement of the first metal layer and a metal pitch requirement of an adjacent upper metal layer of the first metal layer, wherein the extendable margin of the end is a distance along the first direction between the end and an end of a second metal wire on a same metal track as the first metal wire.

[0126] Embodiment 19 is the power grid design system of any one of embodiments 17 and 18. wherein the operations further comprise determining a length of the extension of the end, wherein the length of the extension equals the extendable margin minus the minimum end-end space requirement of the first metal layer.

[0127] Embodiment 20 is the power grid design system of any one of embodiments 17- 19, wherein adding the via comprises:

[0128] adding the via to connect the extension of the first metal wire with a third metal wire, wherein the third metal wire is in the adjacent upper metal layer of the first metal layer and extends in a second direction perpendicular to the first direction.

[0129] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations andeven initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0130] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0131] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

WHAT IS CLAIMED IS:

1. A computer-implemented method for generating a design of a power grid in a semiconductor device, the method comprising: identifying a power switch in the design of the power grid; identifying a first metal wire within a region associated with the power switch, wherein the first metal wire comprises one or more ends; and for each end of the one or more ends of the first metal wire: determining whether the end is extendable based on an extension rule; and in response to determining that the end is extendable, modifying the design by adding an extension to the end of the first metal wire and adding a first via to connect the extension with another metal layer.

2. The method of claim 1, wherein the first metal wire extends in a first direction in a first metal layer of the power grid, and wherein the extension rule comprises: determining that the end is extendable in response to determining that an extendable margin of the end is larger than a sum of a minimum end-to-end space requirement of the first metal layer and a metal pitch requirement of an adjacent upper metal layer of the first metal layer, wherein the extendable margin of the end is a distance along the first direction between the end and an end of a second metal wire on a same metal track as the first metal wire.

3. The method of any one of claims 1-2, further comprising determining a length of the extension of the end, wherein the length of the extension equals the extendable margin minus the minimum end-end space requirement of the first metal layer.

4. The method of any one of claims 1-3, wherein adding the first via comprises: adding the first via to connect the extension of the first metal wire with a third metal wire, wherein the third metal wire is in the adjacent upper metal layer of the first metal layer and extends in a second direction perpendicular to the first direction.

5. The method of any one of claims 1-4, further comprising: identifying an empty metal track in a second metal layer of the power grid within the region;modifying the design by adding a fourth metal wire on the empty metal track; and adding a second via to connect the fourth metal wire with a fifth metal wire, wherein the fifth metal wire is in an adjacent upper metal layer of the second metal layer.

6. The method of claim 1 , wherein the method is performed in a floorplan stage of a power grid planning process.

7. A computer-implemented method for generating a design of a power grid in a semiconductor device, the method comprising: identifying two or more metal wires on a same metal track in a first metal layer in the design of the power grid, wherein the two or more metal wires each belong to a separate metal pillar extending through the first metal layer; determining whether the two or more metal wires are extendable based on an extension rule; and in response to determining that the two or more metal wires are extendable, modifying the design by adding at least one extension on the same metal track to connect the two or more metal wires and adding a via to connect the at least one extension with a second metal wire.

8. The method of claim 7, wherein the second metal wire is in an adjacent upper metal layer of the first metal layer.

9. The method of any one of claims 7-8, wherein the extension rule comprises: determining that the two or more metal wires are extendable in response to determining that: the two or more metal wires are in a region with a functional cell density lower than a threshold; and a cell pin obstacle is absent from spaces between the two or more metal wires.

10. The method of any one of claims 7-9, wherein the method is performed before a routing stage of a power grid planning process.

11. The method of any one of claims 7-10, wherein the extension rule comprises:determining that the two or more metal wires are extendable in response to determining that the two or more metal wires are in a region with a routing density lower than a threshold.

12. The method of claim 11, wherein the method is performed in a routing stage of a power grid planning process.

13. A computer-implemented method for generating a design of a power grid in a semiconductor device, the method comprising: identifying one or more critical cells in the design of the power grid based on at least one of: switching activities of the one or more critical cells, driving information of the one or more critical cells, or types of the one or more critical cells; and performing a location modification for the one or more critical cells based on at least one of: keep out zones associated with the one or more critical cells, distances between the one or more critical cells and power switches, functional cell densities of regions associated with the one or more critical cells, or routing densities of the regions associated with the one or more critical cells.

14. The method of claim 13, wherein the location modification comprises, for each critical cell of the one or more critical cells: modifying a location of the critical cell to reduce a distance between the critical cell and a power switch until a keep out zone of the critical cell is in contact with either a keep out zone of another critical cell or the power switch.

15. The method of any one of claims 13-14, further comprising: determining a priority for each of the one or more critical cells, wherein the location modification is performed in an order based on the priority for each of the one or more critical cells.

16. The method of any one of claims 13-15, wherein the method is performed in a placement stage of a power grid planning process.

17. A power grid design system comprising: at least one processor; andat least one memory coupled to the at least one processor and storing programming instructions for execution by the at least one processor to cause the power grid design system to perform operations comprising: identifying a power switch in a design of a power grid; identifying a first metal wire within a region associated with the power switch, wherein the first metal wire comprises one or more ends; and for each end of the one or more ends of the first metal wire: determining whether the end is extendable based on an extension rule; and in response to determining that the end is extendable, modifying the design by adding an extension to the end of the first metal wire and adding a via to connect the extension with another metal layer.

18. The power grid design system of claim 17, wherein the first metal wire extends in a first direction in a first metal layer of the power grid, and wherein the extension rule comprises: determining that the end is extendable in response to determining that an extendable margin of the end is larger than a sum of a minimum end-end space requirement of the first metal layer and a metal pitch requirement of an adjacent upper metal layer of the first metal layer, wherein the extendable margin of the end is a distance along the first direction between the end and an end of a second metal wire on a same metal track as the first metal wire.

19. The power grid design system of any one of claims 17-18, wherein the operations further comprise determining a length of the extension of the end, w herein the length of the extension equals the extendable margin minus the minimum end-end space requirement of the first metal layer.

20. The power grid design system of any one of claims 17-19, wherein adding the via comprises: adding the via to connect the extension of the first metal wire with a third metal wire, wherein the third metal wire is in the adjacent upper metal layer of the first metal layer and extends in a second direction perpendicular to the first direction.

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