Multiplexing memory module

Abstract

Memory devices on a memory module may include two (or more) interfaces that access non-overlapping sets of memory arrays (i.e., two pseudo-channels). The data bus directionality of each of the two pseudo-channels may be specified or required to always be in the same direction (i.e., both read, or both write). When the data bus directionalities are tied in this manner, the data buffer devices of the module may interleave / deinterleave (i.e., time-multiplex) data for communication with a host between the two pseudo-channel data busses. The data bus directionality of each of the two pseudo-channels may be independent of the directionality of the other pseudo-channel (i.e., either can read or write without regard to the data bus directionality of the other). When the data bus directionalities are independent in this manner, the data buffer devices may interleave / deinterleave data for communication with a host within each of the two pseudo-channel data busses.

Description

MULTIPLEXING MEMORY MODULE BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figures 1 A-1C are block diagrams illustrating a memory system.

[0002] Figure 2 is a block diagram illustrating a memory module with independent rank access.

[0003] Figure 3 is a block diagram illustrating a memory module with independent rank and pseudo-channel access.

[0004] Figures 4A-4B are timing diagrams illustrating an example interleaving of data across memory device pseudo-channels.

[0005] Figures 5A-5B are timing diagrams illustrating an example interleaving of data within a pseudo-channel.

[0006] Figure 6 is a timing diagram illustrating two successive data buffer read commands.

[0007] Figure 7 is a timing diagram illustrating a data buffer read command and a data buffer write command in immediate succession.

[0008] Figure 8 is a flowchart illustrating a method of operating a data buffer device to interleave data across memory device pseudo-channels.

[0009] Figure 9 is a flowchart illustrating a method of operating a data buffer device to interleave data within a pseudo-channel.

[0010] Figure 10 is a block diagram of a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] In an embodiment, the memory devices on a memory module may include two (or more) interfaces that access non-overlapping sets of memory arrays (i.e., two pseudo-channel data busses). This may be implemented, for example, using a single die and single command / address bus, or multiple co-packaged dies that share a single command / address bus. In an embodiment, the data bus directionality of each of the two pseudo-channels are specified or required to always be in the same direction (i.e., both read or both write). When the data bus directionalities are tied in this manner, the data buffer devices of the module may interleave / deinterleave (i.e., time-multiplex) data for communication with a host between the two pseudo-channel data busses. This interleaving / deinterleaving allows independent bus directionality between ranks of the memory module.

[0012] In an embodiment, the data bus directionality of each of the two pseudo-channels are independent of the directionality of the other pseudo-channel (i.e., either can read or writewithout regard to the data bus directionality of the other). When the data bus directionalities are independent in this manner, the data buffer devices may interleave / deinterleave data for communication with a host within each of the two pseudo-channel data busses. This interleaving / deinterleaving allows independent bus directionality between pseudo-channels of the memory module.

[0013] In an embodiment, the memory devices on the memory module may be implemented with two independent memory channels. In other words, the memory devices on the memory module may have two separate command / address interfaces - one for each channel.

[0014] The descriptions and embodiments disclosed herein are made primarily with references to DRAM devices and DRAM memory arrays. This, however, should be understood to be a first example due at least to the widespread adoption of DRAM technology. It should be understood that other memory technologies may also benefit from the methods and / or apparatus described herein. These memory technologies include, but are not limited to static random access memory (SRAM), non-volatile memory (such as flash), conductive bridging random access memory (CBRAM — a.k.a., programmable metallization cell — PMC), resistive random access memory (a.k.a., RRAM or ReRAM), magnetoresistive random-access memory (MRAM), Spin-Torque Transfer (STT-MRAM), phase change memory (PCM), and the like, and / or combinations thereof. Accordingly, it should be understood that in the disclosures and / or descriptions given herein, these aforementioned technologies may be substituted for, included with, and / or encompassed within, the references to DRAM, DRAM devices, and / or DRAM arrays made herein.

[0015] Figures 1 A-1C are block diagrams illustrating a memory system. In Figures 1 A- 1C, memory system 100 comprises memory devices HOa-l lOb, controller 120, and interleaving / deinterleaving 130. Interleaving / deinterleaving 130 may include, or be, one or more data buffer devices. Interleaving / deinterleaving 130 includes mode circuitry 139. Memory devices 110a- 110b respectively include pseudo-channel A data (DQ) interface 11 laa-11 Iba, pseudo-channel B DQ interface 11 lab-11 Ibb, and synchronization signal (e.g., data strobes, write clocks) interface 113a- 113b. Memory device 110a also includes memory arrays 112aa-112ab. Memory device 110b includes memory arrays 112ba-112bb. Controller 120 includes channel data (DQ) interface 121, synchronization signal interface 123, and mode circuitry 129.

[0016] Controller 120, memory devices HOa-l lOb, and interleaving / deinterleaving 130 may be one or more integrated circuit type devices, such as are commonly referred to as“chips”. A memory controller, such as controller 120, manages the flow of data going to and from memory devices and / or memory modules. Memory devices 110a- 110b may be standalone devices, or may be a component of a memory module such as a DIMM module used in servers. In an embodiment, memory devices 110a- 110b may be a device that adheres to, or is compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory devices 110a- 110b may be, or comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 120 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect. In addition, memory controller functionality may be disposed on a separate Input / Output (I / O) die along with the transmitter / receiver circuits that interface to the memory device. Such an I / O die may include other types of I / O interfaces, as well as one or more chiplet interfaces that communicate with one or more respective CPU chiplet dies. The I / O die and CPU chiplet dies may be copackaged together and coupled to one-another via a silicon interposer.

[0017] In an embodiment, mode circuitry 139 may be or include a configuration register. In an embodiment, mode circuitry 139 may be configured by controller 120. In an embodiment, mode circuitry 139 may be configured by a control signal received by interleaving / deinterleaving 130. In an embodiment, the control signal received by interleaving / deinterleaving 130 to configure mode circuitry 139 may be provided by, and / or generated by, a memory module that interleaving / deinterleaving 130 is disposed upon.

[0018] In an embodiment, memory devices 110a-l 10b are disposed on a substrate having local interfaces (not shown in Figure 1), controller side synchronization signals 144, memory device side synchronization signals 147a-147b, memory device side data signals 145aa- 145bb, and controller side data signals 143 interconnected to form a memory module. Controller side data signals 143 may comprise time-multiplexed data signals. Data signals 143 operatively couple channel DQ interface 121 with interleaving / deinterleaving 130. Data signals 145aa operatively couple interleaving / deinterleaving 130 with pseudo-channel A DQ interface 11 laa of memory device 110a. Data signals 145ab operatively couple interleaving / deinterleaving 130 with pseudo-channel B DQ interface 11 lab of memory device 110a. Data signals 145ba operatively couple interleaving / deinterleaving 130 with pseudo-channel A DQ interface 11 Iba of memory device 110b. Data signals 145bboperatively couple interleaving / deinterleaving 130 with pseudo-channel B DQ interface 11 Ibb of memory device 110b.

[0019] Accordingly, controller 120 is operatively coupled to pseudo-channel A DQ interface 11 laa of memory device 110a via channel DQ interface 121, data signals 143, interleaving / deinterleaving 130, and data signals 145aa. Controller 120 is operatively coupled to pseudo-channel B DQ interface 11 lab of memory device 110a via channel DQ interface 121, data signals 143, interleaving / deinterleaving 130, and data signals 145ab. Controller 120 is operatively coupled to pseudo-channel A DQ interface 11 Iba of memory device 110b via channel DQ interface 121, data signals 143, interleaving / deinterleaving 130, and data signals 145ba. Controller 120 is operatively coupled to pseudo-channel B DQ interface 11 Ibb of memory device 110b via channel DQ interface 121, data signals 143, interleaving / deinterleaving 130, and data signals 145bb. Controller 120 is operatively coupled to synchronization signal interface (e.g., data strobe - DQS) 113a of memory device 110a via synchronization signal interface 123, synchronization signals 144, interleaving / deinterleaving 130, and synchronization signals 147a. Controller 120 is operatively coupled to synchronization signal interface (e.g., data strobe - DQS) 113b of memory device 110b via synchronization signal interface 123, synchronization signals 144, interleaving / deinterleaving 130, and synchronization signals 147b.

[0020] Controller 120 is operatively coupled to pseudo-channel A DQ interface 11 Iba of memory device 110b via channel DQ interface 121, data signals 143, interleaving / deinterleaving 130, and data signals 145ba. Controller 120 is operatively coupled to pseudo-channel B DQ interface 11 Ibb of memory device 110b via channel DQ interface 121, data signals 143, interleaving / deinterleaving 130, and data signals 145bb. Controller 120 is operatively coupled to synchronization signal interface 113b of memory device 110b via synchronization signal interface 123, synchronization signals 144, interleaving / deinterleaving 130, and synchronization signals 147b. In an embodiment, interleaving / deinterleaving 130 operates such that data signals 145aa-145bb communicate at a first data rate (e.g., double data rate - DDR) and data signals 143 communicate at a second data rate that is a positive integer multiple of the first data rate (e.g., 2x of DDR, a.k.a., quad data rate - QDR).

[0021] In an embodiment, each of pseudo-channel DQ interfaces A-B of memory devices 110a- 110b operate data transfer functions of their respective data channel interfaces 11 laa- 11 Ibb independently of the other channel A-B and channel interfaces 11 laa-11 Ibb. In an embodiment, each of pseudo-channel DQ interfaces A-B of memory devices 110a- 110b mustoperate their respective data transfer functions of their respective data channel interfaces 11 laa-11 Ibb in the same communication direction as the other channel A-B and channel interfaces 11 laa-11 Ibb. Each of pseudo-channels A-B access non-overlapping sets of memory arrays 112aa-l 12bb in their respective memory device 110a- 110b. In an embodiment, each of channel interfaces 11 laa-11 Ibb and 121a-121b include two (2) bidirectional data (DQ) signals and each synchronization signal interface 113a-l 13b include at least one data strobe (DQS) signal.

[0022] Memory devices 110a- 110b each include a command address (CA) bus interface that operates to access non-overlapping sets of memory arrays 112aa-l 12bb in their respective memory device 110a- 110b. In other words, memory arrays 112aa communicate data via pseudo-channel A DQ interface 11 laa (and not via pseudo-channel B DQ interface 11 lab); memory arrays 112ab communicate data via pseudo-channel B DQ interface 11 lab (and not via pseudo-channel A DQ interface 11 laa); Memory arrays 112ba communicate data via pseudo-channel A DQ interface 11 Iba (and not via pseudo-channel B DQ interface 11 Ibb); and memory arrays 112bb communicate data via pseudo-channel B DQ interface 11 Ibb (and not via pseudo-channel A DQ interface 11 Iba).

[0023] In an embodiment, memory devices 110a- 110b are representative of a larger number of memory devices 110a-l 10b on a memory module. For example, memory devices 110a- 110b may be representative of ten (10) dual data channel memory devices 110a- 110b with two data bits per channel on a memory module. In this example, therefore, channel DQ interface 121 of controller 120 and interleaving / deinterleaving 130 may be configured to form at least: (a) two (e.g., A and B) twenty (20) data bit pseudo-channels (along with accompanying CA signals) that are accessed as different ranks of a channel, and four (e.g., A0, Al, B0, Bl) ten (10) bit pseudo channel and rank combinations (along with accompanying CA signals) that are accessed independently of the communication directions of the other pseudo channel and rank combinations.

[0024] Controller 120 may also include additional channels coupled to additional memory devices 110a-l 10b on the same module. For example, controller 120 may include additional channel interfaces that couple to another ten (10) dual data channel memory devices thereby forming an additional two (or four) pseudo-channels (along with accompanying CA signals).

[0025] Figure IB illustrates memory system 100 with an example configuration for memory devices 110a- 110b with respective pseudo-channel DQ interfaces 11 laa-11 lab and pseudo-channel DQ interfaces 11 lba-11 Ibb operating with the same bus directionality. Inother words, in this configuration (e.g., set by mode circuitry 139 and / or mode circuitry 129), both pseudo-channel DQ interfaces 11 laa-11 lab 11 lba-11 Ibb of a respective memory device 110a- 110b are to be communicating in the read direction or both communicating in the write direction at the same time. Also in Figure IB, in order to more clearly show the functioning of interleaving / deinterleaving 130, data signals 145aa are illustrated as example data signals MDQaa[0: l], data signals 145ab are illustrated as example data signals MDQab[0: l], data signals 145ba are illustrated as example data signals MDQba[0: l], data signals 145bb are illustrated as example data signals MDQbb[0: l], and data signals 143 are illustrated as example data signals DQa[0: l] and DQb[0: l].

[0026] In Figure IB, channel DQ interface 121 of controller 120 is configured (grouped) into rank A DQ interface 121a and rank B DQ interface 121b. Rank A DQ interface 121a communicates data with interleaving / deinterleaving 130 via data signals DQa[0: 1], Rank B DQ interface 121b communicates data with interleaving / deinterleaving 130 via data signals DQb[0:l].

[0027] Interleaving / deinterleaving 130 is configured (e.g., by mode circuitry 139) to interleave / deinterleave MDQaa[0] and MDQab[0] for communication with rank A DQ interface 121a via DQa[0]. Interleaving / deinterleaving 130 is configured to interleave / deinterleave MDQaa[l] and MDQab[l ] for communication with rank A DQ interface 121a via DQa[l], Interleaving / deinterleaving 130 is configured to interleave / deinterleave MDQba[0] and MDQbb[0] for communication with rank B DQ interface 121b via DQb[0]. Interleaving / deinterleaving 130 is configured to interleave / deinterleave MDQbafl] and MDQbb[l ] for communication with rank B DQ interface 121b via DQb[l],

[0028] Thus, it should be understood that the configuration illustrated in Figure IB interleaves / deinterleaves data signals (e.g., MDQaa[0] and MDQab[0]) to / from (i.e., between, or among) different data pseudo-channels (e.g., pseudo-channel A DQ interface 11 laa and pseudo-channel B DQ interface 11 lab, respectively) of the same memory device (e.g., memory device 110a) for communication with controller 120 (e.g., via DQa[0] and rank A DQ interface 121a). It should also be understood that, in some embodiments, the data to / from the various data pseudo-channels of the memory devices 110a- 110b are communicated at one-half the data rate (e.g., DDR) that data is communicated to / from controller 120 (e.g., QDR). These different data rates may be correspondingly reflected in the timings (e.g., frequency) of synchronization signals 147a-147b and synchronization signals 144.

[0029] In an embodiment, (not illustrated in Figures 1 A-1C) data pseudo-channel A DQ interface 11 laa (and associated memory arrays 112aa) and data pseudo-channel B DQ interface 11 lab (and associated memory arrays 112ab) may be on physically separate devices. For example, data pseudo-channel A DQ interface 11 laa (and associated memory arrays 112aa) and data pseudo-channel B DQ interface 11 lab (and associated memory arrays 112ab) may be on separate DRAM dies that are either co-packaged together (e.g., stacked dies) or in separate DRAM packages. Likewise, data pseudo-channel A DQ interface 11 Iba (and associated memory arrays 112ba) and data pseudo-channel B DQ interface 11 Ibb (and associated memory arrays 112bb) may be on physically separate devices. For example, data pseudo-channel A DQ interface 11 Iba (and associated memory arrays 112ba) and data pseudo-channel B DQ interface 11 Ibb (and associated memory arrays 112bb) may be on separate DRAM dies that are either co-packaged together or in separate DRAM packages.

[0030] In an embodiment, (not illustrated in Figures 1 A-1C), data pseudo-channel A DQ interface 11 laa (and associated memory arrays 112aa) and data pseudo-channel B DQ interface 11 lab (and associated memory arrays 112ab) may be on physically separate devices that are also packaged separately. For example, data pseudo-channel A DQ interface 11 laa (and associated memory arrays 112aa) and data pseudo-channel B DQ interface 11 lab (and associated memory arrays 112ab) may be on separate DRAM dies that are part of the same rank but are packaged in different packages. Likewise, data pseudo-channel A DQ interface 11 Iba (and associated memory arrays 112ba) and data pseudo-channel B DQ interface 11 Ibb (and associated memory arrays 112bb) may be on physically separate devices that are also packaged separately. For example, data pseudo-channel A DQ interface 11 Iba (and associated memory arrays 112ba) and data pseudo-channel B DQ interface 11 Ibb (and associated memory arrays 112bb) may be on separate DRAM dies that are part of the same rank but are packaged in different packages.

[0031] Figure 1C illustrates memory system 100 with an example configuration for memory devices 110a- 110b with respective pseudo-channel DQ interfaces 11 laa-11 lab and pseudo-channel DQ interfaces 11 lba-11 Ibb operating with independent bus directionality. In other words, in this configuration (e.g., set by mode circuitry 139 and / or mode circuitry 129), both pseudo-channel DQ interfaces 11 laa-11 lab 11 lba-11 Ibb of a respective memory device 110a- 110b may be communicating in the read direction or in the write direction at the same time without regard to the communication direction of the other of pseudo-channel DQ interfaces 11 laa-11 lab 11 lba-11 Ibb of the same memory device 110a-l 10b. Also in Figure 1C, in order to more clearly show the functioning of interleaving / deinterleaving 130, datasignals 145aa are illustrated as example data signals MDQaa[O: l], data signals 145ab are illustrated as example data signals MDQab[O: l], data signals 145ba are illustrated as example data signals MDQba[O:l], data signals 145bb are illustrated as example data signals MDQbb[O: l], and data signals 143 are illustrated as example data signals DQaafO], DQabfO], DQbafO], and DQbbfO],

[0032] In Figure 1C, channel DQ interface 121 of controller 120 is configured (grouped) into rank A pseudo-channel A DQ interface 121aa, rank A pseudo-channel B DQ interface 121ab, rank B pseudo-channel A DQ interface 121ba, and rank B pseudo-channel B DQ interface 12 Ibb . Rank A pseudo-channel A DQ interface 121aa communicates data with interleaving / deinterleaving 130 via data signal DQaafO], Rank A pseudo-channel B DQ interface 121ab communicates data with interleaving / deinterleaving 130 via data signal DQabfO], Rank B pseudo-channel A DQ interface 121ba communicates data with interleaving / deinterleaving 130 via data signal DQbafO], Rank B pseudo-channel B DQ interface 12 Ibb communicates data with interleaving / deinterleaving 130 via data signal DQbbfO],

[0033] Interleaving / deinterleaving 130 is configured (e.g., by mode circuitry 139) to interleave / deinterleave MDQaafO] and MDQaafl] for communication with rank A pseudochannel A DQ interface 121aa via DQaafO], Interleaving / deinterleaving 130 is configured to interleave / deinterleave MDQabfO] and MDQabfl] for communication with rank A pseudochannel B DQ interface 121ab via DQabfO], Interleaving / deinterleaving 130 is configured to interleave / deinterleave MDQbafO] and MDQbafl] for communication rank B pseudo-channel A DQ interface 121ba via DQbafO], Interleaving / deinterleaving 130 is configured to interleave / deinterleave MDQbbfO] and MDQbbfl] for communication with Rank B pseudochannel B DQ interface 12 Ibb via DQbbfO],

[0034] Thus, it should be understood that the configuration illustrated in Figure 1C interleaves / deinterleaves data signals (e.g., MDQaafO] and MDQaafl]) to / from (i.e., between, or among) the same data pseudo-channels (e.g., pseudo-channel A DQ interface 11 laa) of the same memory device (e.g., memory device 110a) for communication with controller 120 (e.g., via DQaafO] and rank A pseudo-channel A DQ interface 121aa). It should also be understood that, in some embodiments, the data to / from the various data pseudo-channels of the memory devices 110a-l 10b are communicated at one-half the data rate (e.g., DDR) that data is communicated to / from controller 120 (e.g., QDR). These different data rates may be correspondingly reflected in the timings (e.g., frequency) of synchronization signals 147a- 147b and synchronization signals 144.

[0035] Figure 2 is a block diagram illustrating a memory module with independent rank access. In Figure 2, module 200 comprises rank A dual data channel DRAM devices 210a- 210e (representing five DRAM device packages A0-A4), rank B dual channel DRAM devices 21 Of-21 Oj (representing five DRAM device packages B0-B4), rank A multiplexing (interleaving / deinterleaving) data buffer device (MDB) 230a, rank B multiplexing data buffer device(s) (MDB) 230b, multiplexing registering clock driver (MRCD) 235, pseudo-channel A0 / A1 DQ interface 245a, and pseudo-channel B0 / B1 DQ interface 245b. MRCD 235 receives certain signals (e.g., command / address, clock, chip select) that are common to the pseudo-channel DQ interfaces 245a-245b.

[0036] Each dual data channel DRAM device 210a-210j includes two non-overlapping set of memory arrays that respectively communicate via two pseudo-channel DQ interfaces 21 laa-21 Ijb that, with the exception of communication direction, operate independently of each other. In other words, with the exception of communication direction of their two pseudo-channel DQ interfaces 21 laa-21 Ijb, which are operated in the same communication direction, each DRAM device 210a-210j device operates the command, address, and access functions of their respective nonoverlapping sets of memory arrays independently of the other set of memory arrays on the same DRAM device 210a-210j. Thus, for example, pseudochannel A DQ interface 21 laa of DRAM device 210a communicates with a first set of memory arrays in DRAM device 210a and pseudo-channel B interface 21 lab of DRAM device 210a accesses a second set of memory arrays in DRAM device 210a, where the first set of memory arrays and the second set of memory array do not have any common memory array (i.e., are non-overlapping sets).

[0037] At least the CA signals with commands and addresses for module 200 are operatively coupled to MRCD 235. MRCD 235 operatively couples the CA signals for accesses to be communicated via pseudo-channel A0 / A1 DQ interface 245a to the rank A DRAM devices 210a-210e. Similarly, MRCD 235 operatively couples the CA signals for accesses to be communicated via pseudo-channel B0 / B 1 DQ interface 245b to the rank B DRAM devices 21 Of-2 lOj . In Figure 2, the CA signals to be communicated via pseudochannel A0 / A1 DQ interface 245a are illustrated being coupled to DRAM device 210a via CA-A1 signals from MRCD 235, being coupled to DRAM devices 21 Ob-210c via CA-A2 signals from MRCD 235, and being coupled to DRAM devices 210d-210e via CA-A3 signals from MRCD 235. Similarly, in Figure 2, the CA signals to be communicated via pseudochannel B0 / B1 DQ interface 245b are illustrated being coupled to DRAM device 210f via CA-B1 signals from MRCD 235, being coupled to DRAM devices 210g-210h via CA-B2signals from MRCD 235, and being coupled to DRAM devices 21 Oi-21 Oj via CA-B3 signals from MRCD 235.

[0038] The pseudo-channel A DQ interface 21 laa of DRAM device 210a is operatively coupled to communicate N data signals with the memory side pseudo-channel A DQ interface 232aa of data buffer device 230a. The pseudo-channel B interface 21 lab of DRAM device 210a is also operatively coupled to communicate N data signals with memory side pseudo-channel A DQ interface 232aa of data buffer device 230a. Data buffer device 230a interleaves / deinterleaves the N data signals communicated with pseudo-channel A DQ interface 21 laa via memory side pseudo-channel A DQ interface 232aa with the N data signals communicated with pseudo-channel B interface 21 lab memory side pseudo-channel A DQ interface 232aa (a total of N*2 data signals) for communication via pseudo channel A0 / A1 DQ interface 245a using N signals (see Figure IB for an example, with N=2, of this type of interleaving / deinterleaving between different pseudo-channel interfaces of the same device for communication with a host).

[0039] The pseudo-channel A DQ interface 21 Iba of DRAM device 210b is operatively coupled to communicate N bits of data with the memory side pseudo-channel A DQ interface 232ab of data buffer device 230a. The channel B interface 21 Ibb of DRAM device 210b is also operatively coupled to communicate N bits of data with memory side pseudo-channel A DQ interface 232ab of data buffer device 230a. Data buffer device 230a interleaves / deinterleaves the N data signals communicated with pseudo-channel A DQ interface 21 Iba via memory side pseudo-channel A DQ interface 232ab with the N data signals communicated with pseudo-channel B interface 21 Ibb memory side pseudo-channel A DQ interface 232ab (a total of N*2 data signals) for communication via pseudo-channel A0 / A1 DQ interface 245a using N signals.

[0040] The pseudo-channel A DQ interface 21 lea of DRAM device 210c is operatively coupled to communicate N bits of data with the memory side pseudo-channel A DQ interface 232ac of data buffer device 230a. The channel B interface 21 leb of DRAM device 210c is also operatively coupled to communicate N bits of data with memory side pseudo-channel A DQ interface 232ac of data buffer device 230a. A like pattern of connections is followed for all of the DRAM devices 210a-210j and data buffer devices 230a-230b on module 200 (which, for the sake of brevity will not be further detailed herein). Similarly, data buffer device 230a interleaves / deinterleaves the N data signals communicated with pseudo-channel A DQ interface 21 lea via memory side pseudo-channel A DQ interface 232ac with the N data signals communicated with pseudo-channel B interface 21 leb memory side pseudochannel A DQ interface 232ac (a total of N*2 data signals) for communication via pseudochannel A0 / A1 DQ interface 245a using N signals. A like pattern of connection and interleaving / deinterleaving of signals by data buffer devices 230a-230b is followed for all of the DRAM devices 210a-210j and data buffer devices 230a-230b on module 200 (which, for the sake of brevity will not be further detailed herein).

[0041] Controller side interleaved pseudo-channel A0 / A1 DQ interfaces 231aa-231ab are operatively coupled to pseudo-channel A0 / A1 DQ interface 245a. Similarly, controller side interleaved pseudo-channel B0 / B1 DQ interfaces 231ba-231bb are operatively coupled pseudo-channel B0 / B1 DQ interface 245b. In Figure 2, each of controller side interleaved pseudo-channel A0 / A1 DQ interface 231aa and controller side interleaved pseudo-channel A0 / A1 DQ interface 23 lab are operated together with each communicating one-half of the signals communicated with pseudo-channel A0 / A1 DQ interface 245a. Similarly, each of controller side interleaved pseudo-channel B0 / B1 DQ interface 231ba and controller side interleaved pseudo-channel B0 / B1 DQ interface 231bb are operated together with each communicating one-half of the signals communicated with pseudo-channel B0 / B1 DQ interface 245b.

[0042] Collectively, controller side interleaved pseudo-channel A0 / A1 DQ interfaces 231aa-231ab communicate with pseudo-channel A0 / A1 DQ interface 245a using 5*N signals. Collectively, controller side interleaved pseudo-channel B0 / B1 DQ interfaces 231ba- 231bb communicate with pseudo-channel B0 / B1 DQ interface 245b using 5*N signals. The 5*N signals communicated via each of pseudo channel A0 / A1 DQ interface 245a and pseudo channel B0 / B1 DQ interface 245b comprise N signals communicated with each of two (2) pseudo-channel DQ interfaces (i.e., N*2 signals per package 210a-210e) of each of five (5) DRAM packages (i.e., N*2 signals per package 210a-210e times five packages is N*2*5) for a total of N* 10 number of signals that are time-multiplexed and demultiplexed (i.e., interleaved and deinterleaved) by a respective MDB 230a-230b down to [N*2x5] / 2=5><N number of signals communicated via a respective pseudo-channel DQ interface 245a-245b. Thus, for example, for N=2, (e.g., as illustrated by Figure IB), twenty (20) data signals are communicated with memory side pseudo-channel A DQ interfaces 232aa-232ae of data buffer device 230a at a first data rate and ten (10) data signals are communicated via pseudochannel A0 / A1 DQ interface 245a at double the first data rate. Similarly, for N=2, twenty (20) data signals are communicated with memory side pseudo-channel B DQ interfaces 232bf-232bj of data buffer device 230b at the first data rate and ten (10) data signals are communicated via pseudo-channel B0 / B 1 DQ interface 245b at double the first data rate.

[0043] In an embodiment, N=4. For example, each of packages 210a-210e may include two memory devices (e.g., two of memory device 110a) each communicating two data signals (e.g., MDQaa[0: l] and MDQab[0: l]) for each of two pseudo-channel data interfaces (e.g., pseudo-channel A data interface 11 laa and pseudo-channel A data interface 11 lab, respectively). Thus, the two memory devices in each of packages 210a-210e communicate a total of N*2=8 signals (i.e., two memory devices times two pseudo-channels times two signals per pseudo channel is 2*2><2=8 signals per package 210a-210e). Since there are five (5) packages 210a-210e, forty (8x5=40) signals are communicated with MDB 230a by packages 210a-210e for interleaving / deinterleaving by MDB 230a. The forty signals interleaved / deinterleaved by MDB 230a using a 2: 1 interleaving / deinterleaving ratio result in 20 (5x8 / 2=40 / 2=20) signals communicated via pseudo-channel A0 / A1 DQ interface 245a. Similarly, for N=4, 20 twenty (20) signals are communicated via pseudo-channel B0 / B1 DQ interface 245b.

[0044] Figure 3 is a block diagram illustrating a memory module with independent rank and pseudo-channel access. In Figure 3, module 300 comprises rank A dual data channel DRAM devices 310a-3 lOe (representing five DRAM device packages A0-A4), rank B dual channel DRAM devices 310f-3 lOj (representing five DRAM device packages B0-B4), rank A multiplexing buffer device (MDB) 330a, rank B multiplexing data buffer device(s) (MDB) 330b, multiplexing registering clock driver (MRCD) 335, pseudo-channel A0 DQ interface 345a0, pseudo-channel Al DQ interface 345al, pseudo-channel B0 DQ interface 345b0, and pseudo-channel Bl DQ interface 345bl. MRCD 335 receives certain signals (e.g., command / address, clock, chip select) that are common to the pseudo-channel DQ interfaces 345al-345bl.

[0045] Each dual data channel DRAM device 310a-3 IQj includes two non-overlapping set of memory arrays that respectively communicate via two pseudo-channel DQ interfaces 31 laa-31 Ijb that operate independently of each other. In other words, each DRAM device 310a-3 IQj device operates the command, address, access, and data transfer functions of their respective nonoverlapping sets of memory arrays independently of the other set of memory arrays on the same DRAM device 310a-3 lOj . Thus, for example, pseudo-channel A DQ interface 31 laa of DRAM device 310a accesses and communicates with a first set of memory arrays in DRAM device 310a, and pseudo-channel B DQ interface 31 lab of DRAM device 310a accesses and communicates with a second set of memory arrays in DRAM device 310a independently of the accesses and communication of via the other interface 31 laa-31 lab,where the first set of memory arrays and the second set of memory array do not have any common memory array (i.e., are non-overlapping sets).

[0046] At least the CA signals with commands and addresses for module 300 are operatively coupled to MRCD 335. MRCD 335 operatively couples the CA signals for accesses to be communicated via pseudo-channel AO DQ interface 345a0 and pseudo-channel Al DQ interface 345al to the rank A DRAM devices 310a-3 lOe. Similarly, MRCD 335 operatively couples the CA signals for accesses to be communicated via pseudo-channel BO DQ interface 345b0 and pseudo-channel Bl DQ interface 345b 1 to the rank B DRAM devices 310f-3 lOj . In Figure 3, the CA signals to be communicated via pseudo-channel A0 / A1 DQ interfaces 345a0-345al are illustrated being coupled to DRAM device 310a via CA-A1 signals from MRCD 335, being coupled to DRAM devices 310b-310c via CA-A2 signals from MRCD 335, and being coupled to DRAM devices 310d-3 lOe via CA-A3 signals from MRCD 335. Similarly, in Figure 3, the CA signals to be communicated via pseudochannel channel B0 / B1 DQ interfaces 345b0-345bl are illustrated being coupled to DRAM device 3 lOf via CA-B1 signals from MRCD 335, being coupled to DRAM devices 310g- 3 lOh via CA-B2 signals from MRCD 335, and being coupled to DRAM devices 310i-3 lOj via CA-B3 signals from MRCD 335.

[0047] The pseudo-channel A DQ interface 31 laa of DRAM device 310a is operatively coupled to communicate N data signals with the memory side pseudo-channel A DQ interface 332aa of data buffer device 330a. Data buffer device 330a interleaves / deinterleaves the N data signals communicated with pseudo-channel A DQ interface 31 laa via memory side pseudo-channel A DQ interface 332aa among the N data signals communicated with pseudo-channel A DQ interface 31 laa via memory side pseudo-channel A DQ interface 332aa (a total of N data signals) for communication via pseudo-channel A0 DQ interface 345a0 using N / 2 signals (see Figure 1C for an example, with N=2, of this type of interleaving / deinterleaving among signals of the same pseudo-channel interface of the same device for communication with a host).

[0048] The pseudo-channel B DQ interface 31 lab of DRAM device 310a is also operatively coupled to communicate N data signals with memory side pseudo-channel A DQ interface 332aa of data buffer device 330a. Data buffer device 330a interleaves / deinterleaves the N data signals communicated with pseudo-channel A DQ interface 31 laa via memory side pseudo-channel A DQ interface 332aa among the N data signals communicated with pseudo-channel A DQ interface 31 laa via memory side pseudochannel A DQ interface 332aa (a total of N data signals) for communication via pseudo-channel Al DQ interface 345al using N / 2 signals (again, see Figure 1C for an example, with N=2, of this type of interleaving / deinterleaving among signals of the same pseudo-channel interface of the same device for communication with a host).

[0049] The pseudo-channel A DQ interface 31 Iba of DRAM device 310b is operatively coupled to communicate N bits of data with the memory side pseudo-channel A DQ interface 332ab of data buffer device 330a. Data buffer device 330a interleaves / deinterleaves the N data signals communicated with pseudo-channel A DQ interface 31 Iba via memory side pseudo-channel A DQ interface 332ab among the N data signals communicated with pseudochannel A DQ interface 31 Iba via memory side pseudo-channel A DQ interface 332aa (a total of N data signals) for communication via pseudo-channel A0 DQ interface 345a0 using N / 2 signals.

[0050] The pseudo-channel B DQ interface 31 Ibb of DRAM device 310b is also operatively coupled to communicate N bits of data with memory side pseudo-channel A DQ interface 332ab of data buffer device 330a. Data buffer device 330a interleaves / deinterleaves the N data signals communicated with pseudo-channel B DQ interface 31 Ibb via memory side pseudo-channel A DQ interface 332ab among the N data signals communicated with pseudo-channel B DQ interface 31 Ibb via memory side pseudo-channel A DQ interface 332ab (a total of N data signals) for communication via pseudo-channel Al DQ interface 345al using N / 2 signals.

[0051] The pseudo-channel A DQ interface 31 lea of DRAM device 310c is operatively coupled to communicate N bits of data with the memory side pseudo-channel A DQ interface 332ac of data buffer device 330a. The pseudo-channel B interface 31 leb of DRAM device 310c is also operatively coupled to communicate N bits of data with memory side pseudochannel A DQ interface 332ac of data buffer device 330a. A like pattern of connections is followed for all of the DRAM devices 310a-3 lOj and data buffer devices 330a-330b on module 300 (which, for the sake of brevity will not be further detailed herein). Similarly, data buffer device 330a interleaves / deinterleaves among the N data signals communicated with pseudo-channel A DQ interface 31 lea via memory side pseudo-channel A DQ interface 332ac for communication via pseudo-channel A0 DQ interface 345a0 using N / 2 signals, and interleaves / deinterleaves among the N data signals communicated with pseudo-channel B interface 31 leb memory side pseudo-channel A DQ interface 332ab for communication via pseudo-channel Al DQ interface 345al using N / 2 signals. A like pattern of connection and interleaving / deinterleaving of signals by data buffer devices 330a-330b is followed for all ofthe DRAM devices 310a-3 lOj and data buffer devices 330a-330b on module 300 (which, for the sake of brevity will not be further detailed herein).

[0052] Controller side interleaved pseudo-channel AO DQ interface 331aa is operatively coupled to pseudo-channel AO DQ interface 345a0. Controller side interleaved pseudochannel Al DQ interface 33 lab is operatively coupled to pseudo-channel Al DQ interface 345al . Controller side interleaved pseudo-channel BO DQ interface 33 Iba is operatively coupled to pseudo-channel BO DQ interface 345b0. Controller side interleaved pseudochannel Bl DQ interface 33 Ibb is operatively coupled to pseudo-channel Bl DQ interface 345bl.

[0053] Controller side interleaved pseudo-channel A0 DQ interface 331aa communicates with pseudo channel A0 DQ interface 345a0. Controller side interleaved pseudo-channel Al DQ interface 33 lab communicates with pseudo channel Al DQ interface 345al. Controller side interleaved pseudo-channel B0 DQ interface 33 Iba communicates with pseudo channel B0 DQ interface 345b0. Controller side interleaved pseudo-channel Bl DQ interface 33 Ibb communicates with pseudo channel Bl DQ interface 345b 1. Pseudo-channel A0 / A1 DQ interfaces 345a0-345al and pseudo channel B0 / B1 DQ interfaces 345b0-345bl each communicate using 5x(N / 2) signals. The 5x(N / 2) signals communicated via pseudo channel A0 DQ interface 345a0 comprises N data signals communicated with a single pseudo-channel DQ interface 31 laa-3 I lea (i.e., N signals per package 310a-3 lOe) of each of five (5) DRAM packages 310a-3 lOe for a total of Nx5 number of signals that are time-multiplexed and demultiplexed (i.e., interleaved and deinterleaved) by MDB 330a down to 5xN / 2 number of signals communicated via pseudo-channel DQ interface 345a0. The 5x(N / 2) signals communicated via pseudo channel Al DQ interface 345al comprises N data signals communicated with a single pseudo-channel DQ interface 31 lab-311 eb of each of five (5) DRAM packages 310a-3 lOe for a total of Nx5 number of signals that are time-multiplexed and demultiplexed (i.e., interleaved and deinterleaved) by MDB 330a down to 5xN / 2 number of signals communicated via pseudo-channel DQ interface 345al. The 5x(N / 2) signals communicated via pseudo channel B0 DQ interface 345b0 comprises N data signals communicated with a single pseudo-channel DQ interface 31 lfa-31 Ija of each of five (5) DRAM packages 310f-3 lOj for a total of Nx5 number of signals that are time-multiplexed and demultiplexed (i.e., interleaved and deinterleaved) by MDB 330b down to 5xN / 2 number of signals communicated via pseudo-channel DQ interface 345b0. The 5x(N / 2) signals communicated via pseudo channel Bl DQ interface 345b 1 comprises N data signals communicated with a single pseudo-channel DQ interface 31 lfb-31 Ijb of each of five (5)DRAM packages 310f-3 lOj for a total of N*5 number of signals that are time-multiplexed and demultiplexed (i.e., interleaved and deinterleaved) by MDB 330b down to 5*N / 2 number of signals communicated via pseudo-channel DQ interface 345b 1. In other words, each pseudo channel data DQ interface 33 laa-33 Ibb “bundle” of 5x(N / 2) signals corresponds to N signals of a single pseudo-channel DQ interface of each of five DRAM packages (i.e. each 5xN associated DRAM side interface signals are time-multiplexed down to 5xN / 2 associated signals on the host interface side).

[0054] Thus, for example, for N=2, (e.g., as illustrated by Figure 1C), twenty (20) data signals are communicated with memory side pseudo-channel A DQ interfaces 332aa-332ae of data buffer device 330a at a first data rate, five (5) data signals are communicated via pseudo-channel A0 DQ interface 345a0, and five (5) data signals are communicated via pseudo-channel Al DQ interface 345al at double the first data rate. Similarly, for N=2, twenty (20) data signals are communicated with memory side pseudo-channel B DQ interfaces 332bf-332bj of data buffer device 330b at the first data rate, five (5) data signals are communicated via pseudo-channel B0 DQ interface 345b0, and five (5) data signals are communicated via pseudo channel Bl DQ interface 34bal at double the first data rate.

[0055] In an embodiment, N=4. For example, each of packages 310a-3 lOe may include two memory devices (e.g., two of memory device 110a) each communicating two data signals (e.g., MDQaa[0: l] and MDQab[0: l]) for each of two pseudo-channel data interfaces (e.g., pseudo-channel A data interface 11 laa and pseudo-channel A data interface 11 laa, respectively). Thus, the two memory devices in each of packages 310a-3 lOe communicate a total of N*2=8 signals (i.e., two memory devices times two pseudo-channels times two signals per pseudo channel is 2*2><2=8 signals per package 310a-3 lOe). Since there are five (5) packages 310a-3 lOe, forty (8x5=40) signals are communicated with MDB 330a by packages 310a-3 lOe for interleaving / deinterleaving by MDB 330a. The forty signals are grouped by rank (e.g., rank A) and pseudo-channel (e.g., pseudo-channel A0 and pseudo channel Al) for interleaving / deinterleaving by MDB 330a using a 2: 1 interleaving / deinterleaving ratio resulting in ten (5x8 / 4=40 / 4=10) signals communicated via each pseudo-channel DQ interface 345a0-345al. Likewise, the signal counts of 10 signals via each pseudo-channel DQ interface 345b0-345bl apply for the interleaving / deinterleaving by MDB 330b.

[0056] Figures 4A-4B are timing diagrams illustrating an example interleaving of data across memory device pseudo-channels. In Figures 4A-4B, example communication via a data buffer device (e.g., interleaving / deinterleaving 130, MDB 230a-230b) configured tointerleave / deinterleave data signals from pseudo-channels of a dual channel memory device (e.g., memory devices 110a- 110b, memory devices 210a-210j) for communication with a controller (e.g., controller 120) is illustrated. In Figures 4A-4B, data transfers from the memory devices are timed by a first timing reference signal (e.g., clock) DCK. Data transfers to the controller / host are timed by a second timing reference signal QCK that is running at twice the rate of DCK. In Figures 4A-4B, signals MDQaafO: 1] and MDQabfO: 1] communicated between the buffer device and a memory device are illustrated. As also illustrated in Figure IB, data signals MDQaafO: 1] are communicated with a first (e.g., channel A) pseudo-channel DQ interface of the memory device (e.g., memory device 110a), and data signals MDQabfO: 1] are communicated with a second (e.g., channel B) pseudochannel DQ interface of the memory device.

[0057] In Figures 4A-4B, MDQaafO] carries a burst of data bits (e.g., 32-bit burst) timed by DCK and shown as bits aaOfO] to aa31[0]; MDQabfO] carries a burst of data bits (e.g., 32- bit burst) timed by DCK and shown as bits abOfO] to ab31 [0]; MDQaafl] carries a burst of data bits (e.g., 32-bit burst) timed by DCK and shown as bits aaOfl] to aa31[l]; and MDQabfl] carries a burst of data bits (e.g., 32-bit burst) timed by DCK and shown as bits abOfl] to ab31 [1],

[0058] The data buffer device interleaves the bits transferred via MDQaafO] (from the first pseudo-channel interface) with the bits transferred via MDQabfO] (from the second pseudo-channel interface) for communication with the controller via data signal DQafO] (and timed by QCK). This is illustrated by example in Figure 4B by aaOfO] on DQafO] being followed by abOfO] on DQafO] and arrow 401 running from aaOfO] on MDQaafO] to aaOfO] on DQafO] and arrow 402 running from abOfO] on MDQabfO] to abOfO] on DQafO],

[0059] Similarly, The data buffer device interleaves the bits transferred via MDQaafl] (from the first pseudo-channel interface) with the bits transferred via MDQabfl] (from the second pseudo-channel interface) for communication with the controller via data signal DQafl] (and timed by QCK). This is illustrated by example in Figure 4B by aaOfl] on DQafl] being followed by abOfl] on DQafl] and arrow 403 running from aaOfl] on MDQaafl] to aaOfO] on DQafl] and arrow 404 running from abOfl] on MDQabfl] to abOfl] on DQafl],

[0060] Figures 5A-5B are timing diagrams illustrating an example interleaving of data within a pseudo-channel. In Figures 5A-5B, example communication via a data buffer device (e.g., interleaving / deinterleaving 130, MDB 330a-330b) configured to interleave / deinterleave data signals from the same pseudo-channel of a dual channel memory device (e.g., memorydevices 110a-l 10b, memory devices 310a-3 lOj) for communication with a controller (e.g., controller 120) is illustrated. In Figures 5A-5B, data transfers from the memory devices are timed by a first timing reference signal (e.g., clock) DCK. Data transfers to the controller / host are timed by a second timing reference signal QCK that is running at twice the rate of DCK. In Figures 5A-5B, signals MDQaa[0: l] and MDQab[0: l] communicated between the buffer device and a memory device are illustrated. As also illustrated in Figure 1C, data signals MDQaa[0: l] are communicated with a first (e.g., channel A) pseudo-channel DQ interface of the memory device (e.g., memory device 110a), and data signals MDQab[0: l] are communicated with a second (e.g., channel B) pseudo-channel DQ interface of the memory device.

[0061] In Figures 5A-5B, MDQaafO] carries a burst of data bits (e.g., 32-bit burst) timed by DCK and shown as bits aa0[0] to aa31 [0]; MDQabfO] carries a burst of data bits (e.g., 32- bit burst) timed by DCK and shown as bits ab0[0] to ab31 [0]; MDQaafl] carries a burst of data bits (e.g., 32-bit burst) timed by DCK and shown as bits aaOfl] to aa31 [1]; and MDQabfl] carries a burst of data bits (e.g., 32-bit burst) timed by DCK and shown as bits abOfl] to ab31 [1],

[0062] The data buffer device interleaves the bits transferred via MDQaafO] (from the first pseudo-channel interface) with the bits transferred via MDQaafl] (also from the first pseudo-channel interface) for communication with the controller via data signal DQaafO] (and timed by QCK). This is illustrated by example in Figure 5B by aaOfO] on DQaafO] being followed by aaOfl] on DQaafO] and arrow 501 running from aaOfO] on MDQaafO] to aaOfO] on DQaafO] and arrow 502 running from aaOfl] on MDQaafl] to aaOfl] on DQaafO],

[0063] Similarly, the data buffer device interleaves the bits transferred via MDQabfO] (from the second pseudo-channel interface) with the bits transferred via MDQabfl] (also from the second pseudo-channel interface) for communication with the controller via data signal DQabfO] (and timed by QCK). This is illustrated by example in Figure 5B by abOfO] on DQabfO] being followed by abOfl] on DQabfO] and arrow 503 running from abOfO] on MDQabfo] to abOfO] on DQbafO] and arrow 504 running from abOfl] on MDQabfl] to abOfl] on DQabfO],

[0064] Figure 6 is a timing diagram illustrating two successive data buffer read commands. The sequence illustrated in Figure 6 begins with a first read command (RDaa with a timing offset of zero cycles) to transfer data from first pseudo-channel data interface of a memory device (e.g., pseudo-channel A DQ interface 31 laa) being communicated (e.g., to MDB 330a) via a buffer command bus (BCOMf]). The first read command is communicatedover a period of tbcom (e.g., ~3 CK cycles). Immediately succeeding the first read command, a second read command (RDab with a timing offset of minus 1 CK cycle) to transfer data from a second pseudo-channel data interface of the memory device (e.g., pseudo-channel B DQ interface 31 lab) is communicated via the BCOM[] bus (also over a period of tbcom). After a data buffer read latency period (tdbri) from when the RDaa command was communicated, a first read data burst (BURSTaa) is received from the first pseudo-channel data interface via the MDQaaf] data bus using a double data rate transfer interval. This data burst occurs over a burst length period of tBL (e.g., ~ 16 CK cycles). After the data buffer read latency period (tdbri) plus the negative timing offset of one cycle (i.e., toft=-l CK cycle) specified by the RDab command from when the RDab command was communicated, a second read data burst (BURSTab) is received from the second pseudo-channel data interface via the MDQabf] data bus using a double data rate transfer interval. This data burst also occurs over a burst length period of tBL (e.g., ~ 16 CK cycles). Thus, it should be understood from Figure 6 that because RDab was communicated three cycles later (i.e., 3 cycle delay) than RDaa, and RDab specified a minus one cycle timing offset (i.e., toft=-l CK cycle), the net offset between the data being communicated for the RDaa command on MDQaaf] and the data being communicated for RDab command on MDQabf] is tnofn= 2 CK cycles.

[0065] After a read propagation / processing / interleaving / synchronization delay tPRD from the start of BURSTaa on MDQaaf], a quad data rate burst of interleaved data from BURSTaa on MDQaaf] is communicated (transmitted) via controller side data bus DQaaf], This data burst occurs over a burst length period of tBL (e.g., ~ 16 CK cycles). Similarly, after a read propagation / processing / interleaving / synchronization delay tPRD from the start of BURSTab on MDQabf], a quad data rate burst of interleaved data from BURSTab on MDQab[]is communicated (transmitted) via controller side data bus DQabf], This data burst occurs over a burst length period of tBL (e.g., ~ 16 CK cycles).

[0066] Figure 7 is a timing diagram illustrating a data buffer read command and a data buffer write command in immediate succession. The sequence illustrated in Figure 7 begins with a read command (RDaa with a timing offset of zero cycles) to transfer data from first pseudo-channel data interface of a memory device (e.g., pseudo-channel A DQ interface 31 laa) being communicated (e.g., to MDB 330a) via a buffer command bus (BCOMf]). The read command is communicated over a period of tbcom (e.g., ~3 CK cycles). Immediately succeeding the read command, a write command (WRab with a timing offset of minus 2 CK cycles) to transfer data to a second pseudo-channel data interface of the memory device (e.g., pseudo-channel B DQ interface 31 lab) is communicated via the BCOM[] bus (also over aperiod of tbcom). After a data buffer read latency period (taw) from when the RDaa command was communicated, a first read data burst (BURSTaa) is received from the first pseudochannel data interface via the MDQaaf] data bus using a double data rate transfer interval. This data burst occurs over a burst length period of tBL (e.g., ~ 16 CK cycles).

[0067] After the data buffer write latency period (tdbwi), plus the negative timing offset of two cycles (i.e., toft=-2 CK cycles) specified by the WRab command from when the WRab command was communicated, a second write data burst (BURSTab) is transmitted to the second pseudo-channel data interface via the MDQabf] data bus using a double data rate transfer interval. This data burst also occurs over a burst length period of tBL (e.g., ~ 16 CK cycles). A write propagation / processing / deinterleaving / synchronization delay tPwR prior to the transmission of BURSTab via MDAabf], a quad data rate burst of the BURSTab write data starts to be communicated via DQab[] to the data buffer. This data burst occurs over a burst length period of tBL (e.g., ~ 16 CK cycles). After a read propagation / processing / interleaving / synchronization delay tPRD from the start of BURSTaa on MDQaaf], a quad data rate burst of interleaved data from BURSTaa on MDQaa[]is communicated (transmitted) via controller side data bus DQaaf], This data burst occurs over a burst length period of tBL (e.g., ~ 16 CK cycles).

[0068] Figure 6 and Figure 7 illustrate the operation of a system with a single buffer command bus (e.g., BCOM[]) that time multiplexes commands associated with pseudo channel A (e.g., MDQaaf], DQaaf]) and pseudo channel B (e.g., MDQabf], DQabf]). In an embodiment, however, instead of having separate commands for each pseudo channel, commands associated with separate pseudo channels may be combined into a merged command and associated with an indicator of which pseudo channel(s) is (are) active for the associated command. This embodiment results in timing alignment between the pseudo channels. In another embodiment, the data buffer devices may include two physical BCOMf] interfaces on the data buffer - one for each memory device pseudo channel. This embodiment allows for arbitrary timing alignment between the two pseudo channels such that handling of variable latencies (i.e. timing offsets) in the command protocol may be optional or not used at all.

[0069] Figure 8 is a flowchart illustrating a method of operating a data buffer device to interleave data across memory device pseudo-channels. The steps illustrated in Figure 8 may be performed by one or more elements of memory system 100, module 200, and / or module 300. A data buffer device is configured to communicate data between a memory component that includes a first pseudo-channel and a second pseudo-channel and a controller, where thedata communicated between the data buffer device and the controller is time-multiplexed interleaved among the first pseudo-channel and the second pseudo-channel (802). For example, interleaving / deinterleaving 130 may be configured to communicate data between memory device 110a and controller 120 by interleaving data communicated with pseudochannel A DQ interface I l la and data communicated with pseudo-channel B DQ interface 111b.

[0070] By the data buffer device, data transmitted by the first pseudo-channel and data transmitted by the second pseudo-channel are time-multiplexed for transmission to the controller (804). For example, interleaving / deinterleaving 130 may time-multiplex read data received, at a first data rate, from pseudo-channel A DQ interface I l la and data communicated with pseudo-channel B DQ interface 11 lb of memory device 110a and transmit the time-multiplexed data, at twice the first data rate, to controller 120. By the data buffer device, data transmitted by the controller as data to be stored in the rank is time- demultiplexed into data for transmission to the first pseudo-channel and data for transmission to the second pseudo-channel (806). For example, interleaving / deinterleaving 130 may timedemultiplex data received from controller 120 at twice the first data rate into data to be transmitted to pseudo-channel A DQ interface 11 la at the first data rate and data to be transmitted to pseudo-channel B DQ interface 11 lb at the first data rate.

[0071] Figure 9 is a flowchart illustrating a method of operating a data buffer device to interleave data within a pseudo-channel. The steps illustrated in Figure 9 may be performed by one or more elements of memory system 100, module 200, and / or module 300. A data buffer device is configured to communicate data between a memory component that includes a first pseudo-channel and a second pseudo-channel and a controller, where the data communicated between the data buffer device and the controller is time-multiplexed (interleaved) among a plurality of bits of the first pseudo-channel (902). For example, interleaving / deinterleaving 130 may be configured to communicate data between memory device 110a and controller 120 by interleaving a plurality of bits (e.g., two) communicated with pseudo-channel A DQ interface I l la.

[0072] By the data buffer device, among a plurality of bits from the first pseudo-channel that are concurrently received, time-multiplex the plurality of bits for transmission to the controller as data accessed from the first pseudo-channel of the memory component (904). For example, interleaving / deinterleaving 130 may time-multiplex a plurality of bits (e.g., 2) of read data received, at a first data rate, from pseudo-channel A DQ interface I l la and transmit the time-multiplexed data, at twice the first data rate, to controller 120 as dataaccessed from a first pseudo-channel (e.g., rank A pseudo-channel A). By the data buffer device, data transmitted by the controller as data to be stored by the first pseudo-channel is time-demultiplexed into the plurality of bits of the first pseudo-channel for transmission to the first pseudo-channel (906). For example, interleaving / deinterleaving 130 may timedemultiplex data received from controller 120 at twice the first data rate into data to be transmitted via pseudo-channel A DQ interface 11 la at the first data rate.

[0073] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of memory system 100, module 200, and / or module 300, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0074] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0075] Figure 10 is a block diagram illustrating one embodiment of a processing system 1000 for including, processing, or generating, a representation of a circuit component 1020. Processing system 1000 includes one or more processors 1002, a memory 1004, and one or more communications devices 1006. Processors 1002, memory 1004, and communications devices 1006 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1008.

[0076] Processors 1002 execute instructions of one or more processes 1012 stored in a memory 1004 to process and / or generate circuit component 1020 responsive to user inputs 1014 and parameters 1016. Processes 1012 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electroniccircuitry and / or generate photomasks for electronic circuitry. Representation 1020 includes data that describes all or portions of memory system 100, module 200, and / or module 300, and their components, as shown in the Figures.

[0077] Representation 1020 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1020 may be stored on storage media or communicated by carrier waves.

[0078] Data formats in which representation 1020 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

[0079] User inputs 1014 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interface devices. Parameters 1016 may include specifications and / or characteristics that are input to help define representation 1020. For example, parameters 1016 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0080] Memory 1004 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1012, user inputs 1014, parameters 1016, and circuit component 1020.

[0081] Communications devices 1006 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1000 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1006 may transmit circuit component 1020 to another system. Communications devices 1006 may receive processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 and cause processes 1012, user inputs 1014, parameters 1016, and / or circuit component 1020 to be stored in memory 1004.

[0082] Implementations discussed herein include, but are not limited to, the following examples:

[0083] Example 1: A memory module, comprising: a first plurality of dynamic random access memory (DRAM) devices each having a first memory access interface to operate to independently address concurrent accesses having the same data communication direction of one of a first set of memory cores and a second set of memory cores in respective ones of the first plurality of DRAM devices where the first set of memory cores and the second set of memory cores in each of the first plurality of DRAM devices are non-overlapping sets, the first plurality of DRAM devices each having a respective first data interface to communicate data for accesses of the first set of memory cores and a respective second data interface to communicate data for accesses of the second set of memory cores; and a first data buffer device having a first host side interface, a first device side interface, and a second device side interface, the first device side interface to communicate first data with each of the respective first data interfaces of the first plurality of DRAM devices, the second device side interface to communicate second data with each of the respective second data interfaces of the first plurality of DRAM devices, the first host side interface to communicate the first data interleaved with the second data.

[0084] Example 2: The memory module of claim 1, wherein each of the first plurality of DRAM devices comprises a plurality of DRAM integrated circuit dies.

[0085] Example 3: The memory module of claim 2, wherein the first set of memory cores and the second set of memory cores are disposed on each of the plurality of DRAM integrated circuit dies.

[0086] Example 4: The memory module of claim 1, further comprising: a second plurality of DRAM devices each having a second memory access interface to operate to independently address concurrent accesses having the same data communication direction of one of a third set of memory cores and a fourth set of memory cores in respective ones of the second plurality of DRAM devices where the third set of memory cores and the fourth set of memory cores in each of the second plurality of DRAM devices are non-overlapping sets, the second plurality of DRAM devices each having a respective third data interface to communicate data for accesses of the third set of memory cores and a respective fourth data interface to communicate data for accesses of the fourth set of memory cores; and a second data buffer device having a second host side interface, a third device side interface, and a fourth device side interface, the third device side interface to communicate third data with each of the respective third data interfaces of the second plurality of DRAM devices, the fourth device side interface to communicate fourth data with each of the respective fourthdata interfaces of the second plurality of DRAM devices, the second host side interface to communicate the third data interleaved with the fourth data.

[0087] Example 5: The memory module of claim 4, wherein the first memory access interface operates independently of the second memory access interface, and the second memory access interface operates independently of the first memory access interface.

[0088] Example 6: The memory module of claim 1, wherein the first data buffer device communicates interleaved first data and second data via the first host side interface based on a first mode of the first data buffer device.

[0089] Example 7: The memory module of claim 1, wherein the first device side interface comprises a first data signal that communicates third data associated with the first set of memory cores of a first one of the first plurality of DRAM devices and a second data signal that communicates fourth data associated with the first set of memory cores of the first one of the first plurality of DRAM devices and the first host side interface is to, based on a second mode of the first data buffer device, communicate the third data interleaved with the fourth data.

[0090] Example 8: The memory module of claim 7, the second device side interface comprises a third data signal that communicates fifth data associated with the second set of memory cores and a fourth data signal that communicates sixth data associated with the second set of memory cores and the first host side interface is to, based on the second mode of the first data buffer device, communicate the fifth data interleaved with the sixth data.

[0091] Example 9: A memory module, comprising: a first plurality of dynamic random access memory (DRAM) devices each having a first memory access interface to operate to independently access one of a first set of memory cores and a second set of memory cores in respective ones of the first plurality of DRAM devices where the first set of memory cores and the second set of memory cores in each of the first plurality of DRAM devices are nonoverlapping sets, the first plurality of DRAM devices each having a respective first data interface to communicate data for accesses of the first set of memory cores and a respective second data interface to communicate data for accesses of the second set of memory cores; and a first data buffer device includes a first host side interface and a first device side interface coupled to a first data interface of a first one of the first plurality of DRAM devices, the first device side interface including a first data signal to communicate first data and a second data signal to communicate second data, the first host side interface to communicate the first data interleaved with the second data.

[0092] Example 10: The memory module of claim 9, wherein the first data buffer device includes a second host side interface and a second device side interface coupled to a second data interface of the first one of the first plurality of DRAM devices, the second device side interface including a third data signal to communicate third data and a fourth data signal to communicate fourth data, the first host side interface to communicate the third data interleaved with the fourth data.

[0093] Example 11 : The memory module of claim 9, wherein each of the first plurality of DRAM devices comprises a plurality of DRAM integrated circuit dies.

[0094] Example 12: The memory module of claim 10, further comprising: a second plurality of DRAM devices each having a second memory access interface to operate to independently access one of a third set of memory cores and a fourth set of memory cores in respective ones of the second plurality of DRAM devices where the third set of memory cores and the fourth set of memory cores in each of the second plurality of DRAM devices are non-overlapping sets, the second plurality of DRAM devices each having a respective third data interface to communicate data for accesses of the third set of memory cores and a respective fourth data interface to communicate data for accesses of the fourth set of memory cores.

[0095] Example 13: The memory module of claim 12, further comprising: a second data buffer device includes a second host side interface and a third device side interface coupled to a third data interface of a first one of the second plurality of DRAM devices, the third device side interface including a fifth data signal to communicate fifth data and a sixth data signal to communicate sixth data, the second host side interface to communicate the fifth data interleaved with the sixth data.

[0096] Example 14: The memory module of claim 9, wherein the first data buffer device communicates interleaved first data and second data via the first host side interface based on a first mode of the first data buffer device.

[0097] Example 15: The memory module of claim 14, wherein, based on a second mode of the first data buffer device, the first host side interface is to communicate data associated with the first set of memory cores interleaved with data associated with the second set of memory cores.

[0098] Example 16: A memory module, comprising: a dual independent data channel dynamic random access memory (DRAM) device having a first data channel interface and a second data channel interface; and a data buffer device to communicate, via a host interface, first data interleaved with second data, the data buffer device to, in a first mode, communicatethe first data with the first data channel interface and the second data with the second data channel interface, the data buffer device to, in a second mode, communicate the first data with the first data channel interface and the second data with the first data channel interface.

[0099] Example 17: The memory module of claim 16, wherein the data buffer device is to communicate third data interleaved with fourth data, the data buffer device to, in the second mode, communicate the third data with the second data channel interface and the fourth data with the second data channel interface.

[0100] Example 18: The memory module of claim 16, wherein the first mode and the second mode are based on a value in a configuration register of the data buffer device.

[0101] Example 19: The memory module of claim 16, wherein the first mode and the second mode are based on a value received via a control signal received by the data buffer device.

[0102] Example 20: The memory module of claim 19, wherein the control signal is provided by the memory module.

[0103] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

CLAIMSWhat is claimed is:

1. A memory module, comprising: a first plurality of dynamic random access memory (DRAM) devices each having a first memory access interface to operate to independently address concurrent accesses having the same data communication direction of one of a first set of memory cores and a second set of memory cores in respective ones of the first plurality of DRAM devices where the first set of memory cores and the second set of memory cores in each of the first plurality of DRAM devices are nonoverlapping sets, the first plurality of DRAM devices each having a respective first data interface to communicate data for accesses of the first set of memory cores and a respective second data interface to communicate data for accesses of the second set of memory cores; and a first data buffer device having a first host side interface, a first device side interface, and a second device side interface, the first device side interface to communicate first data with each of the respective first data interfaces of the first plurality of DRAM devices, the second device side interface to communicate second data with each of the respective second data interfaces of the first plurality of DRAM devices, the first host side interface to communicate the first data interleaved with the second data.

2. The memory module of claim 1, wherein each of the first plurality of DRAM devices comprises a plurality of DRAM integrated circuit dies.

3. The memory module of claim 2, wherein the first set of memory cores and the second set of memory cores are disposed on each of the plurality of DRAM integrated circuit dies.

4. The memory module of claim 1, further comprising: a second plurality of DRAM devices each having a second memory access interface to operate to independently address concurrent accesses having the same data communication direction of one of a third set of memory cores and a fourth set of memory cores in respective ones of the second plurality of DRAM devices where the third set of memory cores and the fourth set of memory cores ineach of the second plurality of DRAM devices are non-overlapping sets, the second plurality of DRAM devices each having a respective third data interface to communicate data for accesses of the third set of memory cores and a respective fourth data interface to communicate data for accesses of the fourth set of memory cores; and a second data buffer device having a second host side interface, a third device side interface, and a fourth device side interface, the third device side interface to communicate third data with each of the respective third data interfaces of the second plurality of DRAM devices, the fourth device side interface to communicate fourth data with each of the respective fourth data interfaces of the second plurality of DRAM devices, the second host side interface to communicate the third data interleaved with the fourth data.

5. The memory module of claim 4, wherein the first memory access interface operates independently of the second memory access interface, and the second memory access interface operates independently of the first memory access interface.

6. The memory module of claim 1, wherein the first data buffer device communicates interleaved first data and second data via the first host side interface based on a first mode of the first data buffer device.

7. The memory module of claim 1, wherein the first device side interface comprises a first data signal that communicates third data associated with the first set of memory cores of a first one of the first plurality of DRAM devices and a second data signal that communicates fourth data associated with the first set of memory cores of the first one of the first plurality of DRAM devices and the first host side interface is to, based on a second mode of the first data buffer device, communicate the third data interleaved with the fourth data.

8. The memory module of claim 7, the second device side interface comprises a third data signal that communicates fifth data associated with the second set of memory cores and a fourth data signal that communicates sixth data associated with the second set of memory cores and the first host side interface is to, based on the second mode of the first data buffer device, communicate the fifth data interleaved with the sixth data.

9. A memory module, comprising: a first plurality of dynamic random access memory (DRAM) devices each having a first memory access interface to operate to independently access one of a first set of memory cores and a second set of memory cores in respective ones of the first plurality of DRAM devices where the first set of memory cores and the second set of memory cores in each of the first plurality of DRAM devices are non-overlapping sets, the first plurality of DRAM devices each having a respective first data interface to communicate data for accesses of the first set of memory cores and a respective second data interface to communicate data for accesses of the second set of memory cores; and a first data buffer device includes a first host side interface and a first device side interface coupled to a first data interface of a first one of the first plurality of DRAM devices, the first device side interface including a first data signal to communicate first data and a second data signal to communicate second data, the first host side interface to communicate the first data interleaved with the second data.

10. The memory module of claim 9, wherein the first data buffer device includes a second host side interface and a second device side interface coupled to a second data interface of the first one of the first plurality of DRAM devices, the second device side interface including a third data signal to communicate third data and a fourth data signal to communicate fourth data, the first host side interface to communicate the third data interleaved with the fourth data.

11. The memory module of claim 9, wherein each of the first plurality of DRAM devices comprises a plurality of DRAM integrated circuit dies.

12. The memory module of claim 10, further comprising: a second plurality of DRAM devices each having a second memory access interface to operate to independently access one of a third set of memory cores and a fourth set of memory cores in respective ones of the second plurality of DRAM devices where the third set of memory cores and the fourth set of memory cores in each of the second plurality of DRAM devices are nonoverlapping sets, the second plurality of DRAM devices each having arespective third data interface to communicate data for accesses of the third set of memory cores and a respective fourth data interface to communicate data for accesses of the fourth set of memory cores.

13. The memory module of claim 12, further comprising: a second data buffer device includes a second host side interface and a third device side interface coupled to a third data interface of a first one of the second plurality of DRAM devices, the third device side interface including a fifth data signal to communicate fifth data and a sixth data signal to communicate sixth data, the second host side interface to communicate the fifth data interleaved with the sixth data.

14. The memory module of claim 9, wherein the first data buffer device communicates interleaved first data and second data via the first host side interface based on a first mode of the first data buffer device.

15. The memory module of claim 14, wherein, based on a second mode of the first data buffer device, the first host side interface is to communicate data associated with the first set of memory cores interleaved with data associated with the second set of memory cores.

16. A memory module, comprising: a dual independent data channel dynamic random access memory (DRAM) device having a first data channel interface and a second data channel interface; and a data buffer device to communicate, via a host interface, first data interleaved with second data, the data buffer device to, in a first mode, communicate the first data with the first data channel interface and the second data with the second data channel interface, the data buffer device to, in a second mode, communicate the first data with the first data channel interface and the second data with the first data channel interface.

17. The memory module of claim 16, wherein the data buffer device is to communicate third data interleaved with fourth data, the data buffer device to, in the second mode, communicate the third data with the second data channel interface and the fourth data with the second data channel interface.

18. The memory module of claim 16, wherein the first mode and the second mode are based on a value in a configuration register of the data buffer device.

19. The memory module of claim 16, wherein the first mode and the second mode are based on a value received via a control signal received by the data buffer device.

20. The memory module of claim 19, wherein the control signal is provided by the memory module.

Images