Multiplexing memory module

The memory module with dual pseudo-channels and data buffer devices addresses inefficiencies in data transfer by enabling independent access to non-overlapping memory arrays, enhancing performance and compatibility across different memory technologies.

WO2026015327A1 Publication Date: 2026-01-15RAMBUS INC
5 Cites 1 Cited by

Patent Information

Application Number
PCT/US2025/036041
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-11-22
Filing Date
2025-07-01
Publication Date
2026-01-15

AI Technical Summary

Technical Problem

Existing memory systems face inefficiencies in data transfer due to overlapping bus directions and limited independent access to memory arrays, leading to suboptimal performance and compatibility issues across different memory technologies.

Method used

Implementing a memory module with dual pseudo-channels that allow independent or synchronized data bus directionality, enabling independent access to non-overlapping sets of memory arrays through a single command/address bus, and utilizing data buffer devices for time-multiplexing and deinterleaving data across these channels.

Benefits of technology

Enhances data transfer efficiency by allowing independent bus directionality between ranks and pseudo-channels, improving performance and compatibility with various memory technologies such as DRAM, SRAM, and other memory devices.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

Memory devices on a memory module may include two (or more) interfaces that access non-overlapping sets of memory arrays (i.e., two pseudo-channels). The data bus directionality of each of the two pseudo-channels may be specified or required to always be in the same direction (i.e., both read, or both write). When the data bus directionalities are tied in this manner, the data buffer devices of the module may interleave / deinterleave (i.e., time-multiplex) data for communication with a host between the two pseudo-channel data busses. The data bus directionality of each of the two pseudo-channels may be independent of the directionality of the other pseudo-channel (i.e., either can read or write without regard to the data bus directionality of the other). When the data bus directionalities are independent in this manner, the data buffer devices may interleave / deinterleave data for communication with a host within each of the two pseudo-channel data busses.
Need to check novelty before this filing date? Find Prior Art