Display panel and display device
By setting electrode patterns and enhancing the electrostatic discharge path near the bonding area of the display panel, the problem of electrostatic damage to the bonding area and fan-out area is solved, the anti-static capability of the panel is improved, and normal display is ensured.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-07-17
- Publication Date
- 2026-03-26
AI Technical Summary
Display panels are at high risk of damage from external electrostatic discharge (ESD), especially at the bezel, where ESD can easily burn out the drive circuitry in the bonding area or the vias in the fan-out area, leading to display abnormalities.
An electrode pattern is set near the bonding area. A fixed potential is applied through the electrode pattern to shield static electricity and insulate it from the signal line. The main electrode is added to overlap with the grounding wire to dissipate static electricity and increase the static discharge path. This includes setting a comb-like structure and a widened grounding wire to enhance antistatic capability.
It effectively improves the anti-static capability of the display panel, prevents electrostatic damage to the bonding area and fan-out area, and ensures the normal operation of the display function.
Smart Images
Figure CN2024106032_26032026_PF_FP_ABST
Abstract
Description
Display panel and display device TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND
[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high picture quality, no radiation, and portability, and has developed rapidly in recent years. It has gradually replaced the traditional Cathode Ray Tube display (CRT) and occupies a dominant position in the current flat panel display market. Currently, TFT-LCD has been widely used in various large, medium and small size products, and almost covers the main electronic products in today's information society, such as liquid crystal televisions, high-definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigation instruments, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, instruments, public displays, and virtual reality displays, etc.
[0003] SUMMARY
[0004] The display panel and the display device provided by the present disclosure have the following specific solutions:
[0005] In one aspect, the display panel provided by the embodiments of the present disclosure comprises:
[0006] An array substrate and an opposite substrate, wherein the array substrate comprises a display area and at least one binding area located on one side of the display area;
[0007] The opposite substrate comprises a retracted boundary relative to the array substrate, and a projection of the retracted boundary on the array substrate is located between the at least one binding area and the display area;
[0008] The array substrate further comprises:
[0009] A plurality of binding terminals, wherein the plurality of binding terminals are located in the at least one binding area;
[0010] A plurality of signal lines, wherein the plurality of signal lines are electrically connected to the plurality of binding terminals across the projection of the retracted boundary on the array substrate;
[0011] An electrode pattern is disposed in the display area and spaced apart from the plurality of bonding terminals; the electrode pattern is configured to be loaded with a fixed potential, the electrode pattern and the inner recess boundary overlap each other in a direction perpendicular to the display panel, and the electrode pattern is insulated from at least part of the signal lines.
[0012] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the array substrate further comprises at least one fan-out area between the at least one bonding area and the display area.
[0013] The electrode pattern comprises a trunk electrode integrally disposed, the trunk electrode crosses the plurality of signal lines between the bonding area and the fan-out area, and extends to between adjacent fan-out areas.
[0014] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the plurality of signal lines comprises a plurality of data lines.
[0015] The electrode pattern further comprises a branch electrode integrally disposed with the trunk electrode, the branch electrode is located between the bonding area and the fan-out area, and the extension line of the branch electrode and the extension line of the bonding terminal corresponding to the data line overlap each other.
[0016] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the plurality of signal lines further comprises a first ground line located between adjacent two fan-out areas.
[0017] The trunk electrode and the first ground line are electrically connected between adjacent fan-out areas.
[0018] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the trunk electrode comprises a first widened portion located between adjacent fan-out areas, the first ground line comprises a second widened portion located between adjacent fan-out areas, the first widened portion and the second widened portion overlap each other and are electrically connected.
[0019] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the first ground line is located in a gate metal layer, and the electrode pattern is located at least in a transparent electrode layer.
[0020] The array substrate further comprises an insulating layer between the gate metal layer and the transparent electrode layer, and the second widened portion is electrically connected with the first widened portion through a first via hole penetrating through the insulating layer.
[0021] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the electrode pattern is located in a source-drain metal layer and the transparent electrode layer.
[0022] The insulating layer comprises a first insulating layer between the gate metal layer and the source-drain metal layer, and a second insulating layer between the source-drain metal layer and the transparent electrode layer;
[0023] The second widened portion is electrically connected with the first widened portion of the transparent electrode layer through the first via hole penetrating the first insulating layer and the second insulating layer;
[0024] The electrode pattern of the source-drain metal layer and the electrode pattern of the transparent electrode layer are in contact.
[0025] The first widened portion of the source-drain metal layer and the first widened portion of the transparent electrode layer are electrically connected through a second via hole penetrating the second insulating layer.
[0026] In some embodiments, in the display panel provided in the embodiments of the present disclosure, a frame adhesive surrounding the display area is further included, and the first via hole and the second via hole are located on a side of the frame adhesive close to the display area.
[0027] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the insulating layer comprises a first insulating layer between the gate metal layer and the source-drain metal layer, and a second insulating layer between the source-drain metal layer and the transparent electrode layer.
[0028] The electrode pattern is located in the source-drain metal layer and the transparent electrode layer, and the electrode pattern of the source-drain metal layer is in contact with the transparent electrode pattern of the transparent electrode layer.
[0029] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the plurality of signal lines further comprise a first common electrode line between the data line and the first ground line, and the first common electrode line comprises a groove structure avoiding the first widened portion and the second widened portion.
[0030] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the plurality of signal lines further comprise a second ground line, the second ground line is at least partially surrounded by the first ground line on a side of the first ground line away from the first common electrode line, and the second ground line is arranged to intersect the first widened portion.
[0031] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the first ground line is electrically connected with at least one of the binding terminals, the second ground line is electrically connected with at least one of the binding terminals, and the first common electrode line is electrically connected with at least one of the binding terminals.
[0032] At least one of the binding terminals is floating between the binding terminal corresponding to the first common electrode line and the binding terminal corresponding to the data line.
[0033] At least one of the binding terminals is floating between the binding terminal corresponding to the first ground line and the binding terminal corresponding to the first common electrode line.
[0034] At least one of the binding terminals is floating between the binding terminal corresponding to the second ground line and the binding terminal corresponding to the first ground line.
[0035] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the array substrate further comprises a first non-display area on one side of the display area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; wherein the first non-display area comprises the at least one binding area.
[0036] The plurality of signal lines further comprise at least one third ground line in the second non-display area and the third non-display area, and the third ground line is electrically connected to at least one of the binding terminals close to the third non-display area.
[0037] In some embodiments, in the display panel provided in the embodiments of the present disclosure, the plurality of signal lines further comprise a data test line in the third non-display area close to the side of the at least one third ground line close to the display area.
[0038] The data test line is electrically connected to at least one of the binding terminals close to the third non-display area, and the binding terminal corresponding to the data test line is located on the side away from the third non-display area of the binding terminal corresponding to the third ground line.
[0039] In some embodiments, in the display panel provided in the embodiments of the present disclosure, at least one of the binding terminals is floating between the binding terminal corresponding to the data test line and the binding terminal corresponding to the at least one third ground line.
[0040] In some embodiments, in the display panel provided in the embodiments of the present disclosure, further comprising a silver paste point between the display area and the at least one binding area; the electrode pattern is electrically connected to the third ground line through the silver paste point.
[0041] In some embodiments, in the display panel provided in the embodiments of the present disclosure, further comprising a shielding electrode on the side of the opposite substrate away from the array substrate, and the shielding electrode is electrically connected to the third ground line through the silver paste point.
[0042] In some embodiments, in the display panel provided by the embodiments of the present disclosure, the at least two signal lines around the display area are provided with a sharp end structure.
[0043] In some embodiments, in the display panel provided by the embodiments of the present disclosure, a frame glue around the display area is further provided, and the frame glue covers the signal line farthest from the display area.
[0044] In another aspect, the embodiments of the present disclosure provide a display device, which comprises the display panel provided by the embodiments of the present disclosure and a backlight module located on the light-in side of the display panel.
[0045] In some embodiments, in the display device provided by the embodiments of the present disclosure, a circuit board electrically connected to the plurality of binding terminals is further provided, and the circuit board comprises an overvoltage protection device.
[0046] The array substrate comprises a data test line and at least one third ground line, the binding terminal corresponding to the data test line is electrically connected to the overvoltage protection device, and / or the binding terminal corresponding to the third ground line farthest from the display area is electrically connected to the overvoltage protection device.
[0047] In some embodiments, in the display device provided by the embodiments of the present disclosure, the overvoltage protection device is a pressure-sensitive resistor and / or a transient suppression diode. BRIEF DESCRIPTION OF DRAWINGS
[0048] FIG. 1 is a structural schematic diagram of a display panel provided by the embodiments of the present disclosure;
[0049] FIG. 2 is an enlarged structural schematic diagram of a Z1 region in FIG. 1;
[0050] FIG. 3 is an enlarged structural schematic diagram of a Z2 region in FIG. 2;
[0051] FIG. 4 is an enlarged structural schematic diagram of a Z3 region in FIG. 2;
[0052] FIG. 5 is an enlarged structural schematic diagram of a Z4 region in FIG. 4;
[0053] FIG. 6 is an enlarged structural schematic diagram of a Z5 region in FIG. 5;
[0054] FIG. 7 is a structural schematic diagram of a gate metal layer in FIG. 5;
[0055] FIG. 8 is a structural schematic diagram of a source-drain metal layer in FIG. 5;
[0056] FIG. 9 is a structural schematic diagram of a layer where a via is located in FIG. 5;
[0057] FIG. 10 is a structural schematic diagram of the transparent electrode layer in FIG. 5;
[0058] FIG. 11 is an enlarged structural schematic diagram of the Z6 region in FIG. 4;
[0059] FIG. 12 is an enlarged structural schematic diagram of the Z7 region in FIG. 11;
[0060] FIG. 13 is a cross-sectional structural schematic diagram along the line I-I' in FIG. 12;
[0061] FIG. 14 is a structural schematic diagram of the gate metal layer in FIG. 11;
[0062] FIG. 15 is a structural schematic diagram of the source-drain metal layer in FIG. 11;
[0063] FIG. 16 is a structural schematic diagram of the layer where the via is located in FIG. 11;
[0064] FIG. 17 is a structural schematic diagram of the transparent electrode layer in FIG. 11;
[0065] FIG. 18 is an enlarged structural schematic diagram of the Z8 region in FIG. 1;
[0066] FIG. 19 is another structural schematic diagram of the display panel provided by the embodiment of the present disclosure;
[0067] FIG. 20 is a partial structural enlarged view of adjacent signal lines provided by the embodiment of the present disclosure;
[0068] FIG. 21 is a cross-sectional structural schematic diagram along the line II-II' in FIG. 20;
[0069] FIG. 22 is another cross-sectional structural schematic diagram along the line II-II' in FIG. 20;
[0070] FIG. 23 is another structural schematic diagram of the display panel provided by the embodiment of the present disclosure;
[0071] FIG. 24 is a structural schematic diagram of the display device provided by the embodiment of the present disclosure;
[0072] FIG. 25 is another structural schematic diagram of the display device provided by the embodiment of the present disclosure. DETAILED DESCRIPTION
[0073] For the purposes of the present disclosure, the goals, technical solutions, and advantages of the embodiments will be more clearly understood from the following description of the embodiments of the present disclosure, taken in conjunction with the accompanying drawings. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, and the like are exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features. A sharp angle illustrated can typically be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not to be construed as limiting to the region. The purpose of the regions illustrated in the figures is to more conceptually illustrate the logical proximity between illustrated regions for an intraoperative tool to be used in the surgical procedure. Furthermore, the same or similar reference numerals are used in different drawings to denote the same or similar elements or components having the same or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and structures incorporated herein will be omitted.
[0074] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The use of the terms "first", "second", and the like, does not imply any order, quantity, or importance, but rather are used to distinguish one element from another. The terms "comprises", "comprising", "includes", "including" and the like, means encompassing, and therefore specifies the presence and avoids the exclusion of not only the listed components but also other components not specifically listed. The terms "connected", "coupled", and the like, are not limited to direct or physical connections or couplings, but can include indirect coupling between connected items or intervening items therebetween allowing a signal to be sent therebetween. The terms "inner", "outer", "upper", "lower", and the like, are used only to describe relative positions to the absolute positions of the described objects, and can change accordingly when the absolute positions of the described objects change.
[0075] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. When an element or layer is referred to as being "on one side of" another element or layer, it can be directly on the side of the other element or layer, directly connected to the other element or layer, or an intervening element or layer can be present. However, when an element or layer is referred to as being "directly on" another element or layer, or "directly connected to" another element or layer, there is no intervening element or layer present. The term "and / or" includes any and all combinations of one or more of the associated listed items.
[0076] The display panel production process and the post-assembly, use process are subject to the risk of external electrostatic (ESD) damage. In order to verify the ESD resistance of the panel, an electrostatic gun is used to perform electrostatic discharge evaluation on the panel in the quality evaluation process.
[0077] In some embodiments, the upper frame, the left frame, and the right frame of the display panel are provided with a ground line for improving the anti-static ability. When static electricity is generated at the lower frame, the via of the driving circuit (such as a chip on film (COF)) in the binding area or the fanout line in the fanout area is easily burned out, thereby causing display abnormalities.
[0078] To at least improve the above technical problems, the display panel provided by the embodiments of the present disclosure, a structure schematic diagram of a display panel provided by the embodiments of the present disclosure is shown in FIG. 1, an enlarged structure schematic diagram of a Z1 area in FIG. 1 is shown in FIG. 2, an enlarged structure schematic diagram of a Z2 area in FIG. 2 is shown in FIG. 3, an enlarged structure schematic diagram of a Z3 area in FIG. 2 is shown in FIG. 4, an enlarged structure schematic diagram of a Z4 area in FIG. 4 is shown in FIG. 5, an enlarged structure schematic diagram of a Z5 area in FIG. 5 is shown in FIG. 6, a structure schematic diagram of a gate metal layer in FIG. 5 is shown in FIG. 7, a structure schematic diagram of a source-drain metal layer in FIG. 5 is shown in FIG. 8, a structure schematic diagram of a layer where a via is located in FIG. 5 is shown in FIG. 9, a structure schematic diagram of a transparent electrode layer in FIG. 5 is shown in FIG. 10, an enlarged structure schematic diagram of a Z6 area in FIG. 4 is shown in FIG. 11, an enlarged structure schematic diagram of a Z7 area in FIG. 11 is shown in FIG. 12, a cross-sectional structure schematic diagram along a line I-I' in FIG. 12 is shown in FIG. 13, a structure schematic diagram of a gate metal layer in FIG. 11 is shown in FIG. 14, a structure schematic diagram of a source-drain metal layer in FIG. 11 is shown in FIG. 15, a structure schematic diagram of a layer where a via is located in FIG. 11 is shown in FIG. 16, and a structure schematic diagram of a transparent electrode layer in FIG. 11 is shown in FIG. 17.
[0079] As can be seen from FIGS. 1 to 17, the display panel provided by the embodiments of the present disclosure can include:
[0080] The array substrate 001 and the opposite substrate 002 are opposite to each other, wherein the array substrate 001 comprises a display area AA and at least one binding area BA located at one side of the display area AA. Optionally, the display area AA can comprise a red sub-pixel area, a green sub-pixel area, a blue sub-pixel area, etc. The binding area BA can be connected to a driving circuit (such as a flexible circuit board FPC, or a driving circuit of a binding data chip source IC, etc.) in a binding manner. The non-display area where the binding area BA is located is a first non-display area DP. The array substrate 001 can further comprise a second non-display area DPO opposite to the first non-display area DP, and two third non-display areas GL&GR connecting the first non-display area DP and the second non-display area DPO.
[0081] The opposite substrate 002 comprises a retracted boundary CL opposite to the array substrate 001. The orthographic projection of the retracted boundary CL on the array substrate 001 is located between the binding area BA and the display area AA, so as to expose the binding area BA and facilitate the binding connection between the binding area BA and the driving circuit (such as a flexible circuit board FPC, or a driving circuit of a binding data chip source IC, etc.).
[0082] The array substrate 001 can further comprise:
[0083] A plurality of binding terminals 101 are located in the at least one binding area BA. In some embodiments, the present disclosure has a plurality of binding areas BA. The number and arrangement of the binding terminals 101 in each binding area BA can be the same or different. Optionally, the binding terminal 101 is located in the gate metal layer (GT) and the transparent electrode layer (ITO). The pattern of the binding terminal 101 located in the gate metal layer (GT) and the pattern of the binding terminal 101 located in the transparent electrode layer (ITO) are electrically connected through the connection hole V. In some embodiments, the material of the gate metal layer (GT) can comprise at least one metal of gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc. The gate metal layer (GT) can be a single-layer structure or a laminated structure, for example, the gate metal layer (GT) is a single-layer structure composed of a molybdenum metal layer. The material of the transparent electrode layer (ITO) can comprise at least one transparent conductive material of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), etc. In addition, it should be noted that the array substrate 001 in the present disclosure can only comprise the transparent electrode layer where the pixel electrode (pixel) is located, or can simultaneously comprise the transparent electrode layer where the pixel electrode (pixel) is located and the transparent electrode layer where the common electrode (com) is located. In the case that the array substrate 001 has two transparent electrode layers, the transparent electrode layer where the binding terminal 101 is located is the transparent electrode layer closer to the opposite substrate 002.
[0084] A plurality of signal lines 102, the orthogonal projection of the plurality of signal lines 102 on the array substrate 001 across the inwardly recessed boundary CL, the plurality of signal lines CL are electrically connected with the plurality of binding terminals 101, optionally, the signal lines 102 located in the local of the binding area BA can be reused as the gate metal layer (GT) pattern corresponding to the binding terminal 101; in some embodiments, the signal lines 102 can include data lines (Data line, DL), gate driving circuit lines (GOA line), ground lines (GND line), and common electrode lines (Com line); wherein the gate driving circuit lines (GOA line), the ground lines (GND line), and the common electrode lines (Com line) can be located outside the display area AA, the data lines DL are located inside and outside the display area AA, and the data lines DL can be arranged in different layers or in the same layer inside and outside the display area AA, optionally, the data lines DL are located in the source-drain metal layer (SD) inside the display area AA and in the gate metal layer (GT) outside the display area AA.
[0085] The data lines DL can be electrically connected with the binding terminals 101 in the middle of each binding area BA, the gate driving circuit lines (GOA line) and the ground lines (GND line) can be electrically connected with the binding terminals 101 at the left edge of the left end binding area BA and at the right edge of the right end binding area BA, and the common electrode lines (Com line) can be electrically connected with the binding terminals 101 at the right edge of the left end binding area BA, at the left edge of the right end binding area BA, and at the left and right edges of the middle binding area BA.
[0086] In some embodiments, the gate driving circuit lines (GOA line) can include one or more of a frame start signal line STV1A, STV1B, a total reset signal line STV0, clock signal lines CLK1-CLK12 (specifically, the number of clock signal lines is not limited, and in this case, 12 clock signal lines are taken as an example), a noise reduction signal line VDDO, VDDE, a low-level signal line VGL, etc.; wherein the frame start signal line can be one or more, which is not limited herein, and in this case, two frame start signal lines are taken as an example, the frame start signal lines STV1A, STV1B are trigger input signals for odd-numbered rows and even-numbered rows, respectively; the clock signal lines CLK1-CLK12 are responsible for providing the output voltage of each row of gate; the noise reduction signal lines VDDO, VDDE provide input signals for the noise reduction unit of the gate driving circuit, with a 50% duty cycle and high-low level alternately switching; and the low-level signal line VGL provides an internal low-level voltage for the gate driving circuit.
[0087] The electrode pattern 103 is arranged apart from the plurality of binding terminals 101 on the side of the display area AA close to the binding area BA to avoid short-circuiting of the plurality of binding terminals 101 through the electrode pattern 103. Optionally, the electrode pattern 103 is configured to be loaded with a fixed potential (e.g. ground) to serve the purpose of shielding static electricity. The electrode pattern 103 can also overlap the inner shrinkage boundary CL in the direction perpendicular to the display panel to protect the signal lines 102 under the electrode pattern 103 during the cutting process of forming the inner shrinkage boundary CL. In some embodiments, the electrode pattern 103 is at least insulated from at least part of the signal lines 102, for example, the electrode pattern 103 is insulated from the signal lines 102 loaded with non-fixed potentials such as the data lines DL, GOA lines, etc. to avoid signal crosstalk of the electrode pattern 103 to the signal lines 102 loaded with non-fixed potentials. Optionally, the electrode pattern 103 can be located in the transparent electrode layer (ITO) where the binding terminals 101 are located, or the electrode pattern 103 is located in the transparent electrode layer (ITO) and the source-drain metal layer (SD) where the binding terminals 101 are located, and the material of the source-drain metal layer (SD) can include at least one metal such as gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc. The source-drain metal layer (SD) can be a single-layer structure or a stacked structure, for example, the source-drain metal layer (SD) is a stacked structure composed of a titanium metal layer / aluminum metal layer / titanium metal layer.
[0088] In the display panel provided in the embodiments of the present disclosure, the electrode pattern 103 arranged on the DP side of the binding area BA can serve the purpose of shielding static electricity when static electricity is generated on the DP side to improve the anti-static capability of the panel DP side. In addition, the electrode pattern 103 is arranged apart from the binding terminals 101 and insulated from the signal lines 102 loaded with non-fixed potentials to avoid short-circuiting of the electrode pattern 103 with the binding terminals 101 or the signal lines 102. Meanwhile, the electrode pattern 103 can also prevent the cutting process of the opposite substrate 102 from cutting off the signal lines 102. Therefore, the addition of the electrode pattern 103 does not affect the normal display function while improving the anti-static capability.
[0089] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 1-10, the array substrate 001 can further include at least one fan-out area FA between the binding area BA and the display area AA; the electrode pattern 103 can include a trunk electrode 1031, which crosses the plurality of signal lines 102 between the binding area BA and the fan-out area FA and extends between adjacent fan-out areas FA, so as to ensure that the trunk electrode 1031 has a larger area and stronger ability to dissipate static electricity. In the case of cutting protection for the signal lines 102, a floating structure can be provided, and the present disclosure can connect the floating structures together in the arrangement direction (i.e., the left-right direction in the figure) as the trunk electrode 1031, or, in the case where the wiring space allows, to further increase the area of the trunk electrode 1031 and improve the anti-static ability, the trunk electrode 1031 can be arranged to cover the pattern in which the floating structures are connected together in the arrangement direction (i.e., the left-right direction in the figure).
[0090] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 1-6, the electrode pattern 103 can further include a branch electrode 1032 arranged integrally with the trunk electrode 1031, so that the electrode pattern 103 has a comb structure. The branch electrode 1032 is located between the binding area BA and the fan-out area FA, and the extension line of the branch electrode 1032 and the extension line of the binding terminal 101 corresponding to the data line DL (FIGS. 5 and 7 show the complete pattern of two data lines DL close to the first common electrode line COM1, and the remaining data lines DL show the pattern of the vertical line extension and omit the pattern of the inclined extension) overlap each other, and optionally, the binding terminal 101 corresponding to the data line DL after the extension of the branch electrode 1032 substantially coincides. In some embodiments, the branch electrode 1032 can be multiplexed with the floating structure for cutting protection of the signal line 102 in the related art, and at this time, the present disclosure only needs to add the trunk electrode 1031 connecting the floating structures together on the side of the floating structure close to the fan-out area FA to obtain the comb-shaped electrode pattern 103.
[0091] It should be noted that in the embodiments provided in the present disclosure, due to the limitation of process conditions or the influence of other factors such as measurement, the "substantial coincidence" may be exact coincidence or may have some deviation (for example, with a deviation of ±2 μm), and therefore the "substantial coincidence" between the related features is within the protection scope of the present disclosure as long as the error is allowed.
[0092] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 1, 3-17, a first ground line GND1 can be arranged between two adjacent fan-out areas FA, and the trunk electrode 1031 can be electrically connected to the first ground line GND1, so that the electrode pattern 103 conducts static electricity to the external ground through the first ground line GND1 for release.
[0093] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 1, 3, 4, 11-17, to enhance the electrical connection effect, the stem electrode 1031 can include a first widened portion WP1 located between adjacent fan-out areas FA, the first ground line GND1 includes a second widened portion WP2 located between adjacent fan-out areas FA, the first widened portion WP1 and the second widened portion WP2 are mutually overlapped and electrically connected. Optionally, the first ground line GND1 is located in the gate metal layer (GT), and the electrode pattern 103 is at least located in the transparent electrode layer (ITO); the gate metal layer (GT) and the transparent electrode layer (ITO) have an insulating layer 104, and the second widened portion WP2 is electrically connected with the first widened portion WP1 through a first via V1 penetrating the insulating layer 104. In some embodiments, the electrode pattern 103 is located in both the source-drain metal layer (SD) and the transparent electrode layer (ITO); the insulating layer 104 includes a first insulating layer 1041 located between the gate metal layer (GT) and the source-drain metal layer (SD), and a second insulating layer 1042 located between the source-drain metal layer (SD) and the transparent electrode layer (ITO); the second widened portion WP2 is electrically connected with the first widened portion WP1 of the transparent electrode layer (ITO) through a first via V1 penetrating the first insulating layer 1041 and the second insulating layer 1042.
[0094] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 11-17, in the case that the electrode pattern 103 of the source-drain metal layer (SD) and the electrode pattern 103 of the transparent electrode layer (ITO) have a second insulating layer 1042, the first widened portion WP1 of the source-drain metal layer (SD) and the first widened portion WP1 of the transparent electrode layer (ITO) are electrically connected through a second via V2 penetrating the second insulating layer 1042. Optionally, as shown in FIG. 3, the first via V1 and the second via V2 can be located on the side of the display area AA close to the sealing frame glue 105, so as to prevent the first via V1 and the second via V2 from being eroded by water and oxygen through the sealing frame glue 105. Optionally, in the case that the source-drain metal layer (SD) is located between the gate metal layer (GT) and the transparent electrode layer (ITO), as shown in FIG. 12, the first widened portion WP1 of the source-drain metal layer (SD) can include a hollow structure O exposing the first via V1. In addition, the first via V1 and the second via V2 in the present disclosure can have a shape and size of a normal projection substantially the same as that of the connection hole V of the binding terminal 101, so as to simplify the via manufacturing process. In other embodiments, the second insulating layer 1042 between the electrode pattern 103 of the source-drain metal layer (SD) and the electrode pattern 103 of the transparent electrode layer (ITO) can also be omitted, so that the electrode pattern 103 of the source-drain metal layer (SD) and the electrode pattern 103 of the transparent electrode layer (ITO) are arranged in contact.
[0095] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 3 to 17, a first common electrode line Com1 can be arranged between the data line DL and the first ground line GND1. Optionally, the first ground line GND1 and the first common electrode line Com1 can be arranged in the same layer and made of the same material, for example, the first ground line GND1 and the first common electrode line Com1 are located in the gate metal layer (GT). In some embodiments, the first common electrode line Com1 includes a groove structure GS avoiding the first widened portion WP1 and the second widened portion WP2, so as to avoid the short circuit of the first common electrode line Com1 and the first common electrode line Com1.
[0096] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 4 to 17, the signal line 102 can further include a second ground line GND2 arranged in the same layer and made of the same material as the first ground line GND1 between adjacent fan-out areas FA. The second ground line GND2 is at least partially surrounded by the first ground line GND1 on the side of the first ground line GND1 away from the first common electrode line Com1, and the second ground line GND2 is arranged to intersect the first widened portion WP1, so as to further improve the anti-static capability by using the second ground line GND2. Optionally, the second ground line GND2 and the first widened portion WP1 can be electrically connected or insulated from each other, which is not limited in the present disclosure.
[0097] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 4-10, the first ground line GND1 can be electrically connected with the at least one binding terminal 101, the second ground line GND2 can be electrically connected with the at least one binding terminal 101, and the first common electrode line Com1 can be electrically connected with the at least one binding terminal 101. In the case that the first ground line GND1, the second ground line GND2, and the first common electrode line Com1 are respectively electrically connected with the plurality of binding terminals 101, the binding effect can be enhanced, and at the same time, the electrostatic discharge path of the ground line (including the first ground line GND1 and the second ground line GND2) can be increased, and the speed of releasing electrostatic charge can be improved. Optionally, between the binding terminal 101 corresponding to the first common electrode line Com1 and the binding terminal 101 corresponding to the data line DL, at least one floating binding terminal 101 is provided; and / or, between the binding terminal 101 corresponding to the first ground line GND1 and the binding terminal 101 corresponding to the first common electrode line Com1, at least one floating binding terminal 101 is provided; and / or, between the binding terminal 101 corresponding to the second ground line GND2 and the binding terminal 101 corresponding to the first ground line GND1, at least one floating binding terminal 101 is provided. By increasing the floating binding terminal 101 between the binding terminal 101 corresponding to the first ground line GND1 and the second ground line GND2 and other signals (for example, the first common electrode line Com1), the electrostatic discharge of the binding position gold ball from burning other signal lines (for example, the first common electrode line Com1) can be effectively prevented.
[0098] In some embodiments, in the display panel provided in the embodiments of the present disclosure, FIG. 18 is an enlarged structural schematic view of the Z8 region in FIG. 1, and FIG. 19 is another structural schematic view of the display panel provided in the embodiments of the present disclosure. As shown in FIGS. 1, 18, and 19, in order to increase the electrostatic discharge path and improve the anti-static ability, at least one third ground line GND3 can be arranged in the second non-display area DPO and the third non-display area GL&GR, and the third ground line GND3 can be electrically connected with at least one binding terminal 101 close to the third non-display area GL&GR, for example, the third ground line GND3 is electrically connected with 1-4 binding terminals 101 close to the third non-display area GL&GR.
[0099] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIGS. 1 and 18, the third ground line GND3 is provided with a data test line ADD close to one side of the display area AA; the data test line ADD is electrically connected to at least one (for example, 4) binding terminal 101 close to the third non-display area GL&GR, and the binding terminal 101 corresponding to the data test line ADD is located on the side of the binding terminal 101 corresponding to the third ground line GND3 away from the third non-display area GL&GR. The data test line ADD is used to detect whether the data line DL exists in the array stage, and to discharge the static electricity on the data line DL to the ground line or the common electrode line in the Cell segment. In the case that the data test line ADD is electrically connected to a plurality of binding terminals 101, the static electricity release path is increased, and the static electricity release speed is improved, thereby effectively improving the anti-static capability.
[0100] In some embodiments, in the display panel provided in the embodiments of the present disclosure, as shown in FIG. 18, at least one floating binding terminal 101 can be provided between the binding terminal 101 corresponding to the data test line ADD and the binding terminal 101 corresponding to the third ground line GND3, so as to prevent the static electricity release of the third ground line GND3 from burning the data test line ADD.
[0101] In some embodiments, in the display panel provided in the embodiments of the present disclosure, FIG. 20 is an enlarged view of the local structure of the adjacent signal line 102 provided in the embodiments of the present disclosure, as shown in FIG. 20, in addition to the third ground line GND3 and the data test line ADD at least partially arranged in the display area AA, the signal line 102 can also include the second common electrode line Com2, the clock signal line CLK, etc. at least partially arranged in the display area AA. The line width of these signal lines 102 will not be the same due to the wiring limitation, and when static electricity is generated, the place with the thinnest line is usually preferentially broken down. In this regard, at least part of the adjacent signal lines 102 in the present disclosure can include oppositely arranged sawtooth-shaped tip structures, so as to release the accumulated static electricity through the tip structures, prevent static electricity breakdown at the thinner position of the signal line 102, and since the sawtooth-shaped tip structures are arranged more, the static electricity is preferentially attracted to the tip structures to release, which has little effect on the effective line of the signal transmission. In some embodiments, the distance between the oppositely arranged tip structures is greater than or equal to ≥5 μm.
[0102] In some embodiments, as shown in FIG. 21, the sealant 105 can cover the clock signal line CLK, the second common electrode line Com2, and partially overlap the data test line ADD, and the third ground line GND3 is located outside the sealant 105 (i.e., away from the display area AA) and is not covered by the sealant 105. Since the third ground line GND3 in the signal line 102 is closest to the cutting line of the panel on the DPO side and the GL&GR side (i.e., the flush boundary of the array substrate 001 and the opposite substrate 002 on the DPO side and the GL&GR side), when static electricity is generated, static electricity is easily introduced from the gap between the array substrate 001 and the opposite substrate 002, causing the third ground line GND3 exposed by the sealant 105 to burn out. Based on this, as shown in FIG. 22, in some embodiments, the sealant 105 can be arranged to cover the third ground line GND3 farthest from the display area AA, so that when static electricity is generated, it is preferentially shielded / absorbed / consumed by the sealant 105, so that static electricity cannot actually act on the third ground line GND3 or the value of the acting static electricity is small, which is not enough to burn out the third ground line GND3, thereby enhancing the anti-static capability of the panel.
[0103] In some embodiments, in the above-mentioned display panel provided by the embodiments of the present disclosure, as shown in FIG. 23, a shielding electrode 003 can also be arranged on the side of the opposite substrate 002 away from the array substrate 001, and the shielding electrode 003 can be electrically connected to the third ground line GND3 through the silver dot AD shown in FIG. 2, so as to further improve the anti-static capability of the display panel. It should be understood that in the present disclosure, the above-mentioned solutions other than the shielding electrode 003 can also achieve good anti-static effect, and the shielding electrode 003 can be omitted in the present disclosure to be applicable to FIC / low reflectivity products. It should be noted that the connection of the electrode pattern 103 and the GND signal in the present case can be to provide a signal through the pad (i.e., the binding terminal 101) corresponding to the GND1 signal line between adjacent COFs, or to realize signal conduction through the pad corresponding to the third ground line GND3, or to realize signal conduction through both the pad corresponding to the GND1 signal line between adjacent COFs and the pad corresponding to the third ground line GND3, which is not limited herein. In addition, as shown in FIG. 2, the electrode pattern 103 of the present disclosure can also be electrically connected to the third ground line GND3 through the silver dot AD, so that the electrode pattern 103 conducts static electricity to the outside ground through the third ground line GND3 for release, thereby further improving the anti-static capability.
[0104] In some embodiments, in the display panel provided by the embodiments of the present disclosure, as shown in FIG. 1, FIG. 4 and FIG. 18, the array substrate 001 can further include alignment marks MK located at the gate metal layer (GT), dummy patterns DY located at the transparent electrode layer (ITO), and gate drive circuit GOA located at the third non-display area GL&GR, etc. In addition, in order to enhance the curing effect of the frame sealant 105, as shown in FIG. 5, the area with a larger line width of the first common electrode line com1 and other signal lines 102 can be hollowed out. The other indispensable components in the array substrate should be understood by those skilled in the art, and will not be described here again, nor should it be regarded as a limitation on the present disclosure.
[0105] In some embodiments, in the display panel provided by the embodiments of the present disclosure, as shown in FIG. 23, a liquid crystal layer 004 can be further arranged between the array substrate 001 and the opposite substrate 002, a first polarizer 005 can be arranged on the side of the array substrate 001 away from the opposite substrate 002, a second polarizer 006 can be arranged on the side of the opposite substrate 002 away from the array substrate 001, and the polarization direction of the first polarizer 005 is perpendicular to the polarization direction of the second polarizer 006. The other indispensable components in the display panel should be understood by those skilled in the art, and will not be described here again, nor should it be regarded as a limitation on the present disclosure.
[0106] Based on the same inventive concept, the embodiments of the present disclosure provide a display device. FIG. 24 and FIG. 25 are structural schematic diagrams of a display device provided by the embodiments of the present disclosure. As shown in FIG. 24 and FIG. 25, the display device provided by the embodiments of the present disclosure can include the display panel PNL provided by the embodiments of the present disclosure, and a backlight module BLU located on the light-in side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side type backlight module. Optionally, the side type backlight module can include a lamp strip, a laminated reflector, a light guide plate, a diffusion sheet, a prism group, etc., and the lamp strip is located on one side of the light guide plate in the thickness direction. The direct type backlight module can include a matrix light source, a reflector laminated on the light-out side of the matrix light source, a diffusion plate, a brightness enhancement film, etc., and the reflector includes openings corresponding to the positions of the lamp beads in the matrix light source. The lamp beads in the lamp strip and the lamp beads in the matrix light source can be light emitting devices (LEDs), such as quantum dot light emitting devices.
[0107] In some embodiments, the lamp bead can also be a micro light emitting device (such as Mini LED, Micro LED), and the like. The micro light emitting device in the order of sub-millimeter or even micrometer and the organic light emitting device (OLED) are self-luminous devices. Like the organic light emitting device, it has a series of advantages such as high brightness, ultra-low delay, and ultra-large viewing angle. And because the inorganic light emitting device emits light based on the metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, better resistance to high and low temperatures, and longer service life compared to the organic light emitting device based on organic matter. When the micro light emitting device is used as a backlight, it can achieve more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by traditional dynamic backlight between screen bright and dark areas, and optimize the visual experience.
[0108] In some embodiments, in the display device provided by the embodiments of the present disclosure, as shown in FIG. 25, a circuit board XPCB electrically connected to the plurality of binding terminals 101 can be further included, and the circuit board XPCB includes an overvoltage protection device OVP (such as a pressure-sensitive resistor and / or a transient voltage suppression diode TVS). Optionally, the binding terminal 101 corresponding to the data test line ADD is electrically connected to the overvoltage protection device OPV, and / or the binding terminal 101 corresponding to the third ground line GND3 farthest from the display area AA is electrically connected to the overvoltage protection device OPV. In the normal state, the data test line ADD and the third ground line GND3 are in a disconnected state, and when static high voltage arrives, the data test line ADD and the third ground line GND3 are in a connected state, so as to achieve rapid release of static electricity. In addition, the outermost third ground line GND3 is connected in series with an overvoltage protection device OVP on the circuit board XPCB, and then connected in parallel with the inner third ground line GND3. The other ground design of the circuit board XPCB can be consistent with related art. In this way, in the normal working state of the display panel, the GND signal of the circuit terminal is mainly affected by the inner third ground line GND3. When static instantaneous high voltage is generated, the third ground line GND3 containing the overvoltage protection device OVP in the outer circle can absorb excess current and clamp the voltage at a relatively fixed voltage value, so as to protect the in-plane wiring part and improve the anti-static ability of the panel.
[0109] In some embodiments, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as a television, a display, a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, and the like. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through wires, signal lines, and the like arranged additionally. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate array, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate array, programmable array logic, programmable logic device, and the like. In addition, the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or arrange different components.
[0110] Although the preferred embodiments of the present disclosure have been described, those skilled in the art who are informed of the basic inventive concept can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.
[0111] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.
Claims
1. A display panel, wherein, Comprising: opposite array substrate and opposite substrate, wherein the array substrate comprises a display area, and at least one binding area located on one side of the display area; The opposite substrate comprises a retracted boundary relative to the array substrate, and the orthogonal projection of the retracted boundary on the array substrate is located between the at least one binding area and the display area; The array substrate further comprises: A plurality of binding terminals, the plurality of binding terminals are located in the at least one binding area; A plurality of signal lines, the orthogonal projection of the plurality of signal lines on the array substrate across the retracted boundary, the plurality of signal lines are electrically connected with the plurality of binding terminals; The electrode pattern is arranged between the display area and the plurality of binding terminals; the electrode pattern is configured to load a fixed potential, the electrode pattern and the retracted boundary are mutually overlapped in the direction perpendicular to the display panel, and the electrode pattern and at least part of the signal line are mutually insulated.
2. The display panel of claim 1, wherein, The array substrate further comprises at least one fan-out area between the at least one binding area and the display area; The electrode pattern comprises a trunk electrode arranged integrally, the trunk electrode crosses the plurality of signal lines between the binding area and the fan-out area, and extends to between adjacent fan-out areas.
3. The display panel of claim 2, wherein, The plurality of signal lines comprises a plurality of data lines; The electrode pattern further comprises a branch electrode arranged integrally with the trunk electrode, the branch electrode is located between the binding area and the fan-out area, and the extension line of the branch electrode and the extension line of the binding terminal corresponding to the data line are mutually overlapped.
4. The display panel of claim 3, wherein, The plurality of signal lines further comprises a first ground line between adjacent two fan-out areas; The trunk electrode and the first ground line are electrically connected between adjacent fan-out areas.
5. The display panel of claim 4, wherein, The trunk electrode comprises a first widened part between adjacent fan-out areas, the first ground line comprises a second widened part between adjacent fan-out areas, the first widened part and the second widened part are mutually overlapped and electrically connected.
6. The display panel of claim 5, wherein, The first ground line is located in a gate metal layer, and the electrode pattern is located in a transparent electrode layer; The array substrate further comprises an insulating layer between the gate metal layer and the transparent electrode layer, and the second widened part is electrically connected with the first widened part through a first via hole penetrating the insulating layer.
7. The display panel of claim 6, wherein, The electrode pattern is located in a source-drain metal layer and the transparent electrode layer; The insulating layer comprises a first insulating layer between the gate metal layer and the source-drain metal layer, and a second insulating layer between the source-drain metal layer and the transparent electrode layer; The second widened part is electrically connected with the first widened part of the transparent electrode layer through the first via hole penetrating the first insulating layer and the second insulating layer; The electrode pattern of the source-drain metal layer and the electrode pattern of the transparent electrode layer have the second insulating layer therebetween; The first widened part of the source-drain metal layer and the first widened part of the transparent electrode layer are electrically connected through a second via hole penetrating the second insulating layer.
8. The display panel of claim 7, wherein, The array substrate further comprises a sealant surrounding the display area, the first via and the second via are located on a side of the sealant close to the display area.
9. The display panel of claim 6, wherein, The insulating layer comprises a first insulating layer between the gate metal layer and the source-drain metal layer, and a second insulating layer between the source-drain metal layer and the transparent electrode layer. The electrode pattern is located on the source-drain metal layer and the transparent electrode layer, and the electrode pattern of the source-drain metal layer is arranged in contact with the transparent electrode pattern of the transparent electrode layer.
10. The display panel of any of claims 5-9, wherein, The plurality of signal lines further comprises a first common electrode line between the data line and the first ground line, and the first common electrode line comprises a groove structure avoiding the first widened portion and the second widened portion.
11. The display panel of claim 10, wherein, The plurality of signal lines further comprises a second ground line, and the second ground line is at least partially surrounded by the first ground line on a side of the first ground line away from the first common electrode line, and the second ground line is arranged to intersect the first widened portion.
12. The display panel of claim 11, wherein, The first ground line is electrically connected to at least one of the bonding terminals, the second ground line is electrically connected to at least one of the bonding terminals, and the first common electrode line is electrically connected to at least one of the bonding terminals. At least one of the bonding terminals is floating between the bonding terminal corresponding to the first common electrode line and the bonding terminal corresponding to the data line. At least one of the bonding terminals is floating between the bonding terminal corresponding to the first ground line and the bonding terminal corresponding to the first common electrode line. At least one of the bonding terminals is floating between the bonding terminal corresponding to the second ground line and the bonding terminal corresponding to the first ground line.
13. The display panel of any one of claims 1 to 12, wherein, The array substrate further comprises a first non-display area on a side of the display area, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; wherein the first non-display area comprises the at least one binding area. The plurality of signal lines further comprises at least one third ground line in the second non-display area and the third non-display area, and the third ground line is electrically connected to at least one of the bonding terminals close to the third non-display area.
14. The display panel of claim 13, wherein, The plurality of signal lines further comprises a data test line in the third non-display area on a side of the at least one third ground line close to the display area. The data test line is electrically connected to at least one of the bonding terminals close to the third non-display area, and the bonding terminal corresponding to the data test line is located on a side of the bonding terminal corresponding to the third ground line away from the third non-display area. At least one of the bonding terminals is floating between the bonding terminal corresponding to the data test line and the bonding terminal corresponding to the at least one third ground line.
15. The display panel of claim 14, wherein, The array substrate further comprises a silver paste point between the display area and the at least one binding area; and the electrode pattern is electrically connected to the third ground line through the silver paste point.
16. The display panel of any of claims 13-15, wherein, 17. The display panel of claim 16, wherein, The display panel further comprises a shielding electrode on a side of the opposite substrate distal to the array substrate, and the shielding electrode is electrically connected to the third ground line through the silver paste point.
18. The display panel of any one of claims 1-17, wherein, At least part of the two adjacent signal lines around the display area comprises a relatively arranged sharp end structure.
19. The display panel of any one of claims 1-18, wherein, The display panel further comprises a frame sealant around the display area, and the frame sealant covers the signal line farthest from the display area.
20. A display device comprising: The display panel further comprises a backlight module on a light-in side of the display panel.
21. The display device of claim 20, wherein, The display panel further comprises a circuit board electrically connected to the plurality of binding terminals, and the circuit board comprises an overvoltage protection device. The array substrate comprises a data test line and at least one third ground line, the binding terminal corresponding to the data test line is electrically connected to the overvoltage protection device, and / or the binding terminal corresponding to the third ground line farthest from the display area is electrically connected to the overvoltage protection device.
22. The display device of claim 21, wherein, The overvoltage protection device is a pressure-sensitive resistor and / or a transient suppression diode.