Semiconductor structure and semiconductor structure manufacturing method

Abstract

The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a semiconductor structure manufacturing method. The semiconductor structure comprises: a substrate; a support structure located on the substrate and capacitor holes arranged at intervals, the capacitor holes passing through the support structure; and lower electrodes located in the capacitor holes, wherein the lower electrodes each comprise a first lower electrode layer, a second lower electrode layer and a third lower electrode layer, the first lower electrode layer covers the bottom and side wall of the corresponding capacitor hole, the second lower electrode layer is conformal to the first lower electrode layer to form a cavity, the third lower electrode layer fills the cavity, and the work function of the second lower electrode layer is greater than that of the first lower electrode layer and that of the third lower electrode layer.

Description

Semiconductor structure and methods for preparing semiconductor structures

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Chinese Patent Application No. 202410948598.0, filed on July 15, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the semiconductor structure. Background Technology

[0004] Dynamic Random Access Memory (DRAM) is a type of volatile memory. It consists of multiple memory cells, each of which mainly includes a transistor and a capacitor. The memory cells are electrically connected to each other through word lines (WL) and bit lines (BL).

[0005] As DRAM feature sizes continue to shrink, the leakage effect of capacitor structures becomes increasingly apparent when feature sizes are reduced to below a certain value. Improving the leakage effect of capacitor structures while reducing the additional side effects has become an urgent technical problem to be solved.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0007] Summary of the Invention

[0008] This disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure. The semiconductor structure can improve the leakage current performance of the semiconductor structure and reduce the resistance of the semiconductor structure.

[0009] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0010] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0011] Substrate;

[0012] The support structure is located above the substrate and the capacitor holes are arranged at intervals, with the capacitor holes penetrating the support structure.

[0013] The lower electrode is located inside the capacitor hole, and includes a first lower electrode layer, a second lower electrode layer and a third lower electrode layer. The first lower electrode layer covers the bottom and sidewalls of the capacitor hole. The second lower electrode layer is conformal to the first lower electrode layer and forms a cavity. The third lower electrode layer fills the cavity. The work function of the second lower electrode layer is greater than that of the first lower electrode layer and is also greater than that of the third lower electrode layer.

[0014] In one embodiment, the oxygen content of the second lower electrode layer is greater than that of the first lower electrode layer and also greater than that of the third lower electrode layer.

[0015] In one embodiment, the oxygen content of the second lower electrode layer gradually increases or increases in a gradient along the direction from the center to the edge of the capacitor hole.

[0016] In one embodiment, the conductivity of the third lower electrode layer is greater than that of the second lower electrode layer, and is greater than or equal to that of the first lower electrode layer.

[0017] In one embodiment, the material of the third lower electrode layer is different from that of the first lower electrode layer, and the first, second, and third lower electrode layers contain a common metallic element.

[0018] In one embodiment, the ratio of the thickness of the first lower electrode layer to the thickness of the second lower electrode layer is 0.5-0.8.

[0019] In one embodiment, the substrate further comprises spaced-apart capacitor contact structures, with capacitor holes exposing the top surface of the capacitor contact structures, and the capacitor contact structures are electrically connected to the first lower electrode layer.

[0020] In one embodiment, the semiconductor structure further includes: a dielectric layer covering the lower electrode and the support structure, and an upper electrode covering the dielectric layer.

[0021] According to another aspect of this disclosure, a method for fabricating the above-described semiconductor structure is provided, comprising:

[0022] Provide substrate;

[0023] A multilayer structure is formed on the substrate;

[0024] Etch the stacked structure to form capacitor holes;

[0025] A first lower electrode layer, a second lower electrode layer, and a third lower electrode layer are formed within the capacitor aperture. The first lower electrode layer, the second lower electrode layer, and the third lower electrode layer constitute the lower electrode. The first lower electrode layer covers the bottom and sidewalls of the capacitor aperture. The second lower electrode layer is conformal to the first lower electrode layer and forms a cavity. The third lower electrode layer fills the cavity. The work function of the second lower electrode layer is greater than that of the first lower electrode layer and is also greater than that of the third lower electrode layer.

[0026] In one embodiment, forming a stacked structure on a substrate and etching the stacked structure to form a capacitor via includes:

[0027] A stacked structure is formed on a substrate, the stacked structure including at least a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer, and a third support layer;

[0028] The stacked structure is etched along a direction perpendicular to the substrate to expose the substrate and form capacitor holes.

[0029] In one embodiment, a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer are formed within a capacitor aperture. The first lower electrode layer covers the bottom and sidewalls of the capacitor aperture. The second lower electrode layer is conformal to the first lower electrode layer and forms a cavity. The third lower electrode layer fills the cavity.

[0030] A first lower electrode material layer is formed, which covers the bottom and sidewalls of the capacitor hole and the upper surface of the stacked structure.

[0031] A second lower electrode material layer is formed, which is conformal to the first lower electrode material layer, and the second lower electrode material layer forms a cavity in the capacitor hole;

[0032] A third lower electrode material layer is formed, which fills the cavity and covers the top of the second lower electrode material layer.

[0033] The third lower electrode material layer, the second lower electrode material layer, and the first lower electrode material layer are etched to expose the third support layer. The remaining first lower electrode material layer, second lower electrode material layer, and third lower electrode material layer are defined as the first lower electrode layer, the second lower electrode layer, and the third lower electrode layer, respectively.

[0034] In one embodiment, the method further includes:

[0035] A first opening is formed in the third support layer, and the first opening exposes the second sacrificial layer;

[0036] Remove the second sacrificial layer to expose the second support layer;

[0037] The second support layer is etched to form a second opening, which exposes the first sacrificial layer.

[0038] Remove the first sacrificial layer to expose the first support layer. The remaining first support layer, second support layer, and third support layer are defined as the support structure.

[0039] In one embodiment, the etching selectivity ratio of the first sacrificial layer and the first lower electrode layer is greater than or equal to 5, and the etching selectivity ratio of the second sacrificial layer and the first lower electrode layer is greater than or equal to 5.

[0040] In one embodiment, the third support layer includes a third upper support layer and a third lower support layer, and during the formation of the second opening, the third upper support layer and a portion of the lower electrode layer are also etched away.

[0041] In one embodiment, the method further includes:

[0042] A dielectric layer is formed on the exposed surfaces of the lower electrode and the support structure;

[0043] An upper electrode is formed on the surface of the dielectric layer.

[0044] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0046] Figure 1 is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0047] Figure 2 shows a flowchart of the steps of the method for fabricating a semiconductor structure provided in an embodiment of this disclosure;

[0048] Figures 3-10 are schematic cross-sectional views of the semiconductor structure formation process in some embodiments of this disclosure; Detailed Implementation

[0049] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0050] As DRAM feature sizes continue to shrink, the leakage effect of capacitor structures becomes increasingly apparent when feature sizes are reduced to below a certain value. Improving the leakage effect of capacitor structures while reducing the additional side effects has become an urgent technical problem to be solved.

[0051] In view of this, the present disclosure provides a semiconductor structure, including: a substrate; a support structure located above the substrate and spaced-apart capacitor holes penetrating the support structure; and a lower electrode located within the capacitor holes, wherein the lower electrode includes a first lower electrode layer, a second lower electrode layer, and a third lower electrode layer. The first lower electrode layer covers the bottom and sidewalls of the capacitor holes, the second lower electrode layer conforms to the first lower electrode layer and forms a cavity, and the third lower electrode layer fills the cavity. The work function of the second lower electrode layer is greater than that of the first lower electrode layer and is also greater than that of the third lower electrode layer. The semiconductor structure has a columnar capacitor structure. By setting three lower electrode layers, the leakage effect of the columnar capacitor structure is improved, damage to the second lower electrode layer during the process steps is avoided, and the resistance of the columnar capacitor structure is reduced.

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] Figure 1 is a cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0054] Referring to FIG1, in one embodiment, the semiconductor structure 100 includes:

[0055] Substrate 110; in practice, substrate 110 may include, but is not limited to, elemental semiconductor material substrates (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), composite semiconductor material substrates (e.g., silicon-germanium (SiGe) substrates, etc.), or silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, etc. The substrate may be doped or undoped, or may contain both doped and undoped regions. Furthermore, the material of substrate 110 may include, but is not limited to, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0056] A support structure 210 and spaced-apart capacitor holes 183 are located above the substrate 110, with the capacitor holes 183 penetrating the support structure 210. The support structure 210 includes a first support layer 120, a second support layer 140, and a third lower support layer 161. The materials of the first support layer 120, the second support layer 140, and the third lower support layer 161 include, but are not limited to, nitrides. The materials of the first support layer 120, the second support layer 140, and the third lower support layer 161 can be the same or different. Specifically, the material of the first support layer 120 can be a boron-containing insulating material, such as SiBN, because boron doping can reduce the hardness of the material, resulting in a better morphology of the capacitor holes 183 formed, for example, by etching. The material of the second support layer 140 can be a carbide-containing insulating material, such as SiCN, because SiCN has good hardness and can provide good support for the lower electrode 270. The material of the third lower support layer 161 can be an nitrogen-containing insulating material, such as silicon nitride.

[0057] The lower electrode 270 is located within the capacitor hole 183. The lower electrode 270 includes a first lower electrode layer 271, a second lower electrode layer 272, and a third lower electrode layer 273. The first lower electrode layer 271 covers the bottom and sidewalls of the capacitor hole 183. The second lower electrode layer 272 is conformal to the first lower electrode layer 271 and forms a cavity. The third lower electrode layer 273 fills the cavity. The work function of the second lower electrode layer 272 is greater than that of the first lower electrode layer 271 and is also greater than that of the third lower electrode layer 273.

[0058] The work function is an important concept in solid-state physics, describing the minimum energy required for an electron to escape from the interior of a solid into a vacuum. The work function is usually represented by the symbol φ, and its unit is electron volt (eV). On a metal surface, the work function determines the work function of electrons escaping from the metal surface; that is, the energy barrier an electron needs to overcome to move from the interior of the metal to a vacuum. A lower work function means that electrons escape more easily, while a higher work function means that electrons are more difficult to leave the metal surface. The leakage current of a capacitor structure is directly related to the work function of the electrode material. The higher the work function of the electrode material, the smaller the leakage current of the capacitor structure; conversely, electrode materials with low work functions lead to poorer leakage characteristics in the capacitor structure. In a semiconductor structure with a columnar capacitor structure, by setting the lower electrode 270 as a three-layer structure, and setting the work function of the second lower electrode layer 272 to be greater than that of the first lower electrode layer 271 and also greater than that of the third lower electrode layer 273, the leakage current effect of the columnar capacitor structure is improved.

[0059] In one embodiment, the oxygen content of the second lower electrode layer 272 is greater than that of the first lower electrode layer 271, and also greater than that of the third lower electrode layer 273. That is, doping with oxygen can improve the work function of the electrode material; for example, the second lower electrode layer 272 can be TiON; the first lower electrode layer can be TiN or TiSiN, preferably TiSiN; and the third electrode layer 273 can be TiN. In other words, the oxygen content in the material of the second lower electrode layer 272 is greater than that in the material of the first lower electrode layer 271, and also greater than that in the material of the third lower electrode layer 273.

[0060] In one embodiment, the oxygen content of the second lower electrode layer 272 gradually increases or gradients along the direction from the center to the edge of the capacitor hole. Preferably, the first lower electrode layer 271 can be TiSiN; the third electrode layer 273 can be TiN. TiSiN has higher oxygen resistance than TiN, meaning oxygen atoms do not easily penetrate into the first lower electrode layer. Therefore, to ensure a high work function of the second lower electrode layer 272, the oxygen content of the second lower electrode layer 272 can be gradually increased or gradients along the direction from the center to the edge of the capacitor hole. This reduces the penetration of oxygen atoms into the third lower electrode layer, thus preventing an increase in the resistance of the third lower electrode layer, while maintaining the high work function of the second lower electrode layer 272.

[0061] In one embodiment, the conductivity of the third lower electrode layer 273 is greater than that of the second lower electrode layer 272, and greater than or equal to that of the first lower electrode layer 271. Since the second lower electrode layer 272 achieves a high work function through oxygen doping, its resistivity also increases accordingly. Therefore, providing a third lower electrode layer 273 with lower resistivity can improve the overall resistance characteristics of the lower electrode 270, thereby reducing the overall resistance of the lower electrode 270. Furthermore, the content of the (111) crystal plane in the material of the third lower electrode layer 273 can be greater than 50%. The (111) crystal plane of TiN has a high work function, thus the leakage current of the capacitor structure can be reduced through the crystal plane characteristics of the third lower electrode layer 273.

[0062] In one embodiment, the material of the third lower electrode layer 273 is different from that of the first lower electrode layer 271, and the first lower electrode layer 271, the second lower electrode layer 272, and the third lower electrode layer 273 contain a common metal element. Preferably, the first lower electrode layer 271 can be TiSiN; the second lower electrode layer 272 can be TiON; and the third electrode layer 273 can be TiN. The fact that the first lower electrode layer 271, the second lower electrode layer 272, and the third lower electrode layer 273 contain a common metal element can improve the adhesion between the electrode layers, and also improve the conformal capability between the second lower electrode layer 272 and the first lower electrode layer 271, thereby reducing the contact resistance between the electrode layers and reducing the overall resistance of the lower electrode.

[0063] In one embodiment, the thickness ratio of the first lower electrode layer 271 to the thickness ratio of the second lower electrode layer 272 is 0.5-0.8. The first lower electrode layer 271 serves as a protective layer for the second lower electrode layer 272, reducing damage to the first lower electrode layer 271 during the manufacturing process. Therefore, the thickness ratio of the first lower electrode layer 271 to the second lower electrode layer 272 cannot be too large or too small. If it is too large, the resistance of the first lower electrode layer 271 will increase; if it is too small, it will not effectively protect the second lower electrode layer 272.

[0064] In one embodiment, the substrate 110 includes a doped or undoped silicon substrate 111, spaced-apart capacitor contact structures 112 above the silicon substrate 111, and an insulating layer 113 isolating the capacitor contact structures 112. A capacitor via 183 exposes the top surface of the capacitor contact structures 112, which are electrically connected to the first lower electrode layer 271. The capacitor contact structures 112 may also include metal silicides, such as titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi). The interface between the metal silicide and the silicon substrate 111 forms good electrical contact, reducing contact resistance. Furthermore, the resistivity of the metal silicide is much lower than that of the silicon substrate 111, which helps reduce the resistance of the capacitor contact structures 112, thereby reducing power consumption and increasing circuit speed. The insulating layer 113 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. In this embodiment, the insulating layer 113 is made of silicon nitride. Thus, the insulating layer 113 and the first support layer 120 have similar materials, which can improve the contact effect between the two.

[0065] In one embodiment, the semiconductor structure 100 further includes a dielectric layer 191 covering the lower electrode 270 and the support structure 210, and an upper electrode 192 covering the dielectric layer 191. In practice, the material of the dielectric layer 191 includes, but is not limited to, aluminum oxide, hafnium oxide, silicon oxide, zirconium oxide, or combinations thereof. The material of the upper electrode 192 includes, but is not limited to, titanium (Ti), titanium nitride (TiN), or tungsten (W). The lower electrode 270, the dielectric layer 191, and the upper electrode 192 together form a complete columnar capacitor structure.

[0066] The semiconductor structure disclosed herein improves the work function of the second lower electrode layer of the columnar capacitor structure, thereby improving the leakage current performance of the columnar capacitor structure. In order to prevent damage to the second lower electrode layer during the semiconductor structure formation process, a first lower electrode layer is used to protect the second lower electrode layer. In addition, in order to balance the resistance of the lower electrode, a third electrode layer with lower resistivity is used to reduce the overall resistance of the lower electrode.

[0067] Based on the above embodiments, this disclosure also provides a method for fabricating a semiconductor structure (hereinafter referred to as the fabrication method), which is used to fabricate the above-mentioned semiconductor structure 100. The fabrication method will be described in detail below.

[0068] Figure 2 shows a flowchart of the steps of the method for fabricating a semiconductor structure provided in an embodiment of this disclosure;

[0069] Figures 3-10 are schematic cross-sectional views of the semiconductor structure formation process in some embodiments of this disclosure;

[0070] Referring to Figure 2, the method for fabricating the semiconductor structure includes:

[0071] S100, referring to FIG3, a substrate 110 is provided; the substrate 110 includes, but is not limited to, a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. The substrate may be doped or undoped, or may contain both doped and undoped regions. In addition, the material of the substrate 110 may include, but is not limited to, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additionally, the substrate 110 includes a doped or undoped silicon substrate 111, spaced-apart capacitor contact structures 112 above the silicon substrate 111, and an insulating layer 113 isolating the capacitor contact structures 112. The capacitor contact structures 112 may also include metal silicides, such as titanium silicide (TiSi2), cobalt silicide (CoSi2), and nickel silicide (NiSi). The interface between the metal silicide and the silicon substrate 111 can form good electrical contact, reducing contact resistance. Furthermore, the resistivity of the metal silicide is much lower than that of the silicon substrate 111, which helps reduce the resistance of the capacitor contact structures 112, thereby reducing power consumption and increasing circuit speed. The insulating layer 113 can be made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbonitride. In this embodiment, the insulating layer 113 is made of silicon nitride. Thus, the insulating layer 113 and the first support layer 120 have similar materials, which can improve the contact effect between them.

[0072] S200, as shown in FIG3, a stacked structure 11 is formed on the substrate 110;

[0073] S300, as shown in FIG4, the stacked structure 11 is etched to form a capacitor hole 183, the capacitor hole 183 exposing the top surface of the capacitor contact structure 112.

[0074] S400, referring to Figures 5-6, a first lower electrode layer 271, a second lower electrode layer 272, and a third lower electrode layer 273 are formed within the capacitor hole 183. The first lower electrode layer, the second lower electrode layer, and the third lower electrode layer constitute the lower electrode. The first lower electrode layer 271 covers the bottom and sidewalls of the capacitor hole 183. The second lower electrode layer 272 is conformal to the first lower electrode layer 271 and forms a cavity. The third lower electrode layer 273 fills the cavity. The work function of the second lower electrode layer 272 is greater than that of the first lower electrode layer 271 and is also greater than that of the third lower electrode layer 273.

[0075] Referring to Figures 3-4, in one embodiment, a stacked structure 11 is formed on a substrate 110, and the stacked structure 11 is etched to form a capacitor hole 183, including:

[0076] A stacked structure 11 is formed on a substrate 110. The stacked structure 11 includes at least a first support layer 120, a first sacrificial layer 130, a second support layer 140, a second sacrificial layer 150, and a third support layer 160.

[0077] The stacked structure 11 is etched along a direction perpendicular to the substrate 110 to expose the substrate 110 and form a capacitor hole 183.

[0078] In practice, the first support layer 120, the first sacrificial layer 130, the second support layer 140, the second sacrificial layer 150, and the third support layer 160 can be formed using one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The etching of the stacked structure 11 to form the capacitor hole 183 can be performed using anisotropic etching, such as plasma etching. The materials of the first support layer 120, the second support layer 140, and the third support layer 160 include, but are not limited to, nitrides. The materials of the first support layer 120, the second support layer 140, and the third support layer 160 can be the same or different. Specifically, the material of the first support layer 120 can be a boron-containing insulating material, such as SiBN. Because doping with boron reduces the hardness of the material, the morphology of the capacitor hole 183 formed by etching, for example, is better. The material of the second support layer 140 can be a carbon-containing insulating material, such as SiCN. Because SiCN has good hardness, it can provide good support for the lower electrode 270. The material of the third support layer 160 can be an insulating material containing nitrogen, such as silicon nitride and / or silicon oxynitride. The materials of the first sacrificial layer 130 and the second sacrificial layer 150 can be silicon oxide or boron-doped silicon oxide, etc.

[0079] Referring to Figures 5-6, in one embodiment, a first lower electrode layer 271, a second lower electrode layer 272, and a third lower electrode layer 273 are formed within the capacitor hole 183. The first lower electrode layer 271 covers the bottom and sidewalls of the capacitor hole 183. The second lower electrode layer 272 is conformal to the first lower electrode layer 271 and forms a cavity. The third lower electrode layer 273 fills the cavity.

[0080] A first lower electrode material layer 171 is formed, which covers the bottom and sidewalls of the capacitor hole 183 and the upper surface of the stacked structure 11.

[0081] A second lower electrode material layer 172 is formed, which is conformal to the first lower electrode material layer 171, and the second lower electrode material layer 172 forms a cavity in the capacitor hole 183.

[0082] A third lower electrode material layer 173 is formed, which fills the cavity and covers the top of the second lower electrode material layer 172;

[0083] The third lower electrode material layer 173, the second lower electrode material layer 172, and the first lower electrode material layer 171 are etched to expose the third support layer 160. The remaining first lower electrode material layer 171, second lower electrode material layer 172, and third lower electrode material layer 173 are respectively defined as the first lower electrode layer 271, the second lower electrode layer 272, and the third lower electrode layer 273.

[0084] In one embodiment, atomic layer deposition (ALD) is used to deposit a first lower electrode material layer 171, a second lower electrode material layer 172, and a third lower electrode material layer 173, respectively. ALD (Atomic Layer Deposition) is an advanced thin film deposition technique that grows thin films layer by layer through precisely controlled chemical reactions. During ALD, two or more chemical precursors are used alternately, each reacting only with the substrate surface in a self-limiting manner to form a monolayer atomic film. These precursors are typically introduced into the reaction chamber in a pulsed manner and purge with an inert gas between each pulse to ensure complete reaction and removal of the precursors and avoid gas-phase reactions between different precursors. The advantages of ALD technology include extremely high precision in thin film thickness control, excellent thin film uniformity, and the ability to cover complex geometries; therefore, ALD deposition of electrode material layers yields excellent results. For example, a first lower electrode material layer 171 is deposited using TiCl4 (titanium tetrachloride), NH3 (ammonia), DCS (dichlorosilane, SiH2Cl2), SiH4 (silane) or TiCl4 (titanium tetrachloride) and NH3 (ammonia) as the reactive gas; a second lower electrode material layer 172 is deposited using TiCl4 (titanium tetrachloride), NH3 (ammonia), O2 (oxygen), and O3 (ozone) as the reactive gas; and a third lower electrode material layer 173 is deposited using TiCl4 (titanium tetrachloride) and NH3 (ammonia) as the reactive gas.

[0085] In one embodiment, the oxygen content of the second lower electrode material layer 172 is greater than that of the first lower electrode material layer 171, and also greater than that of the third lower electrode material layer 173. That is, doping with oxygen can improve the work function of the electrode material; for example, the second lower electrode material layer 172 can be TiON; the first lower electrode material layer 171 can be TiN or TiSiN, preferably TiSiN; and the third electrode material layer 173 can be TiN. In other words, the oxygen content in the material of the second lower electrode material layer 172 is greater than that in the material of the first lower electrode material layer 171, and also greater than that in the material of the third lower electrode material layer 173.

[0086] In one embodiment, the oxygen content of the second lower electrode material layer 172 gradually increases or gradients along the direction from the center to the edge of the capacitor aperture. Preferably, the first lower electrode material layer 171 can be TiSiN; the third electrode material layer 173 can be TiN. TiSiN has higher oxygen resistance than TiN, meaning oxygen atoms do not easily penetrate into the first lower electrode material layer. Therefore, to ensure a high work function of the second lower electrode material layer 172, the oxygen content of the second lower electrode material layer 172 can be gradually increased or gradients along the direction from the center to the edge of the capacitor aperture. This reduces the penetration of oxygen atoms into the third lower electrode material layer, thus preventing an increase in the resistance of the third lower electrode material layer, while maintaining a high work function of the second lower electrode material layer 172. Alternatively, the oxygen content of the second lower electrode material layer 172 can be adjusted by regulating the amount of oxygen introduced during atomic layer deposition (ALD), thereby obtaining a second lower electrode material layer 172 with a gradually increasing or gradient oxygen content along the direction from the center to the edge of the capacitor aperture.

[0087] In one embodiment, the conductivity of the third lower electrode material layer 173 is greater than that of the second lower electrode material layer 172, and greater than or equal to that of the first lower electrode material layer 171. Since the second lower electrode material layer 172 achieves a high work function through oxygen doping, its resistivity also increases accordingly. Therefore, providing a third lower electrode material layer 173 with lower resistivity can improve the overall resistance characteristics of the lower electrode 270, thereby reducing the overall resistance of the lower electrode 270. Furthermore, the content of the (111) crystal plane in the third lower electrode material layer 173 can be greater than 50%. The (111) crystal plane of TiN has a high work function, thus the leakage current of the capacitor structure can be reduced through the crystal plane characteristics of the third lower electrode material layer 173.

[0088] In one embodiment, the thickness ratio of the first lower electrode material layer 171 to the thickness ratio of the second lower electrode material layer 172 is 0.5-0.8. The first lower electrode material layer 171 serves as a protective layer for the second lower electrode material layer 172, reducing damage to the first lower electrode material layer 171 during the manufacturing process. Therefore, the thickness ratio of the first lower electrode material layer 171 to the second lower electrode material layer 172 cannot be too large or too small. If it is too large, the resistance of the first lower electrode material layer 171 will increase; if it is too small, it will not effectively protect the second lower electrode material layer 172.

[0089] Referring to Figures 7-10, in one embodiment, the method further includes:

[0090] A first opening 181 is formed on the third support layer 160, exposing the second sacrificial layer 150. For example, photoresist is deposited on the third support layer 160 using photolithography or electron beam lithography, and the desired opening pattern is formed by exposure and development. The exposed third support layer 160 is removed using dry etching (such as reactive ion etching-RIE or plasma-enhanced chemical vapor deposition-PECVD) to form the first opening 181. After etching, a cleaning step is used to remove residual photoresist and etching byproducts to ensure surface cleanliness.

[0091] Remove the second sacrificial layer 150 to expose the second support layer 140; in this step, a wet etching process is used to remove the second sacrificial layer 150.

[0092] The second support layer 140 is etched to form a second opening 182, which exposes the first sacrificial layer 130. During the formation of the second opening 182, dry etching (such as reactive ion etching-RIE or plasma enhanced chemical vapor deposition-PECVD) is used to remove the exposed second support layer 140.

[0093] The first sacrificial layer 130 is removed, exposing the first support layer 120. The remaining first, second, and third support layers are defined as the support structure 210. In this step, a wet etching process is used to remove the first sacrificial layer 130.

[0094] Referring to Figures 7-10, in one embodiment, the etching selectivity ratio between the first sacrificial layer 130 and the first lower electrode layer 271 is greater than or equal to 5, and the etching selectivity ratio between the second sacrificial layer 150 and the first lower electrode layer 271 is also greater than or equal to 5. That is, during the removal of the first sacrificial layer 130 or the second sacrificial layer 150, ammonium bifluoride or ammonium fluoride is commonly used for wet etching. Because the first sacrificial layer 130 or the second sacrificial layer 150 has a high etching selectivity ratio with the first lower electrode layer 271, the first lower electrode layer 271 will not experience significant etching during the etching of the sacrificial layer. This protects the second lower electrode layer from damage by the etching solution, improving the overall performance of the lower electrode.

[0095] Referring to Figures 7-10, in one embodiment, the third support layer 160 includes a third upper support layer 162 and a third lower support layer 161. During the formation of the second opening 182, the third upper support layer 162 and a portion of the lower electrode layer are also etched away. During the removal of the second sacrificial layer 150, the top of the second lower electrode layer 272 may be damaged. By removing the damaged second lower electrode layer 272 and the third upper support layer 162 during the formation of the second opening 182, the complete lower electrode 270 structure is preserved. The third upper support layer 162 may be made of SiON, and the third lower support layer 161 may be made of SiN.

[0096] Referring to FIG1, in one embodiment, the method further includes: forming a dielectric layer 191 on the exposed surfaces of the lower electrode 270 and the support structure 210; and forming an upper electrode 192 on the surface of the dielectric layer 191. In practice, the dielectric layer 191 is deposited using atomic layer deposition (ALD), and the material of the dielectric layer 191 includes, but is not limited to, alumina, hafnium oxide, silicon oxide, zirconium oxide, or combinations thereof. The material of the upper electrode 192 includes, but is not limited to, titanium (Ti), titanium nitride (TiN), or tungsten (W). The deposition method of the upper electrode can be physical vapor deposition (PVD, such as sputtering or evaporation), chemical vapor deposition (CVD, such as atmospheric pressure CVD, low pressure CVD, or plasma-enhanced CVD), or atomic layer deposition (ALD). The lower electrode 270, the dielectric layer 191, and the upper electrode 192 together form a complete columnar capacitor structure.

[0097] By employing the aforementioned fabrication method, a second lower electrode layer with a high work function was selected, improving the leakage current performance of the columnar capacitor structure. Furthermore, during the removal of the sacrificial layer, a first lower electrode layer was used to protect the second lower electrode layer from the side. Simultaneously, two third upper and lower support layers of different materials were fabricated, allowing for the selective removal of the third upper support layer and part of the lower electrode, resulting in an excellent bottom electrode morphology. This approach improves the leakage current performance of the semiconductor structure while ensuring the overall resistance requirements of the semiconductor structure are met.

[0098] In the description of this disclosure, it should be understood that the terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0099] In the description of this disclosure, it should be understood that the terms “comprising” and “having” as used herein, and any variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units that are expressly listed, but may include other steps or units that are not expressly listed or that are inherent to such process, method, product, or apparatus.

[0100] Unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can be a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this invention.

Claims

1. A semiconductor structure (100) comprising: a substrate (110) ; a support structure (210) and a plurality of spaced-apart capacitor holes (183) above the substrate (110), the capacitor holes (183) penetrating the support structure (210) ; a lower electrode (270) in the capacitor holes (183), wherein the lower electrode (270) comprises a first lower electrode layer (271), a second lower electrode layer (272) and a third lower electrode layer (273), the first lower electrode layer (271) covers a bottom and sidewalls of the capacitor holes (183), the second lower electrode layer (272) is conformal to the first lower electrode layer (271) and forms a cavity, and the third lower electrode layer (273) fills the cavity, wherein a work function of the second lower electrode layer (272) is greater than a work function of the first lower electrode layer (271) and greater than a work function of the third lower electrode layer (273) ; an oxygen content of the second lower electrode layer (272) is greater than an oxygen content of the first lower electrode layer (271) and greater than an oxygen content of the third lower electrode layer (273) ; the oxygen content of the second lower electrode layer (272) gradually increases or gradiently increases from a center to an edge of the capacitor hole (183) ; an electrical conductivity of the third lower electrode layer (273) is greater than an electrical conductivity of the second lower electrode layer (272) and greater than or equal to an electrical conductivity of the first lower electrode layer (271) ; a material of the third lower electrode layer (273) is different from a material of the first lower electrode layer (271), and the first lower electrode layer (271), the second lower electrode layer (272) and the third lower electrode layer (273) contain a common metal element; a thickness ratio of the first lower electrode layer (271) to the second lower electrode layer (272) is 0.5-0.8; the substrate (110) is further provided with a plurality of spaced-apart capacitor contact structures (112), the capacitor holes (183) expose top surfaces of the capacitor contact structures (112), and the capacitor contact structures (112) are electrically connected to the first lower electrode layer (271) ; the semiconductor structure further comprises a dielectric layer (191) covering the lower electrode (270) and the support structure (210), and an upper electrode (192) covering the dielectric layer (191) ; wherein the semiconductor structure is manufactured by: providing a substrate (110) ; forming a stack structure (11) on the substrate (110) ; etching the stack structure (11) to form capacitor holes (183) ; and forming a lower electrode (270) in the capacitor holes (183). ​ ​ ​ ​ 2. The semiconductor structure of claim 1, wherein, ​ 3. The semiconductor structure of claim 2, wherein, ​ 4. The semiconductor structure of claim 1, wherein, ​ 5. The semiconductor structure of claim 4, wherein, ​ 6. The semiconductor structure of claim 1, wherein, ​ 7. The semiconductor structure of claim 1, wherein, ​ 8. The semiconductor structure of claim 1, wherein, ​ 9. A method of manufacturing a semiconductor structure (100), ​ ​ ​ ​ ​ A first lower electrode layer (271), a second lower electrode layer (272) and a third lower electrode layer (273) are formed in the capacitor hole (183), the first lower electrode layer (271), the second lower electrode layer (272) and the third lower electrode layer (273) constitute a lower electrode (270), the first lower electrode layer (271) covers the bottom and the sidewall of the capacitor hole (183), the second lower electrode layer (272) is conformal to the first lower electrode layer (271) and forms a cavity, and the third lower electrode layer (273) fills the cavity; wherein the work function of the second lower electrode layer (272) is greater than the work function of the first lower electrode layer (271) and greater than the work function of the third lower electrode (273).

10. The method of claim 1, wherein, forming a stack structure (11) on the substrate (110), and etching the stack structure (11) to form the capacitor hole (183), comprises: forming the stack structure (11) on the substrate (110), the stack structure (11) comprising at least a first support layer (120), a first sacrificial layer (130), a second support layer (140), a second sacrificial layer (150), a third support layer (160); etching the stack structure (11) in a direction perpendicular to the substrate (110) to expose the substrate (110) and form the capacitor hole (183).

11. The method of claim 10, wherein, forming a first lower electrode layer (271), a second lower electrode layer (272) and a third lower electrode layer (273) in the capacitor hole (183), the first lower electrode layer (271) covering the bottom and the sidewall of the capacitor hole (183), the second lower electrode layer (272) being conformal to the first lower electrode layer (271) and forming a cavity, and the third lower electrode layer (273) filling the cavity, comprises: forming a first lower electrode material layer (171) covering the bottom and the sidewall of the capacitor hole (183) and the upper surface of the stack structure (11); forming a second lower electrode material layer (172) conformal to the first lower electrode material layer (171), and the second lower electrode material layer (172) forming a cavity in the capacitor hole (183); forming a third lower electrode material layer (173) filling the cavity and covering the top of the second lower electrode material layer (172); etching the third lower electrode material layer (173), the second lower electrode material layer (172) and the first lower electrode material layer (171) to expose the third support layer (160), and the remaining first lower electrode material layer, the second lower electrode material layer and the third lower electrode material layer define the first lower electrode layer (271), the second lower electrode layer (272) and the third lower electrode layer (273), respectively. ​ 12. The method of claim 10, wherein, the method further comprises: forming a first opening (181) on the third support layer (160), the first opening (181) exposing the second sacrificial layer (150); removing the second sacrificial layer (150) to expose the second support layer (140); etching the second support layer (140) to form a second opening (182), the second opening (182) exposing the first sacrificial layer (130); removing the first sacrificial layer (130) to expose the first support layer (120), the remaining first, second and third support layers defining a support structure (210).

13. The method of manufacturing a semiconductor structure according to claim 12, wherein, an etching selectivity ratio of the first sacrificial layer (130) and the first lower electrode layer (271) is greater than or equal to 5, and an etching selectivity ratio of the second sacrificial layer (150) and the first lower electrode layer (271) is greater than or equal to 5.

14. The method of manufacturing a semiconductor structure according to claim 12, wherein, the third support layer (160) comprises a third upper support layer (162) and a third lower support layer (161), and during forming the second opening (182), the third upper support layer (162) and part of the lower electrode (270) are also etched and removed.

15. The method of manufacturing a semiconductor structure according to claim 9, wherein, the method further comprises: forming a dielectric layer (191) on the exposed surface of the lower electrode (270) and the support structure (210); forming an upper electrode (192) on the surface of the dielectric layer (191).

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