Ferroelectric transistor cell supporting index-free sparse training, and in-memory computing hardware

Abstract

Disclosed in the present application are a ferroelectric transistor cell supporting index-free sparse training, and in-memory computing hardware. The ferroelectric transistor cell comprises: a first non-volatile transistor, which comprises a first source electrode, a first drain electrode and a first gate electrode; a second non-volatile transistor, which comprises a second source electrode, a second drain electrode and a second gate electrode; a sparsity line, which is connected to the first gate electrode; a bit line, which is connected to the first source electrode; a data input line, which is connected to the second source electrode; and a data output line, which is connected to the second drain electrode, wherein the first drain electrode is connected to the second gate electrode, the first non-volatile transistor is used for controlling, on the basis of a signal of the sparsity line, the turning on / off of the second non-volatile transistor, and the second non-volatile transistor is used for weight update and data processing and storage. The present application realizes the in-situ storage of sparsity information, enabling the sparsity information to participate in a sparse training process together with weight information, thereby eliminating an external indexing process, and supporting sparse training involving any unstructured and any coarse-grained or fine-grained pruning, and thus realizing theoretical advantages in energy consumption and latency.

Description

Ferroelectric transistor cell supporting index-free sparse training and in-memory hardware

[0001] The present application claims priority to the Chinese patent application No. 2024109552186, filed on July 16, 2024, with the Chinese Patent Office, and entitled “Ferroelectric transistor cell supporting index-free sparse training and in-memory hardware”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of ferroelectric transistor technology, in particular to a ferroelectric transistor cell supporting index-free sparse training and in-memory hardware. BACKGROUND

[0003] With the rapid development of artificial intelligence (AI), the scale of neural networks has also grown exponentially. Model compression techniques, represented by sparse neural networks, have received unprecedented attention. The idea of sparse neural networks is to prune the weights with small values in dense neural networks, so that they do not participate in training and inference, thereby directly improving the speed of computation and power consumption.

[0004] However, the ideal advantages of sparse neural networks have not been realized, because modern AI hardware relies on indexing of off-chip memory to complete pruning. During the indexing process, sparse information is loaded from off-chip memory to on-chip cache in the form of low-precision matrix, and is repeatedly refreshed and read in the subsequent weight update. In actual neural networks, zero weights are often randomly distributed without rules, which corresponds to unstructured, element-wise pruning with the finest granularity, which greatly increases the overhead of indexing.

[0005] To reduce the access of off-chip memory and avoid large indexing overhead, the current mainstream solution is to increase the pruning granularity, from fine-grained pruning to coarser vector-wise pruning and block-wise pruning. However, coarse-grained pruning greatly reduces latency and energy consumption, but also inevitably prunes some important weights, resulting in a decline in accuracy. This is the accuracy-granularity dilemma faced by sparse neural networks. Coarse-grained pruning damages accuracy, while fine-grained pruning damages energy consumption and latency, which greatly weakens the potential advantages of sparse neural networks and has not been solved yet. SUMMARY

[0006] The purpose of the present application is to provide a ferroelectric transistor unit supporting index-free sparse training and a compute-in-memory hardware to solve the technical problem that the existing technology relies on an index of an off-chip memory to complete pruning, and that a coarse-grained pruning damages precision while a fine-grained pruning damages energy consumption and latency, greatly weakening the potential advantages of a sparse neural network.

[0007] To achieve the above-mentioned purpose, the first aspect of the present application provides a ferroelectric transistor unit supporting index-free sparse training, comprising:

[0008] A first non-volatile transistor comprising a first source, a first drain and a first gate;

[0009] A second non-volatile transistor comprising a second source, a second drain and a second gate;

[0010] A sparse line connected with the first gate;

[0011] A bit line connected with the first source;

[0012] A data input line connected with the second source;

[0013] A data output line connected with the second drain;

[0014] The first drain and the second gate are connected, the first non-volatile transistor is configured to control the switching of the second non-volatile transistor based on the signal of the sparse line, and the second non-volatile transistor is configured to perform weight update and data processing storage.

[0015] In one or more embodiments, the ferroelectric transistor unit comprises a substrate, an isolation layer, a ferroelectric layer and a dielectric layer arranged in sequence;

[0016] The first source, the first drain, the second source, the second drain, the sparse line, the bit line, the data input line and the data output line are arranged on the side of the dielectric layer away from the ferroelectric layer or on the side of the substrate facing the isolation layer.

[0017] In one or more embodiments, the first source, the first drain, the second source, the second drain, the data input line and the bit line are arranged on the side of the dielectric layer away from the ferroelectric layer;

[0018] The sparse line and the data output line are arranged on the side of the substrate facing the isolation layer;

[0019] The second drain is connected with the data output line through a first connecting column penetrating through the dielectric layer, the ferroelectric layer and the isolation layer.

[0020] In one or more embodiments, the first nonvolatile transistor further comprises a first channel, the first channel being arranged between the first source and the first drain;

[0021] The second nonvolatile transistor further comprises a second channel, the second channel being arranged between the second source and the second drain.

[0022] In one or more embodiments, the first nonvolatile transistor further comprises a first floating gate, the first floating gate being arranged on a side of the ferroelectric layer facing the dielectric layer, the first floating gate being connected to the first channel through the dielectric layer;

[0023] wherein the first gate is arranged on a side of the ferroelectric layer, and the first gate is connected to the first floating gate through the ferroelectric layer.

[0024] In one or more embodiments, the first gate is arranged on a side of the ferroelectric layer facing the dielectric layer, and the first gate is isolated from the first floating gate;

[0025] The first nonvolatile transistor further comprises a first back gate, the first back gate being arranged on a side of the ferroelectric layer facing away from the dielectric layer, and a projection of the first back gate at least partially overlaps a projection of the first floating gate, and a projection of the first back gate at least partially overlaps a projection of the first gate.

[0026] In one or more embodiments, the first gate is connected to the sparse line through a second connecting column penetrating the ferroelectric layer and the isolation layer.

[0027] In one or more embodiments, the second nonvolatile transistor further comprises a second floating gate, the second floating gate being arranged on a side of the ferroelectric layer facing the dielectric layer, and the second floating gate being connected to the second channel through the dielectric layer;

[0028] wherein the second gate is arranged on a side of the ferroelectric layer, and the second gate is connected to the second floating gate through the ferroelectric layer.

[0029] In one or more embodiments, the second gate is arranged on a side of the ferroelectric layer facing away from the dielectric layer, and a projection of the second gate at least partially overlaps a projection of the second floating gate.

[0030] In one or more embodiments, the second gate is connected to the first drain through a third connecting column penetrating the dielectric layer and the ferroelectric layer.

[0031] To achieve the above object, the second aspect of the present application provides a preparation method of a ferroelectric transistor unit supporting index-free sparse training, comprising:

[0032] Depositing metal on the substrate surface to prepare mutually spaced data output lines and sparse lines;

[0033] Depositing isolation material on the substrate surface to prepare an isolation layer;

[0034] Depositing metal on the surface of the isolation layer to prepare mutually spaced first back gate and second gate;

[0035] Growing ferroelectric material on the surface of the isolation layer to prepare a ferroelectric layer;

[0036] Depositing metal on the surface of the ferroelectric layer to prepare mutually spaced first floating gate, first gate and second floating gate, wherein at least part of the first floating gate overlaps the orthographic projection of the first back gate, at least part of the first gate overlaps the orthographic projection of the first back gate, at least part of the second floating gate overlaps the orthographic projection of the second gate, and the first gate is connected with the second connecting column;

[0037] Fast thermal annealing, followed by depositing dielectric material on the surface of the ferroelectric layer to obtain a dielectric layer;

[0038] Sequentially performing etching and depositing metal on the surface of the dielectric layer to obtain a third connecting column extending from the surface of the dielectric layer to the surface of the isolation layer and connected with the second gate, a first connecting column extending from the surface of the dielectric layer to the surface of the substrate and connected with the data output line, and a second connecting column connecting the first gate and the sparse line;

[0039] Preparing mutually spaced first channel and second channel on the surface of the dielectric layer, and depositing metal to obtain first source, first drain, first source, second drain, data input line and bit line;

[0040] High vacuum annealing to obtain the ferroelectric transistor unit;

[0041] Wherein, at least part of the first channel overlaps the orthographic projection of the first floating gate, at least part of the second channel overlaps the orthographic projection of the second floating gate, the data input line and the bit line are arranged mutually spaced, the first source and the first drain are connected through the first channel, the first source is connected with the bit line, the first drain is connected with the third connecting column, the second source and the second drain are connected through the second channel, the second source is connected with the data input line, and the second drain is connected with the first connecting column.

[0042] In one or more embodiments, the sparse lines and the data output lines are arranged in parallel and spaced apart, the bit lines and the data input lines are arranged in parallel and spaced apart, the sparse lines and the bit lines are distributed vertically, and the data output lines and the data input lines are distributed vertically.

[0043] In one or more embodiments, the first channel and the second channel are MoS2 channels, the first channel and the second channel are prepared on the surface of the dielectric layer, and the step of depositing metal includes:

[0044] transferring a monolayer of MoS2 to the surface of the dielectric layer through a metal film, and etching the metal film and MoS2 in a non-channel region;

[0045] depositing metal on the surface of the dielectric layer to obtain the first source, the first drain, the first source, the second drain, the data input line, and the bit line;

[0046] using the first source, the first drain, the first source, and the second drain as a mask to etch the metal film in a channel region to obtain the first channel and the second channel.

[0047] In one or more embodiments, the method of depositing metal specifically includes defining a deposition area by electron beam exposure, and then depositing a metal material by electron beam evaporation; and / or,

[0048] The method of depositing the isolation material and the dielectric material specifically includes depositing by a plasma-enhanced atomic layer deposition method.

[0049] To achieve the above-mentioned purpose, the third aspect of the present application provides a memory-computing integrated hardware, comprising a plurality of ferroelectric transistor units arranged in an array, or a plurality of ferroelectric transistor units prepared by the preparation method of any one of the above-mentioned embodiments.

[0050] In adjacent ferroelectric transistor units, adjacent sparse lines are connected as a whole, adjacent bit lines are connected as a whole, adjacent data input lines are connected as a whole, and adjacent data output lines are connected as a whole.

[0051] In one or more embodiments, in adjacent ferroelectric transistor units, adjacent sparse lines are parallel to each other, adjacent bit lines are parallel to each other, adjacent data input lines are parallel to each other, and adjacent data output lines are parallel to each other.

[0052] In one or more embodiments, in the ferroelectric transistor units, the sparse lines and the data output lines are arranged in parallel and spaced apart, the bit lines and the data input lines are arranged in parallel and spaced apart, the sparse lines and the bit lines are distributed vertically, and the data output lines and the data input lines are distributed vertically.

[0053] Compared with the prior art, the application has the following beneficial effects:

[0054] The ferroelectric transistor unit of the application includes two non-volatile transistors, wherein the drain of the first non-volatile transistor is connected with the gate of the second non-volatile transistor, and whether the first non-volatile transistor is turned on or not determines whether the training pulse can be transmitted to the second non-volatile transistor, and thus determines whether the weight is pruned, thereby realizing in-situ storage of sparsity information and enabling the sparsity information to participate in the sparse training process together with the weight information, completely eliminating the external indexing process, and supporting any unstructured, any fine-grained pruning sparse training; this new hardware design breaks the dilemma of "accuracy-granularity" of sparse neural networks, and realizes the great advantages of sparse neural networks in energy consumption and time delay. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0056] Fig. 1 is a structural schematic diagram of an embodiment of the storage-computing integrated hardware of the application;

[0057] Fig. 2 is a working principle schematic diagram of the ferroelectric transistor unit of the application;

[0058] Fig. 3 is a structural schematic diagram of an embodiment of the ferroelectric transistor unit of the application;

[0059] Fig. 4 is a perspective structural schematic diagram of an embodiment of the ferroelectric transistor unit of the application;

[0060] Fig. 5 is a three-dimensional structural schematic diagram of an embodiment of the first non-volatile transistor of the application;

[0061] Fig. 6 is a three-dimensional structural schematic diagram of an embodiment of the second non-volatile transistor of the application;

[0062] Fig. 7 is a preparation method of an embodiment of the ferroelectric transistor unit of the application;

[0063] Fig. 8 is a device state diagram corresponding to each step in Fig. 7.

[0064] In the drawings:

[0065] ferroelectric transistor unit 10; bit line 100; data input line 200; data output line 300; sparse line 400;

[0066] First nonvolatile transistor 500; first source 501; first drain 502; first gate 503; first channel 504; first floating gate 505; first back gate 506;

[0067] Second nonvolatile transistor 600; second source 601; second drain 602; second gate 603; second channel 604; second floating gate 605;

[0068] Substrate 700;

[0069] Isolation layer 800;

[0070] Ferroelectric layer 900;

[0071] Dielectric layer 1000;

[0072] First connecting column 1100;

[0073] Second connecting column 1200;

[0074] Third connecting column 1300. DETAILED DESCRIPTION

[0075] In order to enable personnel in the technical field to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should fall within the scope of protection of the present application.

[0076] Modern AI hardware relies on the indexing of off-chip memory to complete pruning. In the indexing process, the sparsity information is loaded from the off-chip memory to the on-chip cache in the form of a low-precision matrix, and is repeatedly refreshed and read in the subsequent weight update. In actual neural networks, zero weights are often randomly distributed without rules, which corresponds to unstructured, most fine-grained element-wise pruning, which greatly increases the overhead of indexing.

[0077] To reduce the access of off-chip memory and avoid large index overhead, the current mainstream solution is to increase the pruning granularity, from fine-grained pruning to coarser vector-wise pruning and block-wise pruning. However, although coarse-grained pruning greatly reduces latency and energy consumption, it inevitably prunes some important weights, thereby causing a decline in accuracy - this is the accuracy-granularity dilemma faced by sparse neural networks. Coarse-grained pruning damages accuracy, while fine-grained pruning damages energy consumption and latency. This greatly weakens the potential advantages of sparse neural networks, and has not yet been solved.

[0078] Currently, to solve the accuracy-granularity dilemma faced by sparse neural networks, fine-grained sparse acceleration technology has been introduced, which adopts a 2:4 sparse mode, that is, of every four consecutive values in a group, at least two must be zero, achieving a 50% sparsity. The remaining non-zero values are reorganized into a structured weight matrix, corresponding to saving half the index. Ultimately, twice the inference speed can be achieved - this is a clever compromise between granularity and accuracy. However, it is still structured and fixed-proportion sparse, and can only achieve limited inference acceleration, but is still not suitable for critical sparse training.

[0079] In addition, there are currently reports of in-memory computing hardware for sparse neural networks. For emerging non-volatile memories, both weight storage and computation occur locally, which is very suitable for fine-grained and unstructured sparse neural network inference. However, for critical sparse training, that is, how to reduce the index overhead, there is still a lack of solutions.

[0080] To solve the above problems, the applicant has developed a new type of in-memory computing hardware that can support sparse training without external indexes, fundamentally eliminating the frequent external indexing process of sparse training, and supporting any unstructured, any coarse-fine-grained pruning sparse training. This new hardware design breaks the accuracy-granularity dilemma of sparse neural networks and realizes the great advantages of sparse neural networks in terms of energy consumption and latency.

[0081] Specifically, please refer to FIG. 1, which is a structural schematic diagram of an embodiment of the in-memory computing hardware of the present application.

[0082] As shown in FIG. 1, the storage-computing integrated hardware is composed of a plurality of ferroelectric transistor units 10 arranged in an array, each of which can include two non-volatile transistors, which are named as first non-volatile transistor 500 and second non-volatile transistor 600, respectively.

[0083] Each ferroelectric transistor unit 10 further includes a bit line 100, a data input line 200, a data output line 300 and a sparsity line 400.

[0084] In this embodiment, the bit lines 100 and the data input lines 200 are arranged in parallel along the x-axis direction, and the data output lines 300 and the sparsity lines 400 are arranged in parallel along the y-axis direction.

[0085] In the x-axis direction, the bit lines 100 and the data input lines 200 of adjacent ferroelectric transistor units 10 can be connected as a whole to realize unified transmission of signals; in the y-axis direction, the sparsity lines 400 and the data output lines 300 of adjacent ferroelectric transistor units 10 can be connected as a whole to realize unified transmission of signals.

[0086] Specifically, the principle of the ferroelectric transistor unit 10 of the present application will be described in detail below. Please refer to FIG. 2, which is a schematic diagram of the working principle of the ferroelectric transistor unit 10 of the present application.

[0087] As shown in FIG. 2, the first non-volatile transistor 500 (sparsity transistor) can be a digital transistor, which can be used to control the switching of the second non-volatile transistor 600 (weight transistor).

[0088] The second non-volatile transistor 600 can be an analog transistor, which can be used for weight update in sparse network training.

[0089] Based on this, whether the first non-volatile transistor 500 is turned on or not determines whether the training pulse can be transmitted to the second non-volatile transistor 600, and thus determines whether the weight is pruned. Since the state of the first non-volatile transistor 500 can be programmed in the unit, the external indexing process is eliminated.

[0090] For the weight that is not pruned, the state of the first non-volatile transistor 500 can be an open state (1 state), at which time the training pulse can be normally transmitted to the second non-volatile transistor 600, and the weight can be normally updated;

[0091] For the weight that is planned to be pruned, the second non-volatile transistor 600 can be first set to zero to stop inference, and then the first non-volatile transistor 500 can be set to zero to stop sparse training.

[0092] For the weight that needs to be regrown, the state of the first non-volatile transistor 500 can be switched to the open state, and the weight update of the second non-volatile transistor 600 is started.

[0093] It can be understood that the ferroelectric transistor unit 10 based on the working principle described above can realize the control of whether the weight is updated through the first non-volatile transistor 500, thereby realizing the in-situ storage of the sparsity information in the unit, and making it participate in the sparse training process together with the weight information, and completely eliminating the external indexing process.

[0094] In particular, the ferroelectric transistor unit 10 described above fully utilizes the characteristics of the storage-computing integrated hardware, supports unstructured and extremely fine-grained sparse training, and can realize high accuracy and fine granularity of the sparse neural network at the same time.

[0095] Specifically, the first source 501 of the first non-volatile transistor 500 can be connected with the bit line 100, the first gate 503 can be connected with the sparse line 400, and the first drain 502 can be connected with the gate of the second non-volatile transistor 600.

[0096] The second source 601 of the second non-volatile transistor 600 can be connected with the data input line 200, the second drain 602 can be connected with the data output line 300, and the second gate 603 can be connected with the first drain 502 of the first non-volatile transistor 500.

[0097] Based on this structure, by controlling the input of the sparse line 400, the output of the first drain 502 of the first non-volatile transistor 500 can be controlled. Since the first drain 502 of the first non-volatile transistor 500 is connected with the second gate 603 of the second non-volatile transistor 600, the output of the first drain 502 of the first non-volatile transistor 500 can realize the switching adjustment of the second non-volatile transistor 600. When the second non-volatile transistor 600 is in the open state, it can update the weight input through the data input line 200, and when the second non-volatile transistor 600 is in the closed state, it cannot update the weight input through the data input line 200, thereby realizing the in-situ storage of the sparsity information without the need for an external indexing process.

[0098] It should be noted that in the above embodiment, the bit line 100 and the data input line 200 are arranged in parallel along the x-axis direction, and the data output line 300 and the sparse line 400 are arranged in parallel along the y-axis direction, thereby facilitating the wiring arrangement of the storage-computing integrated hardware.

[0099] In other embodiments, the bit lines 100 and the data input lines 200 can also be arranged non-parallelly, the data output lines 300 and the sparse lines 400 can also be arranged non-parallelly, the bit lines 100 and the sparse lines 400 can also be arranged non-perpendicularly, the data input lines 200 and the data output lines 300 can also be arranged non-perpendicularly, as long as the spacing of the bit lines 100, the sparse lines 400, the data input lines 200 and the data output lines 300 on the hardware of the storage-computing integration is ensured, and the signal input and output of each ferroelectric transistor unit 10 is ensured, the effect of the embodiment can also be achieved.

[0100] The layout of the two non-volatile transistors on the ferroelectric transistor unit 10 will be described in detail below. Please refer to FIG. 3 and FIG. 4, FIG. 3 is a structural schematic diagram of an embodiment of the ferroelectric transistor unit 10 of the present application, and FIG. 4 is a perspective structural schematic diagram of an embodiment of the ferroelectric transistor unit 10 of the present application.

[0101] As shown in FIG. 3 and FIG. 4, the ferroelectric transistor unit 10 includes a substrate 700, an isolation layer 800, a ferroelectric layer 900 and a dielectric layer 1000 arranged in sequence.

[0102] The substrate 700 can be a P-type silicon substrate 700 with a silicon dioxide oxide layer, or any other substrate 700 material that can be applied to a ferroelectric transistor.

[0103] The isolation layer 800 can be a silicon dioxide layer, or any other isolation material that can be applied to a ferroelectric transistor, and the material thereof is not limited compared with other conventional ferroelectric transistors, and the thickness thereof can meet the isolation requirement, for example, it can be 20 nm.

[0104] The ferroelectric layer 900 can be any conventional ferroelectric material, for example, HZO, etc., and the thickness thereof can be the conventional ferroelectric layer 900 thickness, for example, it can be 10 nm.

[0105] The dielectric layer 1000 can be a conventional ferroelectric transistor dielectric material such as hafnium dioxide, and the thickness thereof can meet the design requirement, for example, it can be 12 nm.

[0106] The first source 501 and the first drain 502 of the first non-volatile transistor 500, the second source 601 and the second drain 602 of the second non-volatile transistor 600, the data input line 200 and the bit line 100 can be arranged on the side of the dielectric layer 1000 away from the ferroelectric layer 900.

[0107] The sparse line 400 and the data output line 300 can be arranged on the side of the substrate 700 facing the isolation layer 800.

[0108] In order to realize the connection of the second drain 602 and the data output line 300, a first connecting column 1100 can be arranged in the ferroelectric transistor unit 10, the first connecting column 1100 penetrating the dielectric layer 1000, the ferroelectric layer 900 and the isolation layer 800, and the two ends of the first connecting column 1100 can be connected with the second drain 602 and the data output line 300 respectively.

[0109] It should be noted that the embodiment only shows one example of two non-volatile transistor layouts; in other embodiments, the first source 501, the first drain 502, the second source 601, the second drain 602, the data input line 200 and the bit line 100 can also not be arranged on the same surface, and can also be arranged at other positions, and the sparse line 400 and the data output line 300 can also not be arranged on the same surface, for example, the first source 501 and the first drain 502 can also be arranged on the surface of the substrate 700, and the second source 601 and the second drain 602 can also be arranged on the surface of the substrate 700; the positions of the data input line 200, the bit line 100, the sparse line 400 and the data output line 300 can also be arbitrarily interchanged, as long as the isolation of the four wires can be realized, and the effects of the embodiment can be realized.

[0110] The first non-volatile transistor 500 further comprises a first channel 504, a first floating gate 505 and a first back gate 506.

[0111] The first channel 504 is arranged on the side of the dielectric layer 1000 away from the ferroelectric layer 900, and the first channel 504 connects the first source 501 and the first drain 502. The material of the first channel 504 can be MoS2, or other channel materials.

[0112] The first floating gate 505 is arranged on the side of the ferroelectric layer 900 facing the dielectric layer 1000, and the first floating gate 505 is connected with the first channel 504 through the dielectric layer 1000.

[0113] The first back gate 506 is arranged on the side of the ferroelectric layer 900 away from the dielectric layer 1000, and the first back gate 506 is connected with the first floating gate 505 through the ferroelectric layer 900.

[0114] The first gate 503 can be arranged on the side of the ferroelectric layer 900 facing the dielectric layer 1000, and the first gate 503 is spaced apart from the first floating gate 505; and the first gate 503 is connected with the first back gate 506 through the ferroelectric layer 900.

[0115] In order to realize the connection of the first gate 503 and the sparse line 400, a second connecting column 1200 can be arranged in the ferroelectric transistor unit 10, the second connecting column 1200 penetrating the ferroelectric layer 900 and the isolation layer 800, and the two ends of the second connecting column 1200 are connected with the sparse line 400 and the first gate 503 respectively.

[0116] For the convenience of understanding the structure of the first nonvolatile transistor 500, refer to FIG. 5, which is a schematic diagram of a perspective structure of an embodiment of the first nonvolatile transistor 500 of the present application.

[0117] As shown in FIG. 5, the first source 501 and the first drain 502 of the first nonvolatile transistor 500 are connected through the first channel 504, the first channel 504 is connected with the first floating gate 505 through the dielectric layer 1000, the first floating gate 505 is connected with the first back gate 506 through the ferroelectric layer 900, and the ferroelectric transistor structure is formed. At the same time, the first gate 503 is also connected with the first back gate 506 through the ferroelectric layer 900.

[0118] The voltage of the first gate 503 is controlled through the sparse line 400, and the output control of the first drain 502 can be realized.

[0119] It should be noted that in the embodiment, the first gate 503 of the first nonvolatile transistor 500 is arranged on the side of the ferroelectric layer 900 facing the dielectric layer 1000, that is, the first gate 503 is arranged on the top surface of the ferroelectric layer 900, and the first back gate 506 is arranged on the back surface of the ferroelectric layer 900; in other embodiments, the first back gate 506 can be omitted, and the first gate 503 can also be directly arranged on the back surface of the ferroelectric layer 900, so that at least part of the first gate 503 overlaps with the orthographic projection of the first floating gate 505, and the effect of the embodiment can also be achieved.

[0120] Please continue to refer to FIG. 3 and FIG. 4, the second nonvolatile transistor 600 further comprises a second channel 604 and a second floating gate 605.

[0121] The second channel 604 is arranged on the side of the dielectric layer 1000 away from the ferroelectric layer 900, and the second channel 604 connects the second source 601 and the second drain 602. The material of the first channel 504 can be MoS2, or other channel materials.

[0122] The second floating gate 605 is arranged on the side of the ferroelectric layer 900 facing the dielectric layer 1000, and the second floating gate 605 is connected with the second channel 604 through the dielectric layer 1000. Among them, the second gate 603 is arranged on the side of the ferroelectric layer 900 away from the dielectric layer 1000, and the second gate 603 is connected with the second floating gate 605 through the ferroelectric layer 900.

[0123] In order to realize the connection between the second gate 603 and the first drain 502 of the first nonvolatile transistor 500, a third connecting column 1300 of the dielectric layer 1000 and the ferroelectric layer 900 can be arranged in the ferroelectric transistor unit 10, and the third connecting column 1300 is connected with the second gate 603 and the first drain 502 at both ends respectively.

[0124] For ease of understanding, reference can be made to FIG. 6, which is a schematic diagram of a perspective structure of an embodiment of the second non-volatile transistor 600.

[0125] As shown in FIG. 6, the second source 601 and the second drain 602 of the second non-volatile transistor 600 are connected through the second channel 604, the second channel 604 is connected with the first floating gate 505 through the dielectric layer 1000, and the first floating gate 505 is connected with the second gate 603 through the ferroelectric layer 900.

[0126] Since the second gate 603 is connected with the first drain 502 of the first non-volatile transistor 500, the first non-volatile transistor 500 can regulate the voltage of the second gate 603, thereby controlling the switching adjustment of the second non-volatile transistor 600.

[0127] It should be noted that in the embodiment, the second gate 603 of the second non-volatile transistor 600 is arranged on the side of the ferroelectric layer 900 away from the dielectric layer 1000, i.e., the second gate 603 is arranged on the back of the ferroelectric layer 900; in other embodiments, the second gate 603 can also be arranged on the side of the ferroelectric layer 900 facing the dielectric layer 1000, i.e., the second gate 603 can also be arranged on the top surface of the ferroelectric layer 900 and isolated from the second floating gate 505, and correspondingly, a back gate metal can be arranged on the back of the ferroelectric layer 900, so that the back gate metal at least partially overlaps the orthographic projection of the second floating gate 605 and at least partially overlaps the orthographic projection of the second gate 603, which can also achieve the effect of the embodiment.

[0128] Based on the structure of the ferroelectric transistor unit 10 in the above embodiments, two non-volatile transistors can be integrated in a single ferroelectric transistor unit 10, and the sparsity index originally outside is integrated into the selection transistor of the weight unit, so that it determines whether the weight participates in the training. This fundamentally eliminates the frequent external index process of sparse training, and supports any unstructured, any coarse-grained pruning sparse training. This new hardware design breaks the dilemma of "accuracy-granularity" of sparse neural networks, and realizes the great advantages of sparse neural networks in energy consumption and time delay.

[0129] The application also provides a preparation method of the ferroelectric transistor unit 10 of the above-mentioned embodiments. Specifically, reference can be made to FIG. 7 and FIG. 8, FIG. 7 is a preparation method of an embodiment of the ferroelectric transistor unit 10, and FIG. 8 is a device state diagram corresponding to each step in FIG. 7.

[0130] As shown in FIG. 7 and FIG. 8, the preparation method comprises:

[0131] S100, depositing metal on the surface of the substrate to prepare a data output line and a sparsity line spaced apart from each other.

[0132] First, metal can be deposited on the surface of the substrate 700 to prepare the row lines, i.e. the data output lines 300 and the sparse lines 400.

[0133] The method of depositing the metal can be to define the deposition area by electron beam exposure, and then to evaporate the metal material by electron beam.

[0134] In an embodiment, the metal material can be Ti or Pt, and the thickness of the deposition can be 15 nm.

[0135] S200, depositing an isolation material on the surface of the substrate to prepare an isolation layer.

[0136] The method of depositing the isolation material can be to use plasma enhanced atomic layer deposition (PE-ALD) for deposition.

[0137] In an embodiment, the isolation material can be silicon dioxide, and the thickness can be 20 nm. In other embodiments, it can also be any other isolation material applicable to the ferroelectric transistor, and the thickness can be designed to ensure the isolation performance.

[0138] S300, depositing metal on the surface of the isolation layer to prepare the first back gate and the second gate spaced from each other.

[0139] The method of depositing the metal can be to define the deposition area by electron beam exposure, and then to evaporate the metal material by electron beam, which is the same as S100.

[0140] In an embodiment, the deposited metal material can be Ti or Pt, and the thickness of the deposition can be 12 nm.

[0141] S400, growing a ferroelectric material on the surface of the isolation layer to prepare a ferroelectric layer.

[0142] The ferroelectric material can be grown by ALD method or MOCVD method through vaporization of metal precursors.

[0143] For example, in an embodiment, the ferroelectric layer 900 adopts HZO ferroelectric material, which can be grown by ALD method using TDMA-Hf and TDMA-Zr as precursors, and the thickness of the ferroelectric layer 900 can be 10 nm.

[0144] S500, depositing metal on the surface of the ferroelectric layer to prepare the first floating gate, the first gate and the second floating gate spaced from each other.

[0145] At least part of the first floating gate 505 overlaps the orthographic projection of the first back gate 506, so as to ensure that the first floating gate 505 can be connected with the first back gate 506 through the ferroelectric layer 900.

[0146] At least part of the first gate 503 overlaps with the orthographic projection of the first back gate 506, so as to ensure that the first gate 503 can be connected with the first back gate 506 through the ferroelectric layer 900.

[0147] At least part of the second floating gate 605 overlaps with the orthographic projection of the second gate 603, so as to ensure that the second floating gate 605 can be connected with the second gate 603 through the ferroelectric layer 900.

[0148] S600, rapid thermal annealing, and then depositing a dielectric material on the surface of the ferroelectric layer to obtain a dielectric layer.

[0149] In an embodiment, the temperature of the rapid thermal annealing can be 450 degrees, and the annealing time can be 30 seconds.

[0150] The method of depositing the dielectric material can also use plasma-enhanced atomic layer deposition (PE-ALD) deposition, which is the same as S200.

[0151] In an embodiment, the material of the dielectric layer 1000 can be hafnium dioxide, and the thickness can be 12 nm. In other embodiments, other dielectric materials applicable to ferroelectric transistors can also be used to achieve the effects of the present embodiment.

[0152] S700, sequentially etching and depositing metal on the surface of the dielectric layer to obtain a first connecting column, a second connecting column and a third connecting column.

[0153] The third connecting column 1300 extends from the surface of the dielectric layer 1000 to the surface of the isolation layer 800 and is connected with the second gate 603, the first connecting column 1100 extends from the surface of the dielectric layer 1000 to the surface of the substrate 700 and is connected with the data output line 300, and the second connecting column 1200 is connected with the sparse line 400 and the first gate 503.

[0154] The etching can be defined by electron beam exposure to define the opening area, and then etched by BCl3 / Ar plasma. When a good etching-resistant material Pt is used in the sparse line 400, the second gate 603 and the data output line 300, the openings can be etched at one time.

[0155] S800, preparing a first channel and a second channel spaced from each other on the surface of the dielectric layer, and depositing metal to obtain a first source electrode, a first drain electrode, a first source electrode, a second drain electrode, a data input line and a bit line.

[0156] At least part of the first channel 504 overlaps with the orthographic projection of the first floating gate 505, so as to ensure that the first channel 504 can be connected with the first floating gate 505 through the dielectric layer 1000.

[0157] At least part of the second channel 604 overlaps with the orthogonal projection of the second floating gate 605, so as to ensure that the second channel 604 can be connected with the second floating gate 605 through the dielectric layer 1000.

[0158] The data input line 200 and the bit line 100 are arranged at intervals.

[0159] The first source electrode 501 and the first drain electrode 502 are connected through the first channel 504, the first source electrode 501 is connected with the bit line 100, the second source electrode 601 and the second drain electrode 602 are connected through the second channel 604, and the second source electrode 601 is connected with the data input line 200,

[0160] The first drain electrode 502 is connected with the third connecting column 1300, so as to realize the connection between the first drain electrode 502 and the second gate 603.

[0161] The second drain electrode 602 is connected with the first connecting column 1100, so as to realize the connection between the second drain electrode 602 and the data output line 300.

[0162] Next, the method for preparing the channel and depositing the metal is described by taking MoS2 as an example.

[0163] Specifically, the method for preparing the channel and depositing the metal can include:

[0164] S801, transferring a single layer of MoS2 to the surface of the dielectric layer 1000 through a metal film, and etching the metal film and MoS2 in the non-channel region.

[0165] Firstly, a single layer of MoS2 can be transferred to the surface of the dielectric layer 1000 by using a metal film, wherein the metal film can be Au or the like, and of course other transfer methods can also be used in other embodiments, as long as the transfer of MoS2 can be realized.

[0166] Then, the MoS2 and Au film in the non-channel region can be etched, and at this time, only the MoS2 and Au film are arranged in the channel region.

[0167] S802, depositing a metal on the surface of the dielectric layer 1000 to obtain the first source electrode 501, the first drain electrode 502, the first source electrode 501, the second drain electrode 602, the data input line 200 and the bit line 100.

[0168] The method for depositing the metal can be to define the deposition area by electron beam exposure, and then to evaporate the metal material by electron beam.

[0169] In an embodiment, the metal material can be Ti or Pt, and the thickness of the deposition can be 60 nm.

[0170] S803, etching the metal film in the channel region with the first source 501, the first drain 502, the first source 501 and the second drain 602 as masks to obtain the first channel 504 and the second channel 604.

[0171] After the deposition is completed, the Au film in the channel region can be etched with the deposited metal as a mask to expose the channel material, thereby obtaining the first channel 504 and the second channel 604.

[0172] S900, high vacuum annealing to obtain the ferroelectric transistor unit.

[0173] In an embodiment, the vacuum degree of the high vacuum annealing can be 10 -6 Pa, the annealing temperature can be 200 degrees, and the annealing time can be 6h.

[0174] It should be noted that the above preparation method only shows a typical preparation scheme of the ferroelectric transistor unit 10 of an embodiment of the present application, and in other embodiments, the specific processes and parameters of each step of the preparation scheme can be adjusted, and the preparation of the ferroelectric transistor unit 10 of the corresponding structure can be realized. The order of each step can also be adjusted for the ferroelectric transistor unit 10 of other embodiments, and the effects of the present embodiment can be achieved.

[0175] For those skilled in the art, it should be understood that although the present application is described in the form of embodiments, each embodiment does not contain only one independent technical solution, and the description of the specification is only for the purpose of clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments that those skilled in the art can understand.

[0176] The foregoing description of specific exemplary embodiments of the application is intended to be illustrative only and is not intended to limit the application to the precise forms described. Many modifications and variations are possible in light of the above teachings without departing from the spirit or essential characteristics of the application. The exemplary embodiments were chosen and described in order to explain the principles of the application and its practical application and to allow others skilled in the art to understand the application for various exemplary embodiments with various modifications as are suited to the particular use contemplated. The scope of the application is to be defined by the claims and their equivalents.

Claims

1. A ferroelectric transistor cell supporting index-free sparse training, comprising: The first non-volatile transistor comprises a first source, a first drain and a first gate. The second non-volatile transistor comprises a second source, a second drain and a second gate. The sparse line is connected with the first gate. The bit line is connected with the first source. The data input line is connected with the second source. The data output line is connected with the second drain. The first drain and the second gate are connected, the first non-volatile transistor is used for controlling the switch of the second non-volatile transistor based on the signal of the sparse line, and the second non-volatile transistor is used for weight update and data processing storage. The substrate, the isolation layer, the ferroelectric layer and the dielectric layer are arranged in sequence.

2. The ferroelectric transistor cell of claim 1, wherein, The first source, the first drain, the second source, the second drain, the sparse line, the bit line, the data input line and the data output line are arranged on one side of the dielectric layer away from the ferroelectric layer or one side of the substrate facing the isolation layer. The first source, the first drain, the second source, the second drain, the data input line and the bit line are arranged on one side of the dielectric layer away from the ferroelectric layer.

3. The ferroelectric transistor cell of claim 2, wherein, The sparse line and the data output line are arranged on one side of the substrate facing the isolation layer. The second drain is connected with the data output line through the first connecting column penetrating the dielectric layer, the ferroelectric layer and the isolation layer. The first non-volatile transistor further comprises a first channel arranged between the first source and the first drain.

4. The ferroelectric transistor cell of claim 3, wherein, The second non-volatile transistor further comprises a second channel arranged between the second source and the second drain. The first non-volatile transistor further comprises a first floating gate arranged on one side of the ferroelectric layer facing the dielectric layer, and the first floating gate is connected with the first channel through the dielectric layer.

5. The ferroelectric transistor cell of claim 4, wherein, The first gate is arranged on one side of the ferroelectric layer, and the first gate is connected with the first floating gate through the ferroelectric layer. The first gate is arranged on one side of the ferroelectric layer facing the dielectric layer, and the first gate is isolated from the first floating gate.

6. The ferroelectric transistor cell of claim 5, wherein, The first non-volatile transistor further comprises a first back gate arranged on one side of the ferroelectric layer away from the dielectric layer, and the first back gate at least partially overlaps the first floating gate in orthographic projection, and the first back gate at least partially overlaps the first gate in orthographic projection. The first gate is connected with the sparse line through the second connecting column penetrating the ferroelectric layer and the isolation layer.

7. The ferroelectric transistor cell of claim 6, wherein, The second non-volatile transistor further comprises a second floating gate arranged on one side of the ferroelectric layer facing the dielectric layer, and the second floating gate is connected with the second channel through the dielectric layer.

8. The ferroelectric transistor cell of claim 4, wherein, The second gate is arranged on one side of the ferroelectric layer, and the second gate is connected with the second floating gate through the ferroelectric layer. The second gate is arranged on one side of the ferroelectric layer away from the dielectric layer, and the second gate at least partially overlaps the second floating gate in orthographic projection.

9. The ferroelectric transistor cell of claim 8, wherein, ​ 10. The ferroelectric transistor cell of claim 9, wherein, The second gate is connected with the first drain through a third connecting column penetrating through the dielectric layer and the ferroelectric layer.

11. The ferroelectric transistor cell of claim 1, wherein, The sparse lines and the data output lines are arranged in parallel and spaced apart, the bit lines and the data input lines are arranged in parallel and spaced apart, the sparse lines and the bit lines are distributed vertically, and the data output lines and the data input lines are distributed vertically.

12. A method for fabricating a ferroelectric transistor cell supporting indexless sparse training, characterized in that, Comprise: Depositing metal on the substrate surface to prepare the data output lines and the sparse lines spaced apart from each other; Depositing isolation material on the substrate surface to prepare the isolation layer; Depositing metal on the surface of the isolation layer to prepare the first back gate and the second gate spaced apart from each other; Growth of ferroelectric material on the surface of the isolation layer to prepare the ferroelectric layer; Depositing metal on the surface of the ferroelectric layer to prepare the first floating gate, the first gate and the second floating gate spaced apart from each other, wherein at least part of the first floating gate overlaps with the orthographic projection of the first back gate, at least part of the first gate overlaps with the orthographic projection of the first back gate, at least part of the second floating gate overlaps with the orthographic projection of the second gate, and the first gate is connected with the second connecting column; Rapid thermal annealing, followed by depositing dielectric material on the surface of the ferroelectric layer to obtain the dielectric layer; On the surface of the dielectric layer, etching and depositing metal in sequence to obtain the third connecting column extending from the surface of the dielectric layer to the surface of the isolation layer and connected with the second gate, the first connecting column extending from the surface of the dielectric layer to the substrate surface and connected with the data output line, and the second connecting column connecting the first gate and the sparse line; On the surface of the dielectric layer, preparing the first channel and the second channel spaced apart from each other, and depositing metal to obtain the first source, the first drain, the first source, the second drain, the data input line and the bit line; High vacuum annealing to obtain the ferroelectric transistor unit; Wherein, at least part of the first channel overlaps with the orthographic projection of the first floating gate, at least part of the second channel overlaps with the orthographic projection of the second floating gate, the data input line and the bit line are arranged spaced apart from each other, the first source and the first drain are connected through the first channel, the first source is connected with the bit line, the first drain is connected with the third connecting column, the second source and the second drain are connected through the second channel, the second source is connected with the data input line, and the second drain is connected with the first connecting column.

13. The method of claim 12, wherein, The sparse lines and the data output lines are arranged in parallel and spaced apart, the bit lines and the data input lines are arranged in parallel and spaced apart, the sparse lines and the bit lines are distributed vertically, and the data output lines and the data input lines are distributed vertically.

14. The method of claim 12, wherein, The first channel and the second channel are MoS2 channels, and the step of preparing the first channel and the second channel spaced apart from each other on the surface of the dielectric layer and depositing metal comprises: Transferring a single layer of MoS2 to the surface of the dielectric layer through a metal film, etching the metal film and MoS2 in the non-channel region; Depositing metal on the surface of the dielectric layer to obtain the first source, the first drain, the first source, the second drain, the data input line and the bit line; The metal film in the channel region is etched by taking the first source electrode, the first drain electrode, the first source electrode and the second drain electrode as a mask to obtain the first channel and the second channel.

15. The preparation method according to claim 12, characterized in that, The method for depositing the metal specifically comprises defining a deposition region by electron beam exposure, and then depositing a metal material by electron beam evaporation; and / or, The method for depositing the isolation material and the dielectric material specifically comprises depositing by a plasma-enhanced atomic layer deposition method.

16. A memory-compute integrated hardware, comprising: The ferroelectric transistor unit comprises a plurality of ferroelectric transistor units arranged in an array, and each of the ferroelectric transistor units is prepared by the preparation method of any one of claims 12 to 15. In adjacent ferroelectric transistor units, adjacent sparse lines are connected as a whole, adjacent bit lines are connected as a whole, adjacent data input lines are connected as a whole, and adjacent data output lines are connected as a whole.

17. The storage and computing integrated hardware according to claim 16, wherein, In adjacent ferroelectric transistor units, adjacent sparse lines are parallel to each other, adjacent bit lines are parallel to each other, adjacent data input lines are parallel to each other, and adjacent data output lines are parallel to each other.

18. The storage and computing integrated hardware according to claim 16, wherein, In the ferroelectric transistor unit, the sparse lines and the data output lines are arranged in parallel and at intervals, the bit lines and the data input lines are arranged in parallel and at intervals, the sparse lines and the bit lines are distributed vertically, and the data output lines and the data input lines are distributed vertically.

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