memory

Abstract

A memory. Each memory cell comprises: a first NMOS transistor comprising an active region and a gate, the active region of the first NMOS transistor being connected to a control gate port; a second NMOS transistor comprising an active region and a gate, the active region of the second NMOS transistor being connected to a TNU port; a first PMOS transistor comprising a first active region, a second active region and a gate, wherein the first active region is connected to a bit line port, and the gate of the first NMOS transistor, the gate of the second NMOS transistor and the gate of the first PMOS transistor are connected to each other; and a select transistor which is a second PMOS transistor and comprises a first active region, a second active region and a gate, wherein the first active region of the select transistor is connected to a select line port, the second active region of the select transistor is connected to the second active region of the first PMOS transistor, and the gate of the select transistor is connected to a word line port. The present disclosure adopts a positive and negative voltage design, the maximum voltage to which devices in each memory cell need to bear is reduced to half of that in the positive voltage design, and a peripheral circuit can also eliminate the design of a high-voltage device, thereby reducing the area of the peripheral circuit.

Description

Memory TECHNICAL FIELD

[0001] The present disclosure relates to information storage, and in particular, to a memory. BACKGROUND

[0002] According to whether the stored data will be lost after power-off, a memory can be divided into a volatile memory (RAM) and a non-volatile memory (NVM). The NVM generally includes three basic operation modes of programming, erasing and reading. The programming and erasing operations change the initial electrical state of the storage unit, thereby storing data. The reading operation distinguishes different states of the storage unit and outputs the reading result.

[0003] A low power non-volatile memory (LNVM) uses FN (Fowler-Nordheim) quantum tunneling principle for erasing and programming. The current consumed by the FN tunneling programming is much smaller than the current consumed by the hot carrier injection programming.

[0004] An exemplary bidirectional FN tunneling LNVM needs to apply high voltage in the programming mode, and the high voltage will cause the chip area of the memory to increase. SUMMARY

[0005] Therefore, it is necessary to provide a memory with a smaller chip area.

[0006] A memory includes a memory array, the memory array includes a plurality of memory cells, each memory cell includes: a first NMOS transistor including an active region and a gate, the active region of the first NMOS transistor is connected to a control gate port to obtain the potential of the control gate port; a second NMOS transistor including an active region and a gate, the active region of the second NMOS transistor is connected to a tunnel port to obtain the potential of the tunnel port; a first PMOS transistor including a first active region, a second active region and a gate, the first active region of the first PMOS transistor is connected to a bit line port to obtain the potential of the bit line port, the gate of the first NMOS transistor, the gate of the second NMOS transistor and the gate of the first PMOS transistor are connected to each other; a selection transistor, which is a second PMOS transistor, including a first active region, a second active region and a gate, the first active region of the selection transistor is connected to a selection line port to obtain the potential of the selection line port, the second active region of the selection transistor is connected to the second active region of the first PMOS transistor, and the gate of the selection transistor is connected to a word line port to obtain the potential of the word line port; wherein, in an erase operation, the control gate port, the bit line port and the word line port connected to the selected memory cell input a positive voltage, and the tunnel port connected to the selected memory cell inputs a negative voltage; in a program operation, the control gate port and the tunnel port connected to the selected memory cell input a negative voltage, and the bit line port and the word line port connected to the selected memory cell input a positive voltage.

[0007] The above memory uses positive and negative voltage design, the maximum voltage required to be borne by each device in the memory cell is reduced to half of that in the positive voltage design, and the peripheral circuit can also be designed without high-voltage devices, thereby reducing the area of the peripheral circuit. Since the maximum voltage to be borne is reduced to half, the reliability and durability of the memory cell can also be improved.

[0008] In one of the embodiments, in a read operation, a low level is applied to the control gate port, the tunnel port and the word line port connected to the selected memory cell, the selection line port connected to the selected memory cell inputs a power supply voltage, and the current size of the bit line connected to the selected memory cell is used to identify the data stored in the selected memory cell.

[0009] In one of the embodiments, the gate of the first NMOS transistor, the gate of the second NMOS transistor and the gate of the first PMOS transistor are integrated.

[0010] In one of the embodiments, the integrated gate is a floating gate, and the first PMOS transistor is a floating gate transistor.

[0011] In one of the embodiments, the second active region of the selection transistor and the second active region of the first PMOS transistor share a P-type region.

[0012] In one of the embodiments, the memory array includes memory cells arranged in at least two rows and at least two columns, at least some of the memory cells of the rows share the tunneling port with the memory cells of the adjacent rows, at least some of the memory cells of the rows share the control gate port with the memory cells of the adjacent rows, the bit line port is an odd row bit line port or an even row bit line port, the odd row bit line port is used to select the memory cells of the odd rows, the even row bit line port is used to select the memory cells of the even rows; the tunneling port, the control gate port and the word line port are used for row selection, and the select line port, the odd row bit line port and the even row bit line port are used for column selection.

[0013] In one of the embodiments, the memory array includes: a first region, which is a long strip extending in a first direction, active regions of a plurality of first NMOS transistors are located in the first region; a second region, which is a long strip extending in the first direction, active regions of a plurality of first NMOS transistors are located in the second region; a third region, which is a long strip extending in the first direction and located between the first region and the second region, active regions of a plurality of second NMOS transistors are located in the third region; a first N-well extending in the first direction and located between the first region and the third region; a second N-well extending in the first direction and located between the second region and the third region; wherein first active regions and second active regions of a plurality of first PMOS transistors and first active regions and second active regions of a plurality of selection transistors are located in the first N-well, and first active regions and second active regions of a plurality of first PMOS transistors and first active regions and second active regions of a plurality of selection transistors are located in the second N-well.

[0014] In one of the embodiments, a plurality of the floating gates extend from above the first region to above the first N-well and then to above the third region, and a plurality of the floating gates extend from above the second region to above the second N-well and then to above the third region.

[0015] In one of the embodiments, the width of the active region of the first NMOS transistor is greater than the width of the active region of the second NMOS transistor, and the width direction is perpendicular to the first direction.

[0016] In one of the embodiments, in the memory array, the first NMOS transistor of at least some of the memory cells of the rows shares a P-well with the first NMOS transistor of the memory cells of the adjacent rows, and the second NMOS transistor of at least some of the memory cells of the rows shares a P-well with the second NMOS transistor of the memory cells of the adjacent rows.

[0017] In one of the embodiments, the first active region and the second active region of the first PMOS transistor and the first active region and the second active region of the select transistor of each memory cell are located in the first N-well, between the active region of the first NMOS transistor and the active region of the second NMOS transistor.

[0018] In one of the embodiments, the active region of the first NMOS transistor of the memory cells in the first column is located in the first region; the active region of the first NMOS transistor of the memory cells in the second column is located in the second region; the active region of the second NMOS transistor of the memory cells in the first column and the active region of the second NMOS transistor of the memory cells in the second column are both located in the third region; the first active region and the second active region of the first PMOS transistor and the first active region and the second active region of the select transistor of the memory cells in the first column are located in the first N-well; the first active region and the second active region of the first PMOS transistor and the first active region and the second active region of the select transistor of the memory cells in the second column are located in the second N-well.

[0019] In one of the embodiments, the first NMOS transistor of at least part of the rows of memory cells shares a P-well with the first NMOS transistor of the memory cells of the adjacent row, specifically: the active region of the first NMOS transistor of two rows of memory cells sharing a control gate port shares a P-well; the second NMOS transistor of at least part of the rows of memory cells shares a P-well with the second NMOS transistor of the memory cells of the adjacent row, specifically: the active region of the second NMOS transistor of two rows of memory cells sharing a tunneling port TNU shares a P-well.

[0020] In one of the embodiments, the area of the active region of the first NMOS transistor is larger than the area of the active region of the second NMOS transistor.

[0021] In one of the embodiments, the area of the first NMOS transistor is larger than the area of the second NMOS transistor.

[0022] In one of the embodiments, the memory is an FN tunneling non-volatile memory.

[0023] It is also necessary to provide a programming method of the memory cell data of the memory of any one of the preceding embodiments, comprising: inputting a negative voltage VBB to the control gate port and the tunneling port connected to the selected memory cell, and inputting a positive voltage VPP to the bit line port and the word line port connected to the selected memory cell during the programming operation.

[0024] It is also necessary to provide a method for erasing data of memory cells of the memory according to any one of the preceding embodiments, comprising inputting positive voltage VPP to the control gate port, the bit line port and the word line port connected to the selected memory cell, and inputting negative voltage VBB to the tunneling port connected to the selected memory cell during the erasing operation.

[0025] It is also necessary to provide a method for reading data of memory cells of the memory according to any one of the preceding embodiments, comprising applying low level to the control gate port, the tunneling port and the word line port connected to the selected memory cell, and inputting power supply voltage VDD to the select line port connected to the selected memory cell during the reading operation. The data stored in the selected memory cell is identified by the current size of the bit line connected to the selected memory cell. BRIEF DESCRIPTION OF DRAWINGS

[0026] For a better description and illustration of the disclosed embodiments and / or examples disclosed herein, reference can be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of the disclosed disclosure, the presently described embodiments and / or examples, and any one of the modes of these disclosures presently understood.

[0027] FIG. 1 is a circuit schematic diagram of a storage cell of a bidirectional FN tunneling LNVM.

[0028] FIG. 2 is a circuit schematic diagram of a storage array of the memory according to an embodiment of the present application.

[0029] FIG. 3 is a schematic diagram of row and column decoding and row and column driving according to an embodiment of the present application.

[0030] FIG. 4 is a partial layout of a storage array of the memory according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] For the purpose of facilitating the understanding of the present disclosure, the present disclosure will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present disclosure is more thorough and complete.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] An exemplary bidirectional FN tunneling LNVM is implemented by a storage cell consisting of 4 transistors, as shown in the differential floating gate storage cell shown in FIG. 1. It realizes the application requirement of low power consumption and low cost by high voltage. The device Tc_1 and the device Tc_0 have a large area (i.e. have a large chip area ratio) as control capacitors to couple the voltage to the floating gate (floating gate FG or floating gate FG_B). The device Tt_1 and the device Tt_0 are small size capacitors, connected to the floating gate as the device Tc_1 / device Tc_0, for receiving large coupling voltage. The floating gate transistor T_1 and the floating gate transistor T_0 are used to store charge and control the current output, and the size of the current can identify whether the data stored in the storage cell is "1" or "0". The transistor Ts_1 and the transistor Ts_0 are the switch tubes (select tubes) of the storage cell.

[0035] The circuit shown in FIG. 1, in the programming operation, a high voltage Vsupply is applied to the tunneling port TNU, and the CG port and the CG_B port are applied with Vsupply and 0 voltage (i.e. low level) respectively. At this time, the floating gate FG is pulled to high voltage, and the floating gate FG_B remains low voltage, so the high voltage coupled by the CG port is applied to the body silicon of the floating gate transistor T_1 from the floating gate FG, and the electrons are stored in the floating gate FG by tunneling. At the same time, the high voltage on the tunneling port TNU is applied to the body silicon of the device Tt_0 to the floating gate FG_B, and the electrons are tunneling from the floating gate FG_B to the body silicon of the device Tt_0. Finally, the floating gate FG and the floating gate FG_B store opposite charges (i.e. positive charge and negative charge). In the read operation, the SL port applies the power voltage, the tunneling port TNU and the CG port apply low level, and the WL port applies low level to open the select tube. Since the floating gate FG stores negative charge and the floating gate FG_B stores positive charge, the current of the BL port will be greater than that of the BL_B port, and the size of the current difference is the storage window of the memory.

[0036] The circuit shown in Fig. 1 requires that the device Tt_1, the device Tc_1 and the floating gate transistor T_1 be placed in different wells due to different port biases, so as to achieve independent biasing. However, the distance between the independent wells is required to be large, and thus the size of the memory cell is large. How to arrange the layout (photolithography mask) to save area is one of the difficulties in the design of the circuit structure. In addition, due to the existence of the high voltage Vsupply, the design of the selection transistor Ts_0 / Ts_1 needs to be able to withstand high voltage. The peripheral circuit also needs to design large-area high-voltage devices (for example, LDMOS (Laterally Diffused Metal Oxide Semiconductor)) to ensure the reliability of voltage transmission, which further increases the circuit area. The limitation of area also affects the improvement of the memory capacity. In addition, high voltage stress can cause the gate oxide reliability of the memory transistor to decrease, which reduces the service life.

[0037] Fig. 2 is a circuit schematic diagram of a memory array of a memory in an embodiment of the present application. The memory includes a memory array including memory cells arranged in at least two rows and at least two columns. In Fig. 2, memory cell 00, memory cell 01, memory cell 10, memory cell 11, memory cell 20, memory cell 21, memory cell 30 and memory cell 31 are shown.

[0038] Taking the memory cell 00 as an example, it includes a first NMOS (N-Metal-Oxide-Semiconductor) transistor Tc_0, a second NMOS transistor Tt_0, a first PMOS (P-Metal-Oxide-Semiconductor) transistor T_0 and a selection transistor Ts_0. The first NMOS transistor Tc_0 includes an active region (i.e. the source region and the drain region of the MOS transistor) and a gate, and the active region is connected to a control gate port CG0 to obtain the potential of the control gate port CG0. The second NMOS transistor Tt_0 includes an active region (i.e. the source region and the drain region of the MOS transistor) and a gate, and the active region of the second NMOS transistor Tt_0 is connected to a tunneling port TNU0 to obtain the potential of the tunneling port TNU0. The first PMOS transistor T_0 includes a first active region, a second active region and a gate. The first active region of the first PMOS transistor T_0 is connected to a bit line port BL_e0 to obtain the potential of the bit line port, and the gate of the first NMOS transistor Tc_0, the gate of the second NMOS transistor Tt_0 and the gate of the first PMOS transistor T_0 are connected to each other. The selection transistor Ts_0 is a PMOS transistor, including a first active region, a second active region and a gate. The first active region of the selection transistor Ts_0 is connected to a selection line port SL0 to obtain the potential of the selection line port SL0, the second active region of the selection transistor Ts_0 is connected to the second active region of the first PMOS transistor T_0, and the gate of the selection transistor Ts_0 is connected to a word line port WL0 to obtain the potential of the word line port WL0.

[0039] In the erase operation, if the storage cell to be erased is 00, a positive voltage VPP is applied to the control gate port CG0, the bit line port BL_e0 and the word line port WL0, and a negative voltage VBB is applied to the tunneling port TNU0. In the program operation, if the storage cell to be programmed is 00, a negative voltage VBB is applied to the control gate port CG0 and the tunneling port TNU0, and a positive voltage VPP is applied to the bit line port BL_e0 and the word line port WL0.

[0040] The above memory uses positive and negative voltage design, the maximum voltage required to be borne by the devices in the storage cell is reduced to half of that in the positive voltage design (i.e. the circuit shown in Fig. 1), and the peripheral circuit can also be designed without high voltage devices, thus reducing the area of the peripheral circuit. Since the maximum voltage to be borne is reduced to half, the reliability and durability of the storage cell can also be improved.

[0041] In one embodiment of the present application, the gate of the first NMOS transistor Tc_0, the gate of the second NMOS transistor Tt_0 and the gate of the first PMOS transistor T_0 are connected together. Further, the connected gate is a floating gate (i.e. a gate not electrically connected to the outside). The first PMOS transistor T_0 is a floating gate transistor.

[0042] In one embodiment of the present application, the memory is an NVM, and further can be a low power non-volatile memory (LNVM). The memory in the embodiment shown in Fig. 2 is an FN tunneling LNVM.

[0043] For the memory shown in Fig. 2, electrons are injected into the floating gate FG during erase operation and electrons are pulled out of the floating gate FG during program operation. Specifically, during erase operation, the control gate port CG0, the bit line port BL_e0 and the word line port WL0 are input with a positive voltage VPP, and the tunnel port TNU0 is input with a negative voltage VBB, at this time the voltage on the floating gate FG is coupled to a high voltage, and a pressure difference is formed between the floating gate FG and the body silicon of the second NMOS transistor Tt_0, so that electrons are injected into the floating gate FG. During program operation, the control gate port CG0 and the tunnel port TNU0 are input with a negative voltage VBB, and the bit line port BL_e0 and the word line port WL0 are input with a positive voltage VPP, at this time the voltage on the floating gate FG is coupled to a negative voltage, and a pressure difference is formed between the floating gate FG and the body silicon of the first PMOS transistor T_0, so that electrons are pulled out of the floating gate FG. During read operation, the control gate port CG0, the tunnel port TNU0 and the word line port WL0 are low (i.e. 0 voltage is applied), the select line port SL0 is input with a power supply voltage VDD, and the current through the bit line port BL_e0 is used to identify the data stored in the memory cell 00. Specifically, at this time, the first NMOS transistor Tc_0 and the second NMOS transistor Tt_0 are biased at 0 voltage, and the first PMOS transistor T_0 and the select transistor Ts_0 are turned on. When the stored data is "0", a large current can be read through the bit line port BL_e0; when the stored data is "1", a small current can be read through the bit line port BL_e0.

[0044] In an embodiment of the present application, for the memory cells that are not selected during erase operation and program operation, a selection voltage option can be input to the control gate port CG connected to the memory cells to reduce the risk of interference.

[0045] The following table shows the voltage logic of the operation method of the memory in an embodiment of the present application. In the table, the unselected state during program operation is that the first row is unselected in the same column, and the second row is unselected in the same row. The unselected state during erase operation is also that the first row is unselected in the same column, and the second row is unselected in the same row. In the table, SA represents that the BL is connected to a sense amplifier.

[0046] In an embodiment of the present application, the memory cells of at least part of the rows share the tunnel port TNU with the memory cells of adjacent rows, and the memory cells of at least part of the rows share the control gate port CG with the memory cells of adjacent rows. The bit line ports BL of the memory include odd row bit line ports BL_o and even row bit line ports BL_e, the odd row bit line ports BL_o are used to select the memory cells of odd rows, and the even row bit line ports BL_e are used to select the memory cells of even rows. The tunnel port TNU, the control gate port CG and the word line port WL are used for row selection, and the select line port SL and the bit line port BL are used for column selection.

[0047] In the embodiment shown in FIG. 2, row 0 shares the tunneling port TNU0 with row 1, row 1 shares the control gate port CG port 1 with row 2, and so on. All even rows, such as row 0 and row 2, are selected by even row bit line port BL_e, and all odd rows, such as row 1 and row 3, are selected by odd row bit line port BL_o. FIG. 3 is a schematic diagram of row and column decoding and row and column driving in an embodiment of the present application. Tunneling port TNU, control gate port CG, and word line port WL are used for row selection, and select line port SL and bit line port BL are used for column selection. The required driving voltages are three, namely power supply voltage VDD, positive voltage VPP, and negative voltage VBB. In row decoding, row address signal AD[n:0] and row decoding enable signal EN_Row_dec are input into row decoder. After decoding the row address signal AD[n:0], the row decoder obtains row selection signal Row_sel, which is input into row driver together with row driving enable signal EN_Row_drv. The row driver also inputs positive voltage VPP, negative voltage VBB, and power supply voltage VDD, and is connected to VSS port. The row driver outputs voltage signals of three ports, namely tunneling port TNU, control gate port CG, and word line port WL. In column decoding, column address signal AD[m:0] and row and column decoding enable signal EN_Col_dec are input into row decoder. After decoding the column address signal AD[m:0], the column decoder obtains column selection signal Col_sel, which is input into column driver together with column driving enable signal EN_Col_drv. The column driver also inputs positive voltage VPP, negative voltage VBB, and power supply voltage VDD, and is connected to VSS port. The column driver outputs voltage signals of select line port SL and bit line port BL.

[0048] The storage unit of the present application adopts a structure of four transistors (4T), two NMOS and two PMOS constituting a storage unit. The first active region of the first PMOS, the second active region of the first PMOS, and the first active region of the select transistor and the second active region of the select transistor are located in the N well, and the N well is located between the active region of the first NMOS and the active region of the second NMOS.

[0049] In an embodiment of the present application, the floating gate extends from above the active region of the first NMOS to above the N well, and then to above the active region of the second NMOS.

[0050] In an embodiment of the present application, the area of the active region of the first NMOS is larger than the area of the active region of the second NMOS. Further, the area of the first NMOS is larger than the area of the second NMOS.

[0051] In an embodiment of the present application, the first NMOS of two adjacent rows in the storage array can share one P well, and the second NMOS of two adjacent rows can share one P well. Thus, the chip area of the memory can be saved.

[0052] Figure 4 is a partial layout of a memory array of a memory in an embodiment of the application. The memory array includes a first region 110, a second region 120, a third region 130, a first N-well 142, and a second N-well 144. The first region 110 is a long strip extending in the Y direction in Figure 4, and a plurality of active regions 112 of first NMOS transistors are located in the first region 110. The active regions 112 are N-type regions. The second region 120 is a long strip extending in the Y direction, and a plurality of active regions 122 of first NMOS transistors are located in the second region 120. The active regions 122 are N-type regions. The third region 130 is a long strip extending in the Y direction and located between the first region 110 and the second region 120, and a plurality of active regions 132 of second NMOS transistors are located in the third region 130. The active regions 132 are N-type regions. The first N-well 142 extends in the Y direction and is located between the first region 110 and the third region 130. The second N-well 144 extends in the Y direction and is located between the second region 120 and the third region 130. A plurality of first active regions and a plurality of second active regions of first PMOS transistors and a plurality of first active regions and a plurality of second active regions of select transistors are located in the first N-well 142 and form a P-type region 152. A plurality of first active regions and a plurality of second active regions of first PMOS transistors and a plurality of first active regions and a plurality of second active regions of select transistors are located in the second N-well 144 and form a P-type region 154. In Figure 4, the locations of contact holes of a control gate port CG, contact holes of a bit line port BL, contact holes of a word line port WL, contact holes of a tunneling port TNU, and contact holes of a select line port SL are indicated by arrows.

[0053] In the embodiment shown in Figure 4, the floating gate 162 extends from above the first region 110 to above the first N-well 142 and then to above the third region 130, and the floating gate 164 extends from above the second region 120 to above the second N-well 144 and then to above the third region 130.

[0054] In the embodiment shown in Figure 4, the width of the active regions of the first NMOS transistors is greater than the width of the active regions of the second NMOS transistors, and the width direction is the X direction in Figure 4.

[0055] In summary, the memory of the embodiment of the present application adopts positive and negative pressure design, the maximum voltage required to be borne by the devices in the storage unit is reduced to half of the circuit shown in Fig. 1, the reliability and durability of the storage unit are improved, and the high-voltage device design can be avoided in the peripheral circuit, thereby reducing the area of the peripheral circuit. On the other hand, the storage unit of the embodiment of the present application adopts a 2PMOS+2NMOS unit structure, which can realize the isolation of P-well and N-well, and the area is much smaller than the area required for the isolation of each N-well in the 4PMOS structure shown in Fig. 1. In addition, in the memory of the embodiment of the present application, the active region 112 in the first region 110 shares a P-well, which is equivalent to the active region of the first NMOS transistor of two rows of storage units sharing a control gate port CG in the storage array sharing a P-well. Similarly, the active region 122 in the second region 120 shares a P-well. The active region 132 in the third region 130 also shares a P-well, which is equivalent to the active region of the second NMOS transistor of two rows of storage units sharing a tunneling port TNU in the storage array sharing a P-well, thereby further reducing the area of the storage array. In an embodiment of the present application, the area of the storage unit with a working voltage of 3.3V is about 10 square microns, which is only 1 / 4 of the area of the structure shown in Fig. 1.

[0056] The present application correspondingly provides a programming method of the storage unit data of the memory of any one of the above embodiments, which comprises inputting negative voltage VBB to the control gate port and the tunneling port TNU connected to the selected storage unit, and inputting positive voltage VPP to the bit line port and the word line port connected to the selected storage unit during programming operation.

[0057] The present application correspondingly provides an erasing method of the storage unit data of the memory of any one of the above embodiments, which comprises inputting positive voltage VPP to the control gate port, the bit line port and the word line port connected to the selected storage unit, and inputting negative voltage VBB to the tunneling port TNU connected to the selected storage unit during erasing operation.

[0058] The present application correspondingly provides a reading method of the storage unit data of the memory of any one of the above embodiments, which comprises applying low level to the control gate port, the tunneling port TNU and the word line port connected to the selected storage unit, and inputting power supply voltage VDD to the select line port connected to the selected storage unit during reading operation. The data stored in the selected storage unit is identified by the current size of the bit line connected to the selected storage unit.

[0059] It should be understood that, although the steps in the flowcharts of the present application are shown in a sequence as indicated by arrows, the steps are not necessarily executed in the order as indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not necessarily limited to the order as indicated by the arrows, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the present application can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution of the steps or stages is not necessarily sequential, but can be performed in rotation or alternation with at least some of the other steps or the steps or stages in the other steps.

[0060] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0061] The technical features of the above-described embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features of the above-described embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered to be within the scope of the present specification.

[0062] The above-described embodiments only express several implementation manners of the present application, and the description is specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A memory, comprising: The memory array comprises a plurality of memory cells, each memory cell comprising: a first NMOS transistor comprising an active region and a gate, the active region of the first NMOS transistor being connected to a control gate port to obtain the potential of the control gate port; a second NMOS transistor comprising an active region and a gate, the active region of the second NMOS transistor being connected to a tunneling port to obtain the potential of the tunneling port; a first PMOS transistor comprising a first active region, a second active region and a gate, the first active region of the first PMOS transistor being connected to a bit line port to obtain the potential of the bit line port, the gate of the first NMOS transistor, the gate of the second NMOS transistor and the gate of the first PMOS transistor being connected to each other; a selection transistor being a second PMOS transistor comprising a first active region, a second active region and a gate, the first active region of the selection transistor being connected to a selection line port to obtain the potential of the selection line port, the second active region of the selection transistor being connected to the second active region of the first PMOS transistor, the gate of the selection transistor being connected to a word line port to obtain the potential of the word line port; wherein, in an erase operation, the control gate port, the bit line port and the word line port connected to the selected memory cell input positive voltage, and the tunneling port connected to the selected memory cell inputs negative voltage; in a program operation, the control gate port and the tunneling port connected to the selected memory cell input negative voltage, and the bit line port and the word line port connected to the selected memory cell input positive voltage.

2. The memory of claim 1, wherein, In a read operation, the control gate port, the tunneling port and the word line port connected to the selected memory cell are applied with low level, the selection line port connected to the selected memory cell inputs power voltage, and the current size of the bit line connected to the selected memory cell is used to identify the data stored in the selected memory cell.

3. The memory of claim 1, wherein, The gate of the first NMOS transistor, the gate of the second NMOS transistor and the gate of the first PMOS transistor are connected to each other.

4. The memory of claim 3, wherein, The gate connected to each other is a floating gate, and the first PMOS transistor is a floating gate transistor.

5. The memory of claim 4, wherein, The second active region of the selection transistor and the second active region of the first PMOS transistor share a P-type region.

6. The memory of claim 5, wherein, The memory array comprises memory cells arranged in at least two rows and at least two columns, at least part of the memory cells in a row share the tunneling port with the memory cells in an adjacent row, at least part of the memory cells in a row share the control gate port with the memory cells in an adjacent row, the bit line port is an odd row bit line port or an even row bit line port, the odd row bit line port is used to select the memory cells in an odd row, and the even row bit line port is used to select the memory cells in an even row; the tunneling port, the control gate port and the word line port are used for row selection, and the selection line port, the odd row bit line port and the even row bit line port are used for column selection.

7. The memory of claim 6, wherein, The memory array comprises: a first region being a long strip extending in a first direction, and the active regions of a plurality of first NMOS transistors being located in the first region; a second region being a long strip extending in the first direction, and the active regions of a plurality of first NMOS transistors being located in the second region; a third region extending in the first direction and located between the first region and the second region, active regions of the second NMOS transistors being located in the third region; a first N-well extending in the first direction and located between the first region and the third region; a second N-well extending in the first direction and located between the second region and the third region; wherein the first active regions and the second active regions of the first PMOS transistors and the first active regions and the second active regions of the selection transistors are located in the first N-well, and the first active regions and the second active regions of the first PMOS transistors and the first active regions and the second active regions of the selection transistors are located in the second N-well.

8. The memory of claim 7, wherein, The floating gates extend from above the first region to above the first N-well, and then to above the third region, and the floating gates extend from above the second region to above the second N-well, and then to above the third region.

9. The memory of claim 7, wherein, The active regions of the first NMOS transistors have a width greater than the width of the active regions of the second NMOS transistors, and the width direction is perpendicular to the first direction.

10. The memory of claim 7 or 9, wherein, In the memory array, the first NMOS transistors of at least part of the rows of memory cells share a P-well with the first NMOS transistors of adjacent rows of memory cells, and the second NMOS transistors of at least part of the rows of memory cells share a P-well with the second NMOS transistors of adjacent rows of memory cells.

11. The memory of claim 1, wherein, The first active regions and the second active regions of the first PMOS transistors and the first active regions and the second active regions of the selection transistors of each memory cell are located in an N-well between the active regions of the first NMOS transistors and the active regions of the second NMOS transistors.

12. The memory of claim 7, wherein The active regions of the first NMOS transistors of the first column of memory cells in the memory array are located in the first region; The active regions of the first NMOS transistors of the second column of memory cells in the memory array are located in the second region; The active regions of the second NMOS transistors of the first column of memory cells and the second column of memory cells are both located in the third region; The first active regions and the second active regions of the first PMOS transistors and the first active regions and the second active regions of the selection transistors of the first column of memory cells in the memory array are located in the first N-well; The first active regions and the second active regions of the first PMOS transistors and the first active regions and the second active regions of the selection transistors of the second column of memory cells in the memory array are located in the second N-well.

13. The memory of claim 10, wherein, The first NMOS transistors of at least part of the rows of memory cells share a P-well with the first NMOS transistors of adjacent rows of memory cells specifically as follows: The active regions of the first NMOS transistors of two rows of memory cells sharing a control gate port share a P-well; The second NMOS transistors of at least part of the rows of memory cells share a P-well with the second NMOS transistors of adjacent rows of memory cells specifically as follows: The active regions of the second NMOS transistors of two rows of memory cells sharing a tunnel port TNU share a P-well.

14. The memory of claim 1, wherein, The area of the active region of the first NMOS transistor is greater than the area of the active region of the second NMOS transistor.

15. The memory of claim 1, wherein, The area of the first NMOS transistor is greater than the area of the second NMOS transistor.

16. The memory of any one of claims 1-15, wherein, The memory is an FN tunneling nonvolatile memory.

17. A programming method of the memory cell data of the memory according to any one of claims 1-16, comprising inputting a negative voltage to the control gate port and the tunneling port connected to the selected memory cell, and inputting a positive voltage to the bit line port and the word line port connected to the selected memory cell during a programming operation.

18. An erasing method of the memory cell data of the memory according to any one of claims 1-16, comprising inputting a positive voltage to the control gate port, the bit line port and the word line port connected to the selected memory cell, and inputting a negative voltage to the tunneling port connected to the selected memory cell during an erasing operation.

19. A reading method of the memory cell data of the memory according to any one of claims 1-16, comprising applying a low level to the control gate port, the tunneling port and the word line port connected to the selected memory cell, and inputting a power supply voltage to the select line port connected to the selected memory cell during a reading operation, and identifying the data stored in the selected memory cell by the current size of the bit line connected to the selected memory cell.

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