GAN device having localization marks, voltage conversion apparatus and electronic device

Abstract

Disclosed in the present application are a GaN device having localization marks, a voltage conversion apparatus and an electronic device. A first localization mark is provided by using an end portion of at least one of a gate, a source and a drain as a reference position, and a second localization mark is provided by using an end portion of an interconnect line as a reference position. The gate extends in a second direction, and at least a section of the interconnect line extends in a first direction, which is equivalent to using the first localization mark as a coordinate point in the first direction, and using the second localization mark as a coordinate point in the second direction, so that the first localization mark and the second localization mark can be used in combination to define the address coordinates of different positions on the GaN device. Furthermore, in the process of device testing and analysis, the first localization mark and the second localization mark can be used in combination to achieve rapid recognition and localization of accurate positions of defects or hotspots, thereby improving the analysis efficiency and success rate.

Description

GaN device with positioning mark, voltage conversion device and electronic equipment

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202410980826.2, filed on July 19, 2024, and entitled “GaN device with positioning mark, voltage conversion device and electronic equipment”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor technology, and in particular to a GaN device with positioning mark, a voltage conversion device and an electronic equipment. BACKGROUND

[0004] Traditional silicon (Si) based devices not only have the disadvantage of low energy utilization rate, but also their performance has approached the theoretical limit of silicon material after years of development. Finding and researching semiconductor devices that can replace Si based devices has become an important direction of power electronic technology development in recent years. Various semiconductor devices developed from the third generation semiconductor material gallium nitride (GaN) have developed rapidly. Compared with traditional Si devices, GaN devices can work at higher voltage stress, faster switching frequency, have greater temperature tolerance, and are more suitable for high-frequency and high-power-density application occasions due to their material properties. Moreover, unlike the mechanism of forming a conductive channel through a PN junction in Si based devices, GaN devices form a two-dimensional electron gas (2DEG) conductive channel through the strong spontaneous polarization and piezoelectric polarization effect at the GaN and AlGaN interface. The difference in the conductive channel causes a difference in the conductive mechanism of the device.

[0005] During the process of preparing GaN devices, some defects will be introduced into the GaN devices. After the GaN device is loaded with voltage, leakage will occur at the positions of these defects, and as the current density at the defect position increases, the temperature at the defect position also rises, so the defect position is usually referred to as a hotspot. During the product development and reliability verification stage, the hotspots of the GaN device need to be located for failure analysis.

[0006] Currently, since the front side (i.e. the side away from the substrate) of the GaN device is usually covered by a large area of thick metal layer, it is not conducive to locate hot spots from the front side. Therefore, hot spots are usually located from the back side (i.e. the side with the substrate) of the GaN device. However, after analyzing the hot spots from the back side, due to the thick metal layer covering the front side and the repetitive unit structure of the device, the identified hot spots are usually in a large size area, which makes it difficult to identify the accurate position of the hot spots, thus it is difficult to accurately locate the failure point, and the analysis efficiency and success rate are reduced. SUMMARY

[0007] Embodiments of the present application provide a GaN device with positioning marks, a voltage conversion device and an electronic device, so as to realize fast identification and positioning of the accurate position of defects or hot spots by setting positioning marks, and improve the analysis efficiency and success rate.

[0008] In a first aspect, embodiments of the present application provide a GaN device with positioning marks, comprising: a substrate, a semiconductor stack arranged on the substrate, an electrode layer arranged on the semiconductor stack, a first dielectric layer arranged on the electrode layer, and a first interconnection layer (i.e. Metal-1 layer) arranged on the first dielectric layer, wherein the electrode layer comprises an electrode group, the electrode group comprises a gate and a source and a drain respectively located on both sides of the gate, and the gate, the source and the drain extend along a second direction. The first interconnection layer comprises an interconnection line, and at least part of the sections of the interconnection line extend along a first direction. Furthermore, the GaN device further comprises a first positioning mark and a second positioning mark arranged at a distance from each other, wherein the end of at least one of the gate, the source and the drain is arranged with the first positioning mark correspondingly, and the end of the interconnection line is arranged with the second positioning mark correspondingly. In this way, the end of at least one of the gate, the source and the drain is used as a reference position to set the first positioning mark, and the end of the interconnection line is used as a reference position to set the second positioning mark. Furthermore, in combination with the above-mentioned extension of the gate along the second direction and the extension of at least part of the sections of the interconnection line along the first direction, it is equivalent to using the first positioning mark as a coordinate point in the first direction and using the second positioning mark as a coordinate point in the second direction, so that the first positioning mark and the second positioning mark can be combined with each other to locate the address coordinates of different positions in the GaN device. Based on this, in the process of device testing and analysis, the first positioning mark and the second positioning mark can be combined to locate the accurate position of defects or hot spots in the GaN device, so as to realize fast identification and positioning of the accurate position of defects or hot spots, and further improve the analysis efficiency and success rate.

[0009] Wherein the first direction and the second direction are parallel to the substrate respectively. Furthermore, the first direction and the second direction intersect, for example, the first direction and the second direction are perpendicular to each other.

[0010] In some embodiments, the semiconductor stack can include one or more cell regions, and each cell region can be provided with an electrode group. In addition, at least part of the cell regions can be provided with a first positioning mark correspondingly, and the cell regions can have an overlapping region with the first positioning mark correspondingly provided in the third direction in the extension region of the cell regions in the second direction. In this way, the first positioning mark can be flexibly arranged in the extension region of the cell regions in the second direction.

[0011] In some embodiments, the semiconductor stack can include one or more active regions and a passive region surrounding each active region to isolate the active region by the passive region. In addition, each active region can include one or more cell regions, i.e., each active region is provided with one or more electrode groups, so that each active region is provided with a first positioning mark correspondingly.

[0012] In some examples, the first positioning mark can be arranged in the passive region to reduce the shielding of the first positioning mark by the active region as much as possible, so that the first positioning mark can be more easily identified from the front of the GaN device by an optical microscope (OM), or after polishing the substrate on the back, the first positioning mark can be more easily identified by an infrared (IR) microscope. Alternatively, the first positioning mark can span the active region and the passive region, so that the area of the passive region occupied by the first positioning mark can be reduced, thereby reducing the overall area of the passive region and increasing the density of the active region. Alternatively, the first positioning mark can be arranged in the active region to reduce the occupied area of the passive region.

[0013] In some examples, the second positioning mark can be arranged in the passive region to reduce the shielding of the second positioning mark by the active region as much as possible, so that the second positioning mark can be more easily identified from the front of the GaN device by an optical microscope (OM), or after polishing the substrate on the back, the second positioning mark can be more easily identified by an infrared (IR) microscope. Alternatively, the second positioning mark can span the active region and the passive region, so that the area of the passive region occupied by the second positioning mark can be reduced, thereby reducing the overall area of the passive region and increasing the density of the active region. Alternatively, the second positioning mark can be arranged in the active region to reduce the occupied area of the passive region.

[0014] In some embodiments, in any of the cell regions, the gate, the source and the drain each has a first end and a second end. The first end of at least one of the gate, the source and the drain is provided with a first positioning mark, and the extension area of the first end of at least one of the gate, the source and the drain in the direction away from the second end thereof at least partially overlaps or is misaligned with the corresponding first positioning mark in the third direction perpendicular to the substrate. In this way, the first end of at least one of the gate, the source and the drain can be used to set the position of the first positioning mark, and the flexibility of setting the position of the first positioning mark in this part can be improved.

[0015] In some embodiments, the second end of at least one of the gate, the source and the drain is provided with a first positioning mark, and the extension area of the second end of at least one of the gate, the source and the drain in the direction away from the first end thereof at least partially overlaps or is misaligned with the corresponding first positioning mark in the third direction perpendicular to the substrate. In this way, the second end of at least one of the gate, the source and the drain can be used to set the position of the first positioning mark, and the flexibility of setting the position of the first positioning mark in this part can be improved.

[0016] In some embodiments, any of the active regions is provided with a plurality of cell regions, and the gate of at least part of the cell regions is provided with a first positioning mark. In this way, the first end and / or the second end of the gate of part or all of the cell regions in any of the active regions can be provided with a first positioning mark.

[0017] In some embodiments, in any of the active regions, each of the gates is provided with a first positioning mark. In this way, the first end and / or the second end of the gate of all of the cell regions in any of the active regions can be provided with a first positioning mark.

[0018] In some embodiments, in any of the active regions, at least one gate is provided between the two adjacent gates provided with a first positioning mark. In this way, the first end and / or the second end of the gate of part of the cell regions in any of the active regions can be provided with a first positioning mark.

[0019] In some embodiments, the first positioning mark can be provided at the first end and the second end of any of the gates respectively, and if the first positioning mark of one of the ends cannot be recognized due to process factors, the first positioning mark of the other end can be used for recognition, so as to ensure the positioning accuracy of defects or hot spots.

[0020] In some embodiments, the first positioning marks provided at the first end and the second end of the same gate can be the same or different.

[0021] In some embodiments, the first positioning marks corresponding to different cell regions in the same active region can be different, so that the different cell regions in the same active region can be distinguished by the first positioning marks.

[0022] In some embodiments, the first positioning marks corresponding to part or all of the cell regions in the same active region can be the same, so as to reduce the complexity of patterning the first positioning marks.

[0023] In some embodiments, the first positioning marks corresponding to the cell regions in part or all of the active regions can be the same, further reducing the complexity of patterning the first positioning marks.

[0024] In some embodiments, the first positioning marks corresponding to the cell regions in different active regions can be different, so as to distinguish the different cell regions in different active regions by the first positioning marks.

[0025] In some embodiments, the segments of the interconnection lines extending in the first direction are arranged in the active region, and since the gates in the active region extend in the second direction, the interconnection lines and the gates have intersection points in the third direction, so that the accuracy of locating the address coordinates of different positions in the GaN device can be further improved in combination with the intersection points, the first positioning marks and the second positioning marks. Based on this, in the process of device testing and analysis, the accurate positions of defects or hot spots can be further quickly identified in combination with the first positioning marks and the second positioning marks, and the analysis efficiency and success rate are further improved.

[0026] In addition, the interconnection lines have first end portions and second end portions, the first end portions of the interconnection lines can be provided with the second positioning marks corresponding thereto and do not have overlapping regions with the second positioning marks corresponding thereto in the third direction, and the extension regions of the first end portions of the interconnection lines in the direction away from the second end portions thereof at least partially overlap or are misaligned with the second positioning marks corresponding thereto in the third direction. By such arrangement, the first end portions of the interconnection lines can be used to set the positions of the second positioning marks, and the flexibility of setting the positions of the second positioning marks in this part can be improved.

[0027] Alternatively, the second end portions of the interconnection lines can be provided with the second positioning marks corresponding thereto and do not have overlapping regions with the second positioning marks corresponding thereto in the third direction, and the extension regions of the second end portions of the interconnection lines in the direction away from the first end portions thereof at least partially overlap or are misaligned with the second positioning marks corresponding thereto in the third direction. By such arrangement, the second end portions of the interconnection lines can be used to set the positions of the second positioning marks, and the flexibility of setting the positions of the second positioning marks in this part can be improved.

[0028] In some embodiments, the interconnection lines include a plurality of source interconnection lines and a plurality of drain interconnection lines, the source interconnection lines being connected to the source through source contact holes penetrating through the first dielectric layer, and the drain interconnection lines being connected to the drain through drain contact holes penetrating through the first dielectric layer.

[0029] In some examples, at least part of the source interconnection lines can be provided with the second positioning marks correspondingly. In this way, the positions of the second positioning marks can be set by using the source interconnection lines, and the flexibility of setting the positions of the second positioning marks can be improved.

[0030] In some examples, the end portions of each source interconnection line can be provided with the second positioning marks correspondingly, so that the second positioning marks can be further subdivided based on the source interconnection lines, and the accuracy of identifying the positions of defects or hot spots can be further improved by using the address coordinates of the intersections of the source interconnection lines and the gate in the third direction, and the analysis efficiency and success rate can be further improved. Alternatively, the end portions of part of the source interconnection lines can be provided with the second positioning marks correspondingly, for example, at least one source interconnection line can be spaced between two adjacent source interconnection lines provided with the second positioning marks correspondingly, so as to reduce the number of the second positioning marks corresponding to the source interconnection lines and reduce the patterning complexity.

[0031] In some examples, the first end portions and the second end portions of all or part of the source interconnection lines can be provided with the second positioning marks correspondingly, and if the second positioning marks of one of the end portions cannot be identified due to process factors, the second positioning marks of the other end portion can be used for identification, so as to ensure the positioning accuracy of defects or hot spots. For example, the second positioning marks provided at the first end portions and the second end portions of the same source interconnection line can be the same, so as to reduce the patterning complexity of the second positioning marks. Alternatively, the second positioning marks provided at the first end portions and the second end portions of the same source interconnection line can be different, so as to facilitate the differentiation.

[0032] In yet some examples, the first end portions or the second end portions of all of the source interconnection lines can be provided with the second positioning marks correspondingly. Alternatively, the first end portions or the second end portions of part of the source interconnection lines can be provided with the second positioning marks correspondingly, and the first end portions and the second end portions of another part of the source interconnection lines can be provided with the second positioning marks correspondingly. Alternatively, the first end portions of part of the source interconnection lines can be provided with the second positioning marks correspondingly, and the second end portions of another part of the source interconnection lines can be provided with the second positioning marks correspondingly.

[0033] Exemplarily, the first end portion of any source interconnect line can be provided with a second positioning mark of the same pattern, so that the second positioning mark of the same pattern can be formed, and the complexity of patterning the second positioning mark can be reduced. Alternatively, the first end portion of any source interconnect line can be provided with a second positioning mark of different patterns, so that the second positioning mark of different patterns can be formed, and the different source interconnect lines can be distinguished. Alternatively, the first end portion of some source interconnect lines can be provided with a second positioning mark of the same pattern, and the first end portion of the other source interconnect lines can be provided with a second positioning mark of different patterns.

[0034] Exemplarily, the second end portion of any source interconnect line can be provided with a second positioning mark of the same pattern, so that the second positioning mark of the same pattern can be formed, and the complexity of patterning the second positioning mark can be reduced. Alternatively, the second end portion of any source interconnect line can be provided with a second positioning mark of different patterns, so that the second positioning mark of different patterns can be formed, and the different source interconnect lines can be distinguished. Alternatively, the second end portion of some source interconnect lines can be provided with a second positioning mark of the same pattern, and the second end portion of the other source interconnect lines can be provided with a second positioning mark of different patterns.

[0035] In some embodiments, at least part of the drain interconnect lines can be provided with a second positioning mark. By virtue of the provision, the position of the second positioning mark can be set by the drain interconnect lines, and the flexibility of setting the position of the second positioning mark can be improved.

[0036] In some examples, the end portion of each drain interconnect line can be provided with a second positioning mark, so that the second positioning mark can be further subdivided based on the drain interconnect lines, and the accuracy of identifying the position of defects or hot spots can be further improved by the address coordinates of the intersection of the drain interconnect lines and the gate in the third direction, and the analysis efficiency and success rate can be further improved.

[0037] In some examples, the end portion of part of the drain interconnect lines can also be provided with a second positioning mark, for example, at least one drain interconnect line can be spaced between two adjacent drain interconnect lines provided with a second positioning mark, so that the number of second positioning marks corresponding to the drain interconnect lines can be reduced, and the complexity of patterning can be reduced.

[0038] In some embodiments, the first end and the second end of all or part of the drain interconnect lines can be provided with the second positioning mark respectively, and if the second positioning mark of one of the ends cannot be recognized due to process factors, the second positioning mark of the other end can be used for recognition, so as to ensure the positioning accuracy of defects or hot spots. Alternatively, the first end or the second end of all of the drain interconnect lines can be provided with the second positioning mark. Alternatively, the first end or the second end of part of the drain interconnect lines can be provided with the second positioning mark, and the first end and the second end of the other part of the drain interconnect lines can be provided with the second positioning mark. Alternatively, the first end of part of the drain interconnect lines can be provided with the second positioning mark, and the second end of the other part of the drain interconnect lines can be provided with the second positioning mark.

[0039] Exemplarily, the second positioning marks provided at the first end and the second end of the same drain interconnect line can be the same, so as to reduce the patterning complexity of the part of the second positioning marks 620. Alternatively, the second positioning marks provided at the first end and the second end of the same drain interconnect line can be different, so as to facilitate the differentiation.

[0040] Exemplarily, the second positioning marks provided at the first end of any drain interconnect line can be the same, so that the same pattern can be used to form the part of the second positioning marks, thereby reducing the patterning complexity of the second positioning marks. Alternatively, the second positioning marks provided at the first end of any drain interconnect line can be different, so that different patterns can be used to form the part of the second positioning marks, thereby facilitating the identification of different drain interconnect lines. Alternatively, the second positioning marks provided at the first end of part of the drain interconnect lines can be the same, and the second positioning marks provided at the first end of the other part of the drain interconnect lines can be different.

[0041] Exemplarily, the second positioning marks provided at the second end of any drain interconnect line can be the same, so that the same pattern can be used to form the part of the second positioning marks, thereby reducing the patterning complexity of the second positioning marks. Alternatively, the second positioning marks provided at the second end of any drain interconnect line can be different, so that different patterns can be used to form the part of the second positioning marks, thereby facilitating the identification of different drain interconnect lines. Alternatively, the second positioning marks provided at the second end of part of the drain interconnect lines can be the same, and the second positioning marks provided at the second end of the other part of the drain interconnect lines can be different.

[0042] Exemplarily, the first end portion of any or part of the source interconnection line and the first end portion of any or part of the drain interconnection line can be provided with the same second positioning mark, so as to reduce the patterning complexity of the second positioning mark. Alternatively, the first end portion of any or part of the source interconnection line and the first end portion of any or part of the drain interconnection line can be provided with different second positioning marks, so as to distinguish the first end portion of the source interconnection line and the first end portion of the drain interconnection line by the different second positioning marks.

[0043] Exemplarily, the second end portion of any or part of the source interconnection line and the second end portion of any or part of the drain interconnection line can be provided with the same second positioning mark, so as to reduce the patterning complexity of the second positioning mark. Alternatively, the second end portion of any or part of the source interconnection line and the second end portion of any or part of the drain interconnection line can be provided with different second positioning marks, so as to distinguish the second end portion of the source interconnection line and the second end portion of the drain interconnection line by the different second positioning marks.

[0044] Exemplarily, the number of the source interconnection lines provided with the second positioning mark can be the same as or different from the number of the drain interconnection lines provided with the second positioning mark.

[0045] In some embodiments, the electrode layer can further include a first gate bus line, and the first gate bus line can be located in the non-active region, so as to avoid occupying the area of the active region. In addition, the first gate bus line can be connected to the gate, so as to transmit signals to the gate through the first gate bus line. In order to avoid the first gate bus line from shielding the first positioning mark and the second positioning mark, the first positioning mark and the second positioning mark can not have overlapping regions with the first gate bus line in the third direction, respectively.

[0046] In some embodiments, the first interconnection layer can further include a second gate bus line, and the second gate bus line can be used to connect the gate, so as to transmit signals to the gate through the second gate bus line. In addition, the second gate bus line can be located in the non-active region, and in order to avoid the second gate bus line from shielding the first positioning mark and the second positioning mark, the second gate bus line can not have overlapping regions with the first positioning mark and the second positioning mark in the third direction, respectively.

[0047] In some embodiments, a third positioning mark can be further included, and one or more third positioning marks can be provided for each active region, and the third positioning mark can be provided corresponding to the corner of the active region. In order to distinguish different active regions, the third positioning marks corresponding to different active regions can be different. In this way, the third positioning mark can be provided in the non-active region, so as to reduce the shielding of the third positioning mark by the active region, thereby facilitating the identification of the third positioning mark. Alternatively, the third positioning mark can span the active region and the non-active region.

[0048] Exemplarily, the gate electrode can include a P-GaN layer and a gate conductive layer which are stacked, and the P-GaN layer is located between the gate conductive layer and the semiconductor stack.

[0049] Exemplarily, the source electrode and the drain electrode can be formed of the same layer of conductive material (e.g., metal material), so that the source electrode and the drain electrode can be formed by etching the same conductive layer, thereby reducing the process steps and saving production costs.

[0050] Exemplarily, the electrode layer can further include a field plate, and an insulating layer is arranged between the field plate and the gate conductive layer, and the field plate can cover part or all of the area of the gate electrode in the orthographic projection of the substrate, so that the problem of increased dynamic on-resistance of the GaN device under high voltage is reduced by the field plate, and the voltage resistance of the GaN device is improved. In some examples, the field plate can be electrically connected to the source electrode. Further, the field plate, the source electrode and the drain electrode can be formed of the same layer of conductive material, so that the field plate, the source electrode and the drain electrode can be formed by etching the same conductive layer, thereby reducing the process steps and saving production costs.

[0051] In some embodiments, the first positioning mark is arranged in the same layer as the first interconnection layer. Alternatively, the first positioning mark is arranged in the same layer as the source electrode and the drain electrode. Alternatively, the first positioning mark is arranged in the same layer as the field plate. Alternatively, the first positioning mark is arranged in the same layer as the gate conductive layer. Alternatively, the first positioning mark is arranged in the same layer as the P-GaN layer. By such arrangement, the process steps can be reduced and the production costs can be saved.

[0052] In some embodiments, the second positioning mark is arranged in the same layer as the first interconnection layer. Alternatively, the second positioning mark is arranged in the same layer as the source electrode and the drain electrode. Alternatively, the second positioning mark is arranged in the same layer as the field plate. Alternatively, the second positioning mark is arranged in the same layer as the gate conductive layer. Alternatively, the second positioning mark is arranged in the same layer as the P-GaN layer. By such arrangement, the process steps can be reduced and the production costs can be saved.

[0053] In some embodiments, the third positioning mark is arranged in the same layer as the first interconnection layer. Alternatively, the third positioning mark is arranged in the same layer as the source electrode and the drain electrode. Alternatively, the third positioning mark is arranged in the same layer as the field plate. Alternatively, the third positioning mark is arranged in the same layer as the gate conductive layer. Alternatively, the third positioning mark is arranged in the same layer as the P-GaN layer. By such arrangement, the process steps can be reduced and the production costs can be saved.

[0054] In some embodiments, the pattern of the first positioning mark includes one or a combination of a letter pattern, a number pattern, a character pattern, a matrix pattern, a regular figure pattern, and an irregular figure pattern.

[0055] In some embodiments, the pattern of the second positioning mark comprises one or a combination of a letter pattern, a number pattern, a character pattern, a matrix pattern, a regular figure pattern, and an irregular figure pattern.

[0056] In some embodiments, the pattern of the third positioning mark comprises one or a combination of a letter pattern, a number pattern, a character pattern, a matrix pattern, a regular figure pattern, and an irregular figure pattern.

[0057] In a second aspect, the embodiments of the present application provide a voltage conversion device, which is configured to convert a received voltage to a higher voltage or a lower voltage and then output the converted voltage. The voltage conversion circuit comprises a switching device, which is configured as the GaN device with the positioning mark in the first aspect or the embodiments of the first aspect.

[0058] In a third aspect, the embodiments of the present application further provide an electronic device, which comprises a power-consuming device and the voltage conversion device. The output terminal of the voltage conversion device is connected to the power-consuming device to supply power to the power-consuming device. The voltage conversion device is the voltage conversion device in the second aspect or the embodiments of the second aspect. Exemplarily, the electronic device can be a terminal device, which includes but is not limited to a mobile phone, a notebook computer, a tablet computer (PAD), a television, a television set-top box, a watch, a smart photo frame, a wearable device (such as a smart watch, virtual reality (VR) glasses, a smart bracelet), and the like. Alternatively, the electronic device can also be a communication device, which is configured to supply power to a power-consuming device in the communication device. The power-consuming device can be a computer, a server, a power amplifier, or a hardware single board, and the like.

[0059] In addition, the technical effects of the corresponding solutions in the second aspect and the third aspect can be referred to the technical effects of the corresponding solutions in the first aspect and the second aspect, and the repeated parts will not be described in detail. BRIEF DESCRIPTION OF DRAWINGS

[0060] FIG. 1 is a schematic diagram of a top view structure of a first interconnection layer to a semiconductor stack in a GaN device according to an embodiment of the present application;

[0061] FIG. 2a is a schematic diagram of a 3-dimensional (3D) structure of a first interconnection layer to a substrate in a GaN device according to an embodiment of the present application;

[0062] FIG. 2b is a schematic diagram of a 3D structure of an electrode layer to a substrate in a GaN device according to an embodiment of the present application;

[0063] FIG. 3 is a schematic diagram of a top view structure of a matrix pattern according to an embodiment of the present application;

[0064] Fig. 4 is another top view of the first interconnection layer to the semiconductor stack in the GaN device according to an embodiment of the present application;

[0065] Fig. 5 is another 3D view of the first interconnection layer to the substrate in the GaN device according to an embodiment of the present application;

[0066] Fig. 6 is another top view of the first interconnection layer to the semiconductor stack in the GaN device according to an embodiment of the present application;

[0067] Fig. 7a is another top view of the first interconnection layer to the semiconductor stack in the GaN device according to an embodiment of the present application;

[0068] Fig. 7b is another top view of the first interconnection layer to the semiconductor stack in the GaN device according to an embodiment of the present application;

[0069] Fig. 8a is a partial 3D view of the first interconnection layer to the substrate in the GaN device shown in Fig. 4;

[0070] Fig. 8b is a cross-sectional view along the direction of AA' in Fig. 8a;

[0071] Fig. 8c is a cross-sectional view along the direction of BB' in Fig. 8a;

[0072] Fig. 9 is another top view of the first interconnection layer to the semiconductor stack in the GaN device according to an embodiment of the present application;

[0073] Fig. 10a is another top view of the first interconnection layer to the semiconductor stack in the GaN device according to an embodiment of the present application;

[0074] Fig. 10b is a partial 3D view corresponding to Fig. 10a;

[0075] Fig. 11 is another top view of the first interconnection layer to the semiconductor stack in the GaN device according to an embodiment of the present application;

[0076] Fig. 12 is a top view of the second interconnection layer in the GaN device according to an embodiment of the present application;

[0077] Fig. 13a is a partial 3D view of the second interconnection layer to the substrate in the GaN device according to an embodiment of the present application;

[0078] Fig. 13b is a cross-sectional view along the direction of AA' in Fig. 13a;

[0079] Fig. 13c is a cross-sectional view along the direction of BB' in Fig. 13a;

[0080] Figure 14a is a schematic diagram of another partial 3D structure of the second interconnect layer to the substrate in the GaN device provided in the embodiment of this application;

[0081] Figure 14b is a schematic cross-sectional view of the structure along the AA' direction in Figure 14a;

[0082] Figure 14c is a schematic cross-sectional view of the structure along the BB' direction in Figure 14a.

[0083] Reference numerals: 100 - Substrate; 200 - Semiconductor stack; 210 - GaN layer; 220 - Barrier layer; 300 - Electrode layer; 310 - Electrode group; 321 - Gate; 322 - Source; 323-Drain; 3211-P-GaN layer; 3212-Gate conductive layer; 314 / 314a / 314b-First gate bus; 400-First dielectric layer; 500-First interconnect layer; 510-Interconnect line; 511-Source interconnect line; 512-Drain interconnect line; 513-Source bus; 514-Drain bus; 520-Second gate bus; 521-First sub-gate bus; 522-Second sub-gate bus; 600-Second dielectric layer; 610-First positioning mark; 620-Second positioning mark; 630-Third positioning mark; 700-Second interconnect layer; 321a / 510a / 511a / 512a-First end; 321b / 510b / 511b / 512b-Second end; AA 11 / AA 1n / AA m1 / AA mn - Active region; aa1 / aa2 - Cell region; AX1 - Source contact hole; AX2 - Drain contact hole; BX1 - Source transition hole; BX2 - Drain transition hole; X - First direction; Y - Second direction; Z - Third direction. Detailed Implementation

[0084] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0085] It should be noted that the same reference signs in the drawings of the present application represent the same or similar structures, and thus repeated description thereof will be omitted. The words expressing position and direction described in the present application are described with reference to the drawings, but changes can be made as needed, and the changes are included in the scope of protection of the present application. The drawings of the present application are only used to show the relative positional relationship and do not represent the true proportion.

[0086] The GaN device provided by the embodiment of the present application can be applied to a voltage conversion device for voltage conversion as a power device. The voltage conversion device can be applied as a separate device, for example, the voltage conversion device can be a switching power adapter. Alternatively, the voltage conversion device can also be applied to an electronic device to supply power to a power-consuming device in the electronic device. Exemplarily, the electronic device can be a terminal device, for example, including but not limited to: a mobile phone, a notebook computer, a tablet computer (PAD), a television, a television set-top box, a watch, a smart photo frame, a wearable device (such as a smart watch, virtual reality (VR) glasses, a smart bracelet), etc. Alternatively, the electronic device can also be a communication device, and the power-consuming device can be a computer, a server, a power amplifier, or a hardware single board, etc.

[0087] In specific implementation, the voltage conversion device is usually provided with a switching device, and is also provided with at least one of a capacitor and an inductor, so that the energy storage characteristics of the capacitor and the inductor can be utilized, and the on and off of the switching device can be controlled in combination with a switching signal, so as to transmit the input electric energy to the power-consuming device through the capacitor (or the inductor).

[0088] The GaN device based on the AlGaN / GaN heterojunction HEMT lateral structure has excellent characteristics such as high electron mobility, high 2DEG surface density, high chemical stability, high frequency, and high power, so that the GaN device has obvious advantages as a switching device, so that the GaN device can be used as the above-mentioned switching device and applied to the voltage conversion device. Moreover, the embodiment of the present application provides a positioning mark in the GaN device. Based on this, when the hot spot of the GaN device is identified in the product development and reliability verification stage, the positioning mark can be used to locate the position of the hot spot, so as to identify the accurate position of the hot spot and improve the analysis efficiency and success rate. It can be understood that the GaN device in the embodiment of the present application is not only suitable for GaN HEMT lateral devices, but also suitable for other semiconductor devices with similar structures, which are not limited by the present application.

[0089] FIG. 1 is a schematic diagram of a top view of a first interconnection layer to a semiconductor stack in a GaN device according to an embodiment of the present application, FIG. 2a is a schematic diagram of a 3D structure of the first interconnection layer to a substrate in a GaN device according to an embodiment of the present application, FIG. 2b is a schematic diagram of a 3D structure of an electrode layer to a substrate in a GaN device according to an embodiment of the present application. Referring to FIGS. 1-2b, the GaN device according to an embodiment of the present application can include a substrate 100. Exemplarily, the substrate 100 can be made of, but not limited to, silicon (Si), sapphire, diamond, silicon carbide (SiC), gallium nitride (GaN), or the like.

[0090] A semiconductor stack 200 is disposed on the substrate 100, and the semiconductor stack 200 serves as a functional layer of the GaN device and is used to form a 2DEG conduction channel. Exemplarily, the semiconductor stack 200 can include a GaN layer 210 and a barrier layer 220 which are stacked, and the GaN layer 210 is located between the barrier layer 220 and the substrate 100, so that a 2DEG conduction channel can be formed at the contact surface of the GaN layer 210 and the barrier layer 220. Exemplarily, the barrier layer 220 can be an AlGaN barrier layer, an AlN barrier layer, or an InAlN barrier layer. It can be understood that if the lattice constant of the substrate 100 is different from that of the GaN layer 210, lattice mismatch will occur, which will cause crystal defects in the GaN layer 210. Therefore, a buffer layer can be disposed between the GaN layer 210 and the substrate 100 to reduce the crystal defects in the GaN layer 210. In addition, the buffer layer is an optional structure layer, and the buffer layer can be set according to the need during the process preparation. For example, when the influence of the lattice constant conflict between the GaN layer 210 and the substrate 100 on the GaN layer 210 is small, the buffer layer can not be set, and the GaN layer 210 can be directly formed on the substrate 100. When the influence of the lattice constant conflict between the GaN layer 210 and the substrate 100 on the GaN layer 210 is large, the GaN layer 210 cannot be directly formed on the substrate 100, and the buffer layer can be set to isolate the substrate 100 from the GaN layer 210. In addition, the material of the buffer layer can be selected according to the material of the substrate 100. For example, the buffer layer can include, but not limited to, a single layer or a multi-layer structure composed of one or more of GaN, AlN, and AlGaN, which is not limited herein.

[0091] The semiconductor stack 200 is provided with an electrode layer 300, the electrode layer 300 includes an electrode group 310, the electrode group 310 includes a gate electrode 321 and a source electrode 322 and a drain electrode 323 respectively located on both sides of the gate electrode 321. Among them, the gate electrode 321, the source electrode 322 and the drain electrode 323 are respectively used to connect an external circuit, and the gate electrode 321 is used to control the on-off of the 2DEG conduction channel. When the gate electrode 321 controls the 2DEG conduction channel to be turned on, the GaN device is in a conduction state, and signals (or also can be called as current) can be transmitted between the source electrode 322 and the drain electrode 323. When the gate electrode 321 controls the 2DEG conduction channel to be turned off, the GaN device is in an off state, and signals (or also can be called as current) cannot be transmitted between the source electrode 322 and the drain electrode 323. Moreover, the gate electrode 321, the source electrode 322 and the drain electrode 323 can respectively extend along a second direction Y and arrange along a first direction X. Among them, the first direction X and the second direction Y are intersected (for example, perpendicular), and the first direction X and the second direction Y are respectively parallel to the substrate 100.

[0092] In a specific implementation, one or more electrode groups 310 can be provided on the semiconductor stack 200. When multiple electrode groups 310 are provided on the semiconductor stack 200, some adjacent electrode groups 310 can share the drain electrode 323 to reduce the area occupied by the drain electrode 323, and some adjacent electrode groups 310 can share the source electrode 322 to reduce the area occupied by the source electrode 322. For example, referring to FIGS. 1 to 2b, two electrode groups 310 are provided on the semiconductor stack 200, and the two electrode groups 310 share the drain electrode 323, that is, two gate electrodes 321 are arranged between two source electrodes 322, and one drain electrode 323 is arranged between the two gate electrodes 321. Of course, any adjacent electrode group 310 can not share the source electrode 322 or the drain electrode 323, which can be determined according to the needs of the actual application scene, which is not limited here.

[0093] Exemplarily, the gate electrode 321 can include a P-GaN layer 3211 and a gate electrode conduction layer 3212 arranged in a stack, wherein the P-GaN layer 3211 is located between the gate electrode conduction layer 3212 and the semiconductor stack 200 (for example, the barrier layer 220). Exemplarily, the material of the gate electrode conduction layer 3212 includes but is not limited to: a single-layer or multi-layer structure composed of one or more of metal nitrides, metal materials, for example, the metal nitride includes but is not limited to TiN, the metal material includes but is not limited to an alloy of one or more of W, Ni, Au and Pt, or an alloy containing metal W, Ni, Au or Pt.

[0094] Further, the source electrode 322 and the drain electrode 323 can be formed of the same layer of conductive material (e.g., metal material), so that the source electrode 322 and the drain electrode 323 can be formed by etching the same layer of conductive material, thereby reducing the process steps and saving the production cost. Exemplarily, the metal material forming the source electrode 322 and the drain electrode 323 can include, but is not limited to, an alloy of one or more of Ag, Ti, Al, Mg, Ni, Au, Pt, and Pd, or an alloy containing the metal Ag, Ti, Al, Mg, Ni, Au, Pt, and Pd.

[0095] It can be understood that the electrode layer can further include a field plate, the field plate and the gate conductive layer are provided with an insulating layer, and the field plate can cover part or all of the area of the gate in the orthographic projection of the substrate, so as to reduce the problem of increased dynamic on-resistance of the GaN device under high voltage and improve the voltage withstand capability of the GaN device. In some examples, the field plate can be electrically connected to the source electrode. Further, the field plate, the source electrode, and the drain electrode can be formed of the same layer of conductive material, so that the field plate, the source electrode, and the drain electrode can be formed by etching the same layer of conductive material, thereby reducing the process steps and saving the production cost.

[0096] The electrode layer 300 further sequentially has a first dielectric layer and a first interconnection layer 500 (also referred to as Metal-1 layer) disposed thereon, i.e., the first dielectric layer is disposed between the first interconnection layer 500 and the electrode layer 300, and can insulate and protect the electrode layer 300 by the first dielectric layer. Exemplarily, the material of the first dielectric layer includes, but is not limited to, silicon dioxide (SiO2), silicon carbon oxide (SiCO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon carbon oxynitride (SiOCN), or a combination thereof. The material of the first interconnection layer 500 is a conductive material, which includes, but is not limited to, a metal material.

[0097] Exemplarily, the first interconnection layer 500 can include an interconnection line 510, at least part of the sections of the interconnection line 510 extend along the first direction X. Exemplarily, the sections of the interconnection line 510 extending along the first direction X have an overlapping area with the gate 321, the source electrode 322, and the drain electrode 323 in the third direction Z, i.e., in the third direction Z, the sections of the interconnection line 510 extending along the first direction X have intersection points with the gate 321, the source electrode 322, and the drain electrode 323. In some examples, all sections of the interconnection line 510 extend along the first direction X. In other examples, part of the sections of the interconnection line 510 extend along the first direction X, and the remaining sections of the interconnection line 510 can be arranged in a curved or bent manner for electrical connection or avoidance. In addition, the third direction Z is perpendicular to the substrate 100.

[0098] Referring to FIG. 1, the GaN device provided by the embodiment of the present application further comprises a first positioning mark 610 and a second positioning mark 620, wherein the first positioning mark 610 is arranged at the end of the gate 321, and the second positioning mark 620 is arranged at the end of the interconnection line 510. In this way, the end of the gate 321 can be used as a reference position to arrange the first positioning mark 610, and the end of the interconnection line 510 can be used as a reference position to arrange the second positioning mark 620. In combination with the above-mentioned extension of the gate 321 along the second direction Y and the extension of at least part of the interconnection line 510 along the first direction X, the first positioning mark 610 can be used as a coordinate point along the first direction X, and the second positioning mark 620 can be used as a coordinate point along the second direction Y. Therefore, the first positioning mark 610 and the second positioning mark 620 can be used to locate the address coordinates of different positions in the GaN device. Based on this, the first positioning mark 610 and the second positioning mark 620 can be used to locate the precise position of defects or hot spots in the GaN device during the device testing and analysis process, so as to realize the rapid identification and positioning of the precise position of defects or hot spots, and further improve the analysis efficiency and success rate.

[0099] In specific implementation, the pattern of the first positioning mark 610 and the second positioning mark 620 includes but is not limited to one or a combination of a letter pattern, a number pattern, a word pattern, a matrix pattern, a regular figure pattern, and an irregular figure pattern. In addition, the pattern of the first positioning mark 610 and the second positioning mark 620 can be the same or different. It can be understood that the pattern of the first positioning mark 610 and the second positioning mark 620 can also be other identifiable patterns, which are not limited in the present application.

[0100] In some examples, the number pattern includes but is not limited to Arabic numerals (e.g., 1, 2, 3, etc.), Roman numerals (e.g., I, II, III, etc.), etc. For example, referring to FIG. 1, the first positioning mark 610 arranged at the end of one gate 321 is taken as an example of Arabic numeral “1”, and the second positioning mark 620 arranged at the end of the interconnection line 510 is taken as an example of Arabic numerals “1” and “2”.

[0101] In some examples, the letter pattern includes but is not limited to one English letter or a combination pattern of multiple same or different English letters, wherein the English letter can be in uppercase or lowercase. For example, the first positioning mark 610 arranged at the end of one gate 321 is taken as an example of uppercase letter “A”, and the second positioning mark 620 arranged at the end of the interconnection line 510 is taken as an example of uppercase letters “A” and “B”.

[0102] In some examples, the character pattern, for example, includes but is not limited to Chinese characters, which can be displayed in various fonts such as Kai Ti, Song Ti, etc.

[0103] In some examples, the matrix pattern, for example, includes but is not limited to a plurality of blocks arranged in an array, and some blocks are filled with a material while the rest of the blocks are not filled with the material to distinguish different matrix patterns. For example, taking a matrix pattern with a 3x3 grid of blocks as an example, referring to FIG. 3, which is a schematic diagram of a top view of a matrix pattern according to an embodiment of the present application, the matrix pattern shown in (a) of FIG. 3 does not fill a block (for example, the block shown by the dashed square) in the first row and the first column with a material, and the remaining eight blocks (for example, the blocks shown by the black squares) are filled with a material, so that the pattern formed by the remaining eight blocks can be identified. The matrix pattern shown in (b) of FIG. 3 does not fill a block (for example, the block shown by the dashed square) in the first row and the second column with a material, and the remaining eight blocks (for example, the blocks shown by the black squares) are filled with a material, so that the pattern formed by the remaining eight blocks can be identified. The matrix pattern shown in (c) of FIG. 3 does not fill a block (for example, the block shown by the dashed square) in the first row and the third column with a material, and the remaining eight blocks (for example, the blocks shown by the black squares) are filled with a material, so that the pattern formed by the remaining eight blocks can be identified. The matrix pattern shown in (d) of FIG. 3 does not fill a block (for example, the block shown by the dashed square) in the second row and the first column with a material, and the remaining eight blocks (for example, the blocks shown by the black squares) are filled with a material, so that the pattern formed by the remaining eight blocks can be identified. The matrix pattern shown in (e) of FIG. 3 does not fill a block (for example, the block shown by the dashed square) in the second row and the second column with a material, and the remaining eight blocks (for example, the blocks shown by the black squares) are filled with a material, so that the pattern formed by the remaining eight blocks can be identified. The matrix pattern shown in (f) of FIG. 3 does not fill a block (for example, the block shown by the dashed square) in the second row and the third column with a material, and the remaining eight blocks (for example, the blocks shown by the black squares) are filled with a material, so that the pattern formed by the remaining eight blocks can be identified. Based on this, the matrix pattern shown in (a) of FIG. 3 can be arranged at the end of one gate line, the matrix pattern shown in (b) of FIG. 3 can be arranged at the end of another gate line, the matrix pattern shown in (c) of FIG. 3 can be arranged at the end of one interconnection line, and the matrix pattern shown in (d) of FIG. 3 can be arranged at the end of another interconnection line, and the rest can be similarly deduced, which will not be described herein. In addition, the blocks shown by the dashed squares in FIG. 3 represent that the blocks do not actually exist, and the blocks shown by the black squares represent that the blocks actually exist. It can be understood that, in actual applications, the above-mentioned method of selecting one block in the 3x3 grid of blocks not to be filled with a material can also be used to select two, three or more blocks in the 3x3 grid of blocks not to be filled with a material as an encoding method of the positioning mark.Of course, the blocks in the matrix pattern are not limited to the 3x3 nine-square grid blocks. Other arrangements and quantities of blocks can also be adopted, which can be specifically determined according to the actual application scenario, and this application does not limit it.

[0104] In some examples, the regular graphic patterns include, but are not limited to, a circle, an ellipse, a triangle, a square, a rectangle, and other polygons, a "+" shape, a "×" shape, a "米" shape, etc.

[0105] In some examples, the irregular graphic patterns include, but are not limited to, a star shape, a heart shape, a crescent shape, a cloud shape, etc.

[0106] In specific implementation, the first positioning mark 610 can be set in the same layer as the first interconnect layer 500, that is, the first positioning mark 610 can be formed by the first interconnect layer 500, so that the first positioning mark 610 and the interconnect line 510 can be formed by etching the same conductive layer, so as to reduce the process steps and save production costs. Alternatively, the first positioning mark 610 can also be set in the same layer as the source electrode 322 and the drain electrode 323, that is, the first positioning mark 610, the source electrode 322, and the drain electrode 323 are formed by the same conductive layer. Alternatively, the first positioning mark 610 can also be set in the same layer as the field plate, that is, the first positioning mark 610 and the field plate are formed by the same conductive layer. Alternatively, the first positioning mark 610 can also be set in the same layer as the gate conductive layer 3212, that is, the first positioning mark 610 and the gate conductive layer 3212 are formed by the same conductive layer. Alternatively, the first positioning mark 610 can also be set in the same layer as the P-GaN layer 3211, that is, the first positioning mark 610 and the P-GaN layer 3211 are formed by the same film layer.

[0107] In specific implementation, the second positioning mark 620 can be set in the same layer as the first interconnect layer 500, that is, the second positioning mark 620 can be formed by the first interconnect layer 500, so that the second positioning mark 620 and the interconnect line 510 can be formed by etching the same conductive layer, so as to reduce the process steps and save production costs. Alternatively, the second positioning mark 620 can also be set in the same layer as the source electrode 322 and the drain electrode 323, that is, the second positioning mark 620, the source electrode 322, and the drain electrode 323 are formed by the same conductive layer. Alternatively, the second positioning mark 620 can also be set in the same layer as the field plate, that is, the second positioning mark 620 and the field plate are formed by the same conductive layer. Alternatively, the second positioning mark 620 can also be set in the same layer as the gate conductive layer 3212, that is, the second positioning mark 620 and the gate conductive layer 3212 are formed by the same conductive layer. Alternatively, the second positioning mark 620 can also be set in the same layer as the P-GaN layer 3211, that is, the second positioning mark 620 and the P-GaN layer 3211 are formed by the same film layer.

[0108] Continuing to refer to FIG. 1, one or more electrode groups 310 can be disposed on the semiconductor stack 200, and a cell region can be defined on the semiconductor stack 200 by the electrode group 310, so that the semiconductor stack 200 can include one or more cell regions, and each cell region is provided with an electrode group 310. The region where the source 322 and the drain 323 in the electrode group 310 are located and the region between the source 322 and the drain 323 can be used as a cell region. For example, referring to FIG. 1, two electrode groups 310 are disposed on the semiconductor stack 200, and two cell regions aal and aa2 are defined on the semiconductor stack 200. In addition, since the first positioning mark 610 is disposed at the end of the gate 321, the cell region aal can be provided with the first positioning mark 610 (for example, "1" in FIG. 1) corresponding thereto, and the cell region aa2 can be provided with the first positioning mark 610 (for example, "A" in FIG. 1) corresponding thereto. In addition, the extension region Sa1 of the cell region aal in the second direction Y has an overlapping region with the first positioning mark 610 (for example, "1" in FIG. 1) provided corresponding thereto in the third direction Z, and the extension region Sa2 of the cell region aa2 in the second direction Y has an overlapping region with the first positioning mark 610 (for example, "A" in FIG. 1) provided corresponding thereto in the third direction Z. In this way, the first positioning mark 610 can be flexibly disposed in the extension region of the cell region in the second direction Y to mark the position of the end of the gate 321. Alternatively, some cell regions can be provided with corresponding first positioning marks 610, and some cell regions can not be provided with corresponding first positioning marks 610.

[0109] In some examples, the first positioning marks 610 corresponding to different cell regions can be different, so that different cell regions can be distinguished by the first positioning marks 610. For example, referring to FIG. 1, the first positioning mark 610 corresponding to the cell region aal is "1", and the first positioning mark 610 corresponding to the cell region aa2 is "A". Alternatively, the first positioning marks 610 corresponding to some or all cell regions can be the same, so as to reduce the complexity of patterning the first positioning marks 610.

[0110] FIG. 4 is another top view of the first interconnection layer to the semiconductor stack in the GaN device according to an embodiment of the present application, and FIG. 5 is another 3D view of the first interconnection layer to the substrate in the GaN device according to an embodiment of the present application. Referring to FIGS. 4 and 5, the semiconductor stack 200 can include m*n active regions AA 11 ~AA mn and passive regions surrounding each active region AA 11 ~AA mn , that is, the plurality of active regions AA 11 ~AA mnThe active regions are isolated from each other, so that the 2DEG conduction channels of different active regions are independent of each other. For example, ion implantation can be used to form the passive regions in the semiconductor stack 200. Alternatively, the passive regions can be isolated by forming a trench isolation structure, for example, the trench isolation structure can be formed as a shallow trench isolation (STI) structure, that is, the STI process can be used to form the trench isolation structure. Alternatively, the trench isolation structure can also be formed as a deep trench isolation (DTI) structure, that is, the DTI process can be used to form the trench isolation structure. It can be understood that FIGS. 4 and 5 exemplarily show AA 11 ~AA mn The region enclosed by the dashed box can be an active region, and the 2DEG conduction channel can be formed in the active region. The active region AA 11 ~AA mn The region outside the dashed box can be a passive region. In addition, m is an integer greater than or equal to 1, n is an integer greater than or equal to 1, and m*n is an integer greater than or equal to 1.

[0111] Referring to FIGS. 4 and 5, the first positioning mark 610 can be disposed in the passive region, that is, the orthographic projection of the first positioning mark 610 on the substrate 100 falls in the orthographic projection of the passive region on the substrate 100, so that the active region can reduce the shielding of the first positioning mark 610 as much as possible, so that the first positioning mark 610 can be more easily identified by OM from the front of the GaN device, or after the substrate 100 on the back is polished, the first positioning mark 610 can be more easily identified by IR microscope. Alternatively, the first positioning mark 610 can span the active region and the passive region, that is, a part of the first positioning mark 610 falls in the orthographic projection of the active region on the substrate 100, and another part of the first positioning mark 610 falls in the orthographic projection of the passive region on the substrate 100, so that the area of the passive region occupied by the first positioning mark 610 can be reduced, and the overall area of the passive region can be reduced, and the density of the active region can be increased. Alternatively, the first positioning mark 610 can be disposed in the active region to reduce the occupied area of the passive region.

[0112] Referring to FIG. 4 and FIG. 5, the second positioning mark 620 can be disposed in the non-active region, i.e., the orthographic projection of the second positioning mark 620 on the substrate 100 falls in the non-active region on the orthographic projection of the substrate 100, so that the second positioning mark 620 can be more easily recognized from the front of the GaN device by an optical microscope (OM) or can be more easily recognized by an infrared (IR) microscope after polishing the back of the substrate 100. Alternatively, the second positioning mark 620 can span the active region and the non-active region, i.e., part of the second positioning mark 620 on the orthographic projection of the substrate 100 falls in the active region on the orthographic projection of the substrate 100, and another part of the second positioning mark 620 on the orthographic projection of the substrate 100 falls in the non-active region on the orthographic projection of the substrate 100, so that the area of the non-active region occupied by the second positioning mark 620 can be reduced, thereby reducing the overall area of the non-active region and increasing the active region density. Alternatively, the second positioning mark 620 can be disposed in the active region to reduce the occupied area of the non-active region.

[0113] Referring back to FIG. 4 and FIG. 5, one or more electrode groups 310 can be disposed in each active region AA 11 ~AA mn In some embodiments, when a plurality of electrode groups 310 are disposed in the active region AA 11 ~AA mn , one or more cell regions can be provided in each active region AA 11 ~AA mn . In some embodiments, when a plurality of electrode groups 310 are disposed in the active region AA 11 ~AA mn , some adjacent electrode groups 310 can share a source electrode 322 or a drain electrode 323, so that the occupied area of the source electrode 322 or the drain electrode 323 can be reduced. Alternatively, adjacent electrode groups 310 can not share a source electrode 322 or a drain electrode 323.

[0114] In some examples, the first positioning mark 610 corresponding to different cell regions in the same active region can be different, so that the different cell regions in the same active region can be distinguished by the first positioning mark 610. For example, referring to FIG. 4 and FIG. 5, taking the active region AA 11 as an example, the first positioning mark 610 corresponding to the cell region aa1 in the active region AA 11 is “1”, and the first positioning mark 610 corresponding to the cell region aa2 in the active region AA 11 is “A”. Alternatively, the first positioning mark 610 corresponding to part or all of the cell regions in the same active region can be the same, so as to reduce the complexity of patterning the first positioning mark 610.

[0115] In some examples, the first positioning marks 610 corresponding to the cell regions in part or all of the active regions can be made the same, further reducing the complexity of patterning the first positioning marks 610. For example, referring to FIGS. 4 and 5, the first positioning marks 610 corresponding to the cell regions aal in the active region AA 11 ~ AA mn are all the same as "1", and the first positioning marks 610 corresponding to the cell regions aa2 are all the same as "A". Alternatively, the first positioning marks 610 corresponding to the cell regions in different active regions can also be made different to distinguish different cell regions in different active regions using the first positioning marks 610. For example, FIG. 6 is another top view structural schematic diagram of a first interconnection layer to a semiconductor stack in a GaN device according to an embodiment of the present application. Referring to FIG. 6, the first positioning marks 610 corresponding to the cell regions aal in the active region AA 11 are "1" and "5", and the first positioning marks 610 corresponding to the cell regions aa2 are "2" and "6". The first positioning marks 610 corresponding to the cell regions aal in the active region AA 1n are "3" and "7", and the first positioning marks 610 corresponding to the cell regions aa2 are "4" and "8". The first positioning marks 610 corresponding to the cell regions aal in the active region AA m1 are "A" and "E", and the first positioning marks 610 corresponding to the cell regions aa2 are "B" and "F". The first positioning marks 610 corresponding to the cell regions aal in the active region AA mn are "C" and "G", and the first positioning marks 610 corresponding to the cell regions aa2 are "D" and "H".

[0116] Referring back to FIGS. 1, 4-6, the gate 321 in any cell region has a first end 321a and a second end 321b in the extension direction (i.e., the second direction Y) of the gate 321, i.e., the area between the first end 321a and the second end 321b of the gate 321 is formed as a solid part. In some examples, the first positioning marks 610 can be provided at the first end 321a and the second end 321b of any gate 321, respectively. If the first positioning mark 610 of one of the ends cannot be recognized due to process factors, the first positioning mark 610 of the other end can be used for recognition, ensuring the positioning accuracy of defects or hot spots. For example, the first positioning marks 610 corresponding to the first end 321a and the second end 321b of the same gate 321 can be made the same. For example, referring to FIG. 4, the first positioning marks 610 corresponding to the first end 321a and the second end 321b of the gate 321 in the active region AA 11For example, the first end portion 321a and the second end portion 321b of the gate 321 in the cell region aa1 are both provided with the first positioning mark 610 with the same value of "1", and the first end portion 321a and the second end portion 321b of the gate 321 in the cell region aa2 are both provided with the first positioning mark 610 with the same value of "A". Alternatively, the first positioning mark 610 provided at the first end portion 321a and the second end portion 321b of the same gate 321 can be different. For example, referring to FIG. 6, the first positioning mark 610 provided at the first end portion 321a of the gate 321 in the active region AA1 is "1", and the first positioning mark 610 provided at the second end portion 321b of the gate 321 in the active region AA1 is "5". The first positioning mark 610 provided at the first end portion 321a of the gate 321 in the active region AA2 is "2", and the first positioning mark 610 provided at the second end portion 321b of the gate 321 in the active region AA2 is "6". 11 For example, the first end portion 321a of the gate 321 in the cell region aa1 is provided with the first positioning mark 610 with the value of "1", and the second end portion 321b of the gate 321 in the cell region aa1 is provided with the first positioning mark 610 with the value of "5". The first end portion 321a of the gate 321 in the cell region aa2 is provided with the first positioning mark 610 with the value of "2", and the second end portion 321b of the gate 321 in the cell region aa2 is provided with the first positioning mark 610 with the value of "6". In some other examples, the first positioning mark 610 can be provided only at the first end portion 321a or the second end portion 321b of the gate 321, which can reduce the number of the first positioning mark 610 and the difficulty of patterning the first positioning mark 610.

[0117] When the first end portion 321a of the gate 321 is provided with the first positioning mark 610, the first end portion 321a of the gate 321 can not overlap the first positioning mark 610 provided correspondingly in the third direction Z, and the extension area of the first end portion 321a of the gate 321 in the direction away from the second end portion 321b can at least partially overlap the first positioning mark 610 provided correspondingly in the third direction Z. For example, referring to FIG. 1, FIG. 4 and FIG. 6, in the third direction Z, the extension area 321as of the first end portion 321a of the gate 321 in the direction away from the second end portion 321b can cover the entire area of the first positioning mark 610 provided correspondingly. Alternatively, in the third direction Z, the extension area of the first end portion 321a of the gate 321 in the direction away from the second end portion 321b can cover part of the area of the first positioning mark 610 provided correspondingly. In this way, the first positioning mark 610 can be provided in the extension direction of the first end portion 321a, so as to be arranged adjacent to the first end portion 321a of the gate 321, and thus the first positioning mark 610 can be used to accurately mark the position of the first end portion 321a of the gate 321.

[0118] Alternatively, the extension region of the second end of the gate away from the direction of the first end of the gate can be misaligned with the corresponding first positioning mark in the third direction, i.e., the extension region of the second end of the gate away from the direction of the first end of the gate does not overlap with the corresponding first positioning mark in the third direction. With this arrangement, the first positioning mark can be arranged to be misaligned with the extension direction of the second end of the gate, but arranged on one side of the extension region of the second end of the gate, so that the first positioning mark can be arranged adjacent to the second end of the gate, and the first positioning mark can be used to accurately mark the position of the second end of the gate.

[0119] When the first positioning mark 610 is arranged corresponding to the second end 321b of the gate 321, the second end 321b of the gate 321 can not overlap with the corresponding first positioning mark 610 in the third direction Z, and the extension region of the second end 321b of the gate 321 away from the direction of the first end 321a of the gate 321 at least partially overlaps with the corresponding first positioning mark 610 in the third direction Z. For example, referring to FIGS. 1, 4-6, in the third direction Z, the extension region 321bs of the second end 321b of the gate 321 away from the direction of the first end 321a of the gate 321 can cover the entire region of the corresponding first positioning mark 610. Alternatively, in the third direction Z, the extension region of the second end 321b of the gate 321 away from the direction of the first end 321a of the gate 321 can cover part of the region of the corresponding first positioning mark 610. With this arrangement, the first positioning mark 610 can be arranged in the extension direction of the second end 321b, so that the first positioning mark 610 can be arranged adjacent to the second end 321b of the gate 321, and the first positioning mark 610 can be used to accurately mark the position of the second end 321b of the gate 321.

[0120] Alternatively, the extension region of the second end of the gate away from the direction of the first end of the gate can be misaligned with the corresponding first positioning mark in the third direction, i.e., the extension region of the second end of the gate away from the direction of the first end of the gate does not overlap with the corresponding first positioning mark in the third direction. With this arrangement, the first positioning mark can be arranged to be misaligned with the extension direction of the second end of the gate, but arranged on one side of the extension region of the second end of the gate, so that the first positioning mark can be arranged adjacent to the second end of the gate, and the first positioning mark can be used to accurately mark the position of the second end of the gate.

[0121] It is worth mentioning that the extension area 321as of the first end portion 321a of the gate 321 away from the second end portion 321b and the extension area 321bs of the second end portion 321b of the gate 321 away from the first end portion 321a can be determined as dummy areas (i.e. non-physical areas) or physical areas according to the specific structure of the GaN device. In addition, the first end portion 321a and / or the second end portion 321b of the gate 321 described above can be aligned with the edge of the active area in the third direction Z, or the first end portion 321a and / or the second end portion 321b of the gate 321 described above can also extend to the edge of the active area and have a certain distance from the edge of the active area, i.e. the first end portion 321a and / or the second end portion 321b of the gate 321 does not cross the edge of the active area and is also not aligned with the edge of the active area in the third direction Z.

[0122] Continuing to refer to 4 and Fig. 5, any active area AA 11 ~ AA mn , the first positioning mark 610 corresponding to each gate 321 can be provided, so that as many first positioning marks 610 corresponding to the gate 321 can be provided as possible, and the coordinates in the first direction X can be further subdivided, and the positioning accuracy of defects or hot spots can be further improved. Alternatively, in any active area AA 11 ~ AA mn , the adjacent two gates 321 corresponding to the first positioning mark 610 can also be separated by one or more gates 321, so as to reduce the number of first positioning marks 610 and reduce the difficulty of patterning.

[0123] Fig. 7a is another top view structural schematic diagram of the first interconnection layer to the semiconductor stack in the GaN device provided by the embodiments of the present application. Referring to Fig. 7a, the electrode layer 300 can further include a plurality of first gate buses 314. The first gate buses 314 are located in the passive area, i.e. the orthographic projection of the first gate buses 314 falls in the orthographic projection of the passive area on the substrate 100, which can avoid the first gate buses 314 occupying the active area. In addition, the first gate buses are connected with the gates 321 to transmit signals to the gates 321 through the first gate buses. Exemplarily, the first end portion 321a of all the gates 321 in the same active area can be connected with the first gate buses 314, so that the gates 321 can be arranged as fingers.

[0124] In some examples, the first gate buses 314 can be arranged as long strips extending in the first direction X, so that the active areas (for example AA 11 ~ AA 1nThe first gate bus 314 to which the gate 321 in the first active region AA 11 The first gate bus 314 to which the gate 321 in the first active region AA 1n The first gate bus 314 to which the gate 321 in the first active region AA

[0125] To avoid the first gate bus 314 from shielding the first positioning mark 610 and the second positioning mark 620, the first positioning mark 610 and the second positioning mark 620 can be respectively arranged without overlapping with the first gate bus 314 in the third direction Z, i.e. the orthographic projection of the first positioning mark 610 and the second positioning mark 620 on the substrate 100 does not overlap with the orthographic projection of the first gate bus 314 on the substrate 100. Exemplarily, when the first gate bus 314 has a segment extending in the first direction X, for the first positioning mark 610 arranged adjacent to the segment of the first gate bus 314 extending in the first direction X, the part of the first positioning mark 610 can be arranged on the side of the segment of the first gate bus 314 extending in the first direction X facing the active region, so as to avoid the segment of the first gate bus 314 extending in the first direction X from shielding the first positioning mark 610. When the first gate bus has a segment extending in the second direction, the second positioning mark arranged adjacent to the segment of the first gate bus extending in the second direction can be arranged on the side of the segment of the first gate bus extending in the second direction facing the active region, so as to avoid the segment of the first gate bus extending in the second direction from shielding the second positioning mark.

[0126] Exemplarily, the first gate bus 314 can be arranged in the same layer as the gate conductive layer 3212, so as to reduce the process steps and save production cost. In addition, taking the active region AA 11 For example, since the first gate bus 314 is arranged in the passive region and the gate 321_1 is arranged in the active region, the first end of the gate 321_1-321_2 (e.g. the gate conductive layer 3212) can extend to the first gate bus 314 in the direction opposite to the second end and directly contact the first gate bus 314, and the extension area of the first end of the gate 321_1-321_2 in the direction opposite to the second end can be a solid area extended by the gate conductive layer 3212, and the extension area of the second end of the gate 321_1-321_2 in the direction opposite to the first end can be a virtual area without solid. The rest is the same, which can be deduced by analogy, and will not be repeated here.

[0127] In some embodiments, when the first positioning mark 610 is arranged in the same layer as the source electrode 322 or the P-GaN layer 3211 or the field plate or the first interconnection layer 500, the first positioning mark 610 can be arranged at the first end and / or the second end of the gate electrode 321. However, when the first positioning mark 610 is arranged in the same layer as the gate conductive layer 3212, if the first positioning mark 610 is arranged at the end of the gate electrode 321 connected to the first gate bus, since the extension area corresponding to the end of the gate electrode 321 is formed by the gate conductive layer 3212, the first positioning mark 610 is also formed by the gate conductive layer 3212, so that the first positioning mark 610 is formed in an integrated structure with the gate conductive layer 3212. Moreover, the pattern of the first positioning mark 610 corresponding to the end of the gate electrode 321 connected to the first gate bus also needs to be designed when patterning, which increases the cost of pattern design. Therefore, the first positioning mark 610 can not be arranged at the end of the gate electrode 321 connected to the first gate bus, but can be arranged at the end of the gate electrode 321 not connected to the first gate bus. For example, the first positioning mark 610 is arranged at the second end of the gate electrode 321_1-321_2, and the first positioning mark 610 is not arranged at the first end of the gate electrode 321_1-321_2.

[0128] FIG. 7b is another schematic top view of the first interconnection layer to the semiconductor stack in a GaN device according to embodiments of the present application. Referring to FIG. 7b, a part of the first gate buses is 314a, and the other part of the gate buses is 314b. The first end 321a of a part of the gate electrodes 321 in the same active region can be connected to the first gate bus 314a, and the second end 321b of the other part of the gate electrodes 321 can be connected to the first gate bus 314b. For example, the gate electrodes 321 connected to the first gate bus 314a and the gate electrodes 321 connected to the first gate bus 314b can be arranged alternately along the first direction X. Alternatively, the gate electrodes 321 connected to the first gate bus 314a can be arranged adjacently, and the gate electrodes 321 connected to the first gate bus 314b can be arranged adjacently.

[0129] In some examples, the first gate buses 314a and 314b can be arranged in a long strip shape extending along the first direction X. For example, the first gate buses 314a connected to the gate electrodes 321 in the active regions (for example, AA 11 ~AA 1n ) arranged along the first direction X can be the same gate bus. Alternatively, the first gate buses 314a connected to the gate electrodes 321 in the active regions (for example, AA 11 ~AA 1n ) arranged along the first direction X can be arranged spaced apart from each other.

[0130] In some examples, the first gate buses 314a connected to the gate electrodes 321 in the active regions (for example, AA11 AA 1n The first gate bus 314b to which the gate 321 in the AA 11 AA 1n The first gate bus 314b to which the gate 321 in the AA

[0131] In other examples, the first gate buses 314a and 314b can also respectively include segments extending along the first direction X and segments extending along the second direction Y, so that the first gate buses 314a and 314b are arranged in a meandering shape. Of course, the first gate buses 314a and 314b can also be in other forms, which are not limited herein.

[0132] When the first gate buses 314a and 314b have segments extending along the first direction X, for the first positioning marks 610 arranged adjacent to the segments of the first gate bus 314a extending along the first direction X, the part of the first positioning marks 610 can be arranged on the side of the segments of the first gate bus 314a extending along the first direction X facing the active area, and for the first positioning marks 610 arranged adjacent to the first gate bus 314b, the part of the first positioning marks 610 can be arranged on the side of the segments of the first gate bus 314b extending along the first direction X facing the active area, so as to avoid the segments of the first gate buses 314a and 314b extending along the first direction X from shielding the first positioning marks 610.

[0133] When the first gate buses 314a and 314b have segments extending along the second direction Y, for the second positioning marks 620 arranged adjacent to the segments of the first gate bus 314a extending along the second direction Y, the part of the second positioning marks 620 can be arranged on the side of the segments of the first gate bus 314a extending along the second direction Y facing the active area, and for the second positioning marks 620 arranged adjacent to the first gate bus 314b, the part of the second positioning marks 620 can be arranged on the side of the segments of the first gate bus 314b extending along the second direction Y facing the active area, so as to avoid the segments of the first gate buses 314a and 314b extending along the second direction Y from shielding the second positioning marks 620.

[0134] For example, when the first gate buses 314a and 314b are arranged in the same layer as the gate conductive layer 3212, the first positioning marks 610 and the second positioning marks 620 can be arranged in the same layer as the gate conductive layer 3212. 11For example, since the first gate bus 314a is disposed in the passive region and the gate 321_1 is disposed in the active region, the first end of the gate 321_1 (for example, the gate conductive layer 3212) can be extended to the first gate bus 314a in the direction away from the second end thereof and directly contact the first gate bus 314a, and the extension area of the first end of the gate 321_1 in the direction away from the second end thereof can be a solid area extended by the gate conductive layer 3212, and the extension area of the second end of the gate 321_1 in the direction away from the first end thereof can be a virtual area without solid. In addition, since the first gate bus 314b is disposed in the passive region and the gate 321_2 is disposed in the active region, the second end of the gate 321_2 (for example, the gate conductive layer 3212) can be extended to the first gate bus 314b in the direction away from the first end thereof and directly contact the first gate bus 314b, and the extension area of the second end of the gate 321_2 in the direction away from the first end thereof can be a solid area extended by the gate conductive layer 3212, and the extension area of the first end of the gate 321_2 in the direction away from the second end thereof can be a virtual area without solid. The rest is the same, which is not repeated here.

[0135] In some embodiments, when the first positioning mark 610 is disposed in the same layer as the source 322 or the P-GaN layer 3211 or the field plate or the first interconnection layer 500, the first positioning mark 610 can be disposed at the first end and / or the second end of the gate 321. When the first positioning mark 610 is disposed in the same layer as the gate conductive layer 3212, the first positioning mark 610 can not be disposed at the end of the gate 321 connected to the first gate bus, but can be disposed at the end of the gate 321 not connected to the first gate bus. For example, the first positioning mark 610 is disposed at the second end of the gate 321_1, and the first positioning mark 610 is not disposed at the first end of the gate 321_1. In addition, the first positioning mark 610 is disposed at the first end of the gate 321_2, and the first positioning mark 610 is not disposed at the second end of the gate 321_2.

[0136] It can be understood that the application takes the end of the gate disposed with the first positioning mark as an example for illustration, and in actual application, the first positioning mark can also be disposed at the end of the source and / or the drain, and for the embodiment in which the end of the source and the drain is disposed with the first positioning mark, the embodiment in which the end of the gate is disposed with the first positioning mark can be referred to, and specific details are not repeated here.

[0137] With reference back to FIGS. 1, 4-7b, the segments of the interconnection line 510 extending in the first direction X can be disposed in the active region, and since the gate 321 in the active region extends in the second direction Y, the interconnection line 510 and the gate 321 have a crossing point in the third direction Z, so that the accuracy of the address coordinates of different positions in the GaN device can be further improved in combination with the crossing point, the first positioning mark 610, and the second positioning mark 620. Based on this, in the process of device testing and analysis, the accurate position of the defect or hot spot can be further quickly identified in combination with the first positioning mark 610 and the second positioning mark 620, and the analysis efficiency and success rate are further improved.

[0138] With reference back to FIGS. 1, 4-7b, the interconnection line 510 can be provided as a plurality of lines, and each interconnection line 510 has a first end portion 510a and a second end portion 510b in its extension direction (for example, the second direction Y), that is, the region between the first end portion 510a and the second end portion 510b of the interconnection line 510 is formed as a solid part. In some examples, the second positioning mark 620 can be correspondingly provided at the first end portion 510a and the second end portion 510b of any interconnection line 510, and if the second positioning mark 620 of one of the end portions cannot be identified due to process factors, the second positioning mark 620 of the other end portion can be used for identification, to ensure the positioning accuracy of the defect or hot spot. For example, the first end portion 510a and the second end portion 510b of the same interconnection line 510 can be provided with the same second positioning mark 620, for example, with reference to FIGS. 1 and 4, the first end portion 510a and the second end portion 510b of the first interconnection line 510 are provided with the same second positioning mark 620, which is “1”, the first end portion 510a and the second end portion 510b of the second interconnection line 510 are provided with the same second positioning mark 620, which is “2”, the first end portion 510a and the second end portion 510b of the third interconnection line 510 are provided with the same second positioning mark 620, which is “A”, and the first end portion 510a and the second end portion 510b of the fourth interconnection line 510 are provided with the same second positioning mark 620, which is “B”. Alternatively, the first end portion 510a and the second end portion 510b of the same interconnection line 510 can be provided with different second positioning marks 620, for example, with reference to FIG. 6, the first end portion 510a and the second end portion 510b of the first interconnection line 510 are provided with different second positioning marks 620, which are “1” and “2” respectively, the first end portion 510a and the second end portion 510b of the second interconnection line 510 are provided with different second positioning marks 620, which are “2” and “3” respectively, the first end portion 510a and the second end portion 510b of the third interconnection line 510 are provided with different second positioning marks 620, which are “3” and “A” respectively, and the first end portion 510a and the second end portion 510b of the fourth interconnection line 510 are provided with different second positioning marks 620, which are “B” and “C” respectively. 11For example, the first end 510a of the first interconnection line 510 corresponds to the second positioning mark 620 set as "1", and the second end 510b corresponds to the second positioning mark 620 set as "3". The first end 510a of the second interconnection line 510 corresponds to the second positioning mark 620 set as "2", and the second end 510b corresponds to the second positioning mark 620 set as "4". The first end 510a of the third interconnection line 510 corresponds to the second positioning mark 620 set as "A", and the second end 510b corresponds to the second positioning mark 620 set as "C". The first end 510a of the fourth interconnection line 510 corresponds to the second positioning mark 620 set as "B", and the second end 510b corresponds to the second positioning mark 620 set as "D". In other examples, the second positioning mark 620 can be set only at the first end 510a or the second end 510b of the interconnection line 510, which can reduce the number of second positioning marks 620 and the difficulty of patterning.

[0139] When the first end portion 510a of the interconnection line 510 is correspondingly provided with the second positioning mark 620, the first end portion 510a of the interconnection line 510 can not have an overlapping area with the second positioning mark 620 correspondingly provided in the third direction Z, and the extension area of the first end portion 510a of the interconnection line 510 in the direction away from the second end portion 510b thereof at least partially overlaps with the second positioning mark 620 correspondingly provided in the third direction Z. For example, referring to FIGS. 1, 4 to 7b, in the third direction Z, the extension area 510as of the first end portion 510a of the interconnection line 510 in the direction away from the second end portion 510b thereof can cover the entire area of the second positioning mark 620 correspondingly provided. Alternatively, in the third direction Z, the extension area of the first end portion 510a of the interconnection line 510 in the direction away from the second end portion 510b thereof can cover part of the area of the second positioning mark 620 correspondingly provided. With such an arrangement, the second positioning mark 620 can be arranged adjacent to the first end portion 510a of the interconnection line 510, so that the second positioning mark 620 can be used to accurately mark the position of the first end portion of the interconnection line 510. Alternatively, the extension area of the first end portion of the interconnection line in the direction away from the second end portion thereof can be arranged to be misaligned with the second positioning mark correspondingly provided in the third direction, i.e., in the third direction, the extension area of the first end portion of the interconnection line in the direction away from the second end portion thereof does not overlap with the second positioning mark correspondingly provided. With such an arrangement, the second positioning mark can be arranged to be misaligned with the extension direction of the first end portion of the interconnection line, but arranged on one side of the extension area of the first end portion of the interconnection line, so that the second positioning mark can also be arranged adjacent to the first end portion of the interconnection line to accurately mark the position of the first end portion of the interconnection line using the second positioning mark. With such an arrangement, the first end portion 510a of the interconnection line 510 can be used to arrange the position of the second positioning mark 620, and the flexibility of arranging the positions of the second positioning marks 620 can be improved.

[0140] When the second end portion 510b of the interconnection line 510 is correspondingly provided with the second positioning mark 620, the second end portion 510b of the interconnection line 510 can not have an overlapping area with the second positioning mark 620 correspondingly provided thereon in the third direction Z, and the extending area of the second end portion 510b of the interconnection line 510 in the direction away from the first end portion 510a thereof at least partially overlaps with the second positioning mark 620 correspondingly provided thereon in the third direction Z. For example, referring to FIG. 1, FIG. 4 to FIG. 7b, in the third direction Z, the extending area 510bs of the second end portion 510b of the interconnection line 510 in the direction away from the first end portion 510a thereof can cover the entire area of the second positioning mark 620 correspondingly provided thereon. Alternatively, in the third direction Z, the extending area of the second end portion 510b of the interconnection line 510 in the direction away from the first end portion 510a thereof can cover part of the area of the second positioning mark 620 correspondingly provided thereon. With such a configuration, the second positioning mark 620 can be provided adjacent to the second end portion 510b of the interconnection line 510, so that the second positioning mark 620 can be used to accurately mark the position of the second end portion 510b of the interconnection line 510. Alternatively, the extending area of the second end portion of the interconnection line in the direction away from the first end portion thereof and the second positioning mark correspondingly provided thereon can be misaligned in the third direction, i.e., in the third direction, the extending area of the second end portion of the interconnection line in the direction away from the first end portion thereof and the second positioning mark correspondingly provided thereon do not overlap. With such a configuration, the second positioning mark can be misaligned with the extending direction of the second end portion of the interconnection line, but can be provided on one side of the extending area of the second end portion of the interconnection line, so that the second positioning mark can also be provided adjacent to the second end portion of the interconnection line, and can be used to accurately mark the position of the second end portion of the interconnection line. With such a configuration, the second positioning mark 620 can be positioned by using the second end portion 510b of the interconnection line 510, and the flexibility of positioning the second positioning mark 620 can be improved.

[0141] It is worth mentioning that the extending area of the first end portion of the interconnection line in the direction away from the second end portion thereof and the extending area of the second end portion of the interconnection line in the direction away from the first end portion thereof can be determined to be a virtual area or a real area according to the specific structure of the GaN device. In addition, the first end portion and / or the second end portion of the interconnection line described above can be aligned with the edge of the active region in the third direction, or the first end portion and / or the second end portion of the interconnection line described above can extend to the edge of the active region and have a certain distance from the edge of the active region, i.e., the first end portion and / or the second end portion of the interconnection line does not cross the edge of the active region, and is also not aligned with the edge of the active region in the third direction. Alternatively, the first end portion and / or the second end portion of the interconnection line described above can also extend to the passive region.

[0142] Fig. 8a is a schematic view of a partial 3D structure of the first interconnection layer to the substrate in the GaN device shown in Fig. 4, Fig. 8b is a schematic view of a cross-sectional structure along the direction AA' in Fig. 8a, and Fig. 8c is a schematic view of a cross-sectional structure along the direction BB' in Fig. 8a. With reference to Figs. 4, 6, 8a-8c, the interconnection line 510 can include a source interconnection line 511 and a drain interconnection line 512 arranged apart from each other, i.e., the source interconnection line 511 and the drain interconnection line 512 can be formed of the same layer of conductive material (e.g., metal material), i.e., the source interconnection line 511 and the drain interconnection line 512 can be formed by etching the same conductive layer, thereby reducing the process steps and saving production costs. Further, the source interconnection line 511 can be connected to the source 322 through one or more source contact holes AX1 penetrating the first dielectric layer 400, i.e., a source contact portion is formed by filling the source contact hole AX1 with conductive material (e.g., one or a combination of metal material, metal nitride material), one end of the source contact portion is connected to the source 322, and the other end of the source contact portion is connected to the source interconnection line 511, so that the source interconnection line 511 and the source 322 are electrically connected, thereby enabling the source interconnection line 511 to transmit signals to the source 322. Further, the drain interconnection line 512 can be connected to the drain 323 through one or more drain contact holes AX2 penetrating the first dielectric layer 400, i.e., a drain contact portion is formed by filling the drain contact hole AX2 with conductive material (e.g., one or a combination of metal material, metal nitride material), one end of the drain contact portion is connected to the drain 323, and the other end of the drain contact portion is connected to the drain interconnection line 512, so that the drain interconnection line 512 and the drain 323 are electrically connected, thereby enabling the drain interconnection line 512 to transmit signals to the drain 323.

[0143] In specific implementations, the interconnection line 510 in the GaN device can include one or more source interconnection lines 511 and one or more drain interconnection lines 512. When the interconnection line 510 includes a plurality of source interconnection lines 511 and a plurality of drain interconnection lines 512, the plurality of source interconnection lines 511 and the plurality of drain interconnection lines 512 can extend along the first direction X and be arranged apart along the second direction Y. For example, with reference to Figs. 4 and 8a, the plurality of source interconnection lines 511 and the plurality of drain interconnection lines 512 can be arranged based on the manner that one source interconnection line 511 and one drain interconnection line 512 are alternately arranged along the second direction Y. Alternatively, the plurality of source interconnection lines 511 and the plurality of drain interconnection lines 512 can be arranged based on the manner that at least two adjacent source interconnection lines 511 or at least two adjacent drain interconnection lines 512 are alternately arranged along the second direction Y.

[0144] In some embodiments of the present application, the second positioning mark 620 can be arranged at least partially on the source interconnect line 511. In this way, the position of the second positioning mark 620 can be arranged on the source interconnect line 511, and the flexibility of arranging the position of the second positioning mark 620 can be improved. For example, referring to FIG. 4 and FIG. 6, the end of each source interconnect line 511 can be arranged with the second positioning mark 620, and the second positioning mark 620 can be further subdivided based on the source interconnect line 511. The address coordinates of the intersection of the source interconnect line 511 and the gate 321 in the third direction Z can further improve the accuracy of identifying the position of the defect or hotspot, and further improve the analysis efficiency and success rate. Alternatively, the end of part of the source interconnect line 511 can be arranged with the second positioning mark 620. For example, the two adjacent source interconnect lines 511 arranged with the second positioning mark 620 can be separated by one, two, three or more source interconnect lines 511, so as to reduce the number of second positioning marks 620 corresponding to the source interconnect line 511, and reduce the patterning complexity.

[0145] In some examples, referring to FIG. 4 and FIG. 6, the first end 511a and the second end 511b of all or part of the source interconnect line 511 can be arranged with the second positioning mark 620, respectively. If the second positioning mark 620 of one of the ends cannot be identified due to process factors, the second positioning mark 620 of the other end can be used for identification, so as to ensure the positioning accuracy of the defect or hotspot.

[0146] For example, referring to FIG. 4, the second positioning marks 620 corresponding to the first end portions 511a and the second end portions 511b of the same source interconnect line 511 can be made identical, for example, where the second positioning marks 620 corresponding to the first end portions 511a and the second end portions 511b of the same source interconnect line 511 are both "B". With such an arrangement, the patterning complexity of the second positioning marks 620 in this portion can be reduced. Alternatively, referring to FIG. 6, the second positioning marks 620 corresponding to the first end portions 511a and the second end portions 511b of the same source interconnect line 511 can also be made different, for example, where the second positioning mark 620 corresponding to the first end portion 511a of one source interconnect line 511 is "B", and the second positioning mark 620 corresponding to the second end portion 511b of the same source interconnect line 511 is "D", so as to be distinguishable. In yet other examples, the first end portions 511a or the second end portions 511b of all source interconnect lines 511 can be provided with the second positioning marks 620. Alternatively, the first end portions 511a or the second end portions 511b of some source interconnect lines 511 can be provided with the second positioning marks 620, and the first end portions 511a and the second end portions 511b of other source interconnect lines 511 can be provided with the second positioning marks 620. Alternatively, the first end portions 511a of some source interconnect lines 511 can be provided with the second positioning marks 620, and the second end portions 511b of other source interconnect lines 511 can be provided with the second positioning marks 620.

[0147] For example, referring to FIG. 4, the second positioning marks 620 corresponding to the first end portions 511a and the second end portions 511b of the same source interconnect line 511 can be made identical, for example, where the second positioning marks 620 corresponding to the first end portions 511a and the second end portions 511b of the same source interconnect line 511 are both "B". With such an arrangement, the patterning complexity of the second positioning marks 620 in this portion can be reduced. Alternatively, referring to FIG. 6, the second positioning marks 620 corresponding to the first end portions 511a and the second end portions 511b of the same source interconnect line 511 can also be made different, for example, where the second positioning mark 620 corresponding to the first end portion 511a of one source interconnect line 511 is "B", and the second positioning mark 620 corresponding to the second end portion 511b of the same source interconnect line 511 is "D", so as to be distinguishable. In yet other examples, the first end portions 511a or the second end portions 511b of all source interconnect lines 511 can be provided with the second positioning marks 620. Alternatively, the first end portions 511a or the second end portions 511b of some source interconnect lines 511 can be provided with the second positioning marks 620, and the first end portions 511a and the second end portions 511b of other source interconnect lines 511 can be provided with the second positioning marks 620. Alternatively, the first end portions 511a of some source interconnect lines 511 can be provided with the second positioning marks 620, and the second end portions 511b of other source interconnect lines 511 can be provided with the second positioning marks 620.

[0148] Exemplarily, the second end portion 511b of any one of the source interconnect lines 511 can be provided with a second positioning mark 620 of the same type, so that the second positioning mark 620 can be formed in the same pattern, and the complexity of patterning the second positioning mark 620 can be reduced. For example, referring to FIG. 4, the second positioning mark 620 provided at the second end portion 511b of one source interconnect line 511 and the second positioning mark 620 provided at the second end portion 511b of another source interconnect line 511 are both "B". Alternatively, the second positioning mark 620 provided at the second end portion 511b of any one of the source interconnect lines 511 can be different, so that the second positioning mark 620 can be formed in different patterns, and the different source interconnect lines 511 can be distinguished. For example, referring to FIG. 6, the second positioning mark 620 provided at the second end portion 511b of one source interconnect line 511 is "D", and the second positioning mark 620 provided at the second end portion 511b of another source interconnect line 511 is "H". Alternatively, the second positioning mark 620 provided at the second end portion 511b of some of the source interconnect lines 511 can be the same, and the second positioning mark 620 provided at the second end portion 511b of some of the source interconnect lines 511 can be different.

[0149] In some embodiments of the present application, at least part of the drain interconnect lines 512 can be provided with the second positioning mark 620. In this way, the position of the second positioning mark 620 can be set by the drain interconnect line 512, and the flexibility of setting the position of the second positioning mark 620 can be improved. For example, referring to FIG. 4 and FIG. 6, the end portion of each drain interconnect line 512 can be provided with the second positioning mark 620, the second positioning mark 620 can be further subdivided based on the drain interconnect line 512, and the address coordinates of the intersection of the drain interconnect line 512 and the gate 321 in the third direction Z can be used to further improve the accuracy of identifying the position of the defect or hot spot, and further improve the analysis efficiency and success rate. Alternatively, the end portion of part of the drain interconnect lines 512 can be provided with the second positioning mark 620, for example, the two adjacent drain interconnect lines 512 provided with the second positioning mark 620 can be separated by one, two, three or more drain interconnect lines 512, so that the number of the second positioning mark 620 corresponding to the drain interconnect line 512 can be reduced, and the complexity of patterning can be reduced.

[0150] In some examples, referring to FIG. 4 and FIG. 6, the first end portion 512a and the second end portion 512b of all or part of the drain interconnect lines 512 can be provided with the second positioning mark 620, respectively. If the second positioning mark 620 of one of the end portions cannot be identified due to process factors, the second positioning mark 620 of the other end portion can be used for identification, so that the positioning accuracy of the defect or hot spot can be ensured.

[0151] Exemplarily, referring to FIG. 4, the second positioning marks 620 corresponding to the first end portions 512a and the second end portions 512b of the same drain interconnection line 512 can be made identical, for example, the second positioning marks 620 corresponding to the first end portions 512a and the second end portions 512b of the same drain interconnection line 512 are all “A”. With such arrangement, the patterning complexity of the second positioning marks 620 in this portion can be reduced. Alternatively, referring to FIG. 6, the second positioning marks 620 corresponding to the first end portions 512a and the second end portions 512b of the same drain interconnection line 512 can also be made different, for example, the second positioning mark 620 corresponding to the first end portion 512a of one drain interconnection line 512 is “A”, and the second positioning mark 620 corresponding to the second end portion 512b of the same drain interconnection line 512 is “C”. With such arrangement, the different drain interconnection lines 512 can be distinguished easily.

[0152] In yet some examples, the first end portions 512a or the second end portions 512b of all the drain interconnection lines 512 can be provided with the second positioning marks 620. Alternatively, the first end portions 512a or the second end portions 512b of some of the drain interconnection lines 512 can be provided with the second positioning marks 620, and the first end portions 512a and the second end portions 512b of the other drain interconnection lines 512 can be provided with the second positioning marks 620. Alternatively, the first end portions 512a of some of the drain interconnection lines 512 can be provided with the second positioning marks 620, and the second end portions 512b of the other drain interconnection lines 512 can be provided with the second positioning marks 620.

[0153] Exemplarily, the second positioning marks 620 corresponding to the first end portions 512a of any of the drain interconnection lines 512 can be made identical, so that the same pattern can be used to form the second positioning marks 620 in this portion, and the patterning complexity of the second positioning marks 620 can be reduced. For example, referring to FIG. 4, the second positioning marks 620 corresponding to the first end portions 512a of one of the drain interconnection lines 512 and the first end portions 512a of another of the drain interconnection lines 512 are all “A”. Alternatively, the second positioning marks 620 corresponding to the first end portions 512a of any of the drain interconnection lines 512 can also be made different, so that different patterns can be used to form the second positioning marks 620 in this portion, and the different drain interconnection lines 512 can be distinguished easily. For example, referring to FIG. 6, the second positioning mark 620 corresponding to the first end portion 512a of one of the drain interconnection lines 512 is “A”, and the second positioning mark 620 corresponding to the first end portion 512a of another of the drain interconnection lines 512 is “E”. Alternatively, the second positioning marks 620 corresponding to the first end portions 512a of some of the drain interconnection lines 512 can be made identical, and the second positioning marks 620 corresponding to the first end portions 512a of the other drain interconnection lines 512 can be made different.

[0154] Exemplarily, the second end portion 512b of any one of the drain interconnect lines 512 can be provided with the same second positioning mark 620, so that the second positioning mark 620 can be formed in the same pattern, and the patterning complexity of the second positioning mark 620 can be reduced. For example, referring to FIG. 4, the second positioning mark 620 provided at the second end portion 512b of one of the drain interconnect lines 512 and the second positioning mark 620 provided at the second end portion 512b of another of the drain interconnect lines 512 are both "A". Alternatively, the second positioning mark 620 provided at the second end portion 512b of any one of the drain interconnect lines 512 can be different, so that the second positioning mark 620 can be formed in different patterns, and the drain interconnect lines 512 can be distinguished from each other. For example, referring to FIG. 6, the second positioning mark 620 provided at the second end portion 512b of one of the drain interconnect lines 512 is "C", and the second positioning mark 620 provided at the second end portion 512b of another of the drain interconnect lines 512 is "G". Alternatively, the second positioning mark 620 provided at the second end portion 512b of some of the drain interconnect lines 512 can be the same, and the second positioning mark 620 provided at the second end portion 512b of some of the drain interconnect lines 512 can be different.

[0155] Further, the second positioning mark 620 provided at the first end portion 511a of any one or some of the source interconnect lines 511 and the second positioning mark 620 provided at the first end portion 512a of any one or some of the drain interconnect lines 512 can be the same, so as to reduce the patterning complexity of the second positioning mark 620. Alternatively, referring to FIG. 4, the second positioning mark 620 provided at the first end portion 511a of any one or some of the source interconnect lines 511 and the second positioning mark 620 provided at the first end portion 512a of any one or some of the drain interconnect lines 512 can be different, so as to distinguish the first end portions of the source interconnect lines 511 and the drain interconnect lines 512 by the different second positioning marks 620.

[0156] Further, the second positioning mark 620 provided at the first end portion 511a of any one or some of the source interconnect lines 511 and the second positioning mark 620 provided at the first end portion 512a of any one or some of the drain interconnect lines 512 can be the same, so as to reduce the patterning complexity of the second positioning mark 620. Alternatively, referring to FIG. 4, the second positioning mark 620 provided at the first end portion 511a of any one or some of the source interconnect lines 511 and the second positioning mark 620 provided at the first end portion 512a of any one or some of the drain interconnect lines 512 can be different, so as to distinguish the first end portions of the source interconnect lines 511 and the drain interconnect lines 512 by the different second positioning marks 620.

[0157] In addition, the number of source interconnection lines 511 provided with the second positioning mark 620 can be the same as or different from the number of drain interconnection lines 512 provided with the second positioning mark 620.

[0158] FIG. 9 is another schematic top view of the first interconnection layer to the semiconductor stack in a GaN device according to embodiments of the present application. Referring to FIG. 9, the first interconnection layer can further include a source bus 513 (Bus) and a drain bus 514 (Bus). The source bus 513 and the drain bus 514 can be disposed in the passive region and connected to the source interconnection lines 511 and the drain interconnection lines 512, respectively, to improve the synchronization of the transmitted signals.

[0159] In some examples, the first end or the second end of some or all of the source interconnection lines 511 can be connected to a source bus 513. As a result, the source interconnection lines 511 can be arranged like fingers. For example, when the second end of the source interconnection line 511 is connected to the source bus 513, the second end of the source interconnection line 511 needs to extend into the passive region, so that the extension area of the second end of the source interconnection line 511 in the direction opposite to the first end is a solid area, and the extension area of the first end of the source interconnection line 511 in the direction opposite to the second end is a virtual area (i.e., a non-solid area). In other examples, the source bus 513 can not be provided.

[0160] In some examples, the first end or the second end of some or all of the drain interconnection lines 512 can be connected to a drain bus 514. For example, when the first end of the drain interconnection line 512 is connected to the drain bus 514, the first end of the drain interconnection line 512 needs to extend into the passive region, so that the extension area of the first end of the drain interconnection line 512 in the direction opposite to the second end is a solid area, and the extension area of the second end of the drain interconnection line 512 in the direction opposite to the first end is a virtual area (i.e., a non-solid area). In other examples, the drain bus 514 can not be provided.

[0161] Fig. 10a is a schematic view of another top structure of the first interconnection layer to the semiconductor stack in a GaN device according to an embodiment of the present application, and Fig. 10b is a schematic view of a corresponding partial 3D structure of Fig. 10a. Referring to Figs. 10a and 10b, the first interconnection layer 500 can further include a second gate bus line 520. That is, the source interconnection line 511, the drain interconnection line 512 and the second gate bus line 520 can be formed by the same layer of conductive material (e.g., metal material), and the second gate bus line 520 is insulated from the source interconnection line 511 and the drain interconnection line 512. In this way, the source interconnection line 511, the drain interconnection line 512 and the second gate bus line 520 can be formed by etching the same layer of conductive material, thereby reducing the process steps and saving production costs.

[0162] The second gate bus line 520 is configured to connect the gate 321 to transmit signals to the gate 321 through the second gate bus line 520. For example, in the embodiment of the first gate bus line 314 shown in Fig. 7a, the second gate bus line 520 is connected to the first gate bus line 314 through one or more gate contact holes penetrating the first dielectric layer 400. That is, the gate contact hole is filled with a conductive material (e.g., metal material) to form a gate contact, one end of the gate contact is connected to the first gate bus line 314, and the other end of the gate contact is connected to the second gate bus line 520, so that the second gate bus line 520 and the first gate bus line are electrically connected, and signals can be transmitted to the gate 321 (e.g., the gate conductive layer 3212) through the second gate bus line 520 and the first gate bus line.

[0163] For example, the second gate bus line 520 is located in the passive region, and to avoid the second gate bus line 520 from blocking the first positioning mark 610 and the second positioning mark 620, the second gate bus line 520 can not overlap the first positioning mark 610 and the second positioning mark 620 in the third direction Z, respectively. For example, the first positioning mark 610 and the second positioning mark 620 can be arranged between the second gate bus line 520 and the active region.

[0164] In some examples, referring to FIGS. 10a and 10b, the second gate bus 520 can include a plurality of first sub-gate buses 521 extending along the first direction X. Exemplarily, a plurality of active regions arranged along the first direction X can be correspondingly provided with two first sub-gate buses 521, one of which can be disposed in the passive region at the first end of the gate 321 and connected to the first gate bus connected to the first end of the gate 321 through a gate contact hole. The other of which can be disposed in the passive region at the second end of the gate 321 and connected to the first gate bus connected to the second end of the gate 321 through a gate contact hole. In addition, in order to avoid the first sub-gate bus 521 from shielding the first positioning mark 610, for the first positioning mark 610 close to the first sub-gate bus 521, the first positioning mark 610 can be disposed on the side of the first sub-gate bus 521 facing the active region. Further, in order to reduce the number of first sub-gate buses 521, the first sub-gate buses 521 between active regions adjacent along the second direction Y can be shared.

[0165] In order to improve the signal synchronization of the gate 321, the above-mentioned plurality of first sub-gate buses 521 can be connected to each other, so that the signals transmitted to different first sub-gate buses 521 can be synchronously transmitted to each gate 321 (e.g., the gate conductive layer 3212). Exemplarily, referring to FIGS. 10a and 10b, the second gate bus 520 can further include a plurality of second sub-gate buses 522, and one or more second sub-gate buses 522 can be connected between each two adjacent first sub-gate buses 521, so that each first sub-gate bus 521 can be connected to each other. In addition, in order to avoid the second sub-gate bus 522 from shielding the second positioning mark 620, for the second positioning mark 620 close to the second sub-gate bus 522, the second positioning mark 620 can be disposed on the side of the second sub-gate bus 522 facing the active region. Further, in order to avoid the second sub-gate bus 522 from occupying the area of the active region, the second sub-gate bus 522 can be disposed in the passive region.

[0166] In some embodiments of the present application, each two adjacent first sub-gate bus lines 521 can be connected to each other through the same number of second sub-gate bus lines 522 to improve the structural uniformity and reliability of the GaN device. For example, referring to FIGS. 10a and 10b, when two second sub-gate bus lines 522 are arranged on both sides of each active region along the first direction X, each active region can be provided with one second sub-gate bus line 522 on each side along the first direction X, so that each two adjacent first sub-gate bus lines 521 can be connected through the second sub-gate bus lines 522 on both sides of each active region between the two first sub-gate bus lines 521. Alternatively, a plurality of active regions arranged along the first direction X can be regarded as an active region group, and each active region group can be provided with one second sub-gate bus line 522 on each side, so that each two adjacent first sub-gate bus lines 521 can be connected through the second sub-gate bus lines 522 on both sides of each active region group between the two first sub-gate bus lines 521. Further, in order to further reduce the area occupied by the second sub-gate bus lines 522, the second sub-gate bus lines 522 between adjacent active regions along the first direction X can be shared.

[0167] In yet some embodiments of the present application, part of each two adjacent first sub-gate bus lines 521 can be connected to each other through the same number of second sub-gate bus lines 522, and the rest of each two adjacent first sub-gate bus lines 521 can be connected to each other through different numbers of second sub-gate bus lines 522. Alternatively, each two adjacent first sub-gate bus lines 521 can be connected to each other through different numbers of second sub-gate bus lines 522.

[0168] It is worth mentioning that, since the interconnection lines 510 and the second sub-gate bus lines 522 are arranged on the same layer and the extension directions of the interconnection lines 510 and the second sub-gate bus lines 522 intersect, in order to avoid short circuit between the interconnection lines 510 and the second sub-gate bus lines 522, when the second sub-gate bus lines 522 are arranged on both sides of each active region, the interconnection lines 510 in each active region can not extend to the outside of the active region, i.e., the interconnection lines 510 are arranged in each active region, so as to separate the interconnection lines 510 from the second sub-gate bus lines 522. When the second sub-gate bus lines 522 are arranged on both sides of each active region group, the interconnection lines 510 in each active region can not extend to the outside of the active region, i.e., the interconnection lines 510 are arranged in each active region, so as to separate the interconnection lines 510 from the second sub-gate bus lines 522. Alternatively, in an active region group, the interconnection lines 510 (i.e., the source interconnection lines 511 and the drain interconnection lines 512) can extend across a plurality of active regions in the active region group based on the manner that the interconnection lines 510 extend from one active region to another active region along the first direction X, and the interconnection lines 510 can be separated from the second sub-gate bus lines 522.

[0169] Fig. 11 is another schematic top view of the first interconnection layer to the semiconductor stack in a GaN device according to embodiments of the present application. Referring to Fig. 11, the GaN device according to embodiments of the present application can further include third positioning marks 630. Each active region can be provided with one or more third positioning marks 630, and the third positioning marks 630 can be provided corresponding to the corners of the active region. The pattern of the third positioning marks 630 can include one or a combination of a letter pattern, a number pattern, a word pattern, a matrix pattern, a regular figure pattern, and an irregular figure pattern.

[0170] To distinguish different active regions, the third positioning marks 630 corresponding to different active regions can be different. For example, the active region AA 11 The third positioning mark 630 corresponding to the active region AA 1n The third positioning mark 630 corresponding to the active region AA m1 The third positioning mark 630 corresponding to the active region AA mn The third positioning mark 630 corresponding to the active region AA

[0171] Referring to Fig. 11, the third positioning marks 630 can be provided in the passive region to reduce the shielding of the third positioning marks 630 by the active region, so as to facilitate the identification of the third positioning marks 630. Alternatively, the third positioning marks 630 can span the active region and the passive region.

[0172] Exemplarily, the third positioning marks 630 can be provided in the same layer as the first positioning marks 610 and the second positioning marks 620, thereby reducing the process steps and saving production costs.

[0173] FIG. 12 is a top view of a second interconnection layer of a GaN device according to an embodiment of the present application, FIG. 13a is a partial 3D view of the second interconnection layer to the substrate of the GaN device according to an embodiment of the present application, FIG. 13b is a cross-sectional view along the AA' direction of FIG. 13a, FIG. 13c is a cross-sectional view along the BB' direction of FIG. 13a, FIG. 14a is another partial 3D view of the second interconnection layer to the substrate of the GaN device according to an embodiment of the present application, FIG. 14b is a cross-sectional view along the AA' direction of FIG. 14a, and FIG. 14c is a cross-sectional view along the BB' direction of FIG. 14a. Referring to FIGS. 12-14c, the GaN device according to an embodiment of the present application can further include a second dielectric layer 600 and a second interconnection layer 700 stacked on the first interconnection layer 500, wherein the first interconnection layer 500 can be insulated and protected by the second dielectric layer 600. Exemplarily, the second dielectric layer 600 can include, but is not limited to, silicon dioxide (SiO2), silicon oxycarbide (SiCO), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), or a combination thereof. In addition, the first dielectric layer 400 and the second dielectric layer 600 can be of the same material or different materials.

[0174] The second interconnection layer 700 can include a source interconnection portion 720, a drain interconnection portion 730, and a gate interconnection portion 710 arranged in a spaced-apart manner, i.e., the source interconnection portion 720, the drain interconnection portion 730, and the gate interconnection portion 710 can be formed of a same layer of conductive material (e.g., a metal material), so that the source interconnection portion 720, the drain interconnection portion 730, and the gate interconnection portion 710 can be formed by etching the same conductive layer, thereby reducing the process steps and saving production costs.

[0175] Exemplarily, referring to FIGS. 12, 13a, and 14a, the source interconnection portion 720 and the drain interconnection portion 730 can each have a planar structure. The source interconnection portion 720 can cover a plurality of active regions in the orthographic projection of the substrate 100, and the drain interconnection portion 730 can also cover a plurality of active regions in the orthographic projection of the substrate 100. Of course, in other embodiments of the present application, the source interconnection portion 720 and the drain interconnection portion 730 can each have a strip structure, a grid structure, or the like, which is not limited herein.

[0176] In addition, the source interconnection portion 720 and the drain interconnection portion 730 can be arranged symmetrically to improve the reliability and stability of the GaN device. Of course, in other embodiments of the present application, the source interconnection portion 720 and the drain interconnection portion 730 can be arranged asymmetrically, which is not limited herein.

[0177] Referring to FIGS. 14a-14c, the source interconnect 720 can be connected to the plurality of source interconnect lines 511 through a source transfer hole BX1 that penetrates the second dielectric layer 600, i.e., a source transfer portion is formed by filling a conductive material (e.g., a metallic material) in the source transfer hole BX1, one end of the source transfer portion is connected to the source interconnect line 511, and the other end of the source transfer portion is connected to the source interconnect 720, so that the source interconnect line 511 and the source interconnect 720 are electrically connected, and thus the source interconnect line 511 can be transmitted with a signal through the source interconnect 720.

[0178] Referring to FIGS. 13a-13c, the drain interconnect 730 can be connected to the plurality of drain interconnect lines 512 through a drain transfer hole BX2 that penetrates the second dielectric layer 600, i.e., a drain transfer portion is formed by filling a conductive material (e.g., a metallic material) in the drain transfer hole BX2, one end of the drain transfer portion is connected to the drain interconnect line 512, and the other end of the drain transfer portion is connected to the drain interconnect 730, so that the drain interconnect line 512 and the drain interconnect 730 are electrically connected, and thus the drain interconnect line 512 can be transmitted with a signal through the drain interconnect 730.

[0179] Referring to FIG. 12, the gate interconnect 710 can include a gate planar structure portion, a first strip structure portion, and a second strip structure portion connected to each other, the first strip structure portion surrounds the source interconnect 720 and the drain interconnect 730, and the second strip structure portion is disposed between the source interconnect 720 and the drain interconnect 730. The first strip structure portion can be connected to the second gate bus through one or more first gate transfer holes, i.e., a first gate transfer portion is formed by filling a conductive material (e.g., a metallic material) in the first gate transfer hole, one end of the first gate transfer portion is connected to the second gate bus, and the other end of the first gate transfer portion is connected to the first strip structure portion. Also, the second strip structure portion can be connected to the second gate bus through one or more second gate transfer holes, i.e., a second gate transfer portion is formed by filling a conductive material (e.g., a metallic material) in the second gate transfer hole, one end of the second gate transfer portion is connected to the second gate bus, and the other end of the second gate transfer portion is connected to the second strip structure portion.

[0180] In other embodiments of the present application, the gate planar structure portion can also be connected to the second gate bus through one or more third gate transfer holes, i.e., a third gate transfer portion is formed by filling a conductive material (e.g., a metallic material) in the third gate transfer hole, one end of the third gate transfer portion is connected to the second gate bus, and the other end of the third gate transfer portion is connected to the gate planar structure portion.

[0181] It is worth mentioning that the above is only an example of the specific structure of the GaN device, and in specific implementation, the specific structure of the GaN device is not limited to the above structure provided by the embodiments of the present application, but can also be other structures known to those skilled in the art, which are not limited herein.

[0182] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A gallium nitride (GaN) device having a positioning mark, characterized by, The application relates to a semiconductor structure, comprising: a substrate; a semiconductor stack arranged on the substrate; an electrode layer arranged on the semiconductor stack, the electrode layer comprising electrode groups, each electrode group comprising a gate electrode and a source electrode and a drain electrode arranged on both sides of the gate electrode respectively, the gate electrode, the source electrode and the drain electrode extending along a second direction; a first dielectric layer arranged on the electrode layer; a first interconnection layer arranged on the first dielectric layer, the first interconnection layer comprising interconnection lines, at least part of the sections of the interconnection lines extending along a first direction; and first positioning marks and second positioning marks arranged at intervals, wherein the end portions of at least one of the gate electrode, the source electrode and the drain electrode are arranged corresponding to the first positioning marks, and the end portions of the interconnection lines are arranged corresponding to the second positioning marks; the first direction and the second direction intersect, and the first direction and the second direction are parallel to the substrate respectively.

2. The GaN device of claim 1, wherein, The electrode layer comprises one or more electrode groups, each electrode group defining a cell region, and at least part of the cell regions are arranged corresponding to the first positioning marks, and the extension regions of the cell regions in the second direction have overlapping regions with the first positioning marks arranged corresponding thereto in the third direction.

3. The GaN device of claim 2, wherein, The semiconductor stack comprises one or more active regions and a passive region surrounding each active region, and the active region comprises one or more cell regions; The first positioning marks are arranged in the passive region or the active region, or the first positioning marks span the active region and the passive region; The second positioning marks are arranged in the passive region or the active region, or the second positioning marks span the active region and the passive region.

4. The GaN device of claim 3, wherein, In any of the cell regions, the gate electrode, the source electrode and the drain electrode each have a first end portion and a second end portion; The first end portion of at least one of the gate electrode, the source electrode and the drain electrode is arranged corresponding to the first positioning marks, and the extension region of the first end portion of at least one of the gate electrode, the source electrode and the drain electrode in the direction opposite to the second end portion direction thereof at least partially overlaps with the first positioning marks arranged corresponding thereto in the third direction, which is perpendicular to the substrate; Or, the second end portion of at least one of the gate electrode, the source electrode and the drain electrode is arranged corresponding to the first positioning marks, and the extension region of the second end portion of at least one of the gate electrode, the source electrode and the drain electrode in the direction opposite to the first end portion direction thereof at least partially overlaps with the first positioning marks arranged corresponding thereto in the third direction, which is perpendicular to the substrate.

5. The GaN device of claim 4, wherein, Any of the active regions is provided with a plurality of cell regions, and the gate electrodes in at least part of the cell regions are arranged corresponding to the first positioning marks.

6. The GaN device of claim 5, wherein, In any of the active regions, each of the gate electrodes is arranged corresponding to the first positioning marks; Or, in any of the active regions, at least one gate electrode is arranged between the two adjacent gate electrodes arranged corresponding to the first positioning marks.

7. A GaN device as claimed in any one of claims 3 to 6, wherein the GaN device is a vertical GaN device. The first positioning marks corresponding to the cell regions in at least part of the active regions are the same; or the first positioning marks corresponding to the cell regions in different active regions are different.

8. A GaN device as claimed in any one of claims 3 to 7, wherein the GaN device is a vertical GaN device. The segment of the interconnection line extending along the first direction is arranged in the active region, and the interconnection line has a first end and a second end; The first end of the interconnection line is provided with the second positioning mark corresponding thereto, and the second positioning mark corresponding thereto has no overlapping area in the third direction, and the extension area of the first end of the interconnection line in the direction away from the second end thereof at least partially overlaps or is misarranged with the second positioning mark corresponding thereto in the third direction; Or, the second end of the interconnection line is provided with the second positioning mark corresponding thereto, and the second positioning mark corresponding thereto has no overlapping area in the third direction, and the extension area of the second end of the interconnection line in the direction away from the first end thereof at least partially overlaps or is misarranged with the second positioning mark corresponding thereto in the third direction.

9. The GaN device of claim 8, wherein, The interconnection line includes a plurality of source interconnection lines and a plurality of drain interconnection lines, the source interconnection lines are connected with the sources through source contact holes penetrating through the first dielectric layer, and the drain interconnection lines are connected with the drains through drain contact holes penetrating through the first dielectric layer; At least part of the source interconnection lines are provided with the second positioning mark corresponding thereto; and / or, at least part of the drain interconnection lines are provided with the second positioning mark corresponding thereto.

10. The GaN device of claim 9, wherein, Each of the source interconnection lines is provided with the second positioning mark corresponding thereto; or At least one source interconnection line is arranged between two adjacent source interconnection lines provided with the second positioning mark corresponding thereto.

11. The GaN device of claim 9 or 10, wherein, Each of the drain interconnection lines is provided with the second positioning mark corresponding thereto; or At least one drain interconnection line is arranged between two adjacent drain interconnection lines provided with the second positioning mark corresponding thereto.

12. The GaN device of any of claims 3-11, wherein, The electrode layer further includes a first gate bus line, the first gate bus line is located in the passive region, and the first gate bus line is connected with the gate; The first positioning mark and the second positioning mark respectively have no overlapping area with the first gate bus line in the third direction.

13. The GaN device of any of claims 3-12, wherein, The first interconnection layer further includes a second gate bus line, the second gate bus line is located in the passive region, and the second gate bus line is used to connect the gate; The second gate bus line respectively has no overlapping area with the first positioning mark and the second positioning mark in the third direction.

14. The GaN device of any of claims 3-13, wherein, A third positioning mark is further included, the third positioning mark is arranged corresponding to the corner of the active region, and the third positioning marks corresponding to different active regions are different; The third positioning mark is arranged in the passive region, or the third positioning mark crosses the active region and the passive region.

15. The GaN device of any of claims 1-14, wherein, The first positioning mark is arranged in the same layer as the first interconnection layer; or the second positioning mark is arranged in the same layer as the first interconnection layer.

16. The GaN device of any of claims 1-15, wherein, The pattern of the first positioning mark comprises one or a combination of a letter pattern, a number pattern, a character pattern, a matrix pattern, a regular figure pattern, and an irregular figure pattern. Alternatively, the pattern of the second positioning mark comprises one or a combination of a letter pattern, a number pattern, a character pattern, a matrix pattern, a regular figure pattern, and an irregular figure pattern.

17. A voltage conversion device, characterized by Comprising: a voltage conversion circuit for outputting after boosting or step-down conversion of a received voltage; the voltage conversion circuit comprises a switching device, and the switching device is the GaN device with a positioning mark according to any one of claims 1-16.

18. An electronic device, comprising: Comprising: a voltage conversion device according to claim 17, and an electrical equipment, wherein an output terminal of the voltage conversion device is connected with the electrical equipment.

Images