Photoelectric conversion substrate and flat panel detection apparatus

Abstract

A photoelectric conversion substrate and a flat panel detection apparatus. The photoelectric conversion substrate comprises a first region, and the photoelectric conversion substrate further comprises a substrate and at least one pixel unit, which is located on one side of the substrate and located in the first region, wherein the pixel unit comprises a photoelectric conversion element, which is located on one side of the substrate; the photoelectric conversion element comprises a first electrode, a photoelectric conversion layer and a second electrode, and the first electrode, the photoelectric conversion layer and the second electrode are sequentially stacked away from the substrate; the pixel unit further comprises at least three conductive patterns, which are located between the photoelectric conversion element and the substrate, the at least three conductive patterns are sequentially stacked away from the substrate and insulated from each other, and signals of any two adjacent ones of the at least three conductive patterns and the first electrode are different, and the orthographic projections of any two adjacent ones of the at least three conductive patterns and the first electrode on the substrate at least partially overlap. The dynamic range of the photoelectric conversion substrate during use is significantly improved, and the detail presentation capability of the photoelectric conversion substrate for a collected image can be significantly improved.

Description

Photoelectric conversion substrate and flat panel detection device TECHNICAL FIELD

[0001] The embodiment of the present disclosure belongs to the technical field of flat panel detectors, and particularly relates to a photoelectric conversion substrate and a flat panel detection device. BACKGROUND

[0002] With the continuous development of FPXD (Flat Panel X-ray Detector), small-size pixels and high spatial resolution products are the future development trend. SUMMARY

[0003] The embodiment of the present disclosure provides a photoelectric conversion substrate and a flat panel detection device.

[0004] The embodiment of the present disclosure provides a photoelectric conversion substrate, comprising a first region,

[0005] The photoelectric conversion substrate comprises a substrate,

[0006] at least one pixel unit is located on one side of the substrate and in the first region;

[0007] The pixel unit comprises a photoelectric conversion element,

[0008] The photoelectric conversion element comprises a first electrode, a photoelectric conversion layer and a second electrode, and the first electrode, the photoelectric conversion layer and the second electrode are sequentially stacked away from the substrate;

[0009] The pixel unit further comprises at least three conductive patterns located between the photoelectric conversion element and the substrate, and the at least three conductive patterns are sequentially stacked away from the substrate and insulated from each other,

[0010] The signals of any two adjacent ones of the at least three conductive patterns and the first electrode are different;

[0011] The orthographic projections of any two adjacent ones of the at least three conductive patterns and the first electrode on the substrate at least partially overlap.

[0012] In some embodiments, the at least three conductive patterns comprise a first conductive pattern, a second conductive pattern and a third conductive pattern,

[0013] The first conductive pattern, the second conductive pattern and the third conductive pattern are sequentially stacked away from the substrate;

[0014] The orthographic projections of the first conductive pattern, the second conductive pattern and the third conductive pattern on the substrate are located within the orthographic projection area of the first electrode on the substrate.

[0015] In some embodiments, the substrate includes a base and a transistor, the transistor is located on a side of the base close to the photoelectric conversion element;

[0016] The transistor includes a gate, a gate insulating layer, an active layer, a first electrode and a second electrode stacked in sequence away from the base,

[0017] The first conductive pattern is located in the same layer as the gate;

[0018] The second conductive pattern is located in the same layer as the first electrode and the second electrode, and the second conductive pattern is connected to the first electrode as an integral structure;

[0019] The gate insulating layer is also provided between the first conductive pattern and the second conductive pattern;

[0020] The photoelectric conversion substrate further includes a first insulating layer and a second insulating layer, the first insulating layer is located between the second conductive pattern and the third conductive pattern; the second insulating layer is located between the third conductive pattern and the first electrode;

[0021] Further comprising at least a first via hole opened in the second insulating layer and the first insulating layer, the first electrode is electrically connected to the first electrode through the first via hole.

[0022] In some embodiments, the second conductive pattern and the first electrode and the connection area of the two at least partially overlap with the orthographic projection of the first conductive pattern on the base,

[0023] The overlapping area of the second conductive pattern and the first electrode and the connection area of the two with the orthographic projection of the first conductive pattern on the base does not overlap with the orthographic projection of the gate on the base.

[0024] In some embodiments, further comprising a plurality of scan lines and a plurality of data lines,

[0025] The number of pixel units is a plurality, and a plurality of pixel units are arranged in an array,

[0026] The scan line is located between adjacent rows of the array, and the scan line extends along the row direction of the array; the data line is located between adjacent columns of the array, and the data line extends along the column direction of the array;

[0027] The pixel unit is located in the area surrounded by the scan line and the data line, the scan line is located in the same layer as the first conductive pattern, and the data line is located in the same layer as the second conductive pattern;

[0028] a projection of the first conductive pattern on the substrate covers a projection of the second conductive pattern on the substrate adjacent to the data line;

[0029] a projection of the second conductive pattern on the substrate covers a projection of the first conductive pattern on the substrate adjacent to the scan line.

[0030] In some embodiments, a thickness of the second insulating layer is less than a thickness of the first insulating layer;

[0031] a projection of the third conductive pattern on the substrate covers a projection of the transistor on the substrate,

[0032] and a projection of the third conductive pattern and the first via on the substrate does not overlap.

[0033] In some embodiments, a thickness of the second insulating layer is greater than a thickness of the first insulating layer;

[0034] a projection of the third conductive pattern on the substrate does not overlap with a projection of the first via and the transistor on the substrate.

[0035] In some embodiments, a projection of the photoelectric conversion layer and the second electrode on the substrate is within a projection area of the first electrode on the substrate;

[0036] a projection of the first electrode on the substrate covers a projection of the first via and the transistor on the substrate;

[0037] a projection of the photoelectric conversion layer and the second electrode on the substrate covers a projection of the transistor on the substrate;

[0038] a projection of the photoelectric conversion layer and the second electrode on the substrate does not overlap with a projection of the first via on the substrate.

[0039] In some embodiments, a second region is further included, the second region is around a periphery of the first region, and the photoelectric conversion element is located in the first region;

[0040] The photoelectric conversion substrate further includes a first trace, a second trace, and a bus line,

[0041] the first trace is in the same layer as the first conductive pattern and is electrically connected;

[0042] the second trace is in the same layer as the third conductive pattern and is electrically connected;

[0043] the bus line is located in the second region;

[0044] The first traces and the second traces extend from the first region to the second region and are electrically connected with the bus line;

[0045] The number of the first traces is plural, and the number of the second traces is plural.

[0046] Each of the first traces extends in a row direction of the array and is electrically connected with the first conductive patterns in the same row.

[0047] Each of the second traces extends in a column direction of the array and is electrically connected with the third conductive patterns in the same column.

[0048] Alternatively, each of the second traces extends in the row direction of the array and is electrically connected with the third conductive patterns in the same row.

[0049] In some embodiments, further comprising a third trace and a third insulating layer,

[0050] The third trace is located on a side of the second electrode facing away from the substrate.

[0051] The third insulating layer is located between the second electrode and the third trace.

[0052] The third trace is electrically connected with the second electrode through a second via hole formed in the third insulating layer.

[0053] The third trace extends from the first region to the second region and is electrically connected with the bus line.

[0054] In some embodiments, the number of the third traces is plural.

[0055] Each of the third traces extends in the column direction of the array and is electrically connected with the second electrodes of the photoelectric conversion elements in the same column.

[0056] Alternatively, each of the third traces extends in the row direction of the array and is electrically connected with the second electrodes of the photoelectric conversion elements in the same row.

[0057] In some embodiments, the third trace at least partially overlaps with a normal projection of the transistor on the substrate.

[0058] Alternatively, the third trace at least partially overlaps with a normal projection of the transistor and the first via hole on the substrate.

[0059] In some embodiments, the bus line comprises a plurality of bus line blocks,

[0060] The bus line block comprises a first pattern, a second pattern and a third pattern,

[0061] The first pattern is located in the same layer as the third conductive pattern, and the first pattern is electrically connected with the second trace;

[0062] The second pattern is located in the same layer as the first electrode;

[0063] The third pattern is located in the same layer as the third trace, and the third pattern is electrically connected with the third trace;

[0064] The first pattern, the second pattern and the third pattern at least partially overlap in orthographic projection on the substrate;

[0065] The second insulating layer is further arranged between the first pattern and the second pattern, and the second pattern is electrically connected with the first pattern through a third via hole formed in the second insulating layer;

[0066] The second pattern, the third pattern and the third insulating layer are sequentially stacked in a direction away from the substrate, and the third insulating layer comprises a first sub-layer and a second sub-layer sequentially stacked away from the substrate,

[0067] The third pattern is electrically connected with the second pattern through a fourth via hole formed in the second sub-layer and a fifth via hole formed in the first sub-layer;

[0068] The fifth via hole has a larger orthographic projection area on the substrate than the third via hole;

[0069] The fifth via hole has a larger orthographic projection area on the substrate than the fourth via hole;

[0070] The orthographic projections of the third via hole and the fourth via hole on the substrate are located within the orthographic projection area of the fifth via hole on the substrate.

[0071] In some embodiments, the bus block further comprises a fourth pattern,

[0072] The fourth pattern is located in the same layer as the first conductive pattern, and the fourth pattern is electrically connected with the first trace;

[0073] The gate insulating layer and the first insulating layer are further arranged between the fourth pattern and the first pattern, and the first insulating layer comprises a third sub-layer and a fourth sub-layer, the third sub-layer and the fourth sub-layer are stacked in a direction away from the substrate,

[0074] The first pattern is electrically connected with the fourth pattern through a sixth via hole formed in the gate insulating layer, a seventh via hole formed in the fourth sub-layer and an eighth via hole formed in the third sub-layer;

[0075] the fifth via and the eighth via have at least partially overlapped orthographic projections on the substrate;

[0076] the eighth via has a larger orthographic projection area on the substrate than the sixth via;

[0077] the eighth via has a larger orthographic projection area on the substrate than the seventh via;

[0078] the third via, the fourth via, the sixth via and the seventh via have orthographic projections on the substrate within the overlapped area of the fifth via and the eighth via.

[0079] In some embodiments, the fifth via and the third via and the fourth via within the orthographic projection area of the fifth via on the substrate constitute a via unit, or the fifth via and the eighth via and the third via, the fourth via, the sixth via and the seventh via within the overlapped area of the fifth via and the eighth via on the substrate constitute a via unit.

[0080] Each of the bus blocks comprises a plurality of the via units, and the plurality of the via units are sequentially and spacedly distributed along the extension direction of the bus block.

[0081] In some embodiments, a plurality of through holes are further formed in the bus block,

[0082] The through holes are uniformly distributed in the interval area between any two adjacent via units.

[0083] The through holes comprise first through holes formed in the first pattern, second through holes formed in the second pattern and third through holes formed in the third pattern.

[0084] The centers of the first through holes, the second through holes and the third through holes coincide.

[0085] The orthographic projection areas of the first through holes, the second through holes and the third through holes on the substrate increase sequentially, and the orthographic projection of the first through hole on the substrate is within the orthographic projection area of the second through hole on the substrate, and the orthographic projection of the second through hole on the substrate is within the orthographic projection area of the third through hole on the substrate.

[0086] Alternatively, the first via hole, the second via hole and the third via hole have areas of their orthogonal projections on the substrate in a decreasing order; the orthogonal projection of the third via hole on the substrate is located within the orthogonal projection area of the second via hole on the substrate, and the orthogonal projection of the second via hole on the substrate is located within the orthogonal projection area of the first via hole on the substrate.

[0087] In some embodiments, the bus further comprises bus traces, the bus traces are located in the same layer as the third pattern, and the bus traces are electrically connected with the third pattern;

[0088] Each bus block is electrically connected with one first trace;

[0089] Each bus block is electrically connected with one second trace;

[0090] Each bus block is electrically connected with one third trace.

[0091] In some embodiments, the second region comprises two first sub-regions and two second sub-regions, the two first sub-regions are oppositely arranged, and the two second sub-regions are oppositely arranged;

[0092] A plurality of bus blocks are distributed in each of the two first sub-regions, and the plurality of bus blocks in the two first sub-regions are arranged in a staggered manner along the transmission direction of the bus signal, and the transmission directions of the bus signal in the two first sub-regions are opposite;

[0093] A plurality of bus blocks are distributed in each of the two second sub-regions, and the plurality of bus blocks in the two second sub-regions are arranged in a staggered manner along the transmission direction of the bus signal, and the transmission directions of the bus signal in the two second sub-regions are opposite;

[0094] The transmission directions of the bus signal in the first sub-region and the second sub-region form an included angle greater than 0°.

[0095] In some embodiments, the bus further comprises a transition block located in the second region and between the adjacent first sub-region and second sub-region;

[0096] The transition block connects the bus blocks in the first sub-region and the bus blocks in the second sub-region;

[0097] The transition block comprises a first part, and the first part has the same structure as the bus block;

[0098] The first portion comprises a plurality of the via units, and the plurality of the via units are arranged in sequence and at intervals along the arrangement direction of the plurality of the bus blocks in the first sub-region, or the plurality of the via units are arranged in sequence and at intervals along the arrangement direction of the plurality of the bus blocks in the second sub-region.

[0099] In some embodiments, the electrostatic discharge electrode is further included, and is located in the second region and at the same layer as the first conductive pattern.

[0100] The transition block further comprises a second portion, the second portion is at the same layer as the first pattern, the second pattern and / or the third pattern, and a plurality of hollows are arranged in the second portion.

[0101] The electrostatic discharge electrode and the plurality of the hollows at least partially overlap in the orthographic projection on the substrate.

[0102] In some embodiments, the second sub-layer covers the hole wall of the fifth via.

[0103] The second sub-layer covers the hole wall of the second via in the first sub-layer.

[0104] The second insulating layer adopts an inorganic material, and the second insulating layer covers the hole wall of the first via in the third sub-layer.

[0105] The fourth sub-layer covers the hole wall of the eighth via in the third sub-layer.

[0106] The present disclosure further provides a flat panel detection device, which comprises the photoelectric conversion substrate.

[0107] The photoelectric conversion substrate provided by the present disclosure can form a capacitance between any two adjacent conductive patterns and the first electrode by applying different signals to any two adjacent conductive patterns and the first electrode and at least partially overlapping the orthographic projection of any two adjacent conductive patterns and the first electrode on the substrate, thereby additionally increasing at least three storage capacitances on the basis of the capacitance of the photoelectric conversion element itself. Compared with the capacitance of the photodiode in the related art, the capacitance of the photoelectric conversion element in the present embodiment is greatly increased on the basis of the capacitance itself, thereby greatly improving the contrast of the image detected by the photoelectric conversion element, and further greatly improving the dynamic range of the photoelectric conversion substrate in use, and greatly improving the detail presentation capability of the image collected by the photoelectric conversion substrate.

[0108] The flat panel detector provided by the embodiments of the present disclosure has a greatly improved contrast ratio of the detected image by using the photoelectric conversion substrate, so that the dynamic range of the flat panel detector during use is greatly improved, and the detail presentation capability of the flat panel detector for collecting images is greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0109] The accompanying drawings are included to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, which are used to explain the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent from the detailed description of the specific example embodiments described below, taken in conjunction with the accompanying drawings, in which:

[0110] FIG. 1a is a structural schematic diagram of a photodiode in the related art.

[0111] FIG. 1b is an equivalent circuit diagram of the photodiode in the related art.

[0112] FIG. 2a is a partial structural top view of a flat panel detector in the related art.

[0113] FIG. 2b is a structural sectional view along the AA' section line in FIG. 2a.

[0114] FIG. 3a is a partial structural top view of a photoelectric conversion substrate in an embodiment of the present disclosure.

[0115] FIG. 3b is a structural sectional view along the BB' section line in FIG. 3a.

[0116] FIG. 4a is an overlapping top view of the first conductive pattern and the second conductive pattern in the photoelectric conversion substrate in an embodiment of the present disclosure.

[0117] FIG. 4b is an overlapping top view of the first electrode layer and the second electrode layer in the flat panel detector in FIG. 2a.

[0118] FIG. 5a is a partial structural top view of another photoelectric conversion substrate in an embodiment of the present disclosure.

[0119] FIG. 5b is a structural sectional view along the CC' section line in FIG. 5a.

[0120] FIG. 6a is a top view of the connection between the wiring in the first area and the bus in the second area in an embodiment of the present disclosure.

[0121] FIG. 6b is an equivalent circuit diagram of the connection between the wiring in the first area and the bus in the second area in an embodiment of the present disclosure.

[0122] FIG. 7a is a partial structural top view of still another photoelectric conversion substrate in an embodiment of the present disclosure.

[0123] Fig. 7b is a top view of the connection between the wire in the first area and the bus in the second area of the photoelectric conversion substrate of Fig. 7a.

[0124] Fig. 8a is a top view of a partial structure of another photoelectric conversion substrate according to an embodiment of the present disclosure.

[0125] Fig. 8b is a top view of the connection between the wire in the first area and the bus in the second area of the photoelectric conversion substrate of Fig. 8a.

[0126] Fig. 9a is a top view of a partial structure of the photoelectric conversion substrate according to an embodiment of the present disclosure.

[0127] Fig. 9b is a cross-sectional view of a structure along the cutting line DD' of Fig. 9a.

[0128] Fig. 9c is a cross-sectional view of another structure along the cutting line DD' of Fig. 9a.

[0129] Fig. 10 is a top view of the distribution of the bus block in the second area of the photoelectric conversion substrate according to an embodiment of the present disclosure.

[0130] Fig. 11 is a top view of the first distance according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0131] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, a photoelectric conversion substrate and a flat panel detection device according to an embodiment of the present disclosure are described in further detail below with reference to the accompanying drawings and specific embodiments.

[0132] In the following, the embodiments of the present disclosure will be described more fully with reference to the accompanying drawings, of which embodiments shown should not be construed as limiting the present disclosure, which is set forth in the claims. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0133] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes. Therefore, the regions illustrated in the drawings have a schematic property, and the shape of the regions shown in the drawings exemplifies a specific shape of the regions, but is not intended to be limiting.

[0134] In the related art, the working principle of the FPXD (Flat Panel X-ray Detector) is, for example, to convert X-rays into visible light by using a cesium iodide crystal, and the visible light is irradiated onto a PN junction of a photodiode. The PN junction, when no light is present, is equivalent to a capacitor, and is pre-charged with an electric charge. The light increases the reverse leakage current, causing the PN junction to discharge. The discharge amount is proportional to the incident photon density. That is, the PN junction can convert visible light into an electrical signal. The specific conversion principle is as follows: as shown in FIGS. 1a and 1b, when a reverse voltage is applied to the PN junction, the size of the reverse current depends on the concentration of the minority carriers in the P region and the N region. When no light is present, the minority carriers (electrons) in the P region and the minority carriers (holes) in the N region are very few, and thus the reverse current is very small. However, when light irradiates the PN junction, as long as the photon energy hv is greater than the band gap width of the material, a photoelectron-hole pair is generated at the PN junction and in the vicinity thereof, thereby greatly increasing the concentration of the minority carriers in the P region and the N region. The number of these carriers has little effect on the majority carriers, but greatly increases the concentration of the minority carriers in the P region and the N region. Under the action of the reverse voltage (the P region is connected to a negative, and the N region is connected to a positive), the reverse saturation leakage current greatly increases, forming a photocurrent that changes with the incident light intensity. When the photocurrent passes through a load (such as a resistor R L ), a voltage signal that changes with the incident light is obtained across the resistor. If the intensity of the incident light changes, the concentration of the photoelectron-hole pairs will change accordingly, and the intensity of the photocurrent passing through the external circuit will also change accordingly. The photodiode converts the visible light into an electrical signal.

[0135] The electrical signal converted by the photodiode is converted into a digital signal by an amplifier and an analog-to-digital converter. The digital signal represents the X-ray intensity distribution inside the detected object. The digital signal is processed and analyzed by a computer, and is processed by an image reconstruction algorithm to form a two-dimensional image of the inside of the detected object. Finally, the image is presented to an operator through a display, so as to be detected and analyzed.

[0136] For small-pixel TFT+PIN (thin-film transistor + photodiode) flat panel photodetectors, such as those used for breast cancer detection and industrial applications, reducing pixel size leads to a significant reduction in the light-receiving area of ​​the PIN (photodiode). This results in a further loss of pixel fill rate (i.e., the area of ​​the photodiode that receives light), consequently reducing the photodiode's capacitance (Cpin). This reduction in photodiode capacitance means a decrease in the full-well capacitance (the maximum amount of charge that can be stored in the pixel well). This reduced capacitance leads to a decrease in the amount of charge converted from the photodiode after receiving light, causing the two-dimensional image of the detected object to saturate at a very low charge dose. This results in decreased image contrast and a lower dynamic range (the range within which the pixel's response value reaches its response threshold during the acquisition of projection data) in actual use, severely limiting the ability of the flat panel photodetector to render detailed images.

[0137] Dynamic range, in this context, refers to the ratio of the maximum to the minimum value of a variable signal (such as sound or light), and can be expressed as a logarithm to base 10 (decibels) or a logarithm to base 2. High Dynamic Range Imaging (HDRI or HDR) is a technique used in computer graphics and cinematography to achieve a greater dynamic range of exposure (i.e., a greater difference between light and dark areas) than ordinary digital imaging techniques. The goal of HDR imaging is to accurately represent the wide range of brightness in the real world, from direct sunlight to the darkest shadows.

[0138] To address the problems caused by the reduced capacitance of the photodiode, related technologies involve connecting an additional storage capacitor in parallel with the photodiode. As shown in Figures 2a and 2b, an additional storage capacitor is formed between the photodiode 24 and its bottom electrode 19 by adding two electrode layers (such as the first electrode layer 17 and the second electrode layer 18) to the flat panel detector for breast detection. However, since one of the added electrode layers (i.e., the first electrode layer 17) is connected to the bottom electrode 19 of the photodiode 24 in situ through perforations in multiple insulating layers 20 within the pixel region, and the photoelectric conversion layer 22 of the photodiode 24 is typically not located at the perforation position, a certain pixel fill rate is lost. Although this substantially increases the pixel capacitance, it further reduces the already limited effective photosensitive area of ​​the photodiode 24. Limited by the effective photosensitive area of ​​photodiode 24 and the thickness of the intermediate insulating layer between adjacent electrodes that constitutes the additional capacitor (the thicker the intermediate insulating layer, the smaller the capacitance), this solution can only increase the storage capacitance by a very limited amount. At most, the capacitance of photodiode 24 can be doubled, but it is difficult to achieve a larger capacitance. As a result, it is difficult to achieve a higher dynamic range of the flat panel photodetector. In application scenarios where the dynamic range of the flat panel photodetector is required to be high, the above solution is no longer applicable.

[0139] To address the series of problems caused by the reduced capacitance of the photodiode, in a first aspect, embodiments of this disclosure provide a photoelectric conversion substrate, as shown in Figures 3a and 3b, comprising a first region 201. The photoelectric conversion substrate includes a substrate 1 and at least one pixel unit 200 located on one side of the substrate 1 and within the first region 201. The pixel unit 200 includes a photoelectric conversion element 2 located on one side of the substrate 1. The photoelectric conversion element 2 includes a first electrode 21, a photoelectric conversion layer 22, and a second electrode 23, which are stacked sequentially away from the substrate 1. The pixel unit 200 also includes at least three conductive patterns located between the photoelectric conversion element 2 and the substrate 1. The at least three conductive patterns are stacked sequentially away from the substrate 1 and are mutually insulated. The signals of the at least three conductive patterns and any two adjacent first electrodes 21 are different. The orthographic projections of the at least three conductive patterns and any two adjacent first electrodes 21 on the substrate 1 at least partially overlap.

[0140] In this embodiment, a capacitance is formed between the first electrode 21 and the second electrode 23 of the photoelectric conversion element 2. By making the signals applied to at least three conductive patterns and any two adjacent first electrodes 21 different, and ensuring that the orthographic projections of at least three conductive patterns and any two adjacent first electrodes 21 on the substrate 1 at least partially overlap, a capacitance can be formed between at least three conductive patterns and any two adjacent first electrodes 21. This adds at least three storage capacitors to the capacitance of the photoelectric conversion element 2 itself. Compared to the capacitance of photodiodes in related technologies, the capacitance of the photoelectric conversion element 2 in this embodiment is significantly increased based on its own capacitance, thereby greatly improving the contrast of the image detected by the photoelectric conversion element 2. This, in turn, greatly improves the dynamic range of the photoelectric conversion substrate during use, and significantly enhances the detail rendering capability of the image acquired by the photoelectric conversion substrate.

[0141] In some embodiments, as shown in FIG3b, at least three conductive patterns include a first conductive pattern 3, a second conductive pattern 4, and a third conductive pattern 5, which are stacked sequentially away from the substrate 1; the orthogonal projections of the first conductive pattern 3, the second conductive pattern 4, and the third conductive pattern 5 on the substrate 1 are located within the orthogonal projection area of ​​the first electrode 21 on the substrate 1.

[0142] In some embodiments, as shown in FIG3a, the photoelectric conversion substrate further includes multiple scan lines 8 and multiple data lines 9. The number of pixel units is multiple, and the multiple pixel units are arranged in an array. The scan lines 8 are located between adjacent rows of the array and extend along the row direction X of the array. The data lines 9 are located between adjacent columns of the array and extend along the column direction Y of the array. The pixel units are located in the area enclosed by the scan lines 8 and the data lines 9.

[0143] Specifically, the effective boundary of the first conductive pattern 3 and the second conductive pattern 4 is the boundary of the overlapping area of ​​their orthogonal projections on the substrate 1 within the region enclosed by the scan line 8 and the data line 9. The effective boundary of the first conductive pattern 3 and the second conductive pattern 4 refers to the boundary of the portion between them where capacitance can be formed, because capacitance can only be formed within the overlapping area of ​​their orthogonal projections. Similarly, the effective boundary of the second conductive pattern 4 and the third conductive pattern 5 is the boundary of the overlapping area of ​​their orthogonal projections on the substrate 1 within the region enclosed by the scan line 8 and the data line 9. The effective boundary of the third conductive pattern 5 and the first electrode 21 is the boundary of the overlapping area of ​​their orthogonal projections on the substrate 1 within the region enclosed by the scan line 8 and the data line 9.

[0144] In this embodiment, compared to the capacitance of a photodiode in related technologies, the capacitance of the photoelectric conversion element 2 in this embodiment can be increased to more than four times its own capacitance, thereby greatly improving the contrast of the image detected by the photoelectric conversion element 2, and thus greatly improving the dynamic range of the photoelectric conversion substrate during use.

[0145] In some embodiments, the substrate 1 includes a base 10 and a transistor 11, the transistor 11 being located on the side of the base 10 closer to the photoelectric conversion element 2; the transistor 11 includes a gate 111, a gate insulating layer 112, an active layer 113, a first electrode 114, and a second electrode 115 stacked sequentially away from the base 10, the first conductive pattern 3 being located on the same layer as the gate 111; the second conductive pattern 4 being located on the same layer as the first electrode 114 and the second electrode 115, and the second conductive pattern 4 being connected to the first electrode 114 as an integral structure; the gate insulating layer 112 is also disposed between the first conductive pattern 3 and the second conductive pattern 4; the photoelectric conversion substrate also includes a first insulating layer 6 and a second insulating layer 7, the first insulating layer 6 being located between the second conductive pattern 4 and the third conductive pattern 5; the second insulating layer 7 being located between the third conductive pattern 5 and the first electrode 21; it also includes a first via 101 at least formed in the second insulating layer 7 and the first insulating layer 6, the first electrode 21 being electrically connected to the first electrode 114 through the first via 101.

[0146] In this configuration, the signals on the second conductive pattern 4 and the first electrode 21 are the same, the signals on the first conductive pattern 3 and the third conductive pattern 5 are the same, and the signals on the first conductive pattern 3 and the second conductive pattern 4 are different. This results in the overlapping region of the orthographic projections of the first conductive pattern 3 and the second conductive pattern 4 forming a first capacitor, the overlapping region of the orthographic projections of the second conductive pattern 4 and the third conductive pattern 5 forming a second capacitor, and the overlapping region of the orthographic projections of the third conductive pattern 5 and the first electrode 21 forming a third capacitor. The first, second, and third capacitors are all additional capacitors added to the capacitance of the photoelectric conversion element 2 itself, and they are connected in parallel with the capacitance of the photoelectric conversion element 2 itself.

[0147] In some embodiments, the signals of the first conductive pattern 3 and the third conductive pattern 5 are the same, such as the signals of the first conductive pattern 3 and the third conductive pattern 5 being DC negative voltage signals; the signals of the second conductive pattern 4 and the first electrode 21 are the signals of the first electrode 114 of the transistor 11.

[0148] In some embodiments, the first conductive pattern 3 and the gate 111 are located in the same layer; the second conductive pattern 4 and the first electrode 114 and the second electrode 115 are located in the same layer; being in the same layer means that the film layers are prepared by a single patterning process (including film deposition, exposure, development, etching, etc.) during the fabrication process. The film layers located in the same layer in terms of film structure can be located on the same plane with the same distance from the substrate 10, or they can be located on different planes with different distances from the substrate 10.

[0149] In some embodiments, the active layer 113 can be amorphous silicon (a-Si) material or IGZO (indium gallium zinc oxide) material, which can be adjusted according to the application scenario of the photoelectric conversion substrate.

[0150] In some embodiments, as shown in FIG4a, the second conductive pattern 4 and the first electrode 114 and their connection area overlap at least partially with the orthographic projection of the first conductive pattern 3 on the substrate 10, and the overlapping area of ​​the second conductive pattern 4 and the first electrode 114 and their connection area with the orthographic projection of the first conductive pattern 3 on the substrate 10 does not overlap with the orthographic projection of the gate 111 on the substrate 10.

[0151] The connection region between the second conductive pattern 4 and the first electrode 114 refers to the region that does not overlap with the first conductive pattern 3 and the active layer 113.

[0152] In related technologies, as shown in Figures 4b and 2b, two electrode layers are added below the bottom electrode of the photodiode. The first electrode layer 17 is disposed on the same layer as the gate 111, and the second electrode layer 18 is disposed on the same layer as the first electrode 114 of the transistor 11. The first electrode 114 is designed as an island, and the first electrode 114 is disconnected from the second electrode layer 18. The first electrode 114 is electrically connected to the lower first electrode layer 17 through a via. The second electrode layer 18 is connected to the bias voltage signal, thereby forming a capacitor in the overlapping area of ​​the orthogonal projections of the second electrode layer 18 and the first electrode layer 17. At the same time, the second electrode layer 18 and the bottom electrode 19 of the photodiode form a capacitor in the overlapping area of ​​their orthogonal projections. These two capacitors are additional capacitors added on top of the inherent capacitance of the photodiode. Compared to the pattern arrangement of the first electrode layer 17 and the second electrode layer 18 in Figure 4b, in this embodiment, the first electrode 114 of the transistor 11 in Figure 4a is arranged on the same layer as the second conductive pattern 4 and connected as an integral structure. That is, the first electrode 114 of the transistor 11 in this embodiment is designed with a large area spread out. As can be seen from the comparison between Figure 4a and Figure 4b, the area of ​​the overlapping region of the orthographic projection of the first conductive pattern 3 and the second conductive pattern 4 in this embodiment is significantly larger than the area of ​​the overlapping region of the orthographic projection of the first electrode layer 17 and the second electrode layer 18 in the related art. Therefore, the pattern design of the first conductive pattern 3 and the second conductive pattern 4 in this embodiment can maximize the area of ​​the storage capacitor electrode formed between them, and at the same time maximize the area of ​​the storage capacitor electrode formed between the second conductive pattern 4 and the third conductive pattern 5, thereby maximizing the capacitance formed between the first conductive pattern 3 and the second conductive pattern 4 and between the second conductive pattern 4 and the third conductive pattern 5.

[0153] In some embodiments, as shown in Figures 3a and 4a, the photoelectric conversion substrate further includes multiple scan lines 8 and multiple data lines 9. There are multiple pixel units arranged in an array. The scan lines 8 are located between adjacent rows of the array and extend along the row direction X of the array. The data lines 9 are located between adjacent columns of the array and extend along the column direction Y of the array. The pixel units are located within the area enclosed by the scan lines 8 and the data lines 9. The scan lines 8 and the first conductive pattern 3 are located on the same layer, and the data lines 9 and the second conductive pattern 4 are located on the same layer. The orthographic projection of the first conductive pattern 3 onto the substrate 10 covers the orthographic projection of the edge of the second conductive pattern 4 adjacent to the data line 9 onto the substrate 10. The orthographic projection of the second conductive pattern 4 onto the substrate 10 covers the orthographic projection of the edge of the first conductive pattern 3 adjacent to the scan line 8 onto the substrate 10.

[0154] Since the data line 9 and the second conductive pattern 4 are located on the same layer, considering process capability and noise impact, it is necessary to ensure that a certain distance is maintained between the data line 9 and the second conductive pattern 4. This is achieved by making the orthographic projection of the first conductive pattern 3 on the substrate 10 cover the orthographic projection of the edge of the second conductive pattern 4 adjacent to the data line 9 on the substrate 10. This ensures that the data line 9 and the second conductive pattern 4 can be accurately fabricated while meeting process capability requirements, and also avoids signal interference between the data line 9 and the second conductive pattern 4. Similarly, since the scan line 8 and the first conductive pattern 3 are located on the same layer, considering process capability and noise impact, it is necessary to ensure that a certain distance is maintained between the scan line 8 and the first conductive pattern 3. This is achieved by making the orthographic projection of the second conductive pattern 4 on the substrate 10 cover the orthographic projection of the edge of the first conductive pattern 3 adjacent to the scan line 8 on the substrate 10. This ensures that the scan line 8 and the first conductive pattern 3 can be accurately fabricated while meeting process capability requirements, and also avoids signal interference between the scan line 8 and the first conductive pattern 3. On the other hand, as shown in Figure 4b, in the related art, the orthographic projection of the second electrode layer 18 on the substrate 10 covers the orthographic projection of each side edge of the first electrode layer 17 overlapping with it on the substrate 10. Compared with the edge coverage scheme of the second electrode layer 18 and the first electrode layer 17 in Figure 4b, the edge coverage scheme between the first conductive pattern 3 and the second conductive pattern 4 in this embodiment can also maximize the first capacitance formed between the first conductive pattern 3 and the second conductive pattern 4.

[0155] In some embodiments, as shown in Figures 3a and 3b, the thickness of the second insulating layer 7 is less than the thickness of the first insulating layer 6; the orthographic projection of the third conductive pattern 5 on the substrate 10 covers the orthographic projection of the transistor 11 on the substrate 10, and the orthographic projections of the third conductive pattern 5 and the first via 101 on the substrate 10 do not overlap.

[0156] The first insulating layer 6 comprises a first passivation layer 61, an organic sublayer 62, and a second passivation layer 63, stacked sequentially away from the substrate 10. The organic sublayer 62 is a resin layer. During the fabrication of the first insulating layer 6, the first passivation layer 61 is not patterned immediately after deposition; instead, simultaneous etching is performed after the second passivation layer 63 is deposited, thus saving a masking process. The first passivation layer 61, the second passivation layer 63, and the second insulating layer 7 are all made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride.

[0157] In some embodiments, as shown in FIG3b, at the location of the first via 101, the second insulating layer 7 covers the hole wall of the first via 101 in the first passivation layer 61, the organic sublayer 62 and the second passivation layer 63, and the second insulating layer 7 extends to contact the second conductive pattern 4.

[0158] In some embodiments, as shown in FIG3b, when the opening of the second insulating layer 7 at the location of the first via 101 is smaller than the opening of the first insulating layer 6 at the location of the first via 101, a step is formed between the sidewall of the second insulating layer 7 covering the first insulating layer 6 and the portion of the second insulating layer 7 in contact with the second conductive pattern 4 at the location of the first via 101, thereby forming a step shape for the first electrode 21 at the step location.

[0159] In some embodiments, the second insulating layer 7 covers the hole wall of the first through-hole 101 in the organic sublayer 62. In this way, the second insulating layer 7 can completely wrap the hole wall of the first through-hole 101 in the organic sublayer 62, thereby avoiding the problem of the metal film layer in direct contact with it being peeled off due to the release of waste gas from the organic sublayer 62 of the resin material during subsequent processes.

[0160] In some embodiments, the thickness of the first insulating layer 6 ranges from 18,000 to 30,000 angstroms; the thickness of the second insulating layer 7 ranges from 1,000 to 3,000 angstroms. This configuration allows the capacitance of the photoelectric conversion element 2 to be increased to more than four times its own capacitance by adjusting the thickness of the first insulating layer 6 and the second insulating layer 7, thereby significantly improving the contrast of the image detected by the photoelectric conversion element 2, and consequently significantly improving the dynamic range of the photoelectric conversion substrate during use.

[0161] In some embodiments, as shown in Figures 5a and 5b, the thickness of the second insulating layer 7 is greater than the thickness of the first insulating layer 6; the orthographic projection of the third conductive pattern 5 on the substrate 10 does not overlap with the orthographic projections of the first via 101 and the transistor 11 on the substrate 10.

[0162] In some embodiments, the second insulating layer 7 includes a first inorganic layer 71, a first organic layer 72, and a second inorganic layer 73 stacked sequentially away from the substrate 10, wherein the first organic layer 72 is a resin layer. During the fabrication of the second insulating layer 7, the first inorganic layer 71 is not patterned immediately after deposition; instead, simultaneous etching is performed after the second inorganic layer 73 is deposited, thus saving a masking process. The first inorganic layer 71, the second inorganic layer 73, and the first insulating layer 6 are all made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride.

[0163] Since the third conductive pattern 5 and the transistor 11 are separated only by a thin first insulating layer 6, if the orthographic projection of the third conductive pattern 5 on the substrate 10 covers the transistor 11, the capacitive coupling between the two will be strong, which will have an adverse effect on the switching characteristics of the transistor 11. Therefore, by ensuring that the orthographic projection of the third conductive pattern 5 on the substrate 10 does not overlap with the orthographic projection of the transistor 11 on the substrate 10, the signal in the third conductive pattern 5 can affect the switching characteristics of the transistor 11, thereby ensuring the normal switching characteristics of the transistor 11.

[0164] In some embodiments, as shown in FIG5b, at the location of the first via 101, the second inorganic layer 73 covers the hole wall of the first via 101 in the first organic layer 72, and the second inorganic layer 73 extends to contact the first inorganic layer 71.

[0165] In some embodiments, as shown in FIG5b, when the opening of the second inorganic layer 73 at the location of the first via 101 is larger than the opening of the first inorganic layer 71 and the first insulating layer 6 at the location of the first via 101, a step is formed between the sidewall of the second inorganic layer 73 covering the first organic layer 72 and the sidewall of the first inorganic layer 71 and the first insulating layer 6 at the location of the first via 101, thereby forming a step shape for the first electrode 21 at the step location.

[0166] In some embodiments, the second inorganic layer 73 covers the hole wall of the first through-hole 101 in the first organic layer 72. In this way, the second inorganic layer 73 can completely encapsulate the hole wall of the first through-hole 101 in the first organic layer 72, thereby avoiding the problem of metal film layer peeling off directly in contact with the first organic layer 72 due to the release of waste gas from the resin material during subsequent processes.

[0167] In some embodiments, as shown in FIG3a, the orthographic projections of the photoelectric conversion layer 22 and the second electrode 23 on the substrate 10 are located within the orthographic projection region of the first electrode 21 on the substrate 10; the orthographic projection of the first electrode 21 on the substrate 10 covers the orthographic projections of the first via 101 and the transistor 11 on the substrate 10; the orthographic projections of the photoelectric conversion layer 22 and the second electrode 23 on the substrate 10 cover the orthographic projection of the transistor 11 on the substrate 10; the orthographic projections of the photoelectric conversion layer 22 and the second electrode 23 on the substrate 10 do not overlap with the orthographic projection of the first via 101 on the substrate 10.

[0168] The orthographic projection of the photoelectric conversion layer 22 and the second electrode 23 on the substrate 10 does not overlap with the orthographic projection of the first via 101 on the substrate 10. This avoids the photoelectric conversion performance of the photoelectric conversion element 2 caused by the material of the photoelectric conversion layer 22 filling the first via 101, thereby ensuring the sensing performance of the photoelectric conversion element 2 for visible light.

[0169] In some embodiments, as shown in Figures 6a and 6b, the photoelectric conversion substrate further includes a second region 202, which surrounds the periphery of the first region 201, and the photoelectric conversion element 2 is located in the first region 201. The photoelectric conversion substrate also includes a first trace 12, a second trace 13, and a bus 14. The first trace 12 is located on the same layer as the first conductive pattern 3 and is electrically connected. The second trace 13 is located on the same layer as the third conductive pattern 5 and is electrically connected. The bus 14 is located in the second region 202. The first trace 12 and the second trace 13 extend from the first region 201 to the second region 202 and are electrically connected to the bus 14.

[0170] The first trace 12 is the portion located outside the effective boundary of the first conductive pattern 3 and electrically connected to the first conductive pattern 3, and the width of the first trace 12 is smaller than the dimension of the first conductive pattern 3 in any direction. The second trace 13 is the portion located outside the effective boundary of the third conductive pattern 5 and electrically connected to the third conductive pattern 5, and the width of the second trace 13 is smaller than the dimension of the third conductive pattern 5 in any direction.

[0171] In some embodiments, as shown in FIG6a, there are multiple first traces 12 and multiple second traces 13; there are multiple first conductive patterns 3, and each of the multiple first conductive patterns 3 corresponds to a multiple photoelectric conversion element 2; there are multiple third conductive patterns 5, and each of the multiple third conductive patterns 5 corresponds to a multiple photoelectric conversion element 2; each first trace 12 extends along the row direction X of the array and is electrically connected to the first conductive pattern 3 located in the same row; each second trace 13 extends along the column direction Y of the array and is electrically connected to the third conductive pattern 5 located in the same column.

[0172] In some embodiments, as shown in Figures 7a and 7b, each second trace 13 extends along the row direction X of the array and is electrically connected to the third conductive pattern 5 located in the same row.

[0173] In this embodiment, by extending each second trace 13 along the row direction X of the array, compared to extending each second trace 13 along the column direction Y of the array, the overlap capacitance caused by the overlap between the scan line 8 and the second trace 13 can be reduced, thereby reducing the load on the scan line 8. As shown in FIG7b, the connection position of the second trace 13 and the bus in the second area 202 needs to be changed, that is, the second trace 13 is changed from being extended along the column direction Y of the array and connected to the bus 14 to being extended along the row direction X of the array and connected to the bus 14.

[0174] In some embodiments, as shown in Figures 3a, 3b, 5a, and 5b, the photoelectric conversion substrate further includes a third trace 15 and a third insulating layer 16. The third trace 15 is located on the side of the second electrode 23 facing away from the substrate 10. The third insulating layer 16 is located between the second electrode 23 and the third trace 15. The third trace 15 is electrically connected to the second electrode 23 through a second via 102 formed in the third insulating layer 16. The third trace 15 extends from the first region 201 to the second region 202 and is electrically connected to the bus 14.

[0175] In some embodiments, as shown in Figures 3a, 3b, 5a and 5b, there are multiple third traces 15; each third trace 15 extends along the column direction Y of the array and is electrically connected to the second electrode 23 of the photoelectric conversion element 2 located in the same column.

[0176] In some embodiments, as shown in Figures 3a, 3b, 5a and 5b, the third trace 15 and the orthographic projection of the transistor 11 onto the substrate 10 at least partially overlap.

[0177] In some embodiments, the second via 102 at least partially overlaps with the orthographic projection of the transistor 11 onto the substrate 10.

[0178] When the surface of transistor 11 facing away from the substrate 10 cannot be filled, the third trace 15 (or the second via 102) overlaps with the orthographic projection of transistor 11 on the substrate 10, which can block the photoelectric conversion layer 22 at the unfilled position of the surface of transistor 11 facing away from the substrate 10, thereby preventing the photoelectric conversion layer 22 at that position from receiving light, and thus preventing photoelectric sensing abnormalities caused by abnormal photoelectric conversion performance of the photoelectric conversion layer at that position.

[0179] In some embodiments, the orthographic projections of the third trace 15 and the transistor 11 onto the substrate 10 may not overlap.

[0180] In some embodiments, the second via and the orthographic projection of the transistor on the substrate may not overlap.

[0181] In some embodiments, as shown in Figures 8a and 8b, each third trace 15 extends along the row direction X of the array and is electrically connected to the second electrode 23 of the photoelectric conversion element 2 located in the same row.

[0182] In some embodiments, as shown in FIG8a, the third trace 15 at least partially overlaps with the orthographic projections of the transistor 11 and the first via 101 on the substrate 10.

[0183] The third trace 15 is a metal trace. The overlap of the orthographic projection of the third trace 15 with the first via 101 reduces the obstruction of the light-receiving area of ​​the photoelectric conversion element 2 by the third trace 15, thereby increasing the pixel fill rate (i.e., the area of ​​the photoelectric conversion element 2 that receives light), and further improving the detection sensitivity of the photoelectric conversion substrate to X-rays. As shown in Figure 8b, the connection position of the third trace 15 and the bus 14 in the second region 202 is also synchronously adjusted so that the third trace 15 extends out along the row direction X of the array and connects to the bus 14.

[0184] In this embodiment, as shown in Figure 6b, the equivalent circuits of the first trace 12, the second trace 13, and the third trace 15 connected to the bus 14 are shown. The bus 14 is connected to a bias voltage signal (such as a DC negative voltage signal). That is, the first trace 12, the second trace 13, and the third trace 15 are connected to the same bias voltage signal. The first capacitor C0, the second capacitor C1, the third capacitor C2, and the capacitance of the photoelectric conversion element C3 itself are connected in parallel, which can increase the capacitance of the photoelectric conversion element 2 to more than 4 times its own capacitance, thereby greatly improving the contrast of the image detected by the photoelectric conversion element 2, and thus greatly improving the dynamic range of the photoelectric conversion substrate during use.

[0185] In some embodiments, as shown in Figures 9a and 9b, the bus 14 includes a plurality of bus blocks 140. Each bus block 140 includes a first pattern 1401, a second pattern 1402, and a third pattern 1403. The first pattern 1401 is located on the same layer as the third conductive pattern 5, and is electrically connected to the second trace 13. The second pattern 1402 is located on the same layer as the first electrode 21. The third pattern 1403 is located on the same layer as the third trace 15, and is electrically connected to the third trace 15. The orthographic projections of the first pattern 1401, the second pattern 1402, and the third pattern 1403 onto the substrate 10 are at least... The second insulating layer 7 is also disposed between the first pattern 1401 and the second pattern 1402. The second pattern 1402 is electrically connected to the first pattern 1401 through a third via 103 formed in the second insulating layer 7. The second pattern 1402, the third pattern 1403 and the third insulating layer 16 are stacked sequentially in a direction away from the substrate 10. The third insulating layer 16 includes a first sub-layer 161 and a second sub-layer 162 stacked sequentially away from the substrate 10. The third pattern 1403 is electrically connected to the second pattern 1402 through a fourth via 104 formed in the second sub-layer 162 and a fifth via 105 formed in the first sub-layer 161.

[0186] The first sublayer 161 is an organic material layer, and the second sublayer 162 is an inorganic material layer. The first pattern 1401, the second pattern 1402, and the third pattern 1403 are electrically connected to each other, which can reduce the resistance of the bus block 140, thereby reducing the loss of the bias voltage signal transmitted on the bus block 140.

[0187] In some embodiments, as shown in FIG9c, the bus block 140 further includes a fourth pattern 1404, which is located on the same layer as the first conductive pattern 3 and is electrically connected to the first trace 12; a gate insulating layer 112 and a first insulating layer 6 are also disposed between the fourth pattern 1404 and the first pattern 1401. The first insulating layer 6 includes a third sublayer and a fourth sublayer, which are stacked in a direction away from the substrate 10. The first pattern 1401 is electrically connected to the fourth pattern 1404 through a sixth via 106 formed in the gate insulating layer 112, a seventh via 107 formed in the fourth sublayer, and an eighth via 108 formed in the third sublayer.

[0188] In this embodiment, the third sublayer includes an organic sublayer 62, and the fourth sublayer includes a first passivation layer 61 and a second passivation layer 63. The first passivation layer 61, the organic sublayer 62, and the second passivation layer 63 are stacked sequentially in a direction away from the substrate 10. The first pattern 1401 is electrically connected to the fourth pattern 1404 through a sixth via 106 formed in the gate insulating layer 112, a seventh via 107 formed in the first passivation layer 61 and the second passivation layer 63, and an eighth via 108 formed in the organic sublayer 62.

[0189] The configuration of the fourth pattern 1404 and its electrical connection with the first pattern 1401 can further reduce the resistance of the bus block 140, thereby further reducing the loss of the bias voltage signal transmitted on the bus block 140.

[0190] In some embodiments, as shown in FIG9b, the orthographic projection area of ​​the fifth via 105 on the substrate 10 is greater than the orthographic projection area of ​​the third via 103 on the substrate 10; the orthographic projection area of ​​the fifth via 105 on the substrate 10 is greater than the orthographic projection area of ​​the fourth via 104 on the substrate 10; the orthographic projections of the third via 103 and the fourth via 104 on the substrate 10 are located within the orthographic projection area of ​​the fifth via 105 on the substrate 10.

[0191] The first sub-layer 161 is a resin layer that serves to planarize the photoelectric conversion substrate. The first sub-layer 161 has a relatively thick thickness (e.g., greater than 2 μm). The fifth via 105 in the first sub-layer 161 is designed as a via with a large opening area to facilitate metal overlap between the third pattern 1403 and the second pattern 1402. This avoids excessive via breakage due to the thickness of the first sub-layer 161, thus preventing the metal layer passing through the via from breaking and ensuring a stable electrical connection between the third pattern 1403 and the second pattern 1402.

[0192] In some embodiments, as shown in FIG9c, the orthographic projections of the fifth via 105 and the eighth via 108 on the substrate 10 at least partially overlap; the orthographic projection area of ​​the eighth via 108 on the substrate 10 is greater than the orthographic projection area of ​​the sixth via 106 on the substrate 10; the orthographic projection area of ​​the eighth via 108 on the substrate 10 is greater than the orthographic projection area of ​​the seventh via 107 on the substrate 10; the orthographic projections of the third via 103, the fourth via 104, the sixth via 106, and the seventh via 107 on the substrate 10 are located within the overlapping area of ​​the orthographic projections of the fifth via 105 and the eighth via 108 on the substrate 10.

[0193] The organic sublayer 62 is a resin layer that plays a planarization role in the photoelectric conversion substrate. The organic sublayer 62 is relatively thick (e.g., thicker than 2μm). The eighth via 108 in the organic sublayer 62 is designed as a via with a large opening area to facilitate metal overlap between the first pattern 1401 and the fourth pattern 1404. This avoids excessive via breakage due to the thickness of the organic sublayer 62, thus preventing the metal layer passing through the via from breaking and ensuring a stable electrical connection between the first pattern 1401 and the fourth pattern 1404.

[0194] In some embodiments, as shown in Figures 9a and 7b, the fifth via 105 and the third via 103 and the fourth via 104 located in the orthographic projection region of the fifth via 105 on the substrate 10 constitute a set of via units 100. Alternatively, the fifth via 105 and the eighth via 108, as well as the third via 103, the fourth via 104, the sixth via 106 and the seventh via 107 located in the overlapping region of their orthographic projections on the substrate 10, constitute a set of via units 100. Each bus block 140 includes a plurality of via units 100, and the plurality of via units 100 are distributed sequentially at intervals along the extension direction of the bus block 140.

[0195] As shown in Figure 9a, each bus block 140 is provided with three via units 100. The number of via units 100 on a bus block 140 can be adjusted according to the actual bus 14 wiring space and the resistance requirements of the bus 14.

[0196] In this embodiment, the first trace 12, the second trace 13 and the third trace 15 are electrically connected to the bus 14 through the via unit 100 disposed in the second region 202. Thus, the vias in the via unit 100 will not affect the fill rate of the pixels in the first region 201 (i.e., the area of ​​the photoelectric conversion element 2 that receives light), thereby improving the detection sensitivity of the photoelectric conversion substrate to X-rays.

[0197] In some embodiments, as shown in FIG9a, the bus block 140 is further provided with a plurality of through holes H1, which are uniformly distributed in the interval region between any two adjacent via units 100; the through holes H1 include a first through hole M1 in the first pattern 1401, a second through hole M2 in the second pattern 1402, and a third through hole M3 in the third pattern 1403; the centers of the first through hole M1, the second through hole M2, and the third through hole M3 coincide; the orthographic projection areas of the first through hole M1, the second through hole M2, and the third through hole M3 on the substrate 10 increase sequentially; the orthographic projection of the first through hole M1 on the substrate 10 is located within the orthographic projection area of ​​the second through hole M2 on the substrate 10, and the orthographic projection of the second through hole M2 on the substrate 10 is located within the orthographic projection area of ​​the third through hole M3 on the substrate 10.

[0198] In some embodiments, the orthographic projection areas of the first through hole M1, the second through hole M2, and the third through hole M3 on the substrate 10 decrease sequentially; the orthographic projection of the third through hole M3 on the substrate 10 is located within the orthographic projection area of ​​the second through hole M2 on the substrate 10, and the orthographic projection of the second through hole M2 on the substrate 10 is located within the orthographic projection area of ​​the first through hole M1 on the substrate 10.

[0199] The purpose of setting the through hole H1 is to ensure the light transmittance of subsequent processes and to ensure the stability of the light transmittance. For example, in the subsequent photocuring process of the adhesive layer, the curing light needs to pass through the through hole H1 to photocur the adhesive layer to be cured.

[0200] In some embodiments, the distance between the corresponding side edges of any two adjacent through holes M1, M2 and M3 is about 2.5 μm, which ensures that the distance requirement is greater than the process alignment accuracy.

[0201] In some embodiments, as shown in FIG9a, each bus block 140 is provided with two vias H1. The number of vias H1 on a bus block 140 can be adjusted according to the actual bus 14 wiring space and the resistance requirements of the bus 14.

[0202] In some embodiments, as shown in Figures 9a and 9b, the bus 14 further includes a bus trace 141, which is located on the same layer as the third pattern 1403 and is electrically connected to the third pattern 1403; each bus block 140 is electrically connected to a first trace 12; and / or, each bus block 140 is electrically connected to a second trace 13; and / or, each bus block 140 is electrically connected to a third trace 15.

[0203] In some embodiments, as shown in FIG10, the second region 202 includes two first sub-regions 202a and two second sub-regions 202b. The two first sub-regions 202a are arranged opposite to each other, and the two second sub-regions 202b are arranged opposite to each other. Multiple bus blocks 140 are distributed in each of the two first sub-regions 202a, and the multiple bus blocks 140 in the two first sub-regions 202a are arranged sequentially at intervals along the bus signal transmission direction P, and the bus signal transmission direction P in the two first sub-regions 202a is opposite. Multiple bus blocks 140 are distributed in each of the two second sub-regions 202b, and the multiple bus blocks 140 in the two second sub-regions 202b are arranged sequentially at intervals along the bus signal transmission direction P, and the bus signal transmission direction P in the two second sub-regions 202b is opposite. The bus signal transmission direction P in the first sub-regions 202a and the second sub-regions 202b forms an angle greater than 0°.

[0204] In this embodiment, the second region 202 surrounds the first region 201, that is, the first sub-region 202a and the second sub-region 202b are alternately distributed around the first region 201, thus surrounding the first region 201. The transmission direction P of the bus signal is the direction in which the first sub-region 202a and the second sub-region 202b are alternately distributed, that is, the bus signal is transmitted around the perimeter of the first region 201.

[0205] In some embodiments, as shown in FIG8b and FIG6a, the bus 14 further includes a transition block 142 located in the second region 202 and between adjacent first sub-regions 202a and second sub-regions 202b; the transition block 142 connects the bus block 140 in the first sub-region 202a and the bus block 140 in the second sub-region 202b; the transition block 142 includes a first portion 142a, which has the same structure as the bus block 140; the first portion 142a includes a plurality of via units 100, which are arranged sequentially at intervals along the arrangement direction of the plurality of bus blocks 140 in the first sub-region 202a, or the plurality of via units 100 are arranged sequentially at intervals along the arrangement direction of the plurality of bus blocks 140 in the second sub-region 202b.

[0206] The transition block 142 connects the bus blocks 140 in adjacent first sub-regions 202a and second sub-regions 202b to facilitate bus signal transmission. The arrangement of multiple via units 100 in the first part 142a of the transition block 142 ensures a more stable and reliable connection between the conductive film layers (such as the first pattern 1401, second pattern 1402, third pattern 1403, and fourth pattern 1404) in the bus block 140. It also reduces the resistance of the bus 14, thereby reducing signal loss during transmission. The arrangement of the multiple via units 100 in the first part 142a ensures a more uniform distribution of the via units 100 during fabrication, resulting in more uniform fabrication of the film layers within the second region 202.

[0207] In some embodiments, as shown in FIG8b and FIG6a, the photoelectric conversion substrate further includes an electrostatic discharge electrode 25 located in the second region 202 and on the same layer as the first conductive pattern 3; the transition block 142 further includes a second portion 142b, which is on the same layer as the first pattern 1401, the second pattern 1402 and / or the third pattern 1403, and a plurality of hollowed-out holes H2 are formed in the second portion 142b; the orthographic projections of the electrostatic discharge electrode 25 and the plurality of hollowed-out holes H2 on the substrate 10 at least partially overlap.

[0208] The electrostatic discharge electrode 25, such as an electrostatic ring, is used to carry and release electrostatic charges. Since there is an overlap between the electrostatic discharge electrode 25 and the second part 142b of the transition block 142, by making the electrostatic discharge electrode 25 overlap with the orthographic projections of the multiple hollow H2 holes on the substrate 10, the area of ​​the overlap region between the electrostatic discharge electrode 25 and the second part 142b of the transition block 142 can be reduced, thereby reducing the capacitance formed between them, and further reducing the interference of the capacitance on the signal on the electrostatic discharge electrode 25 and the bus signal on the second part 142b.

[0209] In some embodiments, as shown in Figures 9a and 8b, multiple scan lines 8 extend from the first region 201 to the first sub-region 202a, and multiple data lines 9 extend from the first region 201 to the second sub-region 202b. Within the first sub-region 202a, each scan line 8 is located between two adjacent bus blocks 140, and the bus blocks 140 and scan lines 8 are alternately distributed. Within the second sub-region 202b, each data line 9 is located between two adjacent bus blocks 140, and the bus blocks 140 and data lines 9 are alternately distributed. As shown in Figure 11, the ratio of the size W of the bus block 140 along the direction parallel to the bus signal transmission direction P to the first distance S is in the range of 60% to 70%. The size L of the bus block 140 along the direction perpendicular to the bus signal transmission direction P is 5 to 6 times the first distance S. The first distance S is the distance between the same edge of two adjacent photoelectric conversion elements 2 arranged along the direction of bus signal transmission P.

[0210] The dimensions W of the bus block 140 along the direction parallel to the bus signal transmission direction P and the dimensions L along the direction perpendicular to the bus signal transmission direction P are set to ensure that the spacing between the bus block 140 and the scan line 8 and the spacing between the bus block 140 and the data line 9 meet the requirements of the manufacturing process accuracy and safety distance. The dimension L of the bus block 140 along the direction perpendicular to the bus signal transmission direction P needs to be designed according to the wiring space in the second area 202 and the resistance requirements of the bus 14. The larger the dimension L of the bus block 140 along the direction perpendicular to the bus signal transmission direction P, the better.

[0211] In some embodiments, as shown in Figures 3b, 9b, and 9c, the second sublayer 162 covers the wall of the fifth via 105; the second sublayer 162 covers the wall of the second via 102 in the first sublayer 161; the second insulating layer 7 is made of an inorganic material; the second insulating layer 7 covers the wall of the first via 101 in the organic sublayer 62; and the second passivation layer 63 covers the wall of the eighth via 108 in the organic sublayer 62.

[0212] This design avoids the problem of metal film layer peeling off directly from the first sublayer 161 and organic sublayer 62 of the resin material due to the release of waste gas during subsequent processes.

[0213] The photoelectric conversion substrate provided in this embodiment, by making the signals applied to at least three conductive patterns and any two adjacent first electrodes different, and by ensuring that the orthographic projections of at least three conductive patterns and any two adjacent first electrodes on the substrate at least partially overlap, enables the formation of a capacitor between at least three conductive patterns and any two adjacent first electrodes. This adds at least three storage capacitors to the capacitance of the photoelectric conversion element itself. Compared to the capacitance of photodiodes in related technologies, the capacitance of the photoelectric conversion element in this embodiment is significantly increased on its own basis, thereby greatly improving the contrast of the image detected by the photoelectric conversion element. Consequently, the dynamic range of the photoelectric conversion substrate during use is greatly improved, significantly enhancing the detail rendering capability of the image acquired by the photoelectric conversion substrate.

[0214] Secondly, this disclosure also provides a flat panel detection device, which includes the photoelectric conversion substrate described in the above embodiments.

[0215] By employing the photoelectric conversion substrate in the above embodiments, the contrast of the images detected by the flat panel detection device is greatly improved, thereby significantly increasing the dynamic range of the flat panel detection device during use and greatly enhancing the ability of the flat panel detection device to present details of the images it acquires.

[0216] The flat panel detection device can be an X-ray flat panel detector.

[0217] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A photoelectric conversion substrate, comprising a first region, The photoelectric conversion substrate comprises a substrate, At least one pixel unit is located on one side of the substrate and in the first region; The pixel unit comprises a photoelectric conversion element, The photoelectric conversion element comprises a first electrode, a photoelectric conversion layer and a second electrode, which are stacked in sequence away from the substrate; wherein The pixel unit further comprises at least three conductive patterns located between the photoelectric conversion element and the substrate, which are stacked in sequence away from the substrate and insulated from each other, The signals of any two adjacent ones of the at least three conductive patterns and the first electrode are different; The orthographic projections of any two adjacent ones of the at least three conductive patterns and the first electrode on the substrate at least partially overlap.

2. The photoelectric conversion substrate according to claim 1, wherein The at least three conductive patterns comprise a first conductive pattern, a second conductive pattern and a third conductive pattern, The first conductive pattern, the second conductive pattern and the third conductive pattern are stacked in sequence away from the substrate; The orthographic projections of the first conductive pattern, the second conductive pattern and the third conductive pattern on the substrate are located within the orthographic projection area of the first electrode on the substrate.

3. The photoelectric conversion substrate according to claim 2, wherein The substrate comprises a base and a transistor located on the side of the base close to the photoelectric conversion element; The transistor comprises a gate, a gate insulating layer, an active layer, a first electrode and a second electrode stacked in sequence away from the base, The first conductive pattern is located in the same layer as the gate; The second conductive pattern is located in the same layer as the first electrode and the second electrode, and the second conductive pattern is connected to the first electrode as an integral structure; The gate insulating layer is further provided between the first conductive pattern and the second conductive pattern; The photoelectric conversion substrate further comprises a first insulating layer located between the second conductive pattern and the third conductive pattern, and a second insulating layer located between the third conductive pattern and the first electrode; It further comprises at least a first via hole opened in the second insulating layer and the first insulating layer, and the first electrode is electrically connected to the first electrode through the first via hole.

4. The photoelectric conversion substrate according to claim 3, wherein The orthographic projections of the second conductive pattern and the first electrode and the connection area of the two on the base at least partially overlap with the orthographic projection of the first conductive pattern on the base, The overlapping area of the orthographic projections of the second conductive pattern and the first electrode and the connection area of the two on the base with the orthographic projection of the first conductive pattern on the base does not overlap with the orthographic projection of the gate on the base.

5. The photoelectric conversion substrate according to claim 3, wherein It further comprises a plurality of scanning lines and a plurality of data lines, The number of pixel units is a plurality, and a plurality of pixel units are arranged in an array, The scanning lines are located between adjacent rows of the array, and the scanning lines extend in the row direction of the array; the data lines are located between adjacent columns of the array, and the data lines extend in the column direction of the array; The pixel units are located in the area surrounded by the scanning lines and the data lines, the scanning lines are located in the same layer as the first conductive pattern, and the data lines are located in the same layer as the second conductive pattern; A normal projection of the first conductive pattern on the substrate covers a normal projection on the substrate of an edge of the second conductive pattern adjacent to the data line; A normal projection of the second conductive pattern on the substrate covers a normal projection on the substrate of an edge of the first conductive pattern adjacent to the scan line.

6. The photoelectric conversion substrate according to claim 3, wherein A thickness of the second insulating layer is less than a thickness of the first insulating layer; A normal projection of the third conductive pattern on the substrate covers a normal projection on the substrate of the transistor, and a normal projection on the substrate of the third conductive pattern and the first via does not overlap.

7. The photoelectric conversion substrate according to claim 3, wherein A thickness of the second insulating layer is greater than a thickness of the first insulating layer; A normal projection on the substrate of the third conductive pattern does not overlap with normal projections on the substrate of the first via and the transistor.

8. The photoelectric conversion substrate according to claim 6 or 7, wherein A normal projection on the substrate of the photoelectric conversion layer and the second electrode is within a normal projection area on the substrate of the first electrode; A normal projection on the substrate of the first electrode covers normal projections on the substrate of the first via and the transistor; A normal projection on the substrate of the photoelectric conversion layer and the second electrode covers a normal projection on the substrate of the transistor; A normal projection on the substrate of the photoelectric conversion layer and the second electrode does not overlap with a normal projection on the substrate of the first via.

9. The photoelectric conversion substrate according to claim 5, wherein Further comprising a second region surrounding a periphery of the first region, the photoelectric conversion element being located in the first region; The photoelectric conversion substrate further comprises a first trace, a second trace, and a bus line, The first trace is in the same layer as the first conductive pattern and is electrically connected; The second trace is in the same layer as the third conductive pattern and is electrically connected; The bus line is located in the second region; The first trace and the second trace extend from the first region to the second region and are electrically connected to the bus line; The number of the first traces is multiple, and the number of the second traces is multiple; Each of the first traces extends along a row direction of the array and is electrically connected to the first conductive patterns in the same row; Each of the second traces extends along a column direction of the array and is electrically connected to the third conductive patterns in the same column; Alternatively, each of the second traces extends along a row direction of the array and is electrically connected to the third conductive patterns in the same row.

10. The photoelectric conversion substrate according to claim 9, wherein Further comprising a third trace and a third insulating layer, The third trace is located on a side of the second electrode facing away from the substrate; The third insulating layer is located between the second electrode and the third trace; The third trace is electrically connected to the second electrode through a second via formed in the third insulating layer; The third trace extends from the first region to the second region and is electrically connected to the bus line.

11. The photoelectric conversion substrate according to claim 10, wherein The number of the third traces is multiple; Each of the third traces extends along a column direction of the array and is electrically connected to the second electrodes of the photoelectric conversion elements in the same column; Alternatively, each of the third traces extends along a row direction of the array and is electrically connected to the second electrodes of the photoelectric conversion elements in the same row.

12. The photoelectric conversion substrate according to claim 11, wherein, The third trace and the transistor are at least partially overlapped in the orthographic projection on the substrate. Alternatively, the third trace and the transistor and the first via are at least partially overlapped in the orthographic projection on the substrate.

13. The photoelectric conversion substrate according to claim 11, wherein, The bus includes a plurality of bus blocks, The bus block includes a first pattern, a second pattern and a third pattern, The first pattern is located in the same layer as the third conductive pattern, and the first pattern is electrically connected with the second trace; The second pattern is located in the same layer as the first electrode; The third pattern is located in the same layer as the third trace, and the third pattern is electrically connected with the third trace; The first pattern, the second pattern and the third pattern are at least partially overlapped in the orthographic projection on the substrate; The second insulating layer is further arranged between the first pattern and the second pattern, and the second pattern is electrically connected with the first pattern through a third via arranged in the second insulating layer; The second pattern, the third pattern and the third insulating layer are sequentially stacked in the direction away from the substrate, and the third insulating layer includes a first sub-layer and a second sub-layer sequentially stacked away from the substrate, The third pattern is electrically connected with the second pattern through a fourth via arranged in the second sub-layer and a fifth via arranged in the first sub-layer; The area of the orthographic projection of the fifth via on the substrate is greater than the area of the orthographic projection of the third via on the substrate; The area of the orthographic projection of the fifth via on the substrate is greater than the area of the orthographic projection of the fourth via on the substrate; The orthographic projection of the third via and the fourth via on the substrate is located in the orthographic projection overlapping area of the fifth via and the eighth via on the substrate.

14. The photoelectric conversion substrate according to claim 13, wherein The bus block further includes a fourth pattern, The fourth pattern is located in the same layer as the first conductive pattern, and the fourth pattern is electrically connected with the first trace; The gate insulating layer and the first insulating layer are further arranged between the fourth pattern and the first pattern, the first insulating layer includes a third sub-layer and a fourth sub-layer, and the third sub-layer and the fourth sub-layer are stacked in the direction away from the substrate, The first pattern is electrically connected with the fourth pattern through a sixth via arranged in the gate insulating layer, a seventh via arranged in the fourth sub-layer and an eighth via arranged in the third sub-layer; The fifth via and the eighth via are at least partially overlapped in the orthographic projection on the substrate; The area of the orthographic projection of the eighth via on the substrate is greater than the area of the orthographic projection of the sixth via on the substrate; The area of the orthographic projection of the eighth via on the substrate is greater than the area of the orthographic projection of the seventh via on the substrate; The orthographic projection of the third via, the fourth via, the sixth via and the seventh via on the substrate is located in the orthographic projection overlapping area of the fifth via and the eighth via on the substrate.

15. The photoelectric conversion substrate according to claim 14, wherein, The fifth via hole and the third via hole and the fourth via hole located in the orthographic projection area of the fifth via hole on the substrate constitute a via hole unit, or the fifth via hole and the eighth via hole and the third via hole, the fourth via hole, the sixth via hole and the seventh via hole located in the overlapping area of the orthographic projection of the fifth via hole and the eighth via hole on the substrate constitute a via hole unit, Each of the bus blocks comprises a plurality of via hole units, and the plurality of via hole units are sequentially and spacedly distributed along the extension direction of the bus block.

16. The photoelectric conversion substrate according to claim 15, wherein A plurality of through holes are further formed in the bus block, The through holes are uniformly distributed in the interval area between any two adjacent via hole units; The through holes comprise first through holes formed in the first pattern, second through holes formed in the second pattern and third through holes formed in the third pattern; The centers of the first through holes, the second through holes and the third through holes coincide; The orthographic projection areas of the first through holes, the second through holes and the third through holes on the substrate sequentially increase; the orthographic projection of the first through hole on the substrate is located in the orthographic projection area of the second through hole on the substrate, and the orthographic projection of the second through hole on the substrate is located in the orthographic projection area of the third through hole on the substrate; Or, the orthographic projection areas of the first through holes, the second through holes and the third through holes on the substrate sequentially decrease; the orthographic projection of the third through hole on the substrate is located in the orthographic projection area of the second through hole on the substrate, and the orthographic projection of the second through hole on the substrate is located in the orthographic projection area of the first through hole on the substrate.

17. The photoelectric conversion substrate according to claim 14, wherein The bus further comprises bus wires, the bus wires are located in the same layer as the third pattern, and the bus wires are electrically connected with the third pattern; Each of the bus blocks is electrically connected with one of the first wires; And / or, each of the bus blocks is electrically connected with one of the second wires; And / or, each of the bus blocks is electrically connected with one of the third wires.

18. The photoelectric conversion substrate according to claim 17, wherein The second area comprises two first sub-areas and two second sub-areas, the two first sub-areas are oppositely arranged, and the two second sub-areas are oppositely arranged; A plurality of bus blocks are distributed in each of the two first sub-areas, and the plurality of bus blocks in the two first sub-areas are sequentially and spacedly arranged along the transmission direction of the bus signal, and the transmission directions of the bus signal in the two first sub-areas are opposite; A plurality of bus blocks are distributed in each of the two second sub-areas, and the plurality of bus blocks in the two second sub-areas are sequentially and spacedly arranged along the transmission direction of the bus signal, and the transmission directions of the bus signal in the two second sub-areas are opposite; The transmission directions of the bus signal in the first sub-area and the second sub-area form an included angle greater than 0°.

19. The photoelectric conversion substrate according to claim 18, wherein, The bus further comprises a transition block located in the second area and between adjacent first sub-areas and second sub-areas; The transition block connects the bus blocks in the first sub-area and the bus blocks in the second sub-area; The transition block comprises a first part, and the first part has the same structure as the bus block. The first portion comprises a plurality of the via units, which are arranged in sequence and at intervals along the arrangement direction of the plurality of bus blocks in the first sub-region, or which are arranged in sequence and at intervals along the arrangement direction of the plurality of bus blocks in the second sub-region.

20. The photoelectric conversion substrate according to claim 19, wherein, The electrostatic discharge electrode is further included and is located in the second region and is located in the same layer as the first conductive pattern; The transition block further comprises a second portion, which is located in the same layer as the first pattern, the second pattern and / or the third pattern, and a plurality of hollows are formed in the second portion; The electrostatic discharge electrode and the plurality of hollows at least partially overlap in the orthographic projection on the substrate.

21. The photoelectric conversion substrate according to claim 14, wherein The second sub-layer covers the hole wall of the fifth via; The second sub-layer covers the hole wall of the second via in the first sub-layer; The second insulating layer is made of inorganic material; The second insulating layer covers the hole wall of the first via in the third sub-layer; The fourth sub-layer covers the hole wall of the eighth via in the third sub-layer.

22. A flat panel detector device, wherein, The photoelectric conversion substrate of any one of claims 1-21.

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