Semiconductor memory device

Abstract

This semiconductor memory device comprises non-volatile memory cells (MC5, MC6) adjacent to each other in the X direction. The memory cell (MC5) includes a program transistor and a switch transistor provided between the program transistor and a bit line (21). The memory cell (MC6) includes a program transistor and a switch transistor provided between the program transistor and a bit line (22). The program transistors and switch transistors included in the memory cells (MC5, MC6) are nanosheet FETs. The bit lines (21, 22) are formed in the same wiring layer and are adjacent to each other without other signal wiring or power wiring therebetween.

Description

semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device including a nanosheet FET (Field Effect Transistor), and in particular to a layout structure of a nonvolatile memory cell using a nanosheet FET.

[0002] Semiconductor memory devices with nonvolatile memory cells are used in many applications. One type of nonvolatile memory cell is the OTP (One Time Programmable) memory cell, which is characterized by storing and reading out the states "1" and "0" in the memory by, for example, destroying an insulating film.

[0003] Furthermore, transistors, which are fundamental components of LSIs, have achieved increased integration density, reduced operating voltages, and improved operating speeds through the reduction of gate length (scaling). However, in recent years, excessive scaling has led to problems with off-state current and the resulting significant increase in power consumption. To solve this problem, active research has been conducted into three-dimensional transistors, which change the transistor structure from the conventional planar type to a three-dimensional type. One such transistor that has attracted attention is the nanosheet (nanowire) FET.

[0004] Patent Document 1 discloses a layout structure of an OTP memory using a fork sheet FET having a gate electrode in a fork shape.

[0005] JP 2023-119368 A

[0006] In the OTP memory described in Patent Document 1, the power supply wiring is provided in the same layer as the bit lines, so the wiring width of the bit lines cannot be increased. This increases the wiring resistance and reduces the operating speed. Furthermore, the wiring width of the power supply wiring cannot be increased. This increases the wiring resistance, which increases the power supply voltage drop when the OTP memory is used as a mask ROM, reducing the operating speed. Furthermore, the closer the distance between the bit lines and the power supply wiring, the larger the parasitic capacitance, reducing the operating speed.

[0007] The present disclosure provides a layout structure for an OTP memory that suppresses a decrease in operating speed without increasing the area.

[0008] In a first aspect of the present disclosure, a semiconductor memory device includes first and second nonvolatile memory cells adjacent to each other in a first direction, first and second word lines extending in the first direction, and first and second bit lines extending in a second direction perpendicular to the first direction, the first memory cell including a first program transistor having a gate connected to the first word line and a first switch transistor provided between the first program transistor and the first bit line and having a gate connected to the second word line, the second memory cell including a second program transistor having a gate connected to the first word line and a second switch transistor provided between the second program transistor and the second bit line and having a gate connected to the second word line, the first and second program transistors being nanosheet field effect transistors (FETs) having first and second nanosheets as channel regions, respectively. The first and second switch transistors are nanosheet FETs having third and fourth nanosheets as channel regions, respectively, and the first and second bit lines are formed in the same first wiring layer and are adjacent to each other without any other signal wiring or power supply wiring therebetween.

[0009] According to this aspect, the semiconductor memory device includes first and second nonvolatile memory cells adjacent in a first direction. The first memory cell includes a first program transistor having a gate connected to a first word line and a first switch transistor disposed between the first program transistor and a first bit line and having a gate connected to a second word line. The second memory cell includes a second program transistor having a gate connected to the first word line and a second switch transistor disposed between the second program transistor and a second bit line and having a gate connected to the second word line. The first and second program transistors and the first and second switch transistors are nanosheet FETs having nanosheets as channel regions. The first and second bit lines are formed in the same wiring layer and are adjacent to each other without other signal wiring or power wiring between them. This allows the wiring width of the bit lines to be increased, thereby reducing their wiring resistance and suppressing a decrease in operating speed. Furthermore, the parasitic capacitance of the bit lines can be reduced, thereby suppressing a decrease in operating speed.

[0010] According to the present disclosure, it is possible to provide a layout structure that can suppress a decrease in operating speed for an OTP memory using a nanosheet FET.

[0011] 7A and 7B are circuit diagrams of a memory cell according to a second embodiment, in which (a) is an OTP memory cell and (b) is a mask ROM cell;

[0012] Hereinafter, embodiments will be described with reference to the drawings.

[0013] In this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Furthermore, in this specification, expressions such as "same wiring width" that mean the same width, etc., are considered to include the range of manufacturing variations.

[0014] In this specification, the source and drain regions of a transistor are referred to as the "nodes" of the transistor, where appropriate. That is, one node of a transistor refers to the source or drain of the transistor, and both nodes of a transistor refer to the source and drain of the transistor.

[0015] First Embodiment FIGS. 1 and 2 are diagrams showing an example of the configuration of a semiconductor memory device including nonvolatile memory cells according to a first embodiment. FIG. 1 is a diagram showing the configuration of a memory cell array, and FIG. 2 is a circuit diagram of the memory cell. As shown in FIG. 1 , each memory cell 1 is connected to a corresponding first word line WLP (denoted as WLPi (i is an integer) as appropriate), second word line WLR (denoted as WLRi (i is an integer) as appropriate), and bit line BL (denoted as BLi (i is an integer) as appropriate). In addition to the memory cell array, the semiconductor memory device also includes peripheral circuits such as a write circuit and a read circuit, but these are not shown here. For simplicity of illustration, FIG. 1 shows the memory cell array as consisting of (4×2) memory cells 1 (MC1 to MC8). However, the number of memory cells 1 is not limited to this in the X direction (the direction in which the first and second word lines WLP and WLR extend in this embodiment) and the Y direction (the direction in which the bit line BL extends in this embodiment).

[0016] In this embodiment, the memory cell 1 is a gate oxide destruction type one-time programmable (OTP) memory cell. As shown in FIG. 2 , the memory cell 1 includes N-conductivity type transistors TP and TS connected in series. The transistor TP is a program element, and its gate is connected to a first word line WLP (program transistor). The program element stores a value of "1" or "0" depending on whether the gate oxide is destroyed or not. The transistor TS is a switch element, and its gate is connected to a second word line WLR (switch transistor). The switch element controls access to the program element from the bit line BL. Here, the switch element and program element are configured, for example, by transistors having a gate oxide thickness similar to that of so-called core transistors in the internal circuit of a semiconductor integrated circuit.

[0017] The write operation of a memory cell 1 is performed as follows: A high voltage VPP, which serves as the write voltage, is applied to the desired first word line WLP. The high voltage VPP is a voltage greater than the breakdown voltage of the gate oxide film of the program element, e.g., 3V. Then, a voltage VPR is applied to the second word line WLR. The voltage VPR is a voltage lower than the breakdown voltage of the gate oxide film of the switch element, and the voltage (VPP-VPR) is also lower than the breakdown voltage of the gate oxide film of the switch element, e.g., 1V. Then, 0V is applied to the bit line BL connected to the memory cell 1 whose gate oxide film is to be destroyed, and the voltage VPR is applied to the bit line BL connected to the memory cell 1 whose gate oxide film is not to be destroyed. As a result, the switch element of the memory cell 1 whose bit line BL is applied with 0V becomes conductive, and the gate oxide film of the program element is destroyed by the application of the high voltage VPP.

[0018] The read operation of the memory cell 1 is performed as follows. The bit line BL is precharged to, for example, 0 V. A voltage VRR lower than the high voltage VPP is applied to the desired first and second word lines WLP and WLR. The voltage VRR is a voltage that does not destroy the gate oxide film of the program element, for example, 1 V. If the gate oxide film of the program element is destroyed, current flows from the first word line WLP to the bit line BL via the gate of the program element, and the potential of the bit line BL rises. On the other hand, if the gate oxide film of the program element is not destroyed, the potential of the bit line BL does not change. This potential difference allows the state of the memory cell 1, i.e., the value "0" or "1," to be read.

[0019] 3 and 4 are diagrams showing an example of a layout structure of a memory cell according to the first embodiment, with Fig. 3 being a plan view of the memory cell array, and Figs. 4(a) and (b) being cross-sectional views showing the cross-sectional structure in the horizontal direction in a plan view of the memory cell array of Fig. 3. Fig. 4(a) is a cross-section taken along line X1-X1', and Fig. 4(b) is a cross-section taken along line X2-X2'.

[0020] 3 and other plan views, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction (corresponding to the depth direction). Note that the X direction is the direction in which the gate wiring and word lines extend, and the Y direction is the channel direction and the direction in which the bit lines extend.

[0021] FIG. 3 corresponds to a layout for (4×2) bits. Dashed lines indicate the frame of a memory cell for one bit. That is, FIG. 3 shows a configuration in which four memory cells are arranged in the X direction and two in the Y direction. In the Y direction, the memory cells are arranged inverted in the Y direction in every other column. In FIG. 3, the two memory cells from the left in the top row of the drawing correspond to memory cells MC1 and MC2 in the circuit diagram of FIG. 1, and the two memory cells from the left in the bottom row of the drawing correspond to memory cells MC5 and MC6 in the circuit diagram of FIG. 1. Below, the structure of the memory cells will be mainly explained using memory cells MC5 and MC6 as an example.

[0022] 3 and 4, power supply wirings 11, 12, 13, and 14 extending in the Y direction are formed in the BM0 wiring layer. The BM0 wiring layer is a wiring layer provided on the back side of the transistors in the semiconductor chip. The power supply wirings 11, 12, 13, and 14 supply VDD.

[0023] In the M1 wiring layer, bit lines 21, 22, 23, and 24 extending in the Y direction are formed. The M1 wiring layer is a wiring layer located above the transistors in the semiconductor chip, i.e., on the surface side of the transistors. The bit lines 21, 22, 23, and 24 correspond to bit lines BL0, BL1, BL2, and BL3, respectively.

[0024] Here, in a semiconductor chip, the back side of a transistor refers to the side opposite to the side on which local wiring, metal wiring, etc. connected to the transistor are stacked, and the side on which local wiring, metal wiring, etc. connected to the transistor are stacked is called the front side of the transistor.

[0025] An active region 31 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 11 and below the bit line 21. The active region 31 overlaps the power supply wiring 11 and the bit line 21 in a planar view. The active region 31 includes nanosheets 32a, 32b, 32c, and 32d that become the channel of the N-type nanosheet FET. The active region 31 also includes portions 33a, 33b, 33c, 33d, and 33e that become the source or drain of the N-type nanosheet FET.

[0026] In memory cell MC5, nanosheet 32a is the channel of transistor TP, nanosheet 32b is the channel of transistor TS, portion 33a is one node of transistor TP, portion 33b is a common node of transistors TP and TS, and portion 33c is the other node of transistor TS.

[0027] An active region 35 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 12 and below the bit line 22. The active region 35 overlaps the power supply wiring 12 and the bit line 22 in a planar view. The active region 35 includes nanosheets 36a, 36b, 36c, and 36d that become the channel of the N-type nanosheet FET. The active region 35 also includes portions 37a, 37b, 37c, 37d, and 37e that become the source or drain of the N-type nanosheet FET.

[0028] In memory cell MC6, nanosheet 36a is the channel of transistor TP, nanosheet 36b is the channel of transistor TS, portion 37a is one node of transistor TP, portion 37b is a common node of transistors TP and TS, and portion 37c is the other node of transistor TS.

[0029] Gate wirings 41, 42, 43, and 44 are formed extending in the X direction. The gate wiring 41 surrounds the outer peripheries in the X and Z directions of the nanosheet 32a of memory cell MC5 via a gate insulating film (not shown). The gate wiring 41 serves as the gate of the transistor TP of memory cell MC5. The gate wiring 42 surrounds the outer peripheries in the X and Z directions of the nanosheet 32b of memory cell MC5 via a gate insulating film (not shown). The gate wiring 42 serves as the gate of the transistor TS of memory cell MC5. The gate wiring 43 surrounds the outer peripheries in the X and Z directions of the nanosheet 36a of memory cell MC6 via a gate insulating film (not shown). The gate wiring 43 serves as the gate of the transistor TP of memory cell MC6. The gate wiring 44 surrounds the outer peripheries in the X and Z directions of the nanosheet 36b of memory cell MC6 via a gate insulating film (not shown). The gate wiring 44 serves as the gate of the transistor TS of memory cell MC6.

[0030] The gate wirings 41 and 43 are connected to other gate wirings aligned in a row in the X direction to form a word line WLP1 extending in the X direction. The gate wirings 41 and 43 are connected by a bridge portion 45 formed between the gate wirings 41 and 43. The gate wirings 42 and 44 are connected to other gate wirings aligned in a row in the X direction to form a word line WLR1 extending in the X direction. The gate wirings 42 and 44 are connected by a bridge portion 46 formed between the gate wirings 42 and 44. The bridge portions 45 and 46 are an example of a gate connecting portion. Similarly, the word lines WLP0 and WLR0 extending in the X direction are formed. The drains of the transistors TS adjacent in the Y direction are shared between the word lines WLR0 and WLR1.

[0031] Local interconnects 51a, 51b, 51c, 51d, and 51e are formed extending in the X direction. In FIG. 3 and other drawings, local interconnects are abbreviated as LI. The local interconnects 51a, 51b, 51c, 51d, and 51e are connected to portions 33a, 33b, 33c, 33d, and 33e in the active region 31, respectively. The local interconnect 51c is connected to the bit line 21 formed in the M1 wiring layer via a contact 61.

[0032] Local interconnections 52a, 52b, 52c, 52d, and 52e are formed extending in the X direction. The local interconnections 52a, 52b, 52c, 52d, and 52e are connected to portions 37a, 37b, 37c, 37d, and 37e, respectively, in the active region 35. The local interconnection 52c is connected via a contact 62 to the bit line 22 formed in the M1 interconnection layer.

[0033] The surface of nanosheet 32a facing nanosheet 36a in the X direction is not covered by gate wiring 41 and is exposed from gate wiring 41. The surface of nanosheet 32b facing nanosheet 36b in the X direction is not covered by gate wiring 42 and is exposed from gate wiring 42. Similarly, the surface of nanosheet 36a facing nanosheet 32a in the X direction is not covered by gate wiring 43 and is exposed from gate wiring 43. The surface of nanosheet 36b facing nanosheet 32b in the X direction is not covered by gate wiring 44 and is exposed from gate wiring 44. That is, memory cells MC5 and MC6 include fork-sheet FETs as transistors TP and TS.

[0034] This reduces the space required between the nanosheets 32a, 32b and the nanosheets 36a, 36b, and therefore the distance d1 between the nanosheets 32a, 32b and the nanosheets 36a, 36b can be reduced (d1<d2), thereby realizing a reduction in the area of ​​a semiconductor memory device having a fork-sheet FET.

[0035] 3 and 4, only bit lines 21, 22, 23, and 24 are formed in the M1 wiring layer, and no other signal wiring or power supply wiring is formed between the bit lines. This allows the wiring width of the bit lines 21, 22, 23, and 24 to be increased. Furthermore, the load capacitance of the bit lines 21, 22, 23, and 24 can be reduced. This allows the operating speed of the OTP memory to be improved.

[0036] As described above, according to this embodiment, the semiconductor memory device includes memory cells MC5 and MC6 adjacent to each other in the X direction. Memory cell MC5 includes nanosheet FETs with nanosheets 32a and 32b as channel regions for transistors TP and TS. Memory cell MC6 includes nanosheet FETs with nanosheets 36a and 36b as channel regions for transistors TP and TS. The bit lines 21 and 22 are formed in the same wiring layer and are adjacent to each other without other signal wiring or power wiring between them. This allows the wiring width of the bit lines 21 and 22 to be increased, thereby reducing their wiring resistance and suppressing a decrease in operating speed. Furthermore, the parasitic capacitance of the bit lines 21 and 22 can be reduced, thereby suppressing a decrease in operating speed.

[0037] Although the power supply wirings 11, 12, 13, and 14 are formed for each bit string, for example, the power supply wirings may be formed integrally for a plurality of bit strings.

[0038] (Conversion to Mask ROM) (First Example) The OTP memory cell described above can be easily converted to a mask ROM cell. FIG. 5 is a circuit diagram of a mask ROM cell converted from an OTP memory cell. In the OTP memory cell shown in FIG. 2, the stored value is determined by whether or not the gate oxide film of the transistor TP, which is the programming element, is destroyed. In contrast, in the mask ROM cell shown in FIG. 5, the stored value is determined by whether or not the source of the transistor TP is connected to the power supply VDD (point "D" in FIG. 5). The presence or absence of a connection is achieved, for example, by the presence or absence of a contact or via.

[0039] Data is read from the mask ROM cell shown in Figure 5 as follows: The bit line BL is precharged to a low level, and in this state, a high level is applied to both the word lines WLP and WLR. When the source of the transistor TP is connected to the power supply VDD, the bit line BL changes to a high level. On the other hand, when the source of the transistor TP is not connected to the power supply VDD, the bit line BL remains at a low level. The state of the mask ROM cell, i.e., the value "0" or "1", is read out depending on the potential difference of the bit line BL.

[0040] Fig. 6 is a plan view showing an example of the layout structure of a mask ROM cell converted from an OTP memory cell. The layout structure of Fig. 6 is basically the same as that of Fig. 3. In Fig. 6, contacts 63 and 64 determine the stored values ​​of mask ROM cells MC5 and MC6 depending on whether or not they are present. In each figure showing a mask ROM, the contacts that determine the stored values ​​are marked with the letter "D."

[0041] When contact 63 is formed, it connects portion 33a of active region 31 to power supply wiring 11 formed in the BM0 wiring layer. That is, whether or not contact 63 is present determines whether the source of transistor TP of mask ROM cell MC5 is connected to power supply VDD. When contact 64 is formed, it connects portion 37a of active region 35 to power supply wiring 12 formed in the BM0 wiring layer. That is, whether or not contact 64 is present determines whether or not the source of transistor TP of mask ROM cell MC6 is connected to power supply VDD.

[0042] 7 is a circuit diagram showing another example of a mask ROM cell converted from an OTP memory cell. In the mask ROM cell shown in Fig. 7, the memory value is determined by whether or not the node between the transistor TP and the transistor TS is connected to the power supply VDD.

[0043] FIG. 8 is a plan view showing an example of the layout structure of a mask ROM cell converted from an OTP memory cell. The layout structure of FIG. 8 is basically the same as that of FIG. 3. As shown in FIG. 8, contacts 65 and 66, which determine the storage values ​​of mask ROM cells MC5 and MC6, are formed in portions 33b and 37b of active region 31 and active region 35, respectively. That is, when contact 65 is formed, it connects the common node of transistors TP and TS in mask ROM cell MC5 to power supply wiring 11 formed in the BM0 wiring layer. When contact 66 is formed, it connects the common node of transistors TP and TS in mask ROM cell MC6 to power supply wiring 12 formed in the BM0 wiring layer.

[0044] 6 and 8, in the BM0 wiring layer, the power supply wiring 11, 12 is arranged so as to overlap with the nanosheet FET in a plan view. Therefore, the wiring width of the power supply wiring 11, 12 can be increased, and the wiring resistance is reduced, thereby improving the operating speed and stability of the mask ROM. In addition, an increase in the area of ​​the mask ROM can be suppressed.

[0045] Furthermore, in the manufacturing process of a semiconductor memory device, the formation of wiring in the back wiring layer is performed after the formation of wiring in the surface wiring layer. Therefore, in this embodiment, the contacts 63, 64, 65, and 66 for setting the memory value of the memory cell can be formed in a later process. This shortens the manufacturing time for changing the memory value of the memory cell.

[0046] That is, in the method for manufacturing a semiconductor memory device according to the present disclosure, for example, a step of forming word lines, bit lines, and a plurality of nanosheet FETs on a semiconductor substrate is performed, and after this step, contacts are formed on the back side of the plurality of nanosheet FETs to connect the sources of the nanosheet FETs to power wiring according to the data to be stored, and then power wiring is formed on the wiring layer on the back side.

[0047] 3, power supply wirings 11, 12, 13, and 14 for supplying VDD are provided to facilitate conversion to a mask ROM cell. However, if conversion to a mask ROM cell is not taken into consideration, the power supply wirings for supplying VDD may be omitted.

[0048] 9 is a plan view showing the layout structure of an OTP memory according to a modification of the first embodiment. This modification corresponds to the first embodiment in which the wiring layers of the bit lines and the VDD power supply wiring are interchanged. That is, in this modification, the bit lines are arranged in the BM0 wiring layer, and the VDD power supply wiring is arranged in the M1 wiring layer.

[0049] 9, bit lines 15, 16, 17, and 18 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 15, 16, 17, and 18 correspond to bit lines BL0, BL1, BL2, and BL3, respectively. Furthermore, power supply lines 25, 26, 27, and 28 extending in the Y direction are formed in the M1 wiring layer. The power supply lines 25, 26, 27, and 28 supply VDD.

[0050] The active region 31 overlaps with the bit line 15 and the power supply wiring 25 in a planar view. A portion 33c of the active region 31 is connected to the bit line 15 via a contact 71. The active region 35 overlaps with the bit line 16 and the power supply wiring 26 in a planar view. A portion 37c of the active region 35 is connected to the bit line 16 via a contact 72.

[0051] In the modified example of FIG. 9, only bit lines 15, 16, 17, and 18 are formed in the BM0 wiring layer, and no other signal wiring or power wiring is formed between the bit lines. Furthermore, the bit lines 15, 16, 17, and 18 are arranged overlapping the nanosheet FET in a planar view. Therefore, the wiring width of the bit lines 15, 16, 17, and 18 can be increased, thereby reducing their wiring resistance, thereby improving the operating speed and stability of the OTP memory. Furthermore, an increase in the area of ​​the OTP memory can be suppressed.

[0052] (Diversion to Mask ROM) The OTP memory cell according to the modified example can also be easily diverted to a mask ROM cell.

[0053] Fig. 10 is a plan view showing an example of the layout structure of a mask ROM cell converted from an OTP memory cell. The layout structure of Fig. 10 conforms to the circuit diagram of Fig. 5. The layout structure of Fig. 10 is basically the same as that of Fig. 9.

[0054] 10, the presence or absence of contacts 73 and 74 determines the storage values ​​of mask ROM cells MC5 and MC6. When formed, contact 73 connects local wiring 51a to power supply wiring 25 formed in the M1 wiring layer. That is, the presence or absence of contact 73 determines whether the source of transistor TP in mask ROM cell MC5 is connected to power supply VDD. When formed, contact 74 connects local wiring 52a to power supply wiring 26 formed in the M1 wiring layer. That is, the presence or absence of contact 74 determines whether the source of transistor TP in mask ROM cell MC6 is connected to power supply VDD.

[0055] 10, in the M1 wiring layer, the power supply wirings 25, 26, 27, and 28 are arranged so as to overlap with the nanosheet FET in a planar view. Therefore, the wiring width of the power supply wirings 25, 26, 27, and 28 can be increased, thereby reducing the wiring resistance, thereby improving the operating speed and stability of the mask ROM. In addition, an increase in the area of ​​the mask ROM can be suppressed.

[0056] Similarly, a layout structure according to the circuit diagram of FIG. 7 can be easily constructed from the layout structure of FIG.

[0057] 9, in order to facilitate conversion to a mask ROM cell, a power supply wiring for supplying VDD and local wiring connected to the nodes of the transistors TP and TS are provided. However, if conversion to a mask ROM cell is not taken into consideration, the power supply wiring for supplying VDD and the local wiring connected to the nodes of the transistors TP and TS may be omitted.

[0058] Second Embodiment FIG. 11 is a circuit diagram of a memory cell in a semiconductor memory device according to a second embodiment, where (a) is an OTP memory cell and (b) is a mask ROM cell converted from an OTP memory.

[0059] 11 , in this embodiment, the program element and the switch element are each composed of two transistors. That is, the program element includes N-conductivity type transistors TP1 and TP2, and the switch element includes N-conductivity type transistors TS1 and TS2. The gates of transistors TP1 and TP2 are connected to a first word line WLP, and the gates of transistors TS1 and TS2 are connected to a second word line WLR.

[0060] The program element having two transistors TP1 and TP2 offers the following advantages. Even if one of the transistors is not fully written, i.e., the gate oxide film is not fully destroyed, the other transistor can change the potential of the bit line BL, allowing the stored data to be read correctly. Furthermore, the drive capability of the transistors is greater than that of the first embodiment, allowing for faster read operations.

[0061] FIG. 12 is a plan view showing the layout structure of a memory cell according to this embodiment. The layout structure in FIG. 12 is basically the same as that in FIG. 3. However, two memory cells aligned in the Y direction in FIG. 3 are combined into a single memory cell. For example, memory cells MC1 and MC5 in FIG. 3 are combined into a single memory cell MC21 in FIG. 12, and memory cells MC2 and MC6 in FIG. 3 are combined into a single memory cell MC22 in FIG. 12. Furthermore, in FIG. 12, word lines WLP0 and WLP1 in FIG. 3 are combined into word line WLP0, which shares a common signal, and word lines WLR0 and WLR1 in FIG. 3 are combined into word line WLR0, which shares a common signal.

[0062] The following description of the memory cell structure will be made mainly using memory cells MC21 and MC22 as an example. Note that detailed description of configurations that can be easily inferred from the layout structure of FIG. 3 may be omitted.

[0063] 12, power supply wirings 111, 112, 113, and 114 extending in the Y direction are formed in the BM0 wiring layer. The power supply wirings 111, 112, 113, and 114 supply VDD. Bit lines 121, 122, 123, and 124 extending in the Y direction are formed in the M1 wiring layer. The bit lines 121, 122, 123, and 124 correspond to bit lines BL0, BL1, BL2, and BL3, respectively.

[0064] An active region 131 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 111 and below the bit line 121. The active region 131 overlaps the power supply wiring 111 and the bit line 121 in a planar view. The active region 131 includes nanosheets 132a, 132b, 132c, and 132d that become the channel of the N-type nanosheet FET. The active region 131 also includes portions 133a, 133b, 133c, 133d, and 133e that become the source or drain of the N-type nanosheet FET.

[0065] In memory cell MC21, nanosheet 132a is the channel of transistor TP1, nanosheet 132b is the channel of transistor TS1, nanosheet 132c is the channel of transistor TS2, and nanosheet 132d is the channel of transistor TP2. Furthermore, portion 133a is one node of transistor TP1, portion 133b is the common node of transistors TP1 and TS1, portion 133c is the common node of transistors TS1 and TS2, portion 133d is the common node of transistors TS2 and TP2, and portion 133e is the other node of transistor TS2.

[0066] An active region 135 constituting the channel, source, and drain of the N-type nanosheet FET is formed above the power supply wiring 112 and below the bit line 122. The active region 135 overlaps the power supply wiring 112 and the bit line 122 in a planar view. The active region 135 includes nanosheets 136a, 136b, 136c, and 136d that become the channel of the N-type nanosheet FET. The active region 135 also includes portions 137a, 137b, 137c, 137d, and 137e that become the source or drain of the N-type nanosheet FET.

[0067] In memory cell MC22, nanosheet 136a is the channel of transistor TP1, nanosheet 136b is the channel of transistor TS1, nanosheet 136c is the channel of transistor TS2, and nanosheet 136d is the channel of transistor TP2. Furthermore, portion 137a is one node of transistor TP1, portion 137b is the common node of transistors TP1 and TS1, portion 137c is the common node of transistors TS1 and TS2, portion 137d is the common node of transistors TS2 and TP2, and portion 137e is the other node of transistor TS2.

[0068] Local interconnections 151a, 151b, 151c, 151d, and 151e are formed extending in the X direction. The local interconnections 151a, 151b, 151c, 151d, and 151e are connected to portions 133a, 133b, 133c, 133d, and 133e, respectively, in the active region 131. The local interconnection 151c is connected via a contact 161 to a bit line 121 formed in the M1 interconnection layer.

[0069] Local interconnections 152a, 152b, 152c, 152d, and 152e are formed extending in the X direction. The local interconnections 152a, 152b, 152c, 152d, and 152e are connected to portions 137a, 137b, 137c, 137d, and 137e, respectively, in the active region 135. The local interconnection 152c is connected via a contact 162 to the bit line 122 formed in the M1 interconnection layer.

[0070] The memory cells MC21 and MC22 each include a fork-sheet FET as transistors TP1, TP2, TS1, and TS2. The surface of nanosheet 132a facing nanosheet 136a in the X direction is not covered by the gate wiring and is exposed from the gate wiring, while the surface of nanosheet 136a facing nanosheet 132a in the X direction is not covered by the gate wiring and is exposed from the gate wiring. Similarly, the surface of nanosheet 132b facing nanosheet 136b in the X direction is not covered by the gate wiring and is exposed from the gate wiring, while the surface of nanosheet 136b facing nanosheet 132b in the X direction is not covered by the gate wiring and is exposed from the gate wiring. The surface of nanosheet 132c facing nanosheet 136c in the X direction is not covered by the gate wiring and is exposed from the gate wiring, while the surface of nanosheet 136c facing nanosheet 132c in the X direction is not covered by the gate wiring and is exposed from the gate wiring. The surface of nanosheet 132d facing nanosheet 136d in the X direction is not covered by the gate wiring and is exposed from the gate wiring, and the surface of nanosheet 136d facing nanosheet 132d in the X direction is not covered by the gate wiring and is exposed from the gate wiring.

[0071] This reduces the space required between nanosheets 132a, 132b, 132c, and 132d and nanosheets 136a, 136b, 136c, and 136d, thereby reducing the distance between nanosheets 132a, 132b, 132c, and 132d and nanosheets 136a, 136b, 136c, and 136d, thereby realizing a reduction in the area of ​​a semiconductor memory device having a fork-sheet FET.

[0072] 12 has a programming element with two transistors TP1 and TP2, and a switching element with two transistors TS1 and TS2. This allows the signal on the bit line BL to be changed by the other transistor even if the programming, i.e., the gate oxide film, of one of the transistors TP1 and TP2 is not fully completed, thereby enabling the stored data to be read correctly. This also enables faster read operations.

[0073] 12, only bit lines 121, 122, 123, and 124 are formed in the M1 wiring layer, and no other signal wiring or power supply wiring is formed between the bit lines. This allows the wiring width of the bit lines 121, 122, 123, and 124 to be increased. Furthermore, the load capacitance of the bit lines 121, 122, 123, and 124 can be reduced. This allows the operating speed of the OTP memory to be improved.

[0074] As described above, according to this embodiment, the semiconductor memory device includes memory cells MC21 and MC22 adjacent to each other in the X direction. Memory cell MC21 includes nanosheet FETs having nanosheets 132a, 132b, 132c, and 132d as channel regions for transistors TP1, TS1, TS2, and TP2. Memory cell MC22 includes nanosheet FETs having nanosheets 136a, 136b, 136c, and 136d as channel regions for transistors TP1, TS1, TS2, and TP2. The bit lines 121 and 122 are formed in the same wiring layer and are adjacent to each other without other signal wiring or power wiring between them. This allows the wiring width of the bit lines 121 and 122 to be increased, thereby reducing their wiring resistance and suppressing a decrease in operating speed. Furthermore, the parasitic capacitance of the bit lines 121 and 122 can be reduced, thereby suppressing a decrease in operating speed.

[0075] Although the power supply wirings 111, 112, 113, and 114 are formed for each bit string, for example, the power supply wirings may be formed integrally for a plurality of bit strings.

[0076] (Conversion to Mask ROM) FIG. 13 is a plan view showing an example of the layout structure of a mask ROM cell converted from an OTP memory cell. The layout structure of FIG. 13 is basically the same as that of FIG. 12. In FIG. 13, the presence or absence of contacts 163 and 164 determines the stored value of memory cell MC21. When formed, contact 163 connects portion 133a, which becomes the node of transistor TP1, to power supply wiring 111 formed in the BM0 wiring layer. When formed, contact 164 connects portion 133e, which becomes the node of transistor TP2, to power supply wiring 111 formed in the BM0 wiring layer. In other words, the presence or absence of contacts 163 and 164 determines whether the sources of transistors TP1 and TP2 of memory cell MC21 are connected to the power supply VDD.

[0077] As in the second example of the first embodiment, contacts that determine the storage value of the memory cell MC21 may be formed at the positions of the portions 133b and 133d, i.e., in this case, when the contacts are formed, they connect the drains of the transistors TP1 and TP2 to the power supply VDD.

[0078] 12, power supply wirings 111, 112, 113, and 114 for supplying VDD are provided to facilitate conversion to a mask ROM cell. However, if conversion to a mask ROM cell is not taken into consideration, the power supply wirings for supplying VDD may be omitted.

[0079] 14 is a plan view showing the layout structure of an OTP memory according to a modification of the second embodiment. This modification corresponds to the second embodiment in which the wiring layers of the bit lines and the VDD power supply wiring are interchanged. That is, in this modification, the bit lines are arranged in the BM0 wiring layer, and the VDD power supply wiring is arranged in the M1 wiring layer.

[0080] 14, bit lines 115, 116, 117, and 118 extending in the Y direction are formed in the BM0 wiring layer. The bit lines 115, 116, 117, and 118 correspond to bit lines BL0, BL1, BL2, and BL3, respectively. Furthermore, power supply lines 125, 126, 127, and 128 extending in the Y direction are formed in the M1 wiring layer. The power supply lines 125, 126, 127, and 128 supply VDD.

[0081] The active region 131 overlaps with the bit line 115 and the power supply wiring 125 in a planar view. A portion 133c of the active region 131 is connected to the bit line 115 via a contact 171. The active region 135 overlaps with the bit line 116 and the power supply wiring 126 in a planar view. A portion 137c of the active region 135 is connected to the bit line 116 via a contact 172.

[0082] In the modified example of FIG. 14, only bit lines 115, 116, 117, and 118 are formed in the BM0 wiring layer, and no other signal wiring or power wiring is formed between the bit lines. Furthermore, the bit lines 115, 116, 117, and 118 are arranged overlapping the nanosheet FET in a planar view. Therefore, the wiring width of the bit lines 115, 116, 117, and 118 can be increased, thereby reducing their wiring resistance, thereby improving the operating speed and stability of the OTP memory. Furthermore, an increase in the area of ​​the OTP memory can be suppressed.

[0083] (Diversion to Mask ROM) The OTP memory cell according to the modified example can also be easily diverted to a mask ROM cell.

[0084] 15 is a plan view showing an example of the layout structure of a mask ROM cell converted from an OTP memory cell. The layout structure of FIG. 15 conforms to the circuit diagram of FIG. 11(b). The layout structure of FIG. 15 is basically the same as that of FIG. 14.

[0085] 15 , the presence or absence of contacts 173 and 174 determines the stored value of mask ROM cell MC21. When formed, contact 173 connects local interconnect 151a to power supply interconnect 125 formed in the M1 wiring layer. When formed, contact 174 connects local interconnect 151e to power supply interconnect 125 formed in the M1 wiring layer. In other words, the presence or absence of contacts 173 and 174 determines whether the sources of transistors TP1 and TP2 of mask ROM cell MC21 are connected to power supply VDD.

[0086] 15, in the M1 wiring layer, the power supply wiring 125, 126, 127, and 128 are arranged so as to overlap with the nanosheet FET in a planar view. Therefore, the wiring width of the power supply wiring 125, 126, 127, and 128 can be increased, thereby reducing the wiring resistance, thereby improving the operating speed and stability of the mask ROM. In addition, an increase in the area of ​​the mask ROM can be suppressed.

[0087] As in the second example of the first embodiment, contacts that determine the storage value of the memory cell MC21 may be formed at the positions of the local interconnects 151b and 151d. That is, in this case, when the contacts are formed, they connect the drains of the transistors TP1 and TP2 to the power supply VDD.

[0088] 14, in order to facilitate conversion to a mask ROM cell, a power supply wiring for supplying VDD and local wiring connected to the nodes of the transistors TP1, TP2, TS1, and TS2 are provided. However, if conversion to a mask ROM cell is not taken into consideration, the power supply wiring for supplying VDD and the local wiring connected to the nodes of the transistors TP1, TP2, TS1, and TS2 may be omitted.

[0089] In the above-described embodiments, the program transistor and switch transistor of the memory cell are fork-sheet FETs, but this is not limiting. That is, the program transistor and switch transistor of the memory cell may be any nanosheet FET having a nanosheet as a channel region.

[0090] Furthermore, in each of the above-described embodiments, each nanosheet is composed of a three-sheet structure, but this is not limited to this, and some or all of the nanosheets may have a one-sheet, two-sheet, or four or more-sheet structure.

[0091] In addition, in each of the above-described embodiments, the cross-sectional shape of the nanosheet is rectangular, but this is not limited to this and may be, for example, square, circular, elliptical, or the like.

[0092] The present disclosure makes it possible to realize a small-area layout structure for a semiconductor integrated circuit device having memory cells using nanosheet FETs, which is useful for improving the performance of semiconductor chips, for example.

[0093] 1 Memory cell 11, 12, 13, 14 Power supply wiring 15, 16, 17, 18 Bit line 21, 22, 23, 24 Bit line 25, 26, 27, 28 Power supply wiring 31, 35 Active area 32a, 32b, 32c, 32d, 36a, 36b, 36c, 36d Nanosheet 41, 42, 43, 44 Gate wiring 45, 46 Gate connection portion 111, 112, 113, 114 Power supply wiring 115, 116, 117, 118 Bit line 121, 122, 123, 124 Bit line 125, 126, 127, 128 Power supply wiring 131, 135 Active area 132a, 132b, 132c, 132d, 136a, 136b, 136c, 136d Nanosheet BLi (i is an integer) Bit line MCi (i is an integer) Memory cell TP, TP1, TP2 Program transistor TS, TS1, TS2 Switch transistor WLPi (i is an integer) Word line WLRi (i is an integer) Word line

Claims

1. A semiconductor memory device comprising: first and second nonvolatile memory cells adjacent to each other in a first direction; first and second word lines extending in the first direction; and first and second bit lines extending in a second direction perpendicular to the first direction; wherein the first memory cell comprises: a first program transistor having a gate connected to the first word line; and a first switch transistor provided between the first program transistor and the first bit line and having a gate connected to the second word line; the second memory cell comprises: a second program transistor having a gate connected to the first word line; and a second switch transistor provided between the second program transistor and the second bit line and having a gate connected to the second word line; the first and second program transistors are nanosheet field effect transistors (FETs) having first and second nanosheets as channel regions, respectively; and the first and second switch transistors are nanosheet FETs having third and fourth nanosheets as channel regions, respectively. The first and second bit lines are formed in the same first wiring layer and are adjacent to each other without any other signal wiring or power supply wiring therebetween.

2. A semiconductor memory device according to claim 1, wherein the first wiring layer is a wiring layer on the surface side of the first and second program transistors and the first and second switch transistors.

3. A semiconductor memory device according to claim 2, further comprising first and second power supply wirings extending in the second direction, the first and second power supply wirings being formed in a wiring layer on the backside of the first and second program transistors and the first and second switch transistors.

4. A semiconductor memory device according to claim 3, wherein the first power supply wiring overlaps the first and third nanosheets in a planar view, and the second power supply wiring overlaps the second and fourth nanosheets in a planar view.

5. A semiconductor memory device according to claim 1, wherein the first wiring layer is a wiring layer on the back side of the first and second program transistors and the first and second switch transistors.

6. A semiconductor memory device according to claim 5, wherein the first bit line overlaps the first and third nanosheets in a planar view, and the second bit line overlaps the second and fourth nanosheets in a planar view.

7. A semiconductor memory device according to claim 5, further comprising first and second power supply wirings extending in the second direction, the first and second power supply wirings being formed in a wiring layer on the surface side of the first and second program transistors and the first and second switch transistors.

8. A semiconductor memory device according to claim 1, wherein the first word line includes a first gate wiring surrounding the periphery of the first nanosheet in the first direction and a third direction perpendicular to the first and second directions, and a second gate wiring surrounding the periphery of the second nanosheet in the first and third directions; the second word line includes a third gate wiring surrounding the periphery of the third nanosheet in the first and third directions, and a fourth gate wiring surrounding the periphery of the fourth nanosheet in the first and third directions; the first and second nanosheets face each other in the first direction, and the surface of the first nanosheet facing the second nanosheet in the first direction is exposed from the first gate wiring, and the surface of the second nanosheet facing the first nanosheet in the first direction is exposed from the second gate wiring; The third and fourth nanosheets face each other in the first direction, and the surface of the third nanosheet facing the fourth nanosheet in the first direction is exposed from the third gate wiring, and the surface of the fourth nanosheet facing the third nanosheet in the first direction is exposed from the fourth gate wiring.

9. A semiconductor memory device according to claim 8, wherein the first word line is formed between the first gate wiring and the second gate wiring and has a first gate connection portion that connects the first gate wiring and the second gate wiring, and the second word line is formed between the third gate wiring and the fourth gate wiring and has a second gate connection portion that connects the third gate wiring and the fourth gate wiring.

10. A semiconductor memory device according to claim 1, comprising third and fourth word lines extending in the first direction, wherein the first memory cell comprises: a third program transistor having a gate connected to the fourth word line; and a third switch transistor provided between the third program transistor and the first bit line and having a gate connected to the third word line, wherein the third program transistor and the third switch transistor are nanosheet FETs having a nanosheet as a channel region, wherein a common first word line signal is applied to the first and fourth word lines, and a common second word line signal is applied to the second and third word lines.

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